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2020-09-28synopsys: Fix fifo allocation schemaJerzy Kasenberg
Recommended FIFO allocation schema includes 2 maximum endpoint sizes. Comment suggested that this is the case while it would work according to this description only in checked endpoints were ascending sizes. Also two same size endpoints would be counted as one. That is fixed by way sz is filled. Calculation used too much modulo operation while single division was enough to account for odd FIFO sizes. Extra space that is evenly distributed between Bulk and control endpoints was incorrectly calculated it could prevent allocation of ISO endpoint FIFO when bulk endpoints existed with smaller endpoint numbers. Minimum endpoint FIFO size is 16 32bit words, FIFO space requirement is now observed.
2020-09-06Start of sampling works.Reinhard Panhuber
2020-09-04Merge remote-tracking branch 'upstream/master' into uac2Reinhard Panhuber
2020-08-24Merge pull request #486 from kasjer/kasjer/add-endpoint-close-to-synopsysHa Thach
Add dcd_edpt_close() to synopsys
2020-08-22add OPT_MCU_SAMD11hathach
skip ci build for example that need more ROM/RAM could fit into SAMD11
2020-08-20Fix formatting, get rid of all tabs.Reinhard Panhuber
2020-08-19Commit before sharing.Reinhard Panhuber
Setup a test example - UNTESTED! Missing: Start transmitting audio data in set_interface.
2020-08-16Merge remote-tracking branch 'upstream/master' into uac2Reinhard Panhuber
Conflicts: src/device/usbd.c src/device/usbd.h src/portable/st/synopsys/dcd_synopsys.c
2020-08-16Add EP close. Fix bug in set_interface within audio.Reinhard Panhuber
2020-08-14Add dcd_edpt_close() to synopsysJerzy Kasenberg
Endpoint close was implemented only in one driver so far. This function is needed for interfaces with several alternate settings. The way FIFO is allocated in dcd_edpt_open() allows to correctly close only one IN endpoint (the one that was opened last).
2020-08-12Fix synopsys fifo flush during stallJerzy Kasenberg
Wrong FIFO was flushed in dcd_edpt_stall(). (epnum - 1) should only be used when accessing DIEPTXF registers. For DIEPCTL and GRSTCTL epnum is correct index.
2020-08-05Merge pull request #476 from kasjer/kasjer/fix-synopsys-fix-iso-frame-bitHa Thach
Fix synopsys odd/even frame bit for IN ISO endpoints
2020-08-04Fix synopsys odd/even frame bit for IN ISO endpointsJerzy Kasenberg
For ISO endpoint driver has to specify when data is to be transmitted (odd or even frame). Currently code was not updating this bit resulting in data being sent every other frame. If interval was 1ms full data packed was sent every 2ms, and ZLP was sent in between.
2020-08-04manually submit unplugged event for nrf dcd_disconnect()hathach
2020-08-04Merge pull request #478 from hathach/move-dcdconnect-to-dcdinitHa Thach
Move pull-up enabling to dcd_init() instead of usbd
2020-08-03Implement dynamic FIFO RAM allocation according to configuration desc.Reinhard Panhuber
2020-08-02Merge pull request #472 from hathach/fix-msp430-warningHa Thach
fix msp430 gcc 9.2.0 warning
2020-08-01enable pull-up in dcd_init() instead of usbdhathach
2020-08-01Merge pull request #477 from hathach/fix-nrf-unplugg-isr-eventHa Thach
correct isr context for nrf DCD_EVENT_UNPLUGGED
2020-08-01correct isr context for nrf DCD_EVENT_UNPLUGGEDhathach
also rename debug lookup to prevent conflict
2020-07-31Fix synopsys size check for ISO endpointJerzy Kasenberg
Constraint was incorrect for ISO endpoint as stated in TODO.
2020-07-29fix nested extern declaration of 'SystemCoreClock' [-Werror=nested-externs]hathach
2020-07-29fix strict prototypehathach
2020-07-28Merge pull request #454 from me-no-dev/esp32-s2-fifosHa Thach
ESP32-S2: Handle the fact that available EP IN FIFOs are less than the number of available EP INs
2020-07-28Update dcd_esp32s2.cme-no-dev
2020-07-28fix msp430 gcc 9.2.0 warning in #465hathach
2020-07-27Implement dynamic reallocation of RX and TX fifos for EP0.Reinhard Panhuber
Tested with EP0 size 8/16/32/64.
2020-07-26add 'set_EP0_max_pkt_size(...)' and fix EP0 size to 64 bytes after resetReinhard Panhuber
2020-07-23fix samd21 race condition with setup packethathach
reproduced with Adafruit_TinyUSB_ArduinoCore port commit 11d669b4d2a40eb2fc5e51b2a9707a6de9d42363 and SAMD BSP 1.6.1
2020-07-17update actual link speed for spresensehathach
2020-07-16update link speed detection for nuc505hathach
2020-07-16dcd tdi report link speed on resethathach
2020-07-10Merge pull request #456 from me-no-dev/esp32-s2-epin-toHa Thach
ESP32-S2: Detect EP IN Xfer Timeout
2020-07-08change REDUCE_SPEED=0/1 to explicitly SPEED=high/fullhathach
update readme, boards.md to add link to new stm boards
2020-07-05Merge pull request #457 from UweBonnes/add-stm-hsHa Thach
Add stm hs
2020-07-03STM32/OTG_HS: Allow OTG_HS port to run at FS speed.Uwe Bonnes
Add "REDUCE_SPEED=1" to the compile options.
2020-07-03update per reviewhathach
2020-07-03fix NVIC disable typohathach
2020-07-02ESP32-S2: Detect EP IN Xfer Timeoutme-no-dev
In some rare ocasions (bad cable, noise, etc.) data transfer might timeout and hang the endpoint, unless the interrupt flag is cleared. This pull request targets to solve that case.
2020-07-02correct HSE_VALUE in hal_confhathach
- although it is define in CFLAGS, it is worth to correct to be consistent with other build - extract set_speed()
2020-07-02change default port some stm bsphathach
- f769disco default port is highspeed port1 - remove PORT0 on stlink since the board only populated HS connector
2020-07-02clean uphathach
2020-07-01Merge branch 'add-stm-hs' of github.com:hathach/tinyusb into add-stm-hshathach
2020-07-01st/synopsys/dcd_synopsys.c: Remove USBC PHY PLL stabilization delay for nowUwe Bonnes
While the ST code has a 2 ms stabilization delay for the USBC PHY PLL, running without this delay showed no problem for at leat 10 USB un/replug cycles. Observe for problems!
2020-07-01only set turnaround in reset completehathach
2020-07-01correctly set turn around according to cpu clockhathach
help to run with low speed mcu
2020-07-01Merge branch 'master' into add-stm-hshathach
2020-07-01clean up codehathach
2020-07-01ESP32-S2: Handle the fact that available EP IN FIFOs are less than the ↵me-no-dev
number of available EP INs ESP32-S2 has only 5 available endpoint-in FIFOs (including EP0) but 7 available EP IN numbers. This change decouples the fifo number from the endpoint number, providing FIFO numbers until they reach the limit, at which point it will return false and assert an error that too many endpoints were allocated.
2020-06-30Clear ep0_pending if rx short packetJan Dümpelmann
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