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2024-10-29update handle in/out, separate allocated and xfer result to make it easier ↵hathach
to manage. Fix channel disable/deallocated.
2024-10-29split handle channel slave out/inhathach
2024-10-29minor clean uphathach
2024-10-29fix nptx fifo empty handlinghathach
2024-10-29restructure, add hcd endpoint, xfer to minimize footprint for managing xfer.hathach
2024-10-28minor renamehathach
2024-10-28implement hcd_edpt_abort_xfer, hcd_device_close,hathach
check request queue available before making usb attempt. Though there is no handling when queue is full. device_info example work well
2024-10-25got In transfer working, able to get 1st device descriptor and set addresshathach
2024-10-25hcd able to send setup packethathach
2024-10-25more progress on dwc2 hcd, initial code for edpt xferhathach
2024-10-21add tusb_time_millis(), able to reset and enable dwc2 port and get SOF activehathach
2024-10-21get hprt interrupt triggeredhathach
2024-10-17get hpri triggeredhathach
2024-10-16move gahbcfg/gintmsk with dma to dwc2 commonhathach
2024-10-15move core init code to dwc2 common. update/correct build for esppressifhathach
2024-10-15adding hcd dwc2hathach
2024-10-14change dcd_init() return from void to boolhathach
2024-10-14change the tusb_rhport_init_t struct, exclude the rhport to make API more ↵hathach
consistent
2024-10-11hcd_init() take init structhathach
2024-10-11fix fuzzing buildhathach
2024-10-11change dcd_init() to take rhport structhathach
2024-10-10remove debug codehathach
2024-10-10enhance dwc2hathach
2024-10-10add f407disco to hil poolhathach
2024-10-10improving dwc2, merging diep and doep if possiblehathach
2024-10-10add stm32f769disco to hil poolhathach
2024-10-10enhance dwc2 markdown with field mappinghathach
2024-10-07Merge pull request #2809 from shuffle2/masterHa Thach
make all python files executable and standardize interpreter
2024-10-04U0 does not have dwc2 controllerhathach
2024-10-02Merge branch 'master' into fork/Maerdl/masterhathach
2024-10-01support stm32U0 deviceHaefner, Martin
2024-09-30esp32p4 use port0 as fs, port1 as highspeedhathach
2024-09-30added p4, seems to work well and enumeratedhathach
2024-09-30update/rename ghwcfg registershathach
2024-09-30update to dwc2 register structhathach
2024-09-24more renamehathach
2024-09-24add CFG_TUD_DWC2_DMA, make it compile time optionhathach
2024-09-24update dfifo allocation scheme to use top pointer, update document and ↵hathach
explanation for EPInfo address and GDFIFO. some function rename update h743 linker to use SRAM1 since USB DMA cannot access DTCM ram update xmc4500 to use uuid for testing
2024-09-17make all python files executable and standardize interpreterShawn Hoffman
2024-09-08Merge branch 'master' into dwc2_dmaHiFiPhile
2024-09-04dwc2: for esp32 force disconnect/connect using USB_WRAP otg pad override ↵hathach
(DM=DP=0) in addition to dwc2's dctrl
2024-08-30Merge pull request #2731 from cumhuronat/masterHa Thach
Fix: Properly Handle NAK Response in MAX3421E driver
2024-08-30Merge pull request #2784 from tannewt/fix_esp32_sx_resumeHa Thach
Fix ESP32-SX resume
2024-08-29Fix ESP32-SX resumeScott Shawcroft
The interrupt handler pipes through the resume event but the interrupt wasn't enabled in the first place.
2024-08-29change order, fixes #2778Reinhard Griech
2024-08-26add sndfifo owner info to skip rewriting data for retrying NAKedhathach
2024-08-23only check SNDBAV IRQ if there is data to sendCumhur Onat
2024-08-23fix for out retry attempts with nak responseCumhur Onat
2024-08-19remove weak from dcd_edpt_close() for port without TUP_DCD_EDPT_ISO_ALLOChathach
2024-08-19add hwfifo_flush()hathach
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