summaryrefslogtreecommitdiff
path: root/src/portable
AgeCommit message (Collapse)Author
2023-05-19more dcache fixhathach
2023-05-19ehci fix dcache clean when control endpoint failedhathach
2023-05-19only clean/invalidate dcache on imxrt if memory is not in DTCMhathach
2023-05-18refactor ehci: add attached_buffer for dcache invalidate for IN transferhathach
2023-05-18refactor ehci, since usbh only queue 1 TD per queue headhathach
2023-05-18EHCI more improvementhathach
- more dcache clean/invalidate - extract init_periodic_list() - improve isr list handling
2023-05-18more cache, fix an similar issue with OHCI when removing an queue headhathach
2023-05-18use weak local for dcache function to skip if()hathach
2023-05-18EHCI adding dcahe support, passing enumertaionhathach
2023-05-17adding hcd_dcache_clean/hcd_dcache_invalidatehathach
2023-05-16fix error on EHCI causes xfer error in non-queued qhd which cause memory faulthathach
2023-05-16usbd: fix control transfer issue for chipidea hs when previous status and ↵hathach
new setup complete in the same isr frame change usbd edpt busy/stalled/claimed value to 0/1 instead of (true/false) since they are 1-bit field.
2023-05-16EHCI: fix xfer failed with disconnected device as stalledhathach
- change CFG_TUH_ENDPOINT_MAX to 16 (max endpoint pair per device) if not defined - change QHD_MAX for EHCI, should be user configurable and more optimized in the future
2023-05-16correct EHCI reporting failed xfer (instead of stalled) when device is unpluggedhathach
2023-05-10allow imxrt build with dual exmapleshathach
2023-05-09fix ehci issue with portsc when enable port power and port resethathach
fix attached device not regconized if attached before power on
2023-04-24Merge pull request #2013 from tannewt/imx_1042Ha Thach
Handle iMX RT 1042 usb naming
2023-04-20[rp2040] Make writes to SIE_CTRL aware of concurrent accessJacek Fedorynski
This commit makes it so that when setting the START_TRANS bit in the SIE_CTRL register, along with some other bits, we first set all the other bits, then wait some cycles, and then set the START_TRANS bit. Doing so protects against a situation where the USB controller is reading the register at the same time and gets an incorrect value. This mirrors the procedure already applied to buffer control registers.
2023-04-06Handle iMX RT 1042 usb namingScott Shawcroft
2023-04-03Add STM32L5 support - no OTG similar to some L4sJohn Cronin
2023-03-24separate CFG_TUSB_MEM_SECTION and CFG_TUSB_MEM_ALIGN tohathach
- CFG_TUD_MEM_SECTION and CFG_TUD_MEM_ALIGN - CFG_TUH_MEM_SECTION and CFG_TUH_MEM_ALIGN - fix missing mem section and align for host
2023-03-20more compatible with IARhathach
2023-03-18more update to kinetis bsphathach
2023-03-18merge kinetis into its own family in bsphathach
2023-03-18Add support for NXP FRDM_K32L2A4S eval board.Bob Paddock
2023-03-18more clean uphathach
2023-03-17Merge branch 'master' into portabilityhathach
2023-03-17fix trailing space and new linehathach
temporarily disable codespell
2023-03-16more fixhathach
2023-03-16rename symbolshathach
2023-03-16rename file link to rusb2hathach
2023-03-16Merge branch 'master' into renesas-rahathach
2023-03-15fix PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY not defined in old pico-sdkhathach
2023-03-14Merge pull request #1953 from tannewt/fix_cached_imx_resetHa Thach
Flush the dcd data on reset
2023-03-13Flush the dcd data on resetScott Shawcroft
2023-03-12minor formathathach
2023-03-11Merge pull request #1948 from dhalbert/remove-volatile-cast-includeHa Thach
rp2040: include hardware/sync.h explicitly
2023-03-11Merge branch 'master' into renesas-rahathach
2023-03-10rp2040: include hardware/sync.h explicitlyDan Halbert
2023-03-10dcd_nrf5x: ISO OUT handlingJerzy Kasenberg
For incoming ISO OUT packets it was possible to start DMA from endpoint to RAM before transfer was started resulting in unrelated memory corruption. This is scenario that causes memory corruption: - ISO OUT packet is received - Packet is transferred by DMA to transfer buffer - xfer->started is cleared and xfer->buffer is updated as it is in every case - Application takes to long to handle it (it happens when debugger is connected breakpoint is hit slowing down software). - Next ISO OUT packet arrives At this point there was no check if transfer was started and packet was copied by DMA to location beyond previous data, possibly overwriting unrelated memory. This solves the issue by checking that transfer was started and there is buffer ready for incoming packet.
2023-03-08fix incorrect merge of hcd linkhathach
2023-03-08fix freertos build with iar, format/indent link_typehathach
2023-03-08Merge branch 'master' into renesas-rahathach
2023-03-02rp2040: Fixup lib and example compile for LLVM Embedded Toolchain for ARMgraham sanderson
2023-03-01add TUP_USBIP_FSDEV and TUP_USBIP_FSDEV_STM32, clean up ifdef with stm32hathach
2023-02-28Merge pull request #1828 from HiFiPhile/stm32_fsdevHa Thach
stm32_fsdev & ISO EP buffer allocation improvements
2023-02-28rename ep_num to ep_idx, minor clean uphathach
2023-02-22comment out osal_task_delay if using os nonehathach
2023-02-22move and add optional tusb_app_virt_to_phys/tusb_app_phys_to_virthathach
also add place holder for tusb_app_dcache_flush() and tusb_app_dcache_invalidate()
2023-02-22rename OHCI_RHPORTS to TUP_OHCI_RHPORTShathach
generated by cgit v1.3.1 (git 2.54.0) at 2026-09-01 22:18:44 +0000