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Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>
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Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>
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core v3.10a (STM32L476)
DWC2 core rev 3.10a pushes an extra EP0 RX_COMPLETE (RXFLVL PKTSTS 0x3)
that is not a real OUT data completion, in two cases flagged on DOEPINT:
- STPKTRX (Setup Packet Received): between SETUP_RX and SETUP_DONE
- STSPHSRX (Status Phase Received, control write): after the OUT data
stage when the host starts the IN status phase
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To avoid STATUS IN completion of previous control transfer treated as next DATA IN when IRQ latency is high.
Signed-off-by: HiFiPhile <[email protected]>
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- GRXSTSP register has internal FIFO, receiving events won't mix up (STATUS OUT & next SETUP)
- Improve efficiency, remove 2nd IRQ overhead
Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Fix issue in the stall handling:
- dcd_edpt_stall() for an IN endpoint cleared EP_TX_LEN(0) instead of
EP_TX_LEN(ep_num), clobbering endpoint 0's transmit length register
when stalling any other IN endpoint.
Co-Authored-By: Claude Opus 4.7 (1M context) <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Refactor the driver to follow USBFS style for easier maintenance.
Replace the old packet/response helpers with explicit queue and update paths for IN and OUT transfers.
Introduce transfer validity tracking and per-endpoint data toggle state.
Reset toggle state on init, close-all, endpoint close, clear-stall, and bus reset.
Initialize endpoint controls consistently in NAK + TOG_0 mode.
Tighten EP0 setup/status handling and route transfer IRQ processing through the transfer-flag path.
Stop enabling ISO_ACT in INT_EN and clear unhandled interrupt flags explicitly.
Signed-off-by: HiFiPhile <[email protected]>
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It would casue race condition, SETUP packet is always acked.
Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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OUT is still buggy
Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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instead of DATA1
hcd_edpt_xfer() previously reset ep->next_pid to 1 only when the control
endpoint direction changed between stages. That handled IN-data control
transfers (e.g. GET_REPORT, GET_DESCRIPTOR) where SETUP is OUT and DATA is
IN, but not OUT-data class requests like SET_REPORT, where SETUP and DATA
are both OUT and the direction-change check is false. ep->next_pid was
left at 0 from hcd_edpt_open(), so the DATA stage went on the wire as
DATA0 when the device expected DATA1. Strict devices (observed: Elgato
Stream Deck) treat this as a protocol violation and disconnect.
Key off "endpoint 0" instead of "direction changed", restoring the
previous behavior. Interrupt/bulk endpoints take the ep->interrupt_num > 0
branch above and never reach this code, so they are unaffected.
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Signed-off-by: HiFiPhile <[email protected]>
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hcd/dwc2: fix txfifo full check
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Track when an EP0 OUT zero-length transfer is actually armed and require that state before synthesizing a status-stage completion ahead of a co-reported SETUP event.
This preserves the validated status-before-SETUP ordering fix while avoiding stale zero-length state from producing spurious EP0 OUT completions.
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On STM32 DWC2, SETUP phase done and EP0 OUT transfer complete can be
reported together. Processing SETUP first can overwrite control state
before the previous zero-length OUT status stage is acknowledged, which
causes DFU DNLOAD/GETSTATUS traffic to lose the status ACK and stall.
Queue the EP0 OUT zero-length transfer completion before queuing the
SETUP event when the endpoint has no pending OUT data and total_len is
zero. This keeps TinyUSB control-transfer ordering intact for the
combined interrupt case.
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USB_EVT_DETECTED runs hfclk_enable() which, when SoftDevice is not yet
enabled, starts HFXO via direct CLOCK register access. After
sd_softdevice_enable() takes over CLOCK, HFXO is physically off again
and SD's HFCLK reference count is 0.
If USB_EVT_READY is fired post-SD (e.g. on nRF52 via Bluefruit's
usb_softdevice_post_enable() when the pre-SD nrfx_power READY callback
didn't get to run before nrfx_power was uninited), the wait loop
'while (!hfclk_running()) {}' calls sd_clock_hfclk_is_running() which
returns false forever -> deadlock that blocks both USB enumeration and
any further app code on the calling thread.
Call hfclk_enable() right before the wait so HFCLK is requested in
whichever context (SD or direct) is current. hfclk_enable() is
idempotent.
Reproduces reliably with bleuart on Feather nRF52840 Express flashed
via JLink: chip wedges in sd_clock_hfclk_is_running SVC, no USB
enumeration, no BLE advertising. With the fix, USB enumerates and BLE
advertises as expected.
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Signed-off-by: HiFiPhile <[email protected]>
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EP_RX_CTRL state
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# Conflicts:
# src/common/tusb_types.h
# src/portable/mentor/musb/dcd_musb.c
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transition. handle status out to make sure xfer_complete() not called before dcd_edpt_xfer()
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hathach/copilot/extract-hcd-pma-buffer-errata-workaround
Refactor STM32 FSDEV PMA errata delay into shared static inline helper and apply to DCD/HCD with overridable timing
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Fix some -Wconversion warnings
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separate process_edpt_n() to process_epin() and process_epout()
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Fix musb RXRDY Clearing
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Resolves an issue in the musb handle_xfer_out function where not all
execution paths cleared the MUSB_RXCSRL1_RXRDY bit, causing the RX
interface to hang and no longer communicate with the host.
Signed-off-by: Brent Kowal <[email protected]>
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