| Age | Commit message (Collapse) | Author |
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Add support for stm32u5a5 (highspeed with built-in femtoPHY)
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get passed otg clock reset
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minor update for max3421
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to make sure it is valid
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UAC IN transfer improvements
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dwc2 core stuck at reset
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STM32U5 HS Support
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tested working with sam d21 and d51, not tested with nrf52, seem not
working with esp32
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revert change in hcd.h
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change tuh_int_handler() to take in_isr as optional parameter (default =
true)
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add -Wno-error=format for espressif
wrap up cdc_msc_hid_freertos
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Fix msd extraneus bytes on reading
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This fixes a problem found on MSD class where data read from from disks were sometimes partially overwritten by the status MSD message ("USBS...").
The function introduced wait for the hw fifo pipe to be empty, that prevent that new writing in the fife overwrite data which are not yet be transmitted by hw.
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- also add usbh_defer_func()
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hanged occasionally.
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CONDETIRQ occurs but we are disabled interrupt (for osal queue access).
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- xact_inout() to support send setup
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- hcd_int_disable/enable is software only to reduce interrupt lag
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- merge addr0 ep to pool
- add control status to xact in/out
- use atomic flag busy to ensure only 1 transfer is active at any time
- execute pending transfer after one is complete (or clear busy flag)
- change rtt mode to block if full
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