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Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>
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Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>
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core v3.10a (STM32L476)
DWC2 core rev 3.10a pushes an extra EP0 RX_COMPLETE (RXFLVL PKTSTS 0x3)
that is not a real OUT data completion, in two cases flagged on DOEPINT:
- STPKTRX (Setup Packet Received): between SETUP_RX and SETUP_DONE
- STSPHSRX (Status Phase Received, control write): after the OUT data
stage when the host starts the IN status phase
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Signed-off-by: HiFiPhile <[email protected]>
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Add control transfer fifo for host stack
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- src/tusb.c: extend tu_str_xfer_result[] with "ABORTED" and "INVALID"
to match the new enum size. Not reachable today (no HCD posts those
values through hcd_event_xfer_complete), but keeps the enum/table
invariant intact so future HCDs that surface ABORTED don't index OOB.
- examples/dual/dynamic_switch/src/main.c: apply the same while(1)
hoist already done for cdc_task / print_devinfo_task to
led_blinking_task. On OS_NONE the loop returned mid-iteration, which
on first call could fire multiple back-to-back toggles while
start_ms (initially 0) caught up to uptime.
Co-Authored-By: Claude Opus 4.7 <[email protected]>
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idx is used in the ENUM_SET_LINE_CONTROL path guarded by
CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, but was declared only under
CFG_TUH_CDC_LINE_CODING_ON_ENUM. Defining LINE_CONTROL_ON_ENUM without
LINE_CODING_ON_ENUM therefore failed to compile with an undeclared
identifier. Guard the declaration under either macro.
Signed-off-by: Andrew Leech <[email protected]>
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Fix premature MTP phase change after short MTP OUT transfer
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To avoid STATUS IN completion of previous control transfer treated as next DATA IN when IRQ latency is high.
Signed-off-by: HiFiPhile <[email protected]>
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Handle OUT transfer differently from IN to not prematurely change MTP phase when host sends short packet that is not end of MTP data phase. Only reaching container length or ZLP should change phase.
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- Added a pending FIFO queue for asynchronous control transfers when the active slot is busy.
- Introduced `control_xfer_dispatch_pending` to handle queued transfers on slot availability.
- Improved synchronization for blocking and non-blocking transfer modes, preventing deadlocks in RTOS.
- Refactored and renamed related functions for clarity and consistency.
- Enhanced error handling and callback invocation for failed or stale transfers.
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- GRXSTSP register has internal FIFO, receiving events won't mix up (STATUS OUT & next SETUP)
- Improve efficiency, remove 2nd IRQ overhead
Signed-off-by: HiFiPhile <[email protected]>
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checks
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Fix issue in the stall handling:
- dcd_edpt_stall() for an IN endpoint cleared EP_TX_LEN(0) instead of
EP_TX_LEN(ep_num), clobbering endpoint 0's transmit length register
when stalling any other IN endpoint.
Co-Authored-By: Claude Opus 4.7 (1M context) <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Co-authored-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Track EP0 control transfer state from SETUP (direction and wLength) and gate CH32 EP0 handshakes accordingly. Switch EP0 type away from control to bulk to block unsolicited OUT ACKs during control read/write gaps, then restore control type when EP0 transfer is explicitly armed.
Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Refactor the driver to follow USBFS style for easier maintenance.
Replace the old packet/response helpers with explicit queue and update paths for IN and OUT transfers.
Introduce transfer validity tracking and per-endpoint data toggle state.
Reset toggle state on init, close-all, endpoint close, clear-stall, and bus reset.
Initialize endpoint controls consistently in NAK + TOG_0 mode.
Tighten EP0 setup/status handling and route transfer IRQ processing through the transfer-flag path.
Stop enabling ISO_ACT in INT_EN and clear unhandled interrupt flags explicitly.
Signed-off-by: HiFiPhile <[email protected]>
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It would casue race condition, SETUP packet is always acked.
Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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OUT is still buggy
Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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Signed-off-by: HiFiPhile <[email protected]>
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feat: Add USB-MIDI 2.0 Device and Host class drivers
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packet api
Signed-off-by: HiFiPhile <[email protected]>
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Default RX/TX buffers to EPSIZE for both device and host. Document
drain-in-loop on ump_read; example device callback drains until
empty.
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Match midi2_host pattern. Literal 256 underran HS endpoints (512B).
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Lets each instance return different NUM_GROUPS, NUM_FUNCTION_BLOCKS,
EP_NAME and PRODUCT_ID. Defaults fall back to the macros.
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MT is in byte 3 of the UMP word in LE memory, not byte 0. Buffers
at mps blocked RX xfer re-arm on partial packets.
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Signed-off-by: HiFiPhile <[email protected]>
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