From 275e834bbed4928094b0a631c7dd36fdcc0b40fe Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Dec 2013 13:40:31 +0700 Subject: add device_os_none keil project for all boards --- demos/bsp/boards/microbuilder/board_rf1ghznode.h | 4 +- .../lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_gpio.c | 819 ++++++ .../lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_gpio.h | 64 + .../lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_uart.c | 238 ++ .../lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_uart.h | 55 + demos/bsp/lpc11uxx/gpio.c | 819 ------ demos/bsp/lpc11uxx/gpio.h | 64 - demos/bsp/lpc11uxx/uart.c | 238 -- demos/bsp/lpc11uxx/uart.h | 55 - .../bsp/lpc175x_6x/startup_keil/startup_LPC17xx.s | 287 ++ demos/device/device_os_none/.cproject | 103 +- demos/device/device_os_none/.project | 9 +- demos/device/device_os_none/device_os_none.uvproj | 2883 +++++++++++++++++++- demos/device/device_os_none/makefile | 100 - demos/device/src/mscd_app.c | 8 +- demos/device/src/tusb_config.h | 16 +- demos/device/src/tusb_descriptors.h | 2 +- demos/host/host_freertos/.cproject | 195 +- demos/host/host_os_none/.cproject | 3 - tinyusb/common/common.h | 10 +- tinyusb/common/compiler/compiler_gcc.h | 55 +- tinyusb/common/compiler/compiler_iar.h | 1 + 22 files changed, 4568 insertions(+), 1460 deletions(-) create mode 100644 demos/bsp/lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_gpio.c create mode 100644 demos/bsp/lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_gpio.h create mode 100644 demos/bsp/lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_uart.c create mode 100644 demos/bsp/lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_uart.h delete mode 100644 demos/bsp/lpc11uxx/gpio.c delete mode 100644 demos/bsp/lpc11uxx/gpio.h delete mode 100644 demos/bsp/lpc11uxx/uart.c delete mode 100644 demos/bsp/lpc11uxx/uart.h create mode 100644 demos/bsp/lpc175x_6x/startup_keil/startup_LPC17xx.s delete mode 100644 demos/device/device_os_none/makefile diff --git a/demos/bsp/boards/microbuilder/board_rf1ghznode.h b/demos/bsp/boards/microbuilder/board_rf1ghznode.h index 565983d86..2ebd4c293 100644 --- a/demos/bsp/boards/microbuilder/board_rf1ghznode.h +++ b/demos/bsp/boards/microbuilder/board_rf1ghznode.h @@ -57,8 +57,8 @@ #endif #include "LPC11Uxx.h" -#include "lpc11uxx/gpio.h" -#include "lpc11uxx/uart.h" +#include "lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_gpio.h" +#include "lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_uart.h" #define CFG_PRINTF_TARGET PRINTF_TARGET_SEMIHOST diff --git a/demos/bsp/lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_gpio.c b/demos/bsp/lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_gpio.c new file mode 100644 index 000000000..f07af3785 --- /dev/null +++ b/demos/bsp/lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_gpio.c @@ -0,0 +1,819 @@ +/**************************************************************************** + * $Id:: gpio.c 6172 2011-01-13 18:22:51Z usb00423 $ + * Project: NXP LPC11Uxx GPIO example + * + * Description: + * This file contains GPIO code example which include GPIO + * initialization, GPIO interrupt handler, and related APIs for + * GPIO access. + * + **************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. +****************************************************************************/ +#include "LPC11Uxx.h" /* LPC11Uxx Peripheral Registers */ +#include "lpc11uxx_gpio.h" + +volatile uint32_t flex_int0_counter = 0; +volatile uint32_t flex_int1_counter = 0; +volatile uint32_t flex_int2_counter = 0; +volatile uint32_t flex_int3_counter = 0; +volatile uint32_t flex_int4_counter = 0; +volatile uint32_t flex_int5_counter = 0; +volatile uint32_t flex_int6_counter = 0; +volatile uint32_t flex_int7_counter = 0; +volatile uint32_t gint0_counter = 0; +volatile uint32_t gint1_counter = 0; +volatile uint32_t flex_int0_level_counter = 0; +volatile uint32_t flex_int0_rising_edge_counter = 0; +volatile uint32_t flex_int0_falling_edge_counter = 0; +volatile uint32_t flex_int1_level_counter = 0; +volatile uint32_t flex_int1_rising_edge_counter = 0; +volatile uint32_t flex_int1_falling_edge_counter = 0; +volatile uint32_t flex_int2_level_counter = 0; +volatile uint32_t flex_int2_rising_edge_counter = 0; +volatile uint32_t flex_int2_falling_edge_counter = 0; +volatile uint32_t flex_int3_level_counter = 0; +volatile uint32_t flex_int3_rising_edge_counter = 0; +volatile uint32_t flex_int3_falling_edge_counter = 0; +volatile uint32_t flex_int4_level_counter = 0; +volatile uint32_t flex_int4_rising_edge_counter = 0; +volatile uint32_t flex_int4_falling_edge_counter = 0; +volatile uint32_t flex_int5_level_counter = 0; +volatile uint32_t flex_int5_rising_edge_counter = 0; +volatile uint32_t flex_int5_falling_edge_counter = 0; +volatile uint32_t flex_int6_level_counter = 0; +volatile uint32_t flex_int6_rising_edge_counter = 0; +volatile uint32_t flex_int6_falling_edge_counter = 0; +volatile uint32_t flex_int7_level_counter = 0; +volatile uint32_t flex_int7_rising_edge_counter = 0; +volatile uint32_t flex_int7_falling_edge_counter = 0; +volatile uint32_t gint0_level_counter = 0; +volatile uint32_t gint0_edge_counter = 0; +volatile uint32_t gint1_level_counter = 0; +volatile uint32_t gint1_edge_counter = 0; + +/***************************************************************************** +** Function name: FLEX_INT0_IRQHandler +** +** Descriptions: Use one GPIO pin as interrupt source +** +** parameters: None +** +** Returned value: None +** +*****************************************************************************/ +void FLEX_INT0_IRQHandler(void) +{ + flex_int0_counter++; + if ( LPC_GPIO_PIN_INT->IST & (0x1<<0) ) + { + if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<0) ) + { + flex_int0_level_counter++; + } + else + { + if ( LPC_GPIO_PIN_INT->RISE & (0x1<<0) ) + { + flex_int0_rising_edge_counter++; + LPC_GPIO_PIN_INT->RISE = 0x1<<0; + } + else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<0) ) + { + flex_int0_falling_edge_counter++; + LPC_GPIO_PIN_INT->FALL = 0x1<<0; + } + LPC_GPIO_PIN_INT->IST = 0x1<<0; + } + } + return; +} + +/***************************************************************************** +** Function name: FLEX_INT1_IRQHandler +** +** Descriptions: Use one GPIO pin as interrupt source +** +** parameters: None +** +** Returned value: None +** +*****************************************************************************/ +void FLEX_INT1_IRQHandler(void) +{ + flex_int1_counter++; + if ( LPC_GPIO_PIN_INT->IST & (0x1<<1) ) + { + if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<1) ) + { + flex_int1_level_counter++; + } + else + { + if ( LPC_GPIO_PIN_INT->RISE & (0x1<<1) ) + { + flex_int1_rising_edge_counter++; + LPC_GPIO_PIN_INT->RISE = 0x1<<1; + } + else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<1) ) + { + flex_int1_falling_edge_counter++; + LPC_GPIO_PIN_INT->FALL = 0x1<<1; + } + LPC_GPIO_PIN_INT->IST = 0x1<<1; + } + } + return; +} + +/***************************************************************************** +** Function name: FLEX_INT2_IRQHandler +** +** Descriptions: Use one GPIO pin as interrupt source +** +** parameters: None +** +** Returned value: None +** +*****************************************************************************/ +void FLEX_INT2_IRQHandler(void) +{ + flex_int2_counter++; + if ( LPC_GPIO_PIN_INT->IST & (0x1<<2) ) + { + if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<2) ) + { + flex_int2_level_counter++; + } + else + { + if ( LPC_GPIO_PIN_INT->RISE & (0x1<<2) ) + { + flex_int2_rising_edge_counter++; + LPC_GPIO_PIN_INT->RISE = 0x1<<2; + } + else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<2) ) + { + flex_int2_falling_edge_counter++; + LPC_GPIO_PIN_INT->FALL = 0x1<<2; + } + LPC_GPIO_PIN_INT->IST = 0x1<<2; + } + } + return; +} + +/***************************************************************************** +** Function name: FLEX_INT3_IRQHandler +** +** Descriptions: Use one GPIO pin as interrupt source +** +** parameters: None +** +** Returned value: None +** +*****************************************************************************/ +void FLEX_INT3_IRQHandler(void) +{ + flex_int3_counter++; + if ( LPC_GPIO_PIN_INT->IST & (0x1<<3) ) + { + if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<3) ) + { + flex_int3_level_counter++; + } + else + { + if ( LPC_GPIO_PIN_INT->RISE & (0x1<<3) ) + { + flex_int3_rising_edge_counter++; + LPC_GPIO_PIN_INT->RISE = 0x1<<3; + } + else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<3) ) + { + flex_int3_falling_edge_counter++; + LPC_GPIO_PIN_INT->FALL = 0x1<<3; + } + LPC_GPIO_PIN_INT->IST = 0x1<<3; + } + } + return; +} + +/***************************************************************************** +** Function name: FLEX_INT4_IRQHandler +** +** Descriptions: Use one GPIO pin as interrupt source +** +** parameters: None +** +** Returned value: None +** +*****************************************************************************/ +void FLEX_INT4_IRQHandler(void) +{ + flex_int4_counter++; + if ( LPC_GPIO_PIN_INT->IST & (0x1<<4) ) + { + if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<4) ) + { + flex_int4_level_counter++; + } + else + { + if ( LPC_GPIO_PIN_INT->RISE & (0x1<<4) ) + { + flex_int4_rising_edge_counter++; + LPC_GPIO_PIN_INT->RISE = 0x1<<4; + } + else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<4) ) + { + flex_int4_falling_edge_counter++; + LPC_GPIO_PIN_INT->FALL = 0x1<<4; + } + LPC_GPIO_PIN_INT->IST = 0x1<<4; + } + } + return; +} + +/***************************************************************************** +** Function name: FLEX_INT5_IRQHandler +** +** Descriptions: Use one GPIO pin as interrupt source +** +** parameters: None +** +** Returned value: None +** +*****************************************************************************/ +void FLEX_INT5_IRQHandler(void) +{ + flex_int5_counter++; + if ( LPC_GPIO_PIN_INT->IST & (0x1<<5) ) + { + if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<5) ) + { + flex_int5_level_counter++; + } + else + { + if ( LPC_GPIO_PIN_INT->RISE & (0x1<<5) ) + { + flex_int5_rising_edge_counter++; + LPC_GPIO_PIN_INT->RISE = 0x1<<5; + } + else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<5) ) + { + flex_int5_falling_edge_counter++; + LPC_GPIO_PIN_INT->FALL = 0x1<<5; + } + LPC_GPIO_PIN_INT->IST = 0x1<<5; + } + } + return; +} + +/***************************************************************************** +** Function name: FLEX_INT6_IRQHandler +** +** Descriptions: Use one GPIO pin as interrupt source +** +** parameters: None +** +** Returned value: None +** +*****************************************************************************/ +void FLEX_INT6_IRQHandler(void) +{ + flex_int6_counter++; + if ( LPC_GPIO_PIN_INT->IST & (0x1<<6) ) + { + if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<6) ) + { + flex_int6_level_counter++; + } + else + { + if ( LPC_GPIO_PIN_INT->RISE & (0x1<<6) ) + { + flex_int6_rising_edge_counter++; + LPC_GPIO_PIN_INT->RISE = 0x1<<6; + } + else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<6) ) + { + flex_int6_falling_edge_counter++; + LPC_GPIO_PIN_INT->FALL = 0x1<<6; + } + LPC_GPIO_PIN_INT->IST = 0x1<<6; + } + } + return; +} + +/***************************************************************************** +** Function name: FLEX_INT7_IRQHandler +** +** Descriptions: Use one GPIO pin as interrupt source +** +** parameters: None +** +** Returned value: None +** +*****************************************************************************/ +void FLEX_INT7_IRQHandler(void) +{ + flex_int7_counter++; + if ( LPC_GPIO_PIN_INT->IST & (0x1<<7) ) + { + if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<7) ) + { + flex_int7_level_counter++; + } + else + { + if ( LPC_GPIO_PIN_INT->RISE & (0x1<<7) ) + { + flex_int7_rising_edge_counter++; + LPC_GPIO_PIN_INT->RISE = 0x1<<7; + } + else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<7) ) + { + flex_int7_falling_edge_counter++; + LPC_GPIO_PIN_INT->FALL = 0x1<<7; + } + LPC_GPIO_PIN_INT->IST = 0x1<<7; + } + } + return; +} + +/***************************************************************************** +** Function name: GINT0_IRQHandler +** +** Descriptions: Use one GPIO pin as interrupt source +** +** parameters: None +** +** Returned value: None +** +*****************************************************************************/ +void GINT0_IRQHandler(void) +{ + gint0_counter++; + if ( LPC_GPIO_GROUP_INT0->CTRL & 0x1 ) + { + if ( LPC_GPIO_GROUP_INT0->CTRL & (0x1<<4) ) + { + gint0_level_counter++; + } + else + { + gint0_edge_counter++; + } + LPC_GPIO_GROUP_INT0->CTRL |= 0x1; + } + return; +} + +/***************************************************************************** +** Function name: GINT1_IRQHandler +** +** Descriptions: Use one GPIO pin as interrupt source +** +** parameters: None +** +** Returned value: None +** +*****************************************************************************/ +void GINT1_IRQHandler(void) +{ + gint1_counter++; + if ( LPC_GPIO_GROUP_INT1->CTRL & 0x1 ) + { + if ( LPC_GPIO_GROUP_INT1->CTRL & (0x1<<4) ) + { + gint1_level_counter++; + } + else + { + gint1_edge_counter++; + } + LPC_GPIO_GROUP_INT1->CTRL |= 0x1; + } + return; +} + +/***************************************************************************** +** Function name: GPIOInit +** +** Descriptions: Initialize GPIO, install the +** GPIO interrupt handler +** +** parameters: None +** +** Returned value: true or false, return false if the VIC table +** is full and GPIO interrupt handler can be +** installed. +** +*****************************************************************************/ +void GPIOInit( void ) +{ + /* Enable AHB clock to the GPIO domain. */ + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6); + + /* Enable AHB clock to the FlexInt, GroupedInt domain. */ + LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24)); + + return; +} + +/***************************************************************************** +** Function name: GPIOSetFlexInterrupt +** +** Descriptions: Set interrupt sense, event, etc. +** sense: edge or level, 0 is edge, 1 is level +** event/polarity: 0 is active low/falling, 1 is high/rising. +** +** parameters: channel #, port #, bit position, sense, event(polarity) +** +** Returned value: None +** +*****************************************************************************/ +void GPIOSetFlexInterrupt( uint32_t channelNum, uint32_t portNum, uint32_t bitPosi, + uint32_t sense, uint32_t event ) +{ + switch ( channelNum ) + { + case CHANNEL0: + if ( portNum ) + { + LPC_SYSCON->PINTSEL[0] = bitPosi + 24; + } + else + { + LPC_SYSCON->PINTSEL[0] = bitPosi; + } + NVIC_EnableIRQ(FLEX_INT0_IRQn); + break; + case CHANNEL1: + if ( portNum ) + { + LPC_SYSCON->PINTSEL[1] = bitPosi + 24; + } + else + { + LPC_SYSCON->PINTSEL[1] = bitPosi; + } + NVIC_EnableIRQ(FLEX_INT1_IRQn); + break; + case CHANNEL2: + if ( portNum ) + { + LPC_SYSCON->PINTSEL[2] = bitPosi + 24; + } + else + { + LPC_SYSCON->PINTSEL[2] = bitPosi; + } + NVIC_EnableIRQ(FLEX_INT2_IRQn); + break; + case CHANNEL3: + if ( portNum ) + { + LPC_SYSCON->PINTSEL[3] = bitPosi + 24; + } + else + { + LPC_SYSCON->PINTSEL[3] = bitPosi; + } + NVIC_EnableIRQ(FLEX_INT3_IRQn); + break; + case CHANNEL4: + if ( portNum ) + { + LPC_SYSCON->PINTSEL[4] = bitPosi + 24; + } + else + { + LPC_SYSCON->PINTSEL[4] = bitPosi; + } + NVIC_EnableIRQ(FLEX_INT4_IRQn); + break; + case CHANNEL5: + if ( portNum ) + { + LPC_SYSCON->PINTSEL[5] = bitPosi + 24; + } + else + { + LPC_SYSCON->PINTSEL[5] = bitPosi; + } + NVIC_EnableIRQ(FLEX_INT5_IRQn); + break; + case CHANNEL6: + if ( portNum ) + { + LPC_SYSCON->PINTSEL[6] = bitPosi + 24; + } + else + { + LPC_SYSCON->PINTSEL[6] = bitPosi; + } + NVIC_EnableIRQ(FLEX_INT6_IRQn); + break; + case CHANNEL7: + if ( portNum ) + { + LPC_SYSCON->PINTSEL[7] = bitPosi + 24; + } + else + { + LPC_SYSCON->PINTSEL[7] = bitPosi; + } + NVIC_EnableIRQ(FLEX_INT7_IRQn); + break; + default: + break; + } + if ( sense == 0 ) + { + LPC_GPIO_PIN_INT->ISEL &= ~(0x1<IENF |= (0x1<IENR |= (0x1<ISEL |= (0x1<IENR |= (0x1<IENF &= ~(0x1<IENF |= (0x1<ISEL & (0x1<SIENF |= (0x1<SIENR |= (0x1<SIENR |= (0x1<ISEL & (0x1<CIENF |= (0x1<CIENR |= (0x1<CIENR |= (0x1<IST & (0x1<ISEL & (0x1<IST = (1<CTRL &= ~(0x1<<2); /* Edge trigger */ + } + else + { + LPC_GPIO_GROUP_INT0->CTRL |= (0x1<<2); /* Level trigger. */ + } + LPC_GPIO_GROUP_INT0->CTRL |= (logic<<1); + LPC_GPIO_GROUP_INT0->PORT_POL[0] = *((uint32_t *)(eventPattern + 0)); + LPC_GPIO_GROUP_INT0->PORT_POL[1] = *((uint32_t *)(eventPattern + 1)); + LPC_GPIO_GROUP_INT0->PORT_ENA[0] = *((uint32_t *)(bitPattern + 0)); + LPC_GPIO_GROUP_INT0->PORT_ENA[1] = *((uint32_t *)(bitPattern + 1)); + /* as soon as enabled, an edge may be generated */ + /* clear interrupt flag and NVIC pending interrupt to */ + /* workaround the potential edge generated as enabled */ + LPC_GPIO_GROUP_INT0->CTRL |= (1<<0); + NVIC_ClearPendingIRQ(GINT0_IRQn); + NVIC_EnableIRQ(GINT0_IRQn); + break; + case GROUP1: + if ( sense == 0 ) + { + LPC_GPIO_GROUP_INT1->CTRL &= ~(0x1<<2); /* Edge trigger */ + } + else + { + LPC_GPIO_GROUP_INT1->CTRL |= (0x1<<2); /* Level trigger. */ + } + LPC_GPIO_GROUP_INT1->CTRL |= (logic<<1); + LPC_GPIO_GROUP_INT1->PORT_POL[0] = *((uint32_t *)(eventPattern + 0)); + LPC_GPIO_GROUP_INT1->PORT_POL[1] = *((uint32_t *)(eventPattern + 1)); + LPC_GPIO_GROUP_INT1->PORT_ENA[0] = *((uint32_t *)(bitPattern + 0)); + LPC_GPIO_GROUP_INT1->PORT_ENA[1] = *((uint32_t *)(bitPattern + 1)); + /* as soon as enabled, an edge may be generated */ + /* clear interrupt flag and NVIC pending interrupt to */ + /* workaround the potential edge generated as enabled */ + LPC_GPIO_GROUP_INT1->CTRL |= (1<<0); + NVIC_ClearPendingIRQ(GINT1_IRQn); + NVIC_EnableIRQ(GINT1_IRQn); + break; + default: + break; + } + + return; +} + +/***************************************************************************** +** Function name: GPIOGetPinValue +** +** Descriptions: Read Current state of port pin, PIN register value +** +** parameters: port num, bit position +** Returned value: None +** +*****************************************************************************/ +uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi ) +{ + uint32_t regVal = 0; + + if( bitPosi < 0x20 ) + { + if ( LPC_GPIO->PIN[portNum] & (0x1<PIN[portNum]; + } + return ( regVal ); +} + +/***************************************************************************** +** Function name: GPIOSetBitValue +** +** Descriptions: Set/clear a bit in a specific position +** +** parameters: port num, bit position, bit value +** +** Returned value: None +** +*****************************************************************************/ +void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal ) +{ + if ( bitVal ) + { + LPC_GPIO->SET[portNum] = 1<CLR[portNum] = 1<DIR[portNum] |= (1<DIR[portNum] &= ~(1< +#include "LPC11Uxx.h" +#include "lpc11uxx_uart.h" + +volatile uint32_t UARTStatus; +volatile uint8_t UARTTxEmpty = 1; +volatile uint8_t UARTBuffer[BUFSIZE]; +volatile uint32_t UARTCount = 0; + +/***************************************************************************** +** Function name: UART_IRQHandler +** +** Descriptions: UART interrupt handler +** +** parameters: None +** Returned value: None +** +*****************************************************************************/ +void UART_IRQHandler(void) +{ + uint8_t IIRValue, LSRValue; + uint8_t Dummy = Dummy; + + IIRValue = LPC_USART->IIR; + + IIRValue >>= 1; /* skip pending bit in IIR */ + IIRValue &= 0x07; /* check bit 1~3, interrupt identification */ + if (IIRValue == IIR_RLS) /* Receive Line Status */ + { + LSRValue = LPC_USART->LSR; + /* Receive Line Status */ + if (LSRValue & (LSR_OE | LSR_PE | LSR_FE | LSR_RXFE | LSR_BI)) + { + /* There are errors or break interrupt */ + /* Read LSR will clear the interrupt */ + UARTStatus = LSRValue; + Dummy = LPC_USART->RBR; /* Dummy read on RX to clear + interrupt, then bail out */ + return; + } + if (LSRValue & LSR_RDR) /* Receive Data Ready */ + { + /* If no error on RLS, normal ready, save into the data buffer. */ + /* Note: read RBR will clear the interrupt */ + UARTBuffer[UARTCount++] = LPC_USART->RBR; + if (UARTCount == BUFSIZE) + { + UARTCount = 0; /* buffer overflow */ + } + } + } + else if (IIRValue == IIR_RDA) /* Receive Data Available */ + { + /* Receive Data Available */ + UARTBuffer[UARTCount++] = LPC_USART->RBR; + if (UARTCount == BUFSIZE) + { + UARTCount = 0; /* buffer overflow */ + } + } + else if (IIRValue == IIR_CTI) /* Character timeout indicator */ + { + /* Character Time-out indicator */ + UARTStatus |= 0x100; /* Bit 9 as the CTI error */ + } + else if (IIRValue == IIR_THRE) /* THRE, transmit holding register empty */ + { + /* THRE interrupt */ + LSRValue = LPC_USART->LSR; /* Check status in the LSR to see if + valid data in U0THR or not */ + if (LSRValue & LSR_THRE) + { + UARTTxEmpty = 1; + } + else + { + UARTTxEmpty = 0; + } + } + return; +} + +#if MODEM_TEST +/***************************************************************************** +** Function name: ModemInit +** +** Descriptions: Initialize UART0 port as modem, setup pin select. +** +** parameters: None +** Returned value: None +** +*****************************************************************************/ +void ModemInit( void ) +{ + LPC_IOCON->PIO2_0 &= ~0x07; /* UART I/O config */ + LPC_IOCON->PIO2_0 |= 0x01; /* UART DTR */ + LPC_IOCON->PIO0_7 &= ~0x07; /* UART I/O config */ + LPC_IOCON->PIO0_7 |= 0x01; /* UART CTS */ + LPC_IOCON->PIO1_5 &= ~0x07; /* UART I/O config */ + LPC_IOCON->PIO1_5 |= 0x01; /* UART RTS */ +#if 1 + LPC_IOCON->DSR_LOC = 0; + LPC_IOCON->PIO2_1 &= ~0x07; /* UART I/O config */ + LPC_IOCON->PIO2_1 |= 0x01; /* UART DSR */ + + LPC_IOCON->DCD_LOC = 0; + LPC_IOCON->PIO2_2 &= ~0x07; /* UART I/O config */ + LPC_IOCON->PIO2_2 |= 0x01; /* UART DCD */ + + LPC_IOCON->RI_LOC = 0; + LPC_IOCON->PIO2_3 &= ~0x07; /* UART I/O config */ + LPC_IOCON->PIO2_3 |= 0x01; /* UART RI */ + +#else + LPC_IOCON->DSR_LOC = 1; + LPC_IOCON->PIO3_1 &= ~0x07; /* UART I/O config */ + LPC_IOCON->PIO3_1 |= 0x01; /* UART DSR */ + + LPC_IOCON->DCD_LOC = 1; + LPC_IOCON->PIO3_2 &= ~0x07; /* UART I/O config */ + LPC_IOCON->PIO3_2 |= 0x01; /* UART DCD */ + + LPC_IOCON->RI_LOC = 1; + LPC_IOCON->PIO3_3 &= ~0x07; /* UART I/O config */ + LPC_IOCON->PIO3_3 |= 0x01; /* UART RI */ +#endif + LPC_USART->MCR = 0xC0; /* Enable Auto RTS and Auto CTS. */ + return; +} +#endif + +/***************************************************************************** +** Function name: UARTInit +** +** Descriptions: Initialize UART0 port, setup pin select, +** clock, parity, stop bits, FIFO, etc. +** +** parameters: UART baudrate +** Returned value: None +** +*****************************************************************************/ +void UARTInit(uint32_t baudrate) +{ + uint32_t Fdiv; + uint32_t regVal; + + UARTTxEmpty = 1; + UARTCount = 0; + + NVIC_DisableIRQ(UART_IRQn); + + LPC_IOCON->PIO0_18 &= ~0x07; /* UART I/O config */ + LPC_IOCON->PIO0_18 |= 0x01; /* UART RXD */ + LPC_IOCON->PIO0_19 &= ~0x07; + LPC_IOCON->PIO0_19 |= 0x01; /* UART TXD */ + /* Enable UART clock */ + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12); + LPC_SYSCON->UARTCLKDIV = 0x1; /* divided by 1 */ + + LPC_USART->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */ + regVal = LPC_SYSCON->UARTCLKDIV; + + Fdiv = (((SystemCoreClock*LPC_SYSCON->SYSAHBCLKDIV)/regVal)/16)/baudrate ; /*baud rate */ + + LPC_USART->DLM = Fdiv / 256; + LPC_USART->DLL = Fdiv % 256; + LPC_USART->LCR = 0x03; /* DLAB = 0 */ + LPC_USART->FCR = 0x07; /* Enable and reset TX and RX FIFO. */ + + /* Read to clear the line status. */ + regVal = LPC_USART->LSR; + + /* Ensure a clean start, no data in either TX or RX FIFO. */ +// CodeRed - added parentheses around comparison in operand of & + while (( LPC_USART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) ); + while ( LPC_USART->LSR & LSR_RDR ) + { + regVal = LPC_USART->RBR; /* Dump data from RX FIFO */ + } + + /* Enable the UART Interrupt */ + NVIC_EnableIRQ(UART_IRQn); + +#if CONFIG_UART_ENABLE_INTERRUPT==1 +#if CONFIG_UART_ENABLE_TX_INTERRUPT==1 + LPC_USART->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */ +#else + LPC_USART->IER = IER_RBR | IER_RLS; /* Enable UART interrupt */ +#endif +#endif + return; +} + +/***************************************************************************** +** Function name: UARTSend +** +** Descriptions: Send a block of data to the UART 0 port based +** on the data length +** +** parameters: buffer pointer, and data length +** Returned value: None +** +*****************************************************************************/ +void UARTSend(uint8_t *BufferPtr, uint32_t Length) +{ + + while ( Length != 0 ) + { + /* THRE status, contain valid data */ +#if CONFIG_UART_ENABLE_TX_INTERRUPT==1 + /* Below flag is set inside the interrupt handler when THRE occurs. */ + while ( !(UARTTxEmpty & 0x01) ); + LPC_USART->THR = *BufferPtr; + UARTTxEmpty = 0; /* not empty in the THR until it shifts out */ +#else + while ( !(LPC_USART->LSR & LSR_THRE) ); + LPC_USART->THR = *BufferPtr; +#endif + BufferPtr++; + Length--; + } + return; +} + +/****************************************************************************** +** End Of File +******************************************************************************/ diff --git a/demos/bsp/lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_uart.h b/demos/bsp/lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_uart.h new file mode 100644 index 000000000..9f00ab8af --- /dev/null +++ b/demos/bsp/lpc11uxx/LPC11Uxx_DriverLib/lpc11uxx_uart.h @@ -0,0 +1,55 @@ +/***************************************************************************** + * uart.h: Header file for NXP LPC1xxx Family Microprocessors + * + * Copyright(C) 2008, NXP Semiconductor + * All rights reserved. + * + * History + * 2009.12.07 ver 1.00 Preliminary version, first Release + * +******************************************************************************/ +#ifndef __UART_H +#define __UART_H + +#define RS485_ENABLED 0 +#define TX_INTERRUPT 0 /* 0 if TX uses polling, 1 interrupt driven. */ +#define MODEM_TEST 0 + +#define IER_RBR 0x01 +#define IER_THRE 0x02 +#define IER_RLS 0x04 + +#define IIR_PEND 0x01 +#define IIR_RLS 0x03 +#define IIR_RDA 0x02 +#define IIR_CTI 0x06 +#define IIR_THRE 0x01 + +#define LSR_RDR 0x01 +#define LSR_OE 0x02 +#define LSR_PE 0x04 +#define LSR_FE 0x08 +#define LSR_BI 0x10 +#define LSR_THRE 0x20 +#define LSR_TEMT 0x40 +#define LSR_RXFE 0x80 + +#define BUFSIZE 0x40 + +/* RS485 mode definition. */ +#define RS485_NMMEN (0x1<<0) +#define RS485_RXDIS (0x1<<1) +#define RS485_AADEN (0x1<<2) +#define RS485_SEL (0x1<<3) +#define RS485_DCTRL (0x1<<4) +#define RS485_OINV (0x1<<5) + +void ModemInit( void ); +void UARTInit(uint32_t Baudrate); +void UART_IRQHandler(void); +void UARTSend(uint8_t *BufferPtr, uint32_t Length); + +#endif /* end __UART_H */ +/***************************************************************************** +** End Of File +******************************************************************************/ diff --git a/demos/bsp/lpc11uxx/gpio.c b/demos/bsp/lpc11uxx/gpio.c deleted file mode 100644 index a113b2cb7..000000000 --- a/demos/bsp/lpc11uxx/gpio.c +++ /dev/null @@ -1,819 +0,0 @@ -/**************************************************************************** - * $Id:: gpio.c 6172 2011-01-13 18:22:51Z usb00423 $ - * Project: NXP LPC11Uxx GPIO example - * - * Description: - * This file contains GPIO code example which include GPIO - * initialization, GPIO interrupt handler, and related APIs for - * GPIO access. - * - **************************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * NXP Semiconductors assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. NXP Semiconductors - * reserves the right to make changes in the software without - * notification. NXP Semiconductors also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. -****************************************************************************/ -#include "LPC11Uxx.h" /* LPC11Uxx Peripheral Registers */ -#include "gpio.h" - -volatile uint32_t flex_int0_counter = 0; -volatile uint32_t flex_int1_counter = 0; -volatile uint32_t flex_int2_counter = 0; -volatile uint32_t flex_int3_counter = 0; -volatile uint32_t flex_int4_counter = 0; -volatile uint32_t flex_int5_counter = 0; -volatile uint32_t flex_int6_counter = 0; -volatile uint32_t flex_int7_counter = 0; -volatile uint32_t gint0_counter = 0; -volatile uint32_t gint1_counter = 0; -volatile uint32_t flex_int0_level_counter = 0; -volatile uint32_t flex_int0_rising_edge_counter = 0; -volatile uint32_t flex_int0_falling_edge_counter = 0; -volatile uint32_t flex_int1_level_counter = 0; -volatile uint32_t flex_int1_rising_edge_counter = 0; -volatile uint32_t flex_int1_falling_edge_counter = 0; -volatile uint32_t flex_int2_level_counter = 0; -volatile uint32_t flex_int2_rising_edge_counter = 0; -volatile uint32_t flex_int2_falling_edge_counter = 0; -volatile uint32_t flex_int3_level_counter = 0; -volatile uint32_t flex_int3_rising_edge_counter = 0; -volatile uint32_t flex_int3_falling_edge_counter = 0; -volatile uint32_t flex_int4_level_counter = 0; -volatile uint32_t flex_int4_rising_edge_counter = 0; -volatile uint32_t flex_int4_falling_edge_counter = 0; -volatile uint32_t flex_int5_level_counter = 0; -volatile uint32_t flex_int5_rising_edge_counter = 0; -volatile uint32_t flex_int5_falling_edge_counter = 0; -volatile uint32_t flex_int6_level_counter = 0; -volatile uint32_t flex_int6_rising_edge_counter = 0; -volatile uint32_t flex_int6_falling_edge_counter = 0; -volatile uint32_t flex_int7_level_counter = 0; -volatile uint32_t flex_int7_rising_edge_counter = 0; -volatile uint32_t flex_int7_falling_edge_counter = 0; -volatile uint32_t gint0_level_counter = 0; -volatile uint32_t gint0_edge_counter = 0; -volatile uint32_t gint1_level_counter = 0; -volatile uint32_t gint1_edge_counter = 0; - -/***************************************************************************** -** Function name: FLEX_INT0_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void FLEX_INT0_IRQHandler(void) -{ - flex_int0_counter++; - if ( LPC_GPIO_PIN_INT->IST & (0x1<<0) ) - { - if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<0) ) - { - flex_int0_level_counter++; - } - else - { - if ( LPC_GPIO_PIN_INT->RISE & (0x1<<0) ) - { - flex_int0_rising_edge_counter++; - LPC_GPIO_PIN_INT->RISE = 0x1<<0; - } - else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<0) ) - { - flex_int0_falling_edge_counter++; - LPC_GPIO_PIN_INT->FALL = 0x1<<0; - } - LPC_GPIO_PIN_INT->IST = 0x1<<0; - } - } - return; -} - -/***************************************************************************** -** Function name: FLEX_INT1_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void FLEX_INT1_IRQHandler(void) -{ - flex_int1_counter++; - if ( LPC_GPIO_PIN_INT->IST & (0x1<<1) ) - { - if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<1) ) - { - flex_int1_level_counter++; - } - else - { - if ( LPC_GPIO_PIN_INT->RISE & (0x1<<1) ) - { - flex_int1_rising_edge_counter++; - LPC_GPIO_PIN_INT->RISE = 0x1<<1; - } - else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<1) ) - { - flex_int1_falling_edge_counter++; - LPC_GPIO_PIN_INT->FALL = 0x1<<1; - } - LPC_GPIO_PIN_INT->IST = 0x1<<1; - } - } - return; -} - -/***************************************************************************** -** Function name: FLEX_INT2_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void FLEX_INT2_IRQHandler(void) -{ - flex_int2_counter++; - if ( LPC_GPIO_PIN_INT->IST & (0x1<<2) ) - { - if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<2) ) - { - flex_int2_level_counter++; - } - else - { - if ( LPC_GPIO_PIN_INT->RISE & (0x1<<2) ) - { - flex_int2_rising_edge_counter++; - LPC_GPIO_PIN_INT->RISE = 0x1<<2; - } - else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<2) ) - { - flex_int2_falling_edge_counter++; - LPC_GPIO_PIN_INT->FALL = 0x1<<2; - } - LPC_GPIO_PIN_INT->IST = 0x1<<2; - } - } - return; -} - -/***************************************************************************** -** Function name: FLEX_INT3_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void FLEX_INT3_IRQHandler(void) -{ - flex_int3_counter++; - if ( LPC_GPIO_PIN_INT->IST & (0x1<<3) ) - { - if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<3) ) - { - flex_int3_level_counter++; - } - else - { - if ( LPC_GPIO_PIN_INT->RISE & (0x1<<3) ) - { - flex_int3_rising_edge_counter++; - LPC_GPIO_PIN_INT->RISE = 0x1<<3; - } - else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<3) ) - { - flex_int3_falling_edge_counter++; - LPC_GPIO_PIN_INT->FALL = 0x1<<3; - } - LPC_GPIO_PIN_INT->IST = 0x1<<3; - } - } - return; -} - -/***************************************************************************** -** Function name: FLEX_INT4_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void FLEX_INT4_IRQHandler(void) -{ - flex_int4_counter++; - if ( LPC_GPIO_PIN_INT->IST & (0x1<<4) ) - { - if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<4) ) - { - flex_int4_level_counter++; - } - else - { - if ( LPC_GPIO_PIN_INT->RISE & (0x1<<4) ) - { - flex_int4_rising_edge_counter++; - LPC_GPIO_PIN_INT->RISE = 0x1<<4; - } - else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<4) ) - { - flex_int4_falling_edge_counter++; - LPC_GPIO_PIN_INT->FALL = 0x1<<4; - } - LPC_GPIO_PIN_INT->IST = 0x1<<4; - } - } - return; -} - -/***************************************************************************** -** Function name: FLEX_INT5_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void FLEX_INT5_IRQHandler(void) -{ - flex_int5_counter++; - if ( LPC_GPIO_PIN_INT->IST & (0x1<<5) ) - { - if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<5) ) - { - flex_int5_level_counter++; - } - else - { - if ( LPC_GPIO_PIN_INT->RISE & (0x1<<5) ) - { - flex_int5_rising_edge_counter++; - LPC_GPIO_PIN_INT->RISE = 0x1<<5; - } - else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<5) ) - { - flex_int5_falling_edge_counter++; - LPC_GPIO_PIN_INT->FALL = 0x1<<5; - } - LPC_GPIO_PIN_INT->IST = 0x1<<5; - } - } - return; -} - -/***************************************************************************** -** Function name: FLEX_INT6_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void FLEX_INT6_IRQHandler(void) -{ - flex_int6_counter++; - if ( LPC_GPIO_PIN_INT->IST & (0x1<<6) ) - { - if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<6) ) - { - flex_int6_level_counter++; - } - else - { - if ( LPC_GPIO_PIN_INT->RISE & (0x1<<6) ) - { - flex_int6_rising_edge_counter++; - LPC_GPIO_PIN_INT->RISE = 0x1<<6; - } - else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<6) ) - { - flex_int6_falling_edge_counter++; - LPC_GPIO_PIN_INT->FALL = 0x1<<6; - } - LPC_GPIO_PIN_INT->IST = 0x1<<6; - } - } - return; -} - -/***************************************************************************** -** Function name: FLEX_INT7_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void FLEX_INT7_IRQHandler(void) -{ - flex_int7_counter++; - if ( LPC_GPIO_PIN_INT->IST & (0x1<<7) ) - { - if ( LPC_GPIO_PIN_INT->ISEL & (0x1<<7) ) - { - flex_int7_level_counter++; - } - else - { - if ( LPC_GPIO_PIN_INT->RISE & (0x1<<7) ) - { - flex_int7_rising_edge_counter++; - LPC_GPIO_PIN_INT->RISE = 0x1<<7; - } - else if ( LPC_GPIO_PIN_INT->FALL & (0x1<<7) ) - { - flex_int7_falling_edge_counter++; - LPC_GPIO_PIN_INT->FALL = 0x1<<7; - } - LPC_GPIO_PIN_INT->IST = 0x1<<7; - } - } - return; -} - -/***************************************************************************** -** Function name: GINT0_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void GINT0_IRQHandler(void) -{ - gint0_counter++; - if ( LPC_GPIO_GROUP_INT0->CTRL & 0x1 ) - { - if ( LPC_GPIO_GROUP_INT0->CTRL & (0x1<<4) ) - { - gint0_level_counter++; - } - else - { - gint0_edge_counter++; - } - LPC_GPIO_GROUP_INT0->CTRL |= 0x1; - } - return; -} - -/***************************************************************************** -** Function name: GINT1_IRQHandler -** -** Descriptions: Use one GPIO pin as interrupt source -** -** parameters: None -** -** Returned value: None -** -*****************************************************************************/ -void GINT1_IRQHandler(void) -{ - gint1_counter++; - if ( LPC_GPIO_GROUP_INT1->CTRL & 0x1 ) - { - if ( LPC_GPIO_GROUP_INT1->CTRL & (0x1<<4) ) - { - gint1_level_counter++; - } - else - { - gint1_edge_counter++; - } - LPC_GPIO_GROUP_INT1->CTRL |= 0x1; - } - return; -} - -/***************************************************************************** -** Function name: GPIOInit -** -** Descriptions: Initialize GPIO, install the -** GPIO interrupt handler -** -** parameters: None -** -** Returned value: true or false, return false if the VIC table -** is full and GPIO interrupt handler can be -** installed. -** -*****************************************************************************/ -void GPIOInit( void ) -{ - /* Enable AHB clock to the GPIO domain. */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6); - - /* Enable AHB clock to the FlexInt, GroupedInt domain. */ - LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<19) | (1<<23) | (1<<24)); - - return; -} - -/***************************************************************************** -** Function name: GPIOSetFlexInterrupt -** -** Descriptions: Set interrupt sense, event, etc. -** sense: edge or level, 0 is edge, 1 is level -** event/polarity: 0 is active low/falling, 1 is high/rising. -** -** parameters: channel #, port #, bit position, sense, event(polarity) -** -** Returned value: None -** -*****************************************************************************/ -void GPIOSetFlexInterrupt( uint32_t channelNum, uint32_t portNum, uint32_t bitPosi, - uint32_t sense, uint32_t event ) -{ - switch ( channelNum ) - { - case CHANNEL0: - if ( portNum ) - { - LPC_SYSCON->PINTSEL[0] = bitPosi + 24; - } - else - { - LPC_SYSCON->PINTSEL[0] = bitPosi; - } - NVIC_EnableIRQ(FLEX_INT0_IRQn); - break; - case CHANNEL1: - if ( portNum ) - { - LPC_SYSCON->PINTSEL[1] = bitPosi + 24; - } - else - { - LPC_SYSCON->PINTSEL[1] = bitPosi; - } - NVIC_EnableIRQ(FLEX_INT1_IRQn); - break; - case CHANNEL2: - if ( portNum ) - { - LPC_SYSCON->PINTSEL[2] = bitPosi + 24; - } - else - { - LPC_SYSCON->PINTSEL[2] = bitPosi; - } - NVIC_EnableIRQ(FLEX_INT2_IRQn); - break; - case CHANNEL3: - if ( portNum ) - { - LPC_SYSCON->PINTSEL[3] = bitPosi + 24; - } - else - { - LPC_SYSCON->PINTSEL[3] = bitPosi; - } - NVIC_EnableIRQ(FLEX_INT3_IRQn); - break; - case CHANNEL4: - if ( portNum ) - { - LPC_SYSCON->PINTSEL[4] = bitPosi + 24; - } - else - { - LPC_SYSCON->PINTSEL[4] = bitPosi; - } - NVIC_EnableIRQ(FLEX_INT4_IRQn); - break; - case CHANNEL5: - if ( portNum ) - { - LPC_SYSCON->PINTSEL[5] = bitPosi + 24; - } - else - { - LPC_SYSCON->PINTSEL[5] = bitPosi; - } - NVIC_EnableIRQ(FLEX_INT5_IRQn); - break; - case CHANNEL6: - if ( portNum ) - { - LPC_SYSCON->PINTSEL[6] = bitPosi + 24; - } - else - { - LPC_SYSCON->PINTSEL[6] = bitPosi; - } - NVIC_EnableIRQ(FLEX_INT6_IRQn); - break; - case CHANNEL7: - if ( portNum ) - { - LPC_SYSCON->PINTSEL[7] = bitPosi + 24; - } - else - { - LPC_SYSCON->PINTSEL[7] = bitPosi; - } - NVIC_EnableIRQ(FLEX_INT7_IRQn); - break; - default: - break; - } - if ( sense == 0 ) - { - LPC_GPIO_PIN_INT->ISEL &= ~(0x1<IENF |= (0x1<IENR |= (0x1<ISEL |= (0x1<IENR |= (0x1<IENF &= ~(0x1<IENF |= (0x1<ISEL & (0x1<SIENF |= (0x1<SIENR |= (0x1<SIENR |= (0x1<ISEL & (0x1<CIENF |= (0x1<CIENR |= (0x1<CIENR |= (0x1<IST & (0x1<ISEL & (0x1<IST = (1<CTRL &= ~(0x1<<2); /* Edge trigger */ - } - else - { - LPC_GPIO_GROUP_INT0->CTRL |= (0x1<<2); /* Level trigger. */ - } - LPC_GPIO_GROUP_INT0->CTRL |= (logic<<1); - LPC_GPIO_GROUP_INT0->PORT_POL[0] = *((uint32_t *)(eventPattern + 0)); - LPC_GPIO_GROUP_INT0->PORT_POL[1] = *((uint32_t *)(eventPattern + 1)); - LPC_GPIO_GROUP_INT0->PORT_ENA[0] = *((uint32_t *)(bitPattern + 0)); - LPC_GPIO_GROUP_INT0->PORT_ENA[1] = *((uint32_t *)(bitPattern + 1)); - /* as soon as enabled, an edge may be generated */ - /* clear interrupt flag and NVIC pending interrupt to */ - /* workaround the potential edge generated as enabled */ - LPC_GPIO_GROUP_INT0->CTRL |= (1<<0); - NVIC_ClearPendingIRQ(GINT0_IRQn); - NVIC_EnableIRQ(GINT0_IRQn); - break; - case GROUP1: - if ( sense == 0 ) - { - LPC_GPIO_GROUP_INT1->CTRL &= ~(0x1<<2); /* Edge trigger */ - } - else - { - LPC_GPIO_GROUP_INT1->CTRL |= (0x1<<2); /* Level trigger. */ - } - LPC_GPIO_GROUP_INT1->CTRL |= (logic<<1); - LPC_GPIO_GROUP_INT1->PORT_POL[0] = *((uint32_t *)(eventPattern + 0)); - LPC_GPIO_GROUP_INT1->PORT_POL[1] = *((uint32_t *)(eventPattern + 1)); - LPC_GPIO_GROUP_INT1->PORT_ENA[0] = *((uint32_t *)(bitPattern + 0)); - LPC_GPIO_GROUP_INT1->PORT_ENA[1] = *((uint32_t *)(bitPattern + 1)); - /* as soon as enabled, an edge may be generated */ - /* clear interrupt flag and NVIC pending interrupt to */ - /* workaround the potential edge generated as enabled */ - LPC_GPIO_GROUP_INT1->CTRL |= (1<<0); - NVIC_ClearPendingIRQ(GINT1_IRQn); - NVIC_EnableIRQ(GINT1_IRQn); - break; - default: - break; - } - - return; -} - -/***************************************************************************** -** Function name: GPIOGetPinValue -** -** Descriptions: Read Current state of port pin, PIN register value -** -** parameters: port num, bit position -** Returned value: None -** -*****************************************************************************/ -uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi ) -{ - uint32_t regVal = 0; - - if( bitPosi < 0x20 ) - { - if ( LPC_GPIO->PIN[portNum] & (0x1<PIN[portNum]; - } - return ( regVal ); -} - -/***************************************************************************** -** Function name: GPIOSetBitValue -** -** Descriptions: Set/clear a bit in a specific position -** -** parameters: port num, bit position, bit value -** -** Returned value: None -** -*****************************************************************************/ -void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal ) -{ - if ( bitVal ) - { - LPC_GPIO->SET[portNum] = 1<CLR[portNum] = 1<DIR[portNum] |= (1<DIR[portNum] &= ~(1< -#include "LPC11Uxx.h" -#include "uart.h" - -volatile uint32_t UARTStatus; -volatile uint8_t UARTTxEmpty = 1; -volatile uint8_t UARTBuffer[BUFSIZE]; -volatile uint32_t UARTCount = 0; - -/***************************************************************************** -** Function name: UART_IRQHandler -** -** Descriptions: UART interrupt handler -** -** parameters: None -** Returned value: None -** -*****************************************************************************/ -void UART_IRQHandler(void) -{ - uint8_t IIRValue, LSRValue; - uint8_t Dummy = Dummy; - - IIRValue = LPC_USART->IIR; - - IIRValue >>= 1; /* skip pending bit in IIR */ - IIRValue &= 0x07; /* check bit 1~3, interrupt identification */ - if (IIRValue == IIR_RLS) /* Receive Line Status */ - { - LSRValue = LPC_USART->LSR; - /* Receive Line Status */ - if (LSRValue & (LSR_OE | LSR_PE | LSR_FE | LSR_RXFE | LSR_BI)) - { - /* There are errors or break interrupt */ - /* Read LSR will clear the interrupt */ - UARTStatus = LSRValue; - Dummy = LPC_USART->RBR; /* Dummy read on RX to clear - interrupt, then bail out */ - return; - } - if (LSRValue & LSR_RDR) /* Receive Data Ready */ - { - /* If no error on RLS, normal ready, save into the data buffer. */ - /* Note: read RBR will clear the interrupt */ - UARTBuffer[UARTCount++] = LPC_USART->RBR; - if (UARTCount == BUFSIZE) - { - UARTCount = 0; /* buffer overflow */ - } - } - } - else if (IIRValue == IIR_RDA) /* Receive Data Available */ - { - /* Receive Data Available */ - UARTBuffer[UARTCount++] = LPC_USART->RBR; - if (UARTCount == BUFSIZE) - { - UARTCount = 0; /* buffer overflow */ - } - } - else if (IIRValue == IIR_CTI) /* Character timeout indicator */ - { - /* Character Time-out indicator */ - UARTStatus |= 0x100; /* Bit 9 as the CTI error */ - } - else if (IIRValue == IIR_THRE) /* THRE, transmit holding register empty */ - { - /* THRE interrupt */ - LSRValue = LPC_USART->LSR; /* Check status in the LSR to see if - valid data in U0THR or not */ - if (LSRValue & LSR_THRE) - { - UARTTxEmpty = 1; - } - else - { - UARTTxEmpty = 0; - } - } - return; -} - -#if MODEM_TEST -/***************************************************************************** -** Function name: ModemInit -** -** Descriptions: Initialize UART0 port as modem, setup pin select. -** -** parameters: None -** Returned value: None -** -*****************************************************************************/ -void ModemInit( void ) -{ - LPC_IOCON->PIO2_0 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO2_0 |= 0x01; /* UART DTR */ - LPC_IOCON->PIO0_7 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO0_7 |= 0x01; /* UART CTS */ - LPC_IOCON->PIO1_5 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO1_5 |= 0x01; /* UART RTS */ -#if 1 - LPC_IOCON->DSR_LOC = 0; - LPC_IOCON->PIO2_1 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO2_1 |= 0x01; /* UART DSR */ - - LPC_IOCON->DCD_LOC = 0; - LPC_IOCON->PIO2_2 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO2_2 |= 0x01; /* UART DCD */ - - LPC_IOCON->RI_LOC = 0; - LPC_IOCON->PIO2_3 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO2_3 |= 0x01; /* UART RI */ - -#else - LPC_IOCON->DSR_LOC = 1; - LPC_IOCON->PIO3_1 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO3_1 |= 0x01; /* UART DSR */ - - LPC_IOCON->DCD_LOC = 1; - LPC_IOCON->PIO3_2 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO3_2 |= 0x01; /* UART DCD */ - - LPC_IOCON->RI_LOC = 1; - LPC_IOCON->PIO3_3 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO3_3 |= 0x01; /* UART RI */ -#endif - LPC_USART->MCR = 0xC0; /* Enable Auto RTS and Auto CTS. */ - return; -} -#endif - -/***************************************************************************** -** Function name: UARTInit -** -** Descriptions: Initialize UART0 port, setup pin select, -** clock, parity, stop bits, FIFO, etc. -** -** parameters: UART baudrate -** Returned value: None -** -*****************************************************************************/ -void UARTInit(uint32_t baudrate) -{ - uint32_t Fdiv; - uint32_t regVal; - - UARTTxEmpty = 1; - UARTCount = 0; - - NVIC_DisableIRQ(UART_IRQn); - - LPC_IOCON->PIO0_18 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO0_18 |= 0x01; /* UART RXD */ - LPC_IOCON->PIO0_19 &= ~0x07; - LPC_IOCON->PIO0_19 |= 0x01; /* UART TXD */ - /* Enable UART clock */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12); - LPC_SYSCON->UARTCLKDIV = 0x1; /* divided by 1 */ - - LPC_USART->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */ - regVal = LPC_SYSCON->UARTCLKDIV; - - Fdiv = (((SystemCoreClock*LPC_SYSCON->SYSAHBCLKDIV)/regVal)/16)/baudrate ; /*baud rate */ - - LPC_USART->DLM = Fdiv / 256; - LPC_USART->DLL = Fdiv % 256; - LPC_USART->LCR = 0x03; /* DLAB = 0 */ - LPC_USART->FCR = 0x07; /* Enable and reset TX and RX FIFO. */ - - /* Read to clear the line status. */ - regVal = LPC_USART->LSR; - - /* Ensure a clean start, no data in either TX or RX FIFO. */ -// CodeRed - added parentheses around comparison in operand of & - while (( LPC_USART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) ); - while ( LPC_USART->LSR & LSR_RDR ) - { - regVal = LPC_USART->RBR; /* Dump data from RX FIFO */ - } - - /* Enable the UART Interrupt */ - NVIC_EnableIRQ(UART_IRQn); - -#if CONFIG_UART_ENABLE_INTERRUPT==1 -#if CONFIG_UART_ENABLE_TX_INTERRUPT==1 - LPC_USART->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */ -#else - LPC_USART->IER = IER_RBR | IER_RLS; /* Enable UART interrupt */ -#endif -#endif - return; -} - -/***************************************************************************** -** Function name: UARTSend -** -** Descriptions: Send a block of data to the UART 0 port based -** on the data length -** -** parameters: buffer pointer, and data length -** Returned value: None -** -*****************************************************************************/ -void UARTSend(uint8_t *BufferPtr, uint32_t Length) -{ - - while ( Length != 0 ) - { - /* THRE status, contain valid data */ -#if CONFIG_UART_ENABLE_TX_INTERRUPT==1 - /* Below flag is set inside the interrupt handler when THRE occurs. */ - while ( !(UARTTxEmpty & 0x01) ); - LPC_USART->THR = *BufferPtr; - UARTTxEmpty = 0; /* not empty in the THR until it shifts out */ -#else - while ( !(LPC_USART->LSR & LSR_THRE) ); - LPC_USART->THR = *BufferPtr; -#endif - BufferPtr++; - Length--; - } - return; -} - -/****************************************************************************** -** End Of File -******************************************************************************/ diff --git a/demos/bsp/lpc11uxx/uart.h b/demos/bsp/lpc11uxx/uart.h deleted file mode 100644 index 9f00ab8af..000000000 --- a/demos/bsp/lpc11uxx/uart.h +++ /dev/null @@ -1,55 +0,0 @@ -/***************************************************************************** - * uart.h: Header file for NXP LPC1xxx Family Microprocessors - * - * Copyright(C) 2008, NXP Semiconductor - * All rights reserved. - * - * History - * 2009.12.07 ver 1.00 Preliminary version, first Release - * -******************************************************************************/ -#ifndef __UART_H -#define __UART_H - -#define RS485_ENABLED 0 -#define TX_INTERRUPT 0 /* 0 if TX uses polling, 1 interrupt driven. */ -#define MODEM_TEST 0 - -#define IER_RBR 0x01 -#define IER_THRE 0x02 -#define IER_RLS 0x04 - -#define IIR_PEND 0x01 -#define IIR_RLS 0x03 -#define IIR_RDA 0x02 -#define IIR_CTI 0x06 -#define IIR_THRE 0x01 - -#define LSR_RDR 0x01 -#define LSR_OE 0x02 -#define LSR_PE 0x04 -#define LSR_FE 0x08 -#define LSR_BI 0x10 -#define LSR_THRE 0x20 -#define LSR_TEMT 0x40 -#define LSR_RXFE 0x80 - -#define BUFSIZE 0x40 - -/* RS485 mode definition. */ -#define RS485_NMMEN (0x1<<0) -#define RS485_RXDIS (0x1<<1) -#define RS485_AADEN (0x1<<2) -#define RS485_SEL (0x1<<3) -#define RS485_DCTRL (0x1<<4) -#define RS485_OINV (0x1<<5) - -void ModemInit( void ); -void UARTInit(uint32_t Baudrate); -void UART_IRQHandler(void); -void UARTSend(uint8_t *BufferPtr, uint32_t Length); - -#endif /* end __UART_H */ -/***************************************************************************** -** End Of File -******************************************************************************/ diff --git a/demos/bsp/lpc175x_6x/startup_keil/startup_LPC17xx.s b/demos/bsp/lpc175x_6x/startup_keil/startup_LPC17xx.s new file mode 100644 index 000000000..02a0f9a99 --- /dev/null +++ b/demos/bsp/lpc175x_6x/startup_keil/startup_LPC17xx.s @@ -0,0 +1,287 @@ +;/**************************************************************************//** +; * @file startup_LPC17xx.s +; * @brief CMSIS Cortex-M3 Core Device Startup File for +; * NXP LPC17xx Device Series +; * @version V1.10 +; * @date 06. April 2011 +; * +; * @note +; * Copyright (C) 2009-2011 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 16: Watchdog Timer + DCD TIMER0_IRQHandler ; 17: Timer0 + DCD TIMER1_IRQHandler ; 18: Timer1 + DCD TIMER2_IRQHandler ; 19: Timer2 + DCD TIMER3_IRQHandler ; 20: Timer3 + DCD UART0_IRQHandler ; 21: UART0 + DCD UART1_IRQHandler ; 22: UART1 + DCD UART2_IRQHandler ; 23: UART2 + DCD UART3_IRQHandler ; 24: UART3 + DCD PWM1_IRQHandler ; 25: PWM1 + DCD I2C0_IRQHandler ; 26: I2C0 + DCD I2C1_IRQHandler ; 27: I2C1 + DCD I2C2_IRQHandler ; 28: I2C2 + DCD SPI_IRQHandler ; 29: SPI + DCD SSP0_IRQHandler ; 30: SSP0 + DCD SSP1_IRQHandler ; 31: SSP1 + DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL) + DCD RTC_IRQHandler ; 33: Real Time Clock + DCD EINT0_IRQHandler ; 34: External Interrupt 0 + DCD EINT1_IRQHandler ; 35: External Interrupt 1 + DCD EINT2_IRQHandler ; 36: External Interrupt 2 + DCD EINT3_IRQHandler ; 37: External Interrupt 3 + DCD ADC_IRQHandler ; 38: A/D Converter + DCD BOD_IRQHandler ; 39: Brown-Out Detect + DCD USB_IRQHandler ; 40: USB + DCD CAN_IRQHandler ; 41: CAN + DCD DMA_IRQHandler ; 42: General Purpose DMA + DCD I2S_IRQHandler ; 43: I2S + DCD ENET_IRQHandler ; 44: Ethernet + DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer + DCD MCPWM_IRQHandler ; 46: Motor Control PWM + DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface + DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) + DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup + DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup + + + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF + ENDIF + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT TIMER0_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT PLL0_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT EINT0_IRQHandler [WEAK] + EXPORT EINT1_IRQHandler [WEAK] + EXPORT EINT2_IRQHandler [WEAK] + EXPORT EINT3_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT RIT_IRQHandler [WEAK] + EXPORT MCPWM_IRQHandler [WEAK] + EXPORT QEI_IRQHandler [WEAK] + EXPORT PLL1_IRQHandler [WEAK] + EXPORT USBActivity_IRQHandler [WEAK] + EXPORT CANActivity_IRQHandler [WEAK] + +WDT_IRQHandler +TIMER0_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER3_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +PWM1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI_IRQHandler +SSP0_IRQHandler +SSP1_IRQHandler +PLL0_IRQHandler +RTC_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +EINT2_IRQHandler +EINT3_IRQHandler +ADC_IRQHandler +BOD_IRQHandler +USB_IRQHandler +CAN_IRQHandler +DMA_IRQHandler +I2S_IRQHandler +ENET_IRQHandler +RIT_IRQHandler +MCPWM_IRQHandler +QEI_IRQHandler +PLL1_IRQHandler +USBActivity_IRQHandler +CANActivity_IRQHandler + + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/demos/device/device_os_none/.cproject b/demos/device/device_os_none/.cproject index 38fca4563..240247db3 100644 --- a/demos/device/device_os_none/.cproject +++ b/demos/device/device_os_none/.cproject @@ -322,6 +322,7 @@ +