From 50381f7b4caf2d5ee10de16e9cf7bf2fb113364a Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 1 Jul 2023 17:08:20 +0700 Subject: refactor to match fsp_cfg --- hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h | 39 ++++ .../ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_clock_cfg.h | 21 ++ .../ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 + .../ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 + .../ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 83 +++++++ hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h | 39 ---- hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h | 21 -- .../boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_cfg.h | 5 - .../ra4m1_ek/fsp_cfg/bsp_mcu_device_pn_cfg.h | 11 - .../boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h | 83 ------- hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h | 37 +++ .../ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_clock_cfg.h | 27 +++ .../ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 260 +++++++++++++++++++++ hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h | 37 --- hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h | 27 --- .../boards/ra4m3_ek/fsp_cfg/bsp_mcu_family_cfg.h | 260 --------------------- hw/bsp/ra/boards/ra6m1_ek/board.cmake | 13 ++ hw/bsp/ra/family.cmake | 1 + hw/bsp/ra/family.mk | 1 + 19 files changed, 498 insertions(+), 483 deletions(-) create mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_clock_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h delete mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h delete mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h delete mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_cfg.h delete mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_pn_cfg.h delete mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_clock_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h delete mode 100755 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h delete mode 100644 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h delete mode 100644 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_mcu_family_cfg.h create mode 100644 hw/bsp/ra/boards/ra6m1_ek/board.cmake diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..b337e49f2 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,39 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" + +#undef RA_NOT_DEFINED +#define BSP_CFG_RTOS (0) +#if defined(_RA_BOOT_IMAGE) +#define BSP_CFG_BOOT_IMAGE (1) +#endif +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) +#define BSP_CFG_HEAP_BYTES (0x1000) +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) + +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + +#define BSP_FEATURE_TFU_SUPPORTED 0 + +// for SystemInit() +void bsp_init(void * p_args); + +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_clock_cfg.h new file mode 100644 index 000000000..930fa3547 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_clock_cfg.h @@ -0,0 +1,21 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ +#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL_8_0) /* PLL Mul x8 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* UCLK Src: PLL */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000..444d32e56 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (4) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..d810dabb2 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA4M1AB3CFP +#define BSP_MCU_FEATURE_SET ('A') +#define BSP_ROM_SIZE_BYTES (262144) +#define BSP_RAM_SIZE_BYTES (32768) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_LQFP +#define BSP_PACKAGE_PINS (100) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..4e080023e --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,83 @@ +/* generated configuration header file through renesas e2 studio */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ + +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "bsp_mcu_info.h" +#include "bsp_clock_cfg.h" + +#define BSP_MCU_GROUP_RA4M1 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (24000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (32000000) + #elif BSP_CFG_HOCO_FREQUENCY == 4 + #define BSP_HOCO_HZ (48000000) + #elif BSP_CFG_HOCO_FREQUENCY == 5 + #define BSP_HOCO_HZ (64000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) + +#define BSP_TZ_SECURE_BUILD (0) +#define BSP_TZ_NONSECURE_BUILD (0) + +#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0 + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) +#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +/* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ +#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) + #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) + #else +/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +#endif + +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h deleted file mode 100644 index b337e49f2..000000000 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h +++ /dev/null @@ -1,39 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" - -#undef RA_NOT_DEFINED -#define BSP_CFG_RTOS (0) -#if defined(_RA_BOOT_IMAGE) -#define BSP_CFG_BOOT_IMAGE (1) -#endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -#define BSP_CFG_HEAP_BYTES (0x1000) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) - -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 - -#define BSP_FEATURE_TFU_SUPPORTED 0 - -// for SystemInit() -void bsp_init(void * p_args); - -#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h deleted file mode 100644 index 930fa3547..000000000 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h +++ /dev/null @@ -1,21 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CLOCK_CFG_H_ -#define BSP_CLOCK_CFG_H_ -#define BSP_CFG_CLOCKS_SECURE (0) -#define BSP_CFG_CLOCKS_OVERRIDE (0) -#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */ -#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ -#define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */ -#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ -#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL_8_0) /* PLL Mul x8 */ -#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ -#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ -#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ -#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */ -#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */ -#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ -#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ -#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ -#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ -#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* UCLK Src: PLL */ -#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_cfg.h deleted file mode 100644 index 444d32e56..000000000 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_CFG_H_ -#define BSP_MCU_DEVICE_CFG_H_ -#define BSP_CFG_MCU_PART_SERIES (4) -#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index d810dabb2..000000000 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA4M1AB3CFP -#define BSP_MCU_FEATURE_SET ('A') -#define BSP_ROM_SIZE_BYTES (262144) -#define BSP_RAM_SIZE_BYTES (32768) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (100) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h deleted file mode 100644 index 4e080023e..000000000 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h +++ /dev/null @@ -1,83 +0,0 @@ -/* generated configuration header file through renesas e2 studio */ -#ifndef BSP_MCU_FAMILY_CFG_H_ -#define BSP_MCU_FAMILY_CFG_H_ - -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "bsp_mcu_info.h" -#include "bsp_clock_cfg.h" - -#define BSP_MCU_GROUP_RA4M1 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (24000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (32000000) - #elif BSP_CFG_HOCO_FREQUENCY == 4 - #define BSP_HOCO_HZ (48000000) - #elif BSP_CFG_HOCO_FREQUENCY == 5 - #define BSP_HOCO_HZ (64000000) - #else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" - #endif -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) - -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (0) - -#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0 - -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) -#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) -#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) - -/* - ID Code - Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. - WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. - */ -#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) - #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) - #else -/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ -#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) -#endif - -#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..a9cb8210b --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,37 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" + +#undef RA_NOT_DEFINED +#define BSP_CFG_RTOS (0) +#if defined(_RA_BOOT_IMAGE) +#define BSP_CFG_BOOT_IMAGE (1) +#endif +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) +#define BSP_CFG_HEAP_BYTES (0x400) +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) + +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + +// for SystemInit() +void bsp_init(void * p_args); + +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_clock_cfg.h new file mode 100644 index 000000000..4f490f340 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_clock_cfg.h @@ -0,0 +1,27 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ + +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_24_0 /* PLL Mul x24.0 */ +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL2 Div /3 */ +#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_24_0 /* PLL2 Mul x24.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_4) /* UCLK Div /4 */ + +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..4ecda1c66 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,260 @@ +/* generated configuration header file through renesas e2 studio */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_info.h" + +#define BSP_CFG_MCU_PART_SERIES (4) +#define BSP_MCU_R7FA4M3AF3CFB +#define BSP_ROM_SIZE_BYTES (1048576) +#define BSP_RAM_SIZE_BYTES (131072) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_LQFP +#define BSP_PACKAGE_PINS (144) + +#define BSP_MCU_GROUP_RA4M3 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (16000000) +#elif BSP_CFG_HOCO_FREQUENCY == 1 +#define BSP_HOCO_HZ (18000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 +#define BSP_HOCO_HZ (20000000) +#else +#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif + +#define BSP_CFG_FLL_ENABLE (0) + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) +#define BSP_MCU_VBATT_SUPPORT (1) + +#if defined(_RA_TZ_SECURE) +#define BSP_TZ_SECURE_BUILD (1) +#define BSP_TZ_NONSECURE_BUILD (0) +#elif defined(_RA_TZ_NONSECURE) +#define BSP_TZ_SECURE_BUILD (0) +#define BSP_TZ_NONSECURE_BUILD (1) +#else +#define BSP_TZ_SECURE_BUILD (0) +#define BSP_TZ_NONSECURE_BUILD (0) +#endif + +/* TrustZone Settings */ +#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) +#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) +#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + +/* CMSIS TrustZone Settings */ +#define SCB_CSR_AIRCR_INIT (1) +#define SCB_AIRCR_BFHFNMINS_VAL (0) +#define SCB_AIRCR_SYSRESETREQS_VAL (1) +#define SCB_AIRCR_PRIS_VAL (0) +#define TZ_FPU_NS_USAGE (1) +#define SCB_NSACR_CP10_11_VAL (3U) + +#define FPU_FPCCR_TS_VAL (1U) +#define FPU_FPCCR_CLRONRETS_VAL (1) + +#define FPU_FPCCR_CLRONRET_VAL (1) + +/* The C-Cache line size that is configured during startup. */ +#define BSP_CFG_C_CACHE_LINE_SIZE (1U) + +/* Type 1 Peripheral Security Attribution */ + +/* Peripheral Security Attribution Register (PSAR) Settings */ +#define BSP_TZ_CFG_PSARB \ + ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ + (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | 0x33f4f9) /* Unused */ +#define BSP_TZ_CFG_PSARC \ + ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | 0x7fffcef4) /* Unused */ +#define BSP_TZ_CFG_PSARD \ + ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ + 0xffae07f0) /* Unused */ +#define BSP_TZ_CFG_PSARE \ + ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ + (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ + (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | 0x3f3ff8) /* Unused */ +#define BSP_TZ_CFG_MSSAR \ + ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ + 0xfffffffc) /* Unused */ + +/* Type 2 Peripheral Security Attribution */ + +/* Security attribution for Cache registers. */ +#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) + +/* Security attribution for RSTSRn registers. */ +#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) + +/* Security attribution for registers of LVD channels. */ +#define BSP_TZ_CFG_LVDSAR \ + ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ + 0xFFFFFFFCU) + +/* Security attribution for LPM registers. */ +#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) +/* Deep Standby Interrupt Factor Security Attribution Register. */ +#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) + +/* Security attribution for CGC registers. */ +#if BSP_CFG_CLOCKS_SECURE +/* Protect all CGC registers from Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) +#endif + +/* Security attribution for Battery Backup registers. */ +#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) + +/* Security attribution for registers for IRQ channels. */ +#define BSP_TZ_CFG_ICUSARA \ + ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | 0xFFFF0000U) + +/* Security attribution for NMI registers. */ +#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ + +/* Security attribution for registers for DMAC channels */ +#define BSP_TZ_CFG_ICUSARC \ + ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | 0xFFFFFF00U) + +/* Security attribution registers for SELSR0. */ +#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) + +/* Security attribution registers for WUPEN0. */ +#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) + +/* Security attribution registers for WUPEN1. */ +#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) + +/* Set DTCSTSAR if the Secure program uses the DTC. */ +// #if RA_NOT_DEFINED == RA_NOT_DEFINED +#define BSP_TZ_CFG_DTC_USED (0U) +// #else +// #define BSP_TZ_CFG_DTC_USED (1U) +// #endif + +/* Security attribution of FLWT and FCKMHZ registers. */ +/* If the CGC registers are only accessible in Secure mode, than there is no + * reason for nonsecure applications to access FLWT and FCKMHZ. */ +#if BSP_CFG_CLOCKS_SECURE +/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ +#define BSP_TZ_CFG_FSAR (0xFEFEU) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_FSAR (0xFFFFU) +#endif + +/* Security attribution for SRAM registers. */ +/* If the CGC registers are only accessible in Secure mode, than there is no + * reason for Non Secure applications to access + * SRAM0WTEN and therefore there is no reason to access PRCR2. */ +#define BSP_TZ_CFG_SRAMSAR (1 | ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | 4 | 0xFFFFFFF8U) + +/* Security attribution for Standby RAM registers. */ +#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) + +/* Security attribution for the DMAC Bus Master MPU settings. */ +/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. + */ +#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) + +/* Security Attribution Register A for BUS Control registers. */ +#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) +/* Security Attribution Register B for BUS Control registers. */ +#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + +/* Option Function Select Register 1 Security Attribution */ +#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) +#define BSP_CFG_ROM_REG_OFS1_SEL \ + (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) +#else +#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) +#endif + +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) + +/* Used to create IELS values for the interrupt initialization table + * g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector) +/* Dual Mode Select Register */ +#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU) +/* Block Protection Register 0 */ +#define BSP_CFG_ROM_REG_BPS0 (~(0U)) +/* Block Protection Register 1 */ +#define BSP_CFG_ROM_REG_BPS1 (~(0U)) +/* Block Protection Register 2 */ +#define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU) +/* Permanent Block Protection Register 0 */ +#define BSP_CFG_ROM_REG_PBPS0 (~(0U)) +/* Permanent Block Protection Register 1 */ +#define BSP_CFG_ROM_REG_PBPS1 (~(0U)) +/* Permanent Block Protection Register 2 */ +#define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU) +/* Security Attribution for Block Protection Register 0 (If any blocks are + * marked as protected in the secure application, then mark them as secure) */ +#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) +/* Security Attribution for Block Protection Register 1 (If any blocks are + * marked as protected in the secure application, then mark them as secure) */ +#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) +/* Security Attribution for Block Protection Register 2 (If any blocks are + * marked as protected in the secure application, then mark them as secure) */ +#define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU) +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) + +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h deleted file mode 100755 index a9cb8210b..000000000 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h +++ /dev/null @@ -1,37 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" - -#undef RA_NOT_DEFINED -#define BSP_CFG_RTOS (0) -#if defined(_RA_BOOT_IMAGE) -#define BSP_CFG_BOOT_IMAGE (1) -#endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -#define BSP_CFG_HEAP_BYTES (0x400) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) - -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 - -// for SystemInit() -void bsp_init(void * p_args); - -#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h deleted file mode 100644 index 4f490f340..000000000 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h +++ /dev/null @@ -1,27 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CLOCK_CFG_H_ -#define BSP_CLOCK_CFG_H_ - -#define BSP_CFG_CLOCKS_SECURE (0) -#define BSP_CFG_CLOCKS_OVERRIDE (0) -#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ -#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ -#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ -#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ -#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_24_0 /* PLL Mul x24.0 */ -#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ -#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL2 Div /3 */ -#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_24_0 /* PLL2 Mul x24.0 */ -#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ -#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ -#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ -#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ -#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ -#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ -#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ -#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ -#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ -#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ -#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_4) /* UCLK Div /4 */ - -#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_mcu_family_cfg.h deleted file mode 100644 index 4ecda1c66..000000000 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_mcu_family_cfg.h +++ /dev/null @@ -1,260 +0,0 @@ -/* generated configuration header file through renesas e2 studio */ -#ifndef BSP_MCU_FAMILY_CFG_H_ -#define BSP_MCU_FAMILY_CFG_H_ - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_info.h" - -#define BSP_CFG_MCU_PART_SERIES (4) -#define BSP_MCU_R7FA4M3AF3CFB -#define BSP_ROM_SIZE_BYTES (1048576) -#define BSP_RAM_SIZE_BYTES (131072) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (144) - -#define BSP_MCU_GROUP_RA4M3 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (16000000) -#elif BSP_CFG_HOCO_FREQUENCY == 1 -#define BSP_HOCO_HZ (18000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 -#define BSP_HOCO_HZ (20000000) -#else -#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" -#endif - -#define BSP_CFG_FLL_ENABLE (0) - -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) -#define BSP_MCU_VBATT_SUPPORT (1) - -#if defined(_RA_TZ_SECURE) -#define BSP_TZ_SECURE_BUILD (1) -#define BSP_TZ_NONSECURE_BUILD (0) -#elif defined(_RA_TZ_NONSECURE) -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (1) -#else -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (0) -#endif - -/* TrustZone Settings */ -#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) -#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) -#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) - -/* CMSIS TrustZone Settings */ -#define SCB_CSR_AIRCR_INIT (1) -#define SCB_AIRCR_BFHFNMINS_VAL (0) -#define SCB_AIRCR_SYSRESETREQS_VAL (1) -#define SCB_AIRCR_PRIS_VAL (0) -#define TZ_FPU_NS_USAGE (1) -#define SCB_NSACR_CP10_11_VAL (3U) - -#define FPU_FPCCR_TS_VAL (1U) -#define FPU_FPCCR_CLRONRETS_VAL (1) - -#define FPU_FPCCR_CLRONRET_VAL (1) - -/* The C-Cache line size that is configured during startup. */ -#define BSP_CFG_C_CACHE_LINE_SIZE (1U) - -/* Type 1 Peripheral Security Attribution */ - -/* Peripheral Security Attribution Register (PSAR) Settings */ -#define BSP_TZ_CFG_PSARB \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ - (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | 0x33f4f9) /* Unused */ -#define BSP_TZ_CFG_PSARC \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | 0x7fffcef4) /* Unused */ -#define BSP_TZ_CFG_PSARD \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ - 0xffae07f0) /* Unused */ -#define BSP_TZ_CFG_PSARE \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ - (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ - (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | 0x3f3ff8) /* Unused */ -#define BSP_TZ_CFG_MSSAR \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ - 0xfffffffc) /* Unused */ - -/* Type 2 Peripheral Security Attribution */ - -/* Security attribution for Cache registers. */ -#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) - -/* Security attribution for RSTSRn registers. */ -#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) - -/* Security attribution for registers of LVD channels. */ -#define BSP_TZ_CFG_LVDSAR \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ - 0xFFFFFFFCU) - -/* Security attribution for LPM registers. */ -#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) -/* Deep Standby Interrupt Factor Security Attribution Register. */ -#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) - -/* Security attribution for CGC registers. */ -#if BSP_CFG_CLOCKS_SECURE -/* Protect all CGC registers from Non-secure write access. */ -#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U) -#else -/* Allow Secure and Non-secure write access. */ -#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) -#endif - -/* Security attribution for Battery Backup registers. */ -#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) - -/* Security attribution for registers for IRQ channels. */ -#define BSP_TZ_CFG_ICUSARA \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ - (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | 0xFFFF0000U) - -/* Security attribution for NMI registers. */ -#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ - -/* Security attribution for registers for DMAC channels */ -#define BSP_TZ_CFG_ICUSARC \ - ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | 0xFFFFFF00U) - -/* Security attribution registers for SELSR0. */ -#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) - -/* Security attribution registers for WUPEN0. */ -#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) - -/* Security attribution registers for WUPEN1. */ -#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) - -/* Set DTCSTSAR if the Secure program uses the DTC. */ -// #if RA_NOT_DEFINED == RA_NOT_DEFINED -#define BSP_TZ_CFG_DTC_USED (0U) -// #else -// #define BSP_TZ_CFG_DTC_USED (1U) -// #endif - -/* Security attribution of FLWT and FCKMHZ registers. */ -/* If the CGC registers are only accessible in Secure mode, than there is no - * reason for nonsecure applications to access FLWT and FCKMHZ. */ -#if BSP_CFG_CLOCKS_SECURE -/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ -#define BSP_TZ_CFG_FSAR (0xFEFEU) -#else -/* Allow Secure and Non-secure write access. */ -#define BSP_TZ_CFG_FSAR (0xFFFFU) -#endif - -/* Security attribution for SRAM registers. */ -/* If the CGC registers are only accessible in Secure mode, than there is no - * reason for Non Secure applications to access - * SRAM0WTEN and therefore there is no reason to access PRCR2. */ -#define BSP_TZ_CFG_SRAMSAR (1 | ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | 4 | 0xFFFFFFF8U) - -/* Security attribution for Standby RAM registers. */ -#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) - -/* Security attribution for the DMAC Bus Master MPU settings. */ -/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. - */ -#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) - -/* Security Attribution Register A for BUS Control registers. */ -#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) -/* Security Attribution Register B for BUS Control registers. */ -#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) - -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) - -/* Option Function Select Register 1 Security Attribution */ -#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) -#define BSP_CFG_ROM_REG_OFS1_SEL \ - (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) -#else -#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) -#endif - -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) - -/* Used to create IELS values for the interrupt initialization table - * g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector) -/* Dual Mode Select Register */ -#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU) -/* Block Protection Register 0 */ -#define BSP_CFG_ROM_REG_BPS0 (~(0U)) -/* Block Protection Register 1 */ -#define BSP_CFG_ROM_REG_BPS1 (~(0U)) -/* Block Protection Register 2 */ -#define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU) -/* Permanent Block Protection Register 0 */ -#define BSP_CFG_ROM_REG_PBPS0 (~(0U)) -/* Permanent Block Protection Register 1 */ -#define BSP_CFG_ROM_REG_PBPS1 (~(0U)) -/* Permanent Block Protection Register 2 */ -#define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU) -/* Security Attribution for Block Protection Register 0 (If any blocks are - * marked as protected in the secure application, then mark them as secure) */ -#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) -/* Security Attribution for Block Protection Register 1 (If any blocks are - * marked as protected in the secure application, then mark them as secure) */ -#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) -/* Security Attribution for Block Protection Register 2 (If any blocks are - * marked as protected in the secure application, then mark them as secure) */ -#define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU) -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) - -#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.cmake b/hw/bsp/ra/boards/ra6m1_ek/board.cmake new file mode 100644 index 000000000..0d599b2da --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/board.cmake @@ -0,0 +1,13 @@ +set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(MCU_VARIANT ra6m1) + +set(JLINK_DEVICE R7FA6M1AD) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + ) + target_sources(${TARGET} PRIVATE + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ) +endfunction() diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index 57e05a4b1..cf7dfad55 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -49,6 +49,7 @@ function(add_board_target BOARD_TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/fsp_cfg + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/fsp_cfg/bsp ${CMSIS_DIR}/CMSIS/Core/Include ${FSP_RA}/inc ${FSP_RA}/inc/api diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index 6e90583e7..03125aac5 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -37,6 +37,7 @@ INC += \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(BOARD_PATH) \ $(TOP)/$(BOARD_PATH)/fsp_cfg \ + $(TOP)/$(BOARD_PATH)/fsp_cfg/bsp \ $(TOP)/$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Include \ $(TOP)/$(FSP_RA)/inc \ $(TOP)/$(FSP_RA)/inc/api \ -- cgit v1.3.1