From 73bf9aeaa6e1ffd453b7bffa4dd3818773e6a763 Mon Sep 17 00:00:00 2001 From: zhiqiang Date: Mon, 7 Jul 2025 14:13:15 +0800 Subject: support at32 mcu --- .../at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f402_405/at32f402_405_clock.c | 127 + hw/bsp/at32f402_405/at32f402_405_clock.h | 44 + hw/bsp/at32f402_405/at32f402_405_conf.h | 151 + hw/bsp/at32f402_405/at32f402_405_int.c | 140 + hw/bsp/at32f402_405/at32f402_405_int.h | 56 + .../boards/AT_START_F402_405/AT32F405xC_FLASH.ld | 154 + .../boards/AT_START_F402_405/AT32F405xx_v2.svd | 45983 +++++++++++++++ .../at32f402_405/boards/AT_START_F402_405/board.h | 169 + .../at32f402_405/boards/AT_START_F402_405/board.mk | 4 + hw/bsp/at32f402_405/family.c | 297 + hw/bsp/at32f402_405/family.mk | 45 + hw/bsp/at32f402_405/startup_at32f402_405.s | 486 + .../at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f403a_407/at32f403a_407_clock.c | 87 + hw/bsp/at32f403a_407/at32f403a_407_clock.h | 44 + hw/bsp/at32f403a_407/at32f403a_407_conf.h | 161 + hw/bsp/at32f403a_407/at32f403a_407_int.c | 117 + hw/bsp/at32f403a_407/at32f403a_407_int.h | 56 + .../boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld | 154 + .../boards/AT_START_F403A_407/AT32F407xx_v2.svd | 28047 +++++++++ .../boards/AT_START_F403A_407/board.h | 61 + .../boards/AT_START_F403A_407/board.mk | 4 + hw/bsp/at32f403a_407/family.c | 287 + hw/bsp/at32f403a_407/family.mk | 42 + hw/bsp/at32f403a_407/startup_at32f403a_407.s | 478 + hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f413/at32f413_clock.c | 94 + hw/bsp/at32f413/at32f413_clock.h | 44 + hw/bsp/at32f413/at32f413_conf.h | 157 + hw/bsp/at32f413/at32f413_int.c | 141 + hw/bsp/at32f413/at32f413_int.h | 56 + .../boards/AT_START_F413/AT32F413xC_FLASH.ld | 168 + .../boards/AT_START_F413/AT32F413xx_v2.svd | 23368 ++++++++ hw/bsp/at32f413/boards/AT_START_F413/board.h | 62 + hw/bsp/at32f413/boards/AT_START_F413/board.mk | 4 + hw/bsp/at32f413/family.c | 286 + hw/bsp/at32f413/family.mk | 42 + hw/bsp/at32f413/startup_at32f413.s | 431 + hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f415/at32f415_clock.c | 92 + hw/bsp/at32f415/at32f415_clock.h | 44 + hw/bsp/at32f415/at32f415_conf.h | 145 + hw/bsp/at32f415/at32f415_int.c | 119 + hw/bsp/at32f415/at32f415_int.h | 56 + .../boards/AT_START_F415/AT32F415xC_FLASH.ld | 154 + .../boards/AT_START_F415/AT32F415xx_v2.svd | 27108 +++++++++ hw/bsp/at32f415/boards/AT_START_F415/board.h | 80 + hw/bsp/at32f415/boards/AT_START_F415/board.mk | 4 + hw/bsp/at32f415/family.c | 287 + hw/bsp/at32f415/family.mk | 43 + hw/bsp/at32f415/startup_at32f415.s | 407 + hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f423/at32f423_clock.c | 128 + hw/bsp/at32f423/at32f423_clock.h | 44 + hw/bsp/at32f423/at32f423_conf.h | 153 + hw/bsp/at32f423/at32f423_int.c | 140 + hw/bsp/at32f423/at32f423_int.h | 56 + .../boards/AT_START_F423/AT32F423xC_FLASH.ld | 154 + .../boards/AT_START_F423/AT32F423xx_v2.svd | 36050 ++++++++++++ hw/bsp/at32f423/boards/AT_START_F423/board.h | 91 + hw/bsp/at32f423/boards/AT_START_F423/board.mk | 4 + hw/bsp/at32f423/family.c | 294 + hw/bsp/at32f423/family.mk | 44 + hw/bsp/at32f423/startup_at32f423.s | 483 + hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f425/at32f425_clock.c | 91 + hw/bsp/at32f425/at32f425_clock.h | 44 + hw/bsp/at32f425/at32f425_conf.h | 145 + hw/bsp/at32f425/at32f425_int.c | 140 + hw/bsp/at32f425/at32f425_int.h | 56 + .../boards/AT_START_F425/AT32F425x8_FLASH.ld | 153 + .../boards/AT_START_F425/AT32F425xx_v2.svd | 30790 ++++++++++ hw/bsp/at32f425/boards/AT_START_F425/board.h | 90 + hw/bsp/at32f425/boards/AT_START_F425/board.mk | 4 + hw/bsp/at32f425/family.c | 298 + hw/bsp/at32f425/family.mk | 43 + hw/bsp/at32f425/startup_at32f425.s | 309 + .../at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f435_437/at32f435_437_clock.c | 119 + hw/bsp/at32f435_437/at32f435_437_clock.h | 44 + hw/bsp/at32f435_437/at32f435_437_conf.h | 173 + hw/bsp/at32f435_437/at32f435_437_int.c | 120 + hw/bsp/at32f435_437/at32f435_437_int.h | 56 + .../boards/AT_START_F435_437/AT32F437xM_FLASH.ld | 154 + .../boards/AT_START_F435_437/AT32F437xx_v2.svd | 58291 +++++++++++++++++++ .../at32f435_437/boards/AT_START_F435_437/board.h | 182 + .../at32f435_437/boards/AT_START_F435_437/board.mk | 4 + hw/bsp/at32f435_437/family.c | 370 + hw/bsp/at32f435_437/family.mk | 45 + hw/bsp/at32f435_437/startup_at32f435_437.s | 569 + src/common/tusb_mcu.h | 38 + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 2 + src/portable/st/stm32_fsdev/fsdev_at32.h | 224 + src/portable/synopsys/dwc2/dwc2_at32.h | 135 + src/portable/synopsys/dwc2/dwc2_common.c | 14 +- src/portable/synopsys/dwc2/dwc2_common.h | 2 + src/tusb_option.h | 9 + tools/get_deps.py | 21 + 99 files changed, 262200 insertions(+), 1 deletion(-) create mode 100644 hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f402_405/at32f402_405_clock.c create mode 100644 hw/bsp/at32f402_405/at32f402_405_clock.h create mode 100644 hw/bsp/at32f402_405/at32f402_405_conf.h create mode 100644 hw/bsp/at32f402_405/at32f402_405_int.c create mode 100644 hw/bsp/at32f402_405/at32f402_405_int.h create mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xC_FLASH.ld create mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd create mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h create mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk create mode 100644 hw/bsp/at32f402_405/family.c create mode 100644 hw/bsp/at32f402_405/family.mk create mode 100644 hw/bsp/at32f402_405/startup_at32f402_405.s create mode 100644 hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f403a_407/at32f403a_407_clock.c create mode 100644 hw/bsp/at32f403a_407/at32f403a_407_clock.h create mode 100644 hw/bsp/at32f403a_407/at32f403a_407_conf.h create mode 100644 hw/bsp/at32f403a_407/at32f403a_407_int.c create mode 100644 hw/bsp/at32f403a_407/at32f403a_407_int.h create mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld create mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd create mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.h create mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk create mode 100644 hw/bsp/at32f403a_407/family.c create mode 100644 hw/bsp/at32f403a_407/family.mk create mode 100644 hw/bsp/at32f403a_407/startup_at32f403a_407.s create mode 100644 hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f413/at32f413_clock.c create mode 100644 hw/bsp/at32f413/at32f413_clock.h create mode 100644 hw/bsp/at32f413/at32f413_conf.h create mode 100644 hw/bsp/at32f413/at32f413_int.c create mode 100644 hw/bsp/at32f413/at32f413_int.h create mode 100644 hw/bsp/at32f413/boards/AT_START_F413/AT32F413xC_FLASH.ld create mode 100644 hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd create mode 100644 hw/bsp/at32f413/boards/AT_START_F413/board.h create mode 100644 hw/bsp/at32f413/boards/AT_START_F413/board.mk create mode 100644 hw/bsp/at32f413/family.c create mode 100644 hw/bsp/at32f413/family.mk create mode 100644 hw/bsp/at32f413/startup_at32f413.s create mode 100644 hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f415/at32f415_clock.c create mode 100644 hw/bsp/at32f415/at32f415_clock.h create mode 100644 hw/bsp/at32f415/at32f415_conf.h create mode 100644 hw/bsp/at32f415/at32f415_int.c create mode 100644 hw/bsp/at32f415/at32f415_int.h create mode 100644 hw/bsp/at32f415/boards/AT_START_F415/AT32F415xC_FLASH.ld create mode 100644 hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd create mode 100644 hw/bsp/at32f415/boards/AT_START_F415/board.h create mode 100644 hw/bsp/at32f415/boards/AT_START_F415/board.mk create mode 100644 hw/bsp/at32f415/family.c create mode 100644 hw/bsp/at32f415/family.mk create mode 100644 hw/bsp/at32f415/startup_at32f415.s create mode 100644 hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f423/at32f423_clock.c create mode 100644 hw/bsp/at32f423/at32f423_clock.h create mode 100644 hw/bsp/at32f423/at32f423_conf.h create mode 100644 hw/bsp/at32f423/at32f423_int.c create mode 100644 hw/bsp/at32f423/at32f423_int.h create mode 100644 hw/bsp/at32f423/boards/AT_START_F423/AT32F423xC_FLASH.ld create mode 100644 hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd create mode 100644 hw/bsp/at32f423/boards/AT_START_F423/board.h create mode 100644 hw/bsp/at32f423/boards/AT_START_F423/board.mk create mode 100644 hw/bsp/at32f423/family.c create mode 100644 hw/bsp/at32f423/family.mk create mode 100644 hw/bsp/at32f423/startup_at32f423.s create mode 100644 hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f425/at32f425_clock.c create mode 100644 hw/bsp/at32f425/at32f425_clock.h create mode 100644 hw/bsp/at32f425/at32f425_conf.h create mode 100644 hw/bsp/at32f425/at32f425_int.c create mode 100644 hw/bsp/at32f425/at32f425_int.h create mode 100644 hw/bsp/at32f425/boards/AT_START_F425/AT32F425x8_FLASH.ld create mode 100644 hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd create mode 100644 hw/bsp/at32f425/boards/AT_START_F425/board.h create mode 100644 hw/bsp/at32f425/boards/AT_START_F425/board.mk create mode 100644 hw/bsp/at32f425/family.c create mode 100644 hw/bsp/at32f425/family.mk create mode 100644 hw/bsp/at32f425/startup_at32f425.s create mode 100644 hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f435_437/at32f435_437_clock.c create mode 100644 hw/bsp/at32f435_437/at32f435_437_clock.h create mode 100644 hw/bsp/at32f435_437/at32f435_437_conf.h create mode 100644 hw/bsp/at32f435_437/at32f435_437_int.c create mode 100644 hw/bsp/at32f435_437/at32f435_437_int.h create mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xM_FLASH.ld create mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd create mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/board.h create mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk create mode 100644 hw/bsp/at32f435_437/family.c create mode 100644 hw/bsp/at32f435_437/family.mk create mode 100644 hw/bsp/at32f435_437/startup_at32f435_437.s create mode 100644 src/portable/st/stm32_fsdev/fsdev_at32.h create mode 100644 src/portable/synopsys/dwc2/dwc2_at32.h diff --git a/hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..d86c92542 --- /dev/null +++ b/hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f402_405.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd b/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd new file mode 100644 index 000000000..94a12b0f4 --- /dev/null +++ b/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd @@ -0,0 +1,45983 @@ + + + + + + + + Keil + ArteryTek + AT32F405xx_v2 + AT32F405 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 168MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Power control register + (PWC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + VRSEL + Voltage regulator state select when deepsleep mode + 0 + 1 + + + LPSEL + Low power mode select when Cortex-M4F sleepdeep + 1 + 1 + + + CLSWEF + Clear SWEF flag + 2 + 1 + + + CLSEF + Clear SEF flag + 3 + 1 + + + PVMEN + Power voltage monitoring enable + 4 + 1 + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + + + BPWEN + Battery powered domain write enable + 8 + 1 + + + + + CTRLSTS + CTRLSTS + Power control and status register + (PWC_CTRLSTS) + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN1 + Standby wake-up pin 1 enable + 8 + 1 + read-write + + + SWPEN2 + Standby wake-up pin 2 enable + 9 + 1 + read-write + + + SWPEN6 + Standby wake-up pin 6 enable + 13 + 1 + read-write + + + + + LDOOV + LDOOV + LDO output voltage register + 0x10 + 0x20 + 0x00000012 + + + LDOOVSEL + LDO output voltage select + 0 + 2 + read-write + + + VREXLPEN + Voltage regulator extra low power mode enable + 4 + 1 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40023800 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 5 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + PLLUSTBL + PLLU clock ready flag + 26 + 1 + read-only + + + + + PLLCFG + PLLCFG + PLL configuration register + (CRM_PLLCFG) + 0x4 + 0x20 + 0x00033002 + + + PLL_MS + PLL pre-division + 0 + 4 + read-write + + + PLL_NS + PLL frequency multiplication factor + 6 + 9 + read-write + + + PLL_FP + PLLP post-division + 16 + 4 + read-write + + + PLL_FU + PLLU post-division + 20 + 3 + read-write + + + PLLU_EN + PLLU enable + 29 + 1 + read-write + + + PLLRCS + PLL reference clock select + 30 + 1 + read-write + + + + + CFG + CFG + Clock configuration register(CRM_CFG) + 0x8 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 10 + 3 + read-write + + + APB2DIV + APB2 division + 13 + 3 + read-write + + + ERTCDIV + HEXT division for ERTC clock + 16 + 5 + read-write + + + I2S5CLKSEL + I2S clock select + 22 + 2 + read-write + + + CLKOUTDIV1 + Clock output division1 + 27 + 3 + read-write + + + CLKOUT_SEL1 + Clock output selection1 + 30 + 2 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + (CRM_CLKINT) + 0xC + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + AHBRST1 + AHBRST1 + AHB peripheral reset register1 + (CRM_AHBRST1) + 0x10 + 0x20 + read-write + 0x000000000 + + + GPIOARST + IO port A reset + 0 + 1 + + + GPIOBRST + IO port B reset + 1 + 1 + + + GPIOCRST + IO port C reset + 2 + 1 + + + GPIODRST + IO port D reset + 3 + 1 + + + GPIOFRST + IO port F reset + 5 + 1 + + + CRCRST + CRC reset + 12 + 1 + + + DMA1RST + DMA1 reset + 22 + 1 + + + DMA2RST + DMA2 reset + 24 + 1 + + + OTGHSRST + OTGHS interface reset + 29 + 1 + + + + + AHBRST2 + AHBRST2 + AHB peripheral reset register 2 + (CRM_AHBRST2) + 0x14 + 0x20 + read-write + 0x00000000 + + + OTGFS1RST + OTGFS1 reset + 7 + 1 + + + + + AHBRST3 + AHBRST3 + AHB peripheral reset register 3 + (CRM_AHBRST3) + 0x18 + 0x20 + read-write + 0x00000000 + + + QSPI1RST + QSPI1 reset + 1 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + (CRM_APB1RST) + 0x20 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer2 reset + 0 + 1 + + + TMR3RST + Timer3 reset + 1 + 1 + + + TMR4RST + Timer4 reset + 2 + 1 + + + TMR6RST + Timer6 reset + 4 + 1 + + + TMR7RST + Timer7 reset + 5 + 1 + + + TMR13RST + Timer13 reset + 7 + 1 + + + TMR14RST + Timer14 reset + 8 + 1 + + + WWDTRST + Window watchdog reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + USART2RST + USART2 reset + 17 + 1 + + + USART3RST + USART3 reset + 18 + 1 + + + USART4RST + USART4 reset + 19 + 1 + + + USART5RST + USART5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + PWCRST + PWC reset + 28 + 1 + + + UART7RST + UART7 reset + 30 + 1 + + + UART8RST + UART8 reset + 31 + 1 + + + + + APB2RST + APB2RST + APB2 peripheral reset register + (CRM_APB2RST) + 0x24 + 0x20 + read-write + 0x00000000 + + + TMR1RST + Timer1 reset + 0 + 1 + + + USART1RST + USART1 reset + 4 + 1 + + + USART6RST + USART6 reset + 5 + 1 + + + ADCRST + ADC reset + 8 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + SCFGRST + SCFG reset + 14 + 1 + + + TMR9RST + Timer9 reset + 16 + 1 + + + TMR10RST + Timer10 reset + 17 + 1 + + + TMR11RST + Timer 11 reset + 18 + 1 + + + I2S5RST + I2S5 reset + 20 + 1 + + + ACCRST + ACC reset + 29 + 1 + + + OTGHSPHYRST + OTGHS phy reset + 31 + 1 + + + + + AHBEN1 + AHBEN1 + AHB Peripheral Clock enable register 1 + (CRM_AHBEN1) + 0x30 + 0x20 + read-write + 0x00000000 + + + GPIOAEN + IO A clock enable + 0 + 1 + + + GPIOBEN + IO B clock enable + 1 + 1 + + + GPIOCEN + IO C clock enable + 2 + 1 + + + GPIODEN + IO D clock enable + 3 + 1 + + + GPIOFEN + IO F clock enable + 5 + 1 + + + CRCEN + CRC clock enable + 12 + 1 + + + DMA1EN + DMA1 clock enable + 22 + 1 + + + DMA2EN + DMA2 clock enable + 24 + 1 + + + OTGHSEN + OTGHS clock enable + 29 + 1 + + + + + AHBEN2 + AHBEN2 + AHB peripheral clock enable register 2 + (CRM_AHBEN2) + 0x34 + 0x20 + read-write + 0x00000000 + + + OTGFS1EN + OTGFS1 clock enable + 7 + 1 + + + + + AHBEN3 + AHBEN3 + AHB peripheral clock enable register 3 + (CRM_AHBEN3) + 0x38 + 0x20 + read-write + 0x00000000 + + + QSPI1EN + QSPI1 clock enable + 1 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + (CRM_APB1EN) + 0x40 + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR4EN + Timer4 clock enable + 2 + 1 + + + TMR6EN + Timer6 clock enable + 4 + 1 + + + TMR7EN + Timer7 clock enable + 5 + 1 + + + TMR13EN + Timer13 clock enable + 7 + 1 + + + TMR14EN + Timer14 clock enable + 8 + 1 + + + WWDTEN + WWDT clock enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + USART4EN + USART4 clock enable + 19 + 1 + + + USART5EN + USART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + PWCEN + PWC clock enable + 28 + 1 + + + UART7EN + UART7 clock enable + 30 + 1 + + + UART8EN + UART8 clock enable + 31 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + (CRM_APB2EN) + 0x44 + 0x20 + read-write + 0x00000000 + + + TMR1EN + Timer1 clock enable + 0 + 1 + + + USART1EN + USART1 clock enable + 4 + 1 + + + USART6EN + USART6 clock enable + 5 + 1 + + + ADC1EN + ADC1 clock enable + 8 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + SCFGEN + SCFG clock enable + 14 + 1 + + + TMR9EN + Timer9 clock enable + 16 + 1 + + + TMR10EN + Timer10 clock enable + 17 + 1 + + + TMR11EN + Timer11 clock enable + 18 + 1 + + + I2S5EN + I2S5 clock enable + 20 + 1 + + + ACCEN + ACC clock enable + 29 + 1 + + + + + AHBLPEN1 + AHBLPEN1 + AHB Low-power Peripheral Clock enable + register 1 (CRM_AHBLPEN1) + 0x50 + 0x20 + read-write + 0x3E6390FF + + + GPIOALPEN + IO A clock enable during sleep mode + 0 + 1 + + + GPIOBLPEN + IO B clock enable during sleep mode + 1 + 1 + + + GPIOCLPEN + IO C clock enable during sleep mode + 2 + 1 + + + GPIODLPEN + IO D clock enable during sleep mode + 3 + 1 + + + GPIOFLPEN + IO F clock enable during sleep mode + 5 + 1 + + + CRCLPEN + CRC clock enable during sleep mode + 12 + 1 + + + FLASHLPEN + Flash clock enable during sleep mode + 15 + 1 + + + SRAMLPEN + SRAM clock enable during sleep mode + 16 + 1 + + + DMA1LPEN + DMA1 clock enable during sleep mode + 22 + 1 + + + DMA2LPEN + DMA2 clock enable during sleep mode + 24 + 1 + + + OTGHSLPEN + OTGHS clock enable during sleep mode + 29 + 1 + + + + + AHBLPEN2 + AHBLPEN2 + AHB peripheral Low-power clock + enable register 2 (CRM_AHBLPEN2) + 0x54 + 0x20 + read-write + 0x00008081 + + + OTGFS1LPEN + OTGFS1 clock enable during sleep mode + 7 + 1 + + + + + AHBLPEN3 + AHBLPEN3 + AHB peripheral Low-power clock + enable register 3 (CRM_AHBLPEN3) + 0x58 + 0x20 + read-write + 0x0000C003 + + + QSPI1LPEN + QSPI1 clock enable during sleep mode + 1 + 1 + + + + + APB1LPEN + APB1LPEN + APB1 peripheral Low-power clock + enable register (CRM_APB1LPEN) + 0x60 + 0x20 + read-write + 0xF6FEE9FF + + + TMR2LPEN + Timer2 clock enable during sleep mode + 0 + 1 + + + TMR3LPEN + Timer3 clock enable during sleep mode + 1 + 1 + + + TMR4LPEN + Timer4 clock enable during sleep mode + 2 + 1 + + + TMR6LPEN + Timer6 clock enable during sleep mode + 4 + 1 + + + TMR7LPEN + Timer7 clock enable during sleep mode + 5 + 1 + + + TMR13LPEN + Timer13 clock enable during sleep mode + 7 + 1 + + + TMR14LPEN + Timer14 clock enable during sleep mode + 8 + 1 + + + WWDTLPEN + WWDT clock enable during sleep mode + 11 + 1 + + + SPI2LPEN + SPI2 clock enable during sleep mode + 14 + 1 + + + SPI3LPEN + SPI3 clock enable during sleep mode + 15 + 1 + + + USART2LPEN + USART2 clock enable during sleep mode + 17 + 1 + + + USART3LPEN + USART3 clock enable during sleep mode + 18 + 1 + + + USART4LPEN + USART4 clock enable during sleep mode + 19 + 1 + + + USART5LPEN + USART5 clock enable during sleep mode + 20 + 1 + + + I2C1CPEN + I2C1 clock enable during sleep mode + 21 + 1 + + + I2C2CPEN + I2C2 clock enable during sleep mode + 22 + 1 + + + I2C3CPEN + I2C3 clock enable during sleep mode + 23 + 1 + + + CAN1LPEN + CAN1 clock enable during sleep mode + 25 + 1 + + + PWCLPEN + PWC clock enable during sleep mode + 28 + 1 + + + UART7LPEN + UART7 clock enable during sleep mode + 30 + 1 + + + UART8LPEN + UART8 clock enable during sleep mode + 31 + 1 + + + + + APB2LPEN + APB2LPEN + APB2 peripheral Low-power clock + enable register (CRM_APB2LPEN) + 0x64 + 0x20 + read-write + 0x20177733 + + + TMR1LPEN + Timer1 clock enable during sleep mode + 0 + 1 + + + USART1LPEN + USART1 clock enable during sleep mode + 4 + 1 + + + USART6LPEN + USART6 clock enable during sleep mode + 5 + 1 + + + SPI1LPEN + SPI1 clock enable during sleep mode + 12 + 1 + + + SCFGLPEN + SCFG clock enable during sleep mode + 14 + 1 + + + TMR9LPEN + Timer9 clock enable during sleep mode + 16 + 1 + + + TMR10LPEN + Timer10 clock enable during sleep mode + 17 + 1 + + + TMR11LPEN + Timer11 clock enable during sleep mode + 18 + 1 + + + I2S5LPEN + I2S5 clock enable during sleep mode + 20 + 1 + + + ACCLPEN + ACC clock enable during sleep mode + 29 + 1 + + + OTGHSPHYLPEN + OTGHS phy clock enable during sleep mode + 31 + 1 + + + + + BPDC + BPDC + Battery powered domain control register + (CRM_BPDC) + 0x70 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + ERTCSEL + ERTC clock source selection + 8 + 2 + read-write + + + ERTCEN + ERTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + (CRM_CTRLSTS) + 0x74 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset reset flag + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + OTGHS + OTGHS + OTGHS register + 0x78 + 0x20 + 0x00000000 + + + XTLSEL + PHY clock source select + 0 + 1 + read-write + + + USBHS_PHY12_SEL + USBHS phy12 select value + 3 + 2 + read-write + + + USBHS_PHY30_SEL + USBHS phy12 select value + 8 + 2 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register1 + 0xA0 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + HICKDIV + HICK 6 divider selection + 12 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 14 + 1 + read-write + + + CLKOUT_SEL2 + Clock output select2 + 16 + 4 + read-write + + + CLKOUTDIV2 + Clock output division2 + 28 + 4 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register2 + 0xA4 + 0x20 + 0x0000000D + + + AUTO_STEP_EN + AUTO_STEP_EN + 4 + 2 + read-write + + + PLLU_USB48_SEL + USB clock source select + 10 + 1 + read-write + + + HICK_TO_SCLK_DIV + HICK as system clock frequency division + 16 + 3 + read-write + + + HEXT_TO_SCLK_DIV + HEXT as system clock frequency division + 19 + 3 + read-write + + + + + + + GPIOA + General purpose I/Os + GPIO + 0x40020000 + + 0x0 + 0x400 + registers + + + + CFGR + CFGR + GPIO configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + IOMC15 + GPIOx pin 15 mode configurate + 30 + 2 + + + IOMC14 + GPIOx pin 14 mode configurate + 28 + 2 + + + IOMC13 + GPIOx pin 13 mode configurate + 26 + 2 + + + IOMC12 + GPIOx pin 12 mode configurate + 24 + 2 + + + IOMC11 + GPIOx pin 11 mode configurate + 22 + 2 + + + IOMC10 + GPIOx pin 10 mode configurate + 20 + 2 + + + IOMC9 + GPIOx pin 9 mode configurate + 18 + 2 + + + IOMC8 + GPIOx pin 8 mode configurate + 16 + 2 + + + IOMC7 + GPIOx pin 7 mode configurate + 14 + 2 + + + IOMC6 + GPIOx pin 6 mode configurate + 12 + 2 + + + IOMC5 + GPIOx pin 5 mode configurate + 10 + 2 + + + IOMC4 + GPIOx pin 4 mode configurate + 8 + 2 + + + IOMC3 + GPIOx pin 3 mode configurate + 6 + 2 + + + IOMC2 + GPIOx pin 2 mode configurate + 4 + 2 + + + IOMC1 + GPIOx pin 1 mode configurate + 2 + 2 + + + IOMC0 + GPIOx pin 0 mode configurate + 0 + 2 + + + + + OMODE + OMODE + GPIO output mode register + 0x4 + 0x20 + read-write + 0x00000000 + + + OM15 + GPIOx pin 15 outpu mode configurate + 15 + 1 + + + OM14 + GPIOx pin 14 outpu mode configurate + 14 + 1 + + + OM13 + GPIOx pin 13 outpu mode configurate + 13 + 1 + + + OM12 + GPIOx pin 12 outpu mode configurate + 12 + 1 + + + OM11 + GPIOx pin 11 outpu mode configurate + 11 + 1 + + + OM10 + GPIOx pin 10 outpu mode configurate + 10 + 1 + + + OM9 + GPIOx pin 9 outpu mode configurate + 9 + 1 + + + OM8 + GPIOx pin 8 outpu mode configurate + 8 + 1 + + + OM7 + GPIOx pin 7 outpu mode configurate + 7 + 1 + + + OM6 + GPIOx pin 6 outpu mode configurate + 6 + 1 + + + OM5 + GPIOx pin 5 outpu mode configurate + 5 + 1 + + + OM4 + GPIOx pin 4 outpu mode configurate + 4 + 1 + + + OM3 + GPIOx pin 3 outpu mode configurate + 3 + 1 + + + OM2 + GPIOx pin 2 outpu mode configurate + 2 + 1 + + + OM1 + GPIOx pin 1 outpu mode configurate + 1 + 1 + + + OM0 + GPIOx pin 0 outpu mode configurate + 0 + 1 + + + + + ODRVR + ODRVR + GPIO drive capability register + 0x8 + 0x20 + read-write + 0x00000000 + + + ODRV15 + GPIOx pin 15 output drive capability + 30 + 2 + + + ODRV14 + GPIOx pin 14 output drive capability + 28 + 2 + + + ODRV13 + GPIOx pin 13 output drive capability + 26 + 2 + + + ODRV12 + GPIOx pin 12 output drive capability + 24 + 2 + + + ODRV11 + GPIOx pin 11 output drive capability + 22 + 2 + + + ODRV10 + GPIOx pin 10 output drive capability + 20 + 2 + + + ODRV9 + GPIOx pin 9 output drive capability + 18 + 2 + + + ODRV8 + GPIOx pin 8 output drive capability + 16 + 2 + + + ODRV7 + GPIOx pin 7 output drive capability + 14 + 2 + + + ODRV6 + GPIOx pin 6 output drive capability + 12 + 2 + + + ODRV5 + GPIOx pin 5 output drive capability + 10 + 2 + + + ODRV4 + GPIOx pin 4 output drive capability + 8 + 2 + + + ODRV3 + GPIOx pin 3 output drive capability + 6 + 2 + + + ODRV2 + GPIOx pin 2 output drive capability + 4 + 2 + + + ODRV1 + GPIOx pin 1 output drive capability + 2 + 2 + + + ODRV0 + GPIOx pin 0 output drive capability + 0 + 2 + + + + + PULL + PULL + GPIO pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PULL15 + GPIOx pin 15 pull configuration + 30 + 2 + + + PULL14 + GPIOx pin 14 pull configuration + 28 + 2 + + + PULL13 + GPIOx pin 13 pull configuration + 26 + 2 + + + PULL12 + GPIOx pin 12 pull configuration + 24 + 2 + + + PULL11 + GPIOx pin 11 pull configuration + 22 + 2 + + + PULL10 + GPIOx pin 10 pull configuration + 20 + 2 + + + PULL9 + GPIOx pin 9 pull configuration + 18 + 2 + + + PULL8 + GPIOx pin 8 pull configuration + 16 + 2 + + + PULL7 + GPIOx pin 7 pull configuration + 14 + 2 + + + PULL6 + GPIOx pin 6 pull configuration + 12 + 2 + + + PULL5 + GPIOx pin 5 pull configuration + 10 + 2 + + + PULL4 + GPIOx pin 4 pull configuration + 8 + 2 + + + PULL3 + GPIOx pin 3 pull configuration + 6 + 2 + + + PULL2 + GPIOx pin 2 pull configuration + 4 + 2 + + + PULL1 + GPIOx pin 1 pull configuration + 2 + 2 + + + PULL0 + GPIOx pin 0 pull configuration + 0 + 2 + + + + + IDT + IDT + GPIO input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + GPIO output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x18 + 0x20 + write-only + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + WPR + WPR + Port write protect + register + 0x1C + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + MUXL + MUXL + GPIO muxing function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + MUXL7 + GPIOx pin 7 muxing + 28 + 4 + + + MUXL6 + GPIOx pin 6 muxing + 24 + 4 + + + MUXL5 + GPIOx pin 5 muxing + 20 + 4 + + + MUXL4 + GPIOx pin 4 muxing + 16 + 4 + + + MUXL3 + GPIOx pin 3 muxing + 12 + 4 + + + MUXL2 + GPIOx pin 2 muxing + 8 + 4 + + + MUXL1 + GPIOx pin 1 muxing + 4 + 4 + + + MUXL0 + GPIOx pin 0 muxing + 0 + 4 + + + + + MUXH + MUXH + GPIO muxing function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + MUXH15 + GPIOx pin 15 muxing + 28 + 4 + + + MUXH14 + GPIOx pin 14 muxing + 24 + 4 + + + MUXH13 + GPIOx pin 13 muxing + 20 + 4 + + + MUXH12 + GPIOx pin 12 muxing + 16 + 4 + + + MUXH11 + GPIOx pin 11 muxing + 12 + 4 + + + MUXH10 + GPIOx pin 10 muxing + 8 + 4 + + + MUXH9 + GPIOx pin 9 muxing + 4 + 4 + + + MUXH8 + GPIOx pin 8 muxing + 0 + 4 + + + + + CLR + CLR + GPIO bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 1 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + TOGR + TOGR + GPIO bit toggle register + 0x2C + 0x20 + write-only + 0x00000000 + + + IOTB0 + toggle bit 0 + 0 + 1 + + + IOTB1 + toggle bit 1 + 1 + 1 + + + IOTB2 + toggle bit 2 + 2 + 1 + + + IOTB3 + toggle bit 3 + 3 + 1 + + + IOTB4 + toggle bit 4 + 4 + 1 + + + IOTB5 + toggle bit 5 + 5 + 1 + + + IOTB6 + toggle bit 6 + 6 + 1 + + + IOTB7 + toggle bit 7 + 7 + 1 + + + IOTB8 + toggle bit 8 + 8 + 1 + + + IOTB9 + toggle bit 9 + 9 + 1 + + + IOTB10 + toggle bit 10 + 10 + 1 + + + IOTB11 + toggle bit 11 + 11 + 1 + + + IOTB12 + toggle bit 12 + 12 + 1 + + + IOTB13 + toggle bit 13 + 13 + 1 + + + IOTB14 + toggle bit 14 + 14 + 1 + + + IOTB15 + toggle bit 15 + 15 + 1 + + + + + HDRV + HDRV + Huge current driver + 0x3C + 0x20 + read-write + 0x00000000 + + + HDRV0 + Port x driver bit y + 0 + 1 + + + HDRV1 + Port x driver bit y + 1 + 1 + + + HDRV2 + Port x driver bit y + 2 + 1 + + + HDRV3 + Port x driver bit y + 3 + 1 + + + HDRV4 + Port x driver bit y + 4 + 1 + + + HDRV5 + Port x driver bit y + 5 + 1 + + + HDRV6 + Port x driver bit y + 6 + 1 + + + HDRV7 + Port x driver bit y + 7 + 1 + + + HDRV8 + Port x driver bit y + 8 + 1 + + + HDRV9 + Port x driver bit y + 9 + 1 + + + HDRV10 + Port x driver bit y + 10 + 1 + + + HDRV11 + Port x driver bit y + 11 + 1 + + + HDRV12 + Port x driver bit y + 12 + 1 + + + HDRV13 + Port x driver bit y + 13 + 1 + + + HDRV14 + Port x driver bit y + 14 + 1 + + + HDRV15 + Port x driver bit y + 15 + 1 + + + + + + + GPIOB + 0x40020400 + + + GPIOC + 0x40020800 + + + GPIOD + 0x40020C00 + + + GPIOF + 0x40021400 + + + EXINT + EXINT + EXINT + 0x40013C00 + + 0x0 + 0x400 + registers + + + EXINT0 + EXINT Line0 interrupt + 6 + + + EXINT1 + EXINT Line1 interrupt + 7 + + + EXINT2 + EXINT Line2 interrupt + 8 + + + EXINT3 + EXINT Line3 interrupt + 9 + + + EXINT4 + EXINT Line4 interrupt + 10 + + + EXINT9_5 + EXINT Line[9:5] interrupts + 23 + + + EXINT15_10 + EXINT Line[15:10] interrupts + 40 + + + PVM + PVM interrupt connect to EXINT line16 + 1 + + + ERTCALARM + ERTC Alarm interrupt connect to EXINT line17 + 41 + + + OTGFS1_WKUP + OTGFS1_WKUP interrupt connect to EXINT line18 + 42 + + + OTGHS_WKUP + OTGHS_WKUP interrupt connect to EXINT line20 + 76 + + + TAMPER + Tamper interrupt connect to EXINT line21 + 2 + + + ERTC_WKUP + ERTC Global interrupt connect to EXINT line22 + 3 + + + + INTEN + INTEN + Interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + INTEN19 + Interrupt enable or disable on line 19 + 19 + 1 + + + INTEN20 + Interrupt enable or disable on line 20 + 20 + 1 + + + INTEN21 + Interrupt enable or disable on line 21 + 21 + 1 + + + INTEN22 + Interrupt enable or disable on line 22 + 22 + 1 + + + + + EVTEN + EVTEN + Event enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + EVTEN19 + Event enable or disable on line 19 + 19 + 1 + + + EVTEN20 + Event enable or disable on line 20 + 20 + 1 + + + EVTEN21 + Event enable or disable on line 21 + 21 + 1 + + + EVTEN22 + Event enable or disable on line 22 + 22 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + RP19 + Rising polarity configuration bit of line 19 + 19 + 1 + + + RP20 + Rising polarity configuration bit of line 20 + 20 + 1 + + + RP21 + Rising polarity configuration bit of line 21 + 21 + 1 + + + RP22 + Rising polarity configuration bit of line 22 + 22 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + FP19 + Falling polarity event configuration bit of line 19 + 19 + 1 + + + FP20 + Falling polarity event configuration bit of line 20 + 20 + 1 + + + FP21 + Falling polarity event configuration bit of line 21 + 21 + 1 + + + FP22 + Falling polarity event configuration bit of line 22 + 22 + 1 + + + + + SWTRG + SWTRG + Software triggle register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + SWT19 + Software triggle on line 19 + 19 + 1 + + + SWT20 + Software triggle on line 20 + 20 + 1 + + + SWT21 + Software triggle on line 21 + 21 + 1 + + + SWT22 + Software triggle on line 22 + 22 + 1 + + + + + INTSTS + INTSTS + Interrupt status register + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + LINE19 + Line 19 state bit + 19 + 1 + + + LINE20 + Line 20 state bit + 20 + 1 + + + LINE21 + Line 21 state bit + 21 + 1 + + + LINE22 + Line 22 state bit + 22 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40026000 + + 0x0 + 0x200 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 13 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 14 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 15 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 16 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 17 + + + + STS + STS + DMA interrupt status register + (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA interrupt flag clear register + (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register(DMA_C1CTRL) + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register (DMA_C2CTRL) + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register (DMA_C3CTRL) + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register (DMA_C4CTRL) + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register (DMA_C5CTRL) + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register(DMA_C6CTRL) + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register(DMA_C7CTRL) + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_MUXSEL + DMA_MUXSEL + DMAMUX Table Selection + 0x100 + 0x20 + 0x00000000 + + + TBL_SEL + Multiplexer Table Select + 0 + 1 + read-write + + + + + MUXC1CTRL + MUXC1CTRL + Channel 1 Configuration Register + 0x104 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC2CTRL + MUXC2CTRL + Channel 2 Configuration Register + 0x108 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC3CTRL + MUXC3CTRL + Channel 3 Configuration Register + 0x10C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC4CTRL + MUXC4CTRL + Channel 4 Configuration Register + 0x110 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC5CTRL + MUXC5CTRL + Channel 5 Configuration Register + 0x114 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC6CTRL + MUXC6CTRL + Channel 6 Configuration Register + 0x118 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC7CTRL + MUXC7CTRL + Channel 7 Configuration Register + 0x11C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXG1CTRL + MUXG1CTRL + Generator 1 Configuration Register + 0x120 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG2CTRL + MUXG2CTRL + Generator 2 Configuration Register + 0x124 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG3CTRL + MUXG3CTRL + Generator 3 Configuration Register + 0x128 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG4CTRL + MUXG4CTRL + Generator 4 Configuration Register + 0x12C + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXSYNCSTS + MUXSYNCSTS + Channel Interrupt Status Register + 0x130 + 0x20 + 0x00000000 + + + SYNCOVF1 + Synchronizaton overrun interrupt flag + 0 + 1 + read-only + + + SYNCOVF2 + Synchronizaton overrun interrupt flag + 1 + 1 + read-only + + + SYNCOVF3 + Synchronizaton overrun interrupt flag + 2 + 1 + read-only + + + SYNCOVF4 + Synchronizaton overrun interrupt flag + 3 + 1 + read-only + + + SYNCOVF5 + Synchronizaton overrun interrupt flag + 4 + 1 + read-only + + + SYNCOVF6 + Synchronizaton overrun interrupt flag + 5 + 1 + read-only + + + SYNCOVF7 + Synchronizaton overrun interrupt flag + 6 + 1 + read-only + + + + + MUXSYNCCLR + MUXSYNCCLR + Channel Interrupt Clear Flag Register + 0x134 + 0x20 + 0x00000000 + + + SYNCOVFC1 + Clear synchronizaton overrun interrupt flag + 0 + 1 + read-write + + + SYNCOVFC2 + Clear synchronizaton overrun interrupt flag + 1 + 1 + read-write + + + SYNCOVFC3 + Clear synchronizaton overrun interrupt flag + 2 + 1 + read-write + + + SYNCOVFC4 + Clear synchronizaton overrun interrupt flag + 3 + 1 + read-write + + + SYNCOVFC5 + Clear synchronizaton overrun interrupt flag + 4 + 1 + read-write + + + SYNCOVFC6 + Clear synchronizaton overrun interrupt flag + 5 + 1 + read-write + + + SYNCOVFC7 + Clear synchronizaton overrun interrupt flag + 6 + 1 + read-write + + + + + MUXGSTS + MUXGSTS + Generator Interrupt Status Register + 0x138 + 0x20 + 0x00000000 + + + TRGOVF1 + Trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVF2 + Trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVF3 + Trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVF4 + Trigger overrun interrupt flag + 3 + 1 + read-write + + + + + MUXGCLR + MUXGCLR + Generator Interrupt Clear Flag Register + 0x13C + 0x20 + 0x00000000 + + + TRGOVFC1 + Clear trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVFC2 + Clear trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVFC3 + Clear trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVFC4 + Clear trigger overrun interrupt flag + 3 + 1 + read-write + + + + + + + DMA2 + 0x40026400 + + + SDIO1 + Secure digital input/output + interface + SDIO + 0x4002C400 + + 0x0 + 0x400 + registers + + + SDIO1 + SDIO1 global interrupt + 49 + + + + PWRCTRL + PWRCTRL + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PS + Power switch + 0 + 2 + + + + + CLKCTRL + CLKCTRL + SD clock control register + (SDIO_CLKCTRL) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock division + 0 + 8 + + + CLKOEN + Clock output enable + 8 + 1 + + + PWRSVEN + Power saving mode enable + 9 + 1 + + + BYPSEN + Clock divider bypass enable + bit + 10 + 1 + + + BUSWS + Bus width selection + 11 + 2 + + + CLKEDS + SDIO_CK edge selection bit + 13 + 1 + + + HFCEN + Hardware flow control enable + 14 + 1 + + + CLKDIV98 + Clock divide factor bit9 and bit8 + 15 + 2 + + + + + ARGU + ARGU + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + ARGU + Command argument + 0 + 32 + + + + + CMDCTRL + CMDCTRL + SDIO command control register + (SDIO_CMDCTRL) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDIDX + CMDIDX + 0 + 6 + + + RSPWT + Wait for response + 6 + 2 + + + INTWT + CCSM wait for interrupt + 8 + 1 + + + PNDWT + CCSM wait for end of transfer + 9 + 1 + + + CCSMEN + Command channel state machine + 10 + 1 + + + IOSUSP + SD I/O suspend command + 11 + 1 + + + + + RSPCMD + RSPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RSPCMD + RSPCMD + 0 + 6 + + + + + RSP1 + RSP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTS1 + CARDSTATUS1 + 0 + 32 + + + + + RSP2 + RSP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS2 + 0 + 32 + + + + + RSP3 + RSP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS3 + 0 + 32 + + + + + RSP4 + RSP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS4 + 0 + 32 + + + + + DTTMR + DTTMR + Bits 31:0 = TIMEOUT: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Data timeout period + 0 + 32 + + + + + DTLEN + DTLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DTLEN + Data length value + 0 + 25 + + + + + DTCTRL + DTCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TFREN + DTEN + 0 + 1 + + + TFRDIR + DTDIR + 1 + 1 + + + TFRMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + BLKSIZE + DBLOCKSIZE + 4 + 4 + + + RDWTSTART + PWSTART + 8 + 1 + + + RDWTSTOP + PWSTOP + 9 + 1 + + + RDWTMODE + RWMOD + 10 + 1 + + + IOEN + SD I/O function enable + 11 + 1 + + + + + DTCNT + DTCNT + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + CNT + Data count value + 0 + 25 + + + + + STS + STS + SDIO status register + (SDIO_STA) + 0x34 + 0x20 + read-only + 0x00000000 + + + CMDFAIL + Command crc fail + 0 + 1 + + + DTFAIL + Data crc fail + 1 + 1 + + + CMDTIMEOUT + Command timeout + 2 + 1 + + + DTTIMEOUT + Data timeout + 3 + 1 + + + TXERRU + Tx under run error + 4 + 1 + + + RXERRO + Rx over run error + 5 + 1 + + + CMDRSPCMPL + Command response complete + 6 + 1 + + + CMDCMPL + Command sent + 7 + 1 + + + DTCMPL + Data sent + 8 + 1 + + + SBITERR + Start bit error + 9 + 1 + + + DTBLKCMPL + Data block sent + 10 + 1 + + + DOCMD + Command transfer in progress + 11 + 1 + + + DOTX + Data transmit in progress + 12 + 1 + + + DORX + Data receive in progress + 13 + 1 + + + TXBUFH + Tx buffer half empty + 14 + 1 + + + RXBUFH + Rx buffer half empty + 15 + 1 + + + TXBUFF + Tx buffer full + 16 + 1 + + + RXBUFF + Rx buffer full + 17 + 1 + + + TXBUFE + Tx buffer empty + 18 + 1 + + + RXBUFE + Rx buffer empty + 19 + 1 + + + TXBUF + Tx data vaild + 20 + 1 + + + RXBUF + Rx data vaild + 21 + 1 + + + IOIF + SD I/O interrupt + 22 + 1 + + + + + INTCLR + INTCLR + SDIO interrupt clear register + (SDIO_INTCLR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CMDFAIL + Command crc fail flag clear + 0 + 1 + + + DTFAIL + Data crc fail flag clear + 1 + 1 + + + CMDTIMEOUT + Command timeout flag clear + 2 + 1 + + + DTTIMEOUT + Data timeout flag clear + 3 + 1 + + + TXERRU + Tx under run error flag clear + 4 + 1 + + + RXERRU + Rx over run error flag clear + 5 + 1 + + + CMDRSPCMPL + Command response complete flag clear + 6 + 1 + + + CMDCMPL + Command sent flag clear + 7 + 1 + + + DTCMPL + Data sent flag clear + 8 + 1 + + + SBITERR + Start bit error flag clear + 9 + 1 + + + DTBLKCMPL + Data block sent clear + 10 + 1 + + + IOIF + SD I/O interrupt flag clear + 22 + 1 + + + + + INTEN + INTEN + SDIO mask register (SDIO_MASK) + 0x3C + 0x20 + read-write + 0x00000000 + + + CMDFAILIEN + Command crc fail interrupt enable + 0 + 1 + + + DTFAILIEN + Data crc fail interrupt enable + 1 + 1 + + + CMDTIMEOUTIEN + Command timeout interrupt enable + 2 + 1 + + + DTTIMEOUTIEN + Data timeout interrupt enable + 3 + 1 + + + TXERRUIEN + Tx under run interrupt enable + 4 + 1 + + + RXERRUIEN + Rx over run interrupt enable + 5 + 1 + + + CMDRSPCMPLIEN + Command response complete interrupt enable + 6 + 1 + + + CMDCMPLIEN + Command sent complete interrupt enable + 7 + 1 + + + DTCMPLIEN + Data sent complete interrupt enable + 8 + 1 + + + SBITERRIEN + Start bit error interrupt enable + 9 + 1 + + + DTBLKCMPLIEN + Data block sent complete interrupt enable + 10 + 1 + + + DOCMDIEN + Command acting interrupt enable + 11 + 1 + + + DOTXIEN + Data transmit acting interrupt enable + 12 + 1 + + + DORXIEN + Data receive acting interrupt enable + 13 + 1 + + + TXBUFHIEN + Tx buffer half empty interrupt enable + 14 + 1 + + + RXBUFHIEN + Rx buffer half empty interrupt enable + 15 + 1 + + + TXBUFFIEN + Tx buffer full interrupt enable + 16 + 1 + + + RXBUFFIEN + Rx buffer full interrupt enable + 17 + 1 + + + TXBUFEIEN + Tx buffer empty interrupt enable + 18 + 1 + + + RXBUFEIEN + Rx buffer empty interrupt enable + 19 + 1 + + + TXBUFIEN + Tx buffer data vaild interrupt enable + 20 + 1 + + + RXBUFIEN + Rx buffer data vaild interrupt enable + 21 + 1 + + + IOIFIEN + SD I/O interrupt enable + 22 + 1 + + + + + BUFCNT + BUFCNT + Bits 23:0 = BUFCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + FIF0COUNT + 0 + 24 + + + + + BUF + BUF + bits 31:0 = Buffer Data: Receive and transmit + buffer data + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Buffer data + 0 + 32 + + + + + + + SDIO2 + 0x50061000 + + SDIO2 + SDIO2 global interrupt + 102 + + + + ERTC + Real-time clock + ERTC + 0x40002800 + + 0x0 + 0x400 + registers + + + + TIME + TIME + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + AMPM + AM/PM notation + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + DATE + DATE + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens + 20 + 4 + + + YU + Year units + 16 + 4 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + CTRL + CTRL + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + CALOEN + Calibration output enable + 23 + 1 + + + OUTSEL + Output source selection + 21 + 2 + + + OUTP + Output polarity + 20 + 1 + + + CALOSEL + Calibration output selection + 19 + 1 + + + BPR + Battery power domain data register + 18 + 1 + + + DEC1H + Decrease 1 hour + 17 + 1 + + + ADD1H + Add 1 hour + 16 + 1 + + + TSIEN + Timestamp interrupt enable + 15 + 1 + + + WATIEN + Wakeup timer interrupt enable + 14 + 1 + + + ALBIEN + Alarm B interrupt enable + 13 + 1 + + + ALAIEN + Alarm A interrupt enable + 12 + 1 + + + TSEN + Timestamp enable + 11 + 1 + + + WATEN + Wakeup timer enable + 10 + 1 + + + ALBEN + Alarm B enable + 9 + 1 + + + ALAEN + Alarm A enable + 8 + 1 + + + CCALEN + Coarse calibration enable + 7 + 1 + + + HM + Hour mode + 6 + 1 + + + DREN + Date/time register direct read enable + 5 + 1 + + + RCDEN + Reference clock detection enable + 4 + 1 + + + TSEDG + Timestamp trigger edge + 3 + 1 + + + WATCLK + Wakeup timer clock selection + 0 + 3 + + + + + STS + STS + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALAWF + Alarm A register allows write flag + 0 + 1 + read-only + + + ALBWF + Alarm B register allows write flag + 1 + 1 + read-only + + + WATWF + Wakeup timer register allows write flag + 2 + 1 + read-only + + + TADJF + Time adjustment flag + 3 + 1 + read-write + + + INITF + Calendar initialization flag + 4 + 1 + read-only + + + UPDF + Calendar update flag + 5 + 1 + read-write + + + IMF + Enter initialization mode flag + 6 + 1 + read-only + + + IMEN + Initialization mode enable + 7 + 1 + read-write + + + ALAF + Alarm A flag + 8 + 1 + read-write + + + ALBF + Alarm B flag + 9 + 1 + read-write + + + WATF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Timestamp flag + 11 + 1 + read-write + + + TSOF + Timestamp overflow flag + 12 + 1 + read-write + + + TP1F + Tamper detection 1 flag + 13 + 1 + read-write + + + TP2F + Tamper detection 2 flag + 14 + 1 + read-write + + + CALUPDF + Calibration value update completed flag + 16 + 1 + read-only + + + + + DIV + DIV + Diveder register + 0x10 + 0x20 + read-write + 0x007F00FF + + + DIVA + Diveder A + 16 + 7 + + + DIVB + Diveder B + 0 + 15 + + + + + WAT + WAT + Wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + VAL + Wakeup timer reload value + 0 + 16 + + + + + CCAL + CCAL + Calibration register + 0x18 + 0x20 + read-write + 0x00000000 + + + CALDIR + Calibration direction + 7 + 1 + + + CALVAL + Calibration value + 0 + 5 + + + + + ALA + ALA + Alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + ALB + ALB + Alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + 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register + 0x0 + 0x20 + 0x0000 + + + RSLOST + Reference Signal Lost + read-write + 1 + 1 + + + CALRDY + Internal high-speed clock calibration ready + read-write + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x04 + 0x20 + 0x0100 + + + STEP + STEP + read-write + 8 + 4 + + + CALRDYIEN + CALRDY interrupt enable + read-write + 5 + 1 + + + EIEN + RSLOST error interrupt enable + read-write + 4 + 1 + + + SOFSEL + SOF Select + read-write + 2 + 1 + + + ENTRIM + Enable trim + read-write + 1 + 1 + + + CALON + Calibration on + read-write + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x08 + 0x20 + 0x2080 + + + HICKTWK + Internal high-speed auto clock trimming + read-only + 8 + 6 + + + HICKCAL + Internal high-speed auto clock calibration + read-only + 0 + 8 + + + + + C1 + C1 + compare value 1 + 0x0C + 0x20 + 0x1F2C + + + C1 + Compare 1 + read-write + 0 + 16 + + + + + C2 + C2 + compare value 2 + 0x10 + 0x20 + 0x1F40 + + + C2 + Compare 2 + read-write + 0 + 16 + + + + + C3 + C3 + compare value 3 + 0x14 + 0x20 + 0x1F54 + + + C3 + Compare 3 + read-write + 0 + 16 + + + + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EVT + I2C1 event interrupt + 31 + + + I2C1_ERR + I2C1 error interrupt + 32 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + 0x00000000 + + + I2CEN + I2C peripheral enable + 0 + 1 + read-write + + + TDIEN + Transmit data interrupt enable + 1 + 1 + read-write + + + RDIEN + Receive data interrupt enable + 2 + 1 + read-write + + + ADDRIEN + Address match interrupt enable + 3 + 1 + read-write + + + ACKFAILIEN + Acknowledge fail interrupt enable + 4 + 1 + read-write + + + STOPIEN + Stop generation complete interrupt enable + 5 + 1 + read-write + + + TDCIEN + Transfer data complete interrupt enable + 6 + 1 + read-write + + + ERRIEN + Error interrupts enable + 7 + 1 + read-write + + + DFLT + Digital filter value + 8 + 4 + read-write + + + DMATEN + DMA Transmit data request enable + 14 + 1 + read-write + + + DMAREN + DMA receive data request enable + 15 + 1 + read-write + + + SCTRL + Slave receiving data control + 16 + 1 + read-write + + + STRETCH + Clock stretching mode + 17 + 1 + read-write + + + GCAEN + General call address enable + 19 + 1 + read-write + + + HADDREN + SMBus host address enable + 20 + 1 + read-write + + + DEVADDREN + SMBus device default address enable + 21 + 1 + read-write + + + SMBALERT + SMBus alert enable / pin set + 22 + 1 + read-write + + + PECEN + PEC calculation enable + 23 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECTEN + Request PEC transmission enable + 26 + 1 + + + ASTOPEN + Automatically send stop condition enable + 25 + 1 + + + RLDEN + Send data reload mode enable + 24 + 1 + + + CNT + Transmit data counter + 16 + 8 + + + NACKEN + Not acknowledge enable + 15 + 1 + + + GENSTOP + Generate stop condition + 14 + 1 + + + GENSTART + Generate start condition + 13 + 1 + + + READH10 + 10-bit address header read enable + 12 + 1 + + + ADDR10 + Host send 10-bit address mode enable + 11 + 1 + + + DIR + Master data transmission direction + 10 + 1 + + + SADDR + Slave address + 0 + 10 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + ADDR1 + Interface address + 0 + 10 + + + ADDR1MODE + Own Address mode + 10 + 1 + + + ADDR1EN + Own address 1 enable + 15 + 1 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2MASK + Own address 2-bit mask + 8 + 3 + + + ADDR2EN + Own address 2 enable + 15 + 1 + + + + + CLKCTRL + CLKCTRL + Clock contorl register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low level + 0 + 8 + + + SCLH + SCL high level + 8 + 8 + + + SDAD + SDA output delay + 16 + 4 + + + SCLD + SCL output delay + 20 + 4 + + + DIVH + High 4 bits of clock divider value + 24 + 4 + + + DIVL + Low 4 bits of clock divider value + 28 + 4 + + + + + TIMEOUT + TIMEOUT + Timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + TOTIME + Clock timeout detection time + 0 + 12 + + + TOMOED + Clock timeout detection mode + 12 + 1 + + + TOEN + Detect clock low/high timeout enable + 15 + 1 + + + EXTTIME + Cumulative clock low extend timeout value + 16 + 12 + + + EXTEN + Cumulative clock low extend timeout enable + 31 + 1 + + + + + STS + STS + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDR + Slave address matching value + 17 + 7 + read-only + + + SDIR + Slave data transmit direction + 16 + 1 + read-only + + + BUSYF + Bus busy + 15 + 1 + read-only + + + ALERTF + SMBus alert flag + 13 + 1 + read-only + + + TMOUT + SMBus timeout flag + 12 + 1 + read-only + + + PECERR + PEC receive error flag + 11 + 1 + read-only + + + OUF + Overflow or underflow flag + 10 + 1 + read-only + + + ARLOST + Arbitration lost flag + 9 + 1 + read-only + + + BUSERR + Bus error flag + 8 + 1 + read-only + + + TCRLD + Transmission is complete, waiting to load data + 7 + 1 + read-only + + + TDC + Transmit data complete flag + 6 + 1 + read-only + + + STOPF + Stop condition generation complete flag + 5 + 1 + read-only + + + ACKFAIL + Acknowledge failure flag + 4 + 1 + read-only + + + ADDRF + 0~7 bit address match flag + 3 + 1 + read-only + + + RDBF + Receive data buffer full flag + 2 + 1 + read-only + + + TDIS + Send interrupt status + 1 + 1 + read-write + + + TDBE + Transmit data buffer empty flag + 0 + 1 + read-write + + + + + CLR + CLR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTC + Clear SMBus alert flag + 13 + 1 + + + TMOUTC + Clear SMBus timeout flag + 12 + 1 + + + PECERRC + Clear PEC receive error flag + 11 + 1 + + + OUFC + Clear overload / underload flag + 10 + 1 + + + ARLOSTC + Clear arbitration lost flag + 9 + 1 + + + BUSERRC + Clear bus error flag + 8 + 1 + + + STOPC + Clear stop condition generation complete flag + 5 + 1 + + + ACKFAILC + Clear acknowledge failure flag + 4 + 1 + + + ADDRC + Clear 0~7 bit address match flag + 3 + 1 + + + + + PEC + PEC + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PECVAL + PEC value + 0 + 8 + + + + + RXDT + RXDT + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + DT + Receive data register + 0 + 8 + + + + + TXDT + TXDT + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + DT + Transmit data register + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 33 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + I2C3 + 0x40005C00 + + I2C3_EVT + I2C3 event interrupt + 72 + + + I2C3_ERR + I2C3 error interrupt + 73 + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3EN + Master clock frequency3 division enable + 9 + 1 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + TIEN + TI mode enable + 4 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + CSPAS + CS pulse abnormal setting fiag + 8 + 1 + read-write + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + I2SF5 + Serial peripheral interface + SPI + 0x40015000 + + 0x0 + 0x400 + registers + + + I2SF5 + I2SF5 global interrupt + 85 + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + CSPAS + CS pulse abnormal setting fiag + 8 + 1 + read-write + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SFDUPEN + I2S full duplex mode enable + 13 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + MISC1 + MISC1 + MISC1 register + 0x30 + 0x20 + read-write + 00000000 + + + I2SFPCMCKSEL + I2S PCM clock edge select + 0 + 1 + + + + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40011000 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CMDF + Character match detection flag + 17 + 1 + read-write + + + RTODF + Reiceiver time out detection flag + 11 + 1 + read-write + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + DBN1 + high bit for Data bit num + 28 + 1 + + + RTODEN + Receiver time out detection enable + 27 + 1 + + + RETODIE + Receiver time out detection interrupt enable + 26 + 1 + + + TSDT + transmit start delay time + 21 + 5 + + + TCDT + transmit complete delay time + 16 + 5 + + + CMDIE + Character match detection interrupt enable + 14 + 1 + + + UEN + USART enable + 13 + 1 + + + DBN0 + low bit for Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + IDH + bit 7-4 for usart identification + 28 + 4 + + + MTF + MSB transmit first + 19 + 1 + + + DTREV + DT register polarity reverse + 18 + 1 + + + TXREV + TX polarity reverse + 17 + 1 + + + RXREV + RX polarity reverse + 16 + 1 + + + TRPSWAP + Transmit receive pin swap + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + IDBN + Identification bit num + 4 + 1 + + + IDL + bit 3-0 for usart identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + DEP + DE polarity selection + 15 + 1 + + + RS485EN + RS485 enable + 14 + 1 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + RTOV + RTOV + Receiver time out value register + 0x1C + 0x20 + read-write + 0x0000 + + + RTOV + Receiver time out value + 0 + 24 + + + + + IFC + IFC + Interruption flag clear register + 0x20 + 0x20 + read-write + 0x0000 + + + CMDFC + Character match detection flag clear + 17 + 1 + + + RTODFC + Receiver time out detection flag clear + 11 + 1 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + USART4 + 0x40004C00 + + USART4 + USART4 global interrupt + 52 + + + + USART5 + 0x40005000 + + USART5 + USART5 global interrupt + 53 + + + + USART6 + 0x40011400 + + USART6 + USART6 global interrupt + 71 + + + + UART7 + Universal asynchronous receiver transmitter + 0x40007800 + + UART7 + UART7 global interrupt + 82 + + + + UART8 + Universal asynchronous receiver transmitter + 0x40007C00 + + UART8 + UART8 global interrupt + 83 + + + + ADC1 + Analog to digital converter + ADC + 0x40012000 + + 0x0 + 0x100 + registers + + + ADC + ADC1 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + + + + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + + 20 + 1 + + + OCTESEL + Low bit of trigger event select for ordinary channels conversion + + 17 + 3 + + + PCTEN + + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + OCDMAEN + DMA transfer enable of ordinary channels + 8 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + OVSP + OVSP + oversampling register + 0x80 + 0x20 + read-write + 0x00000000 + + + OOSRSEL + Ordinary oversampling recovery mode select + 10 + 1 + + + OOSTREN + Ordinary oversampling trigger mode enable + 9 + 1 + + + OSSSEL + Oversampling shift select + 5 + 4 + + + OSRSEL + Oversampling ratio select + 2 + 3 + + + POSEN + Preempted oversampling enable + 1 + 1 + + + OOSEN + Ordinary oversampling enable + 0 + 1 + + + + + + + ADCCOM + ADC common area + ADC + 0x40012300 + + 0x0 + 0x100 + registers + + + + CCTRL + CCTRL + Common control register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADCDIV + ADC division + 16 + 4 + + + + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1_TX + CAN1 TX interrupt + 19 + + + CAN1_RX0 + CAN1 RX0 interrupt + 20 + + + CAN_RX1 + CAN1 RX1 interrupt + 21 + + + CAN_SE + CAN1 SE interrupt + 22 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RF0R + Receive FIFO 0 release + 5 + 1 + read-write + + + RF0OF + Receive FIFO 0 overflow flag + 4 + 1 + read-write + + + RF0FF + Receive FIFO 0 full flag + 3 + 1 + read-write + + + RF0MN + Receive FIFO 0 message num + 0 + 2 + read-only + + + + + RF1 + RF1 + Receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RF1R + Receive FIFO 1 release + 5 + 1 + read-write + + + RF1OF + Receive FIFO 1 overflow flag + 4 + 1 + read-write + + + RF1FF + Receive FIFO 1 full flag + 3 + 1 + read-write + + + RF1MN + Receive FIFO 1 message num + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + EDZIEN + Enter doze mode interrupt enable + 17 + 1 + + + QDZIEN + Quit doze mode interrupt enable + 16 + 1 + + + EOIEN + Error occur interrupt enable + 15 + 1 + + + ETRIEN + Error type record interrupt enable + 11 + 1 + + + BOIEN + Bus-off interrupt enable + 10 + 1 + + + EPIEN + Error passive interrupt enable + 9 + 1 + + + EAIEN + Error active interrupt enable + 8 + 1 + + + RF1OIEN + Receive FIFO 1 overflow interrupt enable + 6 + 1 + + + RF1FIEN + Receive FIFO 1 full interrupt enable + 5 + 1 + + + RF1MIEN + FIFO 1 receive message interrupt enable + 4 + 1 + + + RF0OIEN + Receive FIFO 0 overflow interrupt enable + 3 + 1 + + + RF0FIEN + Receive FIFO 0 full interrupt enable + 2 + 1 + + + RF0MIEN + FIFO 0 receive message interrupt enable + 1 + 1 + + + TCIEN + Transmission complete interrupt enable + 0 + 1 + + + + + ESTS + ESTS + Error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Transmit error counter + 16 + 8 + read-only + + + ETR + Error type record + 4 + 3 + read-write + + + BOF + Bus-off flag + 2 + 1 + read-only + + + EPF + Error passive flag + 1 + 1 + read-only + + + EAF + Error active flag + 0 + 1 + read-only + + + + + BTMG + BTMG + Bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOEN + Listen-Only mode + 31 + 1 + + + LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit 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Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter 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flag interrupt enable + 12 + 1 + + + + + ADDR2 + ADDR2 + Address 2 register + 0x54 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + CONTR + CONTR + Flash continue read register + 0x58 + 0x20 + read-write + 0x00000080 + + + FCONTR_EN + Flash continue read enable + 31 + 1 + + + + + DIVR + DIVR + Flash divider register + 0x60 + 0x20 + 0x00000022 + + + FDIV + Flash divider + 0 + 2 + read-write + + + FDIV_STS + Flash divider status + 4 + 2 + read-only + + + + + SLIB_STS2 + SLIB_STS2 + sLib status 2 register + 0xC8 + 0x20 + 0x0000FFFF + + + SLIB_INST_SS + sLib instruction start sector + 0 + 16 + read-only + + + + + SLIB_STS0 + SLIB_STS0 + sLib status 0 register + 0xCC + 0x20 + 0x00000000 + + + SLIB_ENF + sLib enabled flag + 3 + 1 + read-only + + + + + SLIB_STS1 + SLIB_STS1 + sLib status 1 register + 0xD0 + 0x20 + 0xFFFFFFFF + + + SLIB_SS + sLib start sector + 0 + 16 + read-only + + + SLIB_ES + sLib end sector + 16 + 16 + read-only + + + + + SLIB_PWD_CLR + SLIB_PWD_CLR + SLIB password clear register + 0xD4 + 0x20 + 0x00000000 + write-only + + + SLIB_PCLR_VAL + sLib password clear value + 0 + 32 + + + + + SLIB_MISC_STS + SLIB_MISC_STS + sLib misc status register + 0xD8 + 0x20 + 0x01000000 + + + SLIB_PWD_ERR + sLib password error + 0 + 1 + read-only + + + SLIB_PWD_OK + sLib password ok + 1 + 1 + read-only + + + SLIB_ULKF + sLib unlock flag + 2 + 1 + read-only + + + SLIB_RCNT + sLib remaining count + 16 + 9 + read-only + + + + + SLIB_SET_PWD + SLIB_SET_PWD + sLib password setting register + 0xDC + 0x20 + 0x00000000 + write-only + + + SLIB_PSET_VAL + sLib password setting val + 0 + 32 + + + + + SLIB_SET_RANGE0 + SLIB_SET_RANGE0 + Configure sLib range register 0 + 0xE0 + 0x20 + 0x00000000 + write-only + + + SLIB_SS_SET + sLib start sector setting + 0 + 16 + + + SLIB_ES_SET + sLib end sector setting + 16 + 16 + + + + + SLIB_SET_RANGE1 + SLIB_SET_RANGE1 + Configure sLib range register 1 + 0xE4 + 0x20 + 0x00000000 + write-only + + + SLIB_ISS_SET + sLib instruction start sector setting + 0 + 16 + + + SET_SLIB_STRT + sLib start setting + 31 + 1 + + + + + SLIB_UNLOCK + SLIB_UNLOCK + sLib unlock register + 0xF0 + 0x20 + 0x00000000 + write-only + + + SLIB_UKVAL + sLib unlock key value + 0 + 32 + + + + + CRC_CTRL + CRC_CTRL + CRC controler register + 0xF4 + 0x20 + 0x00000000 + write-only + + + CRC_SS + CRC start sector + 0 + 12 + + + CRC_SN + CRC sector numbler + 12 + 12 + + + CRC_STRT + CRC start + 31 + 1 + + + + + CRC_CHKR + CRC_CHKR + CRC check result register + 0xF8 + 0x20 + 0x00000000 + read-only + + + CRC_CHKR + CRC check result + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + DVP + Digital video parallel interface + DVP + 0x50050000 + + 0x0 + 0x400 + registers + + + DVP + DVP global interrupt + 78 + + + + CTRL + CTRL + Control register + 0x0 + 0x20 + 0x0000 + + + LCDS + Line capture/drop selection + 20 + 1 + read-write + + + LCDC + Line capture/drop control + + 19 + 1 + read-write + + + PCDS + Pixel capture/drop selection + + 18 + 1 + read-write + + + PCDC + Basic pixel capture/drop control + + 16 + 2 + read-write + + + ENA + DVP enable + 14 + 1 + read-write + + + PDL + Pixel data length + 10 + 2 + read-write + + + BFRC + Basic frame rate control + 8 + 2 + read-write + + + VSP + Vertical synchronization + polarity + 7 + 1 + read-write + + + HSP + Horizontal synchronization polarity + + 6 + 1 + read-write + + + CKP + Pixel clock polarity + 5 + 1 + read-write + + + SM + synchronization mode + 4 + 1 + read-write + + + JPEG + JPEG format + 3 + 1 + read-write + + + CRP + Cropping function enable + 2 + 1 + read-write + + + CFM + Capture fire mode + 1 + 1 + read-write + + + CAP + Capture function enable + 0 + 1 + read-write + + + + + STS + STS + status register + 0x4 + 0x20 + read-only + 0x0000 + + + OFNE + Output FIFO Non-empty + 2 + 1 + + + VSYN + Vertical synchronization status + 1 + 1 + + + HSYN + Horizontal synchronization status + 0 + 1 + + + + + ESTS + ESTS + Event status register + 0x8 + 0x20 + read-only + 0x0000 + + + HSES + Horizontal synchronization event status + 4 + 1 + + + VSES + Vertical synchronization event status + 3 + 1 + + + ESEES + Embedded synchronization error event status + + 2 + 1 + + + OVRES + Data FIFO overrun event status + + 1 + 1 + + + CFDES + Capture frame done event status + + 0 + 1 + + + + + IENA + IENA + interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + HSIE + Horizontal synchronization interrupt enable + + 4 + 1 + + + VSIE + Vertical synchronization interrupt enablee + + 3 + 1 + + + ESEIE + Embedded synchronization error interrupt + enable + 2 + 1 + + + OVRIE + Data FIFO overrun interrupt enable + + 1 + 1 + + + CFDIE + Capture frame done interrupt enable + + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-only + 0x0000 + + + HSIS + Horizontal synchronization interrupt + status + 4 + 1 + + + VSIS + Vertical synchronization interrupt + status + 3 + 1 + + + ESEIS + Embedded synchronization error + interrupt status + 2 + 1 + + + OVRIS + Data FIFO overrun interrupt + status + 1 + 1 + + + CFDIS + Capture frame done interrupt + status + 0 + 1 + + + + + ICLR + ICLR + Interrupt clear register + 0x14 + 0x20 + write-only + 0x0000 + + + HSIC + Horizontal synchronization + interrupt clear + 4 + 1 + + + VSIC + Vertical synchronization + interrupt clear + 3 + 1 + + + ESEIC + Embedded synchronization + error interrupt clear + 2 + 1 + + + OVRIC + Data FIFO overrun + interrupt clear + 1 + 1 + + + CFDIC + Capture frame done + interrupt clear + 0 + 1 + + + + + SCR + SCR + Synchronization code + register + 0x18 + 0x20 + read-write + 0x0000 + + + FMEC + Frame end code + 24 + 8 + + + LNEC + Line end code + 16 + 8 + + + LNSC + Line start code + 8 + 8 + + + FMSC + Frame start code + 0 + 8 + + + + + SUR + SUR + Synchronization unmask + register + 0x1C + 0x20 + read-write + 0x0000 + + + FMEU + Frame end unmask + 24 + 8 + + + LNEU + Line end unmask + 16 + 8 + + + LNSU + Line start unmask + + 8 + 8 + + + FMSU + Frame start unmask + + 0 + 8 + + + + + CWST + CWST + Crop window start + 0x20 + 0x20 + read-write + 0x0000 + + + CVSTR + Cropping window vertical start line + + 16 + 13 + + + CHSTR + Cropping window horizontal start pixel + + 0 + 14 + + + + + CWSZ + CWSZ + Crop window size + 0x24 + 0x20 + read-write + 0x0000 + + + CVNUM + Cropping window vertical line number + + 16 + 14 + + + CHNUM + Cropping window horizontal pixel number + + 0 + 14 + + + + + DT + DT + Data register + 0x28 + 0x20 + read-only + 0x0000 + + + DT + Data Port + 0 + 32 + + + + + ACTRL + ACTRL + Advanced Control register + + 0x40 + 0x20 + read-write + 0x0000 + + + VSEID + Vertical synchonization event and interrupt + definition + 17 + 1 + + + HSEID + Horizontal synchonization event and interrupt + definition + 16 + 1 + + + DMABT + DMA burst transfer configuration + + 12 + 1 + + + IDUS + Input data un-used setting + + 10 + 1 + + + IDUN + Input data un-used number + + 8 + 2 + + + EFDM + Enhanced function data format management + + 6 + 1 + + + EFDF + Enhanced function data format + + 4 + 2 + + + PCDES + Basic pixel capture/drop extended + selection + 3 + 1 + + + MIBE + Monochrome image binarization + enable + 2 + 1 + + + EFRCE + Enhanced frame rate control + enable + 1 + 1 + + + EISRE + Enhanced image scaling resize + enable + 0 + 1 + + + + + HSCF + HSCF + Horizontal scaling control flow + + 0x48 + 0x20 + read-write + 0x0000 + + + HSRTF + Horizontal scaling resize target factor + + 16 + 13 + + + HSRSF + Horizontal scaling resize source factor + + 0 + 13 + + + + + VSCF + VSCF + Vertical scaling control flow + + 0x4C + 0x20 + read-write + 0x0000 + + + VSRTF + Vertical scaling resize target factor + + 16 + 13 + + + VSRSF + Vertical scaling resize source factor + + 0 + 13 + + + + + FRF + FRF + Frame rate flow + + 0x50 + 0x20 + read-write + 0x0000 + + + EFRCTF + Enhanced frame rate control target factor + + 8 + 5 + + + EFRCSF + Enhanced frame rate contorl source factor + + 0 + 5 + + + + + BTH + BTH + Binarization threshold + + 0x54 + 0x20 + read-write + 0x0000 + + + MIBTHD + Monochrome image binarization threshold + + 0 + 8 + + + + + + + USB_OTGFS_GLOBAL + USB on-the-go full speed + USB_OTGFS + 0x50000000 + + 0x0 + 0x400 + registers + + + OTGFS + USB On The Go FS global + interrupt + 67 + + + + GOTGCTL + GOTGCTL + OTGFS control and status register + (OTGFS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGFS interrupt register + (OTGFS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGFS AHB configuration register + (OTGFS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGFS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + FS timeout calibration + 0 + 3 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGFS reset register + (OTGFS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGFS core interrupt register + (OTGFS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-write + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGFS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGFS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGFS Receive FIFO size register + (OTGFS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGFS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGFS non-periodic transmit FIFO/queue + status register (OTGFS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGFS general core configuration register + (OTGFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + LP_MODE + Low power mode + 17 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGFS Host periodic transmit FIFO size + register (OTGFS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO5 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF6) + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO6 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF7) + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO7 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTG1_HOST + USB on the go full speed + USB_OTGFS + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGFS host configuration register + (OTGFS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGFS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGFS host frame number/frame time + remaining register (OTGFS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGFS_Host periodic transmit FIFO/queue + status register (OTGFS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGFS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGFS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGFS host port control and status register + (OTGFS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGFS host channel-0 characteristics + register (OTGFS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGFS host channel-1 characteristics + register (OTGFS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGFS host channel-2 characteristics + register (OTGFS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGFS host channel-3 characteristics + register (OTGFS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGFS host channel-4 characteristics + register (OTGFS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGFS host channel-5 characteristics + register (OTGFS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGFS host channel-6 characteristics + register (OTGFS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTGFS host channel-8 characteristics + register (OTGFS_HCCHAR8) + 0x200 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTGFS host channel-9 characteristics + register (OTGFS_HCCHAR9) + 0x220 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTGFS host channel-10 characteristics + register (OTGFS_HCCHAR10) + 0x240 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR11) + 0x260 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTGFS host channel-12 characteristics + register (OTGFS_HCCHAR12) + 0x280 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTGFS host channel-13 characteristics + register (OTGFS_HCCHAR13) + 0x2A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTGFS host channel-14 characteristics + register (OTGFS_HCCHAR14) + 0x2C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTGFS host channel-15 characteristics + register (OTGFS_HCCHAR15) + 0x2E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGFS host channel-0 interrupt register + (OTGFS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGFS host channel-2 interrupt register + (OTGFS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGFS host channel-3 interrupt register + (OTGFS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGFS host channel-4 interrupt register + (OTGFS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGFS host channel-5 interrupt register + (OTGFS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGFS host channel-6 interrupt register + (OTGFS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGFS host channel-7 interrupt register + (OTGFS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT8 + HCINT8 + OTGFS host channel-8 interrupt register + (OTGFS_HCINT8) + 0x208 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT9 + HCINT9 + OTGFS host channel-9 interrupt register + (OTGFS_HCINT9) + 0x228 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT10 + HCINT10 + OTGFS host channel-10 interrupt register + (OTGFS_HCINT10) + 0x248 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT11 + HCINT11 + OTGFS host channel-11 interrupt register + (OTGFS_HCINT11) + 0x268 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT12 + HCINT12 + OTGFS host channel-12 interrupt register + (OTGFS_HCINT12) + 0x288 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT13 + HCINT13 + OTGFS host channel-13 interrupt register + (OTGFS_HCINT13) + 0x2A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT14 + HCINT14 + OTGFS host channel-14 interrupt register + (OTGFS_HCINT14) + 0x2C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT15 + HCINT15 + OTGFS host channel-15 interrupt register + (OTGFS_HCINT15) + 0x2E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGFS host channel-0 mask register + (OTGFS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGFS host channel-1 mask register + (OTGFS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGFS host channel-2 mask register + (OTGFS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGFS host channel-3 mask register + (OTGFS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGFS host channel-4 mask register + (OTGFS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGFS host channel-5 mask register + (OTGFS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGFS host channel-6 mask register + (OTGFS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGFS host channel-7 mask register + (OTGFS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + OTGFS host channel-8 mask register + (OTGFS_HCINTMSK8) + 0x20C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + OTGFS host channel-9 mask register + (OTGFS_HCINTMSK9) + 0x22C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + OTGFS host channel-10 mask register + (OTGFS_HCINTMSK10) + 0x24C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + OTGFS host channel-11 mask register + (OTGFS_HCINTMSK11) + 0x26C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + OTGFS host channel-12 mask register + (OTGFS_HCINTMSK12) + 0x28C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + OTGFS host channel-13 mask register + (OTGFS_HCINTMSK13) + 0x2AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + OTGFS host channel-14 mask register + (OTGFS_HCINTMSK14) + 0x2CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + OTGFS host channel-15 mask register + (OTGFS_HCINTMSK15) + 0x2EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGFS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ1 + HCTSIZ1 + OTGFS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ2 + HCTSIZ2 + OTGFS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ3 + HCTSIZ3 + OTGFS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ4 + HCTSIZ4 + OTGFS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ5 + HCTSIZ5 + OTGFS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ6 + HCTSIZ6 + OTGFS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ7 + HCTSIZ7 + OTGFS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ8 + HCTSIZ8 + OTGFS host channel-8 transfer size + register + 0x210 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ9 + HCTSIZ9 + OTGFS host channel-9 transfer size + register + 0x230 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ10 + HCTSIZ10 + OTGFS host channel-10 transfer size + register + 0x250 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ11 + HCTSIZ11 + OTGFS host channel-11 transfer size + register + 0x270 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ12 + HCTSIZ12 + OTGFS host channel-12 transfer size + register + 0x290 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ13 + HCTSIZ13 + OTGFS host channel-13 transfer size + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ14 + HCTSIZ14 + OTGFS host channel-14 transfer size + register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ15 + HCTSIZ15 + OTGFS host channel-15 transfer size + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + + + USB_OTG1_DEVICE + USB on the go full speed + USB_OTGFS + 0x50000800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGFS device configuration register + (OTGFS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGFS device control register + (OTGFS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTGFS device IN endpoint common interrupt + mask register (OTGFS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTGFS device OUT endpoint common interrupt + mask register (OTGFS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + + + DAINT + DAINT + OTGFS device all endpoints interrupt + register (OTGFS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGFS all endpoints interrupt mask register + (OTGFS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGFS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEPCTL0 + DIEPCTL0 + OTGFS device control IN endpoint 0 control + register (OTGFS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-only + + + EPTENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTGFS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGFS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGFS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL4 + DIEPCTL4 + OTGFS device IN endpoint-4 control + register + 0x180 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL5 + DIEPCTL5 + OTGFS device IN endpoint-5 control + register + 0x1A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL6 + DIEPCTL6 + OTGFS device IN endpoint-6 control + register + 0x1C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL7 + DIEPCTL7 + OTGFS device IN endpoint-7 control + register + 0x1E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGFS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGFS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGFS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGFS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL4 + DOEPCTL4 + OTGFS device OUT endpoint-4 control + register + 0x380 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL5 + DOEPCTL5 + OTGFS device OUT endpoint-5 control + register + 0x3A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL6 + DOEPCTL6 + OTGFS device OUT endpoint-6 control + register + 0x3C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL7 + DOEPCTL7 + OTGFS device OUT endpoint-7 control + register + 0x3E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGFS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT1 + DIEPINT1 + OTGFS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT2 + DIEPINT2 + OTGFS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT3 + DIEPINT3 + OTGFS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT4 + DIEPINT4 + OTGFS device IN endpoint-4 interrupt + register + 0x188 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT5 + DIEPINT5 + OTGFS device IN endpoint-5 interrupt + register + 0x1A8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT6 + DIEPINT6 + OTGFS device IN endpoint-6 interrupt + register + 0x1C8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT7 + DIEPINT7 + OTGFS device IN endpoint-7 interrupt + register + 0x1E8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DOEPINT0 + DOEPINT0 + OTGFS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT1 + DOEPINT1 + OTGFS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT2 + DOEPINT2 + OTGFS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT3 + DOEPINT3 + OTGFS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT4 + DOEPINT4 + OTGFS device OUT endpoint-4 interrupt + register + 0x388 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT5 + DOEPINT5 + OTGFS device OUT endpoint-5 interrupt + register + 0x3A8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT6 + DOEPINT6 + OTGFS device OUT endpoint-6 interrupt + register + 0x3C8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT7 + DOEPINT7 + OTGFS device OUT endpoint-7 interrupt + register + 0x3E8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGFS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGFS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGFS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGFS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ4 + DIEPTSIZ4 + OTG device IN endpoint-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ5 + DIEPTSIZ5 + OTG device IN endpoint-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ6 + DIEPTSIZ6 + OTG device IN endpoint-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ7 + DIEPTSIZ7 + OTG device IN endpoint-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + OTGFS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGFS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGFS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGFS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS4 + DTXFSTS4 + OTGFS device IN endpoint-4 transmit FIFO + status register + 0x198 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS5 + DTXFSTS5 + OTGFS device IN endpoint-5 transmit FIFO + status register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS6 + DTXFSTS6 + OTGFS device IN endpoint-6 transmit FIFO + status register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS7 + DTXFSTS7 + OTGFS device IN endpoint-7 transmit FIFO + status register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGFS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGFS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGFS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + OTGFS device OUT endpoint-4 transfer size + register + 0x390 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + OTGFS device OUT endpoint-5 transfer size + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + OTGFS device OUT endpoint-6 transfer size + register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + OTGFS device OUT endpoint-7 transfer size + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + + + USB_OTG1_PWRCLK + USB on the go full speed + USB_OTGFS + 0x50000E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGFS power and clock gating control + register (OTGFS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + USB_OTGHS_GLOBAL + USB on the go high speed + USB_OTGHS + 0x40040000 + + 0x0 + 0x400 + registers + + + OTGHS + USB On The Go HS global + interrupt + 77 + + + + GOTGCTL + GOTGCTL + OTGHS control and status register + (OTGHS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGHS interrupt register + (OTGHS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGHS AHB configuration register + (OTGHS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + HBSTLEN + Burst Length + 1 + 4 + + + DMAEN + DMA Enable + 5 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGHS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + HS timeout calibration + 0 + 3 + read-write + + + PHYIF + PHY Interface + 3 + 1 + read-write + + + PHYSEL + USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial + Transceiver Select + 6 + 1 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGHS reset register + (OTGHS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + DMAREQ + DMA Request Signal + 30 + 1 + read-only + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGHS core interrupt register + (OTGHS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTGHS interrupt mask register + (OTGHS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-only + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGHS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGHS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGHS Receive FIFO size register + (OTGHS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGHS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGHS non-periodic transmit FIFO/queue + status register (OTGHS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGHS general core configuration register + (OTGHS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + WAIT_CLK_RCV + Wait Clock Soure Recover + 22 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGHS Host periodic transmit FIFO size + register (OTGHS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO5 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF6) + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO6 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF7) + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO7 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTGHS_HOST + USB on the go high speed + USB_OTGHS + 0x40040400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGHS host configuration register + (OTGHS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGHS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGHS host frame number/frame time + remaining register (OTGHS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGHS_Host periodic transmit FIFO/queue + status register (OTGHS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-only + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGHS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGHS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGHS host port control and status register + (OTGHS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGHS host channel-0 characteristics + register (OTGHS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGHS host channel-1 characteristics + register (OTGHS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGHS host channel-2 characteristics + register (OTGHS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGHS host channel-3 characteristics + register (OTGHS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGHS host channel-4 characteristics + register (OTGHS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGHS host channel-5 characteristics + register (OTGHS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGHS host channel-6 characteristics + register (OTGHS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGHS host channel-7 characteristics + register (OTGHS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTGHS host channel-8 characteristics + register (OTGHS_HCCHAR8) + 0x200 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTGHS host channel-9 characteristics + register (OTGHS_HCCHAR9) + 0x220 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTGHS host channel-10 characteristics + register (OTGHS_HCCHAR10) + 0x240 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTGHS host channel-7 characteristics + register (OTGHS_HCCHAR11) + 0x260 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTGHS host channel-12 characteristics + register (OTGHS_HCCHAR12) + 0x280 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTGHS host channel-13 characteristics + register (OTGHS_HCCHAR13) + 0x2A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTGHS host channel-14 characteristics + register (OTGHS_HCCHAR14) + 0x2C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTGHS host channel-15 characteristics + register (OTGHS_HCCHAR15) + 0x2E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCSPLT0 + HCSPLT0 + Host Channel 0 Split Control Register + 0x104 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT1 + HCSPLT1 + Host Channel 1 Split Control Register + 0x124 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT2 + HCSPLT2 + Host Channel 2 Split Control Register + 0x144 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT3 + HCSPLT3 + Host Channel 3 Split Control Register + 0x164 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT4 + HCSPLT4 + Host Channel 1 Split Control Register + 0x184 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT5 + HCSPLT5 + Host Channel 5 Split Control Register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT6 + HCSPLT6 + Host Channel 6 Split Control Register + 0x1C4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT7 + HCSPLT7 + Host Channel 7 Split Control Register + 0x1E4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT8 + HCSPLT8 + Host Channel 8 Split Control Register + 0x204 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT9 + HCSPLT9 + Host Channel 9 Split Control Register + 0x224 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT10 + HCSPLT10 + Host Channel 10 Split Control Register + 0x244 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT11 + HCSPLT11 + Host Channel 11 Split Control Register + 0x264 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT12 + HCSPLT12 + Host Channel 12 Split Control Register + 0x284 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT13 + HCSPLT13 + Host Channel 13 Split Control Register + 0x2A4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT14 + HCSPLT14 + Host Channel 14 Split Control Register + 0x2C4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT15 + HCSPLT15 + Host Channel 15 Split Control Register + 0x2E4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGHS host channel-0 interrupt register + (OTGHS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTGHS host channel-1 interrupt register + (OTGHS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGHS host channel-2 interrupt register + (OTGHS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGHS host channel-3 interrupt register + (OTGHS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGHS host channel-4 interrupt register + (OTGHS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGHS host channel-5 interrupt register + (OTGHS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGHS host channel-6 interrupt register + (OTGHS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGHS host channel-7 interrupt register + (OTGHS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT8 + HCINT8 + OTGHS host channel-8 interrupt register + (OTGHS_HCINT8) + 0x208 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT9 + HCINT9 + OTGHS host channel-9 interrupt register + (OTGHS_HCINT9) + 0x228 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT10 + HCINT10 + OTGHS host channel-10 interrupt register + (OTGHS_HCINT10) + 0x248 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT11 + HCINT11 + OTGHS host channel-11 interrupt register + (OTGHS_HCINT11) + 0x268 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT12 + HCINT12 + OTGHS host channel-12 interrupt register + (OTGHS_HCINT12) + 0x288 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT13 + HCINT13 + OTGHS host channel-13 interrupt register + (OTGHS_HCINT13) + 0x2A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT14 + HCINT14 + OTGHS host channel-14 interrupt register + (OTGHS_HCINT14) + 0x2C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT15 + HCINT15 + OTGHS host channel-15 interrupt register + (OTGHS_HCINT15) + 0x2E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGHS host channel-0 mask register + (OTGHS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGHS host channel-1 mask register + (OTGHS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGHS host channel-2 mask register + (OTGHS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGHS host channel-3 mask register + (OTGHS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGHS host channel-4 mask register + (OTGHS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGHS host channel-5 mask register + (OTGHS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGHS host channel-6 mask register + (OTGHS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGHS host channel-7 mask register + (OTGHS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + OTGHS host channel-8 mask register + (OTGHS_HCINTMSK8) + 0x20C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + OTGHS host channel-9 mask register + (OTGHS_HCINTMSK9) + 0x22C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + OTGHS host channel-10 mask register + (OTGHS_HCINTMSK10) + 0x24C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + OTGHS host channel-11 mask register + (OTGHS_HCINTMSK11) + 0x26C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + OTGHS host channel-12 mask register + (OTGHS_HCINTMSK12) + 0x28C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + OTGHS host channel-13 mask register + (OTGHS_HCINTMSK13) + 0x2AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + OTGHS host channel-14 mask register + (OTGHS_HCINTMSK14) + 0x2CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + OTGHS host channel-15 mask register + (OTGHS_HCINTMSK15) + 0x2EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGHS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ1 + HCTSIZ1 + OTGHS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ2 + HCTSIZ2 + OTGHS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ3 + HCTSIZ3 + OTGHS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ4 + HCTSIZ4 + OTGHS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ5 + HCTSIZ5 + OTGHS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ6 + HCTSIZ6 + OTGHS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ7 + HCTSIZ7 + OTGHS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ8 + HCTSIZ8 + OTGHS host channel-8 transfer size + register + 0x210 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ9 + HCTSIZ9 + OTGHS host channel-9 transfer size + register + 0x230 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ10 + HCTSIZ10 + OTGHS host channel-10 transfer size + register + 0x250 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ11 + HCTSIZ11 + OTGHS host channel-11 transfer size + register + 0x270 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ12 + HCTSIZ12 + OTGHS host channel-12 transfer size + register + 0x290 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ13 + HCTSIZ13 + OTGHS host channel-13 transfer size + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ14 + HCTSIZ14 + OTGHS host channel-14 transfer size + register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ15 + HCTSIZ15 + OTGHS host channel-15 transfer size + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCDMA0 + HCDMA0 + Host channel 0 DMA address + register + 0x114 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA1 + HCDMA1 + Host channel 1 DMA address + register + 0x134 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA2 + HCDMA2 + Host channel 2 DMA address + register + 0x154 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA3 + HCDMA3 + Host channel 3 DMA address + register + 0x174 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA4 + HCDMA4 + Host channel 4 DMA address + register + 0x194 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA5 + HCDMA5 + Host channel 5 DMA address + register + 0x1B4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA6 + HCDMA6 + Host channel 6 DMA address + register + 0x1D4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA7 + HCDMA7 + Host channel 7 DMA address + register + 0x1F4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA8 + HCDMA8 + Host channel 8 DMA address + register + 0x214 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA9 + HCDMA9 + Host channel 9 DMA address + register + 0x234 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA10 + HCDMA10 + Host channel 10 DMA address + register + 0x254 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA11 + HCDMA11 + Host channel 11 DMA address + register + 0x274 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA12 + HCDMA12 + Host channel 12 DMA address + register + 0x294 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA13 + HCDMA13 + Host channel 13 DMA address + register + 0x2B4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA14 + HCDMA14 + Host channel 14 DMA address + register + 0x2D4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA15 + HCDMA15 + Host channel 15 DMA address + register + 0x2F4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + + + USB_OTGHS_DEVICE + USB on the go high speed + USB_OTGHS + 0x40040800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGHS device configuration register + (OTGHS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGHS device control register + (OTGHS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + DEVLNSTS + Device Line Status + 22 + 2 + + + + + DIEPMSK + DIEPMSK + OTGHS device IN endpoint common interrupt + mask register (OTGHS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + AHBERRMSK + AHB Error + mask + 2 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + NAKMSK + NAK interrupt + mask + 13 + 1 + + + + + DOEPMSK + DOEPMSK + OTGHS device OUT endpoint common interrupt + mask register (OTGHS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + AHBERRMSK + AHB Error + mask + 2 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + STSPHSERCVDMSK + Status Phase Received + mask + 5 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + BBLEERRMSK + Babble Error interrupt + mask + 12 + 1 + + + NAKMSK + NAK interrupt + mask + 13 + 1 + + + NYETMSK + NYET interrupt + mask + 14 + 1 + + + + + DAINT + DAINT + OTGHS device all endpoints interrupt + register (OTGHS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGHS all endpoints interrupt mask register + (OTGHS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGHS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DEACHINT + DEACHINT + ODevice Each Endpoints + Interrupt Register + 0x38 + 0x20 + read-write + 0x00000000 + + + ECHINEPINT + Each IN Endpoint Interrupt + bits + 0 + 16 + + + ECHOUTEPINT + Each OUT Endpoint Interrupt + bits + 16 + 16 + + + + + DEACHINTMSK + DEACHINTMSK + Device Each Endpoints + Interrupt Mask Register + 0x3C + 0x20 + read-write + 0x00000000 + + + ECHINEPINTMSK + Each IN Endpoint Interrupt Mask + bits + 0 + 16 + + + ECHOUTEPINTMSK + Each OUT Endpoint Interrupt Mask + bits + 16 + 16 + + + + + DIEPEACHMSK1 + DIEPEACHMSK1 + Device Each IN Endpoint 1 Interrupt Register + 0x44 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + AHBERRMSK + AHB Error + mask + 2 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + NAKMSK + NAK interrupt + mask + 13 + 1 + + + + + DOEPEACHMSK1 + DOEPEACHMSK1 + Device Each OUT Endpoint 1 Interrupt Register + 0x84 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + AHBERRMSK + AHB Error + mask + 2 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + STSPHSERCVDMSK + Status Phase Received + mask + 5 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + BBLEERRMSK + Babble Error interrupt + mask + 12 + 1 + + + NAKMSK + NAK interrupt + mask + 13 + 1 + + + NYETMSK + NYET interrupt + mask + 14 + 1 + + + + + DIEPCTL0 + DIEPCTL0 + OTGHS device control IN endpoint 0 control + register (OTGHS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL1 + DIEPCTL1 + OTGHS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGHS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGHS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL4 + DIEPCTL4 + OTGHS device IN endpoint-4 control + register + 0x180 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL5 + DIEPCTL5 + OTGHS device IN endpoint-5 control + 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interrupt + 13 + 1 + read-write + + + NYETINTPT + NYET interrupt + 14 + 1 + read-write + + + STUPPKTRCVD + Setup Packet Received + 15 + 1 + read-write + + + + + DOEPINT7 + DOEPINT7 + OTGHS device OUT endpoint-7 interrupt + register + 0x3E8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + OUTPKTERR + OUT Packet Error + 8 + 1 + + + BNAINTR + Buffer Not Available Error + 9 + 1 + + + PKTDRPSTS + Packet Drop Status + 11 + 1 + read-write + + + BBLEERR + BBLE error + 12 + 1 + read-write + + + NAKINTPT + NAK interrupt + 13 + 1 + read-write + + + NYETINTPT + NYET interrupt + 14 + 1 + read-write + + + STUPPKTRCVD + Setup Packet Received + 15 + 1 + read-write + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGHS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGHS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGHS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGHS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ4 + DIEPTSIZ4 + OTG device IN endpoint-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ5 + DIEPTSIZ5 + OTG device IN endpoint-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ6 + DIEPTSIZ6 + OTG device IN endpoint-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ7 + DIEPTSIZ7 + OTG device IN endpoint-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPDMA0 + DIEPDMA0 + Device IN Endpoint 0 DMA Address + register + 0x114 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA1 + DIEPDMA1 + Device IN Endpoint 1 DMA Address + register + 0x134 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA2 + DIEPDMA2 + Device IN Endpoint 2 DMA Address + register + 0x154 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA3 + DIEPDMA3 + Device IN Endpoint 3 DMA Address + register + 0x174 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA4 + DIEPDMA4 + Device IN Endpoint 4 DMA Address + register + 0x194 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA5 + DIEPDMA5 + Device IN Endpoint 5 DMA Address + register + 0x1B4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA6 + DIEPDMA6 + Device IN Endpoint 6 DMA Address + register + 0x1D4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA7 + DIEPDMA7 + Device IN Endpoint 7 DMA Address + register + 0x1F4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DTXFSTS0 + DTXFSTS0 + OTGHS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGHS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGHS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGHS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS4 + DTXFSTS4 + OTGHS device IN endpoint-4 transmit FIFO + status register + 0x198 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS5 + DTXFSTS5 + OTGHS device IN endpoint-5 transmit FIFO + status register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS6 + DTXFSTS6 + OTGHS device IN endpoint-6 transmit FIFO + status register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS7 + DTXFSTS7 + OTGHS device IN endpoint-7 transmit FIFO + status register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGHS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGHS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGHS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + OTGHS device OUT endpoint-4 transfer size + register + 0x390 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + OTGHS device OUT endpoint-5 transfer size + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + OTGHS device OUT endpoint-6 transfer size + register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + OTGHS device OUT endpoint-7 transfer size + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPDMA0 + DOEPDMA0 + Device OUT Endpoint 0 DMA Address + register + 0x314 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA1 + DOEPDMA1 + Device OUT Endpoint 1 DMA Address + register + 0x334 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA2 + DOEPDMA2 + Device OUT Endpoint 2 DMA Address + register + 0x354 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA3 + DOEPDMA3 + Device OUT Endpoint 3 DMA Address + register + 0x374 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA4 + DOEPDMA4 + Device OUT Endpoint 4 DMA Address + register + 0x394 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA5 + DOEPDMA5 + Device OUT Endpoint 5 DMA Address + register + 0x3B4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA6 + DOEPDMA6 + Device OUT Endpoint 6 DMA Address + register + 0x3D4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA7 + DOEPDMA7 + Device OUT Endpoint 7 DMA Address + register + 0x3F4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + + + USB_OTGHS_PWRCLK + USB on the go high speed + USB_OTGHS + 0x40040E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGHS power and clock gating control + register (OTGHS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + SCFG + System configuration controller + SCFG + 0x40013800 + + 0x0 + 0x400 + registers + + + + CFG1 + CFG1 + configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MAP_SEL + Memory address mapping selection bits + 0 + 3 + + + IR_POL + IR output polarity selection + 5 + 1 + + + IR_SRC_SEL + IR signal source selection + 6 + 2 + + + + + CFG2 + CFG2 + configuration register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + LOCKUP_LK + CM4F LOCKUP bit enable + 0 + 1 + + + SRAM_OPERR_LK + SRAM odd parity error lock enable + 1 + 1 + + + PVM_LK + PVM lock enable + 2 + 1 + + + SRAM_OPERR_STS + SRAM odd parity error status + 8 + 1 + + + I2S_FD + I2S full duplex config + 30 + 2 + + + + + EXINTC1 + EXINTC1 + external interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXINT3 + EXINT 3 configuration bits + 12 + 4 + + + EXINT2 + EXINT 2 configuration bits + 8 + 4 + + + EXINT1 + EXINT 1 configuration bits + 4 + 4 + + + EXINT0 + EXINT 0 configuration bits + 0 + 4 + + + + + EXINTC2 + EXINTC2 + external interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXINT7 + EXINT 7 configuration bits + 12 + 4 + + + EXINT6 + EXINT 6 configuration bits + 8 + 4 + + + EXINT5 + EXINT 5 configuration bits + 4 + 4 + + + EXINT4 + EXINT 4 configuration bits + 0 + 4 + + + + + EXINTC3 + EXINTC3 + external interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXINT11 + EXINT 11 configuration bits + 12 + 4 + + + EXINT10 + EXINT 10 configuration bits + 8 + 4 + + + EXINT9 + EXINT 9 configuration bits + 4 + 4 + + + EXINT8 + EXINT 8 configuration bits + 0 + 4 + + + + + EXINTC4 + EXINTC4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXINT15 + EXINT 15 configuration bits + 12 + 4 + + + EXINT14 + EXINT 14 configuration bits + 8 + 4 + + + EXINT13 + EXINT 13 configuration bits + 4 + 4 + + + EXINT12 + EXINT 12 configuration bits + 0 + 4 + + + + + UHDRV + UHDRV + Ultra high drive register + 0x2C + 0x20 + read-write + 0x0000 + + + PB10_UH + PB10 ultra high sourcing/sinking strength + 2 + 1 + + + PB9_UH + PB9 ultra high sourcing/sinking strength + 1 + 1 + + + PB3_UH + PB3 ultra high sourcing/sinking strength + 0 + 1 + + + + + + + QSPI1 + Quad SPI Controller + QSPI + 0xA0001000 + + 0x0 + 0x400 + registers + + + QSPI1 + QSPI1 global interrupt + 92 + + + + CMD_W0 + CMD_W0 + Command word 0 + 0x0 + 0x20 + read-write + 0x00000000 + + + SPIADR + SPI flash address + 0 + 32 + + + + + CMD_W1 + CMD_W1 + Command word 1 + 0x4 + 0x20 + read-write + 0x01000003 + + + ADRLEN + SPI address length + 0 + 3 + + + DUM2 + Second dummy state cycle + 16 + 8 + + + INSLEN + Instruction code length + 24 + 2 + + + PEMEN + Perfrmance enhance mode enable + 28 + 1 + + + + + CMD_W2 + CMD_W2 + Command word 2 + 0x8 + 0x20 + read-write + 0x01000003 + + + DCNT + Read write data counter + 0 + 32 + + + + + CMD_W3 + CMD_W3 + Command word 3 + 0xC + 0x20 + read-write + 0x00000000 + + + WEN + Write data enable + 1 + 1 + + + RSTSEN + Read spi status enable + 2 + 1 + + + RSTSC + Read spi status configure + 3 + 1 + + + OPMODE + SPI operate mode + 5 + 3 + + + PEMOPC + Performance enhance mode operate code + 16 + 8 + + + INSC + Instruction code + 24 + 8 + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000000 + + + CLKDIV + SPI clock divider + 0 + 3 + + + SCKMODE + Sckout mode + 4 + 1 + + + XIPIDLE + XIP port idle status + 7 + 1 + + + ABORT + Abort instruction + 8 + 1 + + + BUSY + Busy bit of spi status + 16 + 3 + + + XIPRCMDF + XIP read command flush + 19 + 1 + + + XIPSEL + XIP port selection + 20 + 1 + + + KEYEN + encryption key enable + 21 + 1 + + + + + FIFOSTS + FIFOSTS + FIFO Status register + 0x18 + 0x20 + read-only + 0x00000001 + + + TXFIFORDY + TxFIFO ready status + 0 + 1 + + + RXFIFORDY + RxFIFO ready status + 1 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x20 + 0x20 + read-write + 0x00000001 + + + DMAEN + DMA handshake enable + 0 + 1 + + + CMDIE + Command complete interrupt enable + 1 + 1 + + + TXFIFOTHOD + TxFIFO thod + 8 + 2 + + + RXFIFOTHOD + RxFIFO thod + 12 + 2 + + + + + CMDSTS + CMDSTS + CMD status register + 0x24 + 0x20 + read-only + 0x00000000 + + + CMDSTS + Command complete status + 0 + 1 + + + + + RSTS + RSTS + SPI read status register + 0x28 + 0x20 + read-only + 0x00000000 + + + SPISTS + SPI read status + 0 + 8 + + + + + FSIZE + FSIZE + SPI flash size + 0x2C + 0x20 + read-write + 0x00000000 + + + SPIFSIZE + SPI flash size + 0 + 32 + + + + + XIP_CMD_W0 + XIP_CMD_W0 + XIP command word 0 + 0x30 + 0x20 + read-write + 0x00000000 + + + XIPR_DUM2 + XIP read second dummy cycle + 0 + 8 + + + XIPR_OPMODE + XIP read operate mode + 8 + 3 + + + XIPR_ADRLEN + XIP read address length + 11 + 1 + + + XIPR_INSC + XIP read instruction code + 12 + 8 + + + + + XIP_CMD_W1 + XIP_CMD_W1 + XIP command word 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + XIPW_DUM2 + XIP write second dummy cycle + 0 + 8 + + + XIPW_OPMODE + XIP write operate mode + 8 + 3 + + + XIPW_ADRLEN + XIP write address length + 11 + 1 + + + XIPW_INSC + XIP write instruction code + 12 + 8 + + + + + XIP_CMD_W2 + XIP_CMD_W2 + XIP command word 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + XIPR_DCNT + XIP read data counter + 0 + 5 + + + XIPR_TCNT + XIP continue read cycle counter + 8 + 7 + + + XIPR_SEL + XIP read continue mode select + 15 + 1 + + + XIPW_DCNT + XIP write data counter + 16 + 5 + + + XIPW_TCNT + XIP continue write cycle counter + 24 + 7 + + + XIPW_SEL + XIP write continue mode select + 31 + 1 + + + + + XIP_CMD_W3 + XIP_CMD_W3 + XIP command word 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + BYPASSC + Bypass cache function + 0 + 1 + + + CSTS + Cache status + 3 + 1 + + + + + REV + REV + Revision + 0x50 + 0x20 + read-write + 0x00010500 + + + REVISION + Revision number + 0 + 31 + + + + + DT + DT + 32/16/8 bit data port register + 0x100 + 0x20 + read-write + 0x00000000 + + + + + diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h new file mode 100644 index 000000000..9c07bf192 --- /dev/null +++ b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h @@ -0,0 +1,169 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define USB_VBUS_IGNORE +//#define USB_SOF_OUTPUT_ENABLE + +// LED +#define LED_PORT GPIOF +#define LED_PIN GPIO_PINS_4 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOF_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +//USART +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK +#define PRINT_UART_TX_PIN_SOURCE GPIO_PINS_SOURCE9 +#define PRINT_UART_TX_PIN_MUX_NUM GPIO_MUX_7 + +//USB +#ifdef BOARD_TUD_RHPORT + #if BOARD_TUD_RHPORT == 0 + #define USB_ID USB_OTG1_ID + #define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK + #define OTG_IRQ OTGFS1_IRQn + #define OTG_IRQ_HANDLER OTGFS1_IRQHandler + #define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_18 + #define OTG_PIN_GPIO GPIOA + #define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_VBUS GPIO_PINS_9 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 + #define OTG_PIN_ID GPIO_PINS_10 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_8 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 + #define OTG_PIN_MUX GPIO_MUX_10 + #define USB_SPEED_CORE_ID USB_FULL_SPEED_CORE_ID + #elif BOARD_TUD_RHPORT == 1 + #define USB_ID USB_OTG2_ID + #define OTG_CLOCK CRM_OTGHS_PERIPH_CLOCK + #define OTG_IRQ OTGHS_IRQn + #define OTG_IRQ_HANDLER OTGHS_IRQHandler + #define OTG_WKUP_IRQ OTGHS_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGHS_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_20 + #define OTG_PIN_GPIO GPIOB + #define OTG_PIN_GPIO_CLOCK CRM_GPIOB_PERIPH_CLOCK + #define OTG_PIN_VBUS GPIO_PINS_13 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 + #define OTG_PIN_ID GPIO_PINS_12 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_4 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE4 + #define OTG_PIN_MUX GPIO_MUX_10 + #define USB_SPEED_CORE_ID USB_HIGH_SPEED_CORE_ID + #endif +#endif +#ifdef BOARD_TUH_RHPORT + #if BOARD_TUH_RHPORT == 0 + #define USB_ID USB_OTG1_ID + #define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK + #define OTG_IRQ OTGFS1_IRQn + #define OTG_IRQ_HANDLER OTGFS1_IRQHandler + #define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_18 + #define OTG_PIN_GPIO GPIOA + #define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_VBUS GPIO_PINS_9 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 + #define OTG_PIN_ID GPIO_PINS_10 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_8 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 + #define OTG_PIN_MUX GPIO_MUX_10 + #define USB_SPEED_CORE_ID USB_FULL_SPEED_CORE_ID + #elif BOARD_TUH_RHPORT == 1 + #define USB_ID USB_OTG2_ID + #define OTG_CLOCK CRM_OTGHS_PERIPH_CLOCK + #define OTG_IRQ OTGHS_IRQn + #define OTG_IRQ_HANDLER OTGHS_IRQHandler + #define OTG_WKUP_IRQ OTGHS_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGHS_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_20 + #define OTG_PIN_GPIO GPIOB + #define OTG_PIN_GPIO_CLOCK CRM_GPIOB_PERIPH_CLOCK + #define OTG_PIN_VBUS GPIO_PINS_13 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 + #define OTG_PIN_ID GPIO_PINS_12 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_4 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE4 + #define OTG_PIN_MUX GPIO_MUX_10 + #define USB_SPEED_CORE_ID USB_HIGH_SPEED_CORE_ID + #endif +#endif + +//Vbus +static inline void board_vbus_sense_init(void) +{ + #ifdef BOARD_TUD_RHPORT + #if BOARD_TUD_RHPORT == 0 + *(int*)(0x50000038) |= (1<<21); + #elif BOARD_TUD_RHPORT == 1 + *(int*)(0x40040038) |= (1<<21); + #endif + #endif + #ifdef BOARD_TUH_RHPORT + #if BOARD_TUH_RHPORT == 0 + *(int*)(0x50000038) |= (1<<21); + #elif BOARD_TUH_RHPORT == 1 + *(int*)(0x40040038) |= (1<<21); + #endif + #endif +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk new file mode 100644 index 000000000..527d3706b --- /dev/null +++ b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F405xC_FLASH.ld + +CFLAGS += \ + -DAT32F405RCT7 diff --git a/hw/bsp/at32f402_405/family.c b/hw/bsp/at32f402_405/family.c new file mode 100644 index 000000000..dd8e7de10 --- /dev/null +++ b/hw/bsp/at32f402_405/family.c @@ -0,0 +1,297 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f402_405_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void uart_print_init(uint32_t baudrate); +void usb_clock48m_select(usb_clk48_s clk_s); +void led_and_botton_init(void); +void usb_gpio_config(void); + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTGFS1_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGHS_IRQHandler(void) +{ + tusb_int_handler(1, true); +} +void OTGFS1_WKUP_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGHS_WKUP_IRQHandler(void) +{ + tusb_int_handler(1, true); +} + +void board_init(void) +{ + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* config system clock */ + system_clock_config(); + + /* config usb io*/ + usb_gpio_config(); + + /* enable usb clock */ + crm_periph_clock_enable(OTG_CLOCK, TRUE); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HEXT); + + /* vbus ignore */ + board_vbus_sense_init(); + + /* configure systick */ + SysTick_Config(system_core_clock / 1000); + + #if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + #else + NVIC_SetPriority(OTG_IRQ, 0); + #endif + + /* config led and key */ + led_and_botton_init(); + + /* config usart to printf */ + uart_print_init(115200); + // printf("usart printf config success!\r\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +void led_and_botton_init(void) +{ + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN | GPIO_PINS_5 | GPIO_PINS_6; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + gpio_bits_set(LED_PORT, GPIO_PINS_5); + gpio_bits_set(LED_PORT, GPIO_PINS_6); + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); +} + +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + crm_pllu_output_set(TRUE); + /* wait till pll is ready */ + while(crm_flag_get(CRM_PLLU_STABLE_FLAG) != SET){} + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_PLLU); + } +} + +void usb_gpio_config(void) +{ + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + #ifdef USB_SOF_OUTPUT_ENABLE + crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); + gpio_init_struct.gpio_pins = OTG_PIN_SOF; + gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + #endif + /* otgfs use vbus pin */ + #ifndef USB_VBUS_IGNORE + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); + #endif +} + +/** + * @brief initialize uart + * @param baudrate: uart baudrate + * @retval none + */ +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + gpio_pin_mux_config(PRINT_UART_TX_GPIO, PRINT_UART_TX_PIN_SOURCE, PRINT_UART_TX_PIN_MUX_NUM); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +// Get characters from UART. Return number of read bytes +int board_uart_read(uint8_t *buf, int len) { + (void) buf; + (void) len; + return 0; +} + +// Send characters to UART. Return number of sent bytes +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + +void board_led_write(bool state) +{ + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) +{ + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + uint32_t board_millis(void) + { + return system_ticks; + } + void SVC_Handler(void) + { + } + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) +{ + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/hw/bsp/at32f402_405/family.mk b/hw/bsp/at32f402_405/family.mk new file mode 100644 index 000000000..9dbdb1a55 --- /dev/null +++ b/hw/bsp/at32f402_405/family.mk @@ -0,0 +1,45 @@ +# Submodules +AT32F402_405_SDK = hw/mcu/artery/at32f402_405 +DEPS_SUBMODULES += $(AT32F402_405_SDK) + +# AT32 SDK path +AT32F402_405_SDK_SRC = $(AT32F402_405_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F402_405 \ + -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_gpio.c \ + $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_misc.c \ + $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_usart.c \ + $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_crm.c \ + $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_acc.c \ + $(AT32F402_405_SDK_SRC)/cmsis/cm4/device_support/system_at32f402_405.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F402_405_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F402_405_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F402_405_SDK_SRC)/cmsis/cm4/device_support + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f402_405.s + +# For freeRTOS port source +#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4 + +flash: flash-atlink diff --git a/hw/bsp/at32f402_405/startup_at32f402_405.s b/hw/bsp/at32f402_405/startup_at32f402_405.s new file mode 100644 index 000000000..251ec5058 --- /dev/null +++ b/hw/bsp/at32f402_405/startup_at32f402_405.s @@ -0,0 +1,486 @@ +/** + ****************************************************************************** + * @file startup_at32f402_405.s + * @brief at32f402_405 devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */ + .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_IRQHandler /* ADC1 */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 Channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word ERTCAlarm_IRQHandler /* ERTC Alarm through EXINT Line */ + .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */ + .word 0 /* Reserved */ + .word TMR13_GLOBAL_IRQHandler /* TMR13 */ + .word TMR14_GLOBAL_IRQHandler /* TMR14 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI3_IRQHandler /* SPI3 */ + .word USART4_IRQHandler /* USART4 */ + .word USART5_IRQHandler /* USART5 */ + .word TMR6_GLOBAL_IRQHandler /* TMR6 */ + .word TMR7_GLOBAL_IRQHandler /* TMR7 */ + .word DMA2_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTGFS1_IRQHandler /* OTGFS1 */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + .word 0 /* Reserved */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EVT_IRQHandler /* I2C3 Event */ + .word I2C3_ERR_IRQHandler /* I2C3 Error */ + .word OTGHS_EP1_OUT_IRQHandler /* OTGHS endpoint1 out */ + .word OTGHS_EP1_IN_IRQHandler /* OTGHS endpoint1 in */ + .word OTGHS_WKUP_IRQHandler /* OTGHS Wakeup from suspend */ + .word OTGHS_IRQHandler /* OTGHS */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word 0 /* Reserved */ + .word I2SF5_IRQHandler /* I2SF5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word QSPI1_IRQHandler /* QSPI1 */ + .word 0 /* Reserved */ + .word DMAMUX_IRQHandler /* DMAMUX */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word ACC_IRQHandler /* ACC */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak ERTC_WKUP_IRQHandler + .thumb_set ERTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak ERTCAlarm_IRQHandler + .thumb_set ERTCAlarm_IRQHandler,Default_Handler + + .weak OTGFS1_WKUP_IRQHandler + .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler + + .weak TMR13_GLOBAL_IRQHandler + .thumb_set TMR13_GLOBAL_IRQHandler,Default_Handler + + .weak TMR14_GLOBAL_IRQHandler + .thumb_set TMR14_GLOBAL_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak USART4_IRQHandler + .thumb_set USART4_IRQHandler,Default_Handler + + .weak USART5_IRQHandler + .thumb_set USART5_IRQHandler,Default_Handler + + .weak TMR6_GLOBAL_IRQHandler + .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler + + .weak TMR7_GLOBAL_IRQHandler + .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak OTGFS1_IRQHandler + .thumb_set OTGFS1_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EVT_IRQHandler + .thumb_set I2C3_EVT_IRQHandler,Default_Handler + + .weak I2C3_ERR_IRQHandler + .thumb_set I2C3_ERR_IRQHandler,Default_Handler + + .weak OTGHS_EP1_OUT_IRQHandler + .thumb_set OTGHS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTGHS_EP1_IN_IRQHandler + .thumb_set OTGHS_EP1_IN_IRQHandler,Default_Handler + + .weak OTGHS_WKUP_IRQHandler + .thumb_set OTGHS_WKUP_IRQHandler,Default_Handler + + .weak OTGHS_IRQHandler + .thumb_set OTGHS_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak I2SF5_IRQHandler + .thumb_set I2SF5_IRQHandler,Default_Handler + + .weak QSPI1_IRQHandler + .thumb_set QSPI1_IRQHandler,Default_Handler + + .weak DMAMUX_IRQHandler + .thumb_set DMAMUX_IRQHandler ,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..d63959c4e --- /dev/null +++ b/hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f403a_407.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd new file mode 100644 index 000000000..323218b23 --- /dev/null +++ b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd @@ -0,0 +1,28047 @@ + + + + + + + + Keil + ArteryTek + AT32F407xx_v2 + AT32F407 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 200MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + XMC + Flexible static memory controller + XMC + 0xA0000000 + + 0x0 + 0x1000 + registers + + + XMC + XMC global interrupt + 48 + + + + BK1CTRL1 + BK1CTRL1 + SRAM/NOR-Flash chip-select control register + 1 + 0x0 + 0x20 + read-write + 0x000030DB + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG1 + BK1TMG1 + SRAM/NOR-Flash chip-select timing register + 1 + 0x4 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1CTRL4 + BK1CTRL4 + SRAM/NOR-Flash chip-select control register 4 + 0x18 + 0x20 + read-write + 0x000030D2 + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG4 + BK1TMG4 + SRAM/NOR-Flash chip-select timing register + 4 + 0x1C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK2CTRL + BK2CTRL + PC Card/NAND Flash control register 2 + 0x60 + 0x20 + read-write + 0x00000018 + + + ECCPGS + ECC page size + 17 + 3 + + + TAR + ALE to RE delay + 13 + 4 + + + TCR + CLE to RE delay + 9 + 4 + + + ECCEN + ECC enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 3 + 1 + + + EN + Memory bank enable + 2 + 1 + + + NWEN + Wait feature enable + 1 + 1 + + + + + BK2IS + BK2IS + FIFO status and interrupt register 2 + 0x64 + 0x20 + 0x00000040 + + + FIFOE + FIFO empty + 6 + 1 + read-only + + + FEIEN + Falling edge interrupt enable + 5 + 1 + read-write + + + HLIEN + High-level interrupt enable + 4 + 1 + read-write + + + REIEN + Rising edge interrupt enable + 3 + 1 + read-write + + + FES + Falling edge status + 2 + 1 + read-write + + + HLS + High-level status + 1 + 1 + read-write + + + RES + Rising edge capture status + 0 + 1 + read-write + + + + + BK2TMGMEM + BK2TMGMEM + Regular memory space timing register 2 + 0x68 + 0x20 + read-write + 0xFCFCFCFC + + + RGDHIZT + Regular memory databus High resistance time + 24 + 8 + + + RGHT + Regular memory hold time + 16 + 8 + + + RGWT + Regular memory wait time + 8 + 8 + + + RGST + Regular memory setup time + 0 + 8 + + + + + BK2TMGATT + BK2TMGATT + special memory space timing register 2 + 0x6C + 0x20 + read-write + 0xFCFCFCFC + + + SPDHIZT + special memory databus High resistance time + 24 + 8 + + + SPHT + special memory hold time + 16 + 8 + + + SPWT + special memory wait time + 8 + 8 + + + SPST + special memory setup time + 0 + 8 + + + + + BK2ECC + BK2ECC + ECC result register 2 + 0x74 + 0x20 + read-write + 0x00000000 + + + ECC + ECC result + 0 + 32 + + + + + BK1TMGWR1 + BK1TMGWR1 + SRAM/NOR-Flash write timing registers + 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR4 + BK1TMGWR4 + SRAM/NOR-Flash write timing registers + 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + EXT1 + EXT1 + externl timeing register 1 + 0x220 + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + EXT4 + EXT4 + externl timeing register 4 + 0x22C + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + BUSLATW2W + 0 + 8 + + + BUSLATR2R + BUSLATR2R + 8 + 8 + + + + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Power control register + (PWC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + VRSEL + Voltage regulator state select when deepsleep mode + 0 + 1 + + + LPSEL + Low power mode select when Cortex-M4F sleepdeep + 1 + 1 + + + CLSWEF + Clear SWEF flag + 2 + 1 + + + CLSEF + Clear SEF flag + 3 + 1 + + + PVMEN + Power voltage monitoring enable + 4 + 1 + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + + + BPWEN + Battery powered domain write enable + 8 + 1 + + + + + CTRLSTS + CTRLSTS + Power control and status register + (PWC_CTRLSTS) + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN + Standby wake-up pin enable + 8 + 1 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40021000 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 5 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + + + CFG + CFG + Clock configuration register + (CRM_CFG) + 0x4 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 8 + 3 + read-write + + + APB2DIV + APB2 division + 11 + 3 + read-write + + + ADCDIV1_0 + ADC division bit1 and bit0 + 14 + 2 + read-write + + + PLLRCS + PLL reference clock select + 16 + 1 + read-write + + + PLLHEXTDIV + HEXT division selection for PLL entry clock + 17 + 1 + read-write + + + PLLMULT3_0 + PLL Multiplication Factor bit3 to bit0 + 18 + 4 + read-write + + + USBDIV1_0 + USB division bit1 and bit0 + 22 + 2 + read-write + + + CLKOUT_SEL + Clock output selection bit2 to bit0 + 24 + 3 + read-write + + + USBDIV2 + USB division bit2 + 27 + 1 + read-write + + + ADCDIV2 + ADC division bit2 + 28 + 1 + read-write + + + PLLMULT5_4 + PLL Multiplication Factor bit5 and bit4 + 29 + 2 + read-write + + + PLLRANGE + PLL clock output frequency up 72MHz or not + 31 + 1 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + (CRM_CLKINT) + 0x8 + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + APB2RST + APB2RST + APB2 peripheral reset register + (CRM_APB2RST) + 0xC + 0x20 + read-write + 0x000000000 + + + IOMUXRST + MUX function I/O + reset + 0 + 1 + + + EXINTRST + External interrupt reset + 1 + 1 + + + GPIOARST + IO port A reset + 2 + 1 + + + GPIOBRST + IO port B reset + 3 + 1 + + + GPIOCRST + IO port C reset + 4 + 1 + + + GPIODRST + IO port D reset + 5 + 1 + + + GPIOERST + IO port E reset + 6 + 1 + + + ADC1RST + ADC1 reset + 9 + 1 + + + ADC2RST + ADC2 reset + 10 + 1 + + + TMR1RST + Timer1 reset + 11 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + TMR8RST + Timer8 reset + 13 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + ADC3RST + ADC3 reset + 15 + 1 + + + TMR9RST + Timer9 reset + 19 + 1 + + + TMR10RST + Timer10 reset + 20 + 1 + + + TMR11RST + Timer11 reset + 21 + 1 + + + ACCRST + ACC reset + 22 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + USART6RST + USART6 reset + 24 + 1 + + + UART7RST + UART7 reset + 25 + 1 + + + UART8RST + UART8 reset + 26 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + (CRM_APB1RST) + 0x10 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer 2 reset + 0 + 1 + + + TMR3RST + Timer 3 reset + 1 + 1 + + + TMR4RST + Timer 4 reset + 2 + 1 + + + TMR5RST + Timer 5 reset + 3 + 1 + + + TMR6RST + Timer 6 reset + 4 + 1 + + + TMR7RST + Timer 7 reset + 5 + 1 + + + TMR12RST + Timer 12 reset + 6 + 1 + + + TMR13RST + Timer 13 reset + 7 + 1 + + + TMR14RST + Timer 14 reset + 8 + 1 + + + WWDTRST + Window watchdog timer reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + SPI4RST + SPI4 reset + 16 + 1 + + + USART2RST + USART 2 reset + 17 + 1 + + + USART3RST + USART 3 reset + 18 + 1 + + + UART4RST + UART 4 reset + 19 + 1 + + + UART5RST + UART 5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + USBRST + USB reset + 23 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + CAN2RST + CAN2 reset + 26 + 1 + + + BPRRST + Battery powered domain register reset + 27 + 1 + + + PWCRST + Power controller reset + 28 + 1 + + + DACRST + DAC reset + 29 + 1 + + + + + AHBEN + AHBEN + AHB Peripheral Clock enable register + (CRM_AHBEN) + 0x14 + 0x20 + read-write + 0x00000014 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + SRAMEN + SRAM interface clock + enable + 2 + 1 + + + FLASHEN + FLASH clock enable + 4 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + XMCEN + XMC clock enable + 8 + 1 + + + SDIO1EN + SDIO1 clock enable + 10 + 1 + + + SDIO2EN + SDIO2 clock enable + 11 + 1 + + + EMACEN + EMACEN clock enable + 14 + 1 + + + EMACTXEN + EMACEN Tx clock enable + 15 + 1 + + + EMACRXEN + EMACEN Rx clock enable + 16 + 1 + + + EMACPTPEN + EMACPTP clock enable + 28 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + (CRM_APB2EN) + 0x18 + 0x20 + read-write + 0x00000000 + + + IOMUXEN + MUX function I/O clock + enable + 0 + 1 + + + GPIOAEN + I/O port A clock enable + 2 + 1 + + + GPIOBEN + I/O port B clock enable + 3 + 1 + + + GPIOCEN + I/O port C clock enable + 4 + 1 + + + GPIODEN + I/O port D clock enable + 5 + 1 + + + GPIOEEN + I/O port E clock enable + 6 + 1 + + + ADC1EN + ADC1 clock + enable + 9 + 1 + + + ADC2EN + ADC2 clock + enable + 10 + 1 + + + TMR1EN + Timer1 clock enable + 11 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + TMR8EN + Timer8 clock enable + 13 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + ADC3EN + ADC3 clock enable + 15 + 1 + + + TMR9EN + Timer9 clock enable + 19 + 1 + + + TMR10EN + Timer10 clock enable + 20 + 1 + + + TMR11EN + Timer11 clock enable + 21 + 1 + + + ACCEN + ACC clock enable + 22 + 1 + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + USART6EN + USART6 clock enable + 24 + 1 + + + UART7EN + UART7 clock enable + 25 + 1 + + + UART8EN + UART8 clock enable + 26 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + (CRM_APB1EN) + 0x1C + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR4EN + Timer4 clock enable + 2 + 1 + + + TMR5EN + Timer5 clock enable + 3 + 1 + + + TMR6EN + Timer6 clock enable + 4 + 1 + + + TMR7EN + Timer7 clock enable + 5 + 1 + + + TMR12EN + Timer12 clock enable + 6 + 1 + + + TMR13EN + Timer13 clock enable + 7 + 1 + + + TMR14EN + Timer14 clock enable + 8 + 1 + + + WWDTEN + Window watchdog timer clock + enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + SPI4EN + SPI4 clock enable + 16 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + USBEN + USB clock enable + 23 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + CAN2EN + CAN2 clock enable + 26 + 1 + + + BPREN + Barrery powered domain register clock + enable + 27 + 1 + + + PWCEN + Power clock enable + 28 + 1 + + + DACEN + DAC clock enable + 29 + 1 + + + + + BPDC + BPDC + Battery powered domain control register + (CRM_BPDC) + 0x20 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + RTCSEL + RTC clock selection + 8 + 2 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + (CRM_CTRLSTS) + 0x24 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset flag clear + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + AHBRST + AHBRST + AHB reset register + + 0x28 + 0x20 + 0x00000000 + + + EMACRST + EMAC reset + 14 + 1 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register1 + 0x30 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + CLKOUT_SEL3 + Clock output bit3 + 16 + 1 + read-write + + + USBBUFS + USB buffer size selection + 24 + 1 + read-write + + + HICKDIV + HICK 6 divider selection + 25 + 1 + read-write + + + CLKOUTDIV + Clock output division + 28 + 4 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register2 + 0x50 + 0x20 + 0x00000000 + + + CLK_TO_TMR + Clock output internal connect to timer10 + 16 + 1 + read-write + + + + + MISC3 + MISC3 + Miscellaneous register3 + 0x54 + 0x20 + 0x00000000 + + + AUTO_STEP_EN + AUTO_STEP_EN + 4 + 2 + read-write + + + HICK_TO_USB + HICK to usb clock + 8 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 9 + 1 + read-write + + + HEXTDIV + HEXT division + 12 + 2 + read-write + + + EMAC_PPS_SEL + Ethernet pulse width Select + 15 + 1 + read-write + + + + + INTMAP + INTMAP + Interrupt remap register + 0x5C + 0x20 + 0x00000000 + + + USB_INT_MAP + USBDEV interrupt remap + 0 + 1 + read-write + + + + + + + GPIOA + General purpose IO + GPIO + 0x40010800 + + 0x0 + 0x400 + registers + + + + CFGLR + CFGLR + GPIO function configurate low register + 0x0 + 0x20 + read-write + 0x44444444 + + + IOMC0 + Port n.0 mode configurate bits + 0 + 2 + + + IOFC0 + Port n.0 function configurate + bits + 2 + 2 + + + IOMC1 + Port n.1 mode configurate bits + 4 + 2 + + + IOFC1 + Port n.1 function configurate + bits + 6 + 2 + + + IOMC2 + Port n.2 mode configurate bits + 8 + 2 + + + IOFC2 + Port n.2 function configurate + bits + 10 + 2 + + + IOMC3 + Port n.3 mode configurate bits + 12 + 2 + + + IOFC3 + Port n.3 function configurate + bits + 14 + 2 + + + IOMC4 + Port n.4 mode configurate bits + 16 + 2 + + + IOFC4 + Port n.4 function configurate + bits + 18 + 2 + + + IOMC5 + Port n.5 mode configurate bits + 20 + 2 + + + IOFC5 + Port n.5 function configurate + bits + 22 + 2 + + + IOMC6 + Port n.6 mode configurate bits + 24 + 2 + + + IOFC6 + Port n.6 function configurate + bits + 26 + 2 + + + IOMC7 + Port n.7 mode configurate bits + 28 + 2 + + + IOFC7 + Port n.7 function configurate + bits + 30 + 2 + + + + + CFGHR + CFGHR + GPIO function configurate high register + 0x4 + 0x20 + read-write + 0x44444444 + + + IOMC8 + Port n.8 mode configurate bits + 0 + 2 + + + IOFC8 + Port n.8 function configurate + bits + 2 + 2 + + + IOMC9 + Port n.9 mode configurate bits + 4 + 2 + + + IOFC9 + Port n.9 function configurate + bits + 6 + 2 + + + IOMC10 + Port n.10 mode configurate bits + 8 + 2 + + + IOFC10 + Port n.10 function configurate + bits + 10 + 2 + + + IOMC11 + Port n.11 mode configurate bits + 12 + 2 + + + IOFC11 + Port n.11 function configurate + bits + 14 + 2 + + + IOMC12 + Port n.12 mode configurate bits + 16 + 2 + + + IOFC12 + Port n.12 function configurate + bits + 18 + 2 + + + IOMC13 + Port n.13 mode configurate bits + 20 + 2 + + + IOFC13 + Port n.13 function configurate + bits + 22 + 2 + + + IOMC14 + Port n.14 mode configurate bits + 24 + 2 + + + IOFC14 + Port n.14 function configurate + bits + 26 + 2 + + + IOMC15 + Port n.15 mode configurate bits + 28 + 2 + + + IOFC15 + Port n.15 function configurate + bits + 30 + 2 + + + + + IDT + IDT + Port input data register + 0x8 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + Port output data register + 0xC + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x10 + 0x20 + read-write + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + CLR + CLR + Port bit reset register + 0x14 + 0x20 + read-write + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 1 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + WPR + WPR + Port write protect + register + 0x18 + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + HDRV + HDRV + Port configuration driver + register + 0x3C + 0x20 + read-write + 0x00000000 + + + HDRV0 + Port hdrv bit 0 + 0 + 1 + + + HDRV1 + Port hdrv bit 1 + 1 + 1 + + + HDRV2 + Port hdrv bit 2 + 2 + 1 + + + HDRV3 + Port hdrv bit 3 + 3 + 1 + + + HDRV4 + Port hdrv bit 4 + 4 + 1 + + + HDRV5 + Port hdrv bit 5 + 5 + 1 + + + HDRV6 + Port hdrv bit 6 + 6 + 1 + + + HDRV7 + Port hdrv bit 7 + 7 + 1 + + + HDRV8 + Port hdrv bit 8 + 8 + 1 + + + HDRV9 + Port hdrv bit 9 + 9 + 1 + + + HDRV10 + Port hdrv bit 10 + 10 + 1 + + + HDRV11 + Port hdrv bit 11 + 11 + 1 + + + HDRV12 + Port hdrv bit 12 + 12 + 1 + + + HDRV13 + Port hdrv bit 13 + 13 + 1 + + + HDRV14 + Port hdrv bit 14 + 14 + 1 + + + HDRV15 + Port hdrv bit 15 + 15 + 1 + + + + + + + GPIOB + 0x40010C00 + + + GPIOC + 0x40011000 + + + GPIOD + 0x40011400 + + + GPIOE + 0x40011800 + + + IOMUX + IO MUX function + IOMUX + 0x40010000 + + 0x0 + 0x400 + registers + + + + EVTOUT + EVTOUT + Event output register + (IOMUX_EVTOUT) + 0x0 + 0x20 + read-write + 0x00000000 + + + SELPIN + Select pin + 0 + 4 + + + SELPORT + Select port + 4 + 3 + + + EVOEN + Event output enable + 7 + 1 + + + + + REMAP + REMAP + IO MUX remap register + (IOMUX_REMAP) + 0x4 + 0x20 + 0x00000000 + + + SPI1_MUX0 + SPI1 muxing bit0 + 0 + 1 + read-write + + + I2C1_MUX + I2C1 muxing + 1 + 1 + read-write + + + USART1_MUX + USART1 muxing + 2 + 1 + read-write + + + USART2_MUX + USART2 muxing + 3 + 1 + read-write + + + USART3_MUX + USART3 muxing + 4 + 2 + read-write + + + TMR1_MUX + TMR1 muxing + 6 + 2 + read-write + + + TMR2_MUX + TMR2 muxing + 8 + 2 + read-write + + + TMR3_MUX + TMR3 muxing + 10 + 2 + read-write + + + TMR4_MUX + TMR4 muxing + 12 + 1 + read-write + + + CAN_MUX + CAN1 muxing + 13 + 2 + read-write + + + PD01_MUX + PD0/PD1 muxing on + OSCIN/OSCOUT + 15 + 1 + read-write + + + TMR5CH4_MUX + TMR5 channel4 internal muxing + 16 + 1 + read-write + + + ADC1_ETP_MUX + ADC1 external trigger preempted + conversion muxing + 17 + 1 + read-write + + + ADC1_ETO_MUX + ADC1 external trigger ordinary + conversion muxing + 18 + 1 + read-write + + + ADC2_ETP_MUX + ADC2 external trigger preempted + conversion muxing + 19 + 1 + read-write + + + ADC2_ETO_MUX + ADC2 external trigger ordinary + conversion muxing + 20 + 1 + read-write + + + EMAC_MUX + Ethernet MAC muxing + 21 + 1 + read-write + + + CAN2_MUX + CAN2 muxing + 22 + 1 + read-write + + + MII_RMII_SEL_MUX + MII_RMII select muxing + 23 + 1 + read-write + + + SWJTAG_MUX + SWD JTAG muxing + 24 + 3 + read-write + + + SPI3_MUX + SPI3 muxing + 28 + 1 + read-write + + + TMR2ITR1_MUX + TMR2 internal trigger 1 + muxing + 29 + 1 + read-write + + + PTP_PPS_MUX + PTP_PPS muxing + 30 + 1 + read-write + + + SPI1_MUX1 + SPI1 muxing bit1 + 31 + 1 + read-write + + + + + EXINTC1 + EXINTC1 + External interrupt configuration register 1 + (IOMUX_EXINTC1) + 0x8 + 0x20 + read-write + 0x00000000 + + + EXINT0 + Configure EXINT0 source + 0 + 4 + + + EXINT1 + Configure EXINT1 source + 4 + 4 + + + EXINT2 + Configure EXINT2 source + 8 + 4 + + + EXINT3 + Configure EXINT3 source + 12 + 4 + + + + + EXINTC2 + EXINTC2 + External interrupt configuration register 2 + (IOMUX_EXINTC2) + 0xC + 0x20 + read-write + 0x00000000 + + + EXINT4 + Configure EXINT4 source + 0 + 4 + + + EXINT5 + Configure EXINT5 source + 4 + 4 + + + EXINT6 + Configure EXINT6 source + 8 + 4 + + + EXINT7 + Configure EXINT7 source + 12 + 4 + + + + + EXINTC3 + EXINTC3 + External interrupt configuration register 3 + (IOMUX_EXINTC3) + 0x10 + 0x20 + read-write + 0x00000000 + + + EXINT8 + Configure EXINT8 source + 0 + 4 + + + EXINT9 + Configure EXINT9 source + 4 + 4 + + + EXINT10 + Configure EXINT10 source + 8 + 4 + + + EXINT11 + Configure EXINT11 source + 12 + 4 + + + + + EXINTC4 + EXINTC4 + External interrupt configuration register 4 + (IOMUX_EXINTC4) + 0x14 + 0x20 + read-write + 0x00000000 + + + EXINT12 + Configure EXINT12 source + 0 + 4 + + + EXINT13 + Configure EXINT13 source + 4 + 4 + + + EXINT14 + Configure EXINT14 source + 8 + 4 + + + EXINT15 + Configure EXINT15 source + 12 + 4 + + + + + REMAP2 + REMAP2 + IO MUX remap register 2 + (IOMUX_REMAP2) + 0x1C + 0x20 + read-write + 0x00000000 + + + TMR9_MUX + TMR9 muxing + 5 + 1 + + + XMC_NADV_MUX + NADV connect/disconnect + 10 + 1 + + + SPI4_MUX + SPI4 muxing + 17 + 1 + + + I2C3_MUX + I2C3 muxing + 18 + 1 + + + SDIO2_MUX + SDIO2 muxing + 19 + 2 + + + EXT_SPIM_EN_MUX + SPIM enable muxing + 21 + 1 + + + + + REMAP3 + REMAP3 + IO MUX remap register 3 + (IOMUX_REMAP3) + 0x20 + 0x20 + read-write + 0x00000000 + + + TMR9_GMUX + TMR9 muxing + 0 + 4 + + + + + REMAP4 + REMAP4 + IO MUX remap register 4 + (IOMUX_REMAP4) + 0x24 + 0x20 + read-write + 0x00000000 + + + TMR1_GMUX + TMR1 muxing + 0 + 4 + + + TMR2_GMUX + TMR2 muxing + 4 + 2 + + + TMR2ITR1_GMUX + TMR2 internal trigger 1 + muxing + 6 + 2 + + + TMR3_GMUX + TMR3 muxing + 8 + 4 + + + TMR4_GMUX + TMR4 muxing + 12 + 4 + + + TMR5CH4_GMUX + TMR5 channel4 internal + muxing + 19 + 1 + + + + + REMAP5 + REMAP5 + IO MUX remap register 5 + (IOMUX_REMAP5) + 0x28 + 0x20 + read-write + 0x00000000 + + + USART5_GMUX + USART5 muxing + 0 + 4 + + + I2C1_GMUX + I2C1 muxing + 4 + 4 + + + I2C3_GMUX + I2C3 muxing + 12 + 4 + + + SPI1_GMUX + SPI1 muxing + 16 + 4 + + + SPI2_GMUX + SPI2 muxing + 20 + 4 + + + SPI3_GMUX + SPI3 muxing + 24 + 4 + + + SPI4_GMUX + SPI4 muxing + 28 + 4 + + + + + REMAP6 + REMAP6 + IO MUX remap register 6 + (IOMUX_REMAP6) + 0x2C + 0x20 + read-write + 0x00000000 + + + CAN1_GMUX + CAN1 muxing + 0 + 4 + + + CAN2_GMUX + CAN2 muxing + 4 + 4 + + + SDIO2_GMUX + SDIO2 muxing + 12 + 4 + + + USART1_GMUX + USART1 muxing + 16 + 4 + + + USART2_GMUX + USART2 muxing + 20 + 4 + + + USART3_GMUX + USART3 muxing + 24 + 4 + + + UART4_GMUX + UART4 muxing + 28 + 4 + + + + + REMAP7 + REMAP7 + IO MUX remap register 7 + (IOMUX_REMAP7) + 0x30 + 0x20 + read-write + 0x00000000 + + + EXT_SPIM_GMUX + SPIM muxing + 0 + 3 + + + EXT_SPIM_GEN + SPIM enable + 3 + 1 + + + ADC1_ETP_GMUX + ADC1 external trigger preempted + conversion muxing + 4 + 1 + + + ADC1_ETO_GMUX + ADC1 external trigger ordinary + conversion muxing + 5 + 1 + + + ADC2_ETP_GMUX + ADC2 external trigger preempted + conversion muxing + 8 + 1 + + + ADC2_ETO_GMUX + ADC2 external trigger ordinary + conversion muxing + 9 + 1 + + + SWJTAG_GMUX + Serial wire JTAG muxing + 16 + 3 + + + PD01_GMUX + PortD0/PortD1 mappingon + OSC_IN/OSC_OUT + 20 + 1 + + + XMC_GMUX + XMC muxing + 24 + 3 + + + XMC_NADV_GMUX + XMC_NADV muxing + 27 + 1 + + + + + REMAP8 + REMAP8 + IO MUX remap register 8 + (IOMUX_REMAP8) + 0x34 + 0x20 + read-write + 0x00000000 + + + EMAC_GMUX + Ethernet MAC muxing + 16 + 2 + + + MII_RMII_SEL_GMUX + MII_RMII select muxing + 18 + 1 + + + PTP_PPS_GMUX + PTP_PPS muxing + 19 + 1 + + + USART6_GMUX + USART6 muxing + 20 + 4 + + + UART7_GMUX + UART7 muxing + 24 + 4 + + + UART8_GMUX + UART8 muxing + 28 + 4 + + + + + + + EXINT + EXINT + EXINT + 0x40010400 + + 0x0 + 0x400 + registers + + + TAMPER + Tamper interrupt + 2 + + + EXINT0 + EXINT Line0 interrupt + 6 + + + EXINT1 + EXINT Line1 interrupt + 7 + + + EXINT2 + EXINT Line2 interrupt + 8 + + + EXINT3 + EXINT Line3 interrupt + 9 + + + EXINT4 + EXINT Line4 interrupt + 10 + + + EXINT9_5 + EXINT Line[9:5] interrupts + 23 + + + EXINT15_10 + EXINT Line[15:10] interrupts + 40 + + + PVM + PVM interrupt connect to EXINT line16 + 1 + + + RTCALARM + RTC Alarm interrupt connect to EXINT line17 + 41 + + + USBFSWakeUp + USB Device FS Wakeup interrupt connect to EXINT line18 + 42 + + + EMAC_WKUP + EMAC_WKUP interrupt connect to EXINT line19 + 80 + + + + INTEN + INTEN + Interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + INTEN19 + Interrupt enable or disable on line 19 + 19 + 1 + + + + + EVTEN + EVTEN + Event enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + EVTEN19 + Event enable or disable on line 19 + 19 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + RP19 + Rising polarity configuration bit of line 19 + 19 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + FP19 + Falling polarity event configuration bit of line 19 + 19 + 1 + + + + + SWTRG + SWTRG + Software triggle register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + SWT19 + Software triggle on line 19 + 19 + 1 + + + + + INTSTS + INTSTS + Interrupt status register + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + LINE19 + Line 19 state bit + 19 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 13 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 14 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 15 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 16 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 17 + + + + STS + STS + DMA interrupt status register (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA interrupt flag clear register (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_SRC_SEL0 + DMA_SRC_SEL0 + DMA channel source assignment register + 0xA0 + 0x20 + read-write + 0x00000000 + + + CH1_SRC + CH1 SRC select + 0 + 8 + + + CH2_SRC + CH2 SRC select + 8 + 8 + + + CH3_SRC + CH3 SRC select + 16 + 8 + + + CH4_SRC + CH4 SRC select + 24 + 8 + + + + + DMA_SRC_SEL1 + DMA_SRC_SEL1 + DMA channel source assignment register + 0xA4 + 0x20 + read-write + 0x00000000 + + + CH5_SRC + CH5 SRC select + 0 + 8 + + + CH6_SRC + CH6 SRC select + 8 + 8 + + + CH7_SRC + CH7 SRC select + 16 + 8 + + + DMA_FLEX_EN + DMA FLEX Enable + 24 + 1 + + + + + + + DMA2 + 0x40020400 + + DMA2_Channel1 + DMA2 Channel1 global interrupt + 56 + + + DMA2_Channel2 + DMA2 Channel2 global interrupt + 57 + + + DMA2_Channel3 + DMA2 Channel3 global interrupt + 58 + + + DMA2_Channel4_5 + DMA2 Channel4 and DMA2 Channel5 global + interrupt + 59 + + + DMA2_Channel6_7 + DMA2 Channel6 and DMA2 Channel7 global + interrupt + 75 + + + + SDIO1 + Secure digital input/output + interface + SDIO + 0x40018000 + + 0x0 + 0x400 + registers + + + SDIO1 + SDIO1 global interrupt + 49 + + + + PWRCTRL + PWRCTRL + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PS + Power switch + 0 + 2 + + + + + CLKCTRL + CLKCTRL + SD clock control register + (SDIO_CLKCTRL) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock division + 0 + 8 + + + CLKOEN + Clock output enable + 8 + 1 + + + PWRSVEN + Power saving mode enable + 9 + 1 + + + BYPSEN + Clock divider bypass enable + bit + 10 + 1 + + + BUSWS + Bus width selection + 11 + 2 + + + CLKEDS + SDIO_CK edge selection bit + 13 + 1 + + + HFCEN + Hardware flow control enable + 14 + 1 + + + CLKDIV98 + Clock divide factor bit9 and bit8 + 15 + 2 + + + + + ARGU + ARGU + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + ARGU + Command argument + 0 + 32 + + + + + CMDCTRL + CMDCTRL + SDIO command control register + (SDIO_CMDCTRL) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDIDX + CMDIDX + 0 + 6 + + + RSPWT + Wait for response + 6 + 2 + + + INTWT + CCSM wait for interrupt + 8 + 1 + + + PNDWT + CCSM wait for end of transfer + 9 + 1 + + + CCSMEN + Command channel state machine + 10 + 1 + + + IOSUSP + SD I/O suspend command + 11 + 1 + + + + + RSPCMD + RSPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RSPCMD + RSPCMD + 0 + 6 + + + + + RSP1 + RSP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTS1 + CARDSTATUS1 + 0 + 32 + + + + + RSP2 + RSP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS2 + 0 + 32 + + + + + RSP3 + RSP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTS3 + CARDSTATUS3 + 0 + 32 + + + + + RSP4 + RSP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTS4 + CARDSTATUS4 + 0 + 32 + + + + + DTTMR + DTTMR + Bits 31:0 = TIMEOUT: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Data timeout period + 0 + 32 + + + + + DTLEN + DTLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DTLEN + Data length value + 0 + 25 + + + + + DTCTRL + DTCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TFREN + DTEN + 0 + 1 + + + TFRDIR + DTDIR + 1 + 1 + + + TFRMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + BLKSIZE + DBLOCKSIZE + 4 + 4 + + + RDWTSTART + PWSTART + 8 + 1 + + + RDWTSTOP + PWSTOP + 9 + 1 + + + RDWTMODE + RWMOD + 10 + 1 + + + IOEN + SD I/O function enable + 11 + 1 + + + + + DTCNT + DTCNT + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + CNT + Data count value + 0 + 25 + + + + + STS + STS + SDIO status register + (SDIO_STS) + 0x34 + 0x20 + read-only + 0x00000000 + + + CMDFAIL + Command crc fail + 0 + 1 + + + DTFAIL + Data crc fail + 1 + 1 + + + CMDTIMEOUT + Command timeout + 2 + 1 + + + DTTIMEOUT + Data timeout + 3 + 1 + + + TXERRU + Tx under run error + 4 + 1 + + + RXERRO + Rx over run error + 5 + 1 + + + CMDRSPCMPL + Command response complete + 6 + 1 + + + CMDCMPL + Command sent + 7 + 1 + + + DTCMPL + Data sent + 8 + 1 + + + SBITERR + Start bit error + 9 + 1 + + + DTBLKCMPL + Data block sent + 10 + 1 + + + DOCMD + Command transfer in progress + 11 + 1 + + + DOTX + Data transmit in progress + 12 + 1 + + + DORX + Data receive in progress + 13 + 1 + + + TXBUFH + Tx buffer half empty + 14 + 1 + + + RXBUFH + Rx buffer half empty + 15 + 1 + + + TXBUFF + Tx buffer full + 16 + 1 + + + RXBUFF + Rx buffer full + 17 + 1 + + + TXBUFE + Tx buffer empty + 18 + 1 + + + RXBUFE + Rx buffer empty + 19 + 1 + + + TXBUF + Tx data vaild + 20 + 1 + + + RXBUF + Rx data vaild + 21 + 1 + + + IOIF + SD I/O interrupt + 22 + 1 + + + + + INTCLR + INTCLR + SDIO interrupt clear register + (SDIO_INTCLR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CMDFAIL + Command crc fail flag clear + 0 + 1 + + + DTFAIL + Data crc fail flag clear + 1 + 1 + + + CMDTIMEOUT + Command timeout flag clear + 2 + 1 + + + DTTIMEOUT + Data timeout flag clear + 3 + 1 + + + TXERRU + Tx under run error flag clear + 4 + 1 + + + RXERRU + Rx over run error flag clear + 5 + 1 + + + CMDRSPCMPL + Command response complete flag clear + 6 + 1 + + + CMDCMPL + Command sent flag clear + 7 + 1 + + + DTCMPL + Data sent flag clear + 8 + 1 + + + SBITERR + Start bit error flag clear + 9 + 1 + + + DTBLKCMPL + Data block sent clear + 10 + 1 + + + IOIF + SD I/O interrupt flag clear + 22 + 1 + + + + + INTEN + INTEN + SDIO interrupt enable register + (SDIO_INTEN) + 0x3C + 0x20 + read-write + 0x00000000 + + + CMDFAILIEN + Command crc fail interrupt enable + 0 + 1 + + + DTFAILIEN + Data crc fail interrupt enable + 1 + 1 + + + CMDTIMEOUTIEN + Command timeout interrupt enable + 2 + 1 + + + DTTIMEOUTIEN + Data timeout interrupt enable + 3 + 1 + + + TXERRUIEN + Tx under run interrupt enable + 4 + 1 + + + RXERRUIEN + Rx over run interrupt enable + 5 + 1 + + + CMDRSPCMPLIEN + Command response complete interrupt enable + 6 + 1 + + + CMDCMPLIEN + Command sent complete interrupt enable + 7 + 1 + + + DTCMPLIEN + Data sent complete interrupt enable + 8 + 1 + + + SBITERRIEN + Start bit error interrupt enable + 9 + 1 + + + DTBLKCMPLIEN + Data block sent complete interrupt enable + 10 + 1 + + + DOCMDIEN + Command acting interrupt enable + 11 + 1 + + + DOTXIEN + Data transmit acting interrupt enable + 12 + 1 + + + DORXIEN + Data receive acting interrupt enable + 13 + 1 + + + TXBUFHIEN + Tx buffer half empty interrupt enable + 14 + 1 + + + RXBUFHIEN + Rx buffer half empty interrupt enable + 15 + 1 + + + TXBUFFIEN + Tx buffer full interrupt enable + 16 + 1 + + + RXBUFFIEN + Rx buffer full interrupt enable + 17 + 1 + + + TXBUFEIEN + Tx buffer empty interrupt enable + 18 + 1 + + + RXBUFEIEN + Rx buffer empty interrupt enable + 19 + 1 + + + TXBUFIEN + Tx buffer data vaild interrupt enable + 20 + 1 + + + RXBUFIEN + Rx buffer data vaild interrupt enable + 21 + 1 + + + IOIFIEN + SD I/O interrupt enable + 22 + 1 + + + + + BUFCNT + BUFCNT + Bits 23:0 = BUFCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + FIF0COUNT + 0 + 24 + + + + + BUF + BUF + bits 31:0 = Buffer Data: Receive and transmit + buffer data + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Buffer data + 0 + 32 + + + + + + + SDIO2 + 0x40023400 + + SDIO2 + SDIO2 global interrupt + 60 + + + + RTC + Real time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC + RTC global interrupt + 3 + + + + CTRLH + CTRLH + RTC Control Register High + 0x0 + 0x20 + read-write + 0x00000000 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + TAIEN + Time alarm interrupt enable + 1 + 1 + + + TSIEN + Time second interrupt enable + 2 + 1 + + + + + CTRLL + CTRLL + RTC Control Register Low + 0x4 + 0x20 + 0x00000020 + + + TSF + Time second flag + 0 + 1 + read-write + + + TAF + Time alarm flag + 1 + 1 + read-write + + + OVFF + Overflow Flag + 2 + 1 + read-write + + + UPDF + RTC update finish + 3 + 1 + read-write + + + CFGEN + RTC configuration enable + 4 + 1 + read-write + + + CFGF + RTC configuration finish + 5 + 1 + read-only + + + + + DIVH + DIVH + RTC Divider Register + High + 0x8 + 0x20 + write-only + 0x00000000 + + + DIV + RTC divider high + 0 + 4 + + + + + DIVL + DIVL + RTC Divider Register + Low + 0xC + 0x20 + write-only + 0x8000 + + + DIV + RTC divider low + 0 + 16 + + + + + DIVCNTH + DIVCNTH + RTC Divider Register High + 0x10 + 0x20 + read-write + 0x00000000 + + + DIVCNT + RTC divider register high + 0 + 4 + + + + + DIVCNTL + DIVCNTL + RTC Divider Register Low + 0x14 + 0x20 + read-write + 0x8000 + + + DIVCNT + RTC divider register low + 0 + 16 + + + + + CNTH + CNTH + RTC Counter Register High + 0x18 + 0x20 + read-write + 0x00000000 + + + CNT + RTC counter register high + 0 + 16 + + + + + CNTL + CNTL + RTC Counter Register Low + 0x1C + 0x20 + read-write + 0x00000000 + + + CNT + RTC counter register low + 0 + 16 + + + + + TAH + TAH + RTC Alarm Register High + 0x20 + 0x20 + write-only + 0xFFFF + + + TA + Time alarm register high + 0 + 16 + + + + + TAL + TAL + Time alarm register low + 0x24 + 0x20 + write-only + 0xFFFF + + + TA + RTC alarm register low + 0 + 16 + + + + + + + BPR + Battery powered register + BPR + 0x40006C04 + + 0x0 + 0x3FC + registers + + + + DT1 + DT1 + Battery powered domain data + register (BPR_DTx) + 0x0 + 0x20 + read-write + 0x00000000 + + + DT1 + BPR data1 + 0 + 16 + + + + + DT2 + DT2 + Battery powered domain data + register (BPR_DTx) + 0x4 + 0x20 + read-write + 0x00000000 + + + DT2 + BPR data2 + 0 + 16 + + + + + DT3 + DT3 + Battery powered domain data + register (BPR_DTx) + 0x8 + 0x20 + read-write + 0x00000000 + + + DT3 + BPR data3 + 0 + 16 + + + + + DT4 + DT4 + Battery powered domain data + register (BPR_DTx) + 0xC + 0x20 + read-write + 0x00000000 + + + DT4 + BPR data4 + 0 + 16 + + + + + DT5 + DT5 + Battery powered domain data + register (BPR_DTx) + 0x10 + 0x20 + read-write + 0x00000000 + + + DT5 + BPR data5 + 0 + 16 + + + + + DT6 + DT6 + Battery powered domain data + register (BPR_DTx) + 0x14 + 0x20 + read-write + 0x00000000 + + + DT6 + BPR data6 + 0 + 16 + + + + + DT7 + DT7 + Battery powered domain data + register (BPR_DTx) + 0x18 + 0x20 + read-write + 0x00000000 + + + DT7 + BPR data7 + 0 + 16 + + + + + DT8 + DT8 + Battery powered domain data + register (BPR_DTx) + 0x1C + 0x20 + read-write + 0x00000000 + + + DT8 + BPR data8 + 0 + 16 + + + + + DT9 + DT9 + Battery powered domain data + register (BPR_DTx) + 0x20 + 0x20 + read-write + 0x00000000 + + + DT9 + BPR data9 + 0 + 16 + + + + + DT10 + DT10 + Battery powered domain data + register (BPR_DTx) + 0x24 + 0x20 + read-write + 0x00000000 + + + DT10 + BPR data10 + 0 + 16 + + + + + DT11 + DT11 + Battery powered domain data + register (BPR_DTx) + 0x3C + 0x20 + read-write + 0x00000000 + + + DT11 + BPR data11 + 0 + 16 + + + + + DT12 + DT12 + Battery powered domain data + register (BPR_DTx) + 0x40 + 0x20 + read-write + 0x00000000 + + + DT12 + BPR data12 + 0 + 16 + + + + + DT13 + DT13 + Battery powered domain data + register (BPR_DTx) + 0x44 + 0x20 + read-write + 0x00000000 + + + DT13 + BPR data13 + 0 + 16 + + + + + DT14 + DT14 + Battery powered domain data + register (BPR_DTx) + 0x48 + 0x20 + read-write + 0x00000000 + + + DT14 + BPR data14 + 0 + 16 + + + + + DT15 + DT15 + Battery powered domain data + register (BPR_DTx) + 0x4C + 0x20 + read-write + 0x00000000 + + + DT15 + BPR data15 + 0 + 16 + + + + + DT16 + DT16 + Battery powered domain data + register (BPR_DTx) + 0x50 + 0x20 + read-write + 0x00000000 + + + DT16 + BPR data16 + 0 + 16 + + + + + DT17 + DT17 + Battery powered domain data + register (BPR_DTx) + 0x54 + 0x20 + read-write + 0x00000000 + + + DT17 + BPR data17 + 0 + 16 + + + + + DT18 + DT18 + Battery powered domain data + register (BPR_DTx) + 0x58 + 0x20 + read-write + 0x00000000 + + + DT18 + BPR data18 + 0 + 16 + + + + + DT19 + DT19 + Battery powered domain data + register (BPR_DTx) + 0x5C + 0x20 + read-write + 0x00000000 + + + DT19 + BPR data19 + 0 + 16 + + + + + DT20 + DT20 + Battery powered domain data + register (BPR_DTx) + 0x60 + 0x20 + read-write + 0x00000000 + + + DT20 + BPR data20 + 0 + 16 + + + + + DT21 + DT21 + Battery powered domain data + register (BPR_DTx) + 0x64 + 0x20 + read-write + 0x00000000 + + + DT21 + BPR data21 + 0 + 16 + + + + + DT22 + DT22 + Battery powered domain data + register (BPR_DTx) + 0x68 + 0x20 + read-write + 0x00000000 + + + DT22 + BPR data22 + 0 + 16 + + + + + DT23 + DT23 + Battery powered domain data + register (BPR_DTx) + 0x6C + 0x20 + read-write + 0x00000000 + + + DT23 + BPR data23 + 0 + 16 + + + + + DT24 + DT24 + Battery powered domain data + register (BPR_DTx) + 0x70 + 0x20 + read-write + 0x00000000 + + + DT24 + BPR data24 + 0 + 16 + + + + + DT25 + DT25 + Battery powered domain data + register (BPR_DTx) + 0x74 + 0x20 + read-write + 0x00000000 + + + DT25 + BPR data25 + 0 + 16 + + + + + DT26 + DT26 + Battery powered domain data + register (BPR_DTx) + 0x78 + 0x20 + read-write + 0x00000000 + + + DT26 + BPR data26 + 0 + 16 + + + + + DT27 + DT27 + Battery powered domain data + register (BPR_DTx) + 0x7C + 0x20 + read-write + 0x00000000 + + + DT27 + BPR data27 + 0 + 16 + + + + + DT28 + DT28 + Battery powered domain data + register (BPR_DTx) + 0x80 + 0x20 + read-write + 0x00000000 + + + DT28 + BPR data28 + 0 + 16 + + + + + DT29 + DT29 + Battery powered domain data + register (BPR_DTx) + 0x84 + 0x20 + read-write + 0x00000000 + + + DT29 + BPR data29 + 0 + 16 + + + + + DT30 + DT30 + Battery powered domain data + register (BPR_DTx) + 0x88 + 0x20 + read-write + 0x00000000 + + + DT30 + BPR data30 + 0 + 16 + + + + + DT31 + DT31 + Battery powered domain data + register (BPR_DTx) + 0x8C + 0x20 + read-write + 0x00000000 + + + DT31 + BPR data31 + 0 + 16 + + + + + DT32 + DT32 + Battery powered domain data + register (BPR_DTx) + 0x90 + 0x20 + read-write + 0x00000000 + + + DT32 + BPR data32 + 0 + 16 + + + + + DT33 + DT33 + Battery powered domain data + register (BPR_DTx) + 0x94 + 0x20 + read-write + 0x00000000 + + + DT33 + BPR data33 + 0 + 16 + + + + + DT34 + DT34 + Battery powered domain data + register (BPR_DTx) + 0x98 + 0x20 + read-write + 0x00000000 + + + DT34 + BPR data34 + 0 + 16 + + + + + DT35 + DT35 + Battery powered domain data + register (BPR_DTx) + 0x9C + 0x20 + read-write + 0x00000000 + + + DT35 + BPR data35 + 0 + 16 + + + + + DT36 + DT36 + Battery powered domain data + register (BPR_DTx) + 0xA0 + 0x20 + read-write + 0x00000000 + + + DT36 + BPR data36 + 0 + 16 + + + + + DT37 + DT37 + Battery powered domain data + register (BPR_DTx) + 0xA4 + 0x20 + read-write + 0x00000000 + + + DT37 + BPR data37 + 0 + 16 + + + + + DT38 + DT38 + Battery powered domain data + register (BPR_DTx) + 0xA8 + 0x20 + read-write + 0x00000000 + + + DT38 + BPR data38 + 0 + 16 + + + + + DT39 + DT39 + Battery powered domain data + register (BPR_DTx) + 0xAC + 0x20 + read-write + 0x00000000 + + + DT39 + BPR data39 + 0 + 16 + + + + + DT40 + DT40 + Battery powered domain data + register (BPR_DTx) + 0xB0 + 0x20 + read-write + 0x00000000 + + + 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Channel 2 output buffer enable + 11 + 1 + + + C2OIEN + Channel 2 output immediately enable + 10 + 1 + + + C2C + Channel 2 configure + 8 + 2 + + + C1OSEN + Channel 1 output switch enable + 7 + 1 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C2DF + Channel 2 digital filter + 12 + 4 + + + C2IDIV + Channel 2 input divider + 10 + 2 + + + C2C + Channel 2 configure + 8 + 2 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM2_OUTPUT + CM2_OUTPUT + Channel output mode register 2 + 0x1C + 0x20 + read-write + 0x00000000 + + + C4OSEN + Channel 4 output switch enable + 15 + 1 + + + C4OCTRL + Channel 4 output control + 12 + 3 + + + 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0x00000000 + + + C4DT + Channel 4 data register + 0 + 16 + + + + + DMACTRL + DMACTRL + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DTB + DMA transfer bytes + 8 + 5 + + + ADDR + DMA transfer address offset + 0 + 5 + + + + + DMADT + DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + + + TMR4 + 0x40000800 + + TMR4 + TMR4 global interrupt + 30 + + + + TMR5 + 0x40000C00 + + TMR5 + TMR5 global interrupt + 50 + + + + TMR9 + General purpose timer + TIMER + 0x40014C00 + + 0x0 + 0x400 + registers + + + TMR1_BRK_TMR9 + TMR1 brake interrupt and TMR9 global + interrupt + 24 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + STCTRL + STCTRL + Subordinate TMR control register + 0x8 + 0x20 + read-write + 0x0000 + + + STIS + Subordinate TMR input selection + 4 + 3 + + + SMSEL + Subordinate TMR mode selection + 0 + 3 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + TIEN + Trigger interrupt enable + 6 + 1 + + + C2IEN + Channel 2 interrupt + enable + 2 + 1 + + + C1IEN + Channel 1 interrupt + enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C2RF + Channel 2 recapture flag + 10 + 1 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + TRGIF + Trigger interrupt flag + 6 + 1 + + + C2IF + Channel 2 interrupt flag + 2 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + TRGSWTR + Trigger event triggered by software + 6 + 1 + + + C2SWTR + Channel 2 event triggered by software + 2 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C2OCTRL + Channel 2 output control + 12 + 3 + + + C2OBEN + Channel 2 output buffer enable + 11 + 1 + + + C2OIEN + Channel 2 output immediately enable + 10 + 1 + + + C2C + Channel 2 configure + 8 + 2 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C2DF + Channel 2 digital filter + 12 + 4 + + + C2IDIV + Channel 2 input divider + 10 + 2 + + + C2C + Channel 2 configure + 8 + 2 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C2CP + Channel 2 complementary polarity + 7 + 1 + + + C2CEN + Channel 2 complementary enable + 6 + 1 + + + C2P + Channel 2 Polarity + 5 + 1 + + + C2EN + Channel 2 enable + 4 + 1 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1CEN + Channel 1 complementary enable + 2 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + C2DT + C2DT + Channel 2 data register + 0x38 + 0x20 + read-write + 0x00000000 + + + C2DT + Channel 2 data register + 0 + 16 + + + + + + + TMR12 + 0x40001800 + + TMR8_BRK_TMR12 + TMR8 brake interrupt and TMR12 global + interrupt + 43 + + + + TMR10 + General purpose timer + TIMER + 0x40015000 + + 0x0 + 0x400 + registers + + + TMR1_OVF_TMR10 + TMR1 overflow interrupt and TMR10 global + interrupt + 25 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + C1IEN + Channel 1 interrupt + enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + + + TMR11 + 0x40015400 + + TMR1_TRG_HALL_TMR11 + TMR1 trigger and HALL interrupts and + TMR11 global interrupt + 26 + + + + ACC + HICK Auto Clock Calibration + ACC + 0x40015800 + + 0x0 + 0x400 + registers + + + + STS + STS + status register + 0x0 + 0x20 + 0x0000 + + + RSLOST + Reference Signal Lost + read-write + 1 + 1 + + + CALRDY + Internal high-speed clock calibration ready + read-write + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x04 + 0x20 + 0x0100 + + + STEP + STEP + read-write + 8 + 4 + + + CALRDYIEN + CALRDY interrupt enable + read-write + 5 + 1 + + + EIEN + RSLOST error interrupt enable + read-write + 4 + 1 + + + ENTRIM + Enable trim + read-write + 1 + 1 + + + CALON + Calibration on + read-write + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x08 + 0x20 + 0x2080 + + + HICKTWK + Internal high-speed auto clock trimming + read-only + 8 + 6 + + + HICKCAL + Internal high-speed auto clock calibration + read-only + 0 + 8 + + + + + C1 + C1 + compare value 1 + 0x0C + 0x20 + 0x1F2C + + + C1 + Compare 1 + read-write + 0 + 16 + + + + + C2 + C2 + compare value 2 + 0x10 + 0x20 + 0x1F40 + + + C2 + Compare 2 + read-write + 0 + 16 + + + + + C3 + C3 + compare value 3 + 0x14 + 0x20 + 0x1F54 + + + C3 + Compare 3 + read-write + 0 + 16 + + + + + + + TMR13 + 0x40001C00 + + TMR8_OVF_TMR13 + TMR8 overflow interrupt and TMR13 global + interrupt + 44 + + + + TMR14 + 0x40002000 + + TMR8_TRG_HALL_TMR14 + TMR8 trigger and HALL interrupts and + TMR14 global interrupt + 45 + + + + TMR6 + Basic timer + TIMER + 0x40001000 + + 0x0 + 0x400 + registers + + + TMR6 + TMR6 global interrupt + 54 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + PTOS + Primary TMR output selection + 4 + 3 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + + + TMR7 + 0x40001400 + + TMR7 + TMR7 global interrupt + 55 + + + + I2C1 + Inter integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EVT + I2C1 event interrupt + 31 + + + I2C1_ERR + I2C1 error interrupt + 32 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + RESET + I2C peripheral reset + 15 + 1 + + + SMBALERT + SMBus alert pin set + 13 + 1 + + + PECTEN + Request PEC transmission enable + 12 + 1 + + + MACKCTRL + Master receiving mode acknowledge control + 11 + 1 + + + ACKEN + Acknowledge enable + 10 + 1 + + + GENSTOP + Stop generation + 9 + 1 + + + GENSTART + Start generation + 8 + 1 + + + STRETCH + Clock stretching mode + 7 + 1 + + + GCAEN + General call address enable + 6 + 1 + + + PECEN + PEC calculation enable + 5 + 1 + + + ARPEN + SMBus address resolution protocol enable + 4 + 1 + + + SMBMODE + SMBus device mode + 3 + 1 + + + PERMODE + I2C peripheral mode + 1 + 1 + + + I2CEN + Peripheral enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + DMAEND + DMA transfer end indication + 12 + 1 + + + DMAEN + DMA transfer enable + 11 + 1 + + + DATAIEN + Data transmission interrupt enable + 10 + 1 + + + EVTIEN + Event interrupt enable + 9 + 1 + + + ERRIEN + Error interrupt enable + 8 + 1 + + + CLKFREQ + Input clock frequency + 0 + 8 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + ADDR1MODE + Address mode + 15 + 1 + + + ADDR1 + Own address 1 + 0 + 10 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x0000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2EN + Own address 2 enable + 0 + 1 + + + + + DT + DT + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + DT + data register + 0 + 8 + + + + + STS1 + STS1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + ALERTF + SMBus alert + 15 + 1 + read-write + + + TMOUT + Timeout error + 14 + 1 + read-write + + + PECERR + PEC receive error + 12 + 1 + read-write + + + OUF + Overflow or underflow + 11 + 1 + read-write + + + ACKFAIL + Acknowledge failure + 10 + 1 + read-write + + + ARLOST + Arbitration lost (master + mode) + 9 + 1 + read-write + + + BUSERR + Bus error + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + (transmitters) + 7 + 1 + read-only + + + RDBF + Receive data buffer full + (receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slave + mode) + 4 + 1 + read-only + + + ADDRHF + address header match (Master + mode) + 3 + 1 + read-only + + + TDC + Transmit data complete + 2 + 1 + read-only + + + ADDR7F + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + + STARTF + Start bit (Master mode) + 0 + 1 + read-only + + + + + STS2 + STS2 + Status register 2 + 0x18 + 0x20 + read-only + 0x0000 + + + PECVAL + PEC value + 8 + 8 + + + ADDR2F + Received address 2 + 7 + 1 + + + HOSTADDRF + SMBus host address receiving + 6 + 1 + + + DEVADDRF + SMBus device address receiving + 5 + 1 + + + GCADDRF + General call address reception + 4 + 1 + + + DIRF + Transmission direction + 2 + 1 + + + BUSYF + Bus busy + 1 + 1 + + + TRMODE + Transmission mode + 0 + 1 + + + + + CLKCTRL + CLKCTRL + Clock control register + 0x1C + 0x20 + read-write + 0x0000 + + + SPEEDMODE + Speed mode selection + 15 + 1 + + + DUTYMODE + Fast mode duty cycle + 14 + 1 + + + SPEED + I2C bus speed config + 0 + 12 + + + + + TMRISE + TMRISE + TRISE register + 0x20 + 0x20 + read-write + 0x0002 + + + RISETIME + I2C bus rise time + 0 + 6 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 33 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + I2C3 + 0x40015C00 + + I2C3_EVT + I2C3 event interrupt + 61 + + + I2C3_ERR + I2C3 error interrupt + 62 + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + SPI4 + 0x40004000 + + SPI4 + SPI4 global interrupt + 63 + + + + I2S2_EXT + 0x40016C00 + + + I2S3_EXT + 0x40017000 + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + UEN + USART enable + 13 + 1 + + + DBN + Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + ID + USART identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + USART6 + 0x40016000 + + USART6 + USART6 global interrupt + 76 + + + + ADC1 + Analog to digital converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + MSSEL + Master slave mode select + 16 + 4 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 25 + 1 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 24 + 1 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + OCDMAEN + DMA transfer enable of ordinary channels + 8 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ADC2ODT + ADC2 conversion data of ordinary channel + 16 + 16 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + + + ADC2 + Analog to digital converter + ADC + 0x40012800 + + 0x0 + 0x400 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 25 + 1 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 24 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + + + ADC3 + Analog to digital converter + ADC + 0x40013C00 + + 0x0 + 0x400 + registers + + + ADC3 + ADC3 global interrupt + 47 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 25 + 1 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 24 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + OCDMAEN + DMA transfer enable of ordinary channels + 8 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + USBFS_H_CAN1_TX + CAN1 TX interrupt + 19 + + + USBFS_L_CAN1_RX0 + CAN1 RX0 interrupt + 20 + + + CAN_RX1 + CAN1 RX1 interrupt + 21 + + + CAN_SE + CAN1 SE interrupt + 22 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RF0R + Receive FIFO 0 release + 5 + 1 + read-write + + + RF0OF + Receive FIFO 0 overflow flag + 4 + 1 + read-write + + + RF0FF + Receive FIFO 0 full flag + 3 + 1 + read-write + + + RF0MN + Receive FIFO 0 message num + 0 + 2 + read-only + + + + + RF1 + RF1 + Receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RF1R + Receive FIFO 1 release + 5 + 1 + read-write + + + RF1OF + Receive FIFO 1 overflow flag + 4 + 1 + read-write + + + RF1FF + Receive FIFO 1 full flag + 3 + 1 + read-write + + + RF1MN + Receive FIFO 1 message num + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + EDZIEN + Enter doze mode interrupt enable + 17 + 1 + + + QDZIEN + Quit doze mode interrupt enable + 16 + 1 + + + EOIEN + Error occur interrupt enable + 15 + 1 + + + ETRIEN + Error type record interrupt enable + 11 + 1 + + + BOIEN + Bus-off interrupt enable + 10 + 1 + + + EPIEN + Error passive interrupt enable + 9 + 1 + + + EAIEN + Error active interrupt enable + 8 + 1 + + + RF1OIEN + Receive FIFO 1 overflow interrupt enable + 6 + 1 + + + RF1FIEN + Receive FIFO 1 full interrupt enable + 5 + 1 + + + RF1MIEN + FIFO 1 receive message interrupt enable + 4 + 1 + + + RF0OIEN + Receive FIFO 0 overflow interrupt enable + 3 + 1 + + + RF0FIEN + Receive FIFO 0 full interrupt enable + 2 + 1 + + + RF0MIEN + FIFO 0 receive message interrupt enable + 1 + 1 + + + TCIEN + Transmission complete interrupt enable + 0 + 1 + + + + + ESTS + ESTS + Error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Transmit error counter + 16 + 8 + read-only + + + ETR + Error type record + 4 + 3 + read-write + + + BOF + Bus-off flag + 2 + 1 + read-only + + + EPF + Error passive flag + 1 + 1 + read-only + + + EAF + Error active flag + 0 + 1 + read-only + + + + + BTMG + BTMG + Bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOEN + Listen-Only mode + 31 + 1 + + + LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB2 + F1FB2 + Filter bank 1 filtrate bit register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB1 + F2FB1 + Filter bank 2 filtrate bit register 1 + 0x250 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 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Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F10FB1 + F10FB1 + Filter bank 10 filtrate bit register 1 + 0x290 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F10FB2 + F10FB2 + Filter bank 10 filtrate bit register 2 + 0x294 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F11FB1 + F11FB1 + Filter bank 11 filtrate bit register 1 + 0x298 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F11FB2 + F11FB2 + Filter bank 11 filtrate bit register 2 + 0x29C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F12FB1 + F12FB1 + Filter bank 12 filtrate bit filtrate bit register 1 + 0x2A0 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + 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data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB1 + F13FB1 + Filter bank 13 filtrate bit filtrate bit register 1 + 0x2A8 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB2 + F13FB2 + Filter bank 13 filtrate bit filtrate bit register 2 + 0x2AC + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + + + CAN2 + 0x40006800 + + CAN2_TX + CAN2 TX interrupt + 68 + + + CAN2_RX0 + CAN2 RX0 interrupt + 69 + + + CAN2_RX1 + CAN2 RX1 interrupt + 70 + + + CAN2_SE + CAN2 SE interrupt + 71 + + + + DAC + Digital to analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Control register (DAC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + D1EN + DAC1 enable + 0 + 1 + + + D1OBDIS + DAC1 output buffer disable + 1 + 1 + + + D1TRGEN + DAC1 trigger enable + 2 + 1 + + + D1TRGSEL + DAC1 trigger selection + 3 + 3 + + + D1NM + DAC1 noise/triangle wave generation enable + 6 + 2 + + + D1NBSEL + DAC1 mask/amplitude selector + 8 + 4 + + + D1DMAEN + DAC1 DMA enable + 12 + 1 + + + D2EN + DAC2 enable + 16 + 1 + + + D2OBDIS + DAC2 output buffer disable + 17 + 1 + + + D2TRGEN + DAC2 trigger enable + 18 + 1 + + + D2TRGSEL + DAC2 trigger selection + 19 + 3 + + + D2NM + DAC2 noise/triangle wave generation enable + 22 + 2 + + + D2NBSEL + DAC2 mask/amplitude selector + 24 + 4 + + + D2DMAEN + DAC2 DMA enable + 28 + 1 + + + + + SWTRG + SWTRG + DAC software trigger register(DAC_SWTRIGR) + 0x4 + 0x20 + write-only + 0x00000000 + + + D1SWTRG + DAC1 software trigger + 0 + 1 + + + D2SWTRG + DAC2 software trigger + 1 + 1 + + + + + D1DTH12R + D1DTH12R + DAC1 12-bit right-aligned data holding register(DAC_D1DTH12R) + 0x8 + 0x20 + read-write + 0x00000000 + + + D1DT12R + DAC1 12-bit right-aligned data + 0 + 12 + + + + + D1DTH12L + D1DTH12L + DAC1 12-bit left aligned data holding register (DAC_D1DTH12L) + 0xC + 0x20 + read-write + 0x00000000 + + + D1DT12L + DAC1 12-bit left-aligned data + 4 + 12 + + + + + D1DTH8R + D1DTH8R + DAC1 8-bit right aligned data holding register (DAC_D1DTH8R) + 0x10 + 0x20 + read-write + 0x00000000 + + + D1DT8R + DAC1 8-bit right-aligned data + 0 + 8 + + + + + D2DTH12R + D2DTH12R + DAC2 12-bit right aligned data holding register (DAC_D2DTH12R) + 0x14 + 0x20 + read-write + 0x00000000 + + + D2DT12R + DAC2 12-bit right-aligned + data + 0 + 12 + + + + + D2DTH12L + D2DTH12L + DAC2 12-bit left aligned data holding register (DAC_D2DTH12L) + 0x18 + 0x20 + read-write + 0x00000000 + + + D2DT12L + DAC2 12-bit left-aligned data + 4 + 12 + + + + + D2DTH8R + D2DTH8R + DAC2 8-bit right-aligned data holding register (DAC_D2DTH8R) + 0x1C + 0x20 + read-write + 0x00000000 + + + D2DT8R + DAC2 8-bit right-aligned + data + 0 + 8 + + + + + DDTH12R + DDTH12R + Dual DAC 12-bit right-aligned data holding register (DAC_DDTH12R), Bits 31:28 Reserved, Bits 15:12 Reserved + 0x20 + 0x20 + read-write + 0x00000000 + + + DD1DT12R + DAC1 12-bit right-aligned data + 0 + 12 + + + DD2DT12R + DAC2 12-bit right-aligned data + 16 + 12 + + + + + DDTH12L + DDTH12L + DUAL DAC 12-bit left aligned data holding register (DAC_DDTH12L), Bits 19:16 Reserved, Bits 3:0 Reserved + 0x24 + 0x20 + read-write + 0x00000000 + + + DD1DT12L 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Universal asynchronous receiver transmitter + 0x40004C00 + + UART4 + UART4 global interrupt + 52 + + + + UART5 + Universal asynchronous receiver transmitter + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + UART7 + Universal asynchronous receiver transmitter + 0x40016400 + + UART7 + UART7 global interrupt + 77 + + + + UART8 + Universal asynchronous receiver transmitter + 0x40016800 + + UART8 + UART8 global interrupt + 78 + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DT + DT + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DT + Data Register + 0 + 32 + + + + + CDT + CDT + Common data register + 0x4 + 0x20 + read-write + 0x00000000 + + + CDT + Common Data + 0 + 1 + + + + + CTRL + CTRL + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RST + Reset bit + 0 + 1 + + + REVID + Reverse input data + 5 + 2 + + + REVOD + Reverse output data + 7 + 1 + + + + + IDT + IDT + Initial data register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + IDT + Initial Data + 0 + 32 + + + + + + + FLASH + Flash memory controler + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + PSR + PSR + Performance selection register + 0x0 + 0x20 + 0x00000030 + + + + + UNLOCK + UNLOCK + Unlock register + 0x4 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + USD_UNLOCK + USD_UNLOCK + USD unlock register + 0x8 + 0x20 + write-only + 0x00000000 + + + USD_UKVAL + User system data Unlock key value + 0 + 32 + + + + + STS + STS + Status register + 0xC + 0x20 + 0x00000000 + + + ODF + Operate done flag + 5 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + PRGMERR + program error + 2 + 1 + read-write + + + OBF + Operate busy flag + 0 + 1 + read-only + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + USDPRGM + User system data program + 4 + 1 + + + USDERS + User system data erase + 5 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + USDULKS + User system data unlock success + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR + ADDR + Address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + USD + USD + User system data register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + USDERR + User system data error + 0 + 1 + + + FAP + FLASH access protection + 1 + 1 + + + nWDT_ATO_EN + WDT auto enable + 2 + 1 + + + nDEPSLP_RST + Deepsleep reset + 3 + 1 + + + nSTDBY_RST + Standby reset + 4 + 1 + + + BTOPT + boot option + 5 + 1 + + + USER_D0 + User data 0 + 10 + 8 + + + USER_D1 + User data 1 + 18 + 8 + + + + + EPPS + EPPS + Erase/program protection status register + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + UNLOCK2 + UNLOCK2 + Unlock 2 register + 0x44 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + STS2 + STS2 + Status 2 register + 0x4C + 0x20 + 0x00000000 + + + OBF + Operate busy flag + 0 + 1 + read-only + + + PRGMERR + program error + 2 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + ODF + Operate done flag + 5 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control 2 register + 0x50 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR2 + ADDR2 + Address 2 register + 0x54 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + UNLOCK3 + UNLOCK3 + Unlock 3 register + 0x84 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + SELECT + SELECT + Select register + 0x88 + 0x20 + write-only + 0x00000000 + + + SELECT + spim type selection + 0 + 32 + + + + + STS3 + STS3 + Status 3 register + 0x8C + 0x20 + 0x00000000 + + + OBF + Operate busy flag + 0 + 1 + read-only + + + PRGMERR + program error + 2 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + ODF + Operate done flag + 5 + 1 + read-write + + + + + CTRL3 + CTRL3 + Control 3 register + 0x90 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + CHPERS + Chip erase + 2 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR3 + ADDR3 + Address 3 register + 0x94 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + DA + DA + Spim decryption address + 0x98 + 0x20 + write-only + 0x00000000 + + + FDA + Flash decryption address + 0 + 32 + + + + + SLIB_STS0 + SLIB_STS0 + sLib status 0 register + 0xCC + 0x20 + 0x00000000 + + + SLIB_ENF + sLib enabled flag + 3 + 1 + read-only + + + + + SLIB_STS1 + SLIB_STS1 + sLib status 1 register + 0xD0 + 0x20 + 0x00000000 + + + SLIB_SS + sLib start sector + 0 + 11 + read-only + + + SLIB_DAT_SS + sLib data start sector + 11 + 11 + read-only + + + SLIB_ES + sLib end sector + 22 + 10 + read-only + + + + + SLIB_PWD_CLR + SLIB_PWD_CLR + SLIB password clear register + 0xD4 + 0x20 + 0x00000000 + write-only + + + SLIB_PCLR_VAL + sLib password clear value + 0 + 32 + + + + + SLIB_MISC_STS + SLIB_MISC_STS + sLib misc status register + 0xD8 + 0x20 + 0x01000000 + + + SLIB_PWD_ERR + sLib password error + 0 + 1 + read-only + + + SLIB_PWD_OK + sLib password ok + 1 + 1 + read-only + + + SLIB_ULKF + sLib unlock flag + 2 + 1 + read-only + + + SLIB_RCNT + sLib remaining count + 16 + 9 + read-only + + + + + SLIB_SET_PWD + SLIB_SET_PWD + sLib password setting register + 0xDC + 0x20 + 0x00000000 + write-only + + + SLIB_PSET_VAL + sLib password setting val + 0 + 32 + + + + + SLIB_SET_RANGE + SLIB_SET_RANGE + Configure sLib range register + 0xE0 + 0x20 + 0x00000000 + write-only + + + SLIB_SS_SET + sLib start sector setting,valid input: 0~511 + 0 + 11 + + + SLIB_DSS_SET + sLib data start sector setting,valid input: 0~511, 0 means no data area + 11 + 11 + + + SLIB_ES_SET + sLib end sector setting,valid input: 0~511 + 22 + 10 + + + + + SLIB_UNLOCK + SLIB_UNLOCK + sLib unlock register + 0xF0 + 0x20 + 0x00000000 + write-only + + + SLIB_UKVAL + sLib unlock key value + 0 + 32 + + + + + CRC_CTRL + CRC_CTRL + CRC controler register + 0xF4 + 0x20 + 0x00000000 + write-only + + + CRC_SS + CRC start sector + 0 + 12 + + + CRC_SN + CRC sector numbler + 12 + 12 + + + CRC_STRT + CRC start + 31 + 1 + + + + + CRC_CHKR + CRC_CHKR + CRC check result register + 0xF8 + 0x20 + 0x00000000 + read-only + + + CRC_CHKR + CRC check result + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + USBFS + Universal serial bus full-speed device + interface + USBFS + 0x40005C00 + + 0x0 + 0x400 + registers + + + + EPT0 + EPT0 + endpoint 0 register + 0x0 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT1 + EPT1 + endpoint 1 register + 0x4 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT2 + EPT2 + endpoint 2 register + 0x8 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT3 + EPT3 + endpoint 3 register + 0xC + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT4 + EPT4 + endpoint 4 register + 0x10 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT5 + EPT5 + endpoint 5 register + 0x14 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT6 + EPT6 + endpoint 6 register + 0x18 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT7 + EPT7 + endpoint 7 register + 0x1C + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + CTRL + CTRL + control register + 0x40 + 0x20 + read-write + 0x00000003 + + + CSRST + Core soft reset + 0 + 1 + + + DISUSB + Disable usb phy + 1 + 1 + + + LPM + Low power mode + 2 + 1 + + + SSP + Soft suspend config + 3 + 1 + + + GRESUME + Generate resume request + 4 + 1 + + + LSOFIEN + Lost start of frame interrupt enable + 8 + 1 + + + SOFIEN + Start of frame interrupt + enable + 9 + 1 + + + RSTIEN + Bus reset interrupt enable + 10 + 1 + + + SPIEN + Bus suspend mode interrupt + enable + 11 + 1 + + + WKIEN + Wakeup/Remote wakeup interrupt enable + 12 + 1 + + + BEIEN + Bus error interrupt enable + 13 + 1 + + + UCFORIEN + USB Core fifo overrun + interrupt enable + 14 + 1 + + + TCIEN + transmission completed interrupt + enable + 15 + 1 + + + + + INTSTS + INTSTS + interrupt status register + 0x44 + 0x20 + read-write + 0x00000000 + + + EPT_NUM + Endpoint number + 0 + 4 + + + INOUT + In/Out transaction + 4 + 1 + + + LSOF + Lost start of frame + 8 + 1 + + + SOF + start of frame + 9 + 1 + + + RST + Bus reset + 10 + 1 + + + SP + Bus suspend + 11 + 1 + + + WK + Wakeup + 12 + 1 + + + BE + Bus error + 13 + 1 + + + UCFOR + USB core fifo overrun memory + 14 + 1 + + + TC + transaction completed + 15 + 1 + + + + + SOFRNUM + SOFRNUM + frame number register + 0x48 + 0x20 + read-write + 0x0000 + + + SOFNUM + Start of frame number + 0 + 11 + + + LSOFNUM + Lost start of frame number + 11 + 2 + + + CLCK + Connect locked + 13 + 1 + + + DMSTS + DM status + 14 + 1 + + + DPSTS + DP status + 15 + 1 + + + + + DEVADDR + DEVADDR + device address + 0x4C + 0x20 + read-write + 0x0000 + + + ADDR + Host assign device address + 0 + 7 + + + CEN + USB core enable + 7 + 1 + + + + + BUFTBL + BUFTBL + Buffer table address + 0x50 + 0x20 + read-write + 0x0000 + + + BTADDR + Endpoint buffer table start address + 3 + 13 + + + + + CFG + CFG + CFG control register + 0x60 + 0x20 + read-write + 0x0000 + + + PUO + DP pullup off + 1 + 1 + + + SOFOUTEN + SOF output enable + 0 + 1 + + + + + + + ETHERNET_MAC + Ethernet: media access control + ETHERNET + 0x40028000 + + 0x0 + 0x100 + registers + + + EMAC + Ethernet mac global interrupt + 79 + + + + MACCTRL + MACCTRL + Ethernet MAC configuration register + 0x0 + 0x20 + read-write + 0x00008000 + + + RE + Receiver enable + 2 + 1 + + + TE + Transmitter enable + 3 + 1 + + + DC + Deferral check + 4 + 1 + + + BL + Back-off limit + 5 + 2 + + + ACS + Automatic pad/CRC + stripping + 7 + 1 + + + DR + Disable retry + 9 + 1 + + + IPC + IPv4 checksum offload + 10 + 1 + + + DM + Duplex mode + 11 + 1 + + + LM + Loopback mode + 12 + 1 + + + DRO + Disable receive own + 13 + 1 + + + FES + Fast EMAC speed + 14 + 1 + + + DCS + Disable carrier sense + 16 + 1 + + + IFG + Interframe gap + 17 + 3 + + + JD + Jabber disable + 22 + 1 + + + WD + Watchdog disable + 23 + 1 + + + + + MACFRMF + MACFRMF + Ethernet MAC frame filter register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Promiscuous mode + 0 + 1 + + + HUC + Hash unicast + 1 + 1 + + + HMC + Hash multicast + 2 + 1 + + + DAIF + Destination address inverse + filtering + 3 + 1 + + + PMC + Pass multicast + 4 + 1 + + + DBF + Disable broadcast frames + 5 + 1 + + + PCF + Pass control frames + 6 + 2 + + + SAIF + Source address inverse + filtering + 8 + 1 + + + SAF + Source address filter + 9 + 1 + + + HPF + Hash or perfect filter + 10 + 1 + + + RA + Receive all + 31 + 1 + + + + + MACHTH + MACHTH + Ethernet MAC hash table high register + 0x8 + 0x20 + read-write + 0x00000000 + + + HTH + Hash table high + 0 + 32 + + + + + MACHTL + MACHTL + Ethernet MAC hash table low register + 0xC + 0x20 + read-write + 0x00000000 + + + HTL + Hash table low + 0 + 32 + + + + + MACMIIADDR + MACMIIADDR + Ethernet MAC MII address register + 0x10 + 0x20 + read-write + 0x00000000 + + + MB + MII busy + 0 + 1 + + + MW + MII write + 1 + 1 + + + CR + Clock range + 2 + 3 + + + MII + MII register + 6 + 5 + + + PA + PHY address + 11 + 5 + + + + + MACMIIDT + MACMIIDT + Ethernet MAC MII data register + 0x14 + 0x20 + read-write + 0x00000000 + + + MD + MII data + 0 + 16 + + + + + MACFCTRL + MACFCTRL + Ethernet MAC flow control register + 0x18 + 0x20 + read-write + 0x00000000 + + + FCB_BPA + Flow control busy/back pressure + activate + 0 + 1 + + + ETF + Enable transmit flow control + + 1 + 1 + + + ERF + Enable receive flow control + + 2 + 1 + + + DUP + Detect unicast pause frame + 3 + 1 + + + PLT + Pause low threshold + 4 + 2 + + + DZQP + Disable zero-quanta pause + 7 + 1 + + + PT + Pass time + 16 + 16 + + + + + MACVLT + MACVLT + Ethernet MAC VLAN tag register + 0x1C + 0x20 + read-write + 0x00000000 + + + VTI + VLAN tag identifier (for receive + frames) + 0 + 16 + + + ETV + Enable 12-bit VLAN tag comparison + 16 + 1 + + + + + MACRWFF + MACRWFF + Ethernet MAC remote wakeup frame filter register + 0x28 + 0x20 + read-write + 0x00000000 + + + MACPMTCTRLSTS + MACPMTCTRLSTS + Ethernet MAC PMT control and status register + 0x2C + 0x20 + read-write + 0x00000000 + + + PD + Power down + 0 + 1 + + + EMP + Enable magic packet + 1 + 1 + + + ERWF + Enable remote wakeup frame + 2 + 1 + + + RMP + Received magic packet + 5 + 1 + + + RRWF + Recevied remote wakeup frame + 6 + 1 + + + GUC + Global unicast + 9 + 1 + + + RWFFPR + Remote wakeup frame filter register pointer + reset + 31 + 1 + + + + + MACISTS + MACISTS + Ethernet MAC interrupt status register + 0x38 + 0x20 + read-write + 0x00000000 + + + PIS + PMT interrupt status + 3 + 1 + + + MIS + MMC interrupt status + 4 + 1 + + + MRIS + MMC receive interrupt status + 5 + 1 + + + MTIS + MMC transmit interrupt status + 6 + 1 + + + TIS + Timestamp interrupt status + 9 + 1 + + + + + MACIMR + MACIMR + Ethernet MAC interrupt mask register + 0x3C + 0x20 + read-write + 0x00000000 + + + PIM + PMT interrupt mask + 3 + 1 + + + TIM + Timestamp interrupt mask + 9 + 1 + + + + + MACA0H + MACA0H + Ethernet MAC address 0 high register + 0x40 + 0x20 + 0x0010FFFF + + + MA0H + MAC address0 high + 0 + 16 + read-write + + + AE + Address enable + 31 + 1 + read-only + + + + + MACA0L + MACA0L + Ethernet MAC address 0 low register + 0x44 + 0x20 + read-write + 0xFFFFFFFF + + + MA0L + MAC address0 low + 0 + 32 + + + + + MACA1H + MACA1H + Ethernet MAC address 1 high register + 0x48 + 0x20 + read-write + 0x0000FFFF + + + MA1H + MAC address1 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA1L + MACA1L + Ethernet MAC address1 low register + 0x4C + 0x20 + read-write + 0xFFFFFFFF + + + MA1L + MAC address1 low + 0 + 32 + + + + + MACA2H + MACA2H + Ethernet MAC address 2 high register + 0x50 + 0x20 + read-write + 0x0050 + + + MA2H + MAC address 2 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA2L + MACA2L + Ethernet MAC address 2 low register + 0x54 + 0x20 + read-write + 0xFFFFFFFF + + + MA2L + MAC address2 low + 0 + 31 + + + + + MACA3H + MACA3H + Ethernet MAC address 3 high register + 0x58 + 0x20 + read-write + 0x0000FFFF + + + MA3H + MAC address3 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA3L + MACA3L + Ethernet MAC address 3 low register + 0x5C + 0x20 + read-write + 0xFFFFFFFF + + + MA3L + MAC address3 low + 0 + 32 + + + + + + + ETHERNET_MMC + Ethernet: MAC management counters + ETHERNET + 0x40028100 + + 0x0 + 0x100 + registers + + + + MMCCTRL + MMCCTRL + Ethernet MMC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + RC + Reset counter + 0 + 1 + + + SCR + Stop counter rollover + 1 + 1 + + + RR + Reset on read + 2 + 1 + + + FMC + Freeze MMC counter + 31 + 1 + + + + + MMCRI + MMCRI + Ethernet MMC receive interrupt register + 0x4 + 0x20 + read-write + 0x00000000 + + + RFCE + Received frames CRC error + 5 + 1 + + + RFAE + Received frames alignment error + 6 + 1 + + + RGUF + Received good unicast frames + 17 + 1 + + + + + MMCTI + MMCTI + Ethernet MMC transmit interrupt register + 0x8 + 0x20 + read-write + 0x00000000 + + + TSCGFCI + Transmit single collision good frame + counter interrupt + 14 + 1 + + + TGFMSC + Transmit good frames more single + collision + 15 + 1 + + + TGF + Transmitted good frames + 21 + 1 + + + + + MMCRIM + MMCRIM + Ethernet MMC receive interrupt mask register + 0xC + 0x20 + read-write + 0x00000000 + + + RCEFCIM + Received CRC error frame counter interrupt + mask + 5 + 1 + + + RAEFACIM + Received alignment error frame alignment + counter interrupt mask + 6 + 1 + + + RUGFCIM + Received unicast good frame counter + interrupt mask + 17 + 1 + + + + + MMCTIM + MMCTIM + Ethernet MMC transmit interrupt mask register + 0x10 + 0x20 + read-write + 0x00000000 + + + TSCGFCIM + Transmit single collision good frame + counter interrupt mask + 14 + 1 + + + TMCGFCIM + Transmit multiple collision good frame + counter interrupt mask + 15 + 1 + + + TGFCIM + Transmitted good frame counter interrupt + mask + 21 + 1 + + + + + MMCTFSCC + MMCTFSCC + Ethernet MMC transmitted good frames after a single collision counter + 0x4C + 0x20 + read-only + 0x00000000 + + + TGFSCC + Transmitted good frames single + collision counter + 0 + 32 + + + + + MMCTFMSCC + MMCTFMSCC + Ethernet MMC transmitted good frames after more than a single collision + 0x50 + 0x20 + read-only + 0x00000000 + + + TGFMSCC + Transmitted good frame more single + collision counter + 0 + 32 + + + + + MMCTFCNT + MMCTFCNT + Ethernet MMC transmitted good frames counter register + 0x68 + 0x20 + read-only + 0x00000000 + + + TGFC + Transmitted good frames + counter + 0 + 32 + + + + + MMCRFCECNT + MMCRFCECNT + Ethernet MMC received frames with CRC error counter register + 0x94 + 0x20 + read-only + 0x00000000 + + + RFCEC + Received frames CRC error counter + 0 + 32 + + + + + MMCRFAECNT + MMCRFAECNT + Ethernet MMC received frames with alignment error counter register + 0x98 + 0x20 + read-only + 0x00000000 + + + RFAEC + Received frames alignment error counter + 0 + 32 + + + + + MMCRGUFCNT + MMCRGUFCNT + MMC received good unicast frames counter register + 0xC4 + 0x20 + read-only + 0x00000000 + + + RGUFC + Received good unicast frames + counter + 0 + 32 + + + + + + + ETHERNET_PTP + Ethernet: Precision time protocol + ETHERNET + 0x40028700 + + 0x0 + 0x100 + registers + + + + PTPTSCTRL + PTPTSCTRL + Ethernet PTP time stamp control register + 0x0 + 0x20 + read-write + 0x2000 + + + TE + Timestamp enable + 0 + 1 + + + TFCU + Timestamp fine or coarse + update + 1 + 1 + + + TI + Timestamp initialize + 2 + 1 + + + TU + Timestamp update + 3 + 1 + + + TITE + Timestamp interrupt trigger + enable + 4 + 1 + + + ARU + Addend register update + 5 + 1 + + + ETAF + Enable timestamp for all frames + 8 + 1 + + + TDBRC + Timestamp digital or binary + rollover control + 9 + 1 + + + EPPV2F + Enable PTP packet processing for + version2 format + 10 + 1 + + + EPPEF + Enable processing of PTP + over EMAC frames + 11 + 1 + + + EPPFSIP6U + Enable processing of PTP frames + sent over IPv6-UDP + 12 + 1 + + + EPPFSIP4U + Enable processing of PTP frames + sent over IPv4-UDP + 13 + 1 + + + ETSFEM + Enable timestamp snapshot for + event message + 14 + 1 + + + ESFMRTM + Enable snapshot for message + relevant to master + 15 + 1 + + + SPPFTS + Select PTP packet for taking snapshot + 16 + 2 + + + EMAFPFF + Enable MAC address for PTP frame filtering + 18 + 1 + + + + + PTPSSINC + PTPSSINC + Ethernet PTP subsecond increment register + 0x4 + 0x20 + read-write + 0x00000000 + + + SSIV + Sub-second increment value + 0 + 8 + + + + + PTPTSH + PTPTSH + Ethernet PTP time stamp high register + 0x8 + 0x20 + read-only + 0x00000000 + + + TS + Timestamp second + 0 + 32 + + + + + PTPTSL + PTPTSL + Ethernet PTP time stamp low register + 0xC + 0x20 + read-only + 0x00000000 + + + TSS + Timestamp subseconds + 0 + 31 + + + AST + Add or subtract time + 31 + 1 + + + + + PTPTSHUD + PTPTSHUD + Ethernet PTP time stamp high update register + 0x10 + 0x20 + read-write + 0x00000000 + + + TS + Timestamp second + 0 + 32 + + + + + PTPTSLUD + PTPTSLUD + Ethernet PTP time stamp low update register + 0x14 + 0x20 + read-write + 0x00000000 + + + TSS + Timestamp subseconds + 0 + 31 + + + AST + Add or subtract time + 31 + 1 + + + + + PTPTSAD + PTPTSAD + Ethernet PTP time stamp addend register + 0x18 + 0x20 + read-write + 0x00000000 + + + TAR + Timestamp addend register + 0 + 32 + + + + + PTPTTH + PTPTTH + Ethernet PTP target time high register + 0x1C + 0x20 + read-write + 0x00000000 + + + TTSR + Target time seconds register + 0 + 32 + + + + + PTPTTL + PTPTTL + Ethernet PTP target time low register + 0x20 + 0x20 + read-write + 0x00000000 + + + TTLR + Target timestamp low register + 0 + 32 + + + + + PTPTSSR + PTPTSSR + Ethernet PTP time stamp status register + 0x28 + 0x20 + read-only + 0x00000000 + + + TSO + Timestamp second overflow + 0 + 1 + + + TTTR + Timestamp target time reached + 1 + 1 + + + + + PTPPPSCR + PTPPPSCR + Ethernet PTP PPS control register + 0x2C + 0x20 + read-only + 0x00000000 + + + POFC + PPS Output frequency control + 0 + 4 + + + + + + + ETHERNET_DMA + Ethernet: DMA controller operation + ETHERNET + 0x40029000 + + 0x0 + 0x100 + registers + + + + DMABM + DMABM + Ethernet DMA bus mode register + 0x0 + 0x20 + read-write + 0x20101 + + + SWR + Software reset + 0 + 1 + + + DA + DMA Arbitration + 1 + 1 + + + DSL + Descriptor skip length + 2 + 5 + + + PBL + Programmable burst length + 8 + 6 + + + PR + Priority ratio + 14 + 2 + + + FB + Fixed burst + 16 + 1 + + + RDP + Rx DMA PBL + 17 + 6 + + + USP + Use separate PBL + 23 + 1 + + + PBLx8 + PNLx8 mode + 24 + 1 + + + AAB + Address-aligned beats + 25 + 1 + + + + + DMATPD + DMATPD + Ethernet DMA transmit poll demand register + 0x4 + 0x20 + read-write + 0x00000000 + + + TPD + Transmit poll demand + 0 + 32 + + + + + DMARPD + DMARPD + EHERNET DMA receive poll demand register + 0x8 + 0x20 + read-write + 0x00000000 + + + RPD + Receive poll demand + 0 + 32 + + + + + DMARDLADDR + DMARDLADDR + Ethernet DMA receive descriptor list address register + 0xC + 0x20 + read-write + 0x00000000 + + + SRL + Start of receive list + 0 + 32 + + + + + DMATDLADDR + DMATDLADDR + Ethernet DMA transmit descriptor list address register + 0x10 + 0x20 + read-write + 0x00000000 + + + STL + Start of transmit list + 0 + 32 + + + + + DMASTS + DMASTS + Ethernet DMA status register + 0x14 + 0x20 + 0x00000000 + + + TI + Transmit interrupt + 0 + 1 + read-write + + + TPS + Transmit process stopped + 1 + 1 + read-write + + + TBU + Transmit buffer unavailable + 2 + 1 + read-write + + + TJT + Transmit jabber timeout + 3 + 1 + read-write + + + OVF + Receive overflow + 4 + 1 + read-write + + + UNF + Transmit underflow + 5 + 1 + read-write + + + RI + Receive interrupt + 6 + 1 + read-write + + + RBU + Receive buffer unavailable + 7 + 1 + read-write + + + RPS + Receive process stopped + 8 + 1 + read-write + + + RWT + Receive watchdog timeout + 9 + 1 + read-write + + + ETI + Early transmit interrupt + 10 + 1 + read-write + + + FBEI + Fatal bus error interrupt + 13 + 1 + read-write + + + ERI + Early receive interrupt + 14 + 1 + read-write + + + AIS + Abnormal interrupt summary + 15 + 1 + read-write + + + NIS + Normal interrupt summary + 16 + 1 + read-write + + + RS + Receive process state + 17 + 3 + read-only + + + TS + Transmit process state + 20 + 3 + read-only + + + EB + Error bits + 23 + 3 + read-only + + + MMI + MAC MMC interrupt + 27 + 1 + read-only + + + MPI + MAC PMT interrupt + 28 + 1 + read-only + + + TTI + Timestamp trigger interrupt + 29 + 1 + read-only + + + + + DMAOPM + DMAOPM + Ethernet DMA operation mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + SSR + Start or stop receive + 1 + 1 + + + OSF + Operate on second frame + 2 + 1 + + + RTC + Receive threshold control + 3 + 2 + + + FUGF + Forward undersized good frames + 6 + 1 + + + FEF + Forward error frames + 7 + 1 + + + SSTC + Start of stop transmission command + 13 + 1 + + + TTC + Transmit threshold control + 14 + 3 + + + FTF + Flush transmit FIFO + 20 + 1 + + + TSF + Transmit store and forward + 21 + 1 + + + DFRF + Disable flushing of received + frames + 24 + 1 + + + RSF + Receive store and forward + 25 + 1 + + + DT + Disable dropping of TCP/IP + checksum error frames + 26 + 1 + + + + + DMAIE + DMAIE + Ethernet DMA interrupt enable register + 0x1C + 0x20 + read-write + 0x00000000 + + + TIE + Transmit interrupt enable + 0 + 1 + + + TSE + Transmit stopped enable + 1 + 1 + + + TUE + Transmit buffer unavailable enable + 2 + 1 + + + TJE + Transmit jabber timeout enable + 3 + 1 + + + OVE + Overflow interrupt enable + 4 + 1 + + + UNE + Underflow interrupt enable + 5 + 1 + + + RIE + Receive interrupt enable + 6 + 1 + + + RBUE + Receive buffer unavailable enable + 7 + 1 + + + RSE + Receive stopped enable + 8 + 1 + + + RWTE + receive watchdog timeout enable + 9 + 1 + + + EIE + Early transmit interrupt enable + 10 + 1 + + + FBEE + Fatal bus error enable + 13 + 1 + + + ERE + Early receive interrupt + enable + 14 + 1 + + + AIE + Abnormal interrupt enable + 15 + 1 + + + NIE + Normal interrupt enable + 16 + 1 + + + + + DMAMFBOCNT + DMAMFBOCNT + Ethernet DMA missed frame and buffer overflow counter register + 0x20 + 0x20 + read-only + 0x00000000 + + + MFC + Missed frames control + 0 + 16 + + + OBMFC + Overflow bit for missed frame + counter + 16 + 1 + + + OFC + Overflow frame counter + 17 + 11 + + + OBFOC + Overflow bit for FIFO overflow + counter + 28 + 1 + + + + + DMACTD + DMACTD + Ethernet DMA current host transmit descriptor register + 0x48 + 0x20 + read-only + 0x00000000 + + + HTDAP + Host transmit descriptor address pointer + 0 + 32 + + + + + DMACRD + DMACRD + Ethernet DMA current host receive descriptor register + 0x4C + 0x20 + read-only + 0x00000000 + + + HRDAP + Host receive descriptor address pointer + 0 + 32 + + + + + DMACTBADDR + DMACTBADDR + Ethernet DMA current host transmit buffer address register + 0x50 + 0x20 + read-only + 0x00000000 + + + HTBAP + Host transmit buffer address pointer + 0 + 32 + + + + + DMACRBADDR + DMACRBADDR + Ethernet DMA current host receive buffer address register + 0x54 + 0x20 + read-only + 0x00000000 + + + HRBAP + Host receive buffer address pointer + 0 + 32 + + + + + + + diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.h b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.h new file mode 100644 index 000000000..55d9d05dc --- /dev/null +++ b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.h @@ -0,0 +1,61 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// LED +#define LED_PORT GPIOD +#define LED_PIN GPIO_PINS_13 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +// UART +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK + +static inline void board_vbus_sense_init(void) +{ +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk new file mode 100644 index 000000000..58b3fdb11 --- /dev/null +++ b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F403AxG_FLASH.ld + +CFLAGS += \ + -DAT32F403ACGU7 diff --git a/hw/bsp/at32f403a_407/family.c b/hw/bsp/at32f403a_407/family.c new file mode 100644 index 000000000..23798526f --- /dev/null +++ b/hw/bsp/at32f403a_407/family.c @@ -0,0 +1,287 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f403a_407_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void usb_clock48m_select(usb_clk48_s clk_s); +void uart_print_init(uint32_t baudrate); + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USBFS_H_CAN1_TX_IRQHandler(void) { + tud_int_handler(0); +} +void USBFS_L_CAN1_RX0_IRQHandler(void) { + tud_int_handler(0); +} +void USBFS_MAPH_IRQHandler(void) { + tud_int_handler(0); +} +void USBFS_MAPL_IRQHandler(void) { + tud_int_handler(0); +} +void USBFSWakeUp_IRQHandler(void) { + tud_int_handler(0); +} + +void board_init(void) +{ + system_clock_config(); + + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HICK); + + /* configure systick */ + systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); + + /* enable usb clock */ + crm_periph_clock_enable(CRM_USB_PERIPH_CLOCK, TRUE); + + SysTick_Config(SystemCoreClock / 1000); +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USBFS_H_CAN1_TX_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFS_L_CAN1_RX0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFSWakeUp_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); + + uart_print_init(115200); + printf("usart printf config success!\r\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + switch(system_core_clock) + { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_1); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_1_5); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + /* 120MHz */ + case 120000000: + crm_usb_clock_div_set(CRM_USB_DIV_2_5); + break; + + /* 144MHz */ + case 144000000: + crm_usb_clock_div_set(CRM_USB_DIV_3); + break; + + /* 168MHz */ + case 168000000: + crm_usb_clock_div_set(CRM_USB_DIV_3_5); + break; + + /* 192MHz */ + case 192000000: + crm_usb_clock_div_set(CRM_USB_DIV_4); + break; + + default: + break; + + } + } +} + +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +void board_led_write(bool state) { + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) { + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + +int board_uart_read(uint8_t *buf, int len) { + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + + +#if CFG_TUSB_OS == OPT_OS_NONE + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + + uint32_t board_millis(void) + { + return system_ticks; + } + + void SVC_Handler(void) + { + } + + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/at32f403a_407/family.mk b/hw/bsp/at32f403a_407/family.mk new file mode 100644 index 000000000..4a1c3949c --- /dev/null +++ b/hw/bsp/at32f403a_407/family.mk @@ -0,0 +1,42 @@ +# Submodules +AT32F403A_407_SDK = hw/mcu/artery/at32f403a_407 +DEPS_SUBMODULES += $(AT32F403A_407_SDK) + +# AT32 SDK path +AT32F403A_407_SDK_SRC = $(AT32F403A_407_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F403A_407 + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ + $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_gpio.c \ + $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_misc.c \ + $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_usart.c \ + $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_acc.c \ + $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_crm.c \ + $(AT32F403A_407_SDK_SRC)/cmsis/cm4/device_support/system_at32f403a_407.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F403A_407_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F403A_407_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F403A_407_SDK_SRC)/cmsis/cm4/device_support + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f403a_407.s + +# For freeRTOS port source +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F + +flash: flash-atlink diff --git a/hw/bsp/at32f403a_407/startup_at32f403a_407.s b/hw/bsp/at32f403a_407/startup_at32f403a_407.s new file mode 100644 index 000000000..8bb76a062 --- /dev/null +++ b/hw/bsp/at32f403a_407/startup_at32f403a_407.s @@ -0,0 +1,478 @@ +/** + ****************************************************************************** + * @file startup_at32f403a_407.s + * @brief at32f403a_407xx devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMPER_IRQHandler /* Tamper */ + .word RTC_IRQHandler /* RTC */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_2_IRQHandler /* ADC1 & ADC2 */ + .word USBFS_H_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */ + .word USBFS_L_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 Channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_I2S2EXT_IRQHandler /* SPI2 & I2S2EXT */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */ + .word USBFSWakeUp_IRQHandler /* USB Wakeup from suspend */ + .word TMR8_BRK_TMR12_IRQHandler /* TMR8 Brake and TMR12 */ + .word TMR8_OVF_TMR13_IRQHandler /* TMR8 Overflow and TMR13 */ + .word TMR8_TRG_HALL_TMR14_IRQHandler /* TMR8 Trigger and hall and TMR14 */ + .word TMR8_CH_IRQHandler /* TMR8 Channel */ + .word ADC3_IRQHandler /* ADC3 */ + .word XMC_IRQHandler /* XMC */ + .word SDIO1_IRQHandler /* SDIO1 */ + .word TMR5_GLOBAL_IRQHandler /* TMR5 */ + .word SPI3_I2S3EXT_IRQHandler /* SPI3 & I2S3EXT */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TMR6_GLOBAL_IRQHandler /* TMR6 */ + .word TMR7_GLOBAL_IRQHandler /* TMR7 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */ + .word DMA2_Channel4_5_IRQHandler /* DMA2 Channel4 & Channel5 */ + .word SDIO2_IRQHandler /* SDIO2 */ + .word I2C3_EVT_IRQHandler /* I2C3 Event */ + .word I2C3_ERR_IRQHandler /* I2C3 Error */ + .word SPI4_IRQHandler /* SPI4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SE_IRQHandler /* CAN2 SE */ + .word ACC_IRQHandler /* ACC */ + .word USBFS_MAPH_IRQHandler /* USB Map HP */ + .word USBFS_MAPL_IRQHandler /* USB Map LP */ + .word DMA2_Channel6_7_IRQHandler /* DMA2 Channel6 & Channel7 */ + .word USART6_IRQHandler /* USART6 */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word EMAC_IRQHandler /* EMAC */ + .word EMAC_WKUP_IRQHandler /* EMAC Wakeup */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USBFS_H_CAN1_TX_IRQHandler + .thumb_set USBFS_H_CAN1_TX_IRQHandler,Default_Handler + + .weak USBFS_L_CAN1_RX0_IRQHandler + .thumb_set USBFS_L_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_I2S2EXT_IRQHandler + .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBFSWakeUp_IRQHandler + .thumb_set USBFSWakeUp_IRQHandler,Default_Handler + + .weak TMR8_BRK_TMR12_IRQHandler + .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler + + .weak TMR8_OVF_TMR13_IRQHandler + .thumb_set TMR8_OVF_TMR13_IRQHandler,Default_Handler + + .weak TMR8_TRG_HALL_TMR14_IRQHandler + .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler + + .weak TMR8_CH_IRQHandler + .thumb_set TMR8_CH_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak XMC_IRQHandler + .thumb_set XMC_IRQHandler,Default_Handler + + .weak SDIO1_IRQHandler + .thumb_set SDIO1_IRQHandler,Default_Handler + + .weak TMR5_GLOBAL_IRQHandler + .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler + + .weak SPI3_I2S3EXT_IRQHandler + .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TMR6_GLOBAL_IRQHandler + .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler + + .weak TMR7_GLOBAL_IRQHandler + .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak SDIO2_IRQHandler + .thumb_set SDIO2_IRQHandler,Default_Handler + + .weak I2C3_EVT_IRQHandler + .thumb_set I2C3_EVT_IRQHandler,Default_Handler + + .weak I2C3_ERR_IRQHandler + .thumb_set I2C3_ERR_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler ,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler ,Default_Handler + + .weak CAN2_SE_IRQHandler + .thumb_set CAN2_SE_IRQHandler,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler + + .weak USBFS_MAPH_IRQHandler + .thumb_set USBFS_MAPH_IRQHandler,Default_Handler + + .weak USBFS_MAPL_IRQHandler + .thumb_set USBFS_MAPL_IRQHandler,Default_Handler + + .weak DMA2_Channel6_7_IRQHandler + .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak EMAC_IRQHandler + .thumb_set EMAC_IRQHandler,Default_Handler + + .weak EMAC_WKUP_IRQHandler + .thumb_set EMAC_WKUP_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..599d22ffc --- /dev/null +++ b/hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f413.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + _spim_init_base = LOADADDR(.spim); + _spim_init_length = SIZEOF(.spim); + + .spim : + { + . = ALIGN(4); + _spim_start = .; /* create a global symbol at spim start */ + *(.spim) /* .spim sections */ + *(.spim*) /* .spim* sections */ + . = ALIGN(4); + _spim_end = .; /* define a global symbols at end of spim */ + } >SPIM + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd b/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd new file mode 100644 index 000000000..a4a95208e --- /dev/null +++ b/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd @@ -0,0 +1,23368 @@ + + + + + + + + Keil + ArteryTek + AT32F413xx_v2 + AT32F413 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 200MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + LPSEL + Low power mode select when Cortex-M4F sleepdeep + 1 + 1 + + + CLSWEF + Clear SWEF flag + 2 + 1 + + + CLSEF + Clear SEF flag + 3 + 1 + + + PVMEN + Power voltage monitoring enable + 4 + 1 + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + + + BPWEN + Battery powered domain write enable + 8 + 1 + + + + + CTRLSTS + CTRLSTS + Power control and status register + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN + Standby wake-up pin enable + 8 + 1 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40021000 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 5 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + + + CFG + CFG + Clock configuration register + 0x4 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 8 + 3 + read-write + + + APB2DIV + APB2 division + 11 + 3 + read-write + + + ADCDIV1_0 + ADC division bit1 and bit0 + 14 + 2 + read-write + + + PLLRCS + PLL reference clock select + 16 + 1 + read-write + + + PLLHEXTDIV + HEXT division selection for PLL entry clock + 17 + 1 + read-write + + + PLLMULT3_0 + PLL Multiplication Factor bit3 to bit0 + 18 + 4 + read-write + + + USBDIV1_0 + USB division bit1 and bit0 + 22 + 2 + read-write + + + CLKOUT_SEL + Clock output selection bit2 to bit0 + 24 + 3 + read-write + + + USBDIV2 + USB division bit2 + 27 + 1 + read-write + + + ADCDIV2 + ADC division bit2 + 28 + 1 + read-write + + + PLLMULT5_4 + PLL Multiplication Factor bit5 and bit4 + 29 + 2 + read-write + + + PLLRANGE + PLL clock output frequency up 72MHz or not + 31 + 1 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + 0x8 + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + APB2RST + APB2RST + APB2 peripheral reset register + 0xC + 0x20 + read-write + 0x000000000 + + + IOMUXRST + MUX function I/O reset + 0 + 1 + + + GPIOARST + IO port A reset + 2 + 1 + + + GPIOBRST + IO port B reset + 3 + 1 + + + GPIOCRST + IO port C reset + 4 + 1 + + + GPIODRST + IO port D reset + 5 + 1 + + + GPIOFRST + IO port F reset + 7 + 1 + + + ADC1RST + ADC1 reset + 9 + 1 + + + ADC2RST + ADC2 reset + 10 + 1 + + + TMR1RST + Timer1 reset + 11 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + TMR8RST + Timer8 reset + 13 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + TMR9RST + Timer9 reset + 19 + 1 + + + TMR10RST + Timer10 reset + 20 + 1 + + + TMR11RST + Timer11 reset + 21 + 1 + + + ACCRST + ACC reset + 22 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + 0x10 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer 2 reset + 0 + 1 + + + TMR3RST + Timer 3 reset + 1 + 1 + + + TMR4RST + Timer 4 reset + 2 + 1 + + + TMR5RST + Timer 5 reset + 3 + 1 + + + WWDTRST + Window watchdog timer reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + USART2RST + USART 2 reset + 17 + 1 + + + USART3RST + USART 3 reset + 18 + 1 + + + UART4RST + UART 4 reset + 19 + 1 + + + UART5RST + UART 5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + USBRST + USB reset + 23 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + BPRRST + Battery powered domain register reset + 27 + 1 + + + PWCRST + Power controller reset + 28 + 1 + + + CAN2RST + CAN2 reset + 31 + 1 + + + + + AHBEN + AHBEN + AHB Peripheral Clock enable register + 0x14 + 0x20 + read-write + 0x00000014 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + SRAMEN + SRAM interface clock enable + 2 + 1 + + + FLASHEN + FLASH clock enable + 4 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + SDIO1EN + SDIO1 clock enable + 10 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + 0x18 + 0x20 + read-write + 0x00000000 + + + IOMUXEN + MUX function I/O clock enable + 0 + 1 + + + GPIOAEN + I/O port A clock enable + 2 + 1 + + + GPIOBEN + I/O port B clock enable + 3 + 1 + + + GPIOCEN + I/O port C clock enable + 4 + 1 + + + GPIODEN + I/O port D clock enable + 5 + 1 + + + GPIOFEN + I/O port F clock enable + 7 + 1 + + + ADC1EN + ADC1 clock enable + 9 + 1 + + + ADC2EN + ADC2 clock enable + 10 + 1 + + + TMR1EN + Timer1 clock enable + 11 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + TMR8EN + Timer8 clock enable + 13 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + TMR9EN + Timer9 clock enable + 19 + 1 + + + TMR10EN + Timer10 clock enable + 20 + 1 + + + TMR11EN + Timer11 clock enable + 21 + 1 + + + ACCEN + ACC clock enable + 22 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + 0x1C + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR4EN + Timer4 clock enable + 2 + 1 + + + TMR5EN + Timer5 clock enable + 3 + 1 + + + WWDTEN + Window watchdog timer clock enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + USBEN + USB clock enable + 23 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + BPREN + Barrery powered domain register clock enable + 27 + 1 + + + PWCEN + Power clock enable + 28 + 1 + + + CAN2EN + CAN2 clock enable + 31 + 1 + + + + + BPDC + BPDC + Battery powered domain control register + 0x20 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + RTCSEL + RTC clock selection + 8 + 2 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + 0x24 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset flag clear + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register 1 + 0x30 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + CLKOUT_SEL3 + Clock output bit3 + 16 + 1 + read-write + + + USBBUFS + USB buffer size selection + 24 + 1 + read-write + + + HICKDIV + HICK 6 divider selection + 25 + 1 + read-write + + + CLKOUTDIV + Clock output division + 28 + 4 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register 2 + 0x50 + 0x20 + 0x00000000 + + + CLK_TO_TMR + Clock output internal connect to timer10 + 16 + 1 + read-write + + + + + MISC3 + MISC3 + Miscellaneous register 3 + 0x54 + 0x20 + 0x00000000 + + + AUTO_STEP_EN + Auto step en + 4 + 2 + read-write + + + HICK_TO_USB + HICK to usb clock + 8 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 9 + 1 + read-write + + + + + INTMAP + INTMAP + Interrupt remap register + 0x5C + 0x20 + 0x00000000 + + + USB_INT_MAP + USBDEV interrupt remap + 0 + 1 + read-write + + + + + + + GPIOA + General purpose IO + GPIO + 0x40010800 + + 0x0 + 0x400 + registers + + + + CFGLR + CFGLR + GPIO function configurate low register + 0x0 + 0x20 + read-write + 0x44444444 + + + IOMC0 + Port n.0 mode configurate bits + 0 + 2 + + + IOFC0 + Port n.0 function configurate + bits + 2 + 2 + + + IOMC1 + Port n.1 mode configurate bits + 4 + 2 + + + IOFC1 + Port n.1 function configurate + bits + 6 + 2 + + + IOMC2 + Port n.2 mode configurate bits + 8 + 2 + + + IOFC2 + Port n.2 function configurate + bits + 10 + 2 + + + IOMC3 + Port n.3 mode configurate bits + 12 + 2 + + + IOFC3 + Port n.3 function configurate + bits + 14 + 2 + + + IOMC4 + Port n.4 mode configurate bits + 16 + 2 + + + IOFC4 + Port n.4 function configurate + bits + 18 + 2 + + + IOMC5 + Port n.5 mode configurate bits + 20 + 2 + + + IOFC5 + Port n.5 function configurate + bits + 22 + 2 + + + IOMC6 + Port n.6 mode configurate bits + 24 + 2 + + + IOFC6 + Port n.6 function configurate + bits + 26 + 2 + + + IOMC7 + Port n.7 mode configurate bits + 28 + 2 + + + IOFC7 + Port n.7 function configurate + bits + 30 + 2 + + + + + CFGHR + CFGHR + GPIO function configurate high register + 0x4 + 0x20 + read-write + 0x44444444 + + + IOMC8 + Port n.8 mode configurate bits + 0 + 2 + + + IOFC8 + Port n.8 function configurate + bits + 2 + 2 + + + IOMC9 + Port n.9 mode configurate bits + 4 + 2 + + + IOFC9 + Port n.9 function configurate + bits + 6 + 2 + + + IOMC10 + Port n.10 mode configurate bits + 8 + 2 + + + IOFC10 + Port n.10 function configurate + bits + 10 + 2 + + + IOMC11 + Port n.11 mode configurate bits + 12 + 2 + + + IOFC11 + Port n.11 function configurate + bits + 14 + 2 + + + IOMC12 + Port n.12 mode configurate bits + 16 + 2 + + + IOFC12 + Port n.12 function configurate + bits + 18 + 2 + + + IOMC13 + Port n.13 mode configurate bits + 20 + 2 + + + IOFC13 + Port n.13 function configurate + bits + 22 + 2 + + + IOMC14 + Port n.14 mode configurate bits + 24 + 2 + + + IOFC14 + Port n.14 function configurate + bits + 26 + 2 + + + IOMC15 + Port n.15 mode configurate bits + 28 + 2 + + + IOFC15 + Port n.15 function configurate + bits + 30 + 2 + + + + + IDT + IDT + Port input data register + 0x8 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + Port output data register + 0xC + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x10 + 0x20 + read-write + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + CLR + CLR + Port bit reset register + 0x14 + 0x20 + read-write + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 1 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + WPR + WPR + Port write protect register + 0x18 + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + + + GPIOB + 0x40010C00 + + + GPIOC + 0x40011000 + + + GPIOD + 0x40011400 + + + GPIOE + 0x40011800 + + + IOMUX + IO MUX function + IOMUX + 0x40010000 + + 0x0 + 0x400 + registers + + + + EVTOUT + EVTOUT + Event output register + 0x0 + 0x20 + read-write + 0x00000000 + + + SELPIN + Select pin + 0 + 4 + + + SELPORT + Select port + 4 + 3 + + + EVOEN + Event output enable + 7 + 1 + + + + + REMAP + REMAP + IO MUX remap register + 0x4 + 0x20 + 0x00000000 + + + SPI1_MUX0 + SPI1 muxing bit0 + 0 + 1 + read-write + + + I2C1_MUX + I2C1 muxing + 1 + 1 + read-write + + + USART1_MUX + USART1 muxing + 2 + 1 + read-write + + + USART3_MUX + USART3 muxing + 4 + 2 + read-write + + + TMR1_MUX + TMR1 muxing + 6 + 2 + read-write + + + TMR2_MUX + TMR2 muxing + 8 + 2 + read-write + + + TMR3_MUX + TMR3 muxing + 10 + 2 + read-write + + + CAN_MUX + CAN1 muxing + 13 + 2 + read-write + + + PD01_MUX + PD0/PD1 muxing on + OSCIN/OSCOUT + 15 + 1 + read-write + + + TMR5CH4_MUX + TMR5 channel4 internal muxing + 16 + 1 + read-write + + + ADC1_ETP_MUX + ADC1 external trigger preempted + conversion muxing + 17 + 1 + read-write + + + ADC1_ETO_MUX + ADC1 external trigger ordinary + conversion muxing + 18 + 1 + read-write + + + ADC2_ETP_MUX + ADC2 external trigger preempted + conversion muxing + 19 + 1 + read-write + + + ADC2_ETO_MUX + ADC2 external trigger ordinary + conversion muxing + 20 + 1 + read-write + + + SWJTAG_MUX + SWD JTAG muxing + 24 + 3 + read-write + + + SPI1_MUX1 + SPI1 muxing bit1 + 31 + 1 + read-write + + + + + EXINTC1 + EXINTC1 + External interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + EXINT0 + Configure EXINT0 source + 0 + 4 + + + EXINT1 + Configure EXINT1 source + 4 + 4 + + + EXINT2 + Configure EXINT2 source + 8 + 4 + + + EXINT3 + Configure EXINT3 source + 12 + 4 + + + + + EXINTC2 + EXINTC2 + External interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + EXINT4 + Configure EXINT4 source + 0 + 4 + + + EXINT5 + Configure EXINT5 source + 4 + 4 + + + EXINT6 + Configure EXINT6 source + 8 + 4 + + + EXINT7 + Configure EXINT7 source + 12 + 4 + + + + + EXINTC3 + EXINTC3 + External interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x00000000 + + + EXINT8 + Configure EXINT8 source + 0 + 4 + + + EXINT9 + Configure EXINT9 source + 4 + 4 + + + EXINT10 + Configure EXINT10 source + 8 + 4 + + + EXINT11 + Configure EXINT11 source + 12 + 4 + + + + + EXINTC4 + EXINTC4 + External interrupt configuration register 4 + 0x14 + 0x20 + read-write + 0x00000000 + + + EXINT12 + Configure EXINT12 source + 0 + 4 + + + EXINT13 + Configure EXINT13 source + 4 + 4 + + + EXINT14 + Configure EXINT14 source + 8 + 4 + + + EXINT15 + Configure EXINT15 source + 12 + 4 + + + + + REMAP2 + REMAP2 + IO MUX remap register 2 + 0x1C + 0x20 + read-write + 0x00000000 + + + EXT_SPIM_EN_MUX + SPIM enable + 21 + 1 + + + + + REMAP3 + REMAP3 + IO MUX remap register 3 + 0x20 + 0x20 + read-write + 0x00000000 + + + TMR9_GMUX + TMR9 muxing + 0 + 4 + + + TMR10_GMUX + TMR10 muxing + 4 + 4 + + + TMR11_GMUX + TMR11 muxing + 8 + 4 + + + + + REMAP4 + REMAP4 + IO MUX remap register 4 + 0x24 + 0x20 + read-write + 0x00000000 + + + TMR1_GMUX + TMR1 muxing + 0 + 4 + + + TMR2_GMUX + TMR2 muxing + 4 + 3 + + + TMR2ITR1_GMUX + TMR2 internal trigger 1 muxing + 7 + 1 + + + TMR3_GMUX + TMR3 muxing + 8 + 4 + + + TMR5_GMUX + TMR5 muxing + 16 + 3 + + + TMR5CH4_GMUX + TMR5 channel4 internal muxing + 19 + 1 + + + + + REMAP5 + REMAP5 + IO MUX remap register 5 + 0x28 + 0x20 + read-write + 0x00000000 + + + I2C1_GMUX + I2C1 muxing + 4 + 4 + + + I2C2_GMUX + I2C2 muxing + 8 + 4 + + + SPI1_GMUX + SPI1 muxing + 16 + 4 + + + SPI2_GMUX + SPI2 muxing + 20 + 4 + + + + + REMAP6 + REMAP6 + IO MUX remap register 6 + 0x2C + 0x20 + read-write + 0x00000000 + + + CAN1_GMUX + CAN1 muxing + 0 + 4 + + + CAN2_GMUX + CAN2 muxing + 4 + 4 + + + SDIO1_GMUX + SDIO1 muxing + 8 + 4 + + + USART1_GMUX + USART1 muxing + 16 + 4 + + + USART3_GMUX + USART3 muxing + 24 + 4 + + + UART4_GMUX + UART4 muxing + 28 + 4 + + + + + REMAP7 + REMAP7 + IO MUX remap register 7 + 0x30 + 0x20 + read-write + 0x00000000 + + + EXT_SPIM_GMUX + SPIM muxing + 0 + 3 + + + EXT_SPIM_GEN + SPIM enable + 3 + 1 + + + ADC1_ETP_GMUX + ADC1 external trigger preempted + conversion muxing + 4 + 1 + + + ADC1_ETO_GMUX + ADC1 external trigger ordinary + conversion muxing + 5 + 1 + + + ADC2_ETP_GMUX + ADC2 external trigger preempted + conversion muxing + 8 + 1 + + + ADC2_ETO_GMUX + ADC2 external trigger ordinary + conversion muxing + 9 + 1 + + + SWJTAG_GMUX + Serial wire JTAG muxing + 16 + 3 + + + PD01_GMUX + PortD0/PortD1 mappingon + OSC_IN/OSC_OUT + 20 + 1 + + + + + + + EXINT + EXINT + EXINT + 0x40010400 + + 0x0 + 0x400 + registers + + + TAMPER + Tamper interrupt + 2 + + + EXINT0 + EXINT Line0 interrupt + 6 + + + EXINT1 + EXINT Line1 interrupt + 7 + + + EXINT2 + EXINT Line2 interrupt + 8 + + + EXINT3 + EXINT Line3 interrupt + 9 + + + EXINT4 + EXINT Line4 interrupt + 10 + + + EXINT9_5 + EXINT Line[9:5] interrupts + 23 + + + EXINT15_10 + EXINT Line[15:10] interrupts + 40 + + + PVM + PVM interrupt connect to EXINT line16 + 1 + + + RTCALARM + RTC Alarm interrupt connect to EXINT line17 + 41 + + + USBFSWakeUp + USB Device FS Wakeup interrupt connect to EXINT line18 + 42 + + + + INTEN + INTEN + Interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + + + EVTEN + EVTEN + Event enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + + + SWTRG + SWTRG + Software triggle register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + + + INTSTS + INTSTS + Interrupt status register + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 13 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 14 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 15 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 16 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 17 + + + + STS + STS + DMA status register (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA flag clear register (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_SRC_SEL0 + DMA_SRC_SEL0 + DMA channel source assignment register + 0xA0 + 0x20 + read-write + 0x00000000 + + + CH1_SRC + CH1 SRC select + 0 + 8 + + + CH2_SRC + CH2 SRC select + 8 + 8 + + + CH3_SRC + CH3 SRC select + 16 + 8 + + + CH4_SRC + CH4 SRC select + 24 + 8 + + + + + DMA_SRC_SEL1 + DMA_SRC_SEL1 + DMA channel source assignment register + 0xA4 + 0x20 + read-write + 0x00000000 + + + CH5_SRC + CH5 SRC select + 0 + 8 + + + CH6_SRC + CH6 SRC select + 8 + 8 + + + CH7_SRC + CH7 SRC select + 16 + 8 + + + DMA_FLEX_EN + DMA FLEX Enable + 24 + 1 + + + + + + + DMA2 + 0x40020400 + + DMA2_Channel1 + DMA2 Channel1 global interrupt + 56 + + + DMA2_Channel2 + DMA2 Channel2 global interrupt + 57 + + + DMA2_Channel3 + DMA2 Channel3 global interrupt + 58 + + + DMA2_Channel4_5 + DMA2 Channel4 and DMA2 Channel5 global interrupt + 59 + + + DMA2_Channel6_7 + DMA2 Channel6 and DMA2 Channel7 global interrupt + 75 + + + + SDIO + Secure digital input/output interface + SDIO + 0x40018000 + + 0x0 + 0x400 + registers + + + SDIO + SDIO global interrupt + 49 + + + + PWRCTRL + PWRCTRL + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PS + Power switch + 0 + 2 + + + + + CLKCTRL + CLKCTRL + SD clock control register + (SDIO_CLKCTRL) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock division + 0 + 8 + + + CLKOEN + Clock output enable + 8 + 1 + + + PWRSVEN + Power saving mode enable + 9 + 1 + + + BYPSEN + Clock divider bypass enable + bit + 10 + 1 + + + BUSWS + Bus width selection + 11 + 2 + + + CLKEDS + SDIO_CK edge selection bit + 13 + 1 + + + HFCEN + Hardware flow control enable + 14 + 1 + + + CLKDIV98 + Clock divide factor bit9 and bit8 + 15 + 2 + + + + + ARGU + ARGU + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + ARGU + Command argument + 0 + 32 + + + + + CMDCTRL + CMDCTRL + SDIO command control register + (SDIO_CMDCTRL) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDIDX + CMDIDX + 0 + 6 + + + RSPWT + Wait for response + 6 + 2 + + + INTWT + CCSM wait for interrupt + 8 + 1 + + + PNDWT + CCSM wait for end of transfer + 9 + 1 + + + CCSMEN + Command channel state machine + 10 + 1 + + + IOSUSP + SD I/O suspend command + 11 + 1 + + + + + RSPCMD + RSPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RSPCMD + RSPCMD + 0 + 6 + + + + + RSP1 + RSP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTS1 + CARDSTATUS1 + 0 + 32 + + + + + RSP2 + RSP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS2 + 0 + 32 + + + + + RSP3 + RSP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTS3 + CARDSTATUS3 + 0 + 32 + + + + + RSP4 + RSP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTS4 + CARDSTATUS4 + 0 + 32 + + + + + DTTMR + DTTMR + Bits 31:0 = TIMEOUT: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Data timeout period + 0 + 32 + + + + + DTLEN + DTLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DTLEN + Data length value + 0 + 25 + + + + + DTCTRL + DTCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TFREN + DTEN + 0 + 1 + + + TFRDIR + DTDIR + 1 + 1 + + + TFRMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + BLKSIZE + DBLOCKSIZE + 4 + 4 + + + RDWTSTART + PWSTART + 8 + 1 + + + RDWTSTOP + PWSTOP + 9 + 1 + + + RDWTMODE + RWMOD + 10 + 1 + + + IOEN + SD I/O function enable + 11 + 1 + + + + + DTCNT + DTCNT + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + CNT + Data count value + 0 + 25 + + + + + STS + STS + SDIO status register + (SDIO_STS) + 0x34 + 0x20 + read-only + 0x00000000 + + + CMDFAIL + Command crc fail + 0 + 1 + + + DTFAIL + Data crc fail + 1 + 1 + + + CMDTIMEOUT + Command timeout + 2 + 1 + + + DTTIMEOUT + Data timeout + 3 + 1 + + + TXERRU + Tx under run error + 4 + 1 + + + RXERRO + Rx over run error + 5 + 1 + + + CMDRSPCMPL + Command response complete + 6 + 1 + + + CMDCMPL + Command sent + 7 + 1 + + + DTCMPL + Data sent + 8 + 1 + + + SBITERR + Start bit error + 9 + 1 + + + DTBLKCMPL + Data block sent + 10 + 1 + + + DOCMD + Command transfer in progress + 11 + 1 + + + DOTX + Data transmit in progress + 12 + 1 + + + DORX + Data receive in progress + 13 + 1 + + + TXBUFH + Tx buffer half empty + 14 + 1 + + + RXBUFH + Rx buffer half empty + 15 + 1 + + + TXBUFF + Tx buffer full + 16 + 1 + + + RXBUFF + Rx buffer full + 17 + 1 + + + TXBUFE + Tx buffer empty + 18 + 1 + + + RXBUFE + Rx buffer empty + 19 + 1 + + + TXBUF + Tx data vaild + 20 + 1 + + + RXBUF + Rx data vaild + 21 + 1 + + + IOIF + SD I/O interrupt + 22 + 1 + + + + + INTCLR + INTCLR + SDIO interrupt clear register + (SDIO_INTCLR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CMDFAIL + Command crc fail flag clear + 0 + 1 + + + DTFAIL + Data crc fail flag clear + 1 + 1 + + + CMDTIMEOUT + Command timeout flag clear + 2 + 1 + + + DTTIMEOUT + Data timeout flag clear + 3 + 1 + + + TXERRU + Tx under run error flag clear + 4 + 1 + + + RXERRU + Rx over run error flag clear + 5 + 1 + + + CMDRSPCMPL + Command response complete flag clear + 6 + 1 + + + CMDCMPL + Command sent flag clear + 7 + 1 + + + DTCMPL + Data sent flag clear + 8 + 1 + + + SBITERR + Start bit error flag clear + 9 + 1 + + + DTBLKCMPL + Data block sent clear + 10 + 1 + + + IOIF + SD I/O interrupt flag clear + 22 + 1 + + + + + INTEN + INTEN + SDIO mask register + (SDIO_INTEN) + 0x3C + 0x20 + read-write + 0x00000000 + + + CMDFAILIEN + Command crc fail interrupt enable + 0 + 1 + + + DTFAILIEN + Data crc fail interrupt enable + 1 + 1 + + + CMDTIMEOUTIEN + Command timeout interrupt enable + 2 + 1 + + + DTTIMEOUTIEN + Data timeout interrupt enable + 3 + 1 + + + TXERRUIEN + Tx under run interrupt enable + 4 + 1 + + + RXERRUIEN + Rx over run interrupt enable + 5 + 1 + + + CMDRSPCMPLIEN + Command response complete interrupt enable + 6 + 1 + + + CMDCMPLIEN + Command sent complete interrupt enable + 7 + 1 + + + DTCMPLIEN + Data sent complete interrupt enable + 8 + 1 + + + SBITERRIEN + Start bit error interrupt enable + 9 + 1 + + + DTBLKCMPLIEN + Data block sent complete interrupt enable + 10 + 1 + + + DOCMDIEN + Command acting interrupt enable + 11 + 1 + + + DOTXIEN + Data transmit acting interrupt enable + 12 + 1 + + + DORXIEN + Data receive acting interrupt enable + 13 + 1 + + + TXBUFHIEN + Tx buffer half empty interrupt enable + 14 + 1 + + + RXBUFHIEN + Rx buffer half empty interrupt enable + 15 + 1 + + + TXBUFFIEN + Tx buffer full interrupt enable + 16 + 1 + + + RXBUFFIEN + Rx buffer full interrupt enable + 17 + 1 + + + TXBUFEIEN + Tx buffer empty interrupt enable + 18 + 1 + + + RXBUFEIEN + Rx buffer empty interrupt enable + 19 + 1 + + + TXBUFIEN + Tx buffer data vaild interrupt enable + 20 + 1 + + + RXBUFIEN + Rx buffer data vaild interrupt enable + 21 + 1 + + + IOIFIEN + SD I/O interrupt enable + 22 + 1 + + + + + BUFCNT + BUFCNT + Bits 23:0 = BUFCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + FIF0COUNT + 0 + 24 + + + + + BUF + BUF + bits 31:0 = Buffer Data: Receive and transmit + buffer data + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Buffer data + 0 + 32 + + + + + + + RTC + Real time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC + RTC global interrupt + 3 + + + + CTRLH + CTRLH + RTC Control Register High + 0x0 + 0x20 + read-write + 0x00000000 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + TAIEN + Time alarm interrupt enable + 1 + 1 + + + TSIEN + Time second interrupt enable + 2 + 1 + + + + + CTRLL + CTRLL + RTC Control Register Low + 0x4 + 0x20 + 0x00000020 + + + TSF + Time second flag + 0 + 1 + read-write + + + TAF + Time alarm flag + 1 + 1 + read-write + + + OVFF + Overflow Flag + 2 + 1 + read-write + + + UPDF + RTC update finish + 3 + 1 + read-write + + + CFGEN + RTC configuration enable + 4 + 1 + read-write + + + CFGF + RTC configuration finish + 5 + 1 + read-only + + + + + DIVH + DIVH + RTC Divider Register + High + 0x8 + 0x20 + write-only + 0x00000000 + + + DIV + RTC divider high + 0 + 4 + + + + + DIVL + DIVL + RTC Divider Register + Low + 0xC + 0x20 + write-only + 0x8000 + + + DIV + RTC divider low + 0 + 16 + + + + + DIVCNTH + DIVCNTH + RTC Divider Register High + 0x10 + 0x20 + read-write + 0x00000000 + + + DIVCNT + RTC divider register high + 0 + 4 + + + + + DIVCNTL + DIVCNTL + RTC Divider Register Low + 0x14 + 0x20 + read-write + 0x8000 + + + DIVCNT + RTC divider register low + 0 + 16 + + + + + CNTH + CNTH + RTC Counter Register High + 0x18 + 0x20 + read-write + 0x00000000 + + + CNT + RTC counter register high + 0 + 16 + + + + + CNTL + CNTL + RTC Counter Register Low + 0x1C + 0x20 + read-write + 0x00000000 + + + CNT + RTC counter register low + 0 + 16 + + + + + TAH + TAH + RTC Alarm Register High + 0x20 + 0x20 + write-only + 0xFFFF + + + TA + Time alarm register high + 0 + 16 + + + + + TAL + TAL + Time alarm register low + 0x24 + 0x20 + write-only + 0xFFFF + + + TA + RTC alarm register low + 0 + 16 + + + + + + + BPR + Battery powered register + BPR + 0x40006C04 + + 0x0 + 0x3FC + registers + + + + DT1 + DT1 + Battery powered domain data + register (BPR_DTx) + 0x0 + 0x20 + read-write + 0x00000000 + + + DT1 + BPR data1 + 0 + 16 + + + + + DT2 + DT2 + Battery powered domain data + register (BPR_DTx) + 0x4 + 0x20 + read-write + 0x00000000 + + + DT2 + BPR data2 + 0 + 16 + + + + + DT3 + DT3 + Battery powered domain data + register (BPR_DTx) + 0x8 + 0x20 + read-write + 0x00000000 + + + DT3 + BPR data3 + 0 + 16 + + + + + DT4 + DT4 + Battery powered domain data + register (BPR_DTx) + 0xC + 0x20 + read-write + 0x00000000 + + + DT4 + BPR data4 + 0 + 16 + + + + + DT5 + DT5 + Battery powered domain data + register (BPR_DTx) + 0x10 + 0x20 + read-write + 0x00000000 + + + DT5 + BPR data5 + 0 + 16 + + + + + DT6 + DT6 + Battery powered domain data + register (BPR_DTx) + 0x14 + 0x20 + read-write + 0x00000000 + + + DT6 + BPR data6 + 0 + 16 + + + + + DT7 + DT7 + Battery powered domain data + register (BPR_DTx) + 0x18 + 0x20 + read-write + 0x00000000 + + + DT7 + BPR data7 + 0 + 16 + + + + + DT8 + DT8 + Battery powered domain data + register (BPR_DTx) + 0x1C + 0x20 + read-write + 0x00000000 + + + DT8 + BPR data8 + 0 + 16 + + + + + DT9 + DT9 + Battery powered domain data + register (BPR_DTx) + 0x20 + 0x20 + read-write + 0x00000000 + + + DT9 + BPR data9 + 0 + 16 + + + + + DT10 + DT10 + Battery powered domain data + register (BPR_DTx) + 0x24 + 0x20 + read-write + 0x00000000 + + + DT10 + BPR data10 + 0 + 16 + + + + + DT11 + DT11 + Battery powered domain data + register (BPR_DTx) + 0x3C + 0x20 + read-write + 0x00000000 + + + DT11 + BPR data11 + 0 + 16 + + + + + DT12 + DT12 + Battery powered domain data + register (BPR_DTx) + 0x40 + 0x20 + read-write + 0x00000000 + + + DT12 + BPR data12 + 0 + 16 + + + + + DT13 + DT13 + Battery powered domain data + register (BPR_DTx) + 0x44 + 0x20 + read-write + 0x00000000 + + + DT13 + BPR data13 + 0 + 16 + + + + + DT14 + DT14 + Battery powered domain data + register (BPR_DTx) + 0x48 + 0x20 + read-write + 0x00000000 + + + DT14 + BPR data14 + 0 + 16 + + + + + DT15 + DT15 + Battery powered domain data + register (BPR_DTx) + 0x4C + 0x20 + read-write + 0x00000000 + + + DT15 + BPR data15 + 0 + 16 + + + + + DT16 + DT16 + Battery powered domain data + register (BPR_DTx) + 0x50 + 0x20 + read-write + 0x00000000 + + + DT16 + BPR data16 + 0 + 16 + + + + + DT17 + DT17 + Battery powered domain data + register (BPR_DTx) + 0x54 + 0x20 + read-write + 0x00000000 + + + DT17 + BPR data17 + 0 + 16 + + + + + DT18 + DT18 + Battery powered domain data + register (BPR_DTx) + 0x58 + 0x20 + read-write + 0x00000000 + + + DT18 + BPR data18 + 0 + 16 + + + + + DT19 + DT19 + Battery powered domain data + register (BPR_DTx) + 0x5C + 0x20 + read-write + 0x00000000 + + + DT19 + BPR data19 + 0 + 16 + + + + + DT20 + DT20 + Battery powered domain data + register (BPR_DTx) + 0x60 + 0x20 + read-write + 0x00000000 + + + DT20 + BPR data20 + 0 + 16 + + + + + DT21 + DT21 + Battery powered domain data + register (BPR_DTx) + 0x64 + 0x20 + read-write + 0x00000000 + + + DT21 + BPR data21 + 0 + 16 + + + + + DT22 + DT22 + Battery powered domain data + register (BPR_DTx) + 0x68 + 0x20 + read-write + 0x00000000 + + + DT22 + BPR data22 + 0 + 16 + + + + + DT23 + DT23 + Battery powered domain data + register (BPR_DTx) + 0x6C + 0x20 + read-write + 0x00000000 + + + DT23 + BPR data23 + 0 + 16 + + + + + DT24 + DT24 + Battery powered domain data + register (BPR_DTx) + 0x70 + 0x20 + read-write + 0x00000000 + + + DT24 + BPR data24 + 0 + 16 + + + + + DT25 + DT25 + Battery powered domain data + register (BPR_DTx) + 0x74 + 0x20 + read-write + 0x00000000 + + + DT25 + BPR data25 + 0 + 16 + + + + + DT26 + DT26 + Battery powered domain data + register (BPR_DTx) + 0x78 + 0x20 + read-write + 0x00000000 + + + DT26 + BPR data26 + 0 + 16 + + + + + DT27 + DT27 + Battery powered domain data + register (BPR_DTx) + 0x7C + 0x20 + read-write + 0x00000000 + + + DT27 + BPR data27 + 0 + 16 + + + + + DT28 + DT28 + Battery powered domain data + register (BPR_DTx) + 0x80 + 0x20 + read-write + 0x00000000 + + + DT28 + BPR data28 + 0 + 16 + + + + + DT29 + DT29 + Battery powered domain data + register (BPR_DTx) + 0x84 + 0x20 + read-write + 0x00000000 + + + DT29 + BPR data29 + 0 + 16 + + + + + DT30 + DT30 + Battery powered domain data + register (BPR_DTx) + 0x88 + 0x20 + read-write + 0x00000000 + + + DT30 + BPR data30 + 0 + 16 + + + + + DT31 + DT31 + Battery powered domain data + register (BPR_DTx) + 0x8C + 0x20 + read-write + 0x00000000 + + + DT31 + BPR data31 + 0 + 16 + + + + + DT32 + DT32 + Battery powered domain data + register (BPR_DTx) + 0x90 + 0x20 + read-write + 0x00000000 + + + DT32 + BPR data32 + 0 + 16 + + + + + DT33 + DT33 + Battery powered domain data + register (BPR_DTx) + 0x94 + 0x20 + read-write + 0x00000000 + + + DT33 + BPR data33 + 0 + 16 + + + + + DT34 + DT34 + Battery powered domain data + register (BPR_DTx) + 0x98 + 0x20 + read-write + 0x00000000 + + + DT34 + BPR data34 + 0 + 16 + + + + + DT35 + DT35 + Battery powered domain data + register (BPR_DTx) + 0x9C + 0x20 + read-write + 0x00000000 + + + DT35 + BPR data35 + 0 + 16 + + + + + DT36 + DT36 + Battery powered domain data + register (BPR_DTx) + 0xA0 + 0x20 + read-write + 0x00000000 + + + DT36 + BPR data36 + 0 + 16 + + + + + DT37 + DT37 + Battery powered domain data + register (BPR_DTx) + 0xA4 + 0x20 + read-write + 0x00000000 + + + DT37 + BPR data37 + 0 + 16 + + + + + DT38 + DT38 + Battery powered domain data + register (BPR_DTx) + 0xA8 + 0x20 + read-write + 0x00000000 + + + DT38 + BPR data38 + 0 + 16 + + + + + DT39 + DT39 + Battery powered domain data + register (BPR_DTx) + 0xAC + 0x20 + read-write + 0x00000000 + + + DT39 + BPR data39 + 0 + 16 + + + + + DT40 + DT40 + Battery powered domain data + register (BPR_DTx) + 0xB0 + 0x20 + read-write + 0x00000000 + + + DT40 + BPR data40 + 0 + 16 + + + + + DT41 + DT41 + Battery powered domain data + register (BPR_DTx) + 0xB4 + 0x20 + read-write + 0x00000000 + + + DT41 + BPR data41 + 0 + 16 + + + + + DT42 + DT42 + Battery powered domain data + register (BPR_DTx) + 0xB8 + 0x20 + read-write + 0x00000000 + + + DT42 + BPR data42 + 0 + 16 + + + + + RTCCAL + RTCCAL + RTC clock calibration register + (BPR_RTCCAL) + 0x28 + 0x20 + read-write + 0x00000000 + + + CALVAL + Calibration value + 0 + 7 + + + CALOUT + Calibration Clock Output + 7 + 1 + + + OUTEN + Output enable + 8 + 1 + + + OUTSEL + Output selection + 9 + 1 + + + + + CTRL + CTRL + BPR control register + (BPR_CTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TPEN + Tamper pin enable + 0 + 1 + + + TPP + TAMPER pin polarity + 1 + 1 + + + + + CTRLSTS + CTRLSTS + BPR control/status register + (BPR_CTRLSTS) + 0x30 + 0x20 + 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+ C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C2CP + Channel 2 complementary polarity + 7 + 1 + + + C2CEN + Channel 2 complementary enable + 6 + 1 + + + C2P + Channel 2 Polarity + 5 + 1 + + + C2EN + Channel 2 enable + 4 + 1 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1CEN + Channel 1 complementary enable + 2 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + C2DT + C2DT + Channel 2 data register + 0x38 + 0x20 + read-write + 0x00000000 + + + C2DT + Channel 2 data register + 0 + 16 + + + + + + + TMR10 + General purpose timer + TIMER + 0x40015000 + + 0x0 + 0x400 + registers + + + TMR1_OVF_TMR10 + TMR1 overflow interrupt and TMR10 global + interrupt + 25 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + C1IEN + Channel 1 interrupt + enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + 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+ Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + + + TMR11 + 0x40015400 + + TMR1_TRG_HALL_TMR11 + TMR1 trigger and HALL interrupts and + TMR11 global interrupt + 26 + + + + ACC + HICK Auto Clock Calibration + ACC + 0x40015800 + + 0x0 + 0x400 + registers + + + + STS + STS + status register + 0x0 + 0x20 + 0x0000 + + + RSLOST + Reference Signal Lost + read-write + 1 + 1 + + + CALRDY + Internal high-speed clock calibration ready + read-write + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x04 + 0x20 + 0x0100 + + + STEP + STEP + read-write + 8 + 4 + + + CALRDYIEN + CALRDY interrupt enable + read-write + 5 + 1 + + + EIEN + RSLOST error interrupt enable + read-write + 4 + 1 + + + ENTRIM + Enable trim + read-write + 1 + 1 + + + CALON + Calibration on + read-write + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x08 + 0x20 + 0x2080 + + + HICKTWK + Internal high-speed auto clock trimming + read-only + 8 + 6 + + + HICKCAL + Internal high-speed auto clock calibration + read-only + 0 + 8 + + + + + C1 + C1 + compare value 1 + 0x0C + 0x20 + 0x1F2C + + + C1 + Compare 1 + read-write + 0 + 16 + + + + + C2 + C2 + compare value 2 + 0x10 + 0x20 + 0x1F40 + + + C2 + Compare 2 + read-write + 0 + 16 + + + + + C3 + C3 + compare value 3 + 0x14 + 0x20 + 0x1F54 + + + C3 + Compare 3 + read-write + 0 + 16 + + + + + + + I2C1 + Inter integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EVT + I2C1 event interrupt + 31 + + + I2C1_ERR + I2C1 error interrupt + 32 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + RESET + I2C peripheral reset + 15 + 1 + + + SMBALERT + SMBus alert pin set + 13 + 1 + + + PECTEN + Request PEC transmission enable + 12 + 1 + + + MACKCTRL + Master receiving mode acknowledge control + 11 + 1 + + + ACKEN + Acknowledge enable + 10 + 1 + + + GENSTOP + Stop generation + 9 + 1 + + + GENSTART + Start generation + 8 + 1 + + + STRETCH + Clock stretching mode + 7 + 1 + + + GCAEN + General call address enable + 6 + 1 + + + PECEN + PEC calculation enable + 5 + 1 + + + ARPEN + SMBus address resolution protocol enable + 4 + 1 + + + SMBMODE + SMBus device mode + 3 + 1 + + + PERMODE + I2C peripheral mode + 1 + 1 + + + I2CEN + Peripheral enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + DMAEND + DMA transfer end indication + 12 + 1 + + + DMAEN + DMA transfer enable + 11 + 1 + + + DATAIEN + Data transmission interrupt enable + 10 + 1 + + + EVTIEN + Event interrupt enable + 9 + 1 + + + ERRIEN + Error interrupt enable + 8 + 1 + + + CLKFREQ + Input clock frequency + 0 + 8 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + ADDR1MODE + Address mode + 15 + 1 + + + ADDR1 + Own address 1 + 0 + 10 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x0000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2EN + Own address 2 enable + 0 + 1 + + + + + DT + DT + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + DT + data register + 0 + 8 + + + + + STS1 + STS1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + ALERTF + SMBus alert + 15 + 1 + read-write + + + TMOUT + Timeout error + 14 + 1 + read-write + + + PECERR + PEC receive error + 12 + 1 + read-write + + + OUF + Overflow or underflow + 11 + 1 + read-write + + + ACKFAIL + Acknowledge failure + 10 + 1 + read-write + + + ARLOST + Arbitration lost (master + mode) + 9 + 1 + read-write + + + BUSERR + Bus error + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + (transmitters) + 7 + 1 + read-only + + + RDBF + Receive data buffer full + (receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slave + mode) + 4 + 1 + read-only + + + ADDRHF + address header match (Master + mode) + 3 + 1 + read-only + + + TDC + Transmit data complete + 2 + 1 + read-only + + + ADDR7F + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + + STARTF + Start bit (Master mode) + 0 + 1 + read-only + + + + + STS2 + STS2 + Status register 2 + 0x18 + 0x20 + read-only + 0x0000 + + + PECVAL + PEC value + 8 + 8 + + + ADDR2F + Received address 2 + 7 + 1 + + + HOSTADDRF + SMBus host address receiving + 6 + 1 + + + DEVADDRF + SMBus device address receiving + 5 + 1 + + + GCADDRF + General call address reception + 4 + 1 + + + DIRF + Transmission direction + 2 + 1 + + + BUSYF + Bus busy + 1 + 1 + + + TRMODE + Transmission mode + 0 + 1 + + + + + CLKCTRL + CLKCTRL + Clock control register + 0x1C + 0x20 + read-write + 0x0000 + + + SPEEDMODE + Speed mode selection + 15 + 1 + + + DUTYMODE + Fast mode duty cycle + 14 + 1 + + + SPEED + I2C bus speed config + 0 + 12 + + + + + TMRISE + TMRISE + TRISE register + 0x20 + 0x20 + read-write + 0x0002 + + + RISETIME + I2C bus rise time + 0 + 6 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 33 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + UEN + USART enable + 13 + 1 + + + DBN + Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + ID + USART identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + ADC1 + Analog to digital converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + MSSEL + Master slave mode select + 16 + 4 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 25 + 1 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 24 + 1 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + OCDMAEN + DMA transfer enable of ordinary channels + 8 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ADC2ODT + ADC2 conversion data of ordinary channel + 16 + 16 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + + + ADC2 + Analog to digital converter + ADC + 0x40012800 + + 0x0 + 0x400 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 25 + 1 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 24 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + USBFS_H_CAN1_TX + CAN1 TX interrupt + 19 + + + USBFS_L_CAN1_RX0 + CAN1 RX0 interrupt + 20 + + + CAN_RX1 + CAN1 RX1 interrupt + 21 + + + CAN_SE + CAN1 SE interrupt + 22 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RF0R + Receive FIFO 0 release + 5 + 1 + read-write + + + RF0OF + Receive FIFO 0 overflow flag + 4 + 1 + read-write + + + RF0FF + Receive FIFO 0 full flag + 3 + 1 + read-write + + + RF0MN + Receive FIFO 0 message num + 0 + 2 + read-only + + + + + RF1 + RF1 + Receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RF1R + Receive FIFO 1 release + 5 + 1 + read-write + + + RF1OF + Receive FIFO 1 overflow flag + 4 + 1 + read-write + + + RF1FF + Receive FIFO 1 full flag + 3 + 1 + read-write + + + RF1MN + Receive FIFO 1 message num + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + EDZIEN + Enter doze mode interrupt enable + 17 + 1 + + + QDZIEN + Quit doze mode interrupt enable + 16 + 1 + + + EOIEN + Error occur interrupt enable + 15 + 1 + + + ETRIEN + Error type record interrupt enable + 11 + 1 + + + BOIEN + Bus-off interrupt enable + 10 + 1 + + + EPIEN + Error passive interrupt enable + 9 + 1 + + + EAIEN + Error active interrupt enable + 8 + 1 + + + RF1OIEN + Receive FIFO 1 overflow interrupt enable + 6 + 1 + + + RF1FIEN + Receive FIFO 1 full interrupt enable + 5 + 1 + + + RF1MIEN + FIFO 1 receive message interrupt enable + 4 + 1 + + + RF0OIEN + Receive FIFO 0 overflow interrupt enable + 3 + 1 + + + RF0FIEN + Receive FIFO 0 full interrupt enable + 2 + 1 + + + RF0MIEN + FIFO 0 receive message interrupt enable + 1 + 1 + + + TCIEN + Transmission complete interrupt enable + 0 + 1 + + + + + ESTS + ESTS + Error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Transmit error counter + 16 + 8 + read-only + + + ETR + Error type record + 4 + 3 + read-write + + + BOF + Bus-off flag + 2 + 1 + read-only + + + EPF + Error passive flag + 1 + 1 + read-only + + + EAF + Error active flag + 0 + 1 + read-only + + + + + BTMG + BTMG + Bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOEN + Listen-Only mode + 31 + 1 + + + LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB2 + F1FB2 + Filter bank 1 filtrate bit register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB1 + F2FB1 + Filter bank 2 filtrate bit register 1 + 0x250 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB2 + F2FB2 + Filter bank 2 filtrate bit register 2 + 0x254 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F3FB1 + F3FB1 + Filter bank 3 filtrate bit register 1 + 0x258 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F3FB2 + F3FB2 + Filter bank 3 filtrate bit register 2 + 0x25C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F4FB1 + F4FB1 + Filter bank 4 filtrate bit register 1 + 0x260 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F4FB2 + F4FB2 + Filter bank 4 filtrate bit register 2 + 0x264 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F5FB1 + F5FB1 + Filter bank 5 filtrate bit register 1 + 0x268 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 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data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB2 + F13FB2 + Filter bank 13 filtrate bit filtrate bit register 2 + 0x2AC + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + + + CAN2 + 0x40006800 + + CAN2_TX + CAN2 TX interrupt + 68 + + + CAN2_RX0 + CAN2 RX0 interrupt + 69 + + + CAN2_RX1 + CAN2 RX1 interrupt + 70 + + + CAN2_SE + CAN2 SE interrupt + 71 + + + + DEBUG + Debug support + DEBUG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + DEBUG_IDCODE + 0x0 + 0x20 + read-only + 0x0 + + + PID + PID + 0 + 32 + + + + + CTRL + CTRL + DEBUG_CTRL + 0x4 + 0x20 + read-write + 0x0 + + + SLEEP_DEBUG + SLEEP_DEBUG + 0 + 1 + + + DEEPSLEEP_DEBUG + DEEPSLEEP_DEBUG + 1 + 1 + + + STANDBY_DEBUG + STANDBY_DEBUG + 2 + 1 + + + TRACE_IOEN + TRACE_IOEN + 5 + 1 + + + TRACE_MODE + TRACE_MODE + 6 + 2 + + + WDT_PAUSE + WDT_PAUSE + 8 + 1 + + + WWDT_PAUSE + WWDT_PAUSE + 9 + 1 + + + TMR1_PAUSE + TMR1_PAUSE + 10 + 1 + + + TMR2_PAUSE + TMR2_PAUSE + 11 + 1 + + + TMR3_PAUSE + TMR3_PAUSE + 12 + 1 + + + TMR4_PAUSE + TMR4_PAUSE + 13 + 1 + + + CAN1_PAUSE + CAN1_PAUSE + 14 + 1 + + + I2C1_SMBUS_TIMEOUT + I2C1_SMBUS_TIMEOUT + 15 + 1 + + + I2C2_SMBUS_TIMEOUT + I2C2_SMBUS_TIMEOUT + 16 + 1 + + + TMR8_PAUSE + TMR8_PAUSE + 17 + 1 + + + TMR5_PAUSE + TMR5_PAUSE + 18 + 1 + + + CAN2_PAUSE + CAN2_PAUSE + 21 + 1 + + + TMR9_PAUSE + TMR9_PAUSE + 28 + 1 + + + TMR10_PAUSE + TMR10_PAUSE + 29 + 1 + + + TMR11_PAUSE + TMR11_PAUSE + 30 + 1 + + + + + + + UART4 + Universal asynchronous receiver transmitter + 0x40004C00 + + UART4 + UART4 global interrupt + 52 + + + + UART5 + Universal asynchronous receiver transmitter + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DT + DT + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DT + Data Register + 0 + 32 + + + + + CDT + CDT + Common data register + 0x4 + 0x20 + read-write + 0x00000000 + + + CDT + Common Data + 0 + 1 + + + + + CTRL + CTRL + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RST + Reset bit + 0 + 1 + + + REVID + Reverse input data + 5 + 2 + + + REVOD + Reverse output data + 7 + 1 + + + + + IDT + IDT + Initial data register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + IDT + Initial Data + 0 + 32 + + + + + + + FLASH + Flash memory controler + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + PSR + PSR + Performance selection register + 0x0 + 0x20 + 0x00000030 + + + + + UNLOCK + UNLOCK + Unlock register + 0x4 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + USD_UNLOCK + USD_UNLOCK + USD unlock register + 0x8 + 0x20 + write-only + 0x00000000 + + + USD_UKVAL + User system data Unlock key value + 0 + 32 + + + + + STS + STS + Status register + 0xC + 0x20 + 0x00000000 + + + ODF + Operate done flag + 5 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + PRGMERR + program error + 2 + 1 + read-write + + + OBF + Operate busy flag + 0 + 1 + read-only + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + USDPRGM + User system data program + 4 + 1 + + + USDERS + User system data erase + 5 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + USDULKS + User system data unlock success + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR + ADDR + Address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + USD + USD + User system data register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + USDERR + User system data error + 0 + 1 + + + FAP + FLASH access protection + 1 + 1 + + + nWDT_ATO_EN + WDT auto enable + 2 + 1 + + + nDEPSLP_RST + Deepsleep reset + 3 + 1 + + + nSTDBY_RST + Standby reset + 4 + 1 + + + BTOPT + boot option + 5 + 1 + + + USER_D0 + User data 0 + 10 + 8 + + + USER_D1 + User data 1 + 18 + 8 + + + + + EPPS + EPPS + Erase/program protection status register + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + UNLOCK3 + UNLOCK3 + Unlock 3 register + 0x84 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + SELECT + SELECT + Select register + 0x88 + 0x20 + write-only + 0x00000000 + + + SELECT + spim type selection + 0 + 32 + + + + + STS3 + STS3 + Status 3 register + 0x8C + 0x20 + 0x00000000 + + + OBF + Operate busy flag + 0 + 1 + read-only + + + PRGMERR + program error + 2 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + ODF + Operate done flag + 5 + 1 + read-write + + + + + CTRL3 + CTRL3 + Control 3 register + 0x90 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + CHPERS + Chip erase + 2 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR3 + ADDR3 + Address 3 register + 0x94 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + DA + DA + Spim decryption address + 0x98 + 0x20 + write-only + 0x00000000 + + + FDA + Flash decryption address + 0 + 32 + + + + + SLIB_STS0 + SLIB_STS0 + sLib status 0 register + 0xCC + 0x20 + 0x00000000 + + + SLIB_ENF + sLib enabled flag + 3 + 1 + read-only + + + + + SLIB_STS1 + SLIB_STS1 + sLib status 1 register + 0xD0 + 0x20 + 0x00000000 + + + SLIB_SS + sLib start sector + 0 + 11 + read-only + + + SLIB_DAT_SS + sLib data start sector + 11 + 11 + read-only + + + SLIB_ES + sLib end sector + 22 + 10 + read-only + + + + + SLIB_PWD_CLR + SLIB_PWD_CLR + SLIB password clear register + 0xD4 + 0x20 + 0x00000000 + write-only + + + SLIB_PCLR_VAL + sLib password clear value + 0 + 32 + + + + + SLIB_MISC_STS + SLIB_MISC_STS + sLib misc status register + 0xD8 + 0x20 + 0x01000000 + + + SLIB_PWD_ERR + sLib password error + 0 + 1 + read-only + + + SLIB_PWD_OK + sLib password ok + 1 + 1 + read-only + + + SLIB_ULKF + sLib unlock flag + 2 + 1 + read-only + + + SLIB_RCNT + sLib remaining count + 16 + 9 + read-only + + + + + SLIB_SET_PWD + SLIB_SET_PWD + sLib password setting register + 0xDC + 0x20 + 0x00000000 + write-only + + + SLIB_PSET_VAL + sLib password setting val + 0 + 32 + + + + + SLIB_SET_RANGE + SLIB_SET_RANGE + Configure sLib range register + 0xE0 + 0x20 + 0x00000000 + write-only + + + SLIB_SS_SET + sLib start sector setting + 0 + 11 + + + SLIB_DSS_SET + sLib data start sector setting + 11 + 11 + + + SLIB_ES_SET + sLib end sector setting + 22 + 10 + + + + + SLIB_UNLOCK + SLIB_UNLOCK + sLib unlock register + 0xF0 + 0x20 + 0x00000000 + write-only + + + SLIB_UKVAL + sLib unlock key value + 0 + 32 + + + + + CRC_CTRL + CRC_CTRL + Flash CRC controler register + 0xF4 + 0x20 + 0x00000000 + write-only + + + CRC_SS + CRC start sector + 0 + 7 + + + CRC_SN + CRC sector numbler + 7 + 7 + + + CRC_STRT + CRC start + 14 + 1 + + + + + CRC_CHKR + CRC_CHKR + FLASH CRC check result register + 0xF8 + 0x20 + 0x00000000 + read-only + + + CRC_CHKR + CRC check result + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + USBFS + Universal serial bus full-speed device + interface + USBFS + 0x40005C00 + + 0x0 + 0x400 + registers + + + + EPT0 + EPT0 + endpoint 0 register + 0x0 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT1 + EPT1 + endpoint 1 register + 0x4 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT2 + EPT2 + endpoint 2 register + 0x8 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT3 + EPT3 + endpoint 3 register + 0xC + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT4 + EPT4 + endpoint 4 register + 0x10 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT5 + EPT5 + endpoint 5 register + 0x14 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT6 + EPT6 + endpoint 6 register + 0x18 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT7 + EPT7 + endpoint 7 register + 0x1C + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + CTRL + CTRL + control register + 0x40 + 0x20 + read-write + 0x00000003 + + + CSRST + Core soft reset + 0 + 1 + + + DISUSB + Disable usb phy + 1 + 1 + + + LPM + Low power mode + 2 + 1 + + + SSP + Soft suspend config + 3 + 1 + + + GRESUME + Generate resume request + 4 + 1 + + + LSOFIEN + Lost start of frame interrupt enable + 8 + 1 + + + SOFIEN + Start of frame interrupt + enable + 9 + 1 + + + RSTIEN + Bus reset interrupt enable + 10 + 1 + + + SPIEN + Bus suspend mode interrupt + enable + 11 + 1 + + + WKIEN + Wakeup/Remote wakeup interrupt enable + 12 + 1 + + + BEIEN + Bus error interrupt enable + 13 + 1 + + + UCFORIEN + USB Core fifo overrun + interrupt enable + 14 + 1 + + + TCIEN + transmission completed interrupt + enable + 15 + 1 + + + + + INTSTS + INTSTS + interrupt status register + 0x44 + 0x20 + read-write + 0x00000000 + + + EPT_NUM + Endpoint number + 0 + 4 + + + INOUT + In/Out transaction + 4 + 1 + + + LSOF + Lost start of frame + 8 + 1 + + + SOF + start of frame + 9 + 1 + + + RST + Bus reset + 10 + 1 + + + SP + Bus suspend + 11 + 1 + + + WK + Wakeup + 12 + 1 + + + BE + Bus error + 13 + 1 + + + UCFOR + USB core fifo overrun memory + 14 + 1 + + + TC + transaction completed + 15 + 1 + + + + + SOFRNUM + SOFRNUM + frame number register + 0x48 + 0x20 + read-write + 0x0000 + + + SOFNUM + Start of frame number + 0 + 11 + + + LSOFNUM + Lost start of frame number + 11 + 2 + + + CLCK + Connect locked + 13 + 1 + + + DMSTS + DM status + 14 + 1 + + + DPSTS + DP status + 15 + 1 + + + + + DEVADDR + DEVADDR + device address + 0x4C + 0x20 + read-write + 0x0000 + + + ADDR + Host assign device address + 0 + 7 + + + CEN + USB core enable + 7 + 1 + + + + + BUFTBL + BUFTBL + Buffer table address + 0x50 + 0x20 + read-write + 0x0000 + + + BTADDR + Endpoint buffer table start address + 3 + 13 + + + + + CFG + CFG + CFG control register + 0x60 + 0x20 + read-write + 0x0000 + + + SOFOUTEN + SOF output enable + 0 + 1 + + + + + + + diff --git a/hw/bsp/at32f413/boards/AT_START_F413/board.h b/hw/bsp/at32f413/boards/AT_START_F413/board.h new file mode 100644 index 000000000..f0bf0e4ae --- /dev/null +++ b/hw/bsp/at32f413/boards/AT_START_F413/board.h @@ -0,0 +1,62 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// LED +#define LED_PORT GPIOC +#define LED_PIN GPIO_PINS_2 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +// UART +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK + +static inline void board_vbus_sense_init(void) +{ + +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f413/boards/AT_START_F413/board.mk b/hw/bsp/at32f413/boards/AT_START_F413/board.mk new file mode 100644 index 000000000..28351265d --- /dev/null +++ b/hw/bsp/at32f413/boards/AT_START_F413/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F413xC_FLASH.ld + +CFLAGS += \ + -DAT32F413RCT7 diff --git a/hw/bsp/at32f413/family.c b/hw/bsp/at32f413/family.c new file mode 100644 index 000000000..a38fe450e --- /dev/null +++ b/hw/bsp/at32f413/family.c @@ -0,0 +1,286 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f413_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void usb_clock48m_select(usb_clk48_s clk_s); +void uart_print_init(uint32_t baudrate); + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USBFS_H_CAN1_TX_IRQHandler(void) { + tud_int_handler(0); +} +void USBFS_L_CAN1_RX0_IRQHandler(void) { + tud_int_handler(0); +} +void USBFS_MAPH_IRQHandler(void) { + tud_int_handler(0); +} +void USBFS_MAPL_IRQHandler(void) { + tud_int_handler(0); +} +void USBFSWakeUp_IRQHandler(void) { + tud_int_handler(0); +} + +void board_init(void) +{ + system_clock_config(); + + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HICK); + + /* configure systick */ + systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); + + /* enable usb clock */ + crm_periph_clock_enable(CRM_USB_PERIPH_CLOCK, TRUE); + + SysTick_Config(SystemCoreClock / 1000); +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USBFS_H_CAN1_TX_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFS_L_CAN1_RX0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFSWakeUp_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); + + uart_print_init(115200); + printf("usart printf config success!\r\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + switch(system_core_clock) + { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_1); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_1_5); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + /* 120MHz */ + case 120000000: + crm_usb_clock_div_set(CRM_USB_DIV_2_5); + break; + + /* 144MHz */ + case 144000000: + crm_usb_clock_div_set(CRM_USB_DIV_3); + break; + + /* 168MHz */ + case 168000000: + crm_usb_clock_div_set(CRM_USB_DIV_3_5); + break; + + /* 192MHz */ + case 192000000: + crm_usb_clock_div_set(CRM_USB_DIV_4); + break; + + default: + break; + } + } +} + +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +void board_led_write(bool state) { + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) { + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + +int board_uart_read(uint8_t *buf, int len) { + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + + +#if CFG_TUSB_OS == OPT_OS_NONE + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + + uint32_t board_millis(void) + { + return system_ticks; + } + + void SVC_Handler(void) + { + } + + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/at32f413/family.mk b/hw/bsp/at32f413/family.mk new file mode 100644 index 000000000..c56d1064c --- /dev/null +++ b/hw/bsp/at32f413/family.mk @@ -0,0 +1,42 @@ +# Submodules +AT32F413_SDK = hw/mcu/artery/at32f413 +DEPS_SUBMODULES += $(AT32F413_SDK) + +# AT32 SDK path +AT32F413_SDK_SRC = $(AT32F413_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F413 + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ + $(AT32F413_SDK_SRC)/drivers/src/at32f413_gpio.c \ + $(AT32F413_SDK_SRC)/drivers/src/at32f413_misc.c \ + $(AT32F413_SDK_SRC)/drivers/src/at32f413_usart.c \ + $(AT32F413_SDK_SRC)/drivers/src/at32f413_acc.c \ + $(AT32F413_SDK_SRC)/drivers/src/at32f413_crm.c \ + $(AT32F413_SDK_SRC)/cmsis/cm4/device_support/system_at32f413.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F413_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F413_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F413_SDK_SRC)/cmsis/cm4/device_support + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f413.s + +# For freeRTOS port source +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F + +flash: flash-atlink diff --git a/hw/bsp/at32f413/startup_at32f413.s b/hw/bsp/at32f413/startup_at32f413.s new file mode 100644 index 000000000..4fc1f2a86 --- /dev/null +++ b/hw/bsp/at32f413/startup_at32f413.s @@ -0,0 +1,431 @@ +/** + ****************************************************************************** + * @file startup_at32f413.s + * @brief at32f413xx devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMPER_IRQHandler /* Tamper */ + .word RTC_IRQHandler /* RTC */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_2_IRQHandler /* ADC1 & ADC2 */ + .word USBFS_H_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */ + .word USBFS_L_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 Channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* Reserved */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */ + .word USBFSWakeUp_IRQHandler /* USB Wakeup from suspend */ + .word TMR8_BRK_IRQHandler /* TMR8 Brake */ + .word TMR8_OVF_IRQHandler /* TMR8 Overflow */ + .word TMR8_TRG_HALL_IRQHandler /* TMR8 Trigger and hall */ + .word TMR8_CH_IRQHandler /* TMR8 Channel */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SDIO1_IRQHandler /* SDIO1 */ + .word TMR5_GLOBAL_IRQHandler /* TMR5 */ + .word 0 /* Reserved */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */ + .word DMA2_Channel4_5_IRQHandler /* DMA2 Channel4 & Channel5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SE_IRQHandler /* CAN2 SE */ + .word ACC_IRQHandler /* ACC */ + .word USBFS_MAPH_IRQHandler /* USB Map HP */ + .word USBFS_MAPL_IRQHandler /* USB Map LP */ + .word DMA2_Channel6_7_IRQHandler /* DMA2 Channel6 & Channel7 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USBFS_H_CAN1_TX_IRQHandler + .thumb_set USBFS_H_CAN1_TX_IRQHandler,Default_Handler + + .weak USBFS_L_CAN1_RX0_IRQHandler + .thumb_set USBFS_L_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBFSWakeUp_IRQHandler + .thumb_set USBFSWakeUp_IRQHandler,Default_Handler + + .weak TMR8_BRK_IRQHandler + .thumb_set TMR8_BRK_IRQHandler,Default_Handler + + .weak TMR8_OVF_IRQHandler + .thumb_set TMR8_OVF_IRQHandler,Default_Handler + + .weak TMR8_TRG_HALL_IRQHandler + .thumb_set TMR8_TRG_HALL_IRQHandler,Default_Handler + + .weak TMR8_CH_IRQHandler + .thumb_set TMR8_CH_IRQHandler,Default_Handler + + .weak SDIO1_IRQHandler + .thumb_set SDIO1_IRQHandler,Default_Handler + + .weak TMR5_GLOBAL_IRQHandler + .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler ,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler ,Default_Handler + + .weak CAN2_SE_IRQHandler + .thumb_set CAN2_SE_IRQHandler,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler + + .weak USBFS_MAPH_IRQHandler + .thumb_set USBFS_MAPH_IRQHandler,Default_Handler + + .weak USBFS_MAPL_IRQHandler + .thumb_set USBFS_MAPL_IRQHandler,Default_Handler + + .weak DMA2_Channel6_7_IRQHandler + .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..73889ebf9 --- /dev/null +++ b/hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f415.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd b/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd new file mode 100644 index 000000000..cd22346c7 --- /dev/null +++ b/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd @@ -0,0 +1,27108 @@ + + + + + + + + Keil + ArteryTek + AT32F415xx_v2 + AT32F415 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 150MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Power control register + (PWC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + VRSEL + Voltage regulator state select when deepsleep mode + 0 + 1 + + + LPSEL + Low power mode select when Cortex-M4F sleepdeep + 1 + 1 + + + CLSWEF + Clear SWEF flag + 2 + 1 + + + CLSEF + Clear SEF flag + 3 + 1 + + + PVMEN + Power voltage monitoring enable + 4 + 1 + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + + + BPWEN + Battery powered domain write enable + 8 + 1 + + + + + CTRLSTS + CTRLSTS + Power control register + (PWC_CTRLST) + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN + Standby wake-up pin enable + 8 + 1 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40021000 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 5 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + + + CFG + CFG + Clock configuration register + (CRM_CFG) + 0x4 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 8 + 3 + read-write + + + APB2DIV + APB2 division + 11 + 3 + read-write + + + ADCDIV1_0 + ADC division bit1 and bit0 + 14 + 2 + read-write + + + PLLRCS + PLL reference clock select + 16 + 1 + read-write + + + PLLHEXTDIV + HEXT division selection for PLL entry clock + 17 + 1 + read-write + + + PLLMULT3_0 + PLL Multiplication Factor bit3 to bit0 + 18 + 4 + read-write + + + USBDIV1_0 + USB division bit1 and bit0 + 22 + 2 + read-write + + + CLKOUT_SEL + Clock output selection bit2 to bit0 + 24 + 3 + read-write + + + USBDIV2 + USB division bit2 + 27 + 1 + read-write + + + ADCDIV2 + ADC division bit2 + 28 + 1 + read-write + + + PLLMULT5_4 + PLL Multiplication Factor bit5 and bit4 + 29 + 2 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + (CRM_CLKINT) + 0x8 + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + APB2RST + APB2RST + APB2 peripheral reset register + (CRM_APB2RST) + 0xC + 0x20 + read-write + 0x000000000 + + + IOMUXRST + MUX function I/O + reset + 0 + 1 + + + EXINTRST + External interrupt reset + 1 + 1 + + + GPIOARST + IO port A reset + 2 + 1 + + + GPIOBRST + IO port B reset + 3 + 1 + + + GPIOCRST + IO port C reset + 4 + 1 + + + GPIODRST + IO port D reset + 5 + 1 + + + GPIOFRST + IO port F reset + 7 + 1 + + + ADC1RST + ADC1 reset + 9 + 1 + + + TMR1RST + Timer1 reset + 11 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + TMR9RST + Timer9 reset + 19 + 1 + + + TMR10RST + Timer10 reset + 20 + 1 + + + TMR11RST + Timer11 reset + 21 + 1 + + + ACCRST + ACC reset + 22 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + (CRM_APB1RST) + 0x10 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer 2 reset + 0 + 1 + + + TMR3RST + Timer 3 reset + 1 + 1 + + + TMR4RST + Timer 4 reset + 2 + 1 + + + TMR5RST + Timer 5 reset + 3 + 1 + + + CMPRST + Comparator reset + 9 + 1 + + + WWDTRST + Window watchdog timer reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + USART2RST + USART 2 reset + 17 + 1 + + + USART3RST + USART 3 reset + 18 + 1 + + + UART4RST + UART 4 reset + 19 + 1 + + + UART5RST + UART 5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + PWCRST + Power controller reset + 28 + 1 + + + + + AHBEN + AHBEN + AHB Peripheral Clock enable register + (CRM_AHBEN) + 0x14 + 0x20 + read-write + 0x00000014 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + SRAMEN + SRAM interface clock + enable + 2 + 1 + + + FLASHEN + FLASH clock enable + 4 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + SDIO1EN + SDIO1 clock enable + 10 + 1 + + + OTGFS1EN + OTGFS1 clock enable + 12 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + (CRM_APB2EN) + 0x18 + 0x20 + read-write + 0x00000000 + + + IOMUXEN + MUX function I/O clock + enable + 0 + 1 + + + GPIOAEN + I/O port A clock enable + 2 + 1 + + + GPIOBEN + I/O port B clock enable + 3 + 1 + + + GPIOCEN + I/O port C clock enable + 4 + 1 + + + GPIODEN + I/O port D clock enable + 5 + 1 + + + GPIOFEN + I/O port F clock enable + 7 + 1 + + + ADC1EN + ADC1 clock + enable + 9 + 1 + + + TMR1EN + Timer1 clock enable + 11 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + TMR9EN + Timer9 clock enable + 19 + 1 + + + TMR10EN + Timer10 clock enable + 20 + 1 + + + TMR11EN + Timer11 clock enable + 21 + 1 + + + ACCEN + ACC clock enable + 22 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + (CRM_APB1EN) + 0x1C + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR4EN + Timer4 clock enable + 2 + 1 + + + TMR5EN + Timer5 clock enable + 3 + 1 + + + CMPEN + Comparator clock enable + 9 + 1 + + + WWDTEN + Window watchdog timer clock + enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + PWCEN + Power clock enable + 28 + 1 + + + + + BPDC + BPDC + Battery powered domain control register + (CRM_BPDC) + 0x20 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + ERTCSEL + ERTC clock selection + 8 + 2 + read-write + + + ERTCEN + ERTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + (CRM_CTRLSTS) + 0x24 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset flag clear + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + AHBRST + AHBRST + AHB reset register + + 0x28 + 0x20 + 0x00000000 + + + OTGFS1RST + OTGFS1 reset + 12 + 1 + read-write + + + + + PLL + PLL + PLL configuration register + (RCC_PLL) + 0x2C + 0x20 + 0x00001F10 + + + PLL_FR + PLL_FR + 0 + 3 + read-write + + + PLL_MS + PLL_MS + 4 + 4 + read-write + + + PLL_NS + PLL_NS + 8 + 9 + read-write + + + PLL_FREF + PLL entry clock reference frequency + 24 + 3 + read-write + + + PLLCFGEN + PLL config enable + 31 + 1 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register1 + 0x30 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + CLKOUT_SEL3 + Clock output bit3 + 16 + 1 + read-write + + + HICKDIV + HICK 6 divider selection + 25 + 1 + read-write + + + CLKOUTDIV + Clock output division + 28 + 4 + read-write + + + + + OTG_EXTCTRL + OTG_EXTCTRL + OTGFS external ctrl register1 + 0x44 + 0x20 + 0x00000000 + + + USBDIV_RST + USB divider reset + 30 + 1 + read-write + + + EP3_RMPEN + OTGFS end-point 3 remap enable + 31 + 1 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register2 + 0x54 + 0x20 + 0x0000000D + + + AUTO_STEP_EN + AUTO_STEP_EN + 4 + 2 + read-write + + + HICK_TO_USB + HICK to usb clock + 8 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 9 + 1 + read-write + + + + + + + GPIOA + General purpose IO + GPIO + 0x40010800 + + 0x0 + 0x400 + registers + + + + CFGLR + CFGLR + GPIO function configurate low register + 0x0 + 0x20 + read-write + 0x44444444 + + + IOMC0 + Port n.0 mode configurate bits + 0 + 2 + + + IOFC0 + Port n.0 function configurate + bits + 2 + 2 + + + IOMC1 + Port n.1 mode configurate bits + 4 + 2 + + + IOFC1 + Port n.1 function configurate + bits + 6 + 2 + + + IOMC2 + Port n.2 mode configurate bits + 8 + 2 + + + IOFC2 + Port n.2 function configurate + bits + 10 + 2 + + + IOMC3 + Port n.3 mode configurate bits + 12 + 2 + + + IOFC3 + Port n.3 function configurate + bits + 14 + 2 + + + IOMC4 + Port n.4 mode configurate bits + 16 + 2 + + + IOFC4 + Port n.4 function configurate + bits + 18 + 2 + + + IOMC5 + Port n.5 mode configurate bits + 20 + 2 + + + IOFC5 + Port n.5 function configurate + bits + 22 + 2 + + + IOMC6 + Port n.6 mode configurate bits + 24 + 2 + + + IOFC6 + Port n.6 function configurate + bits + 26 + 2 + + + IOMC7 + Port n.7 mode configurate bits + 28 + 2 + + + IOFC7 + Port n.7 function configurate + bits + 30 + 2 + + + + + CFGHR + CFGHR + GPIO function configurate high register + 0x4 + 0x20 + read-write + 0x44444444 + + + IOMC8 + Port n.8 mode configurate bits + 0 + 2 + + + IOFC8 + Port n.8 function configurate + bits + 2 + 2 + + + IOMC9 + Port n.9 mode configurate bits + 4 + 2 + + + IOFC9 + Port n.9 function configurate + bits + 6 + 2 + + + IOMC10 + Port n.10 mode configurate bits + 8 + 2 + + + IOFC10 + Port n.10 function configurate + bits + 10 + 2 + + + IOMC11 + Port n.11 mode configurate bits + 12 + 2 + + + IOFC11 + Port n.11 function configurate + bits + 14 + 2 + + + IOMC12 + Port n.12 mode configurate bits + 16 + 2 + + + IOFC12 + Port n.12 function configurate + bits + 18 + 2 + + + IOMC13 + Port n.13 mode configurate bits + 20 + 2 + + + IOFC13 + Port n.13 function configurate + bits + 22 + 2 + + + IOMC14 + Port n.14 mode configurate bits + 24 + 2 + + + IOFC14 + Port n.14 function configurate + bits + 26 + 2 + + + IOMC15 + Port n.15 mode configurate bits + 28 + 2 + + + IOFC15 + Port n.15 function configurate + bits + 30 + 2 + + + + + IDT + IDT + Port input data register + 0x8 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + Port output data register + 0xC + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x10 + 0x20 + read-write + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + CLR + CLR + Port bit reset register + 0x14 + 0x20 + read-write + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 1 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + WPR + WPR + Port write protect + register + 0x18 + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + + + GPIOB + 0x40010C00 + + + GPIOC + 0x40011000 + + + GPIOD + 0x40011400 + + + GPIOF + 0x40011C00 + + + IOMUX + IO MUX function + IOMUX + 0x40010000 + + 0x0 + 0x400 + registers + + + + EVTOUT + EVTOUT + Event output register + (IOMUX_EVTOUT) + 0x0 + 0x20 + read-write + 0x00000000 + + + SELPIN + Select pin + 0 + 4 + + + SELPORT + Select port + 4 + 3 + + + EVOEN + Event output enable + 7 + 1 + + + + + REMAP + REMAP + IO MUX remap register + 0x4 + 0x20 + 0x00000000 + + + SPI1_MUX0 + SPI1 muxing bit0 + 0 + 1 + read-write + + + I2C1_MUX + I2C1 muxing + 1 + 1 + read-write + + + USART1_MUX + USART1 muxing + 2 + 1 + read-write + + + USART3_MUX + USART3 muxing + 4 + 2 + read-write + + + TMR1_MUX + TMR1 muxing + 6 + 2 + read-write + + + TMR2_MUX + TMR2 muxing + 8 + 2 + read-write + + + TMR3_MUX + TMR3 muxing + 10 + 2 + read-write + + + CAN_MUX + CAN1 muxing + 13 + 2 + read-write + + + PD01_MUX + PD0/PD1 muxing on OSCIN/OSCOUT + 15 + 1 + read-write + + + TMR5CH4_MUX + TMR5 channel4 internal muxing + 16 + 1 + read-write + + + ADC1_ETP_MUX + ADC1 external trigger preempted conversion muxing + 17 + 1 + read-write + + + ADC1_ETO_MUX + ADC1 external trigger ordinary conversion muxing + 18 + 1 + read-write + + + SWJTAG_MUX + SWD JTAG muxing + 24 + 3 + read-write + + + SPI1_MUX1 + SPI1 muxing bit1 + 31 + 1 + read-write + + + + + EXINTC1 + EXINTC1 + External interrupt configuration register 1 + (IOMUX_EXINTC1) + 0x8 + 0x20 + read-write + 0x00000000 + + + EXINT0 + Configure EXINT0 source + 0 + 4 + + + EXINT1 + Configure EXINT1 source + 4 + 4 + + + EXINT2 + Configure EXINT2 source + 8 + 4 + + + EXINT3 + Configure EXINT3 source + 12 + 4 + + + + + EXINTC2 + EXINTC2 + External interrupt configuration register 2 + (IOMUX_EXINTC2) + 0xC + 0x20 + read-write + 0x00000000 + + + EXINT4 + Configure EXINT4 source + 0 + 4 + + + EXINT5 + Configure EXINT5 source + 4 + 4 + + + EXINT6 + Configure EXINT6 source + 8 + 4 + + + EXINT7 + Configure EXINT7 source + 12 + 4 + + + + + EXINTC3 + EXINTC3 + External interrupt configuration register 3 + (IOMUX_EXINTC3) + 0x10 + 0x20 + read-write + 0x00000000 + + + EXINT8 + Configure EXINT8 source + 0 + 4 + + + EXINT9 + Configure EXINT9 source + 4 + 4 + + + EXINT10 + Configure EXINT10 source + 8 + 4 + + + EXINT11 + Configure EXINT11 source + 12 + 4 + + + + + EXINTC4 + EXINTC4 + External interrupt configuration register 4 + (IOMUX_EXINTC4) + 0x14 + 0x20 + read-write + 0x00000000 + + + EXINT12 + Configure EXINT12 source + 0 + 4 + + + EXINT13 + Configure EXINT13 source + 4 + 4 + + + EXINT14 + Configure EXINT14 source + 8 + 4 + + + EXINT15 + Configure EXINT15 source + 12 + 4 + + + + + REMAP2 + REMAP2 + IO MUX remap register 2 + 0x1C + 0x20 + write-only + 0x00000000 + + + CMP_MUX + CMP internal muxing + 26 + 2 + + + + + REMAP3 + REMAP3 + IO MUX remap register 3 + 0x20 + 0x20 + read-write + 0x00000000 + + + TMR11_GMUX + TMR11 muxing + 8 + 4 + + + TMR10_GMUX + TMR10 muxing + 4 + 4 + + + TMR9_GMUX + TMR9 muxing + 0 + 4 + + + + + REMAP4 + REMAP4 + IO MUX remap register 4 + 0x24 + 0x20 + read-write + 0x00000000 + + + TMR5CH4_GMUX + TMR5CH4 muxing + 19 + 1 + + + TMR5_GMUX + TMR5 muxing + 16 + 3 + + + TMR3_GMUX + TMR3 muxing + 8 + 4 + + + TMR2_GMUX + TMR2 muxing + 4 + 3 + + + TMR1_GMUX + TMR1 muxing + 0 + 4 + + + + + REMAP5 + REMAP5 + IO MUX remap register 5 + 0x28 + 0x20 + read-write + 0x00000000 + + + SPI2_GMUX + SPI2 muxing + 20 + 4 + + + SPI1_GMUX + SPI1 muxing + 16 + 4 + + + I2C2_GMUX + I2C2 muxing + 8 + 4 + + + I2C1_GMUX + I2C1 muxing + 4 + 4 + + + + + REMAP6 + REMAP6 + IO MUX remap register 6 + 0x2C + 0x20 + read-write + 0x00000000 + + + UART4_GMUX + UART4 muxing + 28 + 4 + + + USART3_GMUX + USART3 muxing + 24 + 4 + + + USART1_GMUX + USART1 muxing + 16 + 4 + + + SDIO1_GMUX + SDIO1 muxing + 8 + 4 + + + CAN1_GMUX + CAN1 muxing + 0 + 4 + + + + + REMAP7 + REMAP7 + IO MUX remap register 7 + 0x30 + 0x20 + read-write + 0x00000000 + + + PD01_GMUX + PortD0/PortD1 muxing on OSC_IN/OSC_OUT + 20 + 1 + + + SWJTAG_GMUX + Serial wire JTAG muxing + 16 + 3 + + + ADC1_ETO_GMUX + ADC1 external trigger ordinary conversion muxing + 5 + 1 + + + ADC1_ETP_GMUX + ADC1 external trigger preempted conversion muxing + 4 + 1 + + + + + REMAP8 + REMAP8 + IO MUX remap register 8 + 0x34 + 0x20 + read-write + 0x00000000 + + + TMR3_CH1_CMP_GMUX + TMR3 CH1 CMP muxing + 6 + 2 + + + TMR2_CH4_CMP_GMUX + TMR2 CH4 CMP muxing + 4 + 2 + + + TMR1_CH1_CMP_GMUX + TMR1 CH1 CMP muxing + 2 + 2 + + + TMR1_BK1_CMP_GMUX + TMR1 BK1 CMP muxing + 0 + 2 + + + + + + + EXINT + EXINT + EXINT + 0x40010400 + + 0x0 + 0x400 + registers + + + PVM + PVD interrupt + 1 + + + ERTC + ERTC interrupt + 3 + + + TAMPER + Tamper interrupt + 2 + + + ERTCAlarm + ERTCAlarm interrupt + 41 + + + CMP1 + CMP1 interrupt + 70 + + + CMP2 + CMP2 interrupt + 71 + + + EXTINT0 + EXTI Line0 interrupt + 6 + + + EXTINT1 + EXTI Line1 interrupt + 7 + + + EXTINT2 + EXTI Line2 interrupt + 8 + + + EXTINT3 + EXTI Line3 interrupt + 9 + + + EXTINT4 + EXTI Line4 interrupt + 10 + + + EXTINT9_5 + EXTI Line[9:5] interrupts + 23 + + + EXTINT15_10 + EXTI Line[15:10] interrupts + 40 + + + + INTEN + INTEN + Interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + INTEN19 + Interrupt enable or disable on line 19 + 19 + 1 + + + INTEN20 + Interrupt enable or disable on line 20 + 20 + 1 + + + INTEN21 + Interrupt enable or disable on line 21 + 21 + 1 + + + INTEN22 + Interrupt enable or disable on line 22 + 22 + 1 + + + + + EVTEN + EVTEN + Event enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + EVTEN19 + Event enable or disable on line 19 + 19 + 1 + + + EVTEN20 + Event enable or disable on line 20 + 20 + 1 + + + EVTEN21 + Event enable or disable on line 21 + 21 + 1 + + + EVTEN22 + Event enable or disable on line 22 + 22 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + RP19 + Rising polarity configuration bit of line 19 + 19 + 1 + + + RP20 + Rising polarity configuration bit of line 20 + 20 + 1 + + + RP21 + Rising polarity configuration bit of line 21 + 21 + 1 + + + RP22 + Rising polarity configuration bit of line 22 + 22 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + FP19 + Falling polarity event configuration bit of line 19 + 19 + 1 + + + FP20 + Falling polarity event configuration bit of line 20 + 20 + 1 + + + FP21 + Falling polarity event configuration bit of line 21 + 21 + 1 + + + FP22 + Falling polarity event configuration bit of line 22 + 22 + 1 + + + + + SWTRG + SWTRG + Software triggle register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + SWT19 + Software triggle on line 19 + 19 + 1 + + + SWT20 + Software triggle on line 20 + 20 + 1 + + + SWT21 + Software triggle on line 21 + 21 + 1 + + + SWT22 + Software triggle on line 22 + 22 + 1 + + + + + INTSTS + INTSTS + Interrupt status register + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + LINE19 + Line 19 state bit + 19 + 1 + + + LINE20 + Line 20 state bit + 20 + 1 + + + LINE21 + Line 21 state bit + 21 + 1 + + + LINE22 + Line 22 state bit + 22 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 13 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 14 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 15 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 16 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 17 + + + + STS + STS + DMA status register (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA flag clear register (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_SRC_SEL0 + DMA_SRC_SEL0 + DMA channel source assignment register + 0xA0 + 0x20 + read-write + 0x00000000 + + + CH1_SRC + CH1 SRC select + 0 + 8 + + + CH2_SRC + CH2 SRC select + 8 + 8 + + + CH3_SRC + CH3 SRC select + 16 + 8 + + + CH4_SRC + CH4 SRC select + 24 + 8 + + + + + DMA_SRC_SEL1 + DMA_SRC_SEL1 + DMA channel source assignment register + 0xA4 + 0x20 + read-write + 0x00000000 + + + CH5_SRC + CH5 SRC select + 0 + 8 + + + CH6_SRC + CH6 SRC select + 8 + 8 + + + CH7_SRC + CH7 SRC select + 16 + 8 + + + DMA_FLEX_EN + DMA FLEX Enable + 24 + 1 + + + + + + + DMA2 + 0x40020400 + + DMA2_Channel1 + DMA2 Channel1 global interrupt + 56 + + + DMA2_Channel2 + DMA2 Channel2 global interrupt + 57 + + + DMA2_Channel3 + DMA2 Channel3 global interrupt + 58 + + + DMA2_Channel4_5 + DMA2 Channel4 and DMA2 Channel5 global + interrupt + 59 + + + DMA2_Channel6_7 + DMA2 Channel6 and DMA2 Channel7 global + interrupt + 75 + + + + SDIO1 + Secure digital input/output + interface + SDIO + 0x40018000 + + 0x0 + 0x400 + registers + + + SDIO1 + SDIO1 global interrupt + 49 + + + + POWER + POWER + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + PWRCTRL + 0 + 2 + + + + + CLKCTRL + CLKCTRL + SDI clock control register + (SDIO_CLKCTRL) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKPSC + Clock divide factor + 0 + 8 + + + CLKEN + Clock enable bit + 8 + 1 + + + PWRSVG + Power saving configuration + bit + 9 + 1 + + + BYPS + Clock divider bypass enable + bit + 10 + 1 + + + BUSWIDTH + Wide bus mode enable bit + 11 + 2 + + + CLKEDG + SDIO_CK dephasing selection + bit + 13 + 1 + + + FLWCTRLEN + HW Flow Control enable + 14 + 1 + + + CLKPSC98 + Clock divide factor bit9 and bit8 + 15 + 2 + + + + + ARG + ARG + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + ARG + Command argument + 0 + 32 + + + + + CMD + CMD + SDIO command register + (SDIO_CMD) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDIDX + CMDIDX + 0 + 6 + + + RSPWT + WAITRESP + 6 + 2 + + + INTWT + WAITINT + 8 + 1 + + + PNDWT + WAITPEND + 9 + 1 + + + CMDMEN + CPSMEN + 10 + 1 + + + SDIOSUSP + SDIOSuspend + 11 + 1 + + + + + RSPCMD + RSPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RSPCMD + RSPCMD + 0 + 6 + + + + + RSP1 + RSP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTS1 + CARDSTATUS1 + 0 + 32 + + + + + RSP2 + RSP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS2 + 0 + 32 + + + + + RSP3 + RSP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTS3 + CARDSTATUS3 + 0 + 32 + + + + + RSP4 + RSP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTS4 + CARDSTATUS4 + 0 + 32 + + + + + DTTMR + DTTMR + Bits 31:0 = DATATIME: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Data timeout period + 0 + 32 + + + + + DTLEN + DTLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DTLEN + Data length value + 0 + 25 + + + + + DTCTRL + DTCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TFREN + DTEN + 0 + 1 + + + TFRDIR + DTDIR + 1 + 1 + + + TFRMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + BLKSIZE + DBLOCKSIZE + 4 + 4 + + + RDWTSTART + PWSTART + 8 + 1 + + + RDWTSTOP + PWSTOP + 9 + 1 + + + RDWTMODE + RWMOD + 10 + 1 + + + SDIOEN + SDIOEN + 11 + 1 + + + + + DTCNTR + DTCNTR + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + CNT + Data count value + 0 + 25 + + + + + STS + STS + SDIO status register + (SDIO_STS) + 0x34 + 0x20 + read-only + 0x00000000 + + + CMDFAIL + CCRCFAIL + 0 + 1 + + + DTFAIL + DCRCFAIL + 1 + 1 + + + CMDTIMEOUT + CTIMEOUT + 2 + 1 + + + DTTIMEOUT + DTIMEOUT + 3 + 1 + + + TXERRU + TXUNDERR + 4 + 1 + + + RXERRO + RXOVERR + 5 + 1 + + + CMDRSPCMPL + CMDREND + 6 + 1 + + + CMDCMPL + CMDSENT + 7 + 1 + + + DTCMPL + DATAEND + 8 + 1 + + + SBITERR + STBITERR + 9 + 1 + + + DTBLKCMPL + DBCKEND + 10 + 1 + + + DOCMD + CMDACT + 11 + 1 + + + DOTX + TXACT + 12 + 1 + + + DORX + RXACT + 13 + 1 + + + TXBUF_H + TXFIFOHE + 14 + 1 + + + RXBUF_H + RXFIFOHF + 15 + 1 + + + TXBUF_F + TXFIFOF + 16 + 1 + + + RXBUF_F + RXFIFOF + 17 + 1 + + + TXBUF_E + TXFIFOE + 18 + 1 + + + RXBUF_E + RXFIFOE + 19 + 1 + + + TXBUF + TXDAVL + 20 + 1 + + + RXBUF + RXDAVL + 21 + 1 + + + SDIOIF + SDIOIT + 22 + 1 + + + + + INTCLR + INTCLR + SDIO interrupt clear register + (SDIO_INTCLR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CMDFAIL + CCRCFAILC + 0 + 1 + + + DTFAIL + DCRCFAILC + 1 + 1 + + + CMDTIMEOUT + CTIMEOUTC + 2 + 1 + + + DTTIMEOUT + DTIMEOUTC + 3 + 1 + + + TXERRU + TXUNDERRC + 4 + 1 + + + RXERRU + RXOVERRC + 5 + 1 + + + CMDRSPCMPL + CMDRENDC + 6 + 1 + + + CMDCMPL + CMDSENTC + 7 + 1 + + + DTCMPL + DATAENDC + 8 + 1 + + + SBITERR + STBITERRC + 9 + 1 + + + DTBLKCMPL + DBCKENDC + 10 + 1 + + + SDIOIF + SDIOITC + 22 + 1 + + + + + INTEN + INTEN + SDIO interrupt enable register + (SDIO_INTEN) + 0x3C + 0x20 + read-write + 0x00000000 + + + CMDFAIL + CCRCFAILIE + 0 + 1 + + + DTFAIL + DCRCFAILIE + 1 + 1 + + + CMDTIMEOUT + CTIMEOUTIE + 2 + 1 + + + DTTIMEOUT + DTIMEOUTIE + 3 + 1 + + + TXERRU + TXUNDERRIE + 4 + 1 + + + RXERRU + RXOVERRIE + 5 + 1 + + + CMDRSPCMPL + CMDRENDIE + 6 + 1 + + + CMDCMPL + CMDSENTIE + 7 + 1 + + + DTCMPL + DATAENDIE + 8 + 1 + + + SBITERR + STBITERRIE + 9 + 1 + + + DTBLKCMPL + DBACKENDIE + 10 + 1 + + + DOCMD + CMDACTIE + 11 + 1 + + + DOTX + TXACTIE + 12 + 1 + + + DORX + RXACTIE + 13 + 1 + + + TXBUF_H + TXFIFOHEIE + 14 + 1 + + + RXBUF_H + RXFIFOHFIE + 15 + 1 + + + TXBUF_F + TXFIFOFIE + 16 + 1 + + + RXBUF_F + RXFIFOFIE + 17 + 1 + + + TXBUF_E + TXFIFOEIE + 18 + 1 + + + RXBUF_E + RXFIFOEIE + 19 + 1 + + + TXBUF + TXDAVLIE + 20 + 1 + + + RXBUF + RXDAVLIE + 21 + 1 + + + SDIOIF + SDIOITIE + 22 + 1 + + + + + BUFCNTR + BUFCNTR + Bits 23:0 = FIFOCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + FIF0COUNT + 0 + 24 + + + + + BUF + BUF + bits 31:0 = FIFOData: Receive and transmit + FIFO data + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + FIFOData + 0 + 32 + + + + + + + ACC + HICK Auto Clock Calibration + ACC + 0x40015800 + + 0x0 + 0x400 + registers + + + ACC + ACC global interrupt + 72 + + + + STS + STS + Status register + 0x0 + 0x20 + read-write + 0x00000000 + + + CALRDY + Internal high-speed clock calibration ready + 0 + 1 + + + RSLOST + Reference Signal Lost + 1 + 1 + + + + + CTRL1 + CTRL1 + Control register 1 + 0x4 + 0x20 + read-write + 0x00000100 + + + CALON + Internal high-speed clock calibration ready + 0 + 1 + + + ENTRIM + Enable trim + 1 + 1 + + + EIEN + RSLOST error interrupt enable + 4 + 1 + + + CALRDYIEN + CALRDY interrupt enable + 5 + 1 + + + STEP + STEP + 8 + 4 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x8 + 0x20 + read-only + 0x00002080 + + + ACC_HSICAL + Internal high-speed auto clock calibration + 0 + 8 + + + ACC_HSITRIM + Internal high-speed auto clock trimming + 8 + 6 + + + + + C1 + C1 + Compare 1 + 0xC + 0x20 + read-write + 0x00001F2C + + + C1 + Compare 1 + 0 + 16 + + + + + C2 + C2 + Compare 2 + 0x10 + 0x20 + read-write + 0x00001F40 + + + C2 + Compare 2 + 0 + 16 + + + + + C3 + C3 + Compare 3 + 0x14 + 0x20 + read-write + 0x00001F54 + + + C3 + Compare 3 + 0 + 16 + + + + + + + ERTC + Real-time clock + ERTC + 0x40002800 + + 0x0 + 0x400 + registers + + + + TIME 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peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + UEN + USART enable + 13 + 1 + + + DBN + Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + ID + USART identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + ADC1 + Analog to digital converter + ADC1 + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC1 + ADC1 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 25 + 1 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 24 + 1 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + OCDMAEN + DMA transfer enable of ordinary channels + 8 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1_TX + CAN1 TX interrupt + 19 + + + CAN1_RX0 + CAN1 RX0 interrupt + 20 + + + CAN1_RX1 + CAN1 RX1 interrupt + 21 + + + CAN1_SE + CAN1 SE interrupt + 22 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RF0R + Receive FIFO 0 release + 5 + 1 + read-write + + + RF0OF + Receive FIFO 0 overflow flag + 4 + 1 + read-write + + + RF0FF + Receive FIFO 0 full flag + 3 + 1 + read-write + + + RF0MN + Receive FIFO 0 message num + 0 + 2 + read-only + + + + + RF1 + RF1 + Receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RF1R + Receive FIFO 1 release + 5 + 1 + read-write + + + RF1OF + Receive FIFO 1 overflow flag + 4 + 1 + read-write + + + RF1FF + Receive FIFO 1 full flag + 3 + 1 + read-write + + + RF1MN + Receive FIFO 1 message num + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + EDZIEN + Enter doze mode interrupt enable + 17 + 1 + + + QDZIEN + Quit doze mode interrupt enable + 16 + 1 + + + EOIEN + Error occur interrupt enable + 15 + 1 + + + ETRIEN + Error type record interrupt enable + 11 + 1 + + + BOIEN + Bus-off interrupt enable + 10 + 1 + + + EPIEN + Error passive interrupt enable + 9 + 1 + + + EAIEN + Error active interrupt enable + 8 + 1 + + + RF1OIEN + Receive FIFO 1 overflow interrupt enable + 6 + 1 + + + RF1FIEN + Receive FIFO 1 full interrupt enable + 5 + 1 + + + RF1MIEN + FIFO 1 receive message interrupt enable + 4 + 1 + + + RF0OIEN + Receive FIFO 0 overflow interrupt enable + 3 + 1 + + + RF0FIEN + Receive FIFO 0 full interrupt enable + 2 + 1 + + + RF0MIEN + FIFO 0 receive message interrupt enable + 1 + 1 + + + TCIEN + Transmission complete interrupt enable + 0 + 1 + + + + + ESTS + ESTS + Error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Transmit error counter + 16 + 8 + read-only + + + ETR + Error type record + 4 + 3 + read-write + + + BOF + Bus-off flag + 2 + 1 + read-only + + + EPF + Error passive flag + 1 + 1 + read-only + + + EAF + Error active flag + 0 + 1 + read-only + + + + + BTMG + BTMG + Bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOEN + Listen-Only mode + 31 + 1 + + + LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB2 + F1FB2 + Filter bank 1 filtrate bit register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB1 + F2FB1 + Filter bank 2 filtrate bit register 1 + 0x250 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB2 + F2FB2 + Filter bank 2 filtrate bit register 2 + 0x254 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F3FB1 + F3FB1 + Filter bank 3 filtrate bit register 1 + 0x258 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F3FB2 + F3FB2 + Filter bank 3 filtrate bit register 2 + 0x25C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F4FB1 + F4FB1 + Filter bank 4 filtrate bit register 1 + 0x260 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F4FB2 + F4FB2 + Filter bank 4 filtrate bit register 2 + 0x264 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F5FB1 + F5FB1 + Filter bank 5 filtrate bit register 1 + 0x268 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter 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read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 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Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB2 + F13FB2 + Filter bank 13 filtrate bit filtrate bit register 2 + 0x2AC + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + + + CMP + Comparator + CMP + 0x40002400 + + 0x0 + 0x3FF + registers + + + CMP1 + CMP1 interrupt + 70 + + + CMP2 + CMP2 interrupt + 71 + + + + CTRLSTS1 + CTRLSTS1 + CMP control/status register1 + 0x0 + 0x20 + 0x00000000 + + + CMP1EN + Comparator1 enable bit + 0 + 1 + read-write + + + CMP1IS + Comparator1 input shift + 1 + 1 + read-write + + + CMP1SSEL + Comparator1 speed selection + 2 + 2 + read-write + + + CMP1INVSEL + Comparator1 inverting selection + 4 + 3 + read-write + + + CMP1TAG + Comparator1 output target + 8 + 3 + read-write + + + CMP1P + Comparator1 polarity + 11 + 1 + read-write + + + CMP1HYST + Comparator1 hysteresis + 12 + 2 + read-write + + + CMP1VALUE + Comparator1 output value + 14 + 1 + read-only + + + CMP1WP + Comparator1 write protect + 15 + 1 + read-write + + + CMP2EN + Comparator2 enable bit + 16 + 1 + read-write + + + CMP2SSEL + Comparator2 speed selection + 18 + 2 + read-write + + + CMP2INVSEL + Comparator2 inverting selection + 20 + 3 + read-write + + + DCMPEN + Double comparator mode enable + 23 + 1 + read-write + + + CMP2TAG + Comparator2 output target + 24 + 3 + read-write + + + CMP2P + Comparator2 polarity + 27 + 1 + read-write + + + CMP2HYST + Comparator2 hysteresis + 28 + 2 + read-write + + + CMP2VALUE + Comparator2 output value + 30 + 1 + read-only + + + CMP2WP + Comparator2 write protect + 31 + 1 + read-write + + + + + CTRLSTS2 + CTRLSTS2 + CMP control/status register2 + 0x4 + 0x20 + 0x00000000 + + + COMP1NINVSEL + Comparator1 non-inverting input selection + 0 + 2 + read-write + + + COMP2NINVSEL + Comparator2 non-inverting input selection + 16 + 2 + read-write + + + + + + + DEBUG + Debug support + DEBUG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + DEBUG_IDCODE + DEBUG_IDCODE + DEBUG IDCODE + 0x0 + 0x20 + read-only + 0x0 + + + PID + PID + 0 + 32 + + + + + CTRL + CTRL + MCUDBG_CTRL + 0x4 + 0x20 + read-write + 0x0 + + + SLEEP_DEBUG + SLEEP_DEBUG + 0 + 1 + + + DEEPSLEEP_DEBUG + DEEPSLEEP_DEBUG + 1 + 1 + + + STANDBY_DEBUG + STANDBY_DEBUG + 2 + 1 + + + TRACE_IOEN + TRACE_IOEN + 5 + 1 + + + TRACE_MODE + TRACE_MODE + 6 + 2 + + + WDT_PAUSE + WDT_PAUSE + 8 + 1 + + + WWDT_PAUSE + WWDT_PAUSE + 9 + 1 + + + TMR1_PAUSE + TMR1_PAUSE + 10 + 1 + + + TMR2_PAUSE + TMR2_PAUSE + 11 + 1 + + + TMR3_PAUSE + TMR3_PAUSE + 12 + 1 + + + TMR4_PAUSE + TMR4_PAUSE + 13 + 1 + + + CAN1_PAUSE + CAN1_PAUSE + 14 + 1 + + + I2C1_SMBUS_TIMEOUT + I2C1_SMBUS_TIMEOUT + 15 + 1 + + + I2C2_SMBUS_TIMEOUT + I2C2_SMBUS_TIMEOUT + 16 + 1 + + + TMR5_PAUSE + TMR5_PAUSE + 18 + 1 + + + TMR9_PAUSE + TMR9_PAUSE + 28 + 1 + + + TMR10_PAUSE + TMR10_PAUSE + 29 + 1 + + + TMR11_PAUSE + TMR11_PAUSE + 30 + 1 + + + + + + + UART4 + Universal asynchronous receiver transmitter + 0x40004C00 + + UART4 + UART4 global interrupt + 52 + + + + UART5 + Universal asynchronous receiver transmitter + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DT + DT + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DT + Data Register + 0 + 32 + + + + + CDT + CDT + Common data register + 0x4 + 0x20 + read-write + 0x00000000 + + + CDT + Common Data + 0 + 1 + + + + + CTRL + CTRL + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RST + Reset bit + 0 + 1 + + + REVID + Reverse input data + 5 + 2 + + + REVOD + Reverse output data + 7 + 1 + + + + + IDT + IDT + Initial data register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + IDT + Initial Data + 0 + 32 + + + + + + + FLASH + Flash memory controler + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + PSR + PSR + Performance selection register + 0x0 + 0x20 + 0x00000030 + + + WTCYC + Wait cycle + 0 + 3 + read-write + + + HFCYC_EN + Half cycle acceleration access enable + 3 + 1 + read-write + + + PFT_EN + Prefetch enable + 4 + 1 + read-write + + + PFT_ENF + Prefetch enabled flag + 5 + 1 + read-only + + + + + UNLOCK + UNLOCK + Unlock register + 0x4 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + USD_UNLOCK + USD_UNLOCK + USD unlock register + 0x8 + 0x20 + write-only + 0x00000000 + + + USD_UKVAL + User system data Unlock key value + 0 + 32 + + + + + STS + STS + Status register + 0xC + 0x20 + 0x00000000 + + + ODF + Operate done flag + 5 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + PRGMERR + program error + 2 + 1 + read-write + + + OBF + Operate busy flag + 0 + 1 + read-only + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + USDPRGM + User system data program + 4 + 1 + + + USDERS + User system data erase + 5 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + USDULKS + User system data unlock success + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + FAP_HL_DIS + FAP high level disable + 16 + 1 + + + + + ADDR + ADDR + Address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + USD + USD + User system data register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + USDERR + User system data error + 0 + 1 + + + FAP + FLASH access protection + 1 + 1 + + + nWDT_ATO_EN + WDT auto enable + 2 + 1 + + + nDEPSLP_RST + Deepsleep reset + 3 + 1 + + + nSTDBY_RST + Standby reset + 4 + 1 + + + USER_D0 + User data 0 + 10 + 8 + + + USER_D1 + User data 1 + 18 + 8 + + + FAP_HL + FAP high level + 26 + 1 + + + + + EPPS + EPPS + Erase/program protection status register + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + SLIB_STS0 + SLIB_STS0 + sLib status 0 register + 0x74 + 0x20 + read-only + 0x00000000 + + + BTM_AP_ENF + Boot memory store application code enabled flag + 0 + 1 + + + EM_SLIB_ENF + Extension memory sLib enabled flag + 2 + 1 + + + SLIB_ENF + sLib enabled flag + 3 + 1 + + + EM_SLIB_DAT_SS + Extension memory sLib data start sector + 16 + 8 + + + + + SLIB_STS1 + SLIB_STS1 + sLib status 1 register + 0x78 + 0x20 + read-only + 0xFFFFFFFF + + + SLIB_SS + sLib start sector + 0 + 11 + + + SLIB_DAT_SS + sLib data start sector + 11 + 11 + + + SLIB_ES + sLib end sector + 22 + 10 + + + + + SLIB_PWD_CLR + SLIB_PWD_CLR + SLIB password clear register + 0x7C + 0x20 + 0x00000000 + write-only + + + SLIB_PCLR_VAL + sLib password clear value + 0 + 32 + + + + + SLIB_MISC_STS + SLIB_MISC_STS + sLib misc status register + 0x80 + 0x20 + 0x00000000 + + + SLIB_PWD_ERR + sLib password error + 0 + 1 + read-only + + + SLIB_PWD_OK + sLib password ok + 1 + 1 + read-only + + + SLIB_ULKF + sLib unlock flag + 2 + 1 + read-only + + + + + CRC_ADDR + CRC_ADDR + Flash CRC data start address register + 0x84 + 0x20 + write-only + 0x00000000 + + + CRC_ADDR + CRC address + 0 + 32 + + + + + CRC_CTRL + CRC_CTRL + Flash CRC controll register + 0x88 + 0x20 + 0x00000000 + + + CRC_SN + CRC sector numbler + 0 + 16 + read-write + + + CRC_STRT + CRC start + 16 + 1 + write-only + + + + + CRC_CHKR + CRC_CHKR + FLASH CRC check result register + 0x8C + 0x20 + read-only + 0x00000000 + + + FCRC_OUT + CRC32 verification result of flash user code or SLIB code + 0 + 32 + + + + + SLIB_SET_PWD + SLIB_SET_PWD + sLib password setting register + 0x160 + 0x20 + write-only + 0x00000000 + + + SLIB_PSET_VAL + sLib password setting val + 0 + 32 + + + + + SLIB_SET_RANGE + SLIB_SET_RANGE + Configure sLib range register + 0x164 + 0x20 + write-only + 0x00000000 + + + SLIB_SS_SET + sLib start sector setting + 0 + 11 + + + SLIB_DSS_SET + sLib data start sector setting + 11 + 11 + + + SLIB_ES_SET + sLib end sector setting + 22 + 10 + + + + + EM_SLIB_SET + EM_SLIB_SET + Extension momery slib set register + 0x168 + 0x20 + write-only + 0x00000000 + + + EM_SLIB_SET + Extension memory sLib setting + 0 + 16 + + + EM_SLIB_DSS_SET + Extension memory sLib data start sector setting + 16 + 8 + + + + + BTM_MODE_SET + BTM_MODE_SET + Boot memory mode setting register + 0x16C + 0x20 + write-only + 0x00000000 + + + BTM_MODE_SET + Boot memory mode setting + 0 + 8 + + + + + SLIB_UNLOCK + SLIB_UNLOCK + sLib unlock register + 0x170 + 0x20 + write-only + 0x00000000 + + + SLIB_UKVAL + sLib unlock key value + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + USB_OTG_GLOBAL + USB on the go full speed + USB_OTG + 0x50000000 + + 0x0 + 0x400 + registers + + + OTGFS + USB On The Go FS global + interrupt + 77 + + + + GOTGCTL + GOTGCTL + OTGFS control and status register + (OTGFS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGFS interrupt register + (OTGFS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGFS AHB configuration register + (OTGFS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGFS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + FS timeout calibration + 0 + 3 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGFS reset register + (OTGFS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGFS core interrupt register + (OTGFS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-only + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGFS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGFS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGFS Receive FIFO size register + (OTGFS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGFS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGFS non-periodic transmit FIFO/queue + status register (OTGFS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGFS general core configuration register + (OTGFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + AVALIDSESEN + sense Avalid enable + 18 + 1 + + + BVALIDSESEN + sense Bvalid enable + 19 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGFS Host periodic transmit FIFO size + register (OTGFS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTG_HOST + USB on the go full speed + USB_OTG + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGFS host configuration register + (OTGFS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGFS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGFS host frame number/frame time + remaining register (OTGFS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGFS_Host periodic transmit FIFO/queue + status register (OTGFS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGFS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGFS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGFS host port control and status register + (OTGFS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGFS host channel-0 characteristics + register (OTGFS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGFS host channel-1 characteristics + register (OTGFS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGFS host channel-2 characteristics + register (OTGFS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGFS host channel-3 characteristics + register (OTGFS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGFS host channel-4 characteristics + register (OTGFS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGFS host channel-5 characteristics + register (OTGFS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGFS host channel-6 characteristics + register (OTGFS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGFS host channel-0 interrupt register + (OTGFS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGFS host channel-2 interrupt register + (OTGFS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGFS host channel-3 interrupt register + (OTGFS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGFS host channel-4 interrupt register + (OTGFS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGFS host channel-5 interrupt register + (OTGFS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGFS host channel-6 interrupt register + (OTGFS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGFS host channel-7 interrupt register + (OTGFS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGFS host channel-0 mask register + (OTGFS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGFS host channel-1 mask register + (OTGFS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGFS host channel-2 mask register + (OTGFS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGFS host channel-3 mask register + (OTGFS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGFS host channel-4 mask register + (OTGFS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGFS host channel-5 mask register + (OTGFS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGFS host channel-6 mask register + (OTGFS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGFS host channel-7 mask register + (OTGFS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGFS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ1 + HCTSIZ1 + OTGFS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ2 + HCTSIZ2 + OTGFS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ3 + HCTSIZ3 + OTGFS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ4 + HCTSIZ4 + OTGFS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ5 + HCTSIZ5 + OTGFS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ6 + HCTSIZ6 + OTGFS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ7 + HCTSIZ7 + OTGFS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + + + USB_OTG_DEVICE + USB on the go full speed + USB_OTG + 0x50000800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGFS device configuration register + (OTGFS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGFS device control register + (OTGFS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTGFS device IN endpoint common interrupt + mask register (OTGFS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTGFS device OUT endpoint common interrupt + mask register (OTGFS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + + + DAINT + DAINT + OTGFS device all endpoints interrupt + register (OTGFS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGFS all endpoints interrupt mask register + (OTGFS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGFS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEPCTL0 + DIEPCTL0 + OTGFS device control IN endpoint 0 control + register (OTGFS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-only + + + EPTENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTGFS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGFS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGFS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGFS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGFS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGFS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGFS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGFS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT1 + DIEPINT1 + OTGFS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT2 + DIEPINT2 + OTGFS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT3 + DIEPINT3 + OTGFS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DOEPINT0 + DOEPINT0 + OTGFS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT1 + DOEPINT1 + OTGFS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT2 + DOEPINT2 + OTGFS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT3 + DOEPINT3 + OTGFS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGFS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGFS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGFS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGFS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + OTGFS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGFS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGFS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGFS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGFS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGFS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGFS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + + + USB_OTG_PWRCLK + USB on the go full speed + USB_OTG + 0x50000E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGFS power and clock gating control + register (OTGFS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + diff --git a/hw/bsp/at32f415/boards/AT_START_F415/board.h b/hw/bsp/at32f415/boards/AT_START_F415/board.h new file mode 100644 index 000000000..8b933f9e9 --- /dev/null +++ b/hw/bsp/at32f415/boards/AT_START_F415/board.h @@ -0,0 +1,80 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define USB_VBUS_IGNORE + +// LED +#define LED_PORT GPIOC +#define LED_PIN GPIO_PINS_2 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +// Usart +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK + +//USB +#define USB_ID 0 +#define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK +#define OTG_IRQ OTGFS1_IRQn +#define OTG_IRQ_HANDLER OTGFS1_IRQHandler +#define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn +#define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler +#define OTG_WKUP_EXINT_LINE EXINT_LINE_18 +#define OTG_PIN_GPIO GPIOA +#define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_VBUS GPIO_PINS_9 +#define OTG_PIN_ID GPIO_PINS_10 +#define OTG_PIN_SOF_GPIO GPIOA +#define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_SOF GPIO_PINS_8 + +static inline void board_vbus_sense_init(void) +{ + *(int*)(0x50000038) |= (1<<21); +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f415/boards/AT_START_F415/board.mk b/hw/bsp/at32f415/boards/AT_START_F415/board.mk new file mode 100644 index 000000000..6c877ec71 --- /dev/null +++ b/hw/bsp/at32f415/boards/AT_START_F415/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F415xC_FLASH.ld + +CFLAGS += \ + -DAT32F415RCT7 diff --git a/hw/bsp/at32f415/family.c b/hw/bsp/at32f415/family.c new file mode 100644 index 000000000..6c7600783 --- /dev/null +++ b/hw/bsp/at32f415/family.c @@ -0,0 +1,287 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f415_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void uart_print_init(uint32_t baudrate); +void usb_clock48m_select(usb_clk48_s clk_s); +void led_and_button_init(void); + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTGFS1_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGFS1_WKUP_IRQHandler(void) +{ + tusb_int_handler(0, true); +} + +void board_init(void) +{ + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* config system clock */ + system_clock_config(); + + /* enable usb clock */ + crm_periph_clock_enable(OTG_CLOCK, TRUE); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HEXT); + + /* vbus ignore */ + board_vbus_sense_init(); + + /* configure systick */ + systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); + SysTick_Config(SystemCoreClock / 1000); + #if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + #endif + + /* otgfs use vbus pin */ + #ifndef USB_VBUS_IGNORE + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); + #endif + + /* config led and key */ + led_and_button_init(); + + /* config usart printf */ + uart_print_init(115200); + printf("usart printf config success!\r\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + (void) clk_s; + switch(system_core_clock) + { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_1); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_1_5); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + /* 120MHz */ + case 120000000: + crm_usb_clock_div_set(CRM_USB_DIV_2_5); + break; + + /* 144MHz */ + case 144000000: + crm_usb_clock_div_set(CRM_USB_DIV_3); + break; + + default: + break; + } +} + +void led_and_button_init(void) +{ + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); +} + +/** + * @brief initialize uart + * @param baudrate: uart baudrate + * @retval none + */ +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +// Get characters from UART. Return number of read bytes +int board_uart_read(uint8_t *buf, int len) +{ + (void) buf; + (void) len; + return 0; +} + +// Send characters to UART. Return number of sent bytes +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + +void board_led_write(bool state) +{ + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) +{ + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + + +#if CFG_TUSB_OS == OPT_OS_NONE + + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + + uint32_t board_millis(void) + { + return system_ticks; + } + + void SVC_Handler(void) + { + } + + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) +{ + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/at32f415/family.mk b/hw/bsp/at32f415/family.mk new file mode 100644 index 000000000..d0cca67ab --- /dev/null +++ b/hw/bsp/at32f415/family.mk @@ -0,0 +1,43 @@ +# Submodules +AT32F415_SDK = hw/mcu/artery/at32f415 +DEPS_SUBMODULES += $(AT32F415_SDK) + +# AT32 SDK path +AT32F415_SDK_SRC = $(AT32F415_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m3 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F415 \ + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(AT32F415_SDK_SRC)/drivers/src/at32f415_gpio.c \ + $(AT32F415_SDK_SRC)/drivers/src/at32f415_misc.c \ + $(AT32F415_SDK_SRC)/drivers/src/at32f415_usart.c \ + $(AT32F415_SDK_SRC)/drivers/src/at32f415_crm.c \ + $(AT32F415_SDK_SRC)/cmsis/cm4/device_support/system_at32f415.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F415_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F415_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F415_SDK_SRC)/cmsis/cm4/device_support + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f415.s + +# For freeRTOS port source +#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4 + +flash: flash-atlink diff --git a/hw/bsp/at32f415/startup_at32f415.s b/hw/bsp/at32f415/startup_at32f415.s new file mode 100644 index 000000000..47a913e36 --- /dev/null +++ b/hw/bsp/at32f415/startup_at32f415.s @@ -0,0 +1,407 @@ +/** + ****************************************************************************** + * @file startup_at32f415.s + * @brief at32f415xx devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */ + .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_IRQHandler /* ADC1 */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word ERTCAlarm_IRQHandler /* ERTC Alarm through EXINT Line */ + .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SDIO1_IRQHandler /* SDIO1 */ + .word TMR5_GLOBAL_IRQHandler /* TMR5 */ + .word 0 /* Reserved */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */ + .word DMA2_Channel4_5_IRQHandler /* DMA2 Channel4 & Channel5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTGFS1_IRQHandler /* OTGFS1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word CMP1_IRQHandler /* CMP1 */ + .word CMP2_IRQHandler /* CMP2 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Channel6_7_IRQHandler /* DMA2 Channel6 & Channel7 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak ERTC_WKUP_IRQHandler + .thumb_set ERTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak ERTCAlarm_IRQHandler + .thumb_set ERTCAlarm_IRQHandler,Default_Handler + + .weak OTGFS1_WKUP_IRQHandler + .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler + + .weak SDIO1_IRQHandler + .thumb_set SDIO1_IRQHandler,Default_Handler + + .weak TMR5_GLOBAL_IRQHandler + .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak OTGFS1_IRQHandler + .thumb_set OTGFS1_IRQHandler,Default_Handler + + .weak CMP1_IRQHandler + .thumb_set CMP1_IRQHandler,Default_Handler + + .weak CMP2_IRQHandler + .thumb_set CMP2_IRQHandler,Default_Handler + + .weak DMA2_Channel6_7_IRQHandler + .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..06afc3860 --- /dev/null +++ b/hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f423.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd b/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd new file mode 100644 index 000000000..4954c417f --- /dev/null +++ b/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd @@ -0,0 +1,36050 @@ + + + + + + + + Keil + ArteryTek + AT32F423xx_v2 + AT32F423 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 288MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + XMC + Flexible static memory controller + XMC + 0xA0000000 + + 0x0 + 0x1000 + registers + + + XMC + XMC global interrupt + 48 + + + + BK1CTRL1 + BK1CTRL1 + SRAM/NOR-Flash chip-select control register + 1 + 0x0 + 0x20 + read-write + 0x000030DB + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG1 + BK1TMG1 + SRAM/NOR-Flash chip-select timing register + 1 + 0x4 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1CTRL2 + BK1CTRL2 + SRAM/NOR-Flash chip-select control register + 2 + 0x8 + 0x20 + read-write + 0x000030D2 + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG2 + BK1TMG2 + SRAM/NOR-Flash chip-select timing register + 2 + 0xC + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1CTRL4 + BK1CTRL4 + SRAM/NOR-Flash chip-select control register + 4 + 0x18 + 0x20 + read-write + 0x000030D2 + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG4 + BK1TMG4 + SRAM/NOR-Flash chip-select timing register + 4 + 0x1C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR1 + BK1TMGWR1 + SRAM/NOR-Flash write timing registers + 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR2 + BK1TMGWR2 + SRAM/NOR-Flash write timing registers + 2 + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR4 + BK1TMGWR4 + SRAM/NOR-Flash write timing registers + 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + EXT1 + EXT1 + externl timeing register 1 + 0x220 + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + EXT2 + EXT2 + externl timeing register 2 + 0x224 + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + EXT4 + EXT4 + externl timeing register 4 + 0x22C + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Power control register + (PWC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + VRSEL + Voltage regulator state select when deepsleep mode + 0 + 1 + + + LPSEL + Low power mode select when Cortex-M4F sleepdeep + 1 + 1 + + + CLSWEF + Clear SWEF flag + 2 + 1 + + + CLSEF + Clear SEF flag + 3 + 1 + + + PVMEN + Power voltage monitoring enable + 4 + 1 + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + + + BPWEN + Battery powered domain write enable + 8 + 1 + + + + + CTRLSTS + CTRLSTS + Power control and status register + (PWC_CTRLSTS) + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN1 + Standby wake-up pin 1 enable + 8 + 1 + read-write + + + SWPEN2 + Standby wake-up pin 2 enable + 9 + 1 + read-write + + + SWPEN6 + Standby wake-up pin 6 enable + 13 + 1 + read-write + + + SWPEN7 + Standby wake-up pin 7 enable + 14 + 1 + read-write + + + + + LDOOV + LDOOV + LDO output voltage register + 0x10 + 0x20 + 0x00000000 + + + LDOOVSEL + LDO output voltage select + 0 + 2 + read-write + + + VREXLPEN + Voltage regulator extra low power mode enable + 4 + 1 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40023800 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 5 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + + + PLLCFG + PLLCFG + PLL configuration register + (CRM_PLLCFG) + 0x4 + 0x20 + 0x00033002 + + + PLL_MS + PLL pre-division + 0 + 4 + read-write + + + PLL_NS + PLL frequency multiplication factor + 6 + 9 + read-write + + + PLL_FR + PLL post-division + 16 + 3 + read-write + + + PLLRCS + PLL reference clock select + 22 + 1 + read-write + + + + + CFG + CFG + Clock configuration register(CRM_CFG) + 0x8 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 10 + 3 + read-write + + + APB2DIV + APB2 division + 13 + 3 + read-write + + + ERTCDIV + HEXT division for ERTC clock + 16 + 5 + read-write + + + CLKOUTDIV1 + Clock output division1 + 27 + 3 + read-write + + + CLKOUT_SEL1 + Clock output selection1 + 30 + 2 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + (CRM_CLKINT) + 0xC + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + AHBRST1 + AHBRST1 + AHB peripheral reset register1 + (CRM_AHBRST1) + 0x10 + 0x20 + read-write + 0x000000000 + + + GPIOARST + IO port A reset + 0 + 1 + + + GPIOBRST + IO port B reset + 1 + 1 + + + GPIOCRST + IO port C reset + 2 + 1 + + + GPIODRST + IO port D reset + 3 + 1 + + + GPIOERST + IO port E reset + 4 + 1 + + + GPIOFRST + IO port F reset + 5 + 1 + + + CRCRST + CRC reset + 12 + 1 + + + DMA1RST + DMA1 reset + 22 + 1 + + + DMA2RST + DMA2 reset + 24 + 1 + + + + + AHBRST2 + AHBRST2 + AHB peripheral reset register 2 + (CRM_AHBRST2) + 0x14 + 0x20 + read-write + 0x00000000 + + + OTGFS1RST + OTGFS1 reset + 7 + 1 + + + + + AHBRST3 + AHBRST3 + AHB peripheral reset register 3 + (CRM_AHBRST3) + 0x18 + 0x20 + read-write + 0x00000000 + + + XMCRST + XMC reset + 0 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + (CRM_APB1RST) + 0x20 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer2 reset + 0 + 1 + + + TMR3RST + Timer3 reset + 1 + 1 + + + TMR4RST + Timer4 reset + 2 + 1 + + + TMR6RST + Timer6 reset + 4 + 1 + + + TMR7RST + Timer7 reset + 5 + 1 + + + TMR12RST + Timer12 reset + 6 + 1 + + + TMR13RST + Timer13 reset + 7 + 1 + + + TMR14RST + Timer14 reset + 8 + 1 + + + WWDTRST + Window watchdog reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + USART2RST + USART2 reset + 17 + 1 + + + USART3RST + USART3 reset + 18 + 1 + + + USART4RST + USART4 reset + 19 + 1 + + + USART5RST + USART5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + CAN2RST + CAN2 reset + 26 + 1 + + + PWCRST + PWC reset + 28 + 1 + + + DACRST + DAC reset + 29 + 1 + + + USART7RST + USART7 reset + 30 + 1 + + + USART8RST + USART8 reset + 31 + 1 + + + + + APB2RST + APB2RST + APB2 peripheral reset register + (CRM_APB2RST) + 0x24 + 0x20 + read-write + 0x00000000 + + + TMR1RST + Timer1 reset + 0 + 1 + + + USART1RST + USART1 reset + 4 + 1 + + + USART6RST + USART6 reset + 5 + 1 + + + ADCRST + ADC reset + 8 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + SCFGRST + SCFG reset + 14 + 1 + + + TMR9RST + Timer9 reset + 16 + 1 + + + TMR10RST + Timer10 reset + 17 + 1 + + + TMR11RST + Timer 11 reset + 18 + 1 + + + ACCRST + ACC reset + 29 + 1 + + + + + AHBEN1 + AHBEN1 + AHB Peripheral Clock enable register 1 + (CRM_AHBEN1) + 0x30 + 0x20 + read-write + 0x00000000 + + + GPIOAEN + IO A clock enable + 0 + 1 + + + GPIOBEN + IO B clock enable + 1 + 1 + + + GPIOCEN + IO C clock enable + 2 + 1 + + + GPIODEN + IO D clock enable + 3 + 1 + + + GPIOEEN + IO E clock enable + 4 + 1 + + + GPIOFEN + IO F clock enable + 5 + 1 + + + CRCEN + CRC clock enable + 12 + 1 + + + DMA1EN + DMA1 clock enable + 22 + 1 + + + DMA2EN + DMA2 clock enable + 24 + 1 + + + + + AHBEN2 + AHBEN2 + AHB peripheral clock enable register 2 + (CRM_AHBEN2) + 0x34 + 0x20 + read-write + 0x00000000 + + + OTGFS1EN + OTGFS1 clock enable + 7 + 1 + + + + + AHBEN3 + AHBEN3 + AHB peripheral clock enable register 3 + (CRM_AHBEN3) + 0x38 + 0x20 + read-write + 0x00000000 + + + XMCEN + XMC clock enable + 0 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + (CRM_APB1EN) + 0x40 + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR4EN + Timer4 clock enable + 2 + 1 + + + TMR6EN + Timer6 clock enable + 4 + 1 + + + TMR7EN + Timer7 clock enable + 5 + 1 + + + TMR12EN + Timer12 clock enable + 6 + 1 + + + TMR13EN + Timer13 clock enable + 7 + 1 + + + TMR14EN + Timer14 clock enable + 8 + 1 + + + WWDTEN + WWDT clock enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + USART4EN + USART4 clock enable + 19 + 1 + + + USART5EN + USART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + CAN2EN + CAN2 clock enable + 26 + 1 + + + PWCEN + PWC clock enable + 28 + 1 + + + DACEN + DAC clock enable + 29 + 1 + + + USART7EN + USART7 clock enable + 30 + 1 + + + USART8EN + USART8 clock enable + 31 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + (CRM_APB2EN) + 0x44 + 0x20 + read-write + 0x00000000 + + + TMR1EN + Timer1 clock enable + 0 + 1 + + + USART1EN + USART1 clock enable + 4 + 1 + + + USART6EN + USART6 clock enable + 5 + 1 + + + ADCEN + ADC clock enable + 8 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + SCFGEN + SCFG clock enable + 14 + 1 + + + TMR9EN + Timer9 clock enable + 16 + 1 + + + TMR10EN + Timer10 clock enable + 17 + 1 + + + TMR11EN + Timer11 clock enable + 18 + 1 + + + ACCEN + ACC clock enable + 29 + 1 + + + + + AHBLPEN1 + AHBLPEN1 + AHB Low-power Peripheral Clock enable + register 1 (CRM_AHBLPEN1) + 0x50 + 0x20 + read-write + 0x3E6390FF + + + GPIOALPEN + IO A clock enable during sleep mode + 0 + 1 + + + GPIOBLPEN + IO B clock enable during sleep mode + 1 + 1 + + + GPIOCLPEN + IO C clock enable during sleep mode + 2 + 1 + + + GPIODLPEN + IO D clock enable during sleep mode + 3 + 1 + + + GPIOELPEN + IO E clock enable during sleep mode + 4 + 1 + + + GPIOFLPEN + IO F clock enable during sleep mode + 5 + 1 + + + CRCLPEN + CRC clock enable during sleep mode + 12 + 1 + + + FLASHLPEN + Flash clock enable during sleep mode + 15 + 1 + + + SRAMLPEN + SRAM clock enable during sleep mode + 16 + 1 + + + DMA1LPEN + DMA1 clock enable during sleep mode + 22 + 1 + + + DMA2LPEN + DMA2 clock enable during sleep mode + 24 + 1 + + + + + AHBLPEN2 + AHBLPEN2 + AHB peripheral Low-power clock + enable register 2 (CRM_AHBLPEN2) + 0x54 + 0x20 + read-write + 0x00008081 + + + OTGFS1LPEN + OTGFS1 clock enable during sleep mode + 7 + 1 + + + + + AHBLPEN3 + AHBLPEN3 + AHB peripheral Low-power clock + enable register 3 (CRM_AHBLPEN3) + 0x58 + 0x20 + read-write + 0x0000C003 + + + XMCLPEN + XMC clock enable during sleep mode + 0 + 1 + + + + + APB1LPEN + APB1LPEN + APB1 peripheral Low-power clock + enable register (CRM_APB1LPEN) + 0x60 + 0x20 + read-write + 0xF6FEE9FF + + + TMR2LPEN + Timer2 clock enable during sleep mode + 0 + 1 + + + TMR3LPEN + Timer3 clock enable during sleep mode + 1 + 1 + + + TMR4LPEN + Timer4 clock enable during sleep mode + 2 + 1 + + + TMR6LPEN + Timer6 clock enable during sleep mode + 4 + 1 + + + TMR7LPEN + Timer7 clock enable during sleep mode + 5 + 1 + + + TMR12LPEN + Timer12 clock enable during sleep mode + 6 + 1 + + + TMR13LPEN + Timer13 clock enable during sleep mode + 7 + 1 + + + TMR14LPEN + Timer14 clock enable during sleep mode + 8 + 1 + + + WWDTLPEN + WWDT clock enable during sleep mode + 11 + 1 + + + SPI2LPEN + SPI2 clock enable during sleep mode + 14 + 1 + + + SPI3LPEN + SPI3 clock enable during sleep mode + 15 + 1 + + + USART2LPEN + USART2 clock enable during sleep mode + 17 + 1 + + + USART3LPEN + USART3 clock enable during sleep mode + 18 + 1 + + + USART4LPEN + USART4 clock enable during sleep mode + 19 + 1 + + + USART5LPEN + USART5 clock enable during sleep mode + 20 + 1 + + + I2C1CPEN + I2C1 clock enable during sleep mode + 21 + 1 + + + I2C2CPEN + I2C2 clock enable during sleep mode + 22 + 1 + + + I2C3CPEN + I2C3 clock enable during sleep mode + 23 + 1 + + + CAN1LPEN + CAN1 clock enable during sleep mode + 25 + 1 + + + CAN2LPEN + CAN2 clock enable during sleep mode + 26 + 1 + + + PWCLPEN + PWC clock enable during sleep mode + 28 + 1 + + + DACLPEN + DAC clock enable during sleep mode + 29 + 1 + + + USART7LPEN + USART7 clock enable during sleep mode + 30 + 1 + + + USART8LPEN + USART8 clock enable during sleep mode + 31 + 1 + + + + + APB2LPEN + APB2LPEN + APB2 peripheral Low-power clock + enable register (CRM_APB2LPEN) + 0x64 + 0x20 + read-write + 0x20177733 + + + TMR1LPEN + Timer1 clock enable during sleep mode + 0 + 1 + + + USART1LPEN + USART1 clock enable during sleep mode + 4 + 1 + + + USART6LPEN + USART6 clock enable during sleep mode + 5 + 1 + + + ADCLPEN + ADC clock enable during sleep mode + 8 + 1 + + + SPI1LPEN + SPI1 clock enable during sleep mode + 12 + 1 + + + SCFGLPEN + SCFG clock enable during sleep mode + 14 + 1 + + + TMR9LPEN + Timer9 clock enable during sleep mode + 16 + 1 + + + TMR10LPEN + Timer10 clock enable during sleep mode + 17 + 1 + + + TMR11LPEN + Timer11 clock enable during sleep mode + 18 + 1 + + + ACCLPEN + ACC clock enable during sleep mode + 29 + 1 + + + + + PICLKS + PICLKS + Peripheral independent clock register + (CRM_PICLKS) + 0x68 + 0x20 + 0x00000000 + + + USART1SEL + USART1 clock select + 0 + 2 + read-write + + + USART2SEL + USART2 clock select + 2 + 2 + read-write + + + USART3SEL + USART3 clock select + 4 + 2 + read-write + + + I2C1SEL + I2C1 clock select + 12 + 2 + read-write + + + + + BPDC + BPDC + Battery powered domain control register + (CRM_BPDC) + 0x70 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + ERTCSEL + ERTC clock source selection + 8 + 2 + read-write + + + ERTCEN + ERTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + (CRM_CTRLSTS) + 0x74 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset reset flag + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register1 + 0xA0 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + HICKDIV + HICK 6 divider selection + 12 + 1 + read-write + + + HICK_TO_USB + HICK to usb clock + 13 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 14 + 1 + read-write + + + PLLCLK_TO_ADC + ADC clock source select + 15 + 1 + read-write + + + CLKOUT_SEL2 + Clock output select2 + 16 + 4 + read-write + + + CLKOUTDIV2 + Clock output division2 + 28 + 4 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register2 + 0xA4 + 0x20 + 0x0000000D + + + AUTO_STEP_EN + AUTO_STEP_EN + 4 + 2 + read-write + + + USBDIV + USB division + 12 + 4 + read-write + + + HICK_TO_SCLK_DIV + HICK as system clock frequency division + 16 + 3 + read-write + + + HEXT_TO_SCLK_DIV + HEXT as system clock frequency division + 19 + 3 + read-write + + + + + + + GPIOA + General purpose I/Os + GPIO + 0x40020000 + + 0x0 + 0x400 + registers + + + + CFGR + CFGR + GPIO configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + IOMC15 + GPIOx pin 15 mode configurate + 30 + 2 + + + IOMC14 + GPIOx pin 14 mode configurate + 28 + 2 + + + IOMC13 + GPIOx pin 13 mode configurate + 26 + 2 + + + IOMC12 + GPIOx pin 12 mode configurate + 24 + 2 + + + IOMC11 + GPIOx pin 11 mode configurate + 22 + 2 + + + IOMC10 + GPIOx pin 10 mode configurate + 20 + 2 + + + IOMC9 + GPIOx pin 9 mode configurate + 18 + 2 + + + IOMC8 + GPIOx pin 8 mode configurate + 16 + 2 + + + IOMC7 + GPIOx pin 7 mode configurate + 14 + 2 + + + IOMC6 + GPIOx pin 6 mode configurate + 12 + 2 + + + IOMC5 + GPIOx pin 5 mode configurate + 10 + 2 + + + IOMC4 + GPIOx pin 4 mode configurate + 8 + 2 + + + IOMC3 + GPIOx pin 3 mode configurate + 6 + 2 + + + IOMC2 + GPIOx pin 2 mode configurate + 4 + 2 + + + IOMC1 + GPIOx pin 1 mode configurate + 2 + 2 + + + IOMC0 + GPIOx pin 0 mode configurate + 0 + 2 + + + + + OMODE + OMODE + GPIO output mode register + 0x4 + 0x20 + read-write + 0x00000000 + + + OM15 + GPIOx pin 15 outpu mode configurate + 15 + 1 + + + OM14 + GPIOx pin 14 outpu mode configurate + 14 + 1 + + + OM13 + GPIOx pin 13 outpu mode configurate + 13 + 1 + + + OM12 + GPIOx pin 12 outpu mode configurate + 12 + 1 + + + OM11 + GPIOx pin 11 outpu mode configurate + 11 + 1 + + + OM10 + GPIOx pin 10 outpu mode configurate + 10 + 1 + + + OM9 + GPIOx pin 9 outpu mode configurate + 9 + 1 + + + OM8 + GPIOx pin 8 outpu mode configurate + 8 + 1 + + + OM7 + GPIOx pin 7 outpu mode configurate + 7 + 1 + + + OM6 + GPIOx pin 6 outpu mode configurate + 6 + 1 + + + OM5 + GPIOx pin 5 outpu mode configurate + 5 + 1 + + + OM4 + GPIOx pin 4 outpu mode configurate + 4 + 1 + + + OM3 + GPIOx pin 3 outpu mode configurate + 3 + 1 + + + OM2 + GPIOx pin 2 outpu mode configurate + 2 + 1 + + + OM1 + GPIOx pin 1 outpu mode configurate + 1 + 1 + + + OM0 + GPIOx pin 0 outpu mode configurate + 0 + 1 + + + + + ODRVR + ODRVR + GPIO drive capability register + 0x8 + 0x20 + read-write + 0x00000000 + + + ODRV15 + GPIOx pin 15 output drive capability + 30 + 2 + + + ODRV14 + GPIOx pin 14 output drive capability + 28 + 2 + + + ODRV13 + GPIOx pin 13 output drive capability + 26 + 2 + + + ODRV12 + GPIOx pin 12 output drive capability + 24 + 2 + + + ODRV11 + GPIOx pin 11 output drive capability + 22 + 2 + + + ODRV10 + GPIOx pin 10 output drive capability + 20 + 2 + + + ODRV9 + GPIOx pin 9 output drive capability + 18 + 2 + + + ODRV8 + GPIOx pin 8 output drive capability + 16 + 2 + + + ODRV7 + GPIOx pin 7 output drive capability + 14 + 2 + + + ODRV6 + GPIOx pin 6 output drive capability + 12 + 2 + + + ODRV5 + GPIOx pin 5 output drive capability + 10 + 2 + + + ODRV4 + GPIOx pin 4 output drive capability + 8 + 2 + + + ODRV3 + GPIOx pin 3 output drive capability + 6 + 2 + + + ODRV2 + GPIOx pin 2 output drive capability + 4 + 2 + + + ODRV1 + GPIOx pin 1 output drive capability + 2 + 2 + + + ODRV0 + GPIOx pin 0 output drive capability + 0 + 2 + + + + + PULL + PULL + GPIO pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PULL15 + GPIOx pin 15 pull configuration + 30 + 2 + + + PULL14 + GPIOx pin 14 pull configuration + 28 + 2 + + + PULL13 + GPIOx pin 13 pull configuration + 26 + 2 + + + PULL12 + GPIOx pin 12 pull configuration + 24 + 2 + + + PULL11 + GPIOx pin 11 pull configuration + 22 + 2 + + + PULL10 + GPIOx pin 10 pull configuration + 20 + 2 + + + PULL9 + GPIOx pin 9 pull configuration + 18 + 2 + + + PULL8 + GPIOx pin 8 pull configuration + 16 + 2 + + + PULL7 + GPIOx pin 7 pull configuration + 14 + 2 + + + PULL6 + GPIOx pin 6 pull configuration + 12 + 2 + + + PULL5 + GPIOx pin 5 pull configuration + 10 + 2 + + + PULL4 + GPIOx pin 4 pull configuration + 8 + 2 + + + PULL3 + GPIOx pin 3 pull configuration + 6 + 2 + + + PULL2 + GPIOx pin 2 pull configuration + 4 + 2 + + + PULL1 + GPIOx pin 1 pull configuration + 2 + 2 + + + PULL0 + GPIOx pin 0 pull configuration + 0 + 2 + + + + + IDT + IDT + GPIO input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + GPIO output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x18 + 0x20 + write-only + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + WPR + WPR + Port write protect + register + 0x1C + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + MUXL + MUXL + GPIO muxing function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + MUXL7 + GPIOx pin 7 muxing + 28 + 4 + + + MUXL6 + GPIOx pin 6 muxing + 24 + 4 + + + MUXL5 + GPIOx pin 5 muxing + 20 + 4 + + + MUXL4 + GPIOx pin 4 muxing + 16 + 4 + + + MUXL3 + GPIOx pin 3 muxing + 12 + 4 + + + MUXL2 + GPIOx pin 2 muxing + 8 + 4 + + + MUXL1 + GPIOx pin 1 muxing + 4 + 4 + + + MUXL0 + GPIOx pin 0 muxing + 0 + 4 + + + + + MUXH + MUXH + GPIO muxing function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + MUXH15 + GPIOx pin 15 muxing + 28 + 4 + + + MUXH14 + GPIOx pin 14 muxing + 24 + 4 + + + MUXH13 + GPIOx pin 13 muxing + 20 + 4 + + + MUXH12 + GPIOx pin 12 muxing + 16 + 4 + + + MUXH11 + GPIOx pin 11 muxing + 12 + 4 + + + MUXH10 + GPIOx pin 10 muxing + 8 + 4 + + + MUXH9 + GPIOx pin 9 muxing + 4 + 4 + + + MUXH8 + GPIOx pin 8 muxing + 0 + 4 + + + + + CLR + CLR + GPIO bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 2 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + TOGR + TOGR + GPIO bit toggle register + 0x2C + 0x20 + write-only + 0x00000000 + + + IOTB0 + Toggle bit 0 + 0 + 1 + + + IOTB1 + Toggle bit 1 + 1 + 1 + + + IOTB2 + Toggle bit 2 + 2 + 1 + + + IOTB3 + Toggle bit 3 + 3 + 1 + + + IOTB4 + Toggle bit 4 + 4 + 1 + + + IOTB5 + Toggle bit 5 + 5 + 1 + + + IOTB6 + Toggle bit 6 + 6 + 1 + + + IOTB7 + Toggle bit 7 + 7 + 1 + + + IOTB8 + Toggle bit 8 + 8 + 1 + + + IOTB9 + Toggle bit 9 + 9 + 1 + + + IOTB10 + Toggle bit 10 + 10 + 1 + + + IOTB11 + Toggle bit 11 + 11 + 1 + + + IOTB12 + Toggle bit 12 + 12 + 1 + + + IOTB13 + Toggle bit 13 + 13 + 1 + + + IOTB14 + Toggle bit 14 + 14 + 1 + + + IOTB15 + Toggle bit 15 + 15 + 1 + + + + + HDRV + HDRV + Huge current driver + 0x3C + 0x20 + read-write + 0x00000000 + + + HDRV0 + Port x driver bit y + 0 + 1 + + + HDRV1 + Port x driver bit y + 1 + 1 + + + HDRV2 + Port x driver bit y + 2 + 1 + + + HDRV3 + Port x driver bit y + 3 + 1 + + + HDRV4 + Port x driver bit y + 4 + 1 + + + HDRV5 + Port x driver bit y + 5 + 1 + + + HDRV6 + Port x driver bit y + 6 + 1 + + + HDRV7 + Port x driver bit y + 7 + 1 + + + HDRV8 + Port x driver bit y + 8 + 1 + + + HDRV9 + Port x driver bit y + 9 + 1 + + + HDRV10 + Port x driver bit y + 10 + 1 + + + HDRV11 + Port x driver bit y + 11 + 1 + + + HDRV12 + Port x driver bit y + 12 + 1 + + + HDRV13 + Port x driver bit y + 13 + 1 + + + HDRV14 + Port x driver bit y + 14 + 1 + + + HDRV15 + Port x driver bit y + 15 + 1 + + + + + + + GPIOB + 0x40020400 + + + GPIOC + 0x40020800 + + + GPIOD + 0x40020C00 + + + GPIOE + 0x40021000 + + + GPIOF + 0x40021400 + + + EXINT + EXINT + EXINT + 0x40013C00 + + 0x0 + 0x400 + registers + + + EXINT0 + EXINT Line0 interrupt + 6 + + + EXINT1 + EXINT Line1 interrupt + 7 + + + EXINT2 + EXINT Line2 interrupt + 8 + + + EXINT3 + EXINT Line3 interrupt + 9 + + + EXINT4 + EXINT Line4 interrupt + 10 + + + EXINT9_5 + EXINT Line[9:5] interrupts + 23 + + + EXINT15_10 + EXINT Line[15:10] interrupts + 40 + + + PVM + PVM interrupt connect to EXINT line16 + 1 + + + ERTCALARM + ERTC Alarm interrupt connect to EXINT line17 + 41 + + + OTGFS1_WKUP + OTGFS1_WKUP interrupt connect to EXINT line18 + 42 + + + TAMPER + Tamper interrupt connect to EXINT line21 + 2 + + + ERTC_WKUP + ERTC Global interrupt connect to EXINT line22 + 3 + + + I2C1_EVT + I2C1_EVT interrupt connect to EXINT line23 + 31 + + + USART1 + ERTC Global interrupt connect to EXINT line25 + 37 + + + USART2 + ERTC Global interrupt connect to EXINT line26 + 38 + + + USART3 + USART3 Global interrupt connect to EXINT line28 + 39 + + + + INTEN + INTEN + Interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + INTEN21 + Interrupt enable or disable on line 21 + 21 + 1 + + + INTEN22 + Interrupt enable or disable on line 22 + 22 + 1 + + + INTEN23 + Interrupt enable or disable on line 23 + 23 + 1 + + + INTEN25 + Interrupt enable or disable on line 25 + 25 + 1 + + + INTEN26 + Interrupt enable or disable on line 26 + 26 + 1 + + + INTEN28 + Interrupt enable or disable on line 28 + 28 + 1 + + + + + EVTEN + EVTEN + Event enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + EVTEN21 + Event enable or disable on line 21 + 21 + 1 + + + EVTEN22 + Event enable or disable on line 22 + 22 + 1 + + + EVTEN23 + Event enable or disable on line 23 + 23 + 1 + + + EVTEN25 + Event enable or disable on line 25 + 25 + 1 + + + EVTEN26 + Event enable or disable on line 26 + 26 + 1 + + + EVTEN28 + Event enable or disable on line 28 + 28 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + RP21 + Rising polarity configuration bit of line 21 + 21 + 1 + + + RP22 + Rising polarity configuration bit of line 22 + 22 + 1 + + + RP23 + Rising polarity configuration bit of line 23 + 23 + 1 + + + RP25 + Rising polarity configuration bit of line 25 + 25 + 1 + + + RP26 + Rising polarity configuration bit of line 26 + 26 + 1 + + + RP28 + Rising polarity configuration bit of line 28 + 28 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + FP21 + Falling polarity event configuration bit of line 21 + 21 + 1 + + + FP22 + Falling polarity event configuration bit of line 22 + 22 + 1 + + + FP23 + Falling polarity event configuration bit of line 23 + 23 + 1 + + + FP25 + Falling polarity event configuration bit of line 25 + 25 + 1 + + + FP26 + Falling polarity event configuration bit of line 26 + 26 + 1 + + + FP28 + Falling polarity event configuration bit of line 28 + 28 + 1 + + + + + SWTRG + SWTRG + Software triggle register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + SWT21 + Software triggle on line 21 + 21 + 1 + + + SWT22 + Software triggle on line 22 + 22 + 1 + + + SWT23 + Software triggle on line 233 + 23 + 1 + + + SWT25 + Software triggle on line 255 + 25 + 1 + + + SWT26 + Software triggle on line 26 + 26 + 1 + + + SWT28 + Software triggle on line 28 + 28 + 1 + + + + + INTSTS + INTSTS + Interrupt status register + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + LINE21 + Line 21 state bit + 21 + 1 + + + LINE22 + Line 22 state bit + 22 + 1 + + + LINE23 + Line 23 state bit + 23 + 1 + + + LINE25 + Line 25 state bit + 25 + 1 + + + LINE26 + Line 26 state bit + 26 + 1 + + + LINE28 + Line 28 state bit + 28 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40026000 + + 0x0 + 0x200 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 13 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 14 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 15 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 16 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 17 + + + + STS + STS + DMA interrupt status register + (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA interrupt flag clear register + (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register(DMA_C1CTRL) + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register (DMA_C2CTRL) + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register (DMA_C3CTRL) + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register (DMA_C4CTRL) + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register (DMA_C5CTRL) + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register(DMA_C6CTRL) + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register(DMA_C7CTRL) + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_MUXSEL + DMA_MUXSEL + DMAMUX Table Selection + 0x100 + 0x20 + 0x00000000 + + + TBL_SEL + Multiplexer Table Select + 0 + 1 + read-write + + + + + MUXC1CTRL + MUXC1CTRL + Channel 1 Configuration Register + 0x104 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC2CTRL + MUXC2CTRL + Channel 2 Configuration Register + 0x108 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC3CTRL + MUXC3CTRL + Channel 3 Configuration Register + 0x10C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC4CTRL + MUXC4CTRL + Channel 4 Configuration Register + 0x110 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC5CTRL + MUXC5CTRL + Channel 5 Configuration Register + 0x114 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC6CTRL + MUXC6CTRL + Channel 6 Configuration Register + 0x118 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC7CTRL + MUXC7CTRL + Channel 7 Configuration Register + 0x11C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXG1CTRL + MUXG1CTRL + Generator 1 Configuration Register + 0x120 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG2CTRL + MUXG2CTRL + Generator 2 Configuration Register + 0x124 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG3CTRL + MUXG3CTRL + Generator 3 Configuration Register + 0x128 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG4CTRL + MUXG4CTRL + Generator 4 Configuration Register + 0x12C + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXSYNCSTS + MUXSYNCSTS + Channel Interrupt Status Register + 0x130 + 0x20 + 0x00000000 + + + SYNCOVF1 + Synchronizaton overrun interrupt flag + 0 + 1 + read-only + + + SYNCOVF2 + Synchronizaton overrun interrupt flag + 1 + 1 + read-only + + + SYNCOVF3 + Synchronizaton overrun interrupt flag + 2 + 1 + read-only + + + SYNCOVF4 + Synchronizaton overrun interrupt flag + 3 + 1 + read-only + + + SYNCOVF5 + Synchronizaton overrun interrupt flag + 4 + 1 + read-only + + + SYNCOVF6 + Synchronizaton overrun interrupt flag + 5 + 1 + read-only + + + SYNCOVF7 + Synchronizaton overrun interrupt flag + 6 + 1 + read-only + + + + + MUXSYNCCLR + MUXSYNCCLR + Channel Interrupt Clear Flag Register + 0x134 + 0x20 + 0x00000000 + + + SYNCOVFC1 + Clear synchronizaton overrun interrupt flag + 0 + 1 + read-write + + + SYNCOVFC2 + Clear synchronizaton overrun interrupt flag + 1 + 1 + read-write + + + SYNCOVFC3 + Clear synchronizaton overrun interrupt flag + 2 + 1 + read-write + + + SYNCOVFC4 + Clear synchronizaton overrun interrupt flag + 3 + 1 + read-write + + + SYNCOVFC5 + Clear synchronizaton overrun interrupt flag + 4 + 1 + read-write + + + SYNCOVFC6 + Clear synchronizaton overrun interrupt flag + 5 + 1 + read-write + + + SYNCOVFC7 + Clear synchronizaton overrun interrupt flag + 6 + 1 + read-write + + + + + MUXGSTS + MUXGSTS + Generator Interrupt Status Register + 0x138 + 0x20 + 0x00000000 + + + TRGOVF1 + Trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVF2 + Trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVF3 + Trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVF4 + Trigger overrun interrupt flag + 3 + 1 + read-write + + + + + MUXGCLR + MUXGCLR + Generator Interrupt Clear Flag Register + 0x13C + 0x20 + 0x00000000 + + + TRGOVFC1 + Clear trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVFC2 + Clear trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVFC3 + Clear trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVFC4 + Clear trigger overrun interrupt flag + 3 + 1 + read-write + + + + + + + DMA2 + 0x40026400 + + + SDIO1 + Secure digital input/output + interface + SDIO + 0x4002C400 + + 0x0 + 0x400 + registers + + + SDIO1 + SDIO1 global interrupt + 49 + + + + PWRCTRL + PWRCTRL + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PS + Power switch + 0 + 2 + + + + + CLKCTRL + CLKCTRL + SD clock control register + (SDIO_CLKCTRL) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock division + 0 + 8 + + + CLKOEN + Clock output enable + 8 + 1 + + + PWRSVEN + Power saving mode enable + 9 + 1 + + + BYPSEN + Clock divider bypass enable + bit + 10 + 1 + + + BUSWS + Bus width selection + 11 + 2 + + + CLKEDS + SDIO_CK edge selection bit + 13 + 1 + + + HFCEN + Hardware flow control enable + 14 + 1 + + + CLKDIV98 + Clock divide factor bit9 and bit8 + 15 + 2 + + + + + ARGU + ARGU + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + ARGU + Command argument + 0 + 32 + + + + + CMDCTRL + CMDCTRL + SDIO command control register + (SDIO_CMDCTRL) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDIDX + CMDIDX + 0 + 6 + + + RSPWT + Wait for response + 6 + 2 + + + INTWT + CCSM wait for interrupt + 8 + 1 + + + PNDWT + CCSM wait for end of transfer + 9 + 1 + + + CCSMEN + Command channel state machine + 10 + 1 + + + IOSUSP + SD I/O suspend command + 11 + 1 + + + + + RSPCMD + RSPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RSPCMD + RSPCMD + 0 + 6 + + + + + RSP1 + RSP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTS1 + CARDSTATUS1 + 0 + 32 + + + + + RSP2 + RSP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS2 + 0 + 32 + + + + + RSP3 + RSP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS3 + 0 + 32 + + + + + RSP4 + RSP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS4 + 0 + 32 + + + + + DTTMR + DTTMR + Bits 31:0 = TIMEOUT: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Data timeout period + 0 + 32 + + + + + DTLEN + DTLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DTLEN + Data length value + 0 + 25 + + + + + DTCTRL + DTCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TFREN + DTEN + 0 + 1 + + + TFRDIR + DTDIR + 1 + 1 + + + TFRMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + BLKSIZE + DBLOCKSIZE + 4 + 4 + + + RDWTSTART + PWSTART + 8 + 1 + + + RDWTSTOP + PWSTOP + 9 + 1 + + + RDWTMODE + RWMOD + 10 + 1 + + + IOEN + SD I/O function enable + 11 + 1 + + + + + DTCNT + DTCNT + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + CNT + Data count value + 0 + 25 + + + + + STS + STS + SDIO status register + (SDIO_STA) + 0x34 + 0x20 + read-only + 0x00000000 + + + CMDFAIL + Command crc fail + 0 + 1 + + + DTFAIL + Data crc fail + 1 + 1 + + + CMDTIMEOUT + Command timeout + 2 + 1 + + + DTTIMEOUT + Data timeout + 3 + 1 + + + TXERRU + Tx under run error + 4 + 1 + + + RXERRO + Rx over run error + 5 + 1 + + + CMDRSPCMPL + Command response complete + 6 + 1 + + + CMDCMPL + Command sent + 7 + 1 + + + DTCMPL + Data sent + 8 + 1 + + + SBITERR + Start bit error + 9 + 1 + + + DTBLKCMPL + Data block sent + 10 + 1 + + + DOCMD + Command transfer in progress + 11 + 1 + + + DOTX + Data transmit in progress + 12 + 1 + + + DORX + Data receive in progress + 13 + 1 + + + TXBUFH + Tx buffer half empty + 14 + 1 + + + RXBUFH + Rx buffer half empty + 15 + 1 + + + TXBUFF + Tx buffer full + 16 + 1 + + + RXBUFF + Rx buffer full + 17 + 1 + + + TXBUFE + Tx buffer empty + 18 + 1 + + + RXBUFE + Rx buffer empty + 19 + 1 + + + TXBUF + Tx data vaild + 20 + 1 + + + RXBUF + Rx data vaild + 21 + 1 + + + IOIF + SD I/O interrupt + 22 + 1 + + + + + INTCLR + INTCLR + SDIO interrupt clear register + (SDIO_INTCLR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CMDFAIL + Command crc fail flag clear + 0 + 1 + + + DTFAIL + Data crc fail flag clear + 1 + 1 + + + CMDTIMEOUT + Command timeout flag clear + 2 + 1 + + + DTTIMEOUT + Data timeout flag clear + 3 + 1 + + + TXERRU + Tx under run error flag clear + 4 + 1 + + + RXERRU + Rx over run error flag clear + 5 + 1 + + + CMDRSPCMPL + Command response complete flag clear + 6 + 1 + + + CMDCMPL + Command sent flag clear + 7 + 1 + + + DTCMPL + Data sent flag clear + 8 + 1 + + + SBITERR + Start bit error flag clear + 9 + 1 + + + DTBLKCMPL + Data block sent clear + 10 + 1 + + + IOIF + SD I/O interrupt flag clear + 22 + 1 + + + + + INTEN + INTEN + SDIO mask register (SDIO_MASK) + 0x3C + 0x20 + read-write + 0x00000000 + + + CMDFAILIEN + Command crc fail interrupt enable + 0 + 1 + + + DTFAILIEN + Data crc fail interrupt enable + 1 + 1 + + + CMDTIMEOUTIEN + Command timeout interrupt enable + 2 + 1 + + + DTTIMEOUTIEN + Data timeout interrupt enable + 3 + 1 + + + TXERRUIEN + Tx under run interrupt enable + 4 + 1 + + + RXERRUIEN + Rx over run interrupt enable + 5 + 1 + + + CMDRSPCMPLIEN + Command response complete interrupt enable + 6 + 1 + + + CMDCMPLIEN + Command sent complete interrupt enable + 7 + 1 + + + DTCMPLIEN + Data sent complete interrupt enable + 8 + 1 + + + SBITERRIEN + Start bit error interrupt enable + 9 + 1 + + + DTBLKCMPLIEN + Data block sent complete interrupt enable + 10 + 1 + + + DOCMDIEN + Command acting interrupt enable + 11 + 1 + + + DOTXIEN + Data transmit acting interrupt enable + 12 + 1 + + + DORXIEN + Data receive acting interrupt enable + 13 + 1 + + + TXBUFHIEN + Tx buffer half empty interrupt enable + 14 + 1 + + + RXBUFHIEN + Rx buffer half empty interrupt enable + 15 + 1 + + + TXBUFFIEN + Tx buffer full interrupt enable + 16 + 1 + + + RXBUFFIEN + Rx buffer full interrupt enable + 17 + 1 + + + TXBUFEIEN + Tx buffer empty interrupt enable + 18 + 1 + + + RXBUFEIEN + Rx buffer empty interrupt enable + 19 + 1 + + + TXBUFIEN + Tx buffer data vaild interrupt enable + 20 + 1 + + + RXBUFIEN + Rx buffer data vaild interrupt enable + 21 + 1 + + + IOIFIEN + SD I/O interrupt enable + 22 + 1 + + + + + BUFCNT + BUFCNT + Bits 23:0 = BUFCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + FIF0COUNT + 0 + 24 + + + + + BUF + BUF + bits 31:0 = Buffer Data: Receive and transmit + buffer data + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Buffer data + 0 + 32 + + + + + + + SDIO2 + 0x50061000 + + SDIO2 + SDIO2 global interrupt + 102 + + + + ERTC + Real-time clock + ERTC + 0x40002800 + + 0x0 + 0x400 + registers + + + + TIME + TIME + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + AMPM + AM/PM notation + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + DATE + DATE + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens + 20 + 4 + + + YU + Year units + 16 + 4 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + CTRL + CTRL + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + CALOEN + Calibration output enable + 23 + 1 + + + OUTSEL + Output source selection + 21 + 2 + + + OUTP + Output polarity + 20 + 1 + + + CALOSEL + Calibration output selection + 19 + 1 + + + BPR + Battery power domain data register + 18 + 1 + + + DEC1H + Decrease 1 hour + 17 + 1 + + + ADD1H + Add 1 hour + 16 + 1 + + + TSIEN + Timestamp interrupt enable + 15 + 1 + + + WATIEN + Wakeup timer interrupt enable + 14 + 1 + + + ALBIEN + Alarm B interrupt enable + 13 + 1 + + + ALAIEN + Alarm A interrupt enable + 12 + 1 + + + TSEN + Timestamp enable + 11 + 1 + + + WATEN + Wakeup timer enable + 10 + 1 + + + ALBEN + Alarm B enable + 9 + 1 + + + ALAEN + Alarm A enable + 8 + 1 + + + CCALEN + Coarse calibration enable + 7 + 1 + + + HM + Hour mode + 6 + 1 + + + DREN + Date/time register direct read enable + 5 + 1 + + + RCDEN + Reference clock detection enable + 4 + 1 + + + TSEDG + Timestamp trigger edge + 3 + 1 + + + WATCLK + Wakeup timer clock selection + 0 + 3 + + + + + STS + STS + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALAWF + Alarm A register allows write flag + 0 + 1 + read-only + + + ALBWF + Alarm B register allows write flag + 1 + 1 + read-only + + + WATWF + Wakeup timer register allows write flag + 2 + 1 + read-only + + + TADJF + Time adjustment flag + 3 + 1 + read-write + + + INITF + Calendar initialization flag + 4 + 1 + read-only + + + UPDF + Calendar update flag + 5 + 1 + read-write + + + IMF + Enter initialization mode flag + 6 + 1 + read-only + + + IMEN + Initialization mode enable + 7 + 1 + read-write + + + ALAF + Alarm A flag + 8 + 1 + read-write + + + ALBF + Alarm B flag + 9 + 1 + read-write + + + WATF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Timestamp flag + 11 + 1 + read-write + + + TSOF + Timestamp overflow flag + 12 + 1 + read-write + + + TP1F + Tamper detection 1 flag + 13 + 1 + read-write + + + TP2F + Tamper detection 2 flag + 14 + 1 + read-write + + + CALUPDF + Calibration value update completed flag + 16 + 1 + read-only + + + + + DIV + DIV + Diveder register + 0x10 + 0x20 + read-write + 0x007F00FF + + + DIVA + Diveder A + 16 + 7 + + + DIVB + Diveder B + 0 + 15 + + + + + WAT + WAT + Wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + VAL + Wakeup timer reload value + 0 + 16 + + + + + CCAL + CCAL + Calibration register + 0x18 + 0x20 + read-write + 0x00000000 + + + CALDIR + Calibration direction + 7 + 1 + + + CALVAL + Calibration value + 0 + 5 + + + + + ALA + ALA + Alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + ALB + ALB + Alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + WP + WP + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 8 + + + + + SBS + SBS + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + TADJ + TADJ + time adjust register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add 1 second + 31 + 1 + + + DECSBS + Decrease sub-second value + 0 + 15 + + + + + TSTM + TSTM + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + AMPM + AMPM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + TSDT + TSDT + timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + TSSBS + TSSBS + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + SCAL + SCAL + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + ADD + Add ERTC clock + 15 + 1 + + + CAL8 + 8-second calibration period + 14 + 1 + + + CAL16 + 16 second calibration period + 13 + 1 + + + DEC + Decrease ERTC clock + 0 + 9 + + + + + TAMP + TAMP + tamper and alternate function configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + OUTTYPE + Output type + 18 + 1 + + + TSPIN + Time stamp detection pin selection + 17 + 1 + + + TP1PIN + Tamper detection pin selection + 16 + 1 + + + TPPU + Tamper detection pull-up + 15 + 1 + + + TPPR + Tamper detection pre-charge time + 13 + 2 + + + TPFLT + Tamper detection filter time + 11 + 2 + + + TPFREQ + Tamper detection frequency + 8 + 3 + + + TPTSEN + Tamper detection timestamp enable + 7 + 1 + + + TP2EDG + Tamper detection 2 valid edge + 4 + 1 + + + TP2EN + Tamper detection 2 enable + 3 + 1 + + + TPIEN + Tamper detection interrupt enable + 2 + 1 + + + TP1EDG + Tamper detection 1 valid edge + 1 + 1 + + + TP1EN + Tamper detection 1 enable + 0 + 1 + + + + + ALASBS + ALASBS + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + ALBSBS + ALBSBS + alarm B sub second register + 0x48 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + BPR1DT + BPR1DT + Battery powered domain register + 0x50 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR2DT + BPR2DT + Battery powered domain register + 0x54 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR3DT + BPR3DT + Battery powered domain register + 0x58 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR4DT + BPR4DT + Battery powered domain register + 0x5C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR5DT + BPR5DT + Battery powered domain register + 0x60 + 0x20 + read-write + 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Trigger event triggered by software + 6 + 1 + + + C4SWTR + Channel 4 event triggered by software + 4 + 1 + + + C3SWTR + Channel 3 event triggered by software + 3 + 1 + + + C2SWTR + Channel 2 event triggered by software + 2 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C2OSEN + Channel 2 output switch enable + 15 + 1 + + + C2OCTRL + Channel 2 output control + 12 + 3 + + + C2OBEN + Channel 2 output buffer enable + 11 + 1 + + + C2OIEN + Channel 2 output immediately enable + 10 + 1 + + + C2C + Channel 2 configure + 8 + 2 + + + C1OSEN + Channel 1 output switch enable + 7 + 1 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C2DF + Channel 2 digital filter + 12 + 4 + + + C2IDIV + Channel 2 input divider + 10 + 2 + + + C2C + Channel 2 configure + 8 + 2 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM2_OUTPUT + CM2_OUTPUT + Channel output mode register 2 + 0x1C + 0x20 + read-write + 0x00000000 + + + C4OSEN + Channel 4 output switch enable + 15 + 1 + + + C4OCTRL + Channel 4 output control + 12 + 3 + + + C4OBEN + Channel 4 output buffer enable + 11 + 1 + + + C4OIEN + Channel 4 output immediately enable + 10 + 1 + + + C4C + Channel 4 configure + 8 + 2 + + + C3OSEN + Channel 3 output switch enable + 7 + 1 + + + C3OCTRL + Channel 3 output control + 4 + 3 + + + C3OBEN + Channel 3 output buffer enable + 3 + 1 + + + C3OIEN + Channel 3 output immediately enable + 2 + 1 + + + C3C + Channel 3 configure + 0 + 2 + + + + + CM2_INPUT + CM2_INPUT + Channel input mode register 2 + CM2_OUTPUT + 0x1C + 0x20 + read-write + 0x00000000 + + + C4DF + Channel 4 digital filter + 12 + 4 + + + C4IDIV + Channel 4 input divider + 10 + 2 + + + C4C + Channel 4 configure + 8 + 2 + + + C3DF + Channel 3 digital filter + 4 + 4 + + + C3IDIV + Channel 3 input divider + 2 + 2 + + + C3C + Channel 3 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C4P + Channel 4 Polarity + 13 + 1 + + + C4EN + Channel 4 enable + 12 + 1 + + + C3P + Channel 3 Polarity + 9 + 1 + + + C3EN + Channel 3 enable + 8 + 1 + + + C2P + Channel 2 Polarity + 5 + 1 + + + C2EN + Channel 2 enable + 4 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + C2DT + C2DT + Channel 2 data register + 0x38 + 0x20 + read-write + 0x00000000 + + + C2DT + Channel 2 data register + 0 + 16 + + + + + C3DT + C3DT + Channel 3 data register + 0x3C + 0x20 + read-write + 0x00000000 + + + C3DT + Channel 3 data register + 0 + 16 + + + + + C4DT + C4DT + Channel 4 data register + 0x40 + 0x20 + read-write + 0x00000000 + + + C4DT + Channel 4 data register + 0 + 16 + + + + + DMACTRL + DMACTRL + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DTB + DMA transfer bytes + 8 + 5 + + + ADDR + DMA transfer address offset + 0 + 5 + + + + + DMADT + DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + + + TMR4 + 0x40000800 + + TMR4 + TMR4 global interrupt + 30 + + + + TMR9 + General purpose timer + TIMER + 0x40014000 + + 0x0 + 0x400 + registers + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + TWCMSEL + Two-way count mode selection + 5 + 2 + + + OWCDIR + One-way count direction + 4 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + C2CIOS + Channel 2 complementary idle output state + 11 + 1 + + + C2IOS + Channel 2 idle output state + 10 + 1 + + + C1CIOS + Channel 1 complementary idle output state + 9 + 1 + + + C1IOS + Channel 1 idle output state + 8 + 1 + + + PTOS + Primary TMR output selection + 4 + 3 + + + DRS + DMA request source + 3 + 1 + + + CCFS + Channel control bit flash select + 2 + 1 + + + CBCTRL + Channel buffer control + 0 + 1 + + + + + STCTRL + STCTRL + Subordinate TMR control register + 0x8 + 0x20 + read-write + 0x0000 + + + STS + Subordinate TMR synchronization + 7 + 1 + + + STIS + Subordinate TMR input selection + 4 + 3 + + + SMSEL + Subordinate TMR mode selection + 0 + 3 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDEN + Trigger DMA request enable + 14 + 1 + + + HALLDE + HALL DMA request enable + 13 + 1 + + + C2DEN + Channel 2 DMA request + enable + 10 + 1 + + + C1DEN + Channel 1 DMA request + enable + 9 + 1 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + BRKIE + Brake interrupt enable + 7 + 1 + + + TIEN + Trigger interrupt enable + 6 + 1 + + + HALLIEN + HALL interrupt enable + 5 + 1 + + + C2IEN + Channel 2 interrupt + enable + 2 + 1 + + + C1IEN + Channel 1 interrupt + enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C2RF + Channel 2 recapture flag + 10 + 1 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + BRKIF + Brake interrupt flag + 7 + 1 + + + TRGIF + Trigger interrupt flag + 6 + 1 + + + HALLIF + HALL interrupt flag + 5 + 1 + + + C2IF + Channel 2 interrupt flag + 2 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + BRKSWTR + Brake event triggered by software + 7 + 1 + + + TRGSWTR + Trigger event triggered by software + 6 + 1 + + + HALLSWTR + HALL event triggered by software + 5 + 1 + + + C2SWTR + Channel 2 event triggered by software + 2 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C2OCTRL + Channel 2 output control + 12 + 3 + + + C2OBEN + Channel 2 output buffer enable + 11 + 1 + + + C2OIEN + Channel 2 output immediately enable + 10 + 1 + + + C2C + Channel 2 configure + 8 + 2 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C2DF + Channel 2 digital filter + 12 + 4 + + + C2IDIV + Channel 2 input divider + 10 + 2 + + + C2C + Channel 2 configure + 8 + 2 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C2CP + Channel 2 complementary polarity + 7 + 1 + + + C2CEN + Channel 2 complementary enable + 6 + 1 + + + C2P + Channel 2 Polarity + 5 + 1 + + + C2EN + Channel 2 enable + 4 + 1 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1CEN + Channel 1 complementary enable + 2 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + RPR + RPR + Repetition of period value + 0x30 + 0x20 + read-write + 0x0000 + + + RPR + Repetition of period value + 0 + 8 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + C2DT + C2DT + Channel 2 data register + 0x38 + 0x20 + read-write + 0x00000000 + + + C2DT + Channel 2 data register + 0 + 16 + + + + + BRK + BRK + Brake register + 0x44 + 0x20 + read-write + 0x0000 + + + BKF + brake input filter + 16 + 4 + + + OEN + Output enable + 15 + 1 + + + AOEN + Automatic output enable + 14 + 1 + + + BRKV + Brake input validity + 13 + 1 + + + BRKEN + Brake enable + 12 + 1 + + + FCSOEN + Frozen channel status when + holistic output enable + 11 + 1 + + + FCSODIS + Frozen channel status when + holistic output disable + 10 + 1 + + + WPC + Write protected configuration + 8 + 2 + + + DTC + Dead-time configuration + 0 + 8 + + + + + DMACTRL + DMACTRL + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DTB + DMA transfer bytes + 8 + 5 + + + ADDR + DMA transfer address offset + 0 + 5 + + + + + DMADT + DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + + + TMR12 + 0x40001800 + + + TMR10 + General purpose timer + TIMER + 0x40014400 + + 0x0 + 0x400 + registers + + + TMR1_OVF_TMR10 + TMR1 overflow interrupt and TMR10 global + interrupt + 25 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + TWCMSEL + Two-way count mode selection + 5 + 2 + + + OWCDIR + One-way count direction + 4 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + C1CIOS + Channel 1 complementary idle output state + 9 + 1 + + + C1IOS + Channel 1 idle output state + 8 + 1 + + + DRS + DMA request source + 3 + 1 + + + CCFS + Channel control bit flash select + 2 + 1 + + + CBCTRL + Channel buffer control + 0 + 1 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + C1DEN + Channel 1 DMA request + enable + 9 + 1 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + BRKIE + Brake interrupt enable + 7 + 1 + + + HALLIEN + HALL interrupt enable + 5 + 1 + + + C1IEN + Channel 1 interrupt enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + BRKIF + Brake interrupt flag + 7 + 1 + + + HALLIF + HALL interrupt flag + 5 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + BRKSWTR + Brake event triggered by software + 7 + 1 + + + HALLSWTR + HALL event triggered by software + 5 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1CEN + Channel 1 complementary enable + 2 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + RPR + RPR + Repetition of period value + 0x30 + 0x20 + read-write + 0x0000 + + + RPR + Repetition of period value + 0 + 8 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + BRK + BRK + Brake register + 0x44 + 0x20 + read-write + 0x0000 + + + BKF + brake input filter + 16 + 4 + + + OEN + Output enable + 15 + 1 + + + AOEN + Automatic output enable + 14 + 1 + + + BRKV + Brake input validity + 13 + 1 + + + BRKEN + Brake enable + 12 + 1 + + + FCSOEN + Frozen channel status when + holistic output enable + 11 + 1 + + + FCSODIS + Frozen channel status when + holistic output disable + 10 + 1 + + + WPC + Write protected configuration + 8 + 2 + + + DTC + Dead-time configuration + 0 + 8 + + + + + DMACTRL + DMACTRL + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DTB + DMA transfer bytes + 8 + 5 + + + ADDR + DMA transfer address offset + 0 + 5 + + + + + DMADT + DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + + + TMR11 + 0x40014800 + + TMR1_TRG_HALL_TMR11 + TMR1 trigger and HALL interrupts and + TMR11 global interrupt + 26 + + + + TMR13 + 0x40001C00 + + + TMR14 + 0x40002000 + + + RMP + RMP + TMR14 channel 1 input remap + 0x50 + 0x20 + read-write + 0x00000000 + + + TMR14_CH1_IRMP + TMR14 channel 1 input remap + 6 + 2 + + + + + + + TMR6 + Basic timer + TIMER + 0x40001000 + + 0x0 + 0x400 + registers + + + TMR6 + TMR6 global interrupt + 54 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + PTOS + Primary TMR output selection + 4 + 3 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + + + TMR7 + 0x40001400 + + TMR7 + TMR7 global interrupt + 55 + + + + ACC + HICK Auto Clock Calibration + ACC + 0x40017400 + + 0x0 + 0x400 + registers + + + + STS + STS + status register + 0x0 + 0x20 + 0x0000 + + + RSLOST + Reference Signal Lost + read-write + 1 + 1 + + + CALRDY + Internal high-speed clock calibration ready + read-write + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x04 + 0x20 + 0x0100 + + + STEP + STEP + read-write + 8 + 4 + + + CALRDYIEN + CALRDY interrupt enable + read-write + 5 + 1 + + + EIEN + RSLOST error interrupt enable + read-write + 4 + 1 + + + ENTRIM + Enable trim + read-write + 1 + 1 + + + CALON + Calibration on + read-write + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x08 + 0x20 + 0x2080 + + + HICKTWK + Internal high-speed auto clock trimming + read-only + 8 + 6 + + + HICKCAL + Internal high-speed auto clock calibration + read-only + 0 + 8 + + + + + C1 + C1 + compare value 1 + 0x0C + 0x20 + 0x1F2C + + + C1 + Compare 1 + read-write + 0 + 16 + + + + + C2 + C2 + compare value 2 + 0x10 + 0x20 + 0x1F40 + + + C2 + Compare 2 + read-write + 0 + 16 + + + + + C3 + C3 + compare value 3 + 0x14 + 0x20 + 0x1F54 + + + C3 + Compare 3 + read-write + 0 + 16 + + + + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EVT + I2C1 event interrupt + 31 + + + I2C1_ERR + I2C1 error interrupt + 32 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + 0x00000000 + + + I2CEN + I2C peripheral enable + 0 + 1 + read-write + + + TDIEN + Transmit data interrupt enable + 1 + 1 + read-write + + + RDIEN + Receive data interrupt enable + 2 + 1 + read-write + + + ADDRIEN + Address match interrupt enable + 3 + 1 + read-write + + + ACKFAILIEN + Acknowledge fail interrupt enable + 4 + 1 + read-write + + + STOPIEN + Stop generation complete interrupt enable + 5 + 1 + read-write + + + TDCIEN + Transfer data complete interrupt enable + 6 + 1 + read-write + + + ERRIEN + Error interrupts enable + 7 + 1 + read-write + + + DFLT + Digital filter value + 8 + 4 + read-write + + + DMATEN + DMA Transmit data request enable + 14 + 1 + read-write + + + DMAREN + DMA receive data request enable + 15 + 1 + read-write + + + SCTRL + Slave receiving data control + 16 + 1 + read-write + + + STRETCH + Clock stretching mode + 17 + 1 + read-write + + + GCAEN + General call address enable + 19 + 1 + read-write + + + HADDREN + SMBus host address enable + 20 + 1 + read-write + + + DEVADDREN + SMBus device default address enable + 21 + 1 + read-write + + + SMBALERT + SMBus alert enable / pin set + 22 + 1 + read-write + + + PECEN + PEC calculation enable + 23 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECTEN + Request PEC transmission enable + 26 + 1 + + + ASTOPEN + Automatically send stop condition enable + 25 + 1 + + + RLDEN + Send data reload mode enable + 24 + 1 + + + CNT + Transmit data counter + 16 + 8 + + + NACKEN + Not acknowledge enable + 15 + 1 + + + GENSTOP + Generate stop condition + 14 + 1 + + + GENSTART + Generate start condition + 13 + 1 + + + READH10 + 10-bit address header read enable + 12 + 1 + + + ADDR10 + Host send 10-bit address mode enable + 11 + 1 + + + DIR + Master data transmission direction + 10 + 1 + + + SADDR + Slave address + 0 + 10 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + ADDR1 + Interface address + 0 + 10 + + + ADDR1MODE + Own Address mode + 10 + 1 + + + ADDR1EN + Own address 1 enable + 15 + 1 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2MASK + Own address 2-bit mask + 8 + 3 + + + ADDR2EN + Own address 2 enable + 15 + 1 + + + + + CLKCTRL + CLKCTRL + Clock contorl register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low level + 0 + 8 + + + SCLH + SCL high level + 8 + 8 + + + SDAD + SDA output delay + 16 + 4 + + + SCLD + SCL output delay + 20 + 4 + + + DIVH + High 4 bits of clock divider value + 24 + 4 + + + DIVL + Low 4 bits of clock divider value + 28 + 4 + + + + + TIMEOUT + TIMEOUT + Timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + TOTIME + Clock timeout detection time + 0 + 12 + + + TOMOED + Clock timeout detection mode + 12 + 1 + + + TOEN + Detect clock low/high timeout enable + 15 + 1 + + + EXTTIME + Cumulative clock low extend timeout value + 16 + 12 + + + EXTEN + Cumulative clock low extend timeout enable + 31 + 1 + + + + + STS + STS + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDR + Slave address matching value + 17 + 7 + read-only + + + SDIR + Slave data transmit direction + 16 + 1 + read-only + + + BUSYF + Bus busy + 15 + 1 + read-only + + + ALERTF + SMBus alert flag + 13 + 1 + read-only + + + TMOUT + SMBus timeout flag + 12 + 1 + read-only + + + PECERR + PEC receive error flag + 11 + 1 + read-only + + + OUF + Overflow or underflow flag + 10 + 1 + read-only + + + ARLOST + Arbitration lost flag + 9 + 1 + read-only + + + BUSERR + Bus error flag + 8 + 1 + read-only + + + TCRLD + Transmission is complete, waiting to load data + 7 + 1 + read-only + + + TDC + Transmit data complete flag + 6 + 1 + read-only + + + STOPF + Stop condition generation complete flag + 5 + 1 + read-only + + + ACKFAIL + Acknowledge failure flag + 4 + 1 + read-only + + + ADDRF + 0~7 bit address match flag + 3 + 1 + read-only + + + RDBF + Receive data buffer full flag + 2 + 1 + read-only + + + TDIS + Send interrupt status + 1 + 1 + read-write + + + TDBE + Transmit data buffer empty flag + 0 + 1 + read-write + + + + + CLR + CLR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTC + Clear SMBus alert flag + 13 + 1 + + + TMOUTC + Clear SMBus timeout flag + 12 + 1 + + + PECERRC + Clear PEC receive error flag + 11 + 1 + + + OUFC + Clear overload / underload flag + 10 + 1 + + + ARLOSTC + Clear arbitration lost flag + 9 + 1 + + + BUSERRC + Clear bus error flag + 8 + 1 + + + STOPC + Clear stop condition generation complete flag + 5 + 1 + + + ACKFAILC + Clear acknowledge failure flag + 4 + 1 + + + ADDRC + Clear 0~7 bit address match flag + 3 + 1 + + + + + PEC + PEC + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PECVAL + PEC value + 0 + 8 + + + + + RXDT + RXDT + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + DT + Receive data register + 0 + 8 + + + + + TXDT + TXDT + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + DT + Transmit data register + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 33 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + I2C3 + 0x40005C00 + + I2C3_EVT + I2C3 event interrupt + 72 + + + I2C3_ERR + I2C3 error interrupt + 73 + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3EN + Master clock frequency3 division enable + 9 + 1 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + TIEN + TI mode enable + 4 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + CSPAS + CS pulse abnormal setting fiag + 8 + 1 + read-write + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLKP + I2SCLKP + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40011000 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + DBN1 + high bit for Data bit num + 28 + 1 + + + TSDT + transmit start delay time + 21 + 5 + + + TCDT + transmit complete delay time + 16 + 5 + + + UEN + USART enable + 13 + 1 + + + DBN0 + low bit for Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + ID7_4 + bit 7-4 for usart identification + 28 + 4 + + + TRPSWAP + Transmit receive pin swap + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + IDBN + Identification bit num + 4 + 1 + + + ID3_0 + bit 3-0 for usart identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + DEP + DE polarity selection + 15 + 1 + + + RS485EN + RS485 enable + 14 + 1 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + USART6 + 0x40011400 + + USART6 + USART6 global interrupt + 71 + + + + ADC1 + Analog to digital converter + ADC + 0x40012000 + + 0x0 + 0x100 + registers + + + ADC + ADC1 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + RDY + ADC ready to conversion flag + 6 + 1 + read-only + + + OCCO + Ordinary channel conversion overflow flag + 5 + 1 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + OCCE + Ordinary channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCCOIEN + Ordinary channel conversion overflow interrupt enable + 26 + 1 + + + CRSEL + Conversion resolution select + 24 + 2 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + OCCEIEN + Ordinary channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCSWTRG + Ordinary channel software conversion trigger + 30 + 1 + + + OCETE + Ordinary channel external trigger edge select + 28 + 2 + + + OCTESEL + trigger event select for ordinary channels conversion + 24 + 4 + + + PCSWTRG + Preempted channel software conversion trigger + 22 + 1 + + + PCETE + Preempted channel external trigger edge select + 20 + 2 + + + PCTESEL + trigger event select for preempted channels conversion + 16 + 4 + + + DTALIGN + Data alignment + 11 + 1 + + + EOCSFEN + Each ordinary channel conversion set OCCE flag enable + 10 + 1 + + + OCDRCEN + Ordinary channel DMA request continuation enable for independent mode + 9 + 1 + + + OCDMAEN + Ordinary channel DMA transfer enable for independent mode + 8 + 1 + + + ADABRT + ADC conversion abort + 4 + 1 + + + ADCALINIT + Initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT18 + Selection sample time of channel ADC_IN18 + 24 + 3 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + SPT3 + SPT3 + sample time register 3 + 0x50 + 0x20 + read-write + 0x00000000 + + + CSPT27 + Selection sample time of channel ADC_IN27 + 21 + 3 + + + CSPT26 + Selection sample time of channel ADC_IN26 + 18 + 3 + + + CSPT25 + Selection sample time of channel ADC_IN25 + 15 + 3 + + + CSPT24 + Selection sample time of channel ADC_IN24 + 12 + 3 + + + CSPT23 + Selection sample time of channel ADC_IN23 + 9 + 3 + + + CSPT22 + Selection sample time of channel ADC_IN22 + 6 + 3 + + + CSPT21 + Selection sample time of channel ADC_IN21 + 3 + 3 + + + CSPT20 + Selection sample time of channel ADC_IN20 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 16 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 16 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 5 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + OSQ4 + OSQ4 + Ordinary sequence register 4 + 0x54 + 0x20 + read-write + 0x00000000 + + + OSN22 + Number of 22th conversion in ordinary sequence + 25 + 5 + + + OSN21 + Number of 21th conversion in ordinary sequence + 20 + 5 + + + OSN20 + Number of 20th conversion in ordinary sequence + 15 + 5 + + + OSN19 + number of 19rd conversion in ordinary sequence + 10 + 5 + + + OSN18 + Number of 18nd conversion in ordinary sequence + 5 + 5 + + + OSN17 + Number of 17st conversion in ordinary sequence + 0 + 5 + + + + + OSQ5 + OSQ5 + Ordinary sequence register 5 + 0x58 + 0x20 + read-write + 0x00000000 + + + OSN28 + Number of 28th conversion in ordinary sequence + 25 + 5 + + + OSN27 + Number of 27th conversion in ordinary sequence + 20 + 5 + + + OSN26 + Number of 26th conversion in ordinary sequence + 15 + 5 + + + OSN25 + number of 25rd conversion in ordinary sequence + 10 + 5 + + + OSN24 + Number of 24nd conversion in ordinary sequence + 5 + 5 + + + OSN23 + Number of 23st conversion in ordinary sequence + 0 + 5 + + + + + OSQ6 + OSQ6 + Ordinary sequence register 6 + 0x5C + 0x20 + read-write + 0x00000000 + + + OSN32 + Number of 32th conversion in ordinary sequence + 15 + 5 + + + OSN31 + number of 31rd conversion in ordinary sequence + 10 + 5 + + + OSN30 + Number of 30nd conversion in ordinary sequence + 5 + 5 + + + OSN29 + Number of 29st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + OVSP + OVSP + oversampling register + 0x80 + 0x20 + read-write + 0x00000000 + + + OOSRSEL + Ordinary oversampling recovery mode select + 10 + 1 + + + OOSTREN + Ordinary oversampling trigger mode enable + 9 + 1 + + + OSSSEL + Oversampling shift select + 5 + 4 + + + OSRSEL + Oversampling ratio select + 2 + 3 + + + POSEN + Preempted oversampling enable + 1 + 1 + + + OOSEN + Ordinary oversampling enable + 0 + 1 + + + + + CALVAL + CALVAL + Calibration value register + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALVAL + A/D Calibration value + 0 + 7 + + + + + + + ADCCOM + ADC common area + ADC + 0x40012300 + + 0x0 + 0x100 + registers + + + + CSTS + CSTS + Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + RDY1 + ADC ready to conversion flag of ADC1 + 6 + 1 + + + OCCO1 + Ordinary channel conversion overflow flag of ADC1 + 5 + 1 + + + OCCS1 + Ordinary channel conversion start flag of ADC1 + 4 + 1 + + + PCCS1 + Preempted channel conversion start flag of ADC1 + 3 + 1 + + + PCCE1 + Preempted channels conversion end flag of ADC1 + 2 + 1 + + + OCCE1 + Ordinary channels conversion end flag of ADC1 + 1 + 1 + + + VMOR1 + Voltage monitoring out of range flag of ADC1 + 0 + 1 + + + + + CCTRL + CCTRL + Common control register + 0x4 + 0x20 + read-write + 0x00000000 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + 1 + + + VBATEN + VBAT enable + 22 + 1 + + + ADCDIV + ADC division + 16 + 4 + + + + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1_TX + CAN1 TX interrupt + 19 + + + CAN1_RX0 + CAN1 RX0 interrupt + 20 + + + CAN_RX1 + CAN1 RX1 interrupt + 21 + + + CAN_SE + CAN1 SE interrupt + 22 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RF0R + Receive FIFO 0 release + 5 + 1 + read-write + + + RF0OF + Receive FIFO 0 overflow flag + 4 + 1 + read-write + + + RF0FF + Receive FIFO 0 full flag + 3 + 1 + read-write + + + RF0MN + Receive FIFO 0 message num + 0 + 2 + read-only + + + + + RF1 + RF1 + Receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RF1R + Receive FIFO 1 release + 5 + 1 + read-write + + + RF1OF + Receive FIFO 1 overflow flag + 4 + 1 + read-write + + + RF1FF + Receive FIFO 1 full flag + 3 + 1 + read-write + + + RF1MN + Receive FIFO 1 message num + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + EDZIEN + Enter doze mode interrupt enable + 17 + 1 + + + QDZIEN + Quit doze mode interrupt enable + 16 + 1 + + + EOIEN + Error occur interrupt enable + 15 + 1 + + + ETRIEN + Error type record interrupt enable + 11 + 1 + + + BOIEN + Bus-off interrupt enable + 10 + 1 + + + EPIEN + Error passive interrupt enable + 9 + 1 + + + EAIEN + Error active interrupt enable + 8 + 1 + + + RF1OIEN + Receive FIFO 1 overflow interrupt enable + 6 + 1 + + + RF1FIEN + Receive FIFO 1 full interrupt enable + 5 + 1 + + + RF1MIEN + FIFO 1 receive message interrupt enable + 4 + 1 + + + RF0OIEN + Receive FIFO 0 overflow interrupt enable + 3 + 1 + + + RF0FIEN + Receive FIFO 0 full interrupt enable + 2 + 1 + + + RF0MIEN + FIFO 0 receive message interrupt enable + 1 + 1 + + + TCIEN + Transmission complete interrupt enable + 0 + 1 + + + + + ESTS + ESTS + Error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Transmit error counter + 16 + 8 + read-only + + + ETR + Error type record + 4 + 3 + read-write + + + BOF + Bus-off flag + 2 + 1 + read-only + + + EPF + Error passive flag + 1 + 1 + read-only + + + EAF + Error active flag + 0 + 1 + read-only + + + + + BTMG + BTMG + Bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOEN + Listen-Only mode + 31 + 1 + + + LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB2 + F1FB2 + Filter bank 1 filtrate bit register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB1 + F2FB1 + Filter bank 2 filtrate bit register 1 + 0x250 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB2 + F2FB2 + Filter bank 2 filtrate bit register 2 + 0x254 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data 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+ 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F11FB1 + F11FB1 + Filter bank 11 filtrate bit register 1 + 0x298 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F11FB2 + F11FB2 + Filter bank 11 filtrate bit register 2 + 0x29C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F12FB1 + F12FB1 + Filter bank 12 filtrate bit register 1 + 0x2A0 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F12FB2 + F12FB2 + Filter bank 12 filtrate bit register 2 + 0x2A4 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB1 + F13FB1 + Filter bank 13 filtrate bit register 1 + 0x2A8 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB2 + F13FB2 + Filter bank 13 filtrate bit register 2 + 0x2AC + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + + + CAN2 + 0x40006800 + + CAN2_TX + CAN2 TX interrupt + 63 + + + CAN2_RX0 + CAN2 RX0 interrupt + 64 + + + CAN2_RX1 + CAN2 RX1 interrupt + 65 + + + CAN2_SE + CAN2 SE interrupt + 66 + + + + DAC + Digital to analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Control register (DAC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + D1EN + DAC1 enable + 0 + 1 + + + D1OBDIS + DAC1 output buffer disable + 1 + 1 + + + D1TRGEN + DAC1 trigger enable + 2 + 1 + + + D1TRGSEL + DAC1 trigger selection + 3 + 3 + + + D1NM + DAC1 noise/triangle wave generation enable + 6 + 2 + + + D1NBSEL + DAC1 mask/amplitude selector + 8 + 4 + + + D1DMAEN + DAC1 DMA enable + 12 + 1 + + + D1DMAUDRIEN + DAC1 DMA underrun interrupt enable + 13 + 1 + + + D2EN + DAC2 enable + 16 + 1 + + + D2OBDIS + DAC2 output buffer disable + 17 + 1 + + + D2TRGEN + DAC2 trigger enable + 18 + 1 + + + D2TRGSEL + DAC2 trigger selection + 19 + 3 + + + D2NM + DAC2 noise/triangle wave generation enable + 22 + 2 + + + D2NBSEL + DAC2 mask/amplitude selector + 24 + 4 + + + D2DMAEN + DAC2 DMA enable + 28 + 1 + + + D2DMAUDRIEN + DAC2 DMA underrun interrupt enable + 29 + 1 + + + + + SWTRG + SWTRG + DAC software trigger register(DAC_SWTRIGR) + 0x4 + 0x20 + write-only + 0x00000000 + + + D1SWTRG + DAC1 software trigger + 0 + 1 + + + D2SWTRG + DAC2 software trigger + 1 + 1 + + + + + D1DTH12R + D1DTH12R + DAC1 12-bit right-aligned data holding register(DAC_D1DTH12R) + 0x8 + 0x20 + read-write + 0x00000000 + + + D1DT12R + DAC1 12-bit right-aligned data + 0 + 12 + + + + + D1DTH12L + D1DTH12L + DAC1 12-bit left aligned data holding register (DAC_D1DTH12L) + 0xC + 0x20 + read-write + 0x00000000 + + + D1DT12L + DAC1 12-bit left-aligned data + 4 + 12 + + + + + D1DTH8R + D1DTH8R + DAC1 8-bit right aligned data holding register (DAC_D1DTH8R) + 0x10 + 0x20 + read-write + 0x00000000 + + + D1DT8R + DAC1 8-bit right-aligned data + 0 + 8 + + + + + D2DTH12R + D2DTH12R + DAC2 12-bit right aligned data holding register (DAC_D2DTH12R) + 0x14 + 0x20 + read-write + 0x00000000 + + + D2DT12R + DAC2 12-bit right-aligned + data + 0 + 12 + + + + + D2DTH12L + D2DTH12L + DAC2 12-bit left aligned data holding register (DAC_D2DTH12L) + 0x18 + 0x20 + read-write + 0x00000000 + + + D2DT12L + DAC2 12-bit left-aligned data + 4 + 12 + + + + + D2DTH8R + D2DTH8R + DAC2 8-bit right-aligned data holding register (DAC_D2DTH8R) + 0x1C + 0x20 + read-write + 0x00000000 + + + D2DT8R + DAC2 8-bit right-aligned + data + 0 + 8 + + + + + DDTH12R + DDTH12R + Dual DAC 12-bit right-aligned data holding register (DAC_DDTH12R), Bits 31:28 Reserved, Bits 15:12 Reserved + 0x20 + 0x20 + read-write + 0x00000000 + + + DD1DT12R + DAC1 12-bit right-aligned data + 0 + 12 + + + DD2DT12R + DAC2 12-bit right-aligned data + 16 + 12 + + + + + DDTH12L + DDTH12L + DUAL DAC 12-bit left aligned data holding register (DAC_DDTH12L), Bits 19:16 Reserved, Bits 3:0 Reserved + 0x24 + 0x20 + read-write + 0x00000000 + + + DD1DT12L + DAC1 12-bit left-aligned data + 4 + 12 + + + DD2DT12L + DAC2 12-bit right-aligned data + 20 + 12 + + + + + DDTH8R + DDTH8R + DUAL DAC 8-bit right aligned data holding register (DAC_DDTH8R), Bits 31:16 Reserved + 0x28 + 0x20 + read-write + 0x00000000 + + + DD1DT8R + DAC1 8-bit right-aligned data + 0 + 8 + + + DD2DT8R + DAC2 8-bit right-aligned data + 8 + 8 + + + + + D1ODT + D1ODT + DAC1 data output register (DAC_D1ODT) + 0x2C + 0x20 + read-only + 0x00000000 + + + D1ODT + DAC1 data output + 0 + 12 + + + + + D2ODT + D2ODT + DAC2 data output register (DAC_D2ODT) + 0x30 + 0x20 + read-only + 0x00000000 + + + D2ODT + DAC2 data output + 0 + 12 + + + + + STS + STS + DAC2 status register + (DAC_STS) + 0x34 + 0x20 + read-write + 0x00000000 + + + D1DMAUDRF + DAC1 DMA underrun flag + 13 + 1 + + + D2DMAUDRF + DAC2 DMA underrun flag + 29 + 1 + + + + + + + DEBUG + Debug support + DEBUG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + DEBUG IDCODE + 0x0 + 0x20 + read-only + 0x0 + + + PID + Product ID + 0 + 32 + + + + + CTRL + CTRL + DEBUG CTRL + 0x4 + 0x20 + read-write + 0x0 + + + SLEEP_DEBUG + SLEEP_DEBUG + 0 + 1 + + + DEEPSLEEP_DEBUG + DEEPSLEEP_DEBUG + 1 + 1 + + + STANDBY_DEBUG + STANDBY_DEBUG + 2 + 1 + + + + + APB1_PAUSE + APB1_PAUSE + DEBUG APB1 PAUSE + 0x8 + 0x20 + read-write + 0x0 + + + TMR2_PAUSE + TMR2_PAUSE + 0 + 1 + + + TMR3_PAUSE + TMR3_PAUSE + 1 + 1 + + + TMR4_PAUSE + TMR4_PAUSE + 2 + 1 + + + TMR6_PAUSE + TMR6_PAUSE + 4 + 1 + + + TMR7_PAUSE + TMR7_PAUSE + 5 + 1 + + + TMR12_PAUSE + TMR12_PAUSE + 6 + 1 + + + TMR13_PAUSE + TMR13_PAUSE + 7 + 1 + + + TMR14_PAUSE + TMR14_PAUSE + 8 + 1 + + + ERTC_PAUSE + ERTC_PAUSE + 10 + 1 + + + WWDT_PAUSE + WWDT_PAUSE + 11 + 1 + + + WDT_PAUSE + WDT_PAUSE + 12 + 1 + + + ERTC512_PAUSE + ERTC512_PAUSE + 15 + 1 + + + I2C1_SMBUS_TIMEOUT + I2C1_SMBUS_TIMEOUT + 24 + 1 + + + CAN1_PAUSE + CAN1_PAUSE + 25 + 1 + + + CAN2_PAUSE + CAN2_PAUSE + 26 + 1 + + + I2C2_SMBUS_TIMEOUT + I2C2_SMBUS_TIMEOUT + 27 + 1 + + + I2C3_SMBUS_TIMEOUT + I2C3_SMBUS_TIMEOUT + 28 + 1 + + + + + APB2_PAUSE + APB2_PAUSE + DEBUG APB2 PAUSE + 0xC + 0x20 + read-write + 0x0 + + + TMR1_PAUSE + TMR1_PAUSE + 0 + 1 + + + TMR8_PAUSE + TMR8_PAUSE + 1 + 1 + + + TMR9_PAUSE + TMR9_PAUSE + 16 + 1 + + + TMR10_PAUSE + TMR10_PAUSE + 17 + 1 + + + TMR11_PAUSE + TMR11_PAUSE + 18 + 1 + + + + + SER_ID + SER_ID + SERIES ID + 0x20 + 0x20 + read-only + 0x0 + + + REV_ID + version ID + 0 + 3 + + + SER_ID + series ID + 8 + 8 + + + + + + + UART4 + Universal asynchronous receiver transmitter + 0x40004C00 + + UART4 + UART4 global interrupt + 52 + + + + UART5 + Universal asynchronous receiver transmitter + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + UART7 + Universal asynchronous receiver transmitter + 0x40007800 + + UART7 + UART7 global interrupt + 82 + + + + UART8 + Universal asynchronous receiver transmitter + 0x40007C00 + + UART8 + UART8 global interrupt + 83 + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DT + DT + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DT + Data Register + 0 + 32 + + + + + CDT + CDT + Common data register + 0x4 + 0x20 + read-write + 0x00000000 + + + CDT + Common Data + 0 + 1 + + + + + CTRL + CTRL + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RST + Reset bit + 0 + 1 + + + REVID + Reverse input data + 5 + 2 + + + REVOD + Reverse output data + 7 + 1 + + + + + IDT + IDT + Initial data register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + IDT + Initial Data + 0 + 32 + + + + + + + FLASH + Flash memory controler + FLASH + 0x40023C00 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + PSR + PSR + Performance selection register + 0x0 + 0x20 + 0x00000330 + + + NZW_BST_STS + Flash non-zero wait area boost status + 13 + 1 + read-only + + + NZW_BST + Flash non-zero wait area boost + 12 + 1 + read-write + + + + + UNLOCK + UNLOCK + Unlock register + 0x4 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + USD_UNLOCK + USD_UNLOCK + USD unlock register + 0x8 + 0x20 + write-only + 0x00000000 + + + USD_UKVAL + User system data Unlock key value + 0 + 32 + + + + + STS + STS + Status register + 0xC + 0x20 + 0x00000000 + + + ODF + Operate done flag + 5 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + PRGMERR + program error + 2 + 1 + read-write + + + OBF + Operate busy flag + 0 + 1 + read-only + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + BLKERS + Block erase + 3 + 1 + + + USDPRGM + User system data program + 4 + 1 + + + USDERS + User system data erase + 5 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + USDULKS + User system data unlock success + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR + ADDR + Address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + USD + USD + User system data register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + USDERR + User system data error + 0 + 1 + + + FAP + FLASH access protection + 1 + 1 + + + nWDT_ATO_EN + WDT auto enable + 2 + 1 + + + nDEPSLP_RST + Deepsleep reset + 3 + 1 + + + nSTDBY_RST + Standby reset + 4 + 1 + + + BTOPT + boot option + 5 + 1 + + + nWDT_DEPSLP + WDT deep sleep + 7 + 1 + + + nWDT_STDBY + WDT standby + 8 + 1 + + + USER_D0 + User data 0 + 10 + 8 + + + USER_D1 + User data 1 + 18 + 8 + + + + + EPPS0 + EPPS0 + Erase/program protection status register 0 + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + EPPS1 + EPPS1 + Erase/program protection status register 1 + 0x2C + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + UNLOCK2 + UNLOCK2 + Unlock 2 register + 0x44 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + STS2 + STS2 + Status 2 register + 0x4C + 0x20 + 0x00000000 + + + OBF + Operate busy flag + 0 + 1 + read-only + + + PRGMERR + program error + 2 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + ODF + Operate done flag + 5 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control 2 register + 0x50 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + BLKERS + Block erase + 3 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR2 + ADDR2 + Address 2 register + 0x54 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + CONTR + CONTR + Flash continue read register + 0x58 + 0x20 + read-write + 0x00000080 + + + FCONTR_EN + Flash continue read enable + 31 + 1 + + + + + DIVR + DIVR + Flash divider register + 0x60 + 0x20 + 0x00000022 + + + FDIV + Flash divider + 0 + 2 + read-write + + + FDIV_STS + Flash divider status + 4 + 2 + read-only + + + + + SLIB_STS2 + SLIB_STS2 + sLib status 2 register + 0xC8 + 0x20 + 0x0000FFFF + + + SLIB_INST_SS + sLib instruction start sector + 0 + 16 + read-only + + + + + SLIB_STS0 + SLIB_STS0 + sLib status 0 register + 0xCC + 0x20 + 0x00000000 + + + SLIB_ENF + sLib enabled flag + 3 + 1 + read-only + + + + + SLIB_STS1 + SLIB_STS1 + sLib status 1 register + 0xD0 + 0x20 + 0xFFFFFFFF + + + SLIB_SS + sLib start sector + 0 + 16 + read-only + + + SLIB_ES + sLib end sector + 16 + 16 + read-only + + + + + SLIB_PWD_CLR + SLIB_PWD_CLR + SLIB password clear register + 0xD4 + 0x20 + 0x00000000 + write-only + + + SLIB_PCLR_VAL + sLib password clear value + 0 + 32 + + + + + SLIB_MISC_STS + SLIB_MISC_STS + sLib misc status register + 0xD8 + 0x20 + 0x01000000 + + + SLIB_PWD_ERR + sLib password error + 0 + 1 + read-only + + + SLIB_PWD_OK + sLib password ok + 1 + 1 + read-only + + + SLIB_ULKF + sLib unlock flag + 2 + 1 + read-only + + + SLIB_RCNT + sLib remaining count + 16 + 9 + read-only + + + + + SLIB_SET_PWD + SLIB_SET_PWD + sLib password setting register + 0xDC + 0x20 + 0x00000000 + write-only + + + SLIB_PSET_VAL + sLib password setting val + 0 + 32 + + + + + SLIB_SET_RANGE0 + SLIB_SET_RANGE0 + Configure sLib range register 0 + 0xE0 + 0x20 + 0x00000000 + write-only + + + SLIB_SS_SET + sLib start sector setting + 0 + 16 + + + SLIB_ES_SET + sLib end sector setting + 16 + 16 + + + + + SLIB_SET_RANGE1 + SLIB_SET_RANGE1 + Configure sLib range register 1 + 0xE4 + 0x20 + 0x00000000 + write-only + + + SLIB_ISS_SET + sLib instruction start sector setting + 0 + 16 + + + SET_SLIB_STRT + sLib start setting + 31 + 1 + + + + + SLIB_UNLOCK + SLIB_UNLOCK + sLib unlock register + 0xF0 + 0x20 + 0x00000000 + write-only + + + SLIB_UKVAL + sLib unlock key value + 0 + 32 + + + + + CRC_CTRL + CRC_CTRL + CRC controler register + 0xF4 + 0x20 + 0x00000000 + write-only + + + CRC_SS + CRC start sector + 0 + 12 + + + CRC_SN + CRC sector numbler + 12 + 12 + + + CRC_STRT + CRC start + 31 + 1 + + + + + CRC_CHKR + CRC_CHKR + CRC check result register + 0xF8 + 0x20 + 0x00000000 + read-only + + + CRC_CHKR + CRC check result + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + DVP + Digital video parallel interface + DVP + 0x50050000 + + 0x0 + 0x400 + registers + + + DVP + DVP global interrupt + 78 + + + + CTRL + CTRL + Control register + 0x0 + 0x20 + 0x0000 + + + LCDS + Line capture/drop selection + 20 + 1 + read-write + + + LCDC + Line capture/drop control + + 19 + 1 + read-write + + + PCDS + Pixel capture/drop selection + + 18 + 1 + read-write + + + PCDC + Basic pixel capture/drop control + + 16 + 2 + read-write + + + ENA + DVP enable + 14 + 1 + read-write + + + PDL + Pixel data length + 10 + 2 + read-write + + + BFRC + Basic frame rate control + 8 + 2 + read-write + + + VSP + Vertical synchronization + polarity + 7 + 1 + read-write + + + HSP + Horizontal synchronization polarity + + 6 + 1 + read-write + + + CKP + Pixel clock polarity + 5 + 1 + read-write + + + SM + synchronization mode + 4 + 1 + read-write + + + JPEG + JPEG format + 3 + 1 + read-write + + + CRP + Cropping function enable + 2 + 1 + read-write + + + CFM + Capture fire mode + 1 + 1 + read-write + + + CAP + Capture function enable + 0 + 1 + read-write + + + + + STS + STS + status register + 0x4 + 0x20 + read-only + 0x0000 + + + OFNE + Output FIFO Non-empty + 2 + 1 + + + VSYN + Vertical synchronization status + 1 + 1 + + + HSYN + Horizontal synchronization status + 0 + 1 + + + + + ESTS + ESTS + Event status register + 0x8 + 0x20 + read-only + 0x0000 + + + HSES + Horizontal synchronization event status + 4 + 1 + + + VSES + Vertical synchronization event status + 3 + 1 + + + ESEES + Embedded synchronization error event status + + 2 + 1 + + + OVRES + Data FIFO overrun event status + + 1 + 1 + + + CFDES + Capture frame done event status + + 0 + 1 + + + + + IENA + IENA + interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + HSIE + Horizontal synchronization interrupt enable + + 4 + 1 + + + VSIE + Vertical synchronization interrupt enablee + + 3 + 1 + + + ESEIE + Embedded synchronization error interrupt + enable + 2 + 1 + + + OVRIE + Data FIFO overrun interrupt enable + + 1 + 1 + + + CFDIE + Capture frame done interrupt enable + + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-only + 0x0000 + + + HSIS + Horizontal synchronization interrupt + status + 4 + 1 + + + VSIS + Vertical synchronization interrupt + status + 3 + 1 + + + ESEIS + Embedded synchronization error + interrupt status + 2 + 1 + + + OVRIS + Data FIFO overrun interrupt + status + 1 + 1 + + + CFDIS + Capture frame done interrupt + status + 0 + 1 + + + + + ICLR + ICLR + Interrupt clear register + 0x14 + 0x20 + write-only + 0x0000 + + + HSIC + Horizontal synchronization + interrupt clear + 4 + 1 + + + VSIC + Vertical synchronization + interrupt clear + 3 + 1 + + + ESEIC + Embedded synchronization + error interrupt clear + 2 + 1 + + + OVRIC + Data FIFO overrun + interrupt clear + 1 + 1 + + + CFDIC + Capture frame done + interrupt clear + 0 + 1 + + + + + SCR + SCR + Synchronization code + register + 0x18 + 0x20 + read-write + 0x0000 + + + FMEC + Frame end code + 24 + 8 + + + LNEC + Line end code + 16 + 8 + + + LNSC + Line start code + 8 + 8 + + + FMSC + Frame start code + 0 + 8 + + + + + SUR + SUR + Synchronization unmask + register + 0x1C + 0x20 + read-write + 0x0000 + + + FMEU + Frame end unmask + 24 + 8 + + + LNEU + Line end unmask + 16 + 8 + + + LNSU + Line start unmask + + 8 + 8 + + + FMSU + Frame start unmask + + 0 + 8 + + + + + CWST + CWST + Crop window start + 0x20 + 0x20 + read-write + 0x0000 + + + CVSTR + Cropping window vertical start line + + 16 + 13 + + + CHSTR + Cropping window horizontal start pixel + + 0 + 14 + + + + + CWSZ + CWSZ + Crop window size + 0x24 + 0x20 + read-write + 0x0000 + + + CVNUM + Cropping window vertical line number + + 16 + 14 + + + CHNUM + Cropping window horizontal pixel number + + 0 + 14 + + + + + DT + DT + Data register + 0x28 + 0x20 + read-only + 0x0000 + + + DT + Data Port + 0 + 32 + + + + + ACTRL + ACTRL + Advanced Control register + + 0x40 + 0x20 + read-write + 0x0000 + + + VSEID + Vertical synchonization event and interrupt + definition + 17 + 1 + + + HSEID + Horizontal synchonization event and interrupt + definition + 16 + 1 + + + DMABT + DMA burst transfer configuration + + 12 + 1 + + + IDUS + Input data un-used setting + + 10 + 1 + + + IDUN + Input data un-used number + + 8 + 2 + + + EFDM + Enhanced function data format management + + 6 + 1 + + + EFDF + Enhanced function data format + + 4 + 2 + + + PCDES + Basic pixel capture/drop extended + selection + 3 + 1 + + + MIBE + Monochrome image binarization + enable + 2 + 1 + + + EFRCE + Enhanced frame rate control + enable + 1 + 1 + + + EISRE + Enhanced image scaling resize + enable + 0 + 1 + + + + + HSCF + HSCF + Horizontal scaling control flow + + 0x48 + 0x20 + read-write + 0x0000 + + + HSRTF + Horizontal scaling resize target factor + + 16 + 13 + + + HSRSF + Horizontal scaling resize source factor + + 0 + 13 + + + + + VSCF + VSCF + Vertical scaling control flow + + 0x4C + 0x20 + read-write + 0x0000 + + + VSRTF + Vertical scaling resize target factor + + 16 + 13 + + + VSRSF + Vertical scaling resize source factor + + 0 + 13 + + + + + FRF + FRF + Frame rate flow + + 0x50 + 0x20 + read-write + 0x0000 + + + EFRCTF + Enhanced frame rate control target factor + + 8 + 5 + + + EFRCSF + Enhanced frame rate contorl source factor + + 0 + 5 + + + + + BTH + BTH + Binarization threshold + + 0x54 + 0x20 + read-write + 0x0000 + + + MIBTHD + Monochrome image binarization threshold + + 0 + 8 + + + + + + + USB_OTGFS_GLOBAL + USB on-the-go full speed + USB_OTGFS + 0x50000000 + + 0x0 + 0x400 + registers + + + OTGFS1 + USB On The Go FS global + interrupt + 67 + + + + GOTGCTL + GOTGCTL + OTGFS control and status register + (OTGFS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGFS interrupt register + (OTGFS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGFS AHB configuration register + (OTGFS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGFS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + FS timeout calibration + 0 + 3 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGFS reset register + (OTGFS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGFS core interrupt register + (OTGFS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-write + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGFS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGFS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGFS Receive FIFO size register + (OTGFS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGFS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGFS non-periodic transmit FIFO/queue + status register (OTGFS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGFS general core configuration register + (OTGFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + LP_MODE + Low power mode + 17 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGFS Host periodic transmit FIFO size + register (OTGFS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO5 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF6) + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO6 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF7) + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO7 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTGFS_HOST + USB on the go full speed + USB_OTGFS + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGFS host configuration register + (OTGFS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGFS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGFS host frame number/frame time + remaining register (OTGFS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGFS_Host periodic transmit FIFO/queue + status register (OTGFS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGFS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGFS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGFS host port control and status register + (OTGFS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGFS host channel-0 characteristics + register (OTGFS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGFS host channel-1 characteristics + register (OTGFS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGFS host channel-2 characteristics + register (OTGFS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGFS host channel-3 characteristics + register (OTGFS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGFS host channel-4 characteristics + register (OTGFS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGFS host channel-5 characteristics + register (OTGFS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGFS host channel-6 characteristics + register (OTGFS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTGFS host channel-8 characteristics + register (OTGFS_HCCHAR8) + 0x200 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTGFS host channel-9 characteristics + register (OTGFS_HCCHAR9) + 0x220 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTGFS host channel-10 characteristics + register (OTGFS_HCCHAR10) + 0x240 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR11) + 0x260 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTGFS host channel-12 characteristics + register (OTGFS_HCCHAR12) + 0x280 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTGFS host channel-13 characteristics + register (OTGFS_HCCHAR13) + 0x2A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTGFS host channel-14 characteristics + register (OTGFS_HCCHAR14) + 0x2C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTGFS host channel-15 characteristics + register (OTGFS_HCCHAR15) + 0x2E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGFS host channel-0 interrupt register + (OTGFS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGFS host channel-2 interrupt register + (OTGFS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGFS host channel-3 interrupt register + (OTGFS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGFS host channel-4 interrupt register + (OTGFS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGFS host channel-5 interrupt register + (OTGFS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGFS host channel-6 interrupt register + (OTGFS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGFS host channel-7 interrupt register + (OTGFS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT8 + HCINT8 + OTGFS host channel-8 interrupt register + (OTGFS_HCINT8) + 0x208 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT9 + HCINT9 + OTGFS host channel-9 interrupt register + (OTGFS_HCINT9) + 0x228 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT10 + HCINT10 + OTGFS host channel-10 interrupt register + (OTGFS_HCINT10) + 0x248 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT11 + HCINT11 + OTGFS host channel-11 interrupt register + (OTGFS_HCINT11) + 0x268 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT12 + HCINT12 + OTGFS host channel-12 interrupt register + (OTGFS_HCINT12) + 0x288 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT13 + HCINT13 + OTGFS host channel-13 interrupt register + (OTGFS_HCINT13) + 0x2A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT14 + HCINT14 + OTGFS host channel-14 interrupt register + (OTGFS_HCINT14) + 0x2C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT15 + HCINT15 + OTGFS host channel-15 interrupt register + (OTGFS_HCINT15) + 0x2E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGFS host channel-0 mask register + (OTGFS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGFS host channel-1 mask register + (OTGFS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGFS host channel-2 mask register + (OTGFS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGFS host channel-3 mask register + (OTGFS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGFS host channel-4 mask register + (OTGFS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGFS host channel-5 mask register + (OTGFS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGFS host channel-6 mask register + (OTGFS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGFS host channel-7 mask register + (OTGFS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + OTGFS host channel-8 mask register + (OTGFS_HCINTMSK8) + 0x20C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + OTGFS host channel-9 mask register + (OTGFS_HCINTMSK9) + 0x22C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + OTGFS host channel-10 mask register + (OTGFS_HCINTMSK10) + 0x24C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + OTGFS host channel-11 mask register + (OTGFS_HCINTMSK11) + 0x26C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + OTGFS host channel-12 mask register + (OTGFS_HCINTMSK12) + 0x28C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + OTGFS host channel-13 mask register + (OTGFS_HCINTMSK13) + 0x2AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + OTGFS host channel-14 mask register + (OTGFS_HCINTMSK14) + 0x2CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + OTGFS host channel-15 mask register + (OTGFS_HCINTMSK15) + 0x2EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGFS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ1 + HCTSIZ1 + OTGFS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ2 + HCTSIZ2 + OTGFS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ3 + HCTSIZ3 + OTGFS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ4 + HCTSIZ4 + OTGFS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ5 + HCTSIZ5 + OTGFS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ6 + HCTSIZ6 + OTGFS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ7 + HCTSIZ7 + OTGFS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ8 + HCTSIZ8 + OTGFS host channel-8 transfer size + register + 0x210 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ9 + HCTSIZ9 + OTGFS host channel-9 transfer size + register + 0x230 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ10 + HCTSIZ10 + OTGFS host channel-10 transfer size + register + 0x250 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ11 + HCTSIZ11 + OTGFS host channel-11 transfer size + register + 0x270 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ12 + HCTSIZ12 + OTGFS host channel-12 transfer size + register + 0x290 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ13 + HCTSIZ13 + OTGFS host channel-13 transfer size + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ14 + HCTSIZ14 + OTGFS host channel-14 transfer size + register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ15 + HCTSIZ15 + OTGFS host channel-15 transfer size + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + + + USB_OTGFS_DEVICE + USB on the go full speed + USB_OTGFS + 0x50000800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGFS device configuration register + (OTGFS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGFS device control register + (OTGFS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTGFS device IN endpoint common interrupt + mask register (OTGFS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTGFS device OUT endpoint common interrupt + mask register (OTGFS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + + + DAINT + DAINT + OTGFS device all endpoints interrupt + register (OTGFS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGFS all endpoints interrupt mask register + (OTGFS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGFS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEPCTL0 + DIEPCTL0 + OTGFS device control IN endpoint 0 control + register (OTGFS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-only + + + EPTENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTGFS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGFS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGFS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL4 + DIEPCTL4 + OTGFS device IN endpoint-4 control + register + 0x180 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL5 + DIEPCTL5 + OTGFS device IN endpoint-5 control + register + 0x1A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL6 + DIEPCTL6 + OTGFS device IN endpoint-6 control + register + 0x1C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL7 + DIEPCTL7 + OTGFS device IN endpoint-7 control + register + 0x1E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGFS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGFS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGFS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGFS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL4 + DOEPCTL4 + OTGFS device OUT endpoint-4 control + register + 0x380 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL5 + DOEPCTL5 + OTGFS device OUT endpoint-5 control + register + 0x3A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL6 + DOEPCTL6 + OTGFS device OUT endpoint-6 control + register + 0x3C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL7 + DOEPCTL7 + OTGFS device OUT endpoint-7 control + register + 0x3E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGFS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT1 + DIEPINT1 + OTGFS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT2 + DIEPINT2 + OTGFS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT3 + DIEPINT3 + OTGFS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT4 + DIEPINT4 + OTGFS device IN endpoint-4 interrupt + register + 0x188 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT5 + DIEPINT5 + OTGFS device IN endpoint-5 interrupt + register + 0x1A8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT6 + DIEPINT6 + OTGFS device IN endpoint-6 interrupt + register + 0x1C8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT7 + DIEPINT7 + OTGFS device IN endpoint-7 interrupt + register + 0x1E8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DOEPINT0 + DOEPINT0 + OTGFS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT1 + DOEPINT1 + OTGFS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT2 + DOEPINT2 + OTGFS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT3 + DOEPINT3 + OTGFS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT4 + DOEPINT4 + OTGFS device OUT endpoint-4 interrupt + register + 0x388 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT5 + DOEPINT5 + OTGFS device OUT endpoint-5 interrupt + register + 0x3A8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT6 + DOEPINT6 + OTGFS device OUT endpoint-6 interrupt + register + 0x3C8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT7 + DOEPINT7 + OTGFS device OUT endpoint-7 interrupt + register + 0x3E8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGFS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGFS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGFS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGFS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ4 + DIEPTSIZ4 + OTG device IN endpoint-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ5 + DIEPTSIZ5 + OTG device IN endpoint-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ6 + DIEPTSIZ6 + OTG device IN endpoint-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ7 + DIEPTSIZ7 + OTG device IN endpoint-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + OTGFS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGFS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGFS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGFS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS4 + DTXFSTS4 + OTGFS device IN endpoint-4 transmit FIFO + status register + 0x198 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS5 + DTXFSTS5 + OTGFS device IN endpoint-5 transmit FIFO + status register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS6 + DTXFSTS6 + OTGFS device IN endpoint-6 transmit FIFO + status register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS7 + DTXFSTS7 + OTGFS device IN endpoint-7 transmit FIFO + status register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGFS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGFS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGFS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + OTGFS device OUT endpoint-4 transfer size + register + 0x390 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + OTGFS device OUT endpoint-5 transfer size + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + OTGFS device OUT endpoint-6 transfer size + register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + OTGFS device OUT endpoint-7 transfer size + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + + + USB_OTGFS_PWRCLK + USB on the go full speed + USB_OTGFS + 0x50000E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGFS power and clock gating control + register (OTGFS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + SCFG + System configuration controller + SCFG + 0x40013800 + + 0x0 + 0x400 + registers + + + + CFG1 + CFG1 + configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MAP_SEL + Memory address mapping selection bits + 0 + 3 + + + IR_POL + IR output polarity selection + 5 + 1 + + + IR_SRC_SEL + IR signal source selection + 6 + 2 + + + + + CFG2 + CFG2 + configuration register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + LOCKUP_LK + CM4 LOCKUP bit enable + 0 + 1 + + + PVM_LK + PVM lock enable + 2 + 1 + + + I2S_FD + I2S full duplex configuration bit + 30 + 2 + + + + + EXINTC1 + EXINTC1 + external interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXINT3 + EXINT 3 configuration bits + 12 + 4 + + + EXINT2 + EXINT 2 configuration bits + 8 + 4 + + + EXINT1 + EXINT 1 configuration bits + 4 + 4 + + + EXINT0 + EXINT 0 configuration bits + 0 + 4 + + + + + EXINTC2 + EXINTC2 + external interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXINT7 + EXINT 7 configuration bits + 12 + 4 + + + EXINT6 + EXINT 6 configuration bits + 8 + 4 + + + EXINT5 + EXINT 5 configuration bits + 4 + 4 + + + EXINT4 + EXINT 4 configuration bits + 0 + 4 + + + + + EXINTC3 + EXINTC3 + external interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXINT11 + EXINT 11 configuration bits + 12 + 4 + + + EXINT10 + EXINT 10 configuration bits + 8 + 4 + + + EXINT9 + EXINT 9 configuration bits + 4 + 4 + + + EXINT8 + EXINT 8 configuration bits + 0 + 4 + + + + + EXINTC4 + EXINTC4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXINT15 + EXINT 15 configuration bits + 12 + 4 + + + EXINT14 + EXINT 14 configuration bits + 8 + 4 + + + EXINT13 + EXINT 13 configuration bits + 4 + 4 + + + EXINT12 + EXINT 12 configuration bits + 0 + 4 + + + + + UHDRV + UHDRV + Ultra high drive register + 0x2C + 0x20 + read-write + 0x0000 + + + PD13_UH + PD13 ultra high sourcing/sinking strength + 6 + 1 + + + PD12_UH + PD12 ultra high sourcing/sinking strength + 5 + 1 + + + PB8_UH + PB8 ultra high sourcing/sinking strength + 3 + 1 + + + PB9_UH + PB9 ultra high sourcing/sinking strength + 1 + 1 + + + + + + + QSPI1 + Quad SPI Controller + QSPI + 0xA0001000 + + 0x0 + 0x400 + registers + + + QSPI1 + QSPI1 global interrupt + 92 + + + + CMD_W0 + CMD_W0 + Command word 0 + 0x0 + 0x20 + read-write + 0x00000000 + + + SPIADR + SPI flash address + 0 + 32 + + + + + CMD_W1 + CMD_W1 + Command word 1 + 0x4 + 0x20 + read-write + 0x01000003 + + + ADRLEN + SPI address length + 0 + 3 + + + DUM2 + Second dummy state cycle + 16 + 8 + + + INSLEN + Instruction code length + 24 + 2 + + + PEMEN + Perfrmance enhance mode enable + 28 + 1 + + + + + CMD_W2 + CMD_W2 + Command word 2 + 0x8 + 0x20 + read-write + 0x01000003 + + + DCNT + Read write data counter + 0 + 32 + + + + + CMD_W3 + CMD_W3 + Command word 3 + 0xC + 0x20 + read-write + 0x00000000 + + + WEN + Write data enable + 1 + 1 + + + RSTSEN + Read spi status enable + 2 + 1 + + + RSTSC + Read spi status configure + 3 + 1 + + + OPMODE + SPI operate mode + 5 + 3 + + + PEMOPC + Performance enhance mode operate code + 16 + 8 + + + INSC + Instruction code + 24 + 8 + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000000 + + + CLKDIV + SPI clock divider + 0 + 3 + + + SCKMODE + Sckout mode + 4 + 1 + + + XIPIDLE + XIP port idle status + 7 + 1 + + + ABORT + Abort instruction + 8 + 1 + + + BUSY + Busy bit of spi status + 16 + 3 + + + XIPRCMDF + XIP read command flush + 19 + 1 + + + XIPSEL + XIP port selection + 20 + 1 + + + KEYEN + encryption key enable + 21 + 1 + + + + + ACTR + ACTR + AC timing control register + 0x14 + 0x20 + read-write + 0x0000000F + + + CSDLY + CS delay + 0 + 4 + + + + + FIFOSTS + FIFOSTS + FIFO Status register + 0x18 + 0x20 + read-only + 0x00000001 + + + TXFIFORDY + TxFIFO ready status + 0 + 1 + + + RXFIFORDY + RxFIFO ready status + 1 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x20 + 0x20 + read-write + 0x00000001 + + + DMAEN + DMA handshake enable + 0 + 1 + + + CMDIE + Command complete interrupt enable + 1 + 1 + + + TXFIFOTHOD + TxFIFO thod + 8 + 2 + + + RXFIFOTHOD + RxFIFO thod + 12 + 2 + + + + + CMDSTS + CMDSTS + CMD status register + 0x24 + 0x20 + read-only + 0x00000000 + + + CMDSTS + Command complete status + 0 + 1 + + + + + RSTS + RSTS + SPI read status register + 0x28 + 0x20 + read-only + 0x00000000 + + + SPISTS + SPI read status + 0 + 8 + + + + + FSIZE + FSIZE + SPI flash size + 0x2C + 0x20 + read-write + 0x00000000 + + + SPIFSIZE + SPI flash size + 0 + 32 + + + + + XIP_CMD_W0 + XIP_CMD_W0 + XIP command word 0 + 0x30 + 0x20 + read-write + 0x00000000 + + + XIPR_DUM2 + XIP read second dummy cycle + 0 + 8 + + + XIPR_OPMODE + XIP read operate mode + 8 + 3 + + + XIPR_ADRLEN + XIP read address length + 11 + 1 + + + XIPR_INSC + XIP read instruction code + 12 + 8 + + + + + XIP_CMD_W1 + XIP_CMD_W1 + XIP command word 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + XIPW_DUM2 + XIP write second dummy cycle + 0 + 8 + + + XIPW_OPMODE + XIP write operate mode + 8 + 3 + + + XIPW_ADRLEN + XIP write address length + 11 + 1 + + + XIPW_INSC + XIP write instruction code + 12 + 8 + + + + + XIP_CMD_W2 + XIP_CMD_W2 + XIP command word 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + XIPR_DCNT + XIP read data counter + 0 + 6 + + + XIPR_TCNT + XIP continue read cycle counter + 8 + 7 + + + XIPR_SEL + XIP read continue mode select + 15 + 1 + + + XIPW_DCNT + XIP write data counter + 16 + 6 + + + XIPW_TCNT + XIP continue write cycle counter + 24 + 7 + + + XIPW_SEL + XIP write continue mode select + 31 + 1 + + + + + XIP_CMD_W3 + XIP_CMD_W3 + XIP command word 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + BYPASSC + Bypass cache function + 0 + 1 + + + CSTS + Cache status + 3 + 1 + + + + + REV + REV + Revision + 0x50 + 0x20 + read-write + 0x00010500 + + + REVISION + Revision number + 0 + 31 + + + + + DT + DT + 32/16/8 bit data port register + 0x100 + 0x20 + read-write + 0x00000000 + + + + + QSPI2 + 0xA0002000 + + QSPI2 + QSPI2 global interrupt + 91 + + + + diff --git a/hw/bsp/at32f423/boards/AT_START_F423/board.h b/hw/bsp/at32f423/boards/AT_START_F423/board.h new file mode 100644 index 000000000..fc8e2d8a5 --- /dev/null +++ b/hw/bsp/at32f423/boards/AT_START_F423/board.h @@ -0,0 +1,91 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define USB_VBUS_IGNORE + +// LED +#define LED_PORT GPIOD +#define LED_PIN GPIO_PINS_13 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +// UART +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK +#define PRINT_UART_TX_PIN_SOURCE GPIO_PINS_SOURCE9 +#define PRINT_UART_TX_PIN_MUX_NUM GPIO_MUX_7 + +//USB +#define USB_ID 0 +#define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK +#define OTG_IRQ OTGFS1_IRQn +#define OTG_IRQ_HANDLER OTGFS1_IRQHandler +#define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn +#define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler +#define OTG_WKUP_EXINT_LINE EXINT_LINE_18 +#define OTG_PIN_GPIO GPIOA +#define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_DP GPIO_PINS_12 +#define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE12 +#define OTG_PIN_DM GPIO_PINS_11 +#define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE11 +#define OTG_PIN_VBUS GPIO_PINS_9 +#define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 +#define OTG_PIN_ID GPIO_PINS_10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_SOF_GPIO GPIOA +#define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_SOF GPIO_PINS_8 +#define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 +#define OTG_PIN_MUX GPIO_MUX_10 + +//Vbus +static inline void board_vbus_sense_init(void) +{ + *(int*)(0x50000038) |= (1<<21); +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f423/boards/AT_START_F423/board.mk b/hw/bsp/at32f423/boards/AT_START_F423/board.mk new file mode 100644 index 000000000..95ec21d02 --- /dev/null +++ b/hw/bsp/at32f423/boards/AT_START_F423/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F423xC_FLASH.ld + +CFLAGS += \ + -DAT32F423VCT7 diff --git a/hw/bsp/at32f423/family.c b/hw/bsp/at32f423/family.c new file mode 100644 index 000000000..f63fb8962 --- /dev/null +++ b/hw/bsp/at32f423/family.c @@ -0,0 +1,294 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f423_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void usb_clock48m_select(usb_clk48_s clk_s); +void led_and_button_init(void); +void uart_print_init(uint32_t baudrate); +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTGFS1_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGFS1_WKUP_IRQHandler(void) +{ + tusb_int_handler(0, true); +} + +void board_init(void) +{ + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* config system clock */ + system_clock_config(); + + /* enable usb clock */ + crm_periph_clock_enable(OTG_CLOCK, TRUE); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HEXT); + + /* vbus ignore */ + board_vbus_sense_init(); + + /* configure systick */ + systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); + SysTick_Config(SystemCoreClock / 1000); + #if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + #endif + + /* otgfs use vbus pin */ + #ifndef USB_VBUS_IGNORE + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); + #endif + + /* config led and key */ + led_and_button_init(); + + /* config usart printf */ + uart_print_init(115200); + printf("usart printf config success!\r\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + switch(system_core_clock) + { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_3); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_4); + break; + + /* 120MHz */ + case 120000000: + crm_usb_clock_div_set(CRM_USB_DIV_5); + break; + + /* 144MHz */ + case 144000000: + crm_usb_clock_div_set(CRM_USB_DIV_6); + break; + + default: + break; + } + } +} +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + gpio_pin_mux_config(PRINT_UART_TX_GPIO, PRINT_UART_TX_PIN_SOURCE, PRINT_UART_TX_PIN_MUX_NUM); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +void led_and_button_init(void) +{ + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); +} + +void board_led_write(bool state) +{ + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) +{ + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + +int board_uart_read(uint8_t *buf, int len) +{ + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + +#if CFG_TUSB_OS == OPT_OS_NONE + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + + uint32_t board_millis(void) + { + return system_ticks; + } + + void SVC_Handler(void) + { + } + + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) +{ + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/at32f423/family.mk b/hw/bsp/at32f423/family.mk new file mode 100644 index 000000000..2653842da --- /dev/null +++ b/hw/bsp/at32f423/family.mk @@ -0,0 +1,44 @@ +# Submodules +AT32F423_SDK = hw/mcu/artery/at32f423 +DEPS_SUBMODULES += $(AT32F423_SDK) + +# AT32 SDK path +AT32F423_SDK_SRC = $(AT32F423_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F423 \ + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(AT32F423_SDK_SRC)/drivers/src/at32f423_gpio.c \ + $(AT32F423_SDK_SRC)/drivers/src/at32f423_misc.c \ + $(AT32F423_SDK_SRC)/drivers/src/at32f423_usart.c \ + $(AT32F423_SDK_SRC)/drivers/src/at32f423_crm.c \ + $(AT32F423_SDK_SRC)/drivers/src/at32f423_acc.c \ + $(AT32F423_SDK_SRC)/cmsis/cm4/device_support/system_at32f423.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F423_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F423_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F423_SDK_SRC)/cmsis/cm4/device_support + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f423.s + +# For freeRTOS port source +#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4 + +flash: flash-atlink diff --git a/hw/bsp/at32f423/startup_at32f423.s b/hw/bsp/at32f423/startup_at32f423.s new file mode 100644 index 000000000..764380f0e --- /dev/null +++ b/hw/bsp/at32f423/startup_at32f423.s @@ -0,0 +1,483 @@ +/** + ****************************************************************************** + * @file startup_at32f423.s + * @brief at32f423 devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */ + .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_IRQHandler /* ADC1 */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 Channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word ERTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */ + .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */ + .word TMR12_GLOBAL_IRQHandler /* TMR12 */ + .word TMR13_GLOBAL_IRQHandler /* TMR13 */ + .word TMR14_GLOBAL_IRQHandler /* TMR14 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI3_IRQHandler /* SPI3 */ + .word USART4_IRQHandler /* USART4 */ + .word USART5_IRQHandler /* USART5 */ + .word TMR6_DAC_GLOBAL_IRQHandler /* TMR6 & DAC */ + .word TMR7_GLOBAL_IRQHandler /* TMR7 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SE_IRQHandler /* CAN2 SE */ + .word OTGFS1_IRQHandler /* OTGFS1 */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + .word 0 /* Reserved */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EVT_IRQHandler /* I2C3 Event */ + .word I2C3_ERR_IRQHandler /* I2C3 Error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word USART7_IRQHandler /* USART7 */ + .word USART8_IRQHandler /* USART8 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMAMUX_IRQHandler /* DMAMUX */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word ACC_IRQHandler /* ACC */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak ERTC_WKUP_IRQHandler + .thumb_set ERTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak ERTCAlarm_IRQHandler + .thumb_set ERTCAlarm_IRQHandler,Default_Handler + + .weak OTGFS1_WKUP_IRQHandler + .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler + + .weak TMR12_GLOBAL_IRQHandler + .thumb_set TMR12_GLOBAL_IRQHandler,Default_Handler + + .weak TMR13_GLOBAL_IRQHandler + .thumb_set TMR13_GLOBAL_IRQHandler,Default_Handler + + .weak TMR14_GLOBAL_IRQHandler + .thumb_set TMR14_GLOBAL_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak USART4_IRQHandler + .thumb_set USART4_IRQHandler,Default_Handler + + .weak USART5_IRQHandler + .thumb_set USART5_IRQHandler,Default_Handler + + .weak TMR6_DAC_GLOBAL_IRQHandler + .thumb_set TMR6_DAC_GLOBAL_IRQHandler,Default_Handler + + .weak TMR7_GLOBAL_IRQHandler + .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler ,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler ,Default_Handler + + .weak CAN2_SE_IRQHandler + .thumb_set CAN2_SE_IRQHandler,Default_Handler + + .weak OTGFS1_IRQHandler + .thumb_set OTGFS1_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EVT_IRQHandler + .thumb_set I2C3_EVT_IRQHandler,Default_Handler + + .weak I2C3_ERR_IRQHandler + .thumb_set I2C3_ERR_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak USART7_IRQHandler + .thumb_set USART7_IRQHandler,Default_Handler + + .weak USART8_IRQHandler + .thumb_set USART8_IRQHandler,Default_Handler + + .weak DMAMUX_IRQHandler + .thumb_set DMAMUX_IRQHandler ,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..6cc39f727 --- /dev/null +++ b/hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f425.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd b/hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd new file mode 100644 index 000000000..d18e75e8e --- /dev/null +++ b/hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd @@ -0,0 +1,30790 @@ + + + + + + + + Keil + ArteryTek + AT32F425xx_v2 + AT32F425 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 120MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + PVM + PVM through EXTI line detection interrupt + 1 + + + + CTRL + CTRL + Power control register + (PWC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + VRSEL + Voltage regulator state select when deepsleep mode + 0 + 1 + read-write + + + LPSEL + Low power mode select when Cortex-M4 sleepdeep + 1 + 1 + read-write + + + CLSWEF + Clear SWEF flag + 2 + 1 + write-only + + + CLSEF + Clear SEF flag + 3 + 1 + write-only + + + PVMEN + Power voltage monitoring enable + 4 + 1 + read-write + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + read-write + + + BPWEN + Battery power domain write enable + 8 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Power control register + (PWC_CTRLSTS) + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN1 + Standby wake-up pin1 enable + 8 + 1 + read-write + + + SWPEN2 + Standby wake-up pin2 enable + 9 + 1 + read-write + + + SWPEN4 + Standby wake-up pin4 enable + 11 + 1 + read-write + + + SWPEN5 + Standby wake-up pin5 enable + 12 + 1 + read-write + + + SWPEN6 + Standby wake-up pin6 enable + 13 + 1 + read-write + + + SWPEN7 + Standby wake-up pin7 enable + 14 + 1 + read-write + + + + + CTRL2 + CTRL2 + Power control register 2 + (PWC_CTRL2) + 0x20 + 0x20 + 0x00000000 + + + VREXLPEN + Voltage regulator extra low power mode enable + 5 + 1 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40021000 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 4 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + + + CFG + CFG + Clock configuration register + (CRM_CFG) + 0x4 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 8 + 3 + read-write + + + APB2DIV + APB2 division + 11 + 3 + read-write + + + ADCDIV1_0 + ADC division bit1 and bit0 + 14 + 2 + read-write + + + PLLRCS + PLL reference clock select + 16 + 1 + read-write + + + PLLHEXTDIV + HEXT division selection for PLL entry clock + 17 + 1 + read-write + + + PLLMULT3_0 + PLL Multiplication Factor bit3 to bit0 + 18 + 4 + read-write + + + USBDIV1_0 + USB division bit1 and bit0 + 22 + 2 + read-write + + + CLKOUT_SEL + Clock output selection bit2 to bit0 + 24 + 3 + read-write + + + USBDIV2 + USB division bit2 + 27 + 1 + read-write + + + ADCDIV2 + ADC division bit2 + 28 + 1 + read-write + + + PLLMULT5_4 + PLL Multiplication Factor bit5 and bit4 + 29 + 2 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + (CRM_CLKINT) + 0x8 + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + APB2RST + APB2RST + APB2 peripheral reset register + (CRM_APB2RST) + 0xC + 0x20 + read-write + 0x000000000 + + + SCFGRST + System config reset + 0 + 1 + + + EXINTRST + External interrupt reset + 1 + 1 + + + ADC1RST + ADC1 reset + 9 + 1 + + + TMR1RST + TMR1 reset + 11 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + TMR15RST + Timer15 reset + 16 + 1 + + + TMR16RST + Timer16 reset + 17 + 1 + + + TMR17RST + Timer17 reset + 18 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + (CRM_APB1RST) + 0x10 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer 2 reset + 0 + 1 + + + TMR3RST + Timer 3 reset + 1 + 1 + + + TMR6RST + Timer 6 reset + 4 + 1 + + + TMR7RST + Timer 7 reset + 5 + 1 + + + TMR13RST + Timer 13 reset + 7 + 1 + + + TMR14RST + Timer 14 reset + 8 + 1 + + + WWDTRST + Window watchdog timer reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + USART2RST + USART 2 reset + 17 + 1 + + + USART3RST + USART 3 reset + 18 + 1 + + + USART4RST + USART 4 reset + 19 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + ACCRST + ACC reset + 27 + 1 + + + PWCRST + Power controller reset + 28 + 1 + + + + + AHBEN + AHBEN + AHB Peripheral Clock enable register + (CRM_AHBEN) + 0x14 + 0x20 + read-write + 0x00000014 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + + SRAMEN + SRAM interface clock + enable + 2 + 1 + + + FLASHEN + FLASH clock enable + 4 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + OTGFS1EN + OTGFS1 clock enable + 12 + 1 + + + GPIOAEN + I/O port A clock enable + 17 + 1 + + + GPIOBEN + I/O port B clock enable + 18 + 1 + + + GPIOCEN + I/O port C clock enable + 19 + 1 + + + GPIODEN + I/O port D clock enable + 20 + 1 + + + GPIOFEN + I/O port F clock enable + 22 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + (CRM_APB2EN) + 0x18 + 0x20 + read-write + 0x00000000 + + + SCFGEN + System config clock enable + 0 + 1 + + + ADC1EN + ADC1 clock enable + 9 + 1 + + + TMR1EN + Timer1 clock enable + 11 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + TMR15EN + Timer15 clock enable + 16 + 1 + + + TMR16EN + Timer16 clock enable + 17 + 1 + + + TMR17EN + Timer17 clock enable + 18 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + (CRM_APB1EN) + 0x1C + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR6EN + Timer6 clock enable + 4 + 1 + + + TMR7EN + Timer7 clock enable + 5 + 1 + + + TMR13EN + Timer13 clock enable + 7 + 1 + + + TMR14EN + Timer14 clock enable + 8 + 1 + + + WWDTEN + Window watchdog timer clock + enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + USART4EN + USART4 clock enable + 19 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + ACCEN + ACC clock enable + 27 + 1 + + + PWCEN + Power clock enable + 28 + 1 + + + + + BPDC + BPDC + Battery powered domain control register + (CRM_BPDC) + 0x20 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + ERTCSEL + ERTC clock selection + 8 + 2 + read-write + + + ERTCEN + ERTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + (CRM_CTRLSTS) + 0x24 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset flag clear + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + AHBRST + AHBRST + AHB reset register + + 0x28 + 0x20 + 0x00000000 + + + OTGFS1RST + OTGFS1 reset + 12 + 1 + + + GPIOARST + IO port A reset + 17 + 1 + + + GPIOBRST + IO port B reset + 18 + 1 + + + GPIOCRST + IO port C reset + 19 + 1 + + + GPIODRST + IO port D reset + 20 + 1 + + + GPIOFRST + IO port F reset + 22 + 1 + + + + + PLL + PLL + PLL configuration register + (CRM_PLL) + 0x2C + 0x20 + 0x00001F10 + + + PLL_FR + PLL_FR + 0 + 3 + read-write + + + PLL_MS + PLL_MS + 4 + 4 + read-write + + + PLL_NS + PLL_NS + 8 + 9 + read-write + + + PLL_FREF + PLL entry clock reference frequency + 24 + 3 + read-write + + + PLLCFGEN + PLL config enable + 31 + 1 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register1 + 0x30 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + CLKOUT_SEL3 + Clock output bit3 + 16 + 1 + read-write + + + HICKDIV + HICK 6 divider selection + 25 + 1 + read-write + + + CLKOUTDIV + Clock output division + 28 + 4 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register2 + 0x54 + 0x20 + 0x0000000D + + + HICK_TO_USB + HICK_TO_USB + 8 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 9 + 1 + read-write + + + + + + + GPIOA + General purpose I/Os + GPIO + 0x48000000 + + 0x0 + 0x400 + registers + + + + CFGR + CFGR + GPIO configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + IOMC15 + GPIOx pin 15 mode configurate + 30 + 2 + + + IOMC14 + GPIOx pin 14 mode configurate + 28 + 2 + + + IOMC13 + GPIOx pin 13 mode configurate + 26 + 2 + + + IOMC12 + GPIOx pin 12 mode configurate + 24 + 2 + + + IOMC11 + GPIOx pin 11 mode configurate + 22 + 2 + + + IOMC10 + GPIOx pin 10 mode configurate + 20 + 2 + + + IOMC9 + GPIOx pin 9 mode configurate + 18 + 2 + + + IOMC8 + GPIOx pin 8 mode configurate + 16 + 2 + + + IOMC7 + GPIOx pin 7 mode configurate + 14 + 2 + + + IOMC6 + GPIOx pin 6 mode configurate + 12 + 2 + + + IOMC5 + GPIOx pin 5 mode configurate + 10 + 2 + + + IOMC4 + GPIOx pin 4 mode configurate + 8 + 2 + + + IOMC3 + GPIOx pin 3 mode configurate + 6 + 2 + + + IOMC2 + GPIOx pin 2 mode configurate + 4 + 2 + + + IOMC1 + GPIOx pin 1 mode configurate + 2 + 2 + + + IOMC0 + GPIOx pin 0 mode configurate + 0 + 2 + + + + + OMODE + OMODE + GPIO output mode register + 0x4 + 0x20 + read-write + 0x00000000 + + + OM15 + GPIOx pin 15 outpu mode configurate + 15 + 1 + + + OM14 + GPIOx pin 14 outpu mode configurate + 14 + 1 + + + OM13 + GPIOx pin 13 outpu mode configurate + 13 + 1 + + + OM12 + GPIOx pin 12 outpu mode configurate + 12 + 1 + + + OM11 + GPIOx pin 11 outpu mode configurate + 11 + 1 + + + OM10 + GPIOx pin 10 outpu mode configurate + 10 + 1 + + + OM9 + GPIOx pin 9 outpu mode configurate + 9 + 1 + + + OM8 + GPIOx pin 8 outpu mode configurate + 8 + 1 + + + OM7 + GPIOx pin 7 outpu mode configurate + 7 + 1 + + + OM6 + GPIOx pin 6 outpu mode configurate + 6 + 1 + + + OM5 + GPIOx pin 5 outpu mode configurate + 5 + 1 + + + OM4 + GPIOx pin 4 outpu mode configurate + 4 + 1 + + + OM3 + GPIOx pin 3 outpu mode configurate + 3 + 1 + + + OM2 + GPIOx pin 2 outpu mode configurate + 2 + 1 + + + OM1 + GPIOx pin 1 outpu mode configurate + 1 + 1 + + + OM0 + GPIOx pin 0 outpu mode configurate + 0 + 1 + + + + + ODRVR + ODRVR + GPIO drive capability register + 0x8 + 0x20 + read-write + 0x00000000 + + + ODRV15 + GPIOx pin 15 output drive capability + 30 + 2 + + + ODRV14 + GPIOx pin 14 output drive capability + 28 + 2 + + + ODRV13 + GPIOx pin 13 output drive capability + 26 + 2 + + + ODRV12 + GPIOx pin 12 output drive capability + 24 + 2 + + + ODRV11 + GPIOx pin 11 output drive capability + 22 + 2 + + + ODRV10 + GPIOx pin 10 output drive capability + 20 + 2 + + + ODRV9 + GPIOx pin 9 output drive capability + 18 + 2 + + + ODRV8 + GPIOx pin 8 output drive capability + 16 + 2 + + + ODRV7 + GPIOx pin 7 output drive capability + 14 + 2 + + + ODRV6 + GPIOx pin 6 output drive capability + 12 + 2 + + + ODRV5 + GPIOx pin 5 output drive capability + 10 + 2 + + + ODRV4 + GPIOx pin 4 output drive capability + 8 + 2 + + + ODRV3 + GPIOx pin 3 output drive capability + 6 + 2 + + + ODRV2 + GPIOx pin 2 output drive capability + 4 + 2 + + + ODRV1 + GPIOx pin 1 output drive capability + 2 + 2 + + + ODRV0 + GPIOx pin 0 output drive capability + 0 + 2 + + + + + PULL + PULL + GPIO pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PULL15 + GPIOx pin 15 pull configuration + 30 + 2 + + + PULL14 + GPIOx pin 14 pull configuration + 28 + 2 + + + PULL13 + GPIOx pin 13 pull configuration + 26 + 2 + + + PULL12 + GPIOx pin 12 pull configuration + 24 + 2 + + + PULL11 + GPIOx pin 11 pull configuration + 22 + 2 + + + PULL10 + GPIOx pin 10 pull configuration + 20 + 2 + + + PULL9 + GPIOx pin 9 pull configuration + 18 + 2 + + + PULL8 + GPIOx pin 8 pull configuration + 16 + 2 + + + PULL7 + GPIOx pin 7 pull configuration + 14 + 2 + + + PULL6 + GPIOx pin 6 pull configuration + 12 + 2 + + + PULL5 + GPIOx pin 5 pull configuration + 10 + 2 + + + PULL4 + GPIOx pin 4 pull configuration + 8 + 2 + + + PULL3 + GPIOx pin 3 pull configuration + 6 + 2 + + + PULL2 + GPIOx pin 2 pull configuration + 4 + 2 + + + PULL1 + GPIOx pin 1 pull configuration + 2 + 2 + + + PULL0 + GPIOx pin 0 pull configuration + 0 + 2 + + + + + IDT + IDT + GPIO input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + GPIO output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x18 + 0x20 + write-only + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + WPR + WPR + Port write protect + register + 0x1C + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + MUXL + MUXL + GPIO muxing function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + MUXL7 + GPIOx pin 7 muxing + 28 + 4 + + + MUXL6 + GPIOx pin 6 muxing + 24 + 4 + + + MUXL5 + GPIOx pin 5 muxing + 20 + 4 + + + MUXL4 + GPIOx pin 4 muxing + 16 + 4 + + + MUXL3 + GPIOx pin 3 muxing + 12 + 4 + + + MUXL2 + GPIOx pin 2 muxing + 8 + 4 + + + MUXL1 + GPIOx pin 1 muxing + 4 + 4 + + + MUXL0 + GPIOx pin 0 muxing + 0 + 4 + + + + + MUXH + MUXH + GPIO muxing function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + MUXH15 + GPIOx pin 15 muxing + 28 + 4 + + + MUXH14 + GPIOx pin 14 muxing + 24 + 4 + + + MUXH13 + GPIOx pin 13 muxing + 20 + 4 + + + MUXH12 + GPIOx pin 12 muxing + 16 + 4 + + + MUXH11 + GPIOx pin 11 muxing + 12 + 4 + + + MUXH10 + GPIOx pin 10 muxing + 8 + 4 + + + MUXH9 + GPIOx pin 9 muxing + 4 + 4 + + + MUXH8 + GPIOx pin 8 muxing + 0 + 4 + + + + + CLR + CLR + GPIO bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 1 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + HDRV + HDRV + Huge current driver + 0x3C + 0x20 + read-write + 0x00000000 + + + HDRV0 + Port x driver bit y + 0 + 1 + + + HDRV1 + Port x driver bit y + 1 + 1 + + + HDRV2 + Port x driver bit y + 2 + 1 + + + HDRV3 + Port x driver bit y + 3 + 1 + + + HDRV4 + Port x driver bit y + 4 + 1 + + + HDRV5 + Port x driver bit y + 5 + 1 + + + HDRV6 + Port x driver bit y + 6 + 1 + + + HDRV7 + Port x driver bit y + 7 + 1 + + + HDRV8 + Port x driver bit y + 8 + 1 + + + HDRV9 + Port x driver bit y + 9 + 1 + + + HDRV10 + Port x driver bit y + 10 + 1 + + + HDRV11 + Port x driver bit y + 11 + 1 + + + HDRV12 + Port x driver bit y + 12 + 1 + + + HDRV13 + Port x driver bit y + 13 + 1 + + + HDRV14 + Port x driver bit y + 14 + 1 + + + HDRV15 + Port x driver bit y + 15 + 1 + + + + + + + GPIOB + 0x48000400 + + + GPIOC + 0x48000800 + + + GPIOD + 0x48000C00 + + + GPIOF + 0x48001400 + + + EXINT + EXINT + EXINT + 0x40010400 + + 0x0 + 0x400 + registers + + + PVM + PVM interrupt connect to EXTI line16 + 1 + + + ERTC + ERTC interrupt connect to EXTI line17_19_20 + 2 + + + EXTINT1_0 + EXINT Line1_0 interrupt + 5 + + + EXTINT3_2 + EXINT Line3_2 interrupt + 6 + + + EXTINT15_4 + EXINT Line15_4 interrupt + 7 + + + OTGFS + OTGFS interrupt connect to EXTI Line18 + 31 + + + + INTEN + INTEN + Interrupt enable register (EXTINT_INTEN) + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + INTEN19 + Interrupt enable or disable on line 19 + 19 + 1 + + + INTEN20 + Interrupt enable or disable on line 20 + 20 + 1 + + + + + EVTEN + EVTEN + Event enable register (EXTINT_EVTEN) + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + EVTEN19 + Event enable or disable on line 19 + 19 + 1 + + + EVTEN20 + Event enable or disable on line 20 + 20 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register(EXTINT_POLCFG1) + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + RP19 + Rising polarity configuration bit of line 19 + 19 + 1 + + + RP20 + Rising polarity configuration bit of line 20 + 20 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register(EXTINT_POLCFG2) + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + FP19 + Falling polarity event configuration bit of line 19 + 19 + 1 + + + FP20 + Falling polarity event configuration bit of line 20 + 20 + 1 + + + + + SWTRG + SWTRG + Software triggle register + (EXTINT_SWIE) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + SWT19 + Software triggle on line 19 + 19 + 1 + + + SWT20 + Software triggle on line 20 + 20 + 1 + + + + + INTSTS + INTSTS + Interrupt status register (EXTINT_INTSTS) + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + LINE19 + Line 19 state bit + 19 + 1 + + + LINE20 + Line 20 state bit + 20 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 9 + + + DMA1_Channel3_2 + DMA1 Channel3_2 global interrupt + 10 + + + DMA1_Channel7_4 + DMA1 Channel7_4 global interrupt + 11 + + + + STS + STS + DMA interrupt status register (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA interrupt flag clear register (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_SRC_SEL0 + DMA_SRC_SEL0 + DMA channel source assignment register + 0xA0 + 0x20 + read-write + 0x00000000 + + + CH1_SRC + CH1 SRC select + 0 + 8 + + + CH2_SRC + CH2 SRC select + 8 + 8 + + + CH3_SRC + CH3 SRC select + 16 + 8 + + + CH4_SRC + CH4 SRC select + 24 + 8 + + + + + DMA_SRC_SEL1 + DMA_SRC_SEL1 + DMA channel source assignment register + 0xA4 + 0x20 + read-write + 0x00000000 + + + CH5_SRC + CH5 SRC select + 0 + 8 + + + CH6_SRC + CH6 SRC select + 8 + 8 + + + CH7_SRC + CH7 SRC select + 16 + 8 + + + DMA_FLEX_EN + DMA FLEX Enable + 24 + 1 + + + + + + + ERTC + Real-time clock + ERTC + 0x40002800 + + 0x0 + 0x400 + registers + + + + TIME + TIME + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + AMPM + AM/PM notation + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + DATE + DATE + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens + 20 + 4 + + + YU + Year units + 16 + 4 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + CTRL + CTRL + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + CALOEN + Calibration output enable + 23 + 1 + + + OUTSEL + Output source selection + 21 + 2 + + + OUTP + Output polarity + 20 + 1 + + + CALOSEL + Calibration output selection + 19 + 1 + + + BPR + Battery power domain data register + 18 + 1 + + + DEC1H + Decrease 1 hour + 17 + 1 + + + ADD1H + Add 1 hour + 16 + 1 + + + TSIEN + Timestamp interrupt enable + 15 + 1 + + + WATIEN + Wakeup timer interrupt enable + 14 + 1 + + + ALAIEN + Alarm A interrupt enable + 12 + 1 + + + TSEN + Timestamp enable + 11 + 1 + + + WATEN + Wakeup timer enable + 10 + 1 + + + ALAEN + Alarm A enable + 8 + 1 + + + HM + Hour mode + 6 + 1 + + + DREN + Date/time register direct read enable + 5 + 1 + + + RCDEN + Reference clock detection enable + 4 + 1 + + + TSEDG + Timestamp trigger edge + 3 + 1 + + + WATCLK + Wakeup timer clock selection + 0 + 3 + + + + + STS + STS + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALAWF + Alarm A register allows write flag + 0 + 1 + read-only + + + WATWF + Wakeup timer register allows write flag + 2 + 1 + read-only + + + TADJF + Time adjustment flag + 3 + 1 + read-write + + + INITF + Calendar initialization flag + 4 + 1 + read-only + + + UPDF + Calendar update flag + 5 + 1 + read-write + + + IMF + Enter initialization mode flag + 6 + 1 + read-only + + + IMEN + Initialization mode enable + 7 + 1 + read-write + + + ALAF + Alarm A flag + 8 + 1 + read-write + + + WATF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Timestamp flag + 11 + 1 + read-write + + + TSOF + Timestamp overflow flag + 12 + 1 + read-write + + + TP1F + Tamper detection 1 flag + 13 + 1 + read-write + + + CALUPDF + Calibration value update completed flag + 16 + 1 + read-only + + + + + DIV + DIV + Diveder register + 0x10 + 0x20 + read-write + 0x007F00FF + + + DIVA + Diveder A + 16 + 7 + + + DIVB + Diveder B + 0 + 15 + + + + + WAT + WAT + Wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + VAL + Wakeup timer reload value + 0 + 16 + + + + + ALA + ALA + Alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + WP + WP + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 8 + + + + + SBS + SBS + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + TADJ + TADJ + time adjust register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add 1 second + 31 + 1 + + + DECSBS + Decrease sub-second value + 0 + 15 + + + + + TSTM + TSTM + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + AMPM + AMPM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + TSDT + TSDT + timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + TSSBS + TSSBS + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + SCAL + SCAL + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + ADD + Add ERTC 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DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + + + TMR16 + General-purpose-timers + TIMER + 0x40014400 + + 0x0 + 0x400 + registers + + + TMR16 + TMR16 global interrupt + 21 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + C1CIOS + Channel 1 complementary idle output state + 9 + 1 + + + C1IOS + Channel 1 idle output state + 8 + 1 + + + DRS + DMA request source + 3 + 1 + + + CCFS + Channel control bit flash select + 2 + 1 + + + CBCTRL + Channel buffer control + 0 + 1 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + C1DEN + Channel 1 DMA request + enable + 9 + 1 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + BRKIE + Brake interrupt enable + 7 + 1 + + + HALLIEN + HALL interrupt enable + 5 + 1 + + + C1IEN + Channel 1 interrupt + enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + BRKIF + Brake interrupt flag + 7 + 1 + + + HALLIF + HALL interrupt flag + 5 + 1 + + + C4IF + Channel 4 interrupt flag + 4 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + BRKSWTR + Brake event triggered by software + 7 + 1 + + + HALLSWTR + HALL event triggered by software + 5 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C1OSEN + Channel 1 output switch enable + 7 + 1 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1CEN + Channel 1 complementary enable + 2 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + RPR + RPR + Repetition of period value + 0x30 + 0x20 + read-write + 0x0000 + + + RPR + Repetition of period value + 0 + 8 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + BRK + BRK + Brake register + 0x44 + 0x20 + read-write + 0x0000 + + + OEN + Output enable + 15 + 1 + + + AOEN + Automatic output enable + 14 + 1 + + + BRKV + Brake input validity + 13 + 1 + + + BRKEN + Brake enable + 12 + 1 + + + FCSOEN + Frozen channel status when + holistic output enable + 11 + 1 + + + FCSODIS + Frozen channel status when + holistic output disable + 10 + 1 + + + WPC + Write protected configuration + 8 + 2 + + + DTC + Dead-time configuration + 0 + 8 + + + + + DMACTRL + DMACTRL + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DTB + DMA transfer bytes + 8 + 5 + + + ADDR + DMA transfer address offset + 0 + 5 + + + + + DMADT + DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + + + TMR17 + 0x40014800 + + TMR17 + TMR17 global interrupt + 22 + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EVT + I2C1 event interrupt + 23 + + + I2C1_ERR + I2C1 error interrupt + 32 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + 0x00000000 + + + I2CEN + I2C peripheral enable + 0 + 1 + read-write + + + TDIEN + Transmit data interrupt enable + 1 + 1 + read-write + + + RDIEN + Receive data interrupt enable + 2 + 1 + read-write + + + ADDRIEN + Address match interrupt enable + 3 + 1 + read-write + + + ACKFAILIEN + Acknowledge fail interrupt enable + 4 + 1 + read-write + + + STOPIEN + Stop generation complete interrupt enable + 5 + 1 + read-write + + + TDCIEN + Transfer data complete interrupt enable + 6 + 1 + read-write + + + ERRIEN + Error interrupts enable + 7 + 1 + read-write + + + DFLT + Digital filter value + 8 + 4 + read-write + + + DMATEN + DMA Transmit data request enable + 14 + 1 + read-write + + + DMAREN + DMA receive data request enable + 15 + 1 + read-write + + + SCTRL + Slave receiving data control + 16 + 1 + read-write + + + STRETCH + Clock stretching mode + 17 + 1 + read-write + + + GCAEN + General call address enable + 19 + 1 + read-write + + + HADDREN + SMBus host address enable + 20 + 1 + read-write + + + DEVADDREN + SMBus device default address enable + 21 + 1 + read-write + + + SMBALERT + SMBus alert enable / pin set + 22 + 1 + read-write + + + PECEN + PEC calculation enable + 23 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECTEN + Request PEC transmission enable + 26 + 1 + + + ASTOPEN + Automatically send stop condition enable + 25 + 1 + + + RLDEN + Send data reload mode enable + 24 + 1 + + + CNT + Transmit data counter + 16 + 8 + + + NACKEN + Not acknowledge enable + 15 + 1 + + + GENSTOP + Generate stop condition + 14 + 1 + + + GENSTART + Generate start condition + 13 + 1 + + + READH10 + 10-bit address header read enable + 12 + 1 + + + ADDR10 + Host send 10-bit address mode enable + 11 + 1 + + + DIR + Master data transmission direction + 10 + 1 + + + SADDR + Slave address + 0 + 10 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + ADDR1 + Interface address + 0 + 10 + + + ADDR1MODE + Own Address mode + 10 + 1 + + + ADDR1EN + Own address 1 enable + 15 + 1 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2MASK + Own address 2-bit mask + 8 + 3 + + + ADDR2EN + Own address 2 enable + 15 + 1 + + + + + CLKCTRL + CLKCTRL + Clock contorl register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low level + 0 + 8 + + + SCLH + SCL high level + 8 + 8 + + + SDAD + SDA output delay + 16 + 4 + + + SCLD + SCL output delay + 20 + 4 + + + DIVH + High 4 bits of clock divider value + 24 + 4 + + + DIVL + Low 4 bits of clock divider value + 28 + 4 + + + + + TIMEOUT + TIMEOUT + Timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + TOTIME + Clock timeout detection time + 0 + 12 + + + TOMOED + Clock timeout detection mode + 12 + 1 + + + TOEN + Detect clock low/high timeout enable + 15 + 1 + + + EXTTIME + Cumulative clock low extend timeout value + 16 + 12 + + + EXTEN + Cumulative clock low extend timeout enable + 31 + 1 + + + + + STS + STS + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDR + Slave address matching value + 17 + 7 + read-only + + + SDIR + Slave data transmit direction + 16 + 1 + read-only + + + BUSYF + Bus busy + 15 + 1 + read-only + + + ALERTF + SMBus alert flag + 13 + 1 + read-only + + + TMOUT + SMBus timeout flag + 12 + 1 + read-only + + + PECERR + PEC receive error flag + 11 + 1 + read-only + + + OUF + Overflow or underflow flag + 10 + 1 + read-only + + + ARLOST + Arbitration lost flag + 9 + 1 + read-only + + + BUSERR + Bus error flag + 8 + 1 + read-only + + + TCRLD + Transmission is complete, waiting to load data + 7 + 1 + read-only + + + TDC + Transmit data complete flag + 6 + 1 + read-only + + + STOPF + Stop condition generation complete flag + 5 + 1 + read-only + + + ACKFAIL + Acknowledge failure flag + 4 + 1 + read-only + + + ADDRF + 0~7 bit address match flag + 3 + 1 + read-only + + + RDBF + Receive data buffer full flag + 2 + 1 + read-only + + + TDIS + Send interrupt status + 1 + 1 + read-write + + + TDBE + Transmit data buffer empty flag + 0 + 1 + read-write + + + + + CLR + CLR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTC + Clear SMBus alert flag + 13 + 1 + + + TMOUTC + Clear SMBus timeout flag + 12 + 1 + + + PECERRC + Clear PEC receive error flag + 11 + 1 + + + OUFC + Clear overload / underload flag + 10 + 1 + + + ARLOSTC + Clear arbitration lost flag + 9 + 1 + + + BUSERRC + Clear bus error flag + 8 + 1 + + + STOPC + Clear stop condition generation complete flag + 5 + 1 + + + ACKFAILC + Clear acknowledge failure flag + 4 + 1 + + + ADDRC + Clear 0~7 bit address match flag + 3 + 1 + + + + + PEC + PEC + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PECVAL + PEC value + 0 + 8 + + + + + RXDT + RXDT + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + DT + Receive data register + 0 + 8 + + + + + TXDT + TXDT + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + DT + Transmit data register + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 24 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1 + CAN1 global interrupt + 30 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RF0R + Receive FIFO 0 release + 5 + 1 + read-write + + + RF0OF + Receive FIFO 0 overflow flag + 4 + 1 + read-write + + + RF0FF + Receive FIFO 0 full flag + 3 + 1 + read-write + + + RF0MN + Receive FIFO 0 message num + 0 + 2 + read-only + + + + + RF1 + RF1 + Receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RF1R + Receive FIFO 1 release + 5 + 1 + read-write + + + RF1OF + Receive FIFO 1 overflow flag + 4 + 1 + read-write + + + RF1FF + Receive FIFO 1 full flag + 3 + 1 + read-write + + + RF1MN + Receive FIFO 1 message num + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + EDZIEN + Enter doze mode interrupt enable + 17 + 1 + + + QDZIEN + Quit doze mode interrupt enable + 16 + 1 + + + EOIEN + Error occur interrupt enable + 15 + 1 + + + ETRIEN + Error type record interrupt enable + 11 + 1 + + + BOIEN + Bus-off interrupt enable + 10 + 1 + + + EPIEN + Error passive interrupt enable + 9 + 1 + + + EAIEN + Error active interrupt enable + 8 + 1 + + + RF1OIEN + Receive FIFO 1 overflow interrupt enable + 6 + 1 + + + RF1FIEN + Receive FIFO 1 full interrupt enable + 5 + 1 + + + RF1MIEN + FIFO 1 receive message interrupt enable + 4 + 1 + + + RF0OIEN + Receive FIFO 0 overflow interrupt enable + 3 + 1 + + + RF0FIEN + Receive FIFO 0 full interrupt enable + 2 + 1 + + + RF0MIEN + FIFO 0 receive message interrupt enable + 1 + 1 + + + TCIEN + Transmission complete interrupt enable + 0 + 1 + + + + + ESTS + ESTS + Error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Transmit error counter + 16 + 8 + read-only + + + ETR + Error type record + 4 + 3 + read-write + + + BOF + Bus-off flag + 2 + 1 + read-only + + + EPF + Error passive flag + 1 + 1 + read-only + + + EAF + Error active flag + 0 + 1 + read-only + + + + + BTMG + BTMG + Bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOEN + Listen-Only mode + 31 + 1 + + + LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB2 + F1FB2 + Filter bank 1 filtrate bit register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + 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FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB1 + F13FB1 + Filter bank 13 filtrate bit filtrate bit register 1 + 0x2A8 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter 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0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 26 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 33 + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 27 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + DBN1 + high bit for Data bit num + 28 + 1 + + + TSDT + transmit start delay time + 21 + 5 + + + TCDT + transmit complete delay time + 16 + 5 + + + UEN + USART enable + 13 + 1 + + + DBN0 + Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + ID7_4 + bit 7-4 for usart identification + 28 + 4 + + + TRPSWAP + Transmit receive pin swap + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + ID + USART identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + DEP + DE polarity selection + 15 + 1 + + + RS485EN + RS485 enable + 14 + 1 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 28 + + + + USART3 + 0x40004800 + + USART3 + USART4_3 global interrupt + 29 + + + + USART4 + 0x40004C00 + + + ADC + Analog to digital converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC1 + ADC1 global interrupt + 12 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + OCDMAEN + DMA transfer enable of ordinary channels + 8 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + OVSP + OVSP + oversampling register + 0x80 + 0x20 + read-write + 0x00000000 + + + OOSRSEL + Ordinary oversampling recovery mode select + 10 + 1 + + + OOSTREN + Ordinary oversampling trigger mode enable + 9 + 1 + + + OSSSEL + Oversampling shift select + 5 + 4 + + + OSRSEL + Oversampling ratio select + 2 + 3 + + + POSEN + Preempted oversampling enable + 1 + 1 + + + OOSEN + Ordinary oversampling enable + 0 + 1 + + + + + + + SCFG + System configuration controller + SCFG + 0x40010000 + + 0x0 + 0x400 + registers + + + + CFG1 + CFG1 + configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MAP_SEL + Memory mapping selection + bits + 0 + 2 + + + PA11_12_RMP + PA11/PA12 pins remapping bit + 4 + 1 + + + IR_POL + Infrared output polarity selection + 5 + 1 + + + IR_SRC_SEL + Infrared modulation envelope signal source selection + 6 + 2 + + + PB14_UH + PB14 Ultra high sourcing/sinking strength + 16 + 1 + + + PB13_UH + PB13 Ultra high sourcing/sinking strength + 17 + 1 + + + PB9_UH + PB9 Ultra high sourcing/sinking strength + 18 + 1 + + + PB8_UH + PB8 Ultra high sourcing/sinking strength + 19 + 1 + + + + + EXTIC1 + EXTIC1 + external interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTINT3 + EXTINT 3 configuration bits + 12 + 4 + + + EXTINT2 + EXTINT 2 configuration bits + 8 + 4 + + + EXTINT1 + EXTINT 1 configuration bits + 4 + 4 + + + EXTINT0 + EXTINT 0 configuration bits + 0 + 4 + + + + + EXTIC2 + EXTIC2 + external interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTINT7 + EXTINT 7 configuration bits + 12 + 4 + + + EXTINT6 + EXTINT 6 configuration bits + 8 + 4 + + + EXTINT5 + EXTINT 5 configuration bits + 4 + 4 + + + EXTINT4 + EXTINT 4 configuration bits + 0 + 4 + + + + + EXTIC3 + EXTIC3 + external interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTINT11 + EXTINT 11 configuration bits + 12 + 4 + + + EXTINT10 + EXTINT 10 configuration bits + 8 + 4 + + + EXTINT9 + EXTINT 9 configuration bits + 4 + 4 + + + EXTINT8 + EXTINT 8 configuration bits + 0 + 4 + + + + + EXTIC4 + EXTIC4 + external interrupt configuration register 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTINT15 + EXTINT 15 configuration bits + 12 + 4 + + + EXTINT14 + EXTINT 14 configuration bits + 8 + 4 + + + EXTINT13 + EXTINT 13 configuration bits + 4 + 4 + + + EXTINT12 + EXTINT 12 configuration bits + 0 + 4 + + + + + CFG2 + CFG2 + configuration register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + PVM_LK + PVM lock enable + 2 + 1 + + + I2S_FD + I2S full duplex + 30 + 2 + + + + + + + DEBUG + Debug support + DEBUG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + DEBUG_IDCODE + 0x0 + 0x20 + read-only + 0x0 + + + PID + PID + 0 + 32 + + + + + CTRL + CTRL + DEBUG_CTRL + 0x4 + 0x20 + read-write + 0x0 + + + SLEEP_DEBUG + SLEEP_DEBUG + 0 + 1 + + + DEEPSLEEP_DEBUG + DEEPSLEEP_DEBUG + 1 + 1 + + + STANDBY_DEBUG + STANDBY_DEBUG + 2 + 1 + + + CAN_PAUSE + CAN_PAUSE + 3 + 1 + + + WDT_PAUSE + WDT_PAUSE + 8 + 1 + + + WWDT_PAUSE + WWDT_PAUSE + 9 + 1 + + + TMR1_PAUSE + TMR1_PAUSE + 10 + 1 + + + TMR2_PAUSE + TMR2_PAUSE + 11 + 1 + + + TMR3_PAUSE + TMR3_PAUSE + 12 + 1 + + + ERTC_PAUSE + ERTC_PAUSE + 14 + 1 + + + I2C1_SMBUS_TIMEOUT + I2C1_SMBUS_TIMEOUT + 15 + 1 + + + I2C2_SMBUS_TIMEOUT + I2C2_SMBUS_TIMEOUT + 16 + 1 + + + TMR6_PAUSE + TMR6_PAUSE + 19 + 1 + + + TMR7_PAUSE + TMR7_PAUSE + 20 + 1 + + + ERTC_512_PAUSE + ERTC_512_PAUSE + 21 + 1 + + + TMR15_PAUSE + TMR15_PAUSE + 22 + 1 + + + TMR16_PAUSE + TMR16_PAUSE + 23 + 1 + + + TMR17_PAUSE + TMR17_PAUSE + 24 + 1 + + + TMR13_PAUSE + TMR13_PAUSE + 26 + 1 + + + TMR14_PAUSE + TMR14_PAUSE + 27 + 1 + + + + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DT + DT + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DT + Data Register + 0 + 32 + + + + + CDT + CDT + Common data register + 0x4 + 0x20 + read-write + 0x00000000 + + + CDT + Common Data + 0 + 1 + + + + + CTRL + CTRL + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RST + Reset bit + 0 + 1 + + + REVID + Reverse input data + 5 + 2 + + + REVOD + Reverse output data + 7 + 1 + + + + + IDT + IDT + Initial data register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + IDT + Initial Data + 0 + 32 + + + + + + + FLASH + Flash memory controler + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 3 + + + + PSR + PSR + Performance selection register + 0x0 + 0x20 + 0x00000030 + + + WTCYC + Wait cycle + 0 + 3 + read-write + + + HFCYC_EN + Half cycle acceleration access enable + 3 + 1 + read-write + + + PFT_EN + Prefetch enable + 4 + 1 + read-write + + + PFT_ENF + Prefetch enabled flag + 5 + 1 + read-only + + + PFT_EN2 + Prefetch enable 2 + 6 + 1 + read-write + + + PFT_ENF2 + Prefetch enabled flag 2 + 7 + 1 + read-only + + + PFT_LAT_DIS + Prefetch latency disable + 8 + 1 + read-write + + + + + UNLOCK + UNLOCK + Unlock register + 0x4 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + USD_UNLOCK + USD_UNLOCK + USD unlock register + 0x8 + 0x20 + write-only + 0x00000000 + + + USD_UKVAL + User system data Unlock key value + 0 + 32 + + + + + STS + STS + Status register + 0xC + 0x20 + 0x00000000 + + + ODF + Operate done flag + 5 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + PRGMERR + program error + 2 + 1 + read-write + + + OBF + Operate busy flag + 0 + 1 + read-only + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00020080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + USDPRGM + User system data program + 4 + 1 + + + USDERS + User system data erase + 5 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + USDULKS + User system data unlock success + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + LPMEN + Low power mode enable + 17 + 1 + + + + + ADDR + ADDR + Address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + USD + USD + User system data register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + USDERR + User system data error + 0 + 1 + + + FAP + FLASH access protection + 1 + 1 + + + nWDT_ATO_EN + WDT auto enable + 2 + 1 + + + nDEPSLP_RST + Deepsleep reset + 3 + 1 + + + nSTDBY_RST + Standby reset + 4 + 1 + + + nBOOT1 + boot1 + 6 + 1 + + + nDEPSLP_WDT + Deepsleep wdt stop count + 7 + 1 + + + nSTDBY_WDT + Standby wdt stop count + 8 + 1 + + + USER_D0 + User data 0 + 10 + 8 + + + USER_D1 + User data 1 + 18 + 8 + + + FAP_HL + FAP high level + 26 + 1 + + + + + EPPS + EPPS + Erase/program protection status register + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + SLIB_STS0 + SLIB_STS0 + sLib status 0 register + 0x74 + 0x20 + 0x00000000 + + + BTM_AP_ENF + Boot memory store application code enabled flag + 0 + 1 + + + EM_SLIB_ENF + Extension memory sLib enabled flag + 2 + 1 + + + SLIB_ENF + sLib enabled flag + 3 + 1 + + + EM_SLIB_INST_SS + Extension memory sLib instruction start sector + 16 + 8 + + + + + SLIB_STS1 + SLIB_STS1 + sLib status 1 register + 0x78 + 0x20 + 0x00000000 + + + SLIB_SS + sLib start sector + 0 + 11 + + + SLIB_INST_SS + sLib instruction start sector + 11 + 11 + + + SLIB_ES + sLib end sector + 22 + 10 + + + + + SLIB_PWD_CLR + SLIB_PWD_CLR + SLIB password clear register + 0x7C + 0x20 + 0x00000000 + write-only + + + SLIB_PCLR_VAL + sLib password clear value + 0 + 32 + + + + + SLIB_MISC_STS + SLIB_MISC_STS + sLib misc status register + 0x80 + 0x20 + 0x01000000 + + + SLIB_PWD_ERR + sLib password error + 0 + 1 + read-only + + + SLIB_PWD_OK + sLib password ok + 1 + 1 + read-only + + + SLIB_ULKF + sLib unlock flag + 2 + 1 + read-only + + + + + CRC_ADDR + CRC_ADDR + Flash CRC data start address register + 0x84 + 0x20 + write-only + 0x00000000 + + + CRC_ADDR + CRC address + 0 + 32 + + + + + CRC_CTRL + CRC_CTRL + Flash CRC controll register + 0x88 + 0x20 + 0x00000000 + + + CRC_SN + CRC sector numbler + 0 + 16 + read-write + + + CRC_STRT + CRC start + 16 + 1 + write-only + + + + + CRC_CHKR + CRC_CHKR + FLASH CRC check result register + 0x8C + 0x20 + read-only + 0x00000000 + + + FCRC_OUT + CRC32 verification result of flash user code or SLIB code + 0 + 32 + + + + + SLIB_SET_PWD + SLIB_SET_PWD + sLib password setting register + 0x160 + 0x20 + write-only + 0x00000000 + + + SLIB_PSET_VAL + sLib password setting val + 0 + 32 + + + + + SLIB_SET_RANGE + SLIB_SET_RANGE + Configure sLib range register + 0x164 + 0x20 + write-only + 0x00000000 + + + SLIB_SS_SET + sLib start sector setting + 0 + 11 + + + SLIB_ISS_SET + sLib instruction start sector setting + 11 + 11 + + + SLIB_ES_SET + sLib end sector setting + 22 + 10 + + + + + EM_SLIB_SET + EM_SLIB_SET + Extension momery slib set register + 0x168 + 0x20 + write-only + 0x00000000 + + + EM_SLIB_SET + Extension memory sLib setting + 0 + 16 + + + EM_SLIB_ISS_SET + Extension memory sLib instruction start sector setting + 16 + 8 + + + + + BTM_MODE_SET + BTM_MODE_SET + Boot memory mode setting register + 0x16C + 0x20 + write-only + 0x00000000 + + + BTM_MODE_SET + Boot memory mode setting + 0 + 8 + + + + + SLIB_UNLOCK + SLIB_UNLOCK + sLib unlock register + 0x170 + 0x20 + write-only + 0x00000000 + + + SLIB_UKVAL + sLib unlock key value + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + USB_OTG1_GLOBAL + USB on-the-go full speed + USB_OTG1 + 0x50000000 + + 0x0 + 0x400 + registers + + + OTGFS1 + USB On The Go FS global + interrupt + 67 + + + + GOTGCTL + GOTGCTL + OTGFS control and status register + (OTGFS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGFS interrupt register + (OTGFS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGFS AHB configuration register + (OTGFS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGFS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + FS timeout calibration + 0 + 3 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGFS reset register + (OTGFS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGFS core interrupt register + (OTGFS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-write + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGFS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGFS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGFS Receive FIFO size register + (OTGFS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGFS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGFS non-periodic transmit FIFO/queue + status register (OTGFS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGFS general core configuration register + (OTGFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + LP_MODE + Low power mode + 17 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGFS Host periodic transmit FIFO size + register (OTGFS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO5 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF6) + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO6 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF7) + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO7 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTG1_HOST + USB on the go full speed + USB_OTG1 + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGFS host configuration register + (OTGFS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGFS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGFS host frame number/frame time + remaining register (OTGFS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGFS_Host periodic transmit FIFO/queue + status register (OTGFS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGFS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGFS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGFS host port control and status register + (OTGFS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGFS host channel-0 characteristics + register (OTGFS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGFS host channel-1 characteristics + register (OTGFS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGFS host channel-2 characteristics + register (OTGFS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGFS host channel-3 characteristics + register (OTGFS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGFS host channel-4 characteristics + register (OTGFS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGFS host channel-5 characteristics + register (OTGFS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGFS host channel-6 characteristics + register (OTGFS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTGFS host channel-8 characteristics + register (OTGFS_HCCHAR8) + 0x200 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTGFS host channel-9 characteristics + register (OTGFS_HCCHAR9) + 0x220 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTGFS host channel-10 characteristics + register (OTGFS_HCCHAR10) + 0x240 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR11) + 0x260 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTGFS host channel-12 characteristics + register (OTGFS_HCCHAR12) + 0x280 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTGFS host channel-13 characteristics + register (OTGFS_HCCHAR13) + 0x2A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTGFS host channel-14 characteristics + register (OTGFS_HCCHAR14) + 0x2C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTGFS host channel-15 characteristics + register (OTGFS_HCCHAR15) + 0x2E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGFS host channel-0 interrupt register + (OTGFS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGFS host channel-2 interrupt register + (OTGFS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGFS host channel-3 interrupt register + (OTGFS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGFS host channel-4 interrupt register + (OTGFS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGFS host channel-5 interrupt register + (OTGFS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGFS host channel-6 interrupt register + (OTGFS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGFS host channel-7 interrupt register + (OTGFS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT8 + HCINT8 + OTGFS host channel-8 interrupt register + (OTGFS_HCINT8) + 0x208 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT9 + HCINT9 + OTGFS host channel-9 interrupt register + (OTGFS_HCINT9) + 0x228 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT10 + HCINT10 + OTGFS host channel-10 interrupt register + (OTGFS_HCINT10) + 0x248 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT11 + HCINT11 + OTGFS host channel-11 interrupt register + (OTGFS_HCINT11) + 0x268 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT12 + HCINT12 + OTGFS host channel-12 interrupt register + (OTGFS_HCINT12) + 0x288 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT13 + HCINT13 + OTGFS host channel-13 interrupt register + (OTGFS_HCINT13) + 0x2A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT14 + HCINT14 + OTGFS host channel-14 interrupt register + (OTGFS_HCINT14) + 0x2C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT15 + HCINT15 + OTGFS host channel-15 interrupt register + (OTGFS_HCINT15) + 0x2E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGFS host channel-0 mask register + (OTGFS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGFS host channel-1 mask register + (OTGFS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGFS host channel-2 mask register + (OTGFS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGFS host channel-3 mask register + (OTGFS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGFS host channel-4 mask register + (OTGFS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGFS host channel-5 mask register + (OTGFS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGFS host channel-6 mask register + (OTGFS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGFS host channel-7 mask register + (OTGFS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + OTGFS host channel-8 mask register + (OTGFS_HCINTMSK8) + 0x20C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + OTGFS host channel-9 mask register + (OTGFS_HCINTMSK9) + 0x22C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + OTGFS host channel-10 mask register + (OTGFS_HCINTMSK10) + 0x24C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + OTGFS host channel-11 mask register + (OTGFS_HCINTMSK11) + 0x26C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + OTGFS host channel-12 mask register + (OTGFS_HCINTMSK12) + 0x28C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + OTGFS host channel-13 mask register + (OTGFS_HCINTMSK13) + 0x2AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + OTGFS host channel-14 mask register + (OTGFS_HCINTMSK14) + 0x2CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + OTGFS host channel-15 mask register + (OTGFS_HCINTMSK15) + 0x2EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGFS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ1 + HCTSIZ1 + OTGFS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ2 + HCTSIZ2 + OTGFS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ3 + HCTSIZ3 + OTGFS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ4 + HCTSIZ4 + OTGFS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ5 + HCTSIZ5 + OTGFS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ6 + HCTSIZ6 + OTGFS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ7 + HCTSIZ7 + OTGFS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ8 + HCTSIZ8 + OTGFS host channel-8 transfer size + register + 0x210 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ9 + HCTSIZ9 + OTGFS host channel-9 transfer size + register + 0x230 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ10 + HCTSIZ10 + OTGFS host channel-10 transfer size + register + 0x250 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ11 + HCTSIZ11 + OTGFS host channel-11 transfer size + register + 0x270 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ12 + HCTSIZ12 + OTGFS host channel-12 transfer size + register + 0x290 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ13 + HCTSIZ13 + OTGFS host channel-13 transfer size + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ14 + HCTSIZ14 + OTGFS host channel-14 transfer size + register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ15 + HCTSIZ15 + OTGFS host channel-15 transfer size + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + + + USB_OTG1_DEVICE + USB on the go full speed + USB_OTG1 + 0x50000800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGFS device configuration register + (OTGFS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGFS device control register + (OTGFS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTGFS device IN endpoint common interrupt + mask register (OTGFS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTGFS device OUT endpoint common interrupt + mask register (OTGFS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + + + DAINT + DAINT + OTGFS device all endpoints interrupt + register (OTGFS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGFS all endpoints interrupt mask register + (OTGFS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGFS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEPCTL0 + DIEPCTL0 + OTGFS device control IN endpoint 0 control + register (OTGFS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-only + + + EPTENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTGFS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGFS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGFS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL4 + DIEPCTL4 + OTGFS device IN endpoint-4 control + register + 0x180 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL5 + DIEPCTL5 + OTGFS device IN endpoint-5 control + register + 0x1A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL6 + DIEPCTL6 + OTGFS device IN endpoint-6 control + register + 0x1C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL7 + DIEPCTL7 + OTGFS device IN endpoint-7 control + register + 0x1E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGFS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGFS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGFS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGFS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL4 + DOEPCTL4 + OTGFS device OUT endpoint-4 control + register + 0x380 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL5 + DOEPCTL5 + OTGFS device OUT endpoint-5 control + register + 0x3A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL6 + DOEPCTL6 + OTGFS device OUT endpoint-6 control + register + 0x3C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL7 + DOEPCTL7 + OTGFS device OUT endpoint-7 control + register + 0x3E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGFS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT1 + DIEPINT1 + OTGFS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT2 + DIEPINT2 + OTGFS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT3 + DIEPINT3 + OTGFS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT4 + DIEPINT4 + OTGFS device IN endpoint-4 interrupt + register + 0x188 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT5 + DIEPINT5 + OTGFS device IN endpoint-5 interrupt + register + 0x1A8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT6 + DIEPINT6 + OTGFS device IN endpoint-6 interrupt + register + 0x1C8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT7 + DIEPINT7 + OTGFS device IN endpoint-7 interrupt + register + 0x1E8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DOEPINT0 + DOEPINT0 + OTGFS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT1 + DOEPINT1 + OTGFS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT2 + DOEPINT2 + OTGFS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT3 + DOEPINT3 + OTGFS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT4 + DOEPINT4 + OTGFS device OUT endpoint-4 interrupt + register + 0x388 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT5 + DOEPINT5 + OTGFS device OUT endpoint-5 interrupt + register + 0x3A8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT6 + DOEPINT6 + OTGFS device OUT endpoint-6 interrupt + register + 0x3C8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT7 + DOEPINT7 + OTGFS device OUT endpoint-7 interrupt + register + 0x3E8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGFS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGFS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGFS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGFS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ4 + DIEPTSIZ4 + OTG device IN endpoint-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ5 + DIEPTSIZ5 + OTG device IN endpoint-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ6 + DIEPTSIZ6 + OTG device IN endpoint-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ7 + DIEPTSIZ7 + OTG device IN endpoint-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + OTGFS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGFS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGFS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGFS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS4 + DTXFSTS4 + OTGFS device IN endpoint-4 transmit FIFO + status register + 0x198 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS5 + DTXFSTS5 + OTGFS device IN endpoint-5 transmit FIFO + status register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS6 + DTXFSTS6 + OTGFS device IN endpoint-6 transmit FIFO + status register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS7 + DTXFSTS7 + OTGFS device IN endpoint-7 transmit FIFO + status register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGFS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGFS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGFS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + OTGFS device OUT endpoint-4 transfer size + register + 0x390 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + OTGFS device OUT endpoint-5 transfer size + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + OTGFS device OUT endpoint-6 transfer size + register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + OTGFS device OUT endpoint-7 transfer size + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + + + USB_OTG1_PWRCLK + USB on the go full speed + USB_OTG1 + 0x50000E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGFS power and clock gating control + register (OTGFS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + diff --git a/hw/bsp/at32f425/boards/AT_START_F425/board.h b/hw/bsp/at32f425/boards/AT_START_F425/board.h new file mode 100644 index 000000000..ddfe1f71b --- /dev/null +++ b/hw/bsp/at32f425/boards/AT_START_F425/board.h @@ -0,0 +1,90 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define USB_VBUS_IGNORE + +// LED +#define LED_PORT GPIOC +#define LED_PIN GPIO_PINS_2 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +// Usart +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK +#define PRINT_UART_TX_PIN_SOURCE GPIO_PINS_SOURCE9 +#define PRINT_UART_TX_PIN_MUX_NUM GPIO_MUX_1 + +//USB +#define USB_ID 0 +#define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK +#define OTG_IRQ OTGFS1_IRQn +#define OTG_IRQ_HANDLER OTGFS1_IRQHandler +#define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn +#define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler +#define OTG_WKUP_EXINT_LINE EXINT_LINE_18 +#define OTG_PIN_GPIO GPIOA +#define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_DP GPIO_PINS_12 +#define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE12 +#define OTG_PIN_DM GPIO_PINS_11 +#define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE11 +#define OTG_PIN_VBUS GPIO_PINS_9 +#define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 +#define OTG_PIN_ID GPIO_PINS_10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_SOF_GPIO GPIOA +#define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_SOF GPIO_PINS_8 +#define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 +#define OTG_PIN_MUX GPIO_MUX_3 + +static inline void board_vbus_sense_init(void) +{ + *(int*)(0x50000038) |= (1<<21); +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f425/boards/AT_START_F425/board.mk b/hw/bsp/at32f425/boards/AT_START_F425/board.mk new file mode 100644 index 000000000..3fa74d95a --- /dev/null +++ b/hw/bsp/at32f425/boards/AT_START_F425/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F425x8_FLASH.ld + +CFLAGS += \ + -DAT32F425R8T7 diff --git a/hw/bsp/at32f425/family.c b/hw/bsp/at32f425/family.c new file mode 100644 index 000000000..e0b66730a --- /dev/null +++ b/hw/bsp/at32f425/family.c @@ -0,0 +1,298 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f425_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void uart_print_init(uint32_t baudrate); +void usb_clock48m_select(usb_clk48_s clk_s); +void led_and_button_init(void); + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTGFS1_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGFS1_WKUP_IRQHandler(void) +{ + tusb_int_handler(0, true); +} + +void board_init(void) +{ + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* config system clock */ + system_clock_config(); + + /* enable usb clock */ + crm_periph_clock_enable(OTG_CLOCK, TRUE); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HEXT); + + /* vbus ignore */ + board_vbus_sense_init(); + + /* configure systick */ + systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); + SysTick_Config(SystemCoreClock / 1000); + #if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + #endif + + /* otgfs use vbus pin */ + #ifndef USB_VBUS_IGNORE + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); + #endif + + /* config led and key */ + led_and_button_init(); + + /* config usart printf */ + uart_print_init(115200); + printf("usart printf config success!\r\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + /* usb divider reset */ + crm_usb_div_reset(); + + switch(system_core_clock) + { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_1); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_1_5); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + default: + break; + } + } +} + +void led_and_button_init(void) +{ + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); +} + +/** + * @brief initialize uart + * @param baudrate: uart baudrate + * @retval none + */ +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + gpio_pin_mux_config(PRINT_UART_TX_GPIO, PRINT_UART_TX_PIN_SOURCE, PRINT_UART_TX_PIN_MUX_NUM); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +// Get characters from UART. Return number of read bytes +int board_uart_read(uint8_t *buf, int len) +{ + (void) buf; + (void) len; + return 0; +} + +// Send characters to UART. Return number of sent bytes +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + +void board_led_write(bool state) +{ + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) +{ + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + + +#if CFG_TUSB_OS == OPT_OS_NONE + + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + + uint32_t board_millis(void) + { + return system_ticks; + } + + void SVC_Handler(void) + { + } + + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) +{ + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/at32f425/family.mk b/hw/bsp/at32f425/family.mk new file mode 100644 index 000000000..d1bcdfda3 --- /dev/null +++ b/hw/bsp/at32f425/family.mk @@ -0,0 +1,43 @@ +# Submodules +AT32F425_SDK = hw/mcu/artery/at32f425 +DEPS_SUBMODULES += $(AT32F425_SDK) + +# AT32 SDK path +AT32F425_SDK_SRC = $(AT32F425_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m3 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F425 \ + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(AT32F425_SDK_SRC)/drivers/src/at32f425_gpio.c \ + $(AT32F425_SDK_SRC)/drivers/src/at32f425_misc.c \ + $(AT32F425_SDK_SRC)/drivers/src/at32f425_usart.c \ + $(AT32F425_SDK_SRC)/drivers/src/at32f425_crm.c \ + $(AT32F425_SDK_SRC)/cmsis/cm4/device_support/system_at32f425.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F425_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F425_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F425_SDK_SRC)/cmsis/cm4/device_support + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f425.s + +# For freeRTOS port source +#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4 + +flash: flash-atlink diff --git a/hw/bsp/at32f425/startup_at32f425.s b/hw/bsp/at32f425/startup_at32f425.s new file mode 100644 index 000000000..38127c759 --- /dev/null +++ b/hw/bsp/at32f425/startup_at32f425.s @@ -0,0 +1,309 @@ +/** + ****************************************************************************** + * @file startup_at32f425.s + * @brief at32f425xx devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word ERTC_IRQHandler /* ERTC */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT1_0_IRQHandler /* EXINT Line 1 & 0 */ + .word EXINT3_2_IRQHandler /* EXINT Line 3 & 2 */ + .word EXINT15_4_IRQHandler /* EXINT Line 15 ~ 4 */ + .word ACC_IRQHandler /* ACC */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel3_2_IRQHandler /* DMA1 Channel 3 & 2 */ + .word DMA1_Channel7_4_IRQHandler /* DMA1 Channel 7 & 4 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TMR1_BRK_OVF_TRG_HALL_IRQHandler /* TMR1 brake overflow trigger and hall */ + .word TMR1_CH_IRQHandler /* TMR1 channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR6_GLOBAL_IRQHandler /* TMR6 */ + .word TMR7_GLOBAL_IRQHandler /* TMR7 */ + .word TMR14_GLOBAL_IRQHandler /* TMR14 */ + .word TMR15_GLOBAL_IRQHandler /* TMR15 */ + .word TMR16_GLOBAL_IRQHandler /* TMR16 */ + .word TMR17_GLOBAL_IRQHandler /* TMR17 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART4_3_IRQHandler /* USART3 & USART4 */ + .word CAN1_IRQHandler /* CAN1 */ + .word OTGFS1_IRQHandler /* OTGFS1 */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word SPI3_IRQHandler /* SPI3 */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word TMR13_GLOBAL_IRQHandler /* TMR13 */ +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak ERTC_IRQHandler + .thumb_set ERTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT1_0_IRQHandler + .thumb_set EXINT1_0_IRQHandler,Default_Handler + + .weak EXINT3_2_IRQHandler + .thumb_set EXINT3_2_IRQHandler,Default_Handler + + .weak EXINT15_4_IRQHandler + .thumb_set EXINT15_4_IRQHandler,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel3_2_IRQHandler + .thumb_set DMA1_Channel3_2_IRQHandler,Default_Handler + + .weak DMA1_Channel7_4_IRQHandler + .thumb_set DMA1_Channel7_4_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TMR1_BRK_OVF_TRG_HALL_IRQHandler + .thumb_set TMR1_BRK_OVF_TRG_HALL_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR6_GLOBAL_IRQHandler + .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler + + .weak TMR7_GLOBAL_IRQHandler + .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler + + .weak TMR14_GLOBAL_IRQHandler + .thumb_set TMR14_GLOBAL_IRQHandler,Default_Handler + + .weak TMR15_GLOBAL_IRQHandler + .thumb_set TMR15_GLOBAL_IRQHandler,Default_Handler + + .weak TMR16_GLOBAL_IRQHandler + .thumb_set TMR16_GLOBAL_IRQHandler,Default_Handler + + .weak TMR17_GLOBAL_IRQHandler + .thumb_set TMR17_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART4_3_IRQHandler + .thumb_set USART4_3_IRQHandler,Default_Handler + + .weak CAN1_IRQHandler + .thumb_set CAN1_IRQHandler,Default_Handler + + .weak OTGFS1_IRQHandler + .thumb_set OTGFS1_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak TMR13_GLOBAL_IRQHandler + .thumb_set TMR13_GLOBAL_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..a42e4d414 --- /dev/null +++ b/hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f435_437.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd b/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd new file mode 100644 index 000000000..4f34af9d3 --- /dev/null +++ b/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd @@ -0,0 +1,58291 @@ + + + + + + + + Keil + ArteryTek + AT32F437xx_v2 + AT32F437 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 288MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + XMC + Flexible static memory controller + XMC + 0xA0000000 + + 0x0 + 0x1000 + registers + + + XMC + XMC global interrupt + 48 + + + + BK1CTRL1 + BK1CTRL1 + SRAM/NOR-Flash chip-select control register + 1 + 0x0 + 0x20 + read-write + 0x000030DB + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG1 + BK1TMG1 + SRAM/NOR-Flash chip-select timing register + 1 + 0x4 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1CTRL2 + BK1CTRL2 + SRAM/NOR-Flash chip-select control register + 2 + 0x8 + 0x20 + read-write + 0x000030D2 + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG2 + BK1TMG2 + SRAM/NOR-Flash chip-select timing register + 2 + 0xC + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1CTRL3 + BK1CTRL3 + SRAM/NOR-Flash chip-select control register + 3 + 0x10 + 0x20 + read-write + 0x000030D2 + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG3 + BK1TMG3 + SRAM/NOR-Flash chip-select timing register + 3 + 0x14 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1CTRL4 + BK1CTRL4 + SRAM/NOR-Flash chip-select control register + 4 + 0x18 + 0x20 + read-write + 0x000030D2 + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG4 + BK1TMG4 + SRAM/NOR-Flash chip-select timing register + 4 + 0x1C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK2CTRL + BK2CTRL + PC Card/NAND Flash control register + 2 + 0x60 + 0x20 + read-write + 0x00000018 + + + ECCPGS + ECC page size + 17 + 3 + + + TAR + ALE to RE delay + 13 + 4 + + + TCR + CLE to RE delay + 9 + 4 + + + ECCEN + ECC enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 3 + 1 + + + EN + Memory bank enable + 2 + 1 + + + NWEN + Wait feature enable + 1 + 1 + + + + + BK2IS + BK2IS + FIFO status and interrupt register + 2 + 0x64 + 0x20 + 0x00000040 + + + FIFOE + FIFO empty + 6 + 1 + read-only + + + FEIEN + Falling edge interrupt enable + 5 + 1 + read-write + + + HLIEN + High-level interrupt enable + 4 + 1 + read-write + + + REIEN + Rising edge interrupt enable + 3 + 1 + read-write + + + FES + Falling edge status + 2 + 1 + read-write + + + HLS + High-level status + 1 + 1 + read-write + + + RES + Rising edge capture status + 0 + 1 + read-write + + + + + BK2TMGRG + BK2TMGRG + Regular memory space timing register + 2 + 0x68 + 0x20 + read-write + 0xFCFCFCFC + + + RGDHIZT + Regular memory databus High resistance time + 24 + 8 + + + RGHT + Regular memory hold time + 16 + 8 + + + RGWT + Regular memory wait time + 8 + 8 + + + RGST + Regular memory setup time + 0 + 8 + + + + + BK2TMGSP + BK2TMGSP + special memory space timing register + 2 + 0x6C + 0x20 + read-write + 0xFCFCFCFC + + + SPDHIZT + special memory databus High resistance time + 24 + 8 + + + SPHT + special memory hold time + 16 + 8 + + + SPWT + special memory wait time + 8 + 8 + + + SPST + special memory setup time + 0 + 8 + + + + + BK2ECC + BK2ECC + ECC result register 2 + 0x74 + 0x20 + read-write + 0x00000000 + + + ECC + ECC result + 0 + 32 + + + + + BK3CTRL + BK3CTRL + PC Card/NAND Flash control register + 3 + 0x80 + 0x20 + read-write + 0x00000018 + + + ECCPGS + ECC page size + 17 + 3 + + + TAR + ALE to RE delay + 13 + 4 + + + TCR + CLE to RE delay + 9 + 4 + + + ECCEN + ECC enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 3 + 1 + + + EN + Memory bank enable + 2 + 1 + + + NWEN + Wait feature enable + 1 + 1 + + + + + BK3IS + BK3IS + FIFO status and interrupt register + 3 + 0x84 + 0x20 + 0x00000040 + + + FIFOE + FIFO empty + 6 + 1 + read-only + + + FEIEN + Falling edge interrupt enable + 5 + 1 + read-write + + + HLIEN + High-level interrupt enable + 4 + 1 + read-write + + + REIEN + Rising edge interrupt enable + 3 + 1 + read-write + + + FES + Falling edge status + 2 + 1 + read-write + + + HLS + High-level status + 1 + 1 + read-write + + + RES + Rising edge capture status + 0 + 1 + read-write + + + + + BK3TMGRG + BK3TMGRG + Regular memory space timing register + 3 + 0x88 + 0x20 + read-write + 0xFCFCFCFC + + + RGDHIZT + Regular memory databus High resistance time + 24 + 8 + + + RGHT + Regular memory hold time + 16 + 8 + + + RGWT + Regular memory wait time + 8 + 8 + + + RGST + Regular memory setup time + 0 + 8 + + + + + BK3TMGSP + BK3TMGSP + special memory space timing register + 3 + 0x8C + 0x20 + read-write + 0xFCFCFCFC + + + SPDHIZT + special memory databus High resistance time + 24 + 8 + + + SPHT + special memory hold time + 16 + 8 + + + SPWT + special memory wait time + 8 + 8 + + + SPST + special memory setup time + 0 + 8 + + + + + BK3ECC + BK3ECC + ECC result register 3 + 0x94 + 0x20 + read-write + 0x00000000 + + + ECC + ECC result + 0 + 32 + + + + + BK4CTRL + BK4CTRL + PC Card/NAND Flash control register + 4 + 0xA0 + 0x20 + read-write + 0x00000018 + + + EN + Memory bank enable + 2 + 1 + + + NWEN + Wait feature enable + 1 + 1 + + + + + BK4IS + BK4IS + FIFO status and interrupt register + 4 + 0xA4 + 0x20 + 0x00000040 + + + FIFOE + FIFO empty + 6 + 1 + read-only + + + FEIEN + Falling edge interrupt enable + 5 + 1 + read-write + + + HLIEN + High-level interrupt enable + 4 + 1 + read-write + + + REIEN + Rising edge interrupt enable + 3 + 1 + read-write + + + FES + Falling edge status + 2 + 1 + read-write + + + HLS + High-level status + 1 + 1 + read-write + + + RES + Rising edge capture status + 0 + 1 + read-write + + + + + BK4TMGCM + BK4TMGCM + Regular memory space timing register + 4 + 0xA8 + 0x20 + read-write + 0xFCFCFCFC + + + CMDHIZT + Regular memory databus High resistance time + 24 + 8 + + + CMHT + Regular memory hold time + 16 + 8 + + + CMWT + Regular memory wait time + 8 + 8 + + + CMST + Regular memory setup time + 0 + 8 + + + + + BK4TMGAT + BK4TMGAT + special memory space timing register + 4 + 0xAC + 0x20 + read-write + 0xFCFCFCFC + + + ATDHIZT + special memory databus High resistance time + 24 + 8 + + + ATHT + special memory hold time + 16 + 8 + + + ATWT + special memory wait time + 8 + 8 + + + ATST + special memory setup time + 0 + 8 + + + + + BK4TMGIO + BK4TMGIO + I/O space timing register 4 + 0xB0 + 0x20 + read-write + 0xFCFCFCFC + + + IODHIZT + WRSTP + 24 + 8 + + + IOHT + HLD + 16 + 8 + + + IOWT + OP + 8 + 8 + + + IOST + STP + 0 + 8 + + + + + BK1TMGWR1 + BK1TMGWR1 + SRAM/NOR-Flash write timing registers + 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR2 + BK1TMGWR2 + SRAM/NOR-Flash write timing registers + 2 + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR3 + BK1TMGWR3 + SRAM/NOR-Flash write timing registers + 3 + 0x114 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR4 + BK1TMGWR4 + SRAM/NOR-Flash write timing registers + 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + CTRL1 + CTRL1 + SDRAM Control Register 1 + 0x140 + 0x20 + read-write + 0x000002D0 + + + CA + Number of column address + bits + 0 + 2 + + + RA + Number of row address bits + 2 + 2 + + + DB + Memory data bus width + 4 + 2 + + + INBK + Number of internal banks + 6 + 1 + + + CAS + CAS latency + 7 + 2 + + + WRP + Write protection + 9 + 1 + + + CLKDIV + Clock division configuration + 10 + 2 + + + BSTR + Burst read + 12 + 1 + + + RD + Read delay + 13 + 2 + + + + + CTRL2 + CTRL2 + SDRAM Control Register 2 + 0x144 + 0x20 + read-write + 0x000002D0 + + + CA + Number of column address + bits + 0 + 2 + + + RA + Number of row address bits + 2 + 2 + + + DB + Memory data bus width + 4 + 2 + + + INBK + Number of internal banks + 6 + 1 + + + CAS + CAS latency + 7 + 2 + + + WRP + Write protection + 9 + 1 + + + CLKDIV + Clock division configuration + 10 + 2 + + + BSTR + Burst read + 12 + 1 + + + RD + Read pipe + 13 + 2 + + + + + TM1 + TM1 + SDRAM Timing register 1 + 0x148 + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Mode register program to active delay + 0 + 4 + + + TXSR + Exit Self-refresh to active delay + 4 + 4 + + + TRAS + Self refresh time + 8 + 4 + + + TRC + Refresh to active delay + 12 + 4 + + + TWR + Write Recovery delay + 16 + 4 + + + TRP + Precharge to active delay + 20 + 4 + + + TRCD + Row active to Read/Write delay + 24 + 4 + + + + + TM2 + TM2 + SDRAM Timing register 2 + 0x14C + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Mode register program to active delay + 0 + 4 + + + TXSR + Exit Self-refresh to active delay + 4 + 4 + + + TRAS + Self refresh time + 8 + 4 + + + TRC + Refresh to active delay + 12 + 4 + + + TWR + Write Recovery delay + 16 + 4 + + + TRP + Precharge to active delay + 20 + 4 + + + TRCD + Row active to Read/Write delay + 24 + 4 + + + + + CMD + CMD + SDRAM Command Mode register + 0x150 + 0x20 + 0x00000000 + + + CMD + SDRAM Command + 0 + 3 + write-only + + + BK2 + SDRAM Bank 2 + 3 + 1 + write-only + + + BK1 + SDRAM Bank 1 + 4 + 1 + write-only + + + ART + Auto-refresh times + 5 + 4 + read-write + + + MRD + Mode register data + 9 + 13 + read-write + + + + + RCNT + RCNT + SDRAM Refresh Timer register + 0x154 + 0x20 + 0x00000000 + + + ERRC + error flag clear + 0 + 1 + write-only + + + RC + Refresh Count + 1 + 13 + read-write + + + ERIEN + error Interrupt Enable + 14 + 1 + read-write + + + + + STS + STS + SDRAM Status register + 0x158 + 0x20 + read-only + 0x00000000 + + + ERR + error flag + 0 + 1 + + + BK1STS + Bank 1 Status + 1 + 2 + + + BK2STS + Bank 2 Status + 3 + 2 + + + BUSY + Busy status + 5 + 1 + + + + + EXT1 + EXT1 + externl timeing register 1 + 0x220 + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + EXT2 + EXT2 + externl timeing register 2 + 0x224 + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + EXT3 + EXT3 + externl timeing register 3 + 0x228 + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + EXT4 + EXT4 + externl timeing register 4 + 0x22C + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Power control register + (PWC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + VRSEL + Voltage regulator state select when deepsleep mode + 0 + 1 + + + LPSEL + Low power mode select when Cortex-M4F sleepdeep + 1 + 1 + + + CLSWEF + Clear SWEF flag + 2 + 1 + + + CLSEF + Clear SEF flag + 3 + 1 + + + PVMEN + Power voltage monitoring enable + 4 + 1 + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + + + BPWEN + Battery powered domain write enable + 8 + 1 + + + + + CTRLSTS + CTRLSTS + Power control and status register + (PWC_CTRLSTS) + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN1 + Standby wake-up pin 1 enable + 8 + 1 + read-write + + + SWPEN2 + Standby wake-up pin 2 enable + 9 + 1 + read-write + + + + + LDOOV + LDOOV + LDO output voltage register + 0x10 + 0x20 + 0x00000000 + + + LDOOVSEL + LDO output voltage select + 0 + 3 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40023800 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 5 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + + + PLLCFG + PLLCFG + PLL configuration register + (CRM_PLLCFG) + 0x4 + 0x20 + 0x00033002 + + + PLL_MS + PLL pre-division + 0 + 4 + read-write + + + PLL_NS + PLL frequency multiplication factor + 6 + 9 + read-write + + + PLL_FR + PLL post-division + 16 + 3 + read-write + + + PLLRCS + PLL reference clock select + 22 + 1 + read-write + + + + + CFG + CFG + Clock configuration register(CRM_CFG) + 0x8 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 10 + 3 + read-write + + + APB2DIV + APB2 division + 13 + 3 + read-write + + + ERTCDIV + HEXT division for ERTC clock + 16 + 5 + read-write + + + CLKOUT1_SEL + Clock output1 selection + 21 + 2 + read-write + + + CLKOUT1DIV1 + Clock output1 division1 + 24 + 3 + read-write + + + CLKOUT2DIV1 + Clock output2 division1 + 27 + 3 + read-write + + + CLKOUT2_SEL1 + Clock output2 selection1 + 30 + 2 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + (CRM_CLKINT) + 0xC + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + AHBRST1 + AHBRST1 + AHB peripheral reset register1 + (CRM_AHBRST1) + 0x10 + 0x20 + read-write + 0x000000000 + + + GPIOARST + IO port A reset + 0 + 1 + + + GPIOBRST + IO port B reset + 1 + 1 + + + GPIOCRST + IO port C reset + 2 + 1 + + + GPIODRST + IO port D reset + 3 + 1 + + + GPIOERST + IO port E reset + 4 + 1 + + + GPIOFRST + IO port F reset + 5 + 1 + + + GPIOGRST + IO port G reset + 6 + 1 + + + GPIOHRST + IO port H reset + 7 + 1 + + + CRCRST + CRC reset + 12 + 1 + + + EDMARST + EDMA reset + 21 + 1 + + + DMA1RST + DMA1 reset + 22 + 1 + + + DMA2RST + DMA2 reset + 24 + 1 + + + EMACRST + EMAC reset + 25 + 1 + + + OTGFS2RST + OTGFS2 interface reset + 29 + 1 + + + + + AHBRST2 + AHBRST2 + AHB peripheral reset register 2 + (CRM_AHBRST2) + 0x14 + 0x20 + read-write + 0x00000000 + + + DVPRST + DVP reset + 0 + 1 + + + OTGFS1RST + OTGFS1 reset + 7 + 1 + + + SDIO1RST + SDIO1 reset + 15 + 1 + + + + + AHBRST3 + AHBRST3 + AHB peripheral reset register 3 + (CRM_AHBRST3) + 0x18 + 0x20 + read-write + 0x00000000 + + + XMCRST + XMC reset + 0 + 1 + + + QSPI1RST + QSPI1 reset + 1 + 1 + + + QSPI2RST + QSPI2 reset + 14 + 1 + + + SDIO2RST + SDIO2 reset + 15 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + (CRM_APB1RST) + 0x20 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer2 reset + 0 + 1 + + + TMR3RST + Timer3 reset + 1 + 1 + + + TMR4RST + Timer4 reset + 2 + 1 + + + TMR5RST + Timer5 reset + 3 + 1 + + + TMR6RST + Timer6 reset + 4 + 1 + + + TMR7RST + Timer7 reset + 5 + 1 + + + TMR12RST + Timer12 reset + 6 + 1 + + + TMR13RST + Timer13 reset + 7 + 1 + + + TMR14RST + Timer14 reset + 8 + 1 + + + WWDTRST + Window watchdog reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + USART2RST + USART2 reset + 17 + 1 + + + USART3RST + USART3 reset + 18 + 1 + + + UART4RST + UART4 reset + 19 + 1 + + + UART5RST + UART5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + CAN2RST + CAN2 reset + 26 + 1 + + + PWCRST + PWC reset + 28 + 1 + + + DACRST + DAC reset + 29 + 1 + + + UART7RST + UART7 reset + 30 + 1 + + + UART8RST + UART8 reset + 31 + 1 + + + + + APB2RST + APB2RST + APB2 peripheral reset register + (CRM_APB2RST) + 0x24 + 0x20 + read-write + 0x00000000 + + + TMR1RST + Timer1 reset + 0 + 1 + + + TMR8RST + Timer8 reset + 1 + 1 + + + USART1RST + USART1 reset + 4 + 1 + + + USART6RST + USART6 reset + 5 + 1 + + + ADCRST + ADC reset + 8 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + SPI4RST + SPI4 reset + 13 + 1 + + + SCFGRST + SCFG reset + 14 + 1 + + + TMR9RST + Timer9 reset + 16 + 1 + + + TMR10RST + Timer10 reset + 17 + 1 + + + TMR11RST + Timer 11 reset + 18 + 1 + + + TMR20RST + Timer20 reset + 20 + 1 + + + ACCRST + ACC reset + 29 + 1 + + + + + AHBEN1 + AHBEN1 + AHB Peripheral Clock enable register 1 + (CRM_AHBEN1) + 0x30 + 0x20 + read-write + 0x00000000 + + + GPIOAEN + IO A clock enable + 0 + 1 + + + GPIOBEN + IO B clock enable + 1 + 1 + + + GPIOCEN + IO C clock enable + 2 + 1 + + + GPIODEN + IO D clock enable + 3 + 1 + + + GPIOEEN + IO E clock enable + 4 + 1 + + + GPIOFEN + IO F clock enable + 5 + 1 + + + GPIOGEN + IO G clock enable + 6 + 1 + + + GPIOHEN + IO H clock enable + 7 + 1 + + + CRCEN + CRC clock enable + 12 + 1 + + + EDMAEN + DMA1 clock enable + 21 + 1 + + + DMA1EN + DMA1 clock enable + 22 + 1 + + + DMA2EN + DMA2 clock enable + 24 + 1 + + + EMACEN + EMAC clock enable + 25 + 1 + + + EMACTXEN + EMAC Tx clock enable + 26 + 1 + + + EMACRXEN + EMAC Rx clock enable + 27 + 1 + + + EMACPTPEN + EMAC PTP clock enable + 28 + 1 + + + OTGFS2EN + OTGFS2 clock enable + 29 + 1 + + + + + AHBEN2 + AHBEN2 + AHB peripheral clock enable register 2 + (CRM_AHBEN2) + 0x34 + 0x20 + read-write + 0x00000000 + + + DVPEN + DVP clock enable + 0 + 1 + + + OTGFS1EN + OTGFS1 clock enable + 7 + 1 + + + SDIO1EN + SDIO1 clock enable + 15 + 1 + + + + + AHBEN3 + AHBEN3 + AHB peripheral clock enable register 3 + (CRM_AHBEN3) + 0x38 + 0x20 + read-write + 0x00000000 + + + XMCEN + XMC clock enable + 0 + 1 + + + QSPI1EN + QSPI1 clock enable + 1 + 1 + + + QSPI2EN + QSPI2 clock enable + 14 + 1 + + + SDIO2EN + SDIO 2 clock enable + 15 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + (CRM_APB1EN) + 0x40 + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR4EN + Timer4 clock enable + 2 + 1 + + + TMR5EN + Timer5 clock enable + 3 + 1 + + + TMR6EN + Timer6 clock enable + 4 + 1 + + + TMR7EN + Timer7 clock enable + 5 + 1 + + + TMR12EN + Timer12 clock enable + 6 + 1 + + + TMR13EN + Timer13 clock enable + 7 + 1 + + + TMR14EN + Timer14 clock enable + 8 + 1 + + + WWDTEN + WWDT clock enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + CAN2EN + CAN2 clock enable + 26 + 1 + + + PWCEN + PWC clock enable + 28 + 1 + + + DACEN + DAC clock enable + 29 + 1 + + + UART7EN + UART7 clock enable + 30 + 1 + + + UART8EN + UART8 clock enable + 31 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + (CRM_APB2EN) + 0x44 + 0x20 + read-write + 0x00000000 + + + TMR1EN + Timer1 clock enable + 0 + 1 + + + TMR8EN + Timer8 clock enable + 1 + 1 + + + USART1EN + USART1 clock enable + 4 + 1 + + + USART6EN + USART6 clock enable + 5 + 1 + + + ADC1EN + ADC1 clock enable + 8 + 1 + + + ADC2EN + ADC2 clock enable + 9 + 1 + + + ADC3EN + ADC3 clock enable + 10 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + SPI4EN + SPI4 clock enable + 13 + 1 + + + SCFGEN + SCFG clock enable + 14 + 1 + + + TMR9EN + Timer9 clock enable + 16 + 1 + + + TMR10EN + Timer10 clock enable + 17 + 1 + + + TMR11EN + Timer11 clock enable + 18 + 1 + + + TMR20EN + Timer20 clock enable + 20 + 1 + + + ACCEN + ACC clock enable + 29 + 1 + + + + + AHBLPEN1 + AHBLPEN1 + AHB Low-power Peripheral Clock enable + register 1 (CRM_AHBLPEN1) + 0x50 + 0x20 + read-write + 0x3E6390FF + + + GPIOALPEN + IO A clock enable during sleep mode + 0 + 1 + + + GPIOBLPEN + IO B clock enable during sleep mode + 1 + 1 + + + GPIOCLPEN + IO C clock enable during sleep mode + 2 + 1 + + + GPIODLPEN + IO D clock enable during sleep mode + 3 + 1 + + + GPIOELPEN + IO E clock enable during sleep mode + 4 + 1 + + + GPIOFLPEN + IO F clock enable during sleep mode + 5 + 1 + + + GPIOGLPEN + IO G clock enable during sleep mode + 6 + 1 + + + GPIOHLPEN + IO H clock enable during sleep mode + 7 + 1 + + + CRCLPEN + CRC clock enable during sleep mode + 12 + 1 + + + FLASHLPEN + Flash clock enable during sleep mode + 15 + 1 + + + SRAM1LPEN + SRAM1 clock enable during sleep mode + 16 + 1 + + + SRAM2LPEN + SRAM2 clock enable during sleep mode + 17 + 1 + + + EDMALPEN + EDMA clock enable during sleep mode + 21 + 1 + + + DMA1LPEN + DMA1 clock enable during sleep mode + 22 + 1 + + + DMA2LPEN + DMA2 clock enable during sleep mode + 24 + 1 + + + EMACLPEN + EMAC clock enable during sleep mode + 25 + 1 + + + EMACTXLPEN + EMAC Tx clock enable during sleep mode + 26 + 1 + + + EMACRXLPEN + EMAC Rx clock enable during sleep mode + 27 + 1 + + + EMACPTPLPEN + EMAC PTP clock enable during sleep mode + 28 + 1 + + + OTGFS2LPEN + OTGFS2 clock enable during sleep mode + 29 + 1 + + + + + AHBLPEN2 + AHBLPEN2 + AHB peripheral Low-power clock + enable register 2 (CRM_AHBLPEN2) + 0x54 + 0x20 + read-write + 0x00008081 + + + DVPLPEN + DVP clock enable during sleep mode + 0 + 1 + + + OTGFS1LPEN + OTGFS1 clock enable during sleep mode + 7 + 1 + + + SDIO1LPEN + SDIO1 clock enable during sleep mode + 15 + 1 + + + + + AHBLPEN3 + AHBLPEN3 + AHB peripheral Low-power clock + enable register 3 (CRM_AHBLPEN3) + 0x58 + 0x20 + read-write + 0x0000C003 + + + XMCLPEN + XMC clock enable during sleep mode + 0 + 1 + + + QSPI1LPEN + QSPI1 clock enable during sleep mode + 1 + 1 + + + QSPI2LPEN + QSPI2 clock enable during sleep mode + 14 + 1 + + + SDIO2LPEN + SDIO2 clock enable during sleep mode + 15 + 1 + + + + + APB1LPEN + APB1LPEN + APB1 peripheral Low-power clock + enable register (CRM_APB1LPEN) + 0x60 + 0x20 + read-write + 0xF6FEE9FF + + + TMR2LPEN + Timer2 clock enable during sleep mode + 0 + 1 + + + TMR3LPEN + Timer3 clock enable during sleep mode + 1 + 1 + + + TMR4LPEN + Timer4 clock enable during sleep mode + 2 + 1 + + + TMR5LPEN + Timer5 clock enable during sleep mode + 3 + 1 + + + TMR6LPEN + Timer6 clock enable during sleep mode + 4 + 1 + + + TMR7LPEN + Timer7 clock enable during sleep mode + 5 + 1 + + + TMR12LPEN + Timer12 clock enable during sleep mode + 6 + 1 + + + TMR13LPEN + Timer13 clock enable during sleep mode + 7 + 1 + + + TMR14LPEN + Timer14 clock enable during sleep mode + 8 + 1 + + + WWDTLPEN + WWDT clock enable during sleep mode + 11 + 1 + + + SPI2LPEN + SPI2 clock enable during sleep mode + 14 + 1 + + + SPI3LPEN + SPI3 clock enable during sleep mode + 15 + 1 + + + USART2LPEN + USART2 clock enable during sleep mode + 17 + 1 + + + USART3LPEN + USART3 clock enable during sleep mode + 18 + 1 + + + UART4LPEN + UART4 clock enable during sleep mode + 19 + 1 + + + UART5LPEN + UART5 clock enable during sleep mode + 20 + 1 + + + I2C1CPEN + I2C1 clock enable during sleep mode + 21 + 1 + + + I2C2CPEN + I2C2 clock enable during sleep mode + 22 + 1 + + + I2C3CPEN + I2C3 clock enable during sleep mode + 23 + 1 + + + CAN1LPEN + CAN1 clock enable during sleep mode + 25 + 1 + + + CAN2LPEN + CAN2 clock enable during sleep mode + 26 + 1 + + + PWCLPEN + PWC clock enable during sleep mode + 28 + 1 + + + DACLPEN + DAC clock enable during sleep mode + 29 + 1 + + + UART7LPEN + UART7 clock enable during sleep mode + 30 + 1 + + + UART8LPEN + UART8 clock enable during sleep mode + 31 + 1 + + + + + APB2LPEN + APB2LPEN + APB2 peripheral Low-power clock + enable register (CRM_APB2LPEN) + 0x64 + 0x20 + read-write + 0x20177733 + + + TMR1LPEN + Timer1 clock enable during sleep mode + 0 + 1 + + + TMR8LPEN + Timer8 clock enable during sleep mode + 1 + 1 + + + USART1LPEN + USART1 clock enable during sleep mode + 4 + 1 + + + USART6LPEN + USART6 clock enable during sleep mode + 5 + 1 + + + ADC1CPEN + ADC1 clock enable during sleep mode + 8 + 1 + + + ADC2CPEN + ADC2 clock enable during sleep mode + 9 + 1 + + + ADC3EN + ADC3 clock enable during sleep mode + 10 + 1 + + + SPI1LPEN + SPI1 clock enable during sleep mode + 12 + 1 + + + SPI4LPEN + SPI4 clock enable during sleep mode + 13 + 1 + + + SCFGLPEN + SCFG clock enable during sleep mode + 14 + 1 + + + TMR9LPEN + Timer9 clock enable during sleep mode + 16 + 1 + + + TMR10LPEN + Timer10 clock enable during sleep mode + 17 + 1 + + + TMR11LPEN + Timer11 clock enable during sleep mode + 18 + 1 + + + TMR20LPEN + Timer20 clock enable during sleep mode + 20 + 1 + + + ACCLPEN + ACC clock enable during sleep mode + 29 + 1 + + + + + BPDC + BPDC + Battery powered domain control register + (CRM_BPDC) + 0x70 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + ERTCSEL + ERTC clock source selection + 8 + 2 + read-write + + + ERTCEN + ERTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + (CRM_CTRLSTS) + 0x74 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset reset flag + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register1 + 0xA0 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + HICKDIV + HICK 6 divider selection + 12 + 1 + read-write + + + HICK_TO_USB + HICK to usb clock + 13 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 14 + 1 + read-write + + + CLKOUT2_SEL2 + Clock output2 select2 + 16 + 4 + read-write + + + CLKOUT1DIV2 + Clock output1 division2 + 24 + 4 + read-write + + + CLKOUT2DIV2 + Clock output2 division2 + 28 + 4 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register2 + 0xA4 + 0x20 + 0x0000000D + + + AUTO_STEP_EN + AUTO_STEP_EN + 4 + 2 + read-write + + + CLK_TO_TMR + Clock output internal connect to timer10 + 8 + 1 + read-write + + + USBDIV + USB division + 12 + 4 + read-write + + + + + + + GPIOA + General purpose I/Os + GPIO + 0x40020000 + + 0x0 + 0x400 + registers + + + + CFGR + CFGR + GPIO configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + IOMC15 + GPIOx pin 15 mode configurate + 30 + 2 + + + IOMC14 + GPIOx pin 14 mode configurate + 28 + 2 + + + IOMC13 + GPIOx pin 13 mode configurate + 26 + 2 + + + IOMC12 + GPIOx pin 12 mode configurate + 24 + 2 + + + IOMC11 + GPIOx pin 11 mode configurate + 22 + 2 + + + IOMC10 + GPIOx pin 10 mode configurate + 20 + 2 + + + IOMC9 + GPIOx pin 9 mode configurate + 18 + 2 + + + IOMC8 + GPIOx pin 8 mode configurate + 16 + 2 + + + IOMC7 + GPIOx pin 7 mode configurate + 14 + 2 + + + IOMC6 + GPIOx pin 6 mode configurate + 12 + 2 + + + IOMC5 + GPIOx pin 5 mode configurate + 10 + 2 + + + IOMC4 + GPIOx pin 4 mode configurate + 8 + 2 + + + IOMC3 + GPIOx pin 3 mode configurate + 6 + 2 + + + IOMC2 + GPIOx pin 2 mode configurate + 4 + 2 + + + IOMC1 + GPIOx pin 1 mode configurate + 2 + 2 + + + IOMC0 + GPIOx pin 0 mode configurate + 0 + 2 + + + + + OMODE + OMODE + GPIO output mode register + 0x4 + 0x20 + read-write + 0x00000000 + + + OM15 + GPIOx pin 15 outpu mode configurate + 15 + 1 + + + OM14 + GPIOx pin 14 outpu mode configurate + 14 + 1 + + + OM13 + GPIOx pin 13 outpu mode configurate + 13 + 1 + + + OM12 + GPIOx pin 12 outpu mode configurate + 12 + 1 + + + OM11 + GPIOx pin 11 outpu mode configurate + 11 + 1 + + + OM10 + GPIOx pin 10 outpu mode configurate + 10 + 1 + + + OM9 + GPIOx pin 9 outpu mode configurate + 9 + 1 + + + OM8 + GPIOx pin 8 outpu mode configurate + 8 + 1 + + + OM7 + GPIOx pin 7 outpu mode configurate + 7 + 1 + + + OM6 + GPIOx pin 6 outpu mode configurate + 6 + 1 + + + OM5 + GPIOx pin 5 outpu mode configurate + 5 + 1 + + + OM4 + GPIOx pin 4 outpu mode configurate + 4 + 1 + + + OM3 + GPIOx pin 3 outpu mode configurate + 3 + 1 + + + OM2 + GPIOx pin 2 outpu mode configurate + 2 + 1 + + + OM1 + GPIOx pin 1 outpu mode configurate + 1 + 1 + + + OM0 + GPIOx pin 0 outpu mode configurate + 0 + 1 + + + + + ODRVR + ODRVR + GPIO drive capability register + 0x8 + 0x20 + read-write + 0x00000000 + + + ODRV15 + GPIOx pin 15 output drive capability + 30 + 2 + + + ODRV14 + GPIOx pin 14 output drive capability + 28 + 2 + + + ODRV13 + GPIOx pin 13 output drive capability + 26 + 2 + + + ODRV12 + GPIOx pin 12 output drive capability + 24 + 2 + + + ODRV11 + GPIOx pin 11 output drive capability + 22 + 2 + + + ODRV10 + GPIOx pin 10 output drive capability + 20 + 2 + + + ODRV9 + GPIOx pin 9 output drive capability + 18 + 2 + + + ODRV8 + GPIOx pin 8 output drive capability + 16 + 2 + + + ODRV7 + GPIOx pin 7 output drive capability + 14 + 2 + + + ODRV6 + GPIOx pin 6 output drive capability + 12 + 2 + + + ODRV5 + GPIOx pin 5 output drive capability + 10 + 2 + + + ODRV4 + GPIOx pin 4 output drive capability + 8 + 2 + + + ODRV3 + GPIOx pin 3 output drive capability + 6 + 2 + + + ODRV2 + GPIOx pin 2 output drive capability + 4 + 2 + + + ODRV1 + GPIOx pin 1 output drive capability + 2 + 2 + + + ODRV0 + GPIOx pin 0 output drive capability + 0 + 2 + + + + + PULL + PULL + GPIO pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PULL15 + GPIOx pin 15 pull configuration + 30 + 2 + + + PULL14 + GPIOx pin 14 pull configuration + 28 + 2 + + + PULL13 + GPIOx pin 13 pull configuration + 26 + 2 + + + PULL12 + GPIOx pin 12 pull configuration + 24 + 2 + + + PULL11 + GPIOx pin 11 pull configuration + 22 + 2 + + + PULL10 + GPIOx pin 10 pull configuration + 20 + 2 + + + PULL9 + GPIOx pin 9 pull configuration + 18 + 2 + + + PULL8 + GPIOx pin 8 pull configuration + 16 + 2 + + + PULL7 + GPIOx pin 7 pull configuration + 14 + 2 + + + PULL6 + GPIOx pin 6 pull configuration + 12 + 2 + + + PULL5 + GPIOx pin 5 pull configuration + 10 + 2 + + + PULL4 + GPIOx pin 4 pull configuration + 8 + 2 + + + PULL3 + GPIOx pin 3 pull configuration + 6 + 2 + + + PULL2 + GPIOx pin 2 pull configuration + 4 + 2 + + + PULL1 + GPIOx pin 1 pull configuration + 2 + 2 + + + PULL0 + GPIOx pin 0 pull configuration + 0 + 2 + + + + + IDT + IDT + GPIO input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + GPIO output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x18 + 0x20 + write-only + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + WPR + WPR + Port write protect + register + 0x1C + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + MUXL + MUXL + GPIO muxing function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + MUXL7 + GPIOx pin 7 muxing + 28 + 4 + + + MUXL6 + GPIOx pin 6 muxing + 24 + 4 + + + MUXL5 + GPIOx pin 5 muxing + 20 + 4 + + + MUXL4 + GPIOx pin 4 muxing + 16 + 4 + + + MUXL3 + GPIOx pin 3 muxing + 12 + 4 + + + MUXL2 + GPIOx pin 2 muxing + 8 + 4 + + + MUXL1 + GPIOx pin 1 muxing + 4 + 4 + + + MUXL0 + GPIOx pin 0 muxing + 0 + 4 + + + + + MUXH + MUXH + GPIO muxing function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + MUXH15 + GPIOx pin 15 muxing + 28 + 4 + + + MUXH14 + GPIOx pin 14 muxing + 24 + 4 + + + MUXH13 + GPIOx pin 13 muxing + 20 + 4 + + + MUXH12 + GPIOx pin 12 muxing + 16 + 4 + + + MUXH11 + GPIOx pin 11 muxing + 12 + 4 + + + MUXH10 + GPIOx pin 10 muxing + 8 + 4 + + + MUXH9 + GPIOx pin 9 muxing + 4 + 4 + + + MUXH8 + GPIOx pin 8 muxing + 0 + 4 + + + + + CLR + CLR + GPIO bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 1 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + HDRV + HDRV + Huge current driver + 0x3C + 0x20 + read-write + 0x00000000 + + + HDRV0 + Port x driver bit y + 0 + 1 + + + HDRV1 + Port x driver bit y + 1 + 1 + + + HDRV2 + Port x driver bit y + 2 + 1 + + + HDRV3 + Port x driver bit y + 3 + 1 + + + HDRV4 + Port x driver bit y + 4 + 1 + + + HDRV5 + Port x driver bit y + 5 + 1 + + + HDRV6 + Port x driver bit y + 6 + 1 + + + HDRV7 + Port x driver bit y + 7 + 1 + + + HDRV8 + Port x driver bit y + 8 + 1 + + + HDRV9 + Port x driver bit y + 9 + 1 + + + HDRV10 + Port x driver bit y + 10 + 1 + + + HDRV11 + Port x driver bit y + 11 + 1 + + + HDRV12 + Port x driver bit y + 12 + 1 + + + HDRV13 + Port x driver bit y + 13 + 1 + + + HDRV14 + Port x driver bit y + 14 + 1 + + + HDRV15 + Port x driver bit y + 15 + 1 + + + + + + + GPIOB + 0x40020400 + + + GPIOC + 0x40020800 + + + GPIOD + 0x40020C00 + + + GPIOE + 0x40021000 + + + GPIOF + 0x40021400 + + + GPIOG + 0x40021800 + + + GPIOH + 0x40021C00 + + + EXINT + EXINT + EXINT + 0x40013C00 + + 0x0 + 0x400 + registers + + + EXINT0 + EXINT Line0 interrupt + 6 + + + EXINT1 + EXINT Line1 interrupt + 7 + + + EXINT2 + EXINT Line2 interrupt + 8 + + + EXINT3 + EXINT Line3 interrupt + 9 + + + EXINT4 + EXINT Line4 interrupt + 10 + + + EXINT9_5 + EXINT Line[9:5] interrupts + 23 + + + EXINT15_10 + EXINT Line[15:10] interrupts + 40 + + + PVM + PVM interrupt connect to EXINT line16 + 1 + + + ERTCALARM + ERTC Alarm interrupt connect to EXINT line17 + 41 + + + OTGFS1_WKUP + OTGFS1_WKUP interrupt connect to EXINT line18 + 42 + + + EMAC_WKUP + EMAC_WKUP interrupt connect to EXINT line19 + 62 + + + OTGFS2_WKUP + OTGFS2_WKUP interrupt connect to EXINT line20 + 76 + + + TAMPER + Tamper interrupt connect to EXINT line21 + 2 + + + ERTC_WKUP + ERTC Global interrupt connect to EXINT line22 + 3 + + + + INTEN + INTEN + Interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + INTEN19 + Interrupt enable or disable on line 19 + 19 + 1 + + + INTEN20 + Interrupt enable or disable on line 20 + 20 + 1 + + + INTEN21 + Interrupt enable or disable on line 21 + 21 + 1 + + + INTEN22 + Interrupt enable or disable on line 22 + 22 + 1 + + + + + EVTEN + EVTEN + Event enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + EVTEN19 + Event enable or disable on line 19 + 19 + 1 + + + EVTEN20 + Event enable or disable on line 20 + 20 + 1 + + + EVTEN21 + Event enable or disable on line 21 + 21 + 1 + + + EVTEN22 + Event enable or disable on line 22 + 22 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + RP19 + Rising polarity configuration bit of line 19 + 19 + 1 + + + RP20 + Rising polarity configuration bit of line 20 + 20 + 1 + + + RP21 + Rising polarity configuration bit of line 21 + 21 + 1 + + + RP22 + Rising polarity configuration bit of line 22 + 22 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + FP19 + Falling polarity event configuration bit of line 19 + 19 + 1 + + + FP20 + Falling polarity event configuration bit of line 20 + 20 + 1 + + + FP21 + Falling polarity event configuration bit of line 21 + 21 + 1 + + + FP22 + Falling polarity event configuration bit of line 22 + 22 + 1 + + + + + SWTRG + SWTRG + Software triggle register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + SWT19 + Software triggle on line 19 + 19 + 1 + + + SWT20 + Software triggle on line 20 + 20 + 1 + + + SWT21 + Software triggle on line 21 + 21 + 1 + + + SWT22 + Software triggle on line 22 + 22 + 1 + + + + + INTSTS + INTSTS + Interrupt status register + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + LINE19 + Line 19 state bit + 19 + 1 + + + LINE20 + Line 20 state bit + 20 + 1 + + + LINE21 + Line 21 state bit + 21 + 1 + + + LINE22 + Line 22 state bit + 22 + 1 + + + + + + + EDMA + EDMA controller + EDMA + 0x40026000 + + 0x0 + 0x400 + registers + + + EDMA_Stream1 + EDMA Stream1 global interrupt + 11 + + + EDMA_Stream2 + EDMA Stream2 global interrupt + 12 + + + EDMA_Stream3 + EDMA Stream3 global interrupt + 13 + + + EDMA_Stream4 + EDMA Stream4 global interrupt + 14 + + + EDMA_Stream5 + EDMA Stream5 global interrupt + 15 + + + EDMA_Stream6 + EDMA Stream6 global interrupt + 16 + + + EDMA_Stream7 + EDMA Stream7 global interrupt + 17 + + + EDMA_Stream8 + EDMA Stream8 global interrupt + 47 + + + + STS1 + STS1 + Interrupt status register1 + 0x0 + 0x20 + read-only + 0x00000000 + + + FDTF4 + Stream 4 Full data transfer interrupt flag + + 27 + 1 + + + HDTF4 + Stream 4 half data transfer interrupt flag + + 26 + 1 + + + DTERRF4 + Stream 4 transfer error interrupt flag + + 25 + 1 + + + DMERRF4 + Stream 4 direct mode error interrupt flag + + 24 + 1 + + + FERRF4 + Stream 4 FIFO error interrupt flag + + 22 + 1 + + + FDTF3 + Stream 3 Full data transfer interrupt flag + + 21 + 1 + + + HDTF3 + Stream 3 half data transfer interrupt flag + + 20 + 1 + + + DTERRF3 + Stream 3 transfer error interrupt flag + + 19 + 1 + + + DMERRF3 + Stream 3 direct mode error interrupt flag + + 18 + 1 + + + FERRF3 + Stream 3 FIFO error interrupt flag + + 16 + 1 + + + FDTF2 + Stream 2 Full data transfer interrupt flag + + 11 + 1 + + + HDTF2 + Stream 2 half data transfer interrupt flag + + 10 + 1 + + + DTERRF2 + Stream 2 transfer error interrupt flag + + 9 + 1 + + + DMERRF2 + Stream 2 direct mode error interrupt flag + + 8 + 1 + + + FERRF2 + Stream 2 FIFO error interrupt flag + + 6 + 1 + + + FDTF1 + Stream 1 Full data transfer interrupt flag + + 5 + 1 + + + HDTF1 + Stream 1 half data transfer interrupt flag + + 4 + 1 + + + DTERRF1 + Stream 1 transfer error interrupt flag + + 3 + 1 + + + DMERRF1 + Stream 1 direct mode error interrupt flag + + 2 + 1 + + + FERRF1 + Stream 1 FIFO error interrupt flag + + 0 + 1 + + + + + STS2 + STS2 + Interrupt status register2 + 0x4 + 0x20 + read-only + 0x00000000 + + + FDTF8 + Stream 8 full data transfer interrupt flag + + 27 + 1 + + + HDTF8 + Stream 8 half data transfer interrupt flag + + 26 + 1 + + + DTERRF8 + Stream 8 transfer error interrupt flag + + 25 + 1 + + + DMERRF8 + Stream 8 direct mode error interrupt flag + + 24 + 1 + + + FERRF8 + Stream 8 FIFO error interrupt flag + + 22 + 1 + + + FDTF7 + Stream 7 full data transfer interrupt flag + + 21 + 1 + + + HDTF7 + Stream 7 half data transfer interrupt flag + + 20 + 1 + + + DTERRF7 + Stream 7 transfer error interrupt flag + + 19 + 1 + + + DMERRF7 + Stream 7 direct mode error interrupt flag + + 18 + 1 + + + FERRF7 + Stream 7 FIFO error interrupt flag + + 16 + 1 + + + FDTF6 + Stream 6 full data transfer interrupt flag + + 11 + 1 + + + HDTF6 + Stream 6 half data transfer interrupt flag + + 10 + 1 + + + DTERRF6 + Stream 6 transfer error interrupt flag + + 9 + 1 + + + DMERRF6 + Stream 6 direct mode error interrupt flag + + 8 + 1 + + + FERRF6 + Stream 6 FIFO error interrupt flag + + 6 + 1 + + + FDTF5 + Stream 5 full data transfer interrupt flag + + 5 + 1 + + + HDTF5 + Stream 5 half data transfer interrupt flag + + 4 + 1 + + + DTERRF5 + Stream 5 transfer error interrupt flag + + 3 + 1 + + + DMERRF5 + Stream 5 direct mode error interrupt flag + + 2 + 1 + + + FERRF5 + Stream 5 FIFO error interrupt flag + + 0 + 1 + + + + + CLR1 + CLR1 + Interrupt flag clear register1 + + 0x8 + 0x20 + read-write + 0x00000000 + + + FDTFC4 + Stream 4 clear full data transfer complete interrupt flag + + 27 + 1 + + + HDTFC4 + Stream 4 clear half data transfer interrupt flag + + 26 + 1 + + + DTERRFC4 + Stream 4 clear transfer error interrupt flag + + 25 + 1 + + + DMERRFC4 + Stream 4 clear direct mode error interrupt flag + + 24 + 1 + + + FERRFC4 + Stream 4 clear FIFO error interrupt flag + + 22 + 1 + + + FDTFC3 + Stream 3 clear full data transfer complete interrupt flag + + 21 + 1 + + + HDTFC3 + Stream 3 clear half data transfer interrupt flag + + 20 + 1 + + + DTERRFC3 + Stream 3 clear transfer error interrupt flag + + 19 + 1 + + + DMERRFC3 + Stream 3 clear direct mode error interrupt flag + + 18 + 1 + + + FERRFC3 + Stream 3 clear FIFO error interrupt flag + + 16 + 1 + + + FDTFC2 + Stream 2 clear full data transfer complete interrupt flag + + 11 + 1 + + + HDTFC2 + Stream 2 clear half data transfer interrupt flag + + 10 + 1 + + + DTERRFC2 + Stream 2 clear transfer error interrupt flag + + 9 + 1 + + + DMERRFC2 + Stream 2 clear direct mode error interrupt flag + + 8 + 1 + + + FERRFC2 + Stream 2 clear FIFO error interrupt flag + + 6 + 1 + + + FDTFC1 + Stream 1 clear full data transfer complete interrupt flag + + 5 + 1 + + + HDTFC1 + Stream 1 clear half data transfer interrupt flag + + 4 + 1 + + + DTERRFC1 + Stream 1 clear transfer error interrupt flag + + 3 + 1 + + + DMERRFC1 + Stream 1 clear direct mode error interrupt flag + + 2 + 1 + + + FERRFC1 + Stream 1 clear FIFO error interrupt flag + + 0 + 1 + + + + + CLR2 + CLR2 + Interrupt flag clear register2 + + 0xC + 0x20 + read-write + 0x00000000 + + + FDTFC8 + Stream 8 clear full data transfer complete interrupt flag + + 27 + 1 + + + HDTFC8 + Stream 8 clear half data transfer interrupt flag + + 26 + 1 + + + DTERRFC8 + Stream 8 clear transfer error interrupt flag + + 25 + 1 + + + DMERRFC8 + Stream 8 clear direct mode error interrupt flag + + 24 + 1 + + + FERRFC8 + Stream 8 clear FIFO error interrupt flag + + 22 + 1 + + + FDTFC7 + Stream 7 clear full data transfer complete interrupt flag + + 21 + 1 + + + HDTFC7 + Stream 7 clear half data transfer interrupt flag + + 20 + 1 + + + DTERRFC7 + Stream 7 clear transfer error interrupt flag + + 19 + 1 + + + DMERRFC7 + Stream 7 clear direct mode error interrupt flag + + 18 + 1 + + + FERRFC7 + Stream 7 clear FIFO error interrupt flag + + 16 + 1 + + + FDTFC6 + Stream 6 clear full data transfer complete interrupt flag + + 11 + 1 + + + HDTFC6 + Stream 6 clear half data transfer interrupt flag + + 10 + 1 + + + DTERRFC6 + Stream 6 clear transfer error interrupt flag + + 9 + 1 + + + DMERRFC6 + Stream 6 clear direct mode error interrupt flag + + 8 + 1 + + + FERRFC6 + Stream 6 clear FIFO error interrupt flag + + 6 + 1 + + + FDTFC5 + Stream 5 clear full data transfer complete interrupt flag + + 5 + 1 + + + HDTFC5 + Stream 5 clear half data transfer interrupt flag + + 4 + 1 + + + DTERRFC5 + Stream 5 clear transfer error interrupt flag + + 3 + 1 + + + DMERRFC5 + Stream 5 clear direct mode error interrupt flag + + 2 + 1 + + + FERRFC5 + Stream 5 clear FIFO error interrupt flag + + 0 + 1 + + + + + S1CTRL + S1CTRL + stream 1 control + register + 0x10 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S1DTCNT + S1DTCNT + stream 1 number of data + register + 0x14 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S1PADDR + S1PADDR + stream 1 peripheral address + register + 0x18 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S1M0ADDR + S1M0ADDR + stream 1 memory 0 address + register + 0x1C + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S1M1ADDR + S1M1ADDR + stream 1 memory 1 address + register + 0x20 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S1FCTRL + S1FCTRL + stream 1 FIFO control register + 0x24 + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S2CTRL + S2CTRL + stream 2 control + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S2DTCNT + S2DTCNT + stream 2 number of data + register + 0x2C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S2PADDR + S2PADDR + stream 2 peripheral address + register + 0x30 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S2M0ADDR + S2M0ADDR + stream 2 memory 0 address + register + 0x34 + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S2M1ADDR + S2M1ADDR + stream 2 memory 1 address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S2FCTRL + S2FCTRL + stream 2 FIFO control register + 0x3C + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S3CTRL + S3CTRL + stream 3 control + register + 0x40 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S3DTCNT + S3DTCNT + stream 3 number of data + register + 0x44 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S3PADDR + S3PADDR + stream 3 peripheral address + register + 0x48 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S3M0ADDR + S3M0ADDR + stream 3 memory 0 address + register + 0x4C + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S3M1ADDR + S3M1ADDR + stream 3 memory 1 address + register + 0x50 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S3FCTRL + S3FCTRL + stream 3 FIFO control register + 0x54 + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S4CTRL + S4CTRL + stream 4 control + register + 0x58 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S4DTCNT + S4DTCNT + stream 4 number of data + register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S4PADDR + S4PADDR + stream 4 peripheral address + register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S4M0ADDR + S4M0ADDR + stream 4 memory 0 address + register + 0x64 + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S4M1ADDR + S4M1ADDR + stream 4 memory 1 address + register + 0x68 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S4FCTRL + S4FCTRL + stream 4 FIFO control register + 0x6C + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S5CTRL + S5CTRL + stream 5 control + register + 0x70 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S5DTCNT + S5DTCNT + stream 5 number of data + register + 0x74 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S5PADDR + S5PADDR + stream 5 peripheral address + register + 0x78 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S5M0ADDR + S5M0ADDR + stream 5 memory 0 address + register + 0x7C + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S5M1ADDR + S5M1ADDR + stream 5 memory 1 address + register + 0x80 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S5FCTRL + S5FCTRL + stream 5 FIFO control register + 0x84 + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S6CTRL + S6CTRL + stream 6 control + register + 0x88 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S6DTCNT + S6DTCNT + stream 6 number of data + register + 0x8C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S6PADDR + S6PADDR + stream 6 peripheral address + register + 0x90 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S6M0ADDR + S6M0ADDR + stream 6 memory 0 address + register + 0x94 + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S6M1ADDR + S6M1ADDR + stream 6 memory 1 address + register + 0x98 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S6FCTRL + S6FCTRL + stream 6 FIFO control register + 0x9C + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S7CTRL + S7CTRL + stream 7 control + register + 0xA0 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S7DTCNT + S7DTCNT + stream 7 number of data + register + 0xA4 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S7PADDR + S7PADDR + stream 7 peripheral address + register + 0xA8 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S7M0ADDR + S7M0ADDR + stream 7 memory 0 address + register + 0xAC + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S7M1ADDR + S7M1ADDR + stream 7 memory 1 address + register + 0xB0 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S7FCTRL + S7FCTRL + stream 7 FIFO control register + 0xB4 + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S8CTRL + S8CTRL + stream 8 control + register + 0xB8 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S8DTCNT + S8DTCNT + stream 8 number of data + register + 0xBC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S8PADDR + S8PADDR + stream 8 peripheral address + register + 0xC0 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S8M0ADDR + S8M0ADDR + stream 8 memory 0 address + register + 0xC4 + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S8M1ADDR + S8M1ADDR + stream 8 memory 1 address + register + 0xC8 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S8FCTRL + S8FCTRL + stream 8 FIFO control register + 0xCC + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + LLCTRL + LLCTRL + DMA Link List Control Register + 0xD0 + 0x20 + 0x00000000 + + + S1LLEN + Stream 1 link list enable + 0 + 1 + read-write + + + S2LLEN + Stream 2 link list enable + 1 + 1 + read-write + + + S3LLEN + Stream 3 link list enable + 2 + 1 + read-write + + + S4LLEN + Stream 4 link list enable + 3 + 1 + read-write + + + S5LLEN + Stream 5 link list enable + 4 + 1 + read-write + + + S6LLEN + Stream 6 link list enable + 5 + 1 + read-write + + + S7LLEN + Stream 7 link list enable + 6 + 1 + read-write + + + S8LLEN + Stream 8 link list enable + 7 + 1 + read-write + + + + + S1LLP + S1LLP + Stream 1 Link List Pointer + 0xD4 + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S2LLP + S2LLP + Stream 2 Link List Pointer + 0xD8 + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S3LLP + S3LLP + Stream 3 Link List Pointer + 0xDC + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S4LLP + S4LLP + Stream 4 Link List Pointer + 0xE0 + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S5LLP + S5LLP + Stream 5 Link List Pointer + 0xE4 + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S6LLP + S6LLP + Stream 6 Link List Pointer + 0xE8 + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S7LLP + S7LLP + Stream 7 Link List Pointer + 0xEC + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S8LLP + S8LLP + Stream 8 Link List Pointer + 0xF0 + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S2DCTRL + S2DCTRL + EDMA 2D Transfer Control Register + 0xF4 + 0x20 + 0x00000000 + + + S1_2DEN + Stream 1 2D transfer enable + 0 + 1 + read-write + + + S2_2DEN + Stream 2 2D transfer enable + 1 + 1 + read-write + + + S3_2DEN + Stream 3 2D transfer enable + 2 + 1 + read-write + + + S4_2DEN + Stream 4 2D transfer enable + 3 + 1 + read-write + + + S5_2DEN + Stream 5 2D transfer enable + 4 + 1 + read-write + + + S6_2DEN + Stream 6 2D transfer enable + 5 + 1 + read-write + + + S7_2DEN + Stream 7 2D transfer enable + 6 + 1 + read-write + + + S8_2DEN + Stream 8 2D transfer enable + 7 + 1 + read-write + + + + + S1_2DCNT + S1_2DCNT + Stream 1 2D Transfer Count + 0xF8 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S1_STRIDE + S1_STRIDE + Stream 1 2D Transfer Stride + 0xFC + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S2_2DCNT + S2_2DCNT + Stream 2 2D Transfer Count + 0x100 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S2_STRIDE + S2_STRIDE + Stream 2 2D Transfer Stride + 0x104 + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S3_2DCNT + S3_2DCNT + Stream 3 2D Transfer Count + 0x108 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S3_STRIDE + S3_STRIDE + Stream 3 2D Transfer Stride + 0x10C + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S4_2DCNT + S4_2DCNT + Stream 4 2D Transfer Count + 0x110 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S4_STRIDE + S4_STRIDE + Stream 4 2D Transfer Stride + 0x114 + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S5_2DCNT + S5_2DCNT + Stream 5 2D Transfer Count + 0x118 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S5_STRIDE + S5_STRIDE + Stream 5 2D Transfer Stride + 0x11C + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S6_2DCNT + S6_2DCNT + Stream 6 2D Transfer Count + 0x120 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S6_STRIDE + S6_STRIDE + Stream 6 2D Transfer Stride + 0x124 + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S7_2DCNT + S7_2DCNT + Stream 7 2D Transfer Count + 0x128 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S7_STRIDE + S7_STRIDE + Stream 7 2D Transfer Stride + 0x12C + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S8_2DCNT + S8_2DCNT + Stream 8 2D Transfer Count + 0x130 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S8_STRIDE + S8_STRIDE + Stream 8 2D Transfer Stride + 0x134 + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + SYNCEN + SYNCEN + Sync Enable + 0x138 + 0x20 + 0x00000000 + + + S1SYNC + Stream 1 sync enable + 0 + 1 + read-write + + + S2SYNC + Stream 2 sync enable + 1 + 1 + read-write + + + S3SYNC + Stream 3 sync enable + 2 + 1 + read-write + + + S4SYNC + Stream 4 sync enable + 3 + 1 + read-write + + + S5SYNC + Stream 5 sync enable + 4 + 1 + read-write + + + S6SYNC + Stream 6 sync enable + 5 + 1 + read-write + + + S7SYNC + Stream 7 sync enable + 6 + 1 + read-write + + + S8SYNC + Stream 8 sync enable + 7 + 1 + read-write + + + + + MUXSEL + MUXSEL + EDMA MUX Table Selection + 0x13C + 0x20 + 0x00000000 + + + TBL_SEL + Multiplexer Table Select + 0 + 1 + read-write + + + + + MUXS1CTRL + MUXS1CTRL + Stream 1 Configuration Register + 0x140 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS2CTRL + MUXS2CTRL + Stream 2 Configuration Register + 0x144 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS3CTRL + MUXS3CTRL + Stream 3 Configuration Register + 0x148 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS4CTRL + MUXS4CTRL + Stream 4 Configuration Register + 0x14C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS5CTRL + MUXS5CTRL + Stream x Configuration Register + 0x150 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS6CTRL + MUXS6CTRL + Stream 6 Configuration Register + 0x154 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS7CTRL + MUXS7CTRL + Stream 7 Configuration Register + 0x158 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS8CTRL + MUXS8CTRL + Stream 8 Configuration Register + 0x15C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXG1CTRL + MUXG1CTRL + Generator 1 Configuration Register + 0x160 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG2CTRL + MUXG2CTRL + Generator 2 Configuration Register + 0x164 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG3CTRL + MUXG3CTRL + Generator 3 Configuration Register + 0x168 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG4CTRL + MUXG4CTRL + Generator 4 Configuration Register + 0x16C + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXSYNCSTS + MUXSYNCSTS + Channel Interrupt Status Register + 0x170 + 0x20 + 0x00000000 + + + SYNCOVF1 + Synchronizaton overrun interrupt flag + 0 + 1 + read-only + + + SYNCOVF2 + Synchronizaton overrun interrupt flag + 1 + 1 + read-only + + + SYNCOVF3 + Synchronizaton overrun interrupt flag + 2 + 1 + read-only + + + SYNCOVF4 + Synchronizaton overrun interrupt flag + 3 + 1 + read-only + + + SYNCOVF5 + Synchronizaton overrun interrupt flag + 4 + 1 + read-only + + + SYNCOVF6 + Synchronizaton overrun interrupt flag + 5 + 1 + read-only + + + SYNCOVF7 + Synchronizaton overrun interrupt flag + 6 + 1 + read-only + + + SYNCOVF8 + Synchronizaton overrun interrupt flag + 7 + 1 + read-only + + + + + MUXSYNCCLR + MUXSYNCCLR + Channel Interrupt Clear Flag Register + 0x174 + 0x20 + 0x00000000 + + + SYNCOVFC1 + Clear synchronizaton overrun interrupt flag + 0 + 1 + read-write + + + SYNCOVFC2 + Clear synchronizaton overrun interrupt flag + 1 + 1 + read-write + + + SYNCOVFC3 + Clear synchronizaton overrun interrupt flag + 2 + 1 + read-write + + + SYNCOVFC4 + Clear synchronizaton overrun interrupt flag + 3 + 1 + read-write + + + SYNCOVFC5 + Clear synchronizaton overrun interrupt flag + 4 + 1 + read-write + + + SYNCOVFC6 + Clear synchronizaton overrun interrupt flag + 5 + 1 + read-write + + + SYNCOVFC7 + Clear synchronizaton overrun interrupt flag + 6 + 1 + read-write + + + SYNCOVFC8 + Clear synchronizaton overrun interrupt flag + 7 + 1 + read-write + + + + + MUXGSTS + MUXGSTS + Generator Interrupt Status Register + 0x178 + 0x20 + 0x00000000 + + + TRGOVF1 + Trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVF2 + Trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVF3 + Trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVF4 + Trigger overrun interrupt flag + 3 + 1 + read-write + + + + + MUXGCLR + MUXGCLR + Generator Interrupt Clear Flag Register + 0x17C + 0x20 + 0x00000000 + + + TRGOVFC1 + Clear trigger overrun interrupt flag + 0 + 1 + read-write + + + + TRGOVFC2 + Clear trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVFC3 + Clear trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVFC4 + Clear trigger overrun interrupt flag + 3 + 1 + read-write + + + + + + + DMA1 + DMA controller + DMA + 0x40026400 + + 0x0 + 0x200 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 56 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 57 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 58 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 59 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 60 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 68 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 69 + + + + STS + STS + DMA interrupt status register + (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA interrupt flag clear register + (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register(DMA_C1CTRL) + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register (DMA_C2CTRL) + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register (DMA_C3CTRL) + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register (DMA_C4CTRL) + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register (DMA_C5CTRL) + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register(DMA_C6CTRL) + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register(DMA_C7CTRL) + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_MUXSEL + DMA_MUXSEL + DMAMUX Table Selection + 0x100 + 0x20 + 0x00000000 + + + TBL_SEL + Multiplexer Table Select + 0 + 1 + read-write + + + + + MUXC1CTRL + MUXC1CTRL + Channel 1 Configuration Register + 0x104 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC2CTRL + MUXC2CTRL + Channel 2 Configuration Register + 0x108 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC3CTRL + MUXC3CTRL + Channel 3 Configuration Register + 0x10C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC4CTRL + MUXC4CTRL + Channel 4 Configuration Register + 0x110 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC5CTRL + MUXC5CTRL + Channel 5 Configuration Register + 0x114 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC6CTRL + MUXC6CTRL + Channel 6 Configuration Register + 0x118 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC7CTRL + MUXC7CTRL + Channel 7 Configuration Register + 0x11C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXG1CTRL + MUXG1CTRL + Generator 1 Configuration Register + 0x120 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG2CTRL + MUXG2CTRL + Generator 2 Configuration Register + 0x124 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG3CTRL + MUXG3CTRL + Generator 3 Configuration Register + 0x128 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG4CTRL + MUXG4CTRL + Generator 4 Configuration Register + 0x12C + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXSYNCSTS + MUXSYNCSTS + Channel Interrupt Status Register + 0x130 + 0x20 + 0x00000000 + + + SYNCOVF1 + Synchronizaton overrun interrupt flag + 0 + 1 + read-only + + + SYNCOVF2 + Synchronizaton overrun interrupt flag + 1 + 1 + read-only + + + SYNCOVF3 + Synchronizaton overrun interrupt flag + 2 + 1 + read-only + + + SYNCOVF4 + Synchronizaton overrun interrupt flag + 3 + 1 + read-only + + + SYNCOVF5 + Synchronizaton overrun interrupt flag + 4 + 1 + read-only + + + SYNCOVF6 + Synchronizaton overrun interrupt flag + 5 + 1 + read-only + + + SYNCOVF7 + Synchronizaton overrun interrupt flag + 6 + 1 + read-only + + + + + MUXSYNCCLR + MUXSYNCCLR + Channel Interrupt Clear Flag Register + 0x134 + 0x20 + 0x00000000 + + + SYNCOVFC1 + Clear synchronizaton overrun interrupt flag + 0 + 1 + read-write + + + SYNCOVFC2 + Clear synchronizaton overrun interrupt flag + 1 + 1 + read-write + + + SYNCOVFC3 + Clear synchronizaton overrun interrupt flag + 2 + 1 + read-write + + + SYNCOVFC4 + Clear synchronizaton overrun interrupt flag + 3 + 1 + read-write + + + SYNCOVFC5 + Clear synchronizaton overrun interrupt flag + 4 + 1 + read-write + + + SYNCOVFC6 + Clear synchronizaton overrun interrupt flag + 5 + 1 + read-write + + + SYNCOVFC7 + Clear synchronizaton overrun interrupt flag + 6 + 1 + read-write + + + + + MUXGSTS + MUXGSTS + Generator Interrupt Status Register + 0x138 + 0x20 + 0x00000000 + + + TRGOVF1 + Trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVF2 + Trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVF3 + Trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVF4 + Trigger overrun interrupt flag + 3 + 1 + read-write + + + + + MUXGCLR + MUXGCLR + Generator Interrupt Clear Flag Register + 0x13C + 0x20 + 0x00000000 + + + TRGOVFC1 + Clear trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVFC2 + Clear trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVFC3 + Clear trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVFC4 + Clear trigger overrun interrupt flag + 3 + 1 + read-write + + + + + + + DMA2 + 0x40026600 + + + SDIO1 + Secure digital input/output + interface + SDIO + 0x4002C400 + + 0x0 + 0x400 + registers + + + SDIO1 + SDIO1 global interrupt + 49 + + + + PWRCTRL + PWRCTRL + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PS + Power switch + 0 + 2 + + + + + CLKCTRL + CLKCTRL + SD clock control register + (SDIO_CLKCTRL) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock division + 0 + 8 + + + CLKOEN + Clock output enable + 8 + 1 + + + PWRSVEN + Power saving mode enable + 9 + 1 + + + BYPSEN + Clock divider bypass enable + bit + 10 + 1 + + + BUSWS + Bus width selection + 11 + 2 + + + CLKEDS + SDIO_CK edge selection bit + 13 + 1 + + + HFCEN + Hardware flow control enable + 14 + 1 + + + CLKDIV98 + Clock divide factor bit9 and bit8 + 15 + 2 + + + + + ARGU + ARGU + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + ARGU + Command argument + 0 + 32 + + + + + CMDCTRL + CMDCTRL + SDIO command control register + (SDIO_CMDCTRL) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDIDX + CMDIDX + 0 + 6 + + + RSPWT + Wait for response + 6 + 2 + + + INTWT + CCSM wait for interrupt + 8 + 1 + + + PNDWT + CCSM wait for end of transfer + 9 + 1 + + + CCSMEN + Command channel state machine + 10 + 1 + + + IOSUSP + SD I/O suspend command + 11 + 1 + + + + + RSPCMD + RSPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RSPCMD + RSPCMD + 0 + 6 + + + + + RSP1 + RSP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTS1 + CARDSTATUS1 + 0 + 32 + + + + + RSP2 + RSP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS2 + 0 + 32 + + + + + RSP3 + RSP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS3 + 0 + 32 + + + + + RSP4 + RSP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS4 + 0 + 32 + + + + + DTTMR + DTTMR + Bits 31:0 = TIMEOUT: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Data timeout period + 0 + 32 + + + + + DTLEN + DTLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DTLEN + Data length value + 0 + 25 + + + + + DTCTRL + DTCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TFREN + DTEN + 0 + 1 + + + TFRDIR + DTDIR + 1 + 1 + + + TFRMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + BLKSIZE + DBLOCKSIZE + 4 + 4 + + + RDWTSTART + PWSTART + 8 + 1 + + + RDWTSTOP + PWSTOP + 9 + 1 + + + RDWTMODE + RWMOD + 10 + 1 + + + IOEN + SD I/O function enable + 11 + 1 + + + + + DTCNT + DTCNT + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + CNT + Data count value + 0 + 25 + + + + + STS + STS + SDIO status register + (SDIO_STA) + 0x34 + 0x20 + read-only + 0x00000000 + + + CMDFAIL + Command crc fail + 0 + 1 + + + DTFAIL + Data crc fail + 1 + 1 + + + CMDTIMEOUT + Command timeout + 2 + 1 + + + DTTIMEOUT + Data timeout + 3 + 1 + + + TXERRU + Tx under run error + 4 + 1 + + + RXERRO + Rx over run error + 5 + 1 + + + CMDRSPCMPL + Command response complete + 6 + 1 + + + CMDCMPL + Command sent + 7 + 1 + + + DTCMPL + Data sent + 8 + 1 + + + SBITERR + Start bit error + 9 + 1 + + + DTBLKCMPL + Data block sent + 10 + 1 + + + DOCMD + Command transfer in progress + 11 + 1 + + + DOTX + Data transmit in progress + 12 + 1 + + + DORX + Data receive in progress + 13 + 1 + + + TXBUFH + Tx buffer half empty + 14 + 1 + + + RXBUFH + Rx buffer half empty + 15 + 1 + + + TXBUFF + Tx buffer full + 16 + 1 + + + RXBUFF + Rx buffer full + 17 + 1 + + + TXBUFE + Tx buffer empty + 18 + 1 + + + RXBUFE + Rx buffer empty + 19 + 1 + + + TXBUF + Tx data vaild + 20 + 1 + + + RXBUF + Rx data vaild + 21 + 1 + + + IOIF + SD I/O interrupt + 22 + 1 + + + + + INTCLR + INTCLR + SDIO interrupt clear register + (SDIO_INTCLR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CMDFAIL + Command crc fail flag clear + 0 + 1 + + + DTFAIL + Data crc fail flag clear + 1 + 1 + + + CMDTIMEOUT + Command timeout flag clear + 2 + 1 + + + DTTIMEOUT + Data timeout flag clear + 3 + 1 + + + TXERRU + Tx under run error flag clear + 4 + 1 + + + RXERRU + Rx over run error flag clear + 5 + 1 + + + CMDRSPCMPL + Command response complete flag clear + 6 + 1 + + + CMDCMPL + Command sent flag clear + 7 + 1 + + + DTCMPL + Data sent flag clear + 8 + 1 + + + SBITERR + Start bit error flag clear + 9 + 1 + + + DTBLKCMPL + Data block sent clear + 10 + 1 + + + IOIF + SD I/O interrupt flag clear + 22 + 1 + + + + + INTEN + INTEN + SDIO mask register (SDIO_MASK) + 0x3C + 0x20 + read-write + 0x00000000 + + + CMDFAILIEN + Command crc fail interrupt enable + 0 + 1 + + + DTFAILIEN + Data crc fail interrupt enable + 1 + 1 + + + CMDTIMEOUTIEN + Command timeout interrupt enable + 2 + 1 + + + DTTIMEOUTIEN + Data timeout interrupt enable + 3 + 1 + + + TXERRUIEN + Tx under run interrupt enable + 4 + 1 + + + RXERRUIEN + Rx over run interrupt enable + 5 + 1 + + + CMDRSPCMPLIEN + Command response complete interrupt enable + 6 + 1 + + + CMDCMPLIEN + Command sent complete interrupt enable + 7 + 1 + + + DTCMPLIEN + Data sent complete interrupt enable + 8 + 1 + + + SBITERRIEN + Start bit error interrupt enable + 9 + 1 + + + DTBLKCMPLIEN + Data block sent complete interrupt enable + 10 + 1 + + + DOCMDIEN + Command acting interrupt enable + 11 + 1 + + + DOTXIEN + Data transmit acting interrupt enable + 12 + 1 + + + DORXIEN + Data receive acting interrupt enable + 13 + 1 + + + TXBUFHIEN + Tx buffer half empty interrupt enable + 14 + 1 + + + RXBUFHIEN + Rx buffer half empty interrupt enable + 15 + 1 + + + TXBUFFIEN + Tx buffer full interrupt enable + 16 + 1 + + + RXBUFFIEN + Rx buffer full interrupt enable + 17 + 1 + + + TXBUFEIEN + Tx buffer empty interrupt enable + 18 + 1 + + + RXBUFEIEN + Rx buffer empty interrupt enable + 19 + 1 + + + TXBUFIEN + Tx buffer data vaild interrupt enable + 20 + 1 + + + RXBUFIEN + Rx buffer data vaild interrupt enable + 21 + 1 + + + IOIFIEN + SD I/O interrupt enable + 22 + 1 + + + + + BUFCNT + BUFCNT + Bits 23:0 = BUFCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + FIF0COUNT + 0 + 24 + + + + + BUF + BUF + bits 31:0 = Buffer Data: Receive and transmit + buffer data + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Buffer data + 0 + 32 + + + + + + + SDIO2 + 0x50061000 + + SDIO2 + SDIO2 global interrupt + 102 + + + + ERTC + Real-time clock + ERTC + 0x40002800 + + 0x0 + 0x400 + registers + + + + TIME + TIME + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + AMPM + AM/PM notation + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + DATE + DATE + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens + 20 + 4 + + + YU + Year units + 16 + 4 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + CTRL + CTRL + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + CALOEN + Calibration output enable + 23 + 1 + + + OUTSEL + Output source selection + 21 + 2 + + + OUTP + Output polarity + 20 + 1 + + + CALOSEL + Calibration output selection + 19 + 1 + + + BPR + Battery power domain data register + 18 + 1 + + + DEC1H + Decrease 1 hour + 17 + 1 + + + ADD1H + Add 1 hour + 16 + 1 + + + TSIEN + Timestamp interrupt enable + 15 + 1 + + + WATIEN + Wakeup timer interrupt enable + 14 + 1 + + + ALBIEN + Alarm B interrupt enable + 13 + 1 + + + ALAIEN + Alarm A interrupt enable + 12 + 1 + + + TSEN + Timestamp enable + 11 + 1 + + + WATEN + Wakeup timer enable + 10 + 1 + + + ALBEN + Alarm B enable + 9 + 1 + + + ALAEN + Alarm A enable + 8 + 1 + + + CCALEN + Coarse calibration enable + 7 + 1 + + + HM + Hour mode + 6 + 1 + + + DREN + Date/time register direct read enable + 5 + 1 + + + RCDEN + Reference clock detection enable + 4 + 1 + + + TSEDG + Timestamp trigger edge + 3 + 1 + + + WATCLK + Wakeup timer clock selection + 0 + 3 + + + + + STS + STS + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALAWF + Alarm A register allows write flag + 0 + 1 + read-only + + + ALBWF + Alarm B register allows write flag + 1 + 1 + read-only + + + WATWF + Wakeup timer register allows write flag + 2 + 1 + read-only + + + TADJF + Time adjustment flag + 3 + 1 + read-write + + + INITF + Calendar initialization flag + 4 + 1 + read-only + + + UPDF + Calendar update flag + 5 + 1 + read-write + + + IMF + Enter initialization mode flag + 6 + 1 + read-only + + + IMEN + Initialization mode enable + 7 + 1 + read-write + + + ALAF + Alarm A flag + 8 + 1 + read-write + + + ALBF + Alarm B flag + 9 + 1 + read-write + + + WATF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Timestamp flag + 11 + 1 + read-write + + + TSOF + Timestamp overflow flag + 12 + 1 + read-write + + + TP1F + Tamper detection 1 flag + 13 + 1 + read-write + + + TP2F + Tamper detection 2 flag + 14 + 1 + read-write + + + CALUPDF + Calibration value update completed flag + 16 + 1 + read-only + + + + + DIV + DIV + Diveder register + 0x10 + 0x20 + read-write + 0x007F00FF + + + DIVA + Diveder A + 16 + 7 + + + DIVB + Diveder B + 0 + 15 + + + + + WAT + WAT + Wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + VAL + Wakeup timer reload value + 0 + 16 + + + + + CCAL + CCAL + Calibration register + 0x18 + 0x20 + read-write + 0x00000000 + + + CALDIR + Calibration direction + 7 + 1 + + + CALVAL + Calibration value + 0 + 5 + + + + + ALA + ALA + Alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + ALB + ALB + Alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + WP + WP + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 8 + + + + + SBS + SBS + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + TADJ + TADJ + time adjust register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add 1 second + 31 + 1 + + + DECSBS + Decrease sub-second value + 0 + 15 + + + + + TSTM + TSTM + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + AMPM + AMPM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + TSDT + TSDT + timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + TSSBS + TSSBS + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + SCAL + SCAL + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + ADD + Add ERTC clock + 15 + 1 + + + CAL8 + 8-second calibration period + 14 + 1 + + + CAL16 + 16 second calibration period + 13 + 1 + + + DEC + Decrease ERTC clock + 0 + 9 + + + + + TAMP + TAMP + tamper and alternate function configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + OUTTYPE + Output type + 18 + 1 + + + TSPIN + Time stamp detection pin selection + 17 + 1 + + + TP1PIN + Tamper detection pin selection + 16 + 1 + + + TPPU + Tamper detection pull-up + 15 + 1 + + + TPPR + Tamper detection pre-charge time + 13 + 2 + + + TPFLT + Tamper detection filter time + 11 + 2 + + + TPFREQ + Tamper detection frequency + 8 + 3 + + + TPTSEN + Tamper detection timestamp enable + 7 + 1 + + + TP2EDG + Tamper detection 2 valid edge + 4 + 1 + + + TP2EN + Tamper detection 2 enable + 3 + 1 + + + TPIEN + Tamper detection interrupt enable + 2 + 1 + + + TP1EDG + Tamper detection 1 valid edge + 1 + 1 + + + TP1EN + Tamper detection 1 enable + 0 + 1 + + + + + ALASBS + ALASBS + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + ALBSBS + ALBSBS + alarm B sub second register + 0x48 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + BPR1DT + BPR1DT + Battery powered domain register + 0x50 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR2DT + BPR2DT + Battery powered domain register + 0x54 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR3DT + BPR3DT + Battery powered domain register + 0x58 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR4DT + BPR4DT + Battery powered domain register + 0x5C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR5DT + BPR5DT + Battery powered domain register + 0x60 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR6DT + BPR6DT + Battery powered domain register + 0x64 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR7DT + BPR7DT + Battery powered domain register + 0x68 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR8DT + BPR8DT + Battery powered domain register + 0x6C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR9DT + BPR9DT + Battery powered domain register + 0x70 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR10DT + BPR10DT + Battery powered domain register + 0x74 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR11DT + BPR11DT + Battery powered domain register + 0x78 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR12DT + BPR12DT + Battery powered domain register + 0x7C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR13DT + BPR13DT + Battery powered domain register + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR14DT + BPR14DT + Battery powered domain register + 0x84 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR15DT + BPR15DT + Battery powered domain register + 0x88 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR16DT + BPR16DT + Battery powered domain register + 0x8C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR17DT + BPR17DT + Battery powered domain register + 0x90 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR18DT + BPR18DT + Battery powered domain register + 0x94 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR19DT + BPR19DT + Battery powered domain register + 0x98 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR20DT + BPR20DT + Battery powered domain register + 0x9C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + + + WDT + Watchdog + WDT + 0x40003000 + + 0x0 + 0x400 + registers + + + + CMD + CMD + Command register + 0x0 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 16 + + + + + DIV + DIV + Division register + 0x4 + 0x20 + read-write + 0x00000000 + + + DIV + Division divider + 0 + 3 + + + + + RLD + RLD + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RLD + Reload value + 0 + 12 + + + + + STS + STS + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + DIVF + Division value update complete flag + 0 + 1 + + + RLDF + Reload value update complete flag + 1 + 1 + + + WINF + Window value update complete flag + 2 + 1 + + + + + WIN + WIN + Window register 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control register + 0x48 + 0x20 + read-write + 0x0000 + + + DTB + DMA transfer bytes + 8 + 5 + + + ADDR + DMA transfer address offset + 0 + 5 + + + + + DMADT + DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + CM3_OUTPUT + CM3_OUTPUT + Channel output mode register + 0x70 + 0x20 + read-write + 0x00000000 + + + C5OSEN + Channel 5 output switch enable + 7 + 1 + + + C5OCTRL + Channel 5 output control + 4 + 3 + + + C5OBEN + Channel 5 output buffer enable + 3 + 1 + + + C5OIEN + Channel 5 output immediately enable + 2 + 1 + + + + + C5DT + C5DT + Channel 5 data register + 0x74 + 0x20 + read-write + 0x00000000 + + + C5DT + Channel 5 data register + 0 + 16 + + + + + + + TMR8 + 0x40010400 + + TMR8_BRK_TMR12 + TMR8 brake interrupt and TMR12 global + interrupt + 43 + + + TMR8_OVF_TMR13 + TMR8 overflow interrupt and TMR13 global + interrupt + 44 + + + TMR8_TRG_HALL_TMR14 + TMR8 trigger and HALL interrupts and + TMR14 global interrupt + 45 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Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + TRGSWTR + Trigger event triggered by software + 6 + 1 + + + C4SWTR + Channel 4 event triggered by software + 4 + 1 + + + C3SWTR + Channel 3 event triggered by software + 3 + 1 + + + C2SWTR + Channel 2 event triggered by software + 2 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C2OSEN + Channel 2 output switch enable + 15 + 1 + + + C2OCTRL + Channel 2 output control + 12 + 3 + + + C2OBEN + Channel 2 output buffer enable + 11 + 1 + + + C2OIEN + Channel 2 output immediately enable + 10 + 1 + + + C2C + Channel 2 configure + 8 + 2 + + + C1OSEN + Channel 1 output switch enable + 7 + 1 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 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Channel 2 Polarity + 5 + 1 + + + C2EN + Channel 2 enable + 4 + 1 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1CEN + Channel 1 complementary enable + 2 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + C2DT + C2DT + Channel 2 data register + 0x38 + 0x20 + read-write + 0x00000000 + + + C2DT + Channel 2 data register + 0 + 16 + + + + + + + TMR12 + 0x40001800 + + TMR8_BRK_TMR12 + TMR8 brake interrupt and TMR12 global + interrupt + 43 + + + + TMR10 + General purpose timer + TIMER + 0x40014400 + + 0x0 + 0x400 + registers + + + TMR1_OVF_TMR10 + TMR1 overflow interrupt and TMR10 global + interrupt + 25 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + C1IEN + Channel 1 interrupt + enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + + + TMR11 + 0x40014800 + + TMR1_TRG_HALL_TMR11 + TMR1 trigger and HALL interrupts and + TMR11 global interrupt + 26 + + + + TMR13 + 0x40001C00 + + TMR8_OVF_TMR13 + TMR8 overflow interrupt and TMR13 global + interrupt + 44 + + + + TMR14 + 0x40002000 + + TMR8_TRG_HALL_TMR14 + TMR8 trigger and HALL interrupts and + TMR14 global interrupt + 45 + + + + TMR6 + Basic timer + TIMER + 0x40001000 + + 0x0 + 0x400 + registers + + + TMR6 + TMR6 global interrupt + 54 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + PTOS + Primary TMR output selection + 4 + 3 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + + + TMR7 + 0x40001400 + + TMR7 + TMR7 global interrupt + 55 + + + + ACC + HSI Auto Clock Calibration + ACC + 0x40017400 + + 0x0 + 0x400 + registers + + + + STS + STS + status register + 0x0 + 0x20 + 0x0000 + + + RSLOST + Reference Signal Lost + read-write + 1 + 1 + + + CALRDY + Internal high-speed clock calibration ready + read-write + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x04 + 0x20 + 0x0100 + + + STEP + STEP + read-write + 8 + 4 + + + CALRDYIEN + CALRDY interrupt enable + read-write + 5 + 1 + + + EIEN + RSLOST error interrupt enable + read-write + 4 + 1 + + + SOFSEL + SOF Select + read-write + 2 + 1 + + + ENTRIM + Enable trim + read-write + 1 + 1 + + + CALON + Calibration on + read-write + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x08 + 0x20 + 0x2080 + + + HICKTWK + Internal high-speed auto clock trimming + read-only + 8 + 6 + + + HICKCAL + Internal high-speed auto clock calibration + read-only + 0 + 8 + + + + + C1 + C1 + compare value 1 + 0x0C + 0x20 + 0x1F2C + + + C1 + Compare 1 + read-write + 0 + 16 + + + + + C2 + C2 + compare value 2 + 0x10 + 0x20 + 0x1F40 + + + C2 + Compare 2 + read-write + 0 + 16 + + + + + C3 + C3 + compare value 3 + 0x14 + 0x20 + 0x1F54 + + + C3 + Compare 3 + read-write + 0 + 16 + + + + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EVT + I2C1 event interrupt + 31 + + + I2C1_ERR + I2C1 error interrupt + 32 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + 0x00000000 + + + I2CEN + I2C peripheral enable + 0 + 1 + read-write + + + TDIEN + Transmit data interrupt enable + 1 + 1 + read-write + + + RDIEN + Receive data interrupt enable + 2 + 1 + read-write + + + ADDRIEN + Address match interrupt enable + 3 + 1 + read-write + + + ACKFAILIEN + Acknowledge fail interrupt enable + 4 + 1 + read-write + + + STOPIEN + Stop generation complete interrupt enable + 5 + 1 + read-write + + + TDCIEN + Transfer data complete interrupt enable + 6 + 1 + read-write + + + ERRIEN + Error interrupts enable + 7 + 1 + read-write + + + DFLT + Digital filter value + 8 + 4 + read-write + + + DMATEN + DMA Transmit data request enable + 14 + 1 + read-write + + + DMAREN + DMA receive data request enable + 15 + 1 + read-write + + + SCTRL + Slave receiving data control + 16 + 1 + read-write + + + STRETCH + Clock stretching mode + 17 + 1 + read-write + + + GCAEN + General call address enable + 19 + 1 + read-write + + + HADDREN + SMBus host address enable + 20 + 1 + read-write + + + DEVADDREN + SMBus device default address enable + 21 + 1 + read-write + + + SMBALERT + SMBus alert enable / pin set + 22 + 1 + read-write + + + PECEN + PEC calculation enable + 23 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECTEN + Request PEC transmission enable + 26 + 1 + + + ASTOPEN + Automatically send stop condition enable + 25 + 1 + + + RLDEN + Send data reload mode enable + 24 + 1 + + + CNT + Transmit data counter + 16 + 8 + + + NACKEN + Not acknowledge enable + 15 + 1 + + + GENSTOP + Generate stop condition + 14 + 1 + + + GENSTART + Generate start condition + 13 + 1 + + + READH10 + 10-bit address header read enable + 12 + 1 + + + ADDR10 + Host send 10-bit address mode enable + 11 + 1 + + + DIR + Master data transmission direction + 10 + 1 + + + SADDR + Slave address + 0 + 10 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + ADDR1 + Interface address + 0 + 10 + + + ADDR1MODE + Own Address mode + 10 + 1 + + + ADDR1EN + Own address 1 enable + 15 + 1 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2MASK + Own address 2-bit mask + 8 + 3 + + + ADDR2EN + Own address 2 enable + 15 + 1 + + + + + CLKCTRL + CLKCTRL + Clock contorl register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low level + 0 + 8 + + + SCLH + SCL high level + 8 + 8 + + + SDAD + SDA output delay + 16 + 4 + + + SCLD + SCL output delay + 20 + 4 + + + DIVH + High 4 bits of clock divider value + 24 + 4 + + + DIVL + Low 4 bits of clock divider value + 28 + 4 + + + + + TIMEOUT + TIMEOUT + Timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + TOTIME + Clock timeout detection time + 0 + 12 + + + TOMOED + Clock timeout detection mode + 12 + 1 + + + TOEN + Detect clock low/high timeout enable + 15 + 1 + + + EXTTIME + Cumulative clock low extend timeout value + 16 + 12 + + + EXTEN + Cumulative clock low extend timeout enable + 31 + 1 + + + + + STS + STS + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDR + Slave address matching value + 17 + 7 + read-only + + + SDIR + Slave data transmit direction + 16 + 1 + read-only + + + BUSYF + Bus busy + 15 + 1 + read-only + + + ALERTF + SMBus alert flag + 13 + 1 + read-only + + + TMOUT + SMBus timeout flag + 12 + 1 + read-only + + + PECERR + PEC receive error flag + 11 + 1 + read-only + + + OUF + Overflow or underflow flag + 10 + 1 + read-only + + + ARLOST + Arbitration lost flag + 9 + 1 + read-only + + + BUSERR + Bus error flag + 8 + 1 + read-only + + + TCRLD + Transmission is complete, waiting to load data + 7 + 1 + read-only + + + TDC + Transmit data complete flag + 6 + 1 + read-only + + + STOPF + Stop condition generation complete flag + 5 + 1 + read-only + + + ACKFAIL + Acknowledge failure flag + 4 + 1 + read-only + + + ADDRF + 0~7 bit address match flag + 3 + 1 + read-only + + + RDBF + Receive data buffer full flag + 2 + 1 + read-only + + + TDIS + Send interrupt status + 1 + 1 + read-write + + + TDBE + Transmit data buffer empty flag + 0 + 1 + read-write + + + + + CLR + CLR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTC + Clear SMBus alert flag + 13 + 1 + + + TMOUTC + Clear SMBus timeout flag + 12 + 1 + + + PECERRC + Clear PEC receive error flag + 11 + 1 + + + OUFC + Clear overload / underload flag + 10 + 1 + + + ARLOSTC + Clear arbitration lost flag + 9 + 1 + + + BUSERRC + Clear bus error flag + 8 + 1 + + + STOPC + Clear stop condition generation complete flag + 5 + 1 + + + ACKFAILC + Clear acknowledge failure flag + 4 + 1 + + + ADDRC + Clear 0~7 bit address match flag + 3 + 1 + + + + + PEC + PEC + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PECVAL + PEC value + 0 + 8 + + + + + RXDT + RXDT + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + DT + Receive data register + 0 + 8 + + + + + TXDT + TXDT + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + DT + Transmit data register + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 33 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + I2C3 + 0x40005C00 + + I2C3_EVT + I2C3 event interrupt + 72 + + + I2C3_ERR + I2C3 error interrupt + 73 + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3EN + Master clock frequency3 division enable + 9 + 1 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + TIEN + TI mode enable + 4 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + CSPAS + CS pulse abnormal setting fiag + 8 + 1 + read-write + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + SPI4 + 0x40013400 + + SPI4 + SPI4 global interrupt + 84 + + + + I2S2_EXT + 0x40017800 + + + I2S3_EXT + 0x40017C00 + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40011000 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + DBN1 + high bit for Data bit num + 28 + 1 + + + TSDT + transmit start delay time + 21 + 5 + + + TCDT + transmit complete delay time + 16 + 5 + + + UEN + USART enable + 13 + 1 + + + DBN0 + low bit for Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + ID7_4 + bit 7-4 for usart identification + 28 + 4 + + + TRPSWAP + Transmit receive pin swap + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + IDBN + Identification bit num + 4 + 1 + + + ID3_0 + bit 3-0 for usart identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + DEP + DE polarity selection + 15 + 1 + + + RS485EN + RS485 enable + 14 + 1 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + USART6 + 0x40011400 + + USART6 + USART6 global interrupt + 71 + + + + ADC1 + Analog to digital converter + ADC + 0x40012000 + + 0x0 + 0x100 + registers + + + ADC + ADC1 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + RDY + ADC ready to conversion flag + 6 + 1 + read-only + + + OCCO + Ordinary channel conversion overflow flag + 5 + 1 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + OCCE + Ordinary channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCCOIEN + Ordinary channel conversion overflow interrupt enable + 26 + 1 + + + CRSEL + Conversion resolution select + 24 + 2 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + OCCEIEN + Ordinary channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 31 + 1 + + + OCSWTRG + Ordinary channel software conversion trigger + 30 + 1 + + + OCETE + Ordinary channel external trigger edge select + 28 + 2 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 24 + 4 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 23 + 1 + + + PCSWTRG + Preempted channel software conversion trigger + 22 + 1 + + + PCETE + Preempted channel external trigger edge select + 20 + 2 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 16 + 4 + + + DTALIGN + Data alignment + 11 + 1 + + + EOCSFEN + Each ordinary channel conversion set OCCE flag enable + 10 + 1 + + + OCDRCEN + Ordinary channel DMA request continuation enable for independent mode + 9 + 1 + + + OCDMAEN + Ordinary channel DMA transfer enable for independent mode + 8 + 1 + + + ADABRT + ADC conversion abort + 4 + 1 + + + ADCALINIT + Initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT18 + Selection sample time of channel ADC_IN18 + 24 + 3 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + OVSP + OVSP + oversampling register + 0x80 + 0x20 + read-write + 0x00000000 + + + OOSRSEL + Ordinary oversampling recovery mode select + 10 + 1 + + + OOSTREN + Ordinary oversampling trigger mode enable + 9 + 1 + + + OSSSEL + Oversampling shift select + 5 + 4 + + + OSRSEL + Oversampling ratio select + 2 + 3 + + + POSEN + Preempted oversampling enable + 1 + 1 + + + OOSEN + Ordinary oversampling enable + 0 + 1 + + + + + CALVAL + CALVAL + Calibration value register + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALVAL + A/D Calibration value + 0 + 7 + + + + + + + ADC2 + 0x40012100 + + ADC + ADC2 global interrupts + 18 + + + + ADC3 + 0x40012200 + + ADC + ADC3 global interrupts + 18 + + + + ADCCOM + ADC common area + ADC + 0x40012300 + + 0x0 + 0x100 + registers + + + + CSTS + CSTS + Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + RDY3 + ADC ready to conversion flag of ADC3 + 22 + 1 + + + OCCO3 + Ordinary channel conversion overflow flag of ADC3 + 21 + 1 + + + OCCS3 + Ordinary channel conversion start flag of ADC3 + 20 + 1 + + + PCCS3 + Preempted channel conversion start flag of ADC3 + 19 + 1 + + + PCCE3 + Preempted channels conversion end flag of ADC3 + 18 + 1 + + + OCCE3 + Ordinary channels conversion end flag of ADC3 + 17 + 1 + + + VMOR3 + Voltage monitoring out of range flag of ADC3 + 16 + 1 + + + RDY2 + ADC ready to conversion flag of ADC2 + 14 + 1 + + + OCCO2 + Ordinary channel conversion overflow flag of ADC2 + 13 + 1 + + + OCCS2 + Ordinary channel conversion start flag of ADC2 + 12 + 1 + + + PCCS2 + Preempted channel conversion start flag of ADC2 + 11 + 1 + + + PCCE2 + Preempted channels conversion end flag of ADC2 + 10 + 1 + + + OCCE2 + Ordinary channels conversion end flag of ADC2 + 9 + 1 + + + VMOR2 + Voltage monitoring out of range flag of ADC2 + 8 + 1 + + + RDY1 + ADC ready to conversion flag of ADC1 + 6 + 1 + + + OCCO1 + Ordinary channel conversion overflow flag of ADC1 + 5 + 1 + + + OCCS1 + Ordinary channel conversion start flag of ADC1 + 4 + 1 + + + PCCS1 + Preempted channel conversion start flag of ADC1 + 3 + 1 + + + PCCE1 + Preempted channels conversion end flag of ADC1 + 2 + 1 + + + OCCE1 + Ordinary channels conversion end flag of ADC1 + 1 + 1 + + + VMOR1 + Voltage monitoring out of range flag of ADC1 + 0 + 1 + + + + + CCTRL + CCTRL + Common control register + 0x4 + 0x20 + read-write + 0x00000000 + + + MSDMASEL_H + High bit of ordinary channel DMA transfer mode select for master slave mode + 28 + 1 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + 1 + + + VBATEN + VBAT enable + 22 + 1 + + + ADCDIV + ADC division + 16 + 4 + + + MSDMASEL_L + Low bit of ordinary channel DMA transfer mode select for master slave mode + 14 + 2 + + + MSDRCEN + Ordinary channel DMA request continuation enable for master slave mode + 13 + 1 + + + ASISEL + Adjacent ADC sampling interval select for ordinary shifting mode + 8 + 4 + + + MSSEL + Master slave mode select + 0 + 5 + + + + + CODT + CODT + Common Ordinary data register + 0x8 + 0x20 + read-only + 0x00000000 + + + CODTH + Ordinary conversion high halfword data for master slave mode + 16 + 16 + + + CODTL + Ordinary conversion low halfword data for master slave mode + 0 + 16 + + + + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1_TX + CAN1 TX interrupt + 19 + + + CAN1_RX0 + CAN1 RX0 interrupt + 20 + + + CAN_RX1 + CAN1 RX1 interrupt + 21 + + + CAN_SE + CAN1 SE interrupt + 22 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC 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LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + FMSEL14 + Filter mode select + 14 + 1 + + + FMSEL15 + Filter mode select + 15 + 1 + + + FMSEL16 + Filter mode select + 16 + 1 + + + FMSEL17 + Filter mode select + 17 + 1 + + + FMSEL18 + Filter mode select + 18 + 1 + + + FMSEL19 + Filter mode select + 19 + 1 + + + FMSEL20 + Filter mode select + 20 + 1 + + + FMSEL21 + Filter mode select + 21 + 1 + + + FMSEL22 + Filter mode select + 22 + 1 + + + FMSEL23 + Filter mode select + 23 + 1 + + + FMSEL24 + Filter mode select + 24 + 1 + + + FMSEL25 + Filter mode select + 25 + 1 + + + FMSEL26 + Filter mode select + 26 + 1 + + + FMSEL27 + Filter mode select + 27 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + FBWSEL14 + Filter bit width select + 14 + 1 + + + FBWSEL15 + Filter bit width select + 15 + 1 + + + FBWSEL16 + Filter bit width select + 16 + 1 + + + FBWSEL17 + Filter bit width select + 17 + 1 + + + FBWSEL18 + Filter bit width select + 18 + 1 + + + FBWSEL19 + Filter bit width select + 19 + 1 + + + FBWSEL20 + Filter bit width select + 20 + 1 + + + FBWSEL21 + Filter bit width select + 21 + 1 + + + FBWSEL22 + Filter bit width select + 22 + 1 + + + FBWSEL23 + Filter bit width select + 23 + 1 + + + FBWSEL24 + Filter bit width select + 24 + 1 + + + FBWSEL25 + Filter bit width select + 25 + 1 + + + FBWSEL26 + Filter bit width select + 26 + 1 + + + FBWSEL27 + Filter bit width select + 27 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + FRFSEL14 + Filter relation FIFO select + 14 + 1 + + + FRFSEL15 + Filter relation FIFO select + 15 + 1 + + + FRFSEL16 + Filter relation FIFO select + 16 + 1 + + FRFSEL17 + Filter relation FIFO select + 17 + 1 + + + FRFSEL18 + Filter relation FIFO select + 18 + 1 + + + FRFSEL19 + Filter relation FIFO select + 19 + 1 + + + FRFSEL20 + Filter relation FIFO select + 20 + 1 + + + FRFSEL21 + Filter relation FIFO select + 21 + 1 + + + FRFSEL22 + Filter relation FIFO select + 22 + 1 + + + FRFSEL23 + Filter relation FIFO select + 23 + 1 + + + FRFSEL24 + Filter relation FIFO select + 24 + 1 + + + FRFSEL25 + Filter relation FIFO select + 25 + 1 + + + FRFSEL26 + Filter relation FIFO select + 26 + 1 + + + FRFSEL27 + Filter relation FIFO select + 27 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + FAEN14 + Filter activate enable + 14 + 1 + + FAEN15 + Filter activate enable + 15 + 1 + + + FAEN16 + Filter activate enable + 16 + 1 + + + FAEN17 + Filter activate enable + 17 + 1 + + + FAEN18 + Filter activate enable + 18 + 1 + + + FAEN19 + Filter activate enable + 19 + 1 + + + FAEN20 + Filter activate enable + 20 + 1 + + + FAEN21 + Filter activate enable + 21 + 1 + + + FAEN22 + Filter activate enable + 22 + 1 + + + FAEN23 + Filter activate enable + 23 + 1 + + + FAEN24 + Filter activate enable + 24 + 1 + + + FAEN25 + Filter activate enable + 25 + 1 + + + FAEN26 + Filter activate enable + 26 + 1 + + + FAEN27 + Filter activate enable + 27 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB2 + F1FB2 + Filter bank 1 filtrate bit register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data 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bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F24FB2 + F24FB2 + Filter bank 24 filtrate bit register 2 + 0x304 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F25FB1 + F25FB1 + Filter bank 25 filtrate bit register 1 + 0x308 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F25FB2 + F25FB2 + Filter bank 25 filtrate bit register 2 + 0x30C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F26FB1 + F26FB1 + Filter bank 26 filtrate bit register 1 + 0x310 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F26FB2 + F26FB2 + Filter bank 26 filtrate bit register 2 + 0x314 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F27FB1 + F27FB1 + Filter bank 27 filtrate bit register 1 + 0x318 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F27FB2 + F27FB2 + Filter bank 27 filtrate bit register 2 + 0x31C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + + + CAN2 + 0x40006800 + + CAN2_TX + CAN2 TX interrupt + 63 + + + CAN2_RX0 + CAN2 RX0 interrupt + 64 + + + CAN2_RX1 + CAN2 RX1 interrupt + 65 + + + CAN2_SE + CAN2 SE interrupt + 66 + + + + DAC + Digital to analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Control register (DAC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + D1EN + DAC1 enable + 0 + 1 + + + D1OBDIS + DAC1 output buffer disable + 1 + 1 + + + D1TRGEN + DAC1 trigger enable + 2 + 1 + + + D1TRGSEL + DAC1 trigger selection + 3 + 3 + + + D1NM + DAC1 noise/triangle wave generation enable + 6 + 2 + + + D1NBSEL + DAC1 mask/amplitude selector + 8 + 4 + + + D1DMAEN + DAC1 DMA enable + 12 + 1 + + + D1DMAUDRIEN + DAC1 DMA underrun interrupt enable + 13 + 1 + + + D2EN + DAC2 enable + 16 + 1 + + + D2OBDIS + DAC2 output buffer disable + 17 + 1 + + + D2TRGEN + DAC2 trigger enable + 18 + 1 + + + D2TRGSEL + DAC2 trigger selection + 19 + 3 + + + D2NM + DAC2 noise/triangle wave generation enable + 22 + 2 + + + D2NBSEL + DAC2 mask/amplitude selector + 24 + 4 + + + D2DMAEN + DAC2 DMA enable + 28 + 1 + + + D2DMAUDRIEN + DAC2 DMA underrun interrupt enable + 29 + 1 + + + + + SWTRG + SWTRG + DAC software trigger register(DAC_SWTRIGR) + 0x4 + 0x20 + write-only + 0x00000000 + + + D1SWTRG + DAC1 software trigger + 0 + 1 + + + D2SWTRG + DAC2 software trigger + 1 + 1 + + + + + D1DTH12R + D1DTH12R + DAC1 12-bit right-aligned data holding register(DAC_D1DTH12R) + 0x8 + 0x20 + read-write + 0x00000000 + + + D1DT12R + DAC1 12-bit right-aligned data + 0 + 12 + + + + + D1DTH12L + D1DTH12L + DAC1 12-bit left aligned data holding register (DAC_D1DTH12L) + 0xC + 0x20 + read-write + 0x00000000 + + + D1DT12L + DAC1 12-bit left-aligned data + 4 + 12 + + + + + D1DTH8R + D1DTH8R + DAC1 8-bit right aligned data holding register (DAC_D1DTH8R) + 0x10 + 0x20 + read-write + 0x00000000 + + + D1DT8R + DAC1 8-bit right-aligned data + 0 + 8 + + + + + D2DTH12R + D2DTH12R + DAC2 12-bit right aligned data holding register (DAC_D2DTH12R) + 0x14 + 0x20 + read-write + 0x00000000 + + + D2DT12R + DAC2 12-bit right-aligned + data + 0 + 12 + + + + + D2DTH12L + D2DTH12L + DAC2 12-bit left aligned data holding register (DAC_D2DTH12L) + 0x18 + 0x20 + read-write + 0x00000000 + + + D2DT12L + DAC2 12-bit left-aligned data + 4 + 12 + + + + + D2DTH8R + D2DTH8R + DAC2 8-bit right-aligned data holding register (DAC_D2DTH8R) + 0x1C + 0x20 + read-write + 0x00000000 + + + D2DT8R + DAC2 8-bit right-aligned + data + 0 + 8 + + + + + DDTH12R + DDTH12R + Dual DAC 12-bit right-aligned data holding register (DAC_DDTH12R), Bits 31:28 Reserved, Bits 15:12 Reserved + 0x20 + 0x20 + read-write + 0x00000000 + + + DD1DT12R + DAC1 12-bit right-aligned data + 0 + 12 + + + DD2DT12R + DAC2 12-bit right-aligned data + 16 + 12 + + + + + DDTH12L + DDTH12L + DUAL DAC 12-bit left aligned data holding register (DAC_DDTH12L), Bits 19:16 Reserved, Bits 3:0 Reserved + 0x24 + 0x20 + read-write + 0x00000000 + + + DD1DT12L + DAC1 12-bit left-aligned data + 4 + 12 + + + DD2DT12L + DAC2 12-bit right-aligned data + 20 + 12 + + + + + DDTH8R + DDTH8R + DUAL DAC 8-bit right aligned data holding register (DAC_DDTH8R), Bits 31:16 Reserved + 0x28 + 0x20 + read-write + 0x00000000 + + + DD1DT8R + DAC1 8-bit right-aligned data + 0 + 8 + + + DD2DT8R + DAC2 8-bit right-aligned data + 8 + 8 + + + + + D1ODT + D1ODT + DAC1 data output register (DAC_D1ODT) + 0x2C + 0x20 + read-only + 0x00000000 + + + D1ODT + DAC1 data output + 0 + 12 + + + + + D2ODT + D2ODT + DAC2 data output register (DAC_D2ODT) + 0x30 + 0x20 + read-only + 0x00000000 + + + D2ODT + DAC2 data output + 0 + 12 + + + + + STS + STS + DAC2 status register + (DAC_STS) + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAUDR1 + DAC1 DMA underrun flag + 13 + 1 + + + DMAUDR2 + DAC2 DMA underrun flag + 29 + 1 + + + + + + + DEBUG + Debug support + DEBUG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + DEBUG IDCODE + 0x0 + 0x20 + read-only + 0x0 + + + PID + Product ID + 0 + 32 + + + + + CTRL + CTRL + DEBUG CTRL + 0x4 + 0x20 + read-write + 0x0 + + + SLEEP_DEBUG + SLEEP_DEBUG + 0 + 1 + + + DEEPSLEEP_DEBUG + DEEPSLEEP_DEBUG + 1 + 1 + + + STANDBY_DEBUG + STANDBY_DEBUG + 2 + 1 + + + + + APB1_PAUSE + APB1_PAUSE + DEBUG APB1 PAUSE + 0x8 + 0x20 + read-write + 0x0 + + + TMR2_PAUSE + TMR2_PAUSE + 0 + 1 + + + TMR3_PAUSE + TMR3_PAUSE + 1 + 1 + + + TMR4_PAUSE + TMR4_PAUSE + 2 + 1 + + + TMR5_PAUSE + TMR5_PAUSE + 3 + 1 + + + TMR6_PAUSE + TMR6_PAUSE + 4 + 1 + + + TMR7_PAUSE + TMR7_PAUSE + 5 + 1 + + + TMR12_PAUSE + TMR12_PAUSE + 6 + 1 + + + TMR13_PAUSE + TMR13_PAUSE + 7 + 1 + + + TMR14_PAUSE + TMR14_PAUSE + 8 + 1 + + + ERTC_PAUSE + ERTC_PAUSE + 10 + 1 + + + WWDT_PAUSE + WWDT_PAUSE + 11 + 1 + + + WDT_PAUSE + WDT_PAUSE + 12 + 1 + + + ERTC512_PAUSE + ERTC512_PAUSE + 15 + 1 + + + I2C1_SMBUS_TIMEOUT + I2C1_SMBUS_TIMEOUT + 24 + 1 + + + CAN1_PAUSE + CAN1_PAUSE + 25 + 1 + + + CAN2_PAUSE + CAN2_PAUSE + 26 + 1 + + + I2C2_SMBUS_TIMEOUT + I2C2_SMBUS_TIMEOUT + 27 + 1 + + + I2C3_SMBUS_TIMEOUT + I2C3_SMBUS_TIMEOUT + 28 + 1 + + + + + APB2_PAUSE + APB2_PAUSE + DEBUG APB2 PAUSE + 0xC + 0x20 + read-write + 0x0 + + + TMR1_PAUSE + TMR1_PAUSE + 0 + 1 + + + TMR8_PAUSE + TMR8_PAUSE + 1 + 1 + + + TMR20_PAUSE + TIM20_PAUSE + 6 + 1 + + + TMR9_PAUSE + TMR9_PAUSE + 16 + 1 + + + TMR10_PAUSE + TMR10_PAUSE + 17 + 1 + + + TMR11_PAUSE + TMR11_PAUSE + 18 + 1 + + + + + SER_ID + SER_ID + SERIES ID + 0x20 + 0x20 + read-only + 0x0 + + + REV_ID + version ID + 0 + 3 + + + SER_ID + series ID + 8 + 8 + + + + + + + UART4 + Universal asynchronous receiver transmitter + 0x40004C00 + + UART4 + UART4 global interrupt + 52 + + + + UART5 + Universal asynchronous receiver transmitter + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + UART7 + Universal asynchronous receiver transmitter + 0x40007800 + + UART7 + UART7 global interrupt + 82 + + + + UART8 + Universal asynchronous receiver transmitter + 0x40007C00 + + UART8 + UART8 global interrupt + 83 + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DT + DT + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DT + Data Register + 0 + 32 + + + + + CDT + CDT + Common data register + 0x4 + 0x20 + read-write + 0x00000000 + + + CDT + Common Data + 0 + 1 + + + + + CTRL + CTRL + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RST + Reset bit + 0 + 1 + + + REVID + Reverse input data + 5 + 2 + + + REVOD + Reverse output data + 7 + 1 + + + + + IDT + IDT + Initial data register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + IDT + Initial Data + 0 + 32 + + + + + + + FLASH + Flash memory controler + FLASH + 0x40023C00 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + PSR + PSR + Performance selection register + 0x0 + 0x20 + 0x00000330 + + + NZW_BST_STS + Flash non-zero wait area boost status + 13 + 1 + read-only + + + NZW_BST + Flash non-zero wait area boost + 12 + 1 + read-write + + + + + UNLOCK + UNLOCK + Unlock register + 0x4 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + USD_UNLOCK + USD_UNLOCK + USD unlock register + 0x8 + 0x20 + write-only + 0x00000000 + + + USD_UKVAL + User system data Unlock key value + 0 + 32 + + + + + STS + STS + Status register + 0xC + 0x20 + 0x00000000 + + + ODF + Operate done flag + 5 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + PRGMERR + program error + 2 + 1 + read-write + + + OBF + Operate busy flag + 0 + 1 + read-only + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + BLKERS + Block erase + 3 + 1 + + + USDPRGM + User system data program + 4 + 1 + + + USDERS + User system data erase + 5 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + USDULKS + User system data unlock success + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR + ADDR + Address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + USD + USD + User system data register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + USDERR + User system data error + 0 + 1 + + + FAP + FLASH access protection + 1 + 1 + + + nWDT_ATO_EN + WDT auto enable + 2 + 1 + + + nDEPSLP_RST + Deepsleep reset + 3 + 1 + + + nSTDBY_RST + Standby reset + 4 + 1 + + + BTOPT + boot option + 5 + 1 + + + nWDT_DEPSLP + WDT deep sleep + 7 + 1 + + + nWDT_STDBY + WDT standby + 8 + 1 + + + USER_D0 + User data 0 + 10 + 8 + + + USER_D1 + User data 1 + 18 + 8 + + + + + EPPS0 + EPPS0 + Erase/program protection status register 0 + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + EPPS1 + EPPS1 + Erase/program protection status register 1 + 0x2C + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + UNLOCK2 + UNLOCK2 + Unlock 2 register + 0x44 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + STS2 + STS2 + Status 2 register + 0x4C + 0x20 + 0x00000000 + + + OBF + Operate busy flag + 0 + 1 + read-only + + + PRGMERR + program error + 2 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + ODF + Operate done flag + 5 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control 2 register + 0x50 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + BLKERS + Block erase + 3 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR2 + ADDR2 + Address 2 register + 0x54 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + CONTR + CONTR + Flash continue read register + 0x58 + 0x20 + read-write + 0x00000080 + + + FCONTR_EN + Flash continue read enable + 31 + 1 + + + + + DIVR + DIVR + Flash divider register + 0x60 + 0x20 + 0x00000022 + + + FDIV + Flash divider + 0 + 2 + read-write + + + FDIV_STS + Flash divider status + 4 + 2 + read-only + + + + + SLIB_STS2 + SLIB_STS2 + sLib status 2 register + 0xC8 + 0x20 + 0x0000FFFF + + + SLIB_INST_SS + sLib instruction start sector + 0 + 16 + read-only + + + + + SLIB_STS0 + SLIB_STS0 + sLib status 0 register + 0xCC + 0x20 + 0x00000000 + + + SLIB_ENF + sLib enabled flag + 3 + 1 + read-only + + + + + SLIB_STS1 + SLIB_STS1 + sLib status 1 register + 0xD0 + 0x20 + 0xFFFFFFFF + + + SLIB_SS + sLib start sector + 0 + 16 + read-only + + + SLIB_ES + sLib end sector + 16 + 16 + read-only + + + + + SLIB_PWD_CLR + SLIB_PWD_CLR + SLIB password clear register + 0xD4 + 0x20 + 0x00000000 + write-only + + + SLIB_PCLR_VAL + sLib password clear value + 0 + 32 + + + + + SLIB_MISC_STS + SLIB_MISC_STS + sLib misc status register + 0xD8 + 0x20 + 0x01000000 + + + SLIB_PWD_ERR + sLib password error + 0 + 1 + read-only + + + SLIB_PWD_OK + sLib password ok + 1 + 1 + read-only + + + SLIB_ULKF + sLib unlock flag + 2 + 1 + read-only + + + SLIB_RCNT + sLib remaining count + 16 + 9 + read-only + + + + + SLIB_SET_PWD + SLIB_SET_PWD + sLib password setting register + 0xDC + 0x20 + 0x00000000 + write-only + + + SLIB_PSET_VAL + sLib password setting val + 0 + 32 + + + + + SLIB_SET_RANGE0 + SLIB_SET_RANGE0 + Configure sLib range register 0 + 0xE0 + 0x20 + 0x00000000 + write-only + + + SLIB_SS_SET + sLib start sector setting + 0 + 16 + + + SLIB_ES_SET + sLib end sector setting + 16 + 16 + + + + + SLIB_SET_RANGE1 + SLIB_SET_RANGE1 + Configure sLib range register 1 + 0xE4 + 0x20 + 0x00000000 + write-only + + + SLIB_ISS_SET + sLib instruction start sector setting + 0 + 16 + + + SET_SLIB_STRT + sLib start setting + 31 + 1 + + + + + SLIB_UNLOCK + SLIB_UNLOCK + sLib unlock register + 0xF0 + 0x20 + 0x00000000 + write-only + + + SLIB_UKVAL + sLib unlock key value + 0 + 32 + + + + + CRC_CTRL + CRC_CTRL + CRC controler register + 0xF4 + 0x20 + 0x00000000 + write-only + + + CRC_SS + CRC start sector + 0 + 12 + + + CRC_SN + CRC sector numbler + 12 + 12 + + + CRC_STRT + CRC start + 31 + 1 + + + + + CRC_CHKR + CRC_CHKR + CRC check result register + 0xF8 + 0x20 + 0x00000000 + read-only + + + CRC_CHKR + CRC check result + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + DVP + Digital video parallel interface + DVP + 0x50050000 + + 0x0 + 0x400 + registers + + + DVP + DVP global interrupt + 78 + + + + CTRL + CTRL + Control register + 0x0 + 0x20 + 0x0000 + + + LCDS + Line capture/drop selection + 20 + 1 + read-write + + + LCDC + Line capture/drop control + + 19 + 1 + read-write + + + PCDS + Pixel capture/drop selection + + 18 + 1 + read-write + + + PCDC + Basic pixel capture/drop control + + 16 + 2 + read-write + + + ENA + DVP enable + 14 + 1 + read-write + + + PDL + Pixel data length + 10 + 2 + read-write + + + BFRC + Basic frame rate control + 8 + 2 + read-write + + + VSP + Vertical synchronization + polarity + 7 + 1 + read-write + + + HSP + Horizontal synchronization polarity + + 6 + 1 + read-write + + + CKP + Pixel clock polarity + 5 + 1 + read-write + + + SM + synchronization mode + 4 + 1 + read-write + + + JPEG + JPEG format + 3 + 1 + read-write + + + CRP + Cropping function enable + 2 + 1 + read-write + + + CFM + Capture fire mode + 1 + 1 + read-write + + + CAP + Capture function enable + 0 + 1 + read-write + + + + + STS + STS + status register + 0x4 + 0x20 + read-only + 0x0000 + + + OFNE + Output FIFO Non-empty + 2 + 1 + + + VSYN + Vertical synchronization status + 1 + 1 + + + HSYN + Horizontal synchronization status + 0 + 1 + + + + + ESTS + ESTS + Event status register + 0x8 + 0x20 + read-only + 0x0000 + + + HSES + Horizontal synchronization event status + 4 + 1 + + + VSES + Vertical synchronization event status + 3 + 1 + + + ESEES + Embedded synchronization error event status + + 2 + 1 + + + OVRES + Data FIFO overrun event status + + 1 + 1 + + + CFDES + Capture frame done event status + + 0 + 1 + + + + + IENA + IENA + interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + HSIE + Horizontal synchronization interrupt enable + + 4 + 1 + + + VSIE + Vertical synchronization interrupt enablee + + 3 + 1 + + + ESEIE + Embedded synchronization error interrupt + enable + 2 + 1 + + + OVRIE + Data FIFO overrun interrupt enable + + 1 + 1 + + + CFDIE + Capture frame done interrupt enable + + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-only + 0x0000 + + + HSIS + Horizontal synchronization interrupt + status + 4 + 1 + + + VSIS + Vertical synchronization interrupt + status + 3 + 1 + + + ESEIS + Embedded synchronization error + interrupt status + 2 + 1 + + + OVRIS + Data FIFO overrun interrupt + status + 1 + 1 + + + CFDIS + Capture frame done interrupt + status + 0 + 1 + + + + + ICLR + ICLR + Interrupt clear register + 0x14 + 0x20 + write-only + 0x0000 + + + HSIC + Horizontal synchronization + interrupt clear + 4 + 1 + + + VSIC + Vertical synchronization + interrupt clear + 3 + 1 + + + ESEIC + Embedded synchronization + error interrupt clear + 2 + 1 + + + OVRIC + Data FIFO overrun + interrupt clear + 1 + 1 + + + CFDIC + Capture frame done + interrupt clear + 0 + 1 + + + + + SCR + SCR + Synchronization code + register + 0x18 + 0x20 + read-write + 0x0000 + + + FMEC + Frame end code + 24 + 8 + + + LNEC + Line end code + 16 + 8 + + + LNSC + Line start code + 8 + 8 + + + FMSC + Frame start code + 0 + 8 + + + + + SUR + SUR + Synchronization unmask + register + 0x1C + 0x20 + read-write + 0x0000 + + + FMEU + Frame end unmask + 24 + 8 + + + LNEU + Line end unmask + 16 + 8 + + + LNSU + Line start unmask + + 8 + 8 + + + FMSU + Frame start unmask + + 0 + 8 + + + + + CWST + CWST + Crop window start + 0x20 + 0x20 + read-write + 0x0000 + + + CVSTR + Cropping window vertical start line + + 16 + 13 + + + CHSTR + Cropping window horizontal start pixel + + 0 + 14 + + + + + CWSZ + CWSZ + Crop window size + 0x24 + 0x20 + read-write + 0x0000 + + + CVNUM + Cropping window vertical line number + + 16 + 14 + + + CHNUM + Cropping window horizontal pixel number + + 0 + 14 + + + + + DT + DT + Data register + 0x28 + 0x20 + read-only + 0x0000 + + + DT + Data Port + 0 + 32 + + + + + ACTRL + ACTRL + Advanced Control register + + 0x40 + 0x20 + read-write + 0x0000 + + + VSEID + Vertical synchonization event and interrupt + definition + 17 + 1 + + + HSEID + Horizontal synchonization event and interrupt + definition + 16 + 1 + + + DMABT + DMA burst transfer configuration + + 12 + 1 + + + IDUS + Input data un-used setting + + 10 + 1 + + + IDUN + Input data un-used number + + 8 + 2 + + + EFDM + Enhanced function data format management + + 6 + 1 + + + EFDF + Enhanced function data format + + 4 + 2 + + + PCDES + Basic pixel capture/drop extended + selection + 3 + 1 + + + MIBE + Monochrome image binarization + enable + 2 + 1 + + + EFRCE + Enhanced frame rate control + enable + 1 + 1 + + + EISRE + Enhanced image scaling resize + enable + 0 + 1 + + + + + HSCF + HSCF + Horizontal scaling control flow + + 0x48 + 0x20 + read-write + 0x0000 + + + HSRTF + Horizontal scaling resize target factor + + 16 + 13 + + + HSRSF + Horizontal scaling resize source factor + + 0 + 13 + + + + + VSCF + VSCF + Vertical scaling control flow + + 0x4C + 0x20 + read-write + 0x0000 + + + VSRTF + Vertical scaling resize target factor + + 16 + 13 + + + VSRSF + Vertical scaling resize source factor + + 0 + 13 + + + + + FRF + FRF + Frame rate flow + + 0x50 + 0x20 + read-write + 0x0000 + + + EFRCTF + Enhanced frame rate control target factor + + 8 + 5 + + + EFRCSF + Enhanced frame rate contorl source factor + + 0 + 5 + + + + + BTH + BTH + Binarization threshold + + 0x54 + 0x20 + read-write + 0x0000 + + + MIBTHD + Monochrome image binarization threshold + + 0 + 8 + + + + + + + USB_OTG1_GLOBAL + USB on-the-go full speed + USB_OTG1 + 0x50000000 + + 0x0 + 0x400 + registers + + + OTGFS1 + USB On The Go FS global + interrupt + 67 + + + + GOTGCTL + GOTGCTL + OTGFS control and status register + (OTGFS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGFS interrupt register + (OTGFS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGFS AHB configuration register + (OTGFS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGFS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + FS timeout calibration + 0 + 3 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGFS reset register + (OTGFS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGFS core interrupt register + (OTGFS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-write + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGFS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGFS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGFS Receive FIFO size register + (OTGFS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGFS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGFS non-periodic transmit FIFO/queue + status register (OTGFS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGFS general core configuration register + (OTGFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + LP_MODE + Low power mode + 17 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGFS Host periodic transmit FIFO size + register (OTGFS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO5 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF6) + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO6 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF7) + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO7 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTG1_HOST + USB on the go full speed + USB_OTG1 + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGFS host configuration register + (OTGFS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGFS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGFS host frame number/frame time + remaining register (OTGFS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGFS_Host periodic transmit FIFO/queue + status register (OTGFS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGFS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGFS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGFS host port control and status register + (OTGFS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGFS host channel-0 characteristics + register (OTGFS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGFS host channel-1 characteristics + register (OTGFS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGFS host channel-2 characteristics + register (OTGFS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGFS host channel-3 characteristics + register (OTGFS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGFS host channel-4 characteristics + register (OTGFS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGFS host channel-5 characteristics + register (OTGFS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGFS host channel-6 characteristics + register (OTGFS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTGFS host channel-8 characteristics + register (OTGFS_HCCHAR8) + 0x200 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTGFS host channel-9 characteristics + register (OTGFS_HCCHAR9) + 0x220 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTGFS host channel-10 characteristics + register (OTGFS_HCCHAR10) + 0x240 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR11) + 0x260 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTGFS host channel-12 characteristics + register (OTGFS_HCCHAR12) + 0x280 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTGFS host channel-13 characteristics + register (OTGFS_HCCHAR13) + 0x2A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTGFS host channel-14 characteristics + register (OTGFS_HCCHAR14) + 0x2C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTGFS host channel-15 characteristics + register (OTGFS_HCCHAR15) + 0x2E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGFS host channel-0 interrupt register + (OTGFS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGFS host channel-2 interrupt register + (OTGFS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGFS host channel-3 interrupt register + (OTGFS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGFS host channel-4 interrupt register + (OTGFS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGFS host channel-5 interrupt register + (OTGFS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGFS host channel-6 interrupt register + (OTGFS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGFS host channel-7 interrupt register + (OTGFS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT8 + HCINT8 + OTGFS host channel-8 interrupt register + (OTGFS_HCINT8) + 0x208 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT9 + HCINT9 + OTGFS host channel-9 interrupt register + (OTGFS_HCINT9) + 0x228 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT10 + HCINT10 + OTGFS host channel-10 interrupt register + (OTGFS_HCINT10) + 0x248 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT11 + HCINT11 + OTGFS host channel-11 interrupt register + (OTGFS_HCINT11) + 0x268 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT12 + HCINT12 + OTGFS host channel-12 interrupt register + (OTGFS_HCINT12) + 0x288 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT13 + HCINT13 + OTGFS host channel-13 interrupt register + (OTGFS_HCINT13) + 0x2A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT14 + HCINT14 + OTGFS host channel-14 interrupt register + (OTGFS_HCINT14) + 0x2C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT15 + HCINT15 + OTGFS host channel-15 interrupt register + (OTGFS_HCINT15) + 0x2E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGFS host channel-0 mask register + (OTGFS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGFS host channel-1 mask register + (OTGFS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGFS host channel-2 mask register + (OTGFS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGFS host channel-3 mask register + (OTGFS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGFS host channel-4 mask register + (OTGFS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGFS host channel-5 mask register + (OTGFS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGFS host channel-6 mask register + (OTGFS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGFS host channel-7 mask register + (OTGFS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + OTGFS host channel-8 mask register + (OTGFS_HCINTMSK8) + 0x20C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + OTGFS host channel-9 mask register + (OTGFS_HCINTMSK9) + 0x22C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + OTGFS host channel-10 mask register + (OTGFS_HCINTMSK10) + 0x24C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + OTGFS host channel-11 mask register + (OTGFS_HCINTMSK11) + 0x26C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + OTGFS host channel-12 mask register + (OTGFS_HCINTMSK12) + 0x28C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + OTGFS host channel-13 mask register + (OTGFS_HCINTMSK13) + 0x2AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + OTGFS host channel-14 mask register + (OTGFS_HCINTMSK14) + 0x2CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + OTGFS host channel-15 mask register + (OTGFS_HCINTMSK15) + 0x2EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGFS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ1 + HCTSIZ1 + OTGFS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ2 + HCTSIZ2 + OTGFS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ3 + HCTSIZ3 + OTGFS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ4 + HCTSIZ4 + OTGFS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ5 + HCTSIZ5 + OTGFS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ6 + HCTSIZ6 + OTGFS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ7 + HCTSIZ7 + OTGFS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ8 + HCTSIZ8 + OTGFS host channel-8 transfer size + register + 0x210 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ9 + HCTSIZ9 + OTGFS host channel-9 transfer size + register + 0x230 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ10 + HCTSIZ10 + OTGFS host channel-10 transfer size + register + 0x250 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ11 + HCTSIZ11 + OTGFS host channel-11 transfer size + register + 0x270 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ12 + HCTSIZ12 + OTGFS host channel-12 transfer size + register + 0x290 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ13 + HCTSIZ13 + OTGFS host channel-13 transfer size + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ14 + HCTSIZ14 + OTGFS host channel-14 transfer size + register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ15 + HCTSIZ15 + OTGFS host channel-15 transfer size + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + + + USB_OTG1_DEVICE + USB on the go full speed + USB_OTG1 + 0x50000800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGFS device configuration register + (OTGFS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGFS device control register + (OTGFS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTGFS device IN endpoint common interrupt + mask register (OTGFS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTGFS device OUT endpoint common interrupt + mask register (OTGFS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + + + DAINT + DAINT + OTGFS device all endpoints interrupt + register (OTGFS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGFS all endpoints interrupt mask register + (OTGFS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGFS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEPCTL0 + DIEPCTL0 + OTGFS device control IN endpoint 0 control + register (OTGFS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-only + + + EPTENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTGFS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGFS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGFS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL4 + DIEPCTL4 + OTGFS device IN endpoint-4 control + register + 0x180 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL5 + DIEPCTL5 + OTGFS device IN endpoint-5 control + register + 0x1A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL6 + DIEPCTL6 + OTGFS device IN endpoint-6 control + register + 0x1C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL7 + DIEPCTL7 + OTGFS device IN endpoint-7 control + register + 0x1E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGFS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGFS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGFS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGFS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL4 + DOEPCTL4 + OTGFS device OUT endpoint-4 control + register + 0x380 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL5 + DOEPCTL5 + OTGFS device OUT endpoint-5 control + register + 0x3A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL6 + DOEPCTL6 + OTGFS device OUT endpoint-6 control + register + 0x3C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL7 + DOEPCTL7 + OTGFS device OUT endpoint-7 control + register + 0x3E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGFS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT1 + DIEPINT1 + OTGFS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT2 + DIEPINT2 + OTGFS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT3 + DIEPINT3 + OTGFS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT4 + DIEPINT4 + OTGFS device IN endpoint-4 interrupt + register + 0x188 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT5 + DIEPINT5 + OTGFS device IN endpoint-5 interrupt + register + 0x1A8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT6 + DIEPINT6 + OTGFS device IN endpoint-6 interrupt + register + 0x1C8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT7 + DIEPINT7 + OTGFS device IN endpoint-7 interrupt + register + 0x1E8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DOEPINT0 + DOEPINT0 + OTGFS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT1 + DOEPINT1 + OTGFS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT2 + DOEPINT2 + OTGFS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT3 + DOEPINT3 + OTGFS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT4 + DOEPINT4 + OTGFS device OUT endpoint-4 interrupt + register + 0x388 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT5 + DOEPINT5 + OTGFS device OUT endpoint-5 interrupt + register + 0x3A8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT6 + DOEPINT6 + OTGFS device OUT endpoint-6 interrupt + register + 0x3C8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT7 + DOEPINT7 + OTGFS device OUT endpoint-7 interrupt + register + 0x3E8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGFS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGFS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGFS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGFS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ4 + DIEPTSIZ4 + OTG device IN endpoint-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ5 + DIEPTSIZ5 + OTG device IN endpoint-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ6 + DIEPTSIZ6 + OTG device IN endpoint-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ7 + DIEPTSIZ7 + OTG device IN endpoint-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + OTGFS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGFS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGFS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGFS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS4 + DTXFSTS4 + OTGFS device IN endpoint-4 transmit FIFO + status register + 0x198 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS5 + DTXFSTS5 + OTGFS device IN endpoint-5 transmit FIFO + status register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS6 + DTXFSTS6 + OTGFS device IN endpoint-6 transmit FIFO + status register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS7 + DTXFSTS7 + OTGFS device IN endpoint-7 transmit FIFO + status register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGFS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGFS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGFS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + OTGFS device OUT endpoint-4 transfer size + register + 0x390 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + OTGFS device OUT endpoint-5 transfer size + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + OTGFS device OUT endpoint-6 transfer size + register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + OTGFS device OUT endpoint-7 transfer size + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + + + USB_OTG1_PWRCLK + USB on the go full speed + USB_OTG1 + 0x50000E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGFS power and clock gating control + register (OTGFS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + USB_OTG2_GLOBAL + USB on the go full speed + USB_OTG2 + 0x40040000 + + 0x0 + 0x400 + registers + + + OTGFS2 + USB On The Go FS2 global + interrupt + 77 + + + + GOTGCTL + GOTGCTL + OTGFS control and status register + (OTGFS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGFS interrupt register + (OTGFS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGFS AHB configuration register + (OTGFS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGFS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + FS timeout calibration + 0 + 3 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGFS reset register + (OTGFS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGFS core interrupt register + (OTGFS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-only + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGFS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGFS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGFS Receive FIFO size register + (OTGFS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGFS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGFS non-periodic transmit FIFO/queue + status register (OTGFS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGFS general core configuration register + (OTGFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + LP_MODE + Low power mode + 17 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGFS Host periodic transmit FIFO size + register (OTGFS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO5 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF6) + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO6 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF7) + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO7 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTG2_HOST + USB on the go full speed + USB_OTG2 + 0x40040400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGFS host configuration register + (OTGFS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGFS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGFS host frame number/frame time + remaining register (OTGFS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGFS_Host periodic transmit FIFO/queue + status register (OTGFS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGFS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGFS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGFS host port control and status register + (OTGFS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGFS host channel-0 characteristics + register (OTGFS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGFS host channel-1 characteristics + register (OTGFS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGFS host channel-2 characteristics + register (OTGFS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGFS host channel-3 characteristics + register (OTGFS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGFS host channel-4 characteristics + register (OTGFS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGFS host channel-5 characteristics + register (OTGFS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGFS host channel-6 characteristics + register (OTGFS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTGFS host channel-8 characteristics + register (OTGFS_HCCHAR8) + 0x200 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTGFS host channel-9 characteristics + register (OTGFS_HCCHAR9) + 0x220 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTGFS host channel-10 characteristics + register (OTGFS_HCCHAR10) + 0x240 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR11) + 0x260 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTGFS host channel-12 characteristics + register (OTGFS_HCCHAR12) + 0x280 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTGFS host channel-13 characteristics + register (OTGFS_HCCHAR13) + 0x2A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTGFS host channel-14 characteristics + register (OTGFS_HCCHAR14) + 0x2C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTGFS host channel-15 characteristics + register (OTGFS_HCCHAR15) + 0x2E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGFS host channel-0 interrupt register + (OTGFS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGFS host channel-2 interrupt register + (OTGFS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGFS host channel-3 interrupt register + (OTGFS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGFS host channel-4 interrupt register + (OTGFS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGFS host channel-5 interrupt register + (OTGFS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGFS host channel-6 interrupt register + (OTGFS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGFS host channel-7 interrupt register + (OTGFS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT8 + HCINT8 + OTGFS host channel-8 interrupt register + (OTGFS_HCINT8) + 0x208 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT9 + HCINT9 + OTGFS host channel-9 interrupt register + (OTGFS_HCINT9) + 0x228 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT10 + HCINT10 + OTGFS host channel-10 interrupt register + (OTGFS_HCINT10) + 0x248 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT11 + HCINT11 + OTGFS host channel-11 interrupt register + (OTGFS_HCINT11) + 0x268 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT12 + HCINT12 + OTGFS host channel-12 interrupt register + (OTGFS_HCINT12) + 0x288 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT13 + HCINT13 + OTGFS host channel-13 interrupt register + (OTGFS_HCINT13) + 0x2A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT14 + HCINT14 + OTGFS host channel-14 interrupt register + (OTGFS_HCINT14) + 0x2C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT15 + HCINT15 + OTGFS host channel-15 interrupt register + (OTGFS_HCINT15) + 0x2E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGFS host channel-0 mask register + (OTGFS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGFS host channel-1 mask register + (OTGFS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGFS host channel-2 mask register + (OTGFS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGFS host channel-3 mask register + (OTGFS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGFS host channel-4 mask register + (OTGFS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGFS host channel-5 mask register + (OTGFS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGFS host channel-6 mask register + (OTGFS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGFS host channel-7 mask register + (OTGFS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + OTGFS host channel-8 mask register + (OTGFS_HCINTMSK8) + 0x20C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + OTGFS host channel-9 mask register + (OTGFS_HCINTMSK9) + 0x22C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + OTGFS host channel-10 mask register + (OTGFS_HCINTMSK10) + 0x24C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + OTGFS host channel-11 mask register + (OTGFS_HCINTMSK11) + 0x26C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + OTGFS host channel-12 mask register + (OTGFS_HCINTMSK12) + 0x28C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + OTGFS host channel-13 mask register + (OTGFS_HCINTMSK13) + 0x2AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + OTGFS host channel-14 mask register + (OTGFS_HCINTMSK14) + 0x2CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + OTGFS host channel-15 mask register + (OTGFS_HCINTMSK15) + 0x2EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGFS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ1 + HCTSIZ1 + OTGFS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ2 + HCTSIZ2 + OTGFS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ3 + HCTSIZ3 + OTGFS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ4 + HCTSIZ4 + OTGFS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ5 + HCTSIZ5 + OTGFS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ6 + HCTSIZ6 + OTGFS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ7 + HCTSIZ7 + OTGFS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ8 + HCTSIZ8 + OTGFS host channel-8 transfer size + register + 0x210 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ9 + HCTSIZ9 + OTGFS host channel-9 transfer size + register + 0x230 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ10 + HCTSIZ10 + OTGFS host channel-10 transfer size + register + 0x250 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ11 + HCTSIZ11 + OTGFS host channel-11 transfer size + register + 0x270 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ12 + HCTSIZ12 + OTGFS host channel-12 transfer size + register + 0x290 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ13 + HCTSIZ13 + OTGFS host channel-13 transfer size + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ14 + HCTSIZ14 + OTGFS host channel-14 transfer size + register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ15 + HCTSIZ15 + OTGFS host channel-15 transfer size + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + + + USB_OTG2_DEVICE + USB on the go full speed + USB_OTG2 + 0x40040800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGFS device configuration register + (OTGFS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGFS device control register + (OTGFS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTGFS device IN endpoint common interrupt + mask register (OTGFS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTGFS device OUT endpoint common interrupt + mask register (OTGFS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + + + DAINT + DAINT + OTGFS device all endpoints interrupt + register (OTGFS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGFS all endpoints interrupt mask register + (OTGFS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGFS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEPCTL0 + DIEPCTL0 + OTGFS device control IN endpoint 0 control + register (OTGFS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-only + + + EPTENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTGFS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGFS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGFS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL4 + DIEPCTL4 + OTGFS device IN endpoint-4 control + register + 0x180 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL5 + DIEPCTL5 + OTGFS device IN endpoint-5 control + register + 0x1A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL6 + DIEPCTL6 + OTGFS device IN endpoint-6 control + register + 0x1C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL7 + DIEPCTL7 + OTGFS device IN endpoint-7 control + register + 0x1E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGFS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGFS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGFS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGFS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL4 + DOEPCTL4 + OTGFS device OUT endpoint-4 control + register + 0x380 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL5 + DOEPCTL5 + OTGFS device OUT endpoint-5 control + register + 0x3A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL6 + DOEPCTL6 + OTGFS device OUT endpoint-6 control + register + 0x3C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL7 + DOEPCTL7 + OTGFS device OUT endpoint-7 control + register + 0x3E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGFS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT1 + DIEPINT1 + OTGFS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT2 + DIEPINT2 + OTGFS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT3 + DIEPINT3 + OTGFS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT4 + DIEPINT4 + OTGFS device IN endpoint-4 interrupt + register + 0x188 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT5 + DIEPINT5 + OTGFS device IN endpoint-5 interrupt + register + 0x1A8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT6 + DIEPINT6 + OTGFS device IN endpoint-6 interrupt + register + 0x1C8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT7 + DIEPINT7 + OTGFS device IN endpoint-7 interrupt + register + 0x1E8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DOEPINT0 + DOEPINT0 + OTGFS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT1 + DOEPINT1 + OTGFS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT2 + DOEPINT2 + OTGFS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT3 + DOEPINT3 + OTGFS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT4 + DOEPINT4 + OTGFS device OUT endpoint-4 interrupt + register + 0x388 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT5 + DOEPINT5 + OTGFS device OUT endpoint-5 interrupt + register + 0x3A8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT6 + DOEPINT6 + OTGFS device OUT endpoint-6 interrupt + register + 0x3C8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT7 + DOEPINT7 + OTGFS device OUT endpoint-7 interrupt + register + 0x3E8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGFS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGFS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGFS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGFS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ4 + DIEPTSIZ4 + OTG device IN endpoint-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ5 + DIEPTSIZ5 + OTG device IN endpoint-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ6 + DIEPTSIZ6 + OTG device IN endpoint-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ7 + DIEPTSIZ7 + OTG device IN endpoint-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + OTGFS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGFS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGFS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGFS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS4 + DTXFSTS4 + OTGFS device IN endpoint-4 transmit FIFO + status register + 0x198 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS5 + DTXFSTS5 + OTGFS device IN endpoint-5 transmit FIFO + status register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS6 + DTXFSTS6 + OTGFS device IN endpoint-6 transmit FIFO + status register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS7 + DTXFSTS7 + OTGFS device IN endpoint-7 transmit FIFO + status register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGFS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGFS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGFS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + OTGFS device OUT endpoint-4 transfer size + register + 0x390 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + OTGFS device OUT endpoint-5 transfer size + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + OTGFS device OUT endpoint-6 transfer size + register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + OTGFS device OUT endpoint-7 transfer size + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + + + USB_OTG2_PWRCLK + USB on the go full speed + USB_OTG2 + 0x40040E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGFS power and clock gating control + register (OTGFS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + SCFG + System configuration controller + SCFG + 0x40013800 + + 0x0 + 0x400 + registers + + + + CFG1 + CFG1 + configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MAP_SEL + Memory address mapping selection bits + 0 + 3 + + + IR_POL + IR output polarity selection + 5 + 1 + + + IR_SRC_SEL + IR signal source selection + 6 + 2 + + + SWAP_XMC + XMC address mapping swap + 10 + 2 + + + + + CFG2 + CFG2 + configuration register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + MII_RMII_SEL + MII or RMII selection + bits + 23 + 1 + + + + + EXINTC1 + EXINTC1 + external interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXINT3 + EXINT 3 configuration bits + 12 + 4 + + + EXINT2 + EXINT 2 configuration bits + 8 + 4 + + + EXINT1 + EXINT 1 configuration bits + 4 + 4 + + + EXINT0 + EXINT 0 configuration bits + 0 + 4 + + + + + EXINTC2 + EXINTC2 + external interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXINT7 + EXINT 7 configuration bits + 12 + 4 + + + EXINT6 + EXINT 6 configuration bits + 8 + 4 + + + EXINT5 + EXINT 5 configuration bits + 4 + 4 + + + EXINT4 + EXINT 4 configuration bits + 0 + 4 + + + + + EXINTC3 + EXINTC3 + external interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXINT11 + EXINT 11 configuration bits + 12 + 4 + + + EXINT10 + EXINT 10 configuration bits + 8 + 4 + + + EXINT9 + EXINT 9 configuration bits + 4 + 4 + + + EXINT8 + EXINT 8 configuration bits + 0 + 4 + + + + + EXINTC4 + EXINTC4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXINT15 + EXINT 15 configuration bits + 12 + 4 + + + EXINT14 + EXINT 14 configuration bits + 8 + 4 + + + EXINT13 + EXINT 13 configuration bits + 4 + 4 + + + EXINT12 + EXINT 12 configuration bits + 0 + 4 + + + + + UHDRV + UHDRV + Ultra high drive register + 0x2C + 0x20 + read-write + 0x0000 + + + PF15_UH + PF15 ultra high sourcing/sinking strength + 10 + 1 + + + PF14_UH + PF14 ultra high sourcing/sinking strength + 9 + 1 + + + PD15_UH + PD15 ultra high sourcing/sinking strength + 8 + 1 + + + PD14_UH + PD14 ultra high sourcing/sinking strength + 7 + 1 + + + PD13_UH + PD13 ultra high sourcing/sinking strength + 6 + 1 + + + PD12_UH + PD12 ultra high sourcing/sinking strength + 5 + 1 + + + PB10_UH + PB10 ultra high sourcing/sinking strength + 2 + 1 + + + PB9_UH + PB9 ultra high sourcing/sinking strength + 1 + 1 + + + PB3_UH + PB3 ultra high sourcing/sinking strength + 0 + 1 + + + + + + + QSPI1 + Quad SPI Controller + QSPI + 0xA0001000 + + 0x0 + 0x400 + registers + + + QSPI1 + QSPI1 global interrupt + 92 + + + + CMD_W0 + CMD_W0 + Command word 0 + 0x0 + 0x20 + read-write + 0x00000000 + + + SPIADR + SPI flash address + 0 + 32 + + + + + CMD_W1 + CMD_W1 + Command word 1 + 0x4 + 0x20 + read-write + 0x01000003 + + + ADRLEN + SPI address length + 0 + 3 + + + DUM2 + Second dummy state cycle + 16 + 8 + + + INSLEN + Instruction code length + 24 + 2 + + + PEMEN + Perfrmance enhance mode enable + 28 + 1 + + + + + CMD_W2 + CMD_W2 + Command word 2 + 0x8 + 0x20 + read-write + 0x01000003 + + + DCNT + Read write data counter + 0 + 32 + + + + + CMD_W3 + CMD_W3 + Command word 3 + 0xC + 0x20 + read-write + 0x00000000 + + + WEN + Write data enable + 1 + 1 + + + RSTSEN + Read spi status enable + 2 + 1 + + + RSTSC + Read spi status configure + 3 + 1 + + + OPMODE + SPI operate mode + 5 + 3 + + + PEMOPC + Performance enhance mode operate code + 16 + 8 + + + INSC + Instruction code + 24 + 8 + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000000 + + + CLKDIV + SPI clock divider + 0 + 3 + + + SCKMODE + Sckout mode + 4 + 1 + + + XIPIDLE + XIP port idle status + 7 + 1 + + + ABORT + Abort instruction + 8 + 1 + + + BUSY + Busy bit of spi status + 16 + 3 + + + XIPRCMDF + XIP read command flush + 19 + 1 + + + XIPSEL + XIP port selection + 20 + 1 + + + KEYEN + encryption key enable + 21 + 1 + + + + + ACTR + ACTR + AC timing control register + 0x14 + 0x20 + read-write + 0x0000000F + + + CSDLY + CS delay + 0 + 4 + + + + + FIFOSTS + FIFOSTS + FIFO Status register + 0x18 + 0x20 + read-only + 0x00000001 + + + TXFIFORDY + TxFIFO ready status + 0 + 1 + + + RXFIFORDY + RxFIFO ready status + 1 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x20 + 0x20 + read-write + 0x00000001 + + + DMAEN + DMA handshake enable + 0 + 1 + + + CMDIE + Command complete interrupt enable + 1 + 1 + + + TXFIFOTHOD + TxFIFO thod + 8 + 2 + + + RXFIFOTHOD + RxFIFO thod + 12 + 2 + + + + + CMDSTS + CMDSTS + CMD status register + 0x24 + 0x20 + read-only + 0x00000000 + + + CMDSTS + Command complete status + 0 + 1 + + + + + RSTS + RSTS + SPI read status register + 0x28 + 0x20 + read-only + 0x00000000 + + + SPISTS + SPI read status + 0 + 8 + + + + + FSIZE + FSIZE + SPI flash size + 0x2C + 0x20 + read-write + 0x00000000 + + + SPIFSIZE + SPI flash size + 0 + 32 + + + + + XIP_CMD_W0 + XIP_CMD_W0 + XIP command word 0 + 0x30 + 0x20 + read-write + 0x00000000 + + + XIPR_DUM2 + XIP read second dummy cycle + 0 + 8 + + + XIPR_OPMODE + XIP read operate mode + 8 + 3 + + + XIPR_ADRLEN + XIP read address length + 11 + 1 + + + XIPR_INSC + XIP read instruction code + 12 + 8 + + + + + XIP_CMD_W1 + XIP_CMD_W1 + XIP command word 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + XIPW_DUM2 + XIP write second dummy cycle + 0 + 8 + + + XIPW_OPMODE + XIP write operate mode + 8 + 3 + + + XIPW_ADRLEN + XIP write address length + 11 + 1 + + + XIPW_INSC + XIP write instruction code + 12 + 8 + + + + + XIP_CMD_W2 + XIP_CMD_W2 + XIP command word 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + XIPR_DCNT + XIP read data counter + 0 + 6 + + + XIPR_TCNT + XIP continue read cycle counter + 8 + 7 + + + XIPR_SEL + XIP read continue mode select + 15 + 1 + + + XIPW_DCNT + XIP write data counter + 16 + 6 + + + XIPW_TCNT + XIP continue write cycle counter + 24 + 7 + + + XIPW_SEL + XIP write continue mode select + 31 + 1 + + + + + XIP_CMD_W3 + XIP_CMD_W3 + XIP command word 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + BYPASSC + Bypass cache function + 0 + 1 + + + CSTS + Cache status + 3 + 1 + + + + + REV + REV + Revision + 0x50 + 0x20 + read-write + 0x00010500 + + + REVISION + Revision number + 0 + 31 + + + + + DT + DT + 32/16/8 bit data port register + 0x100 + 0x20 + read-write + 0x00000000 + + + + + QSPI2 + 0xA0002000 + + QSPI2 + QSPI2 global interrupt + 91 + + + + ETHERNET_MAC + Ethernet: media access control + ETHERNET + 0x40028000 + + 0x0 + 0x100 + registers + + + EMAC + Ethernet mac global interrupt + 61 + + + + MACCTRL + MACCTRL + Ethernet MAC configuration register + 0x0 + 0x20 + read-write + 0x00008000 + + + RE + Receiver enable + 2 + 1 + + + TE + Transmitter enable + 3 + 1 + + + DC + Deferral check + 4 + 1 + + + BL + Back-off limit + 5 + 2 + + + ACS + Automatic pad/CRC + stripping + 7 + 1 + + + DR + Disable retry + 9 + 1 + + + IPC + IPv4 checksum offload + 10 + 1 + + + DM + Duplex mode + 11 + 1 + + + LM + Loopback mode + 12 + 1 + + + DRO + Disable receive own + 13 + 1 + + + FES + Fast EMAC speed + 14 + 1 + + + DCS + Disable carrier sense + 16 + 1 + + + IFG + Interframe gap + 17 + 3 + + + JD + Jabber disable + 22 + 1 + + + WD + Watchdog disable + 23 + 1 + + + + + MACFRMF + MACFRMF + Ethernet MAC frame filter register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Promiscuous mode + 0 + 1 + + + HUC + Hash unicast + 1 + 1 + + + HMC + Hash multicast + 2 + 1 + + + DAIF + Destination address inverse + filtering + 3 + 1 + + + PMC + Pass multicast + 4 + 1 + + + DBF + Disable broadcast frames + 5 + 1 + + + PCF + Pass control frames + 6 + 2 + + + SAIF + Source address inverse + filtering + 8 + 1 + + + SAF + Source address filter + 9 + 1 + + + HPF + Hash or perfect filter + 10 + 1 + + + RA + Receive all + 31 + 1 + + + + + MACHTH + MACHTH + Ethernet MAC hash table high register + 0x8 + 0x20 + read-write + 0x00000000 + + + HTH + Hash table high + 0 + 32 + + + + + MACHTL + MACHTL + Ethernet MAC hash table low register + 0xC + 0x20 + read-write + 0x00000000 + + + HTL + Hash table low + 0 + 32 + + + + + MACMIIADDR + MACMIIADDR + Ethernet MAC MII address register + 0x10 + 0x20 + read-write + 0x00000000 + + + MB + MII busy + 0 + 1 + + + MW + MII write + 1 + 1 + + + CR + Clock range + 2 + 3 + + + MII + MII register + 6 + 5 + + + PA + PHY address + 11 + 5 + + + + + MACMIIDT + MACMIIDT + Ethernet MAC MII data register + 0x14 + 0x20 + read-write + 0x00000000 + + + MD + MII data + 0 + 16 + + + + + MACFCTRL + MACFCTRL + Ethernet MAC flow control register + 0x18 + 0x20 + read-write + 0x00000000 + + + FCB_BPA + Flow control busy/back pressure + activate + 0 + 1 + + + ETF + Enable transmit flow control + + 1 + 1 + + + ERF + Enable receive flow control + + 2 + 1 + + + DUP + Detect unicast pause frame + 3 + 1 + + + PLT + Pause low threshold + 4 + 2 + + + DZQP + Disable zero-quanta pause + 7 + 1 + + + PT + Pass time + 16 + 16 + + + + + MACVLT + MACVLT + Ethernet MAC VLAN tag register + 0x1C + 0x20 + read-write + 0x00000000 + + + VTI + VLAN tag identifier (for receive + frames) + 0 + 16 + + + ETV + Enable 12-bit VLAN tag comparison + 16 + 1 + + + + + MACRWFF + MACRWFF + Ethernet MAC remote wakeup frame filter register + 0x28 + 0x20 + read-write + 0x00000000 + + + MACPMTCTRLSTS + MACPMTCTRLSTS + Ethernet MAC PMT control and status register + 0x2C + 0x20 + read-write + 0x00000000 + + + PD + Power down + 0 + 1 + + + EMP + Enable magic packet + 1 + 1 + + + ERWF + Enable remote wakeup frame + 2 + 1 + + + RMP + Received magic packet + 5 + 1 + + + RRWF + Recevied remote wakeup frame + 6 + 1 + + + GUC + Global unicast + 9 + 1 + + + RWFFPR + Remote wakeup frame filter register pointer + reset + 31 + 1 + + + + + MACISTS + MACISTS + Ethernet MAC interrupt status register + 0x38 + 0x20 + read-write + 0x00000000 + + + PIS + PMT interrupt status + 3 + 1 + + + MIS + MMC interrupt status + 4 + 1 + + + MRIS + MMC receive interrupt status + 5 + 1 + + + MTIS + MMC transmit interrupt status + 6 + 1 + + + TIS + Timestamp interrupt status + 9 + 1 + + + + + MACIMR + MACIMR + Ethernet MAC interrupt mask register + 0x3C + 0x20 + read-write + 0x00000000 + + + PIM + PMT interrupt mask + 3 + 1 + + + TIM + Timestamp interrupt mask + 9 + 1 + + + + + MACA0H + MACA0H + Ethernet MAC address 0 high register + 0x40 + 0x20 + 0x0010FFFF + + + MA0H + MAC address0 high + 0 + 16 + read-write + + + AE + Address enable + 31 + 1 + read-only + + + + + MACA0L + MACA0L + Ethernet MAC address 0 low register + 0x44 + 0x20 + read-write + 0xFFFFFFFF + + + MA0L + MAC address0 low + 0 + 32 + + + + + MACA1H + MACA1H + Ethernet MAC address 1 high register + 0x48 + 0x20 + read-write + 0x0000FFFF + + + MA1H + MAC address1 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA1L + MACA1L + Ethernet MAC address1 low register + 0x4C + 0x20 + read-write + 0xFFFFFFFF + + + MA1L + MAC address1 low + 0 + 32 + + + + + MACA2H + MACA2H + Ethernet MAC address 2 high register + 0x50 + 0x20 + read-write + 0x0050 + + + MA2H + MAC address 2 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA2L + MACA2L + Ethernet MAC address 2 low register + 0x54 + 0x20 + read-write + 0xFFFFFFFF + + + MA2L + MAC address2 low + 0 + 31 + + + + + MACA3H + MACA3H + Ethernet MAC address 3 high register + 0x58 + 0x20 + read-write + 0x0000FFFF + + + MA3H + MAC address3 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA3L + MACA3L + Ethernet MAC address 3 low register + 0x5C + 0x20 + read-write + 0xFFFFFFFF + + + MA3L + MAC address3 low + 0 + 32 + + + + + + + ETHERNET_MMC + Ethernet: MAC management counters + ETHERNET + 0x40028100 + + 0x0 + 0x100 + registers + + + + MMCCTRL + MMCCTRL + Ethernet MMC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + RC + Reset counter + 0 + 1 + + + SCR + Stop counter rollover + 1 + 1 + + + RR + Reset on read + 2 + 1 + + + FMC + Freeze MMC counter + 31 + 1 + + + + + MMCRI + MMCRI + Ethernet MMC receive interrupt register + 0x4 + 0x20 + read-write + 0x00000000 + + + RFCE + Received frames CRC error + 5 + 1 + + + RFAE + Received frames alignment error + 6 + 1 + + + RGUF + Received good unicast frames + 17 + 1 + + + + + MMCTI + MMCTI + Ethernet MMC transmit interrupt register + 0x8 + 0x20 + read-write + 0x00000000 + + + TSCGFCI + Transmit single collision good frame + counter interrupt + 14 + 1 + + + TGFMSC + Transmit good frames more single + collision + 15 + 1 + + + TGF + Transmitted good frames + 21 + 1 + + + + + MMCRIM + MMCRIM + Ethernet MMC receive interrupt mask register + 0xC + 0x20 + read-write + 0x00000000 + + + RCEFCIM + Received CRC error frame counter interrupt + mask + 5 + 1 + + + RAEFACIM + Received alignment error frame alignment + counter interrupt mask + 6 + 1 + + + RUGFCIM + Received unicast good frame counter + interrupt mask + 17 + 1 + + + + + MMCTIM + MMCTIM + Ethernet MMC transmit interrupt mask register + 0x10 + 0x20 + read-write + 0x00000000 + + + TSCGFCIM + Transmit single collision good frame + counter interrupt mask + 14 + 1 + + + TMCGFCIM + Transmit multiple collision good frame + counter interrupt mask + 15 + 1 + + + TGFCIM + Transmitted good frame counter interrupt + mask + 21 + 1 + + + + + MMCTFSCC + MMCTFSCC + Ethernet MMC transmitted good frames after a single collision counter + 0x4C + 0x20 + read-only + 0x00000000 + + + TGFSCC + Transmitted good frames single + collision counter + 0 + 32 + + + + + MMCTFMSCC + MMCTFMSCC + Ethernet MMC transmitted good frames after more than a single collision + 0x50 + 0x20 + read-only + 0x00000000 + + + TGFMSCC + Transmitted good frame more single + collision counter + 0 + 32 + + + + + MMCTFCNT + MMCTFCNT + Ethernet MMC transmitted good frames counter register + 0x68 + 0x20 + read-only + 0x00000000 + + + TGFC + Transmitted good frames + counter + 0 + 32 + + + + + MMCRFCECNT + MMCRFCECNT + Ethernet MMC received frames with CRC error counter register + 0x94 + 0x20 + read-only + 0x00000000 + + + RFCEC + Received frames CRC error counter + 0 + 32 + + + + + MMCRFAECNT + MMCRFAECNT + Ethernet MMC received frames with alignment error counter register + 0x98 + 0x20 + read-only + 0x00000000 + + + RFAEC + Received frames alignment error counter + 0 + 32 + + + + + MMCRGUFCNT + MMCRGUFCNT + MMC received good unicast frames counter register + 0xC4 + 0x20 + read-only + 0x00000000 + + + RGUFC + Received good unicast frames + counter + 0 + 32 + + + + + + + ETHERNET_PTP + Ethernet: Precision time protocol + ETHERNET + 0x40028700 + + 0x0 + 0x100 + registers + + + + PTPTSCTRL + PTPTSCTRL + Ethernet PTP time stamp control register + 0x0 + 0x20 + read-write + 0x2000 + + + TE + Timestamp enable + 0 + 1 + + + TFCU + Timestamp fine or coarse + update + 1 + 1 + + + TI + Timestamp initialize + 2 + 1 + + + TU + Timestamp update + 3 + 1 + + + TITE + Timestamp interrupt trigger + enable + 4 + 1 + + + ARU + Addend register update + 5 + 1 + + + ETAF + Enable timestamp for all frames + 8 + 1 + + + TDBRC + Timestamp digital or binary + rollover control + 9 + 1 + + + EPPV2F + Enable PTP packet processing for + version2 format + 10 + 1 + + + EPPEF + Enable processing of PTP + over EMAC frames + 11 + 1 + + + EPPFSIP6U + Enable processing of PTP frames + sent over IPv6-UDP + 12 + 1 + + + EPPFSIP4U + Enable processing of PTP frames + sent over IPv4-UDP + 13 + 1 + + + ETSFEM + Enable timestamp snapshot for + event message + 14 + 1 + + + ESFMRTM + Enable snapshot for message + relevant to master + 15 + 1 + + + SPPFTS + Select PTP packet for taking snapshot + 16 + 2 + + + EMAFPFF + Enable MAC address for PTP frame filtering + 18 + 1 + + + + + PTPSSINC + PTPSSINC + Ethernet PTP subsecond increment register + 0x4 + 0x20 + read-write + 0x00000000 + + + SSIV + Sub-second increment value + 0 + 8 + + + + + PTPTSH + PTPTSH + Ethernet PTP time stamp high register + 0x8 + 0x20 + read-only + 0x00000000 + + + TS + Timestamp second + 0 + 32 + + + + + PTPTSL + PTPTSL + Ethernet PTP time stamp low register + 0xC + 0x20 + read-only + 0x00000000 + + + TSS + Timestamp subseconds + 0 + 31 + + + AST + Add or subtract time + 31 + 1 + + + + + PTPTSHUD + PTPTSHUD + Ethernet PTP time stamp high update register + 0x10 + 0x20 + read-write + 0x00000000 + + + TS + Timestamp second + 0 + 32 + + + + + PTPTSLUD + PTPTSLUD + Ethernet PTP time stamp low update register + 0x14 + 0x20 + read-write + 0x00000000 + + + TSS + Timestamp subseconds + 0 + 31 + + + AST + Add or subtract time + 31 + 1 + + + + + PTPTSAD + PTPTSAD + Ethernet PTP time stamp addend register + 0x18 + 0x20 + read-write + 0x00000000 + + + TAR + Timestamp addend register + 0 + 32 + + + + + PTPTTH + PTPTTH + Ethernet PTP target time high register + 0x1C + 0x20 + read-write + 0x00000000 + + + TTSR + Target time seconds register + 0 + 32 + + + + + PTPTTL + PTPTTL + Ethernet PTP target time low register + 0x20 + 0x20 + read-write + 0x00000000 + + + TTLR + Target timestamp low register + 0 + 32 + + + + + PTPTSSR + PTPTSSR + Ethernet PTP time stamp status register + 0x28 + 0x20 + read-only + 0x00000000 + + + TSO + Timestamp second overflow + 0 + 1 + + + TTTR + Timestamp target time reached + 1 + 1 + + + + + PTPPPSCR + PTPPPSCR + Ethernet PTP PPS control register + 0x2C + 0x20 + read-only + 0x00000000 + + + POFC + PPS Output frequency control + 0 + 4 + + + + + + + ETHERNET_DMA + Ethernet: DMA controller operation + ETHERNET + 0x40029000 + + 0x0 + 0x100 + registers + + + + DMABM + DMABM + Ethernet DMA bus mode register + 0x0 + 0x20 + read-write + 0x20101 + + + SWR + Software reset + 0 + 1 + + + DA + DMA Arbitration + 1 + 1 + + + DSL + Descriptor skip length + 2 + 5 + + + PBL + Programmable burst length + 8 + 6 + + + PR + Priority ratio + 14 + 2 + + + FB + Fixed burst + 16 + 1 + + + RDP + Rx DMA PBL + 17 + 6 + + + USP + Use separate PBL + 23 + 1 + + + PBLx8 + PNLx8 mode + 24 + 1 + + + AAB + Address-aligned beats + 25 + 1 + + + + + DMATPD + DMATPD + Ethernet DMA transmit poll demand register + 0x4 + 0x20 + read-write + 0x00000000 + + + TPD + Transmit poll demand + 0 + 32 + + + + + DMARPD + DMARPD + EHERNET DMA receive poll demand register + 0x8 + 0x20 + read-write + 0x00000000 + + + RPD + Receive poll demand + 0 + 32 + + + + + DMARDLADDR + DMARDLADDR + Ethernet DMA receive descriptor list address register + 0xC + 0x20 + read-write + 0x00000000 + + + SRL + Start of receive list + 0 + 32 + + + + + DMATDLADDR + DMATDLADDR + Ethernet DMA transmit descriptor list address register + 0x10 + 0x20 + read-write + 0x00000000 + + + STL + Start of transmit list + 0 + 32 + + + + + DMASTS + DMASTS + Ethernet DMA status register + 0x14 + 0x20 + 0x00000000 + + + TI + Transmit interrupt + 0 + 1 + read-write + + + TPS + Transmit process stopped + 1 + 1 + read-write + + + TBU + Transmit buffer unavailable + 2 + 1 + read-write + + + TJT + Transmit jabber timeout + 3 + 1 + read-write + + + OVF + Receive overflow + 4 + 1 + read-write + + + UNF + Transmit underflow + 5 + 1 + read-write + + + RI + Receive interrupt + 6 + 1 + read-write + + + RBU + Receive buffer unavailable + 7 + 1 + read-write + + + RPS + Receive process stopped + 8 + 1 + read-write + + + RWT + Receive watchdog timeout + 9 + 1 + read-write + + + ETI + Early transmit interrupt + 10 + 1 + read-write + + + FBEI + Fatal bus error interrupt + 13 + 1 + read-write + + + ERI + Early receive interrupt + 14 + 1 + read-write + + + AIS + Abnormal interrupt summary + 15 + 1 + read-write + + + NIS + Normal interrupt summary + 16 + 1 + read-write + + + RS + Receive process state + 17 + 3 + read-only + + + TS + Transmit process state + 20 + 3 + read-only + + + EB + Error bits + 23 + 3 + read-only + + + MMI + MAC MMC interrupt + 27 + 1 + read-only + + + MPI + MAC PMT interrupt + 28 + 1 + read-only + + + TTI + Timestamp trigger interrupt + 29 + 1 + read-only + + + + + DMAOPM + DMAOPM + Ethernet DMA operation mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + SSR + Start or stop receive + 1 + 1 + + + OSF + Operate on second frame + 2 + 1 + + + RTC + Receive threshold control + 3 + 2 + + + FUGF + Forward undersized good frames + 6 + 1 + + + FEF + Forward error frames + 7 + 1 + + + SSTC + Start of stop transmission command + 13 + 1 + + + TTC + Transmit threshold control + 14 + 3 + + + FTF + Flush transmit FIFO + 20 + 1 + + + TSF + Transmit store and forward + 21 + 1 + + + DFRF + Disable flushing of received + frames + 24 + 1 + + + RSF + Receive store and forward + 25 + 1 + + + DT + Disable dropping of TCP/IP + checksum error frames + 26 + 1 + + + + + DMAIE + DMAIE + Ethernet DMA interrupt enable register + 0x1C + 0x20 + read-write + 0x00000000 + + + TIE + Transmit interrupt enable + 0 + 1 + + + TSE + Transmit stopped enable + 1 + 1 + + + TUE + Transmit buffer unavailable enable + 2 + 1 + + + TJE + Transmit jabber timeout enable + 3 + 1 + + + OVE + Overflow interrupt enable + 4 + 1 + + + UNE + Underflow interrupt enable + 5 + 1 + + + RIE + Receive interrupt enable + 6 + 1 + + + RBUE + Receive buffer unavailable enable + 7 + 1 + + + RSE + Receive stopped enable + 8 + 1 + + + RWTE + receive watchdog timeout enable + 9 + 1 + + + EIE + Early transmit interrupt enable + 10 + 1 + + + FBEE + Fatal bus error enable + 13 + 1 + + + ERE + Early receive interrupt + enable + 14 + 1 + + + AIE + Abnormal interrupt enable + 15 + 1 + + + NIE + Normal interrupt enable + 16 + 1 + + + + + DMAMFBOCNT + DMAMFBOCNT + Ethernet DMA missed frame and buffer overflow counter register + 0x20 + 0x20 + read-only + 0x00000000 + + + MFC + Missed frames control + 0 + 16 + + + OBMFC + Overflow bit for missed frame + counter + 16 + 1 + + + OFC + Overflow frame counter + 17 + 11 + + + OBFOC + Overflow bit for FIFO overflow + counter + 28 + 1 + + + + + DMACTD + DMACTD + Ethernet DMA current host transmit descriptor register + 0x48 + 0x20 + read-only + 0x00000000 + + + HTDAP + Host transmit descriptor address pointer + 0 + 32 + + + + + DMACRD + DMACRD + Ethernet DMA current host receive descriptor register + 0x4C + 0x20 + read-only + 0x00000000 + + + HRDAP + Host receive descriptor address pointer + 0 + 32 + + + + + DMACTBADDR + DMACTBADDR + Ethernet DMA current host transmit buffer address register + 0x50 + 0x20 + read-only + 0x00000000 + + + HTBAP + Host transmit buffer address pointer + 0 + 32 + + + + + DMACRBADDR + DMACRBADDR + Ethernet DMA current host receive buffer address register + 0x54 + 0x20 + read-only + 0x00000000 + + + HRBAP + Host receive buffer address pointer + 0 + 32 + + + + + + + diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.h b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.h new file mode 100644 index 000000000..ef4ec6dcf --- /dev/null +++ b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.h @@ -0,0 +1,182 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +//#define USB_VBUS_IGNORE +//#define USB_SOF_OUTPUT_ENABLE + +// LED +#define LED_PORT GPIOD +#define LED_PIN GPIO_PINS_13 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 1 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +// USART +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK +#define PRINT_UART_TX_PIN_SOURCE GPIO_PINS_SOURCE9 +#define PRINT_UART_TX_PIN_MUX_NUM GPIO_MUX_7 + +// USB +#ifdef BOARD_TUD_RHPORT + #if BOARD_TUD_RHPORT == 0 + #define USB_ID 0 + #define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK + #define OTG_IRQ OTGFS1_IRQn + #define OTG_IRQ_HANDLER OTGFS1_IRQHandler + #define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_18 + #define OTG_PIN_GPIO GPIOA + #define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_DP GPIO_PINS_12 + #define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE12 + #define OTG_PIN_DM GPIO_PINS_11 + #define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE11 + #define OTG_PIN_VBUS GPIO_PINS_9 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 + #define OTG_PIN_ID GPIO_PINS_10 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_8 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 + #define OTG_PIN_MUX GPIO_MUX_10 + #elif BOARD_TUD_RHPORT == 1 + #define USB_ID 1 + #define OTG_CLOCK CRM_OTGFS2_PERIPH_CLOCK + #define OTG_IRQ OTGFS2_IRQn + #define OTG_IRQ_HANDLER OTGFS2_IRQHandler + #define OTG_WKUP_IRQ OTGFS2_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGFS2_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_20 + #define OTG_PIN_GPIO GPIOB + #define OTG_PIN_GPIO_CLOCK CRM_GPIOB_PERIPH_CLOCK + #define OTG_PIN_DP GPIO_PINS_15 + #define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE15 + #define OTG_PIN_DM GPIO_PINS_14 + #define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE14 + #define OTG_PIN_VBUS GPIO_PINS_13 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 + #define OTG_PIN_ID GPIO_PINS_12 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_4 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE4 + #define OTG_PIN_MUX GPIO_MUX_12 + #endif +#endif + +#ifdef BOARD_TUH_RHPORT + #if BOARD_TUH_RHPORT == 0 + #define USB_ID 0 + #define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK + #define OTG_IRQ OTGFS1_IRQn + #define OTG_IRQ_HANDLER OTGFS1_IRQHandler + #define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_18 + #define OTG_PIN_GPIO GPIOA + #define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_DP GPIO_PINS_12 + #define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE12 + #define OTG_PIN_DM GPIO_PINS_11 + #define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE11 + #define OTG_PIN_VBUS GPIO_PINS_9 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 + #define OTG_PIN_ID GPIO_PINS_10 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_8 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 + #define OTG_PIN_MUX GPIO_MUX_10 + #elif BOARD_TUH_RHPORT == 1 + #define USB_ID 1 + #define OTG_CLOCK CRM_OTGFS2_PERIPH_CLOCK + #define OTG_IRQ OTGFS2_IRQn + #define OTG_IRQ_HANDLER OTGFS2_IRQHandler + #define OTG_WKUP_IRQ OTGFS2_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGFS2_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_20 + #define OTG_PIN_GPIO GPIOB + #define OTG_PIN_GPIO_CLOCK CRM_GPIOB_PERIPH_CLOCK + #define OTG_PIN_DP GPIO_PINS_15 + #define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE15 + #define OTG_PIN_DM GPIO_PINS_14 + #define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE14 + #define OTG_PIN_VBUS GPIO_PINS_13 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 + #define OTG_PIN_ID GPIO_PINS_12 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_4 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE4 + #define OTG_PIN_MUX GPIO_MUX_12 + #endif +#endif + +// VBUS +static inline void board_vbus_sense_init(void) +{ + #ifdef BOARD_TUD_RHPORT + #if BOARD_TUD_RHPORT == 0 + *(int*)(0x50000038) |= (1<<21); + #elif BOARD_TUD_RHPORT == 1 + *(int*)(0x40040038) |= (1<<21); + #endif + #endif + #ifdef BOARD_TUH_RHPORT + #if BOARD_TUH_RHPORT == 0 + *(int*)(0x50000038) |= (1<<21); + #elif BOARD_TUH_RHPORT == 1 + *(int*)(0x40040038) |= (1<<21); + #endif + #endif +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk new file mode 100644 index 000000000..823ae677d --- /dev/null +++ b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F437xM_FLASH.ld + +CFLAGS += \ + -DAT32F437ZMT7 diff --git a/hw/bsp/at32f435_437/family.c b/hw/bsp/at32f435_437/family.c new file mode 100644 index 000000000..c238fff32 --- /dev/null +++ b/hw/bsp/at32f435_437/family.c @@ -0,0 +1,370 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f435_437_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void usb_gpio_config(void); +void uart_print_init(uint32_t baudrate); +void usb_clock48m_select(usb_clk48_s clk_s); +void led_and_botton_init(void); +int inHandlerMode(void); +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTGFS1_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGFS2_IRQHandler(void) +{ + tusb_int_handler(1, true); +} +void OTGFS1_WKUP_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGFS2_WKUP_IRQHandler(void) +{ + tusb_int_handler(1, true); +} + +void board_init(void) +{ + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* config system clock to 288Mhz */ + system_clock_config(); + + /* config usb io */ + usb_gpio_config(); + + /* enable usb clock */ + crm_periph_clock_enable(OTG_CLOCK, TRUE); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HEXT); + + /* enable otgfs irq */ + //nvic_irq_enable(OTG_IRQ, 0, 0); + + /* vbus ignore */ + board_vbus_sense_init(); + + SysTick_Config(SystemCoreClock / 1000); +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + + /* config led and key */ + led_and_botton_init(); + + /* config usart printf */ + uart_print_init(115200); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + #ifdef BOARD_TUD_RHPORT + #if BOARD_TUD_RHPORT == 0 + acc_sof_select(ACC_SOF_OTG1); + #else + acc_sof_select(ACC_SOF_OTG2); + #endif + #endif + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + switch(system_core_clock) + { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_1); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_1_5); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + /* 120MHz */ + case 120000000: + crm_usb_clock_div_set(CRM_USB_DIV_2_5); + break; + + /* 144MHz */ + case 144000000: + crm_usb_clock_div_set(CRM_USB_DIV_3); + break; + + /* 168MHz */ + case 168000000: + crm_usb_clock_div_set(CRM_USB_DIV_3_5); + break; + + /* 192MHz */ + case 192000000: + crm_usb_clock_div_set(CRM_USB_DIV_4); + break; + + /* 216MHz */ + case 216000000: + crm_usb_clock_div_set(CRM_USB_DIV_4_5); + break; + + /* 240MHz */ + case 240000000: + crm_usb_clock_div_set(CRM_USB_DIV_5); + break; + + /* 264MHz */ + case 264000000: + crm_usb_clock_div_set(CRM_USB_DIV_5_5); + break; + + /* 288MHz */ + case 288000000: + crm_usb_clock_div_set(CRM_USB_DIV_6); + break; + + default: + break; + } + } +} + +void led_and_botton_init(void) +{ + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + gpio_bits_set(LED_PORT, LED_PIN); + gpio_bits_set(LED_PORT, GPIO_PINS_14); + gpio_bits_set(LED_PORT, GPIO_PINS_15); + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); +} + +/** + * @brief initialize uart + * @param baudrate: uart baudrate + * @retval none + */ +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + gpio_pin_mux_config(PRINT_UART_TX_GPIO, PRINT_UART_TX_PIN_SOURCE, PRINT_UART_TX_PIN_MUX_NUM); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +// Get characters from UART. Return number of read bytes +int board_uart_read(uint8_t *buf, int len) +{ + (void) buf; + (void) len; + return 0; +} +// Send characters to UART. Return number of sent bytes +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + +int inHandlerMode(void) +{ + return __get_IPSR(); +} + +void usb_gpio_config(void) +{ + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + /* dp and dm */ + gpio_init_struct.gpio_pins = OTG_PIN_DP | OTG_PIN_DM; + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_DP_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_DM_SOURCE, OTG_PIN_MUX); + #ifdef USB_SOF_OUTPUT_ENABLE + crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); + gpio_init_struct.gpio_pins = OTG_PIN_SOF; + gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + #endif + /* otgfs use vbus pin */ + #ifndef USB_VBUS_IGNORE + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); + #endif +} + +void board_led_write(bool state) +{ + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) +{ + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + uint32_t board_millis(void) + { + return system_ticks; + } + void SVC_Handler(void) + { + } + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) +{ + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/at32f435_437/family.mk b/hw/bsp/at32f435_437/family.mk new file mode 100644 index 000000000..47731b621 --- /dev/null +++ b/hw/bsp/at32f435_437/family.mk @@ -0,0 +1,45 @@ +# Submodules +AT32F435_437_SDK = hw/mcu/artery/at32f435_437 +DEPS_SUBMODULES += $(AT32F435_437_SDK) + +# AT32 SDK path +AT32F435_437_SDK_SRC = $(AT32F435_437_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F435_437 \ + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_gpio.c \ + $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_misc.c \ + $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_usart.c \ + $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_crm.c \ + $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_acc.c \ + $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_exint.c \ + $(AT32F435_437_SDK_SRC)/cmsis/cm4/device_support/system_at32f435_437.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F435_437_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F435_437_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F435_437_SDK_SRC)/cmsis/cm4/device_support \ + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f435_437.s + +# For freeRTOS port source +#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F + +flash: flash-atlink diff --git a/hw/bsp/at32f435_437/startup_at32f435_437.s b/hw/bsp/at32f435_437/startup_at32f435_437.s new file mode 100644 index 000000000..aa1aa3f4a --- /dev/null +++ b/hw/bsp/at32f435_437/startup_at32f435_437.s @@ -0,0 +1,569 @@ +/** + ****************************************************************************** + * @file startup_at32f435_437.s + * @brief at32f435_437 devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */ + .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word EDMA_Stream1_IRQHandler /* EDMA Stream 1 */ + .word EDMA_Stream2_IRQHandler /* EDMA Stream 2 */ + .word EDMA_Stream3_IRQHandler /* EDMA Stream 3 */ + .word EDMA_Stream4_IRQHandler /* EDMA Stream 4 */ + .word EDMA_Stream5_IRQHandler /* EDMA Stream 5 */ + .word EDMA_Stream6_IRQHandler /* EDMA Stream 6 */ + .word EDMA_Stream7_IRQHandler /* EDMA Stream 7 */ + .word ADC1_2_3_IRQHandler /* ADC1 & ADC2 & ADC3 */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 Channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_I2S2EXT_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word ERTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */ + .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */ + .word TMR8_BRK_TMR12_IRQHandler /* TMR8 Brake and TMR12 */ + .word TMR8_OVF_TMR13_IRQHandler /* TMR8 Overflow and TMR13 */ + .word TMR8_TRG_HALL_TMR14_IRQHandler /* TMR8 Trigger and hall and TMR14 */ + .word TMR8_CH_IRQHandler /* TMR8 Channel */ + .word EDMA_Stream8_IRQHandler /* EDMA Stream 8 */ + .word XMC_IRQHandler /* XMC */ + .word SDIO1_IRQHandler /* SDIO1 */ + .word TMR5_GLOBAL_IRQHandler /* TMR5 */ + .word SPI3_I2S3EXT_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TMR6_DAC_GLOBAL_IRQHandler /* TMR6 & DAC */ + .word TMR7_GLOBAL_IRQHandler /* TMR7 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word EMAC_IRQHandler /* EMAC */ + .word EMAC_WKUP_IRQHandler /* EMAC Wakeup */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SE_IRQHandler /* CAN2 SE */ + .word OTGFS1_IRQHandler /* OTGFS1 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word 0 /* Reserved */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EVT_IRQHandler /* I2C3 Event */ + .word I2C3_ERR_IRQHandler /* I2C3 Error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTGFS2_WKUP_IRQHandler /* OTGFS2 Wakeup from suspend */ + .word OTGFS2_IRQHandler /* OTGFS2 */ + .word DVP_IRQHandler /* DVP */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word QSPI2_IRQHandler /* QSPI2 */ + .word QSPI1_IRQHandler /* QSPI1 */ + .word 0 /* Reserved */ + .word DMAMUX_IRQHandler /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SDIO2_IRQHandler /* SDIO2 */ + .word ACC_IRQHandler /* ACC */ + .word TMR20_BRK_IRQHandler /* TMR20 Brake */ + .word TMR20_OVF_IRQHandler /* TMR20 Overflow */ + .word TMR20_TRG_HALL_IRQHandler /* TMR20 Trigger and hall */ + .word TMR20_CH_IRQHandler /* TMR20 Channel */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak ERTC_WKUP_IRQHandler + .thumb_set ERTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak EDMA_Stream1_IRQHandler + .thumb_set EDMA_Stream1_IRQHandler,Default_Handler + + .weak EDMA_Stream2_IRQHandler + .thumb_set EDMA_Stream2_IRQHandler,Default_Handler + + .weak EDMA_Stream3_IRQHandler + .thumb_set EDMA_Stream3_IRQHandler,Default_Handler + + .weak EDMA_Stream4_IRQHandler + .thumb_set EDMA_Stream4_IRQHandler,Default_Handler + + .weak EDMA_Stream5_IRQHandler + .thumb_set EDMA_Stream5_IRQHandler,Default_Handler + + .weak EDMA_Stream6_IRQHandler + .thumb_set EDMA_Stream6_IRQHandler,Default_Handler + + .weak EDMA_Stream7_IRQHandler + .thumb_set EDMA_Stream7_IRQHandler,Default_Handler + + .weak ADC1_2_3_IRQHandler + .thumb_set ADC1_2_3_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_I2S2EXT_IRQHandler + .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak ERTCAlarm_IRQHandler + .thumb_set ERTCAlarm_IRQHandler,Default_Handler + + .weak OTGFS1_WKUP_IRQHandler + .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler + + .weak TMR8_BRK_TMR12_IRQHandler + .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler + + .weak TMR8_OVF_TMR13_IRQHandler + .thumb_set TMR8_OVF_TMR13_IRQHandler,Default_Handler + + .weak TMR8_TRG_HALL_TMR14_IRQHandler + .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler + + .weak TMR8_CH_IRQHandler + .thumb_set TMR8_CH_IRQHandler,Default_Handler + + .weak EDMA_Stream8_IRQHandler + .thumb_set EDMA_Stream8_IRQHandler,Default_Handler + + .weak XMC_IRQHandler + .thumb_set XMC_IRQHandler,Default_Handler + + .weak SDIO1_IRQHandler + .thumb_set SDIO1_IRQHandler,Default_Handler + + .weak TMR5_GLOBAL_IRQHandler + .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler + + .weak SPI3_I2S3EXT_IRQHandler + .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TMR6_DAC_GLOBAL_IRQHandler + .thumb_set TMR6_DAC_GLOBAL_IRQHandler,Default_Handler + + .weak TMR7_GLOBAL_IRQHandler + .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak EMAC_IRQHandler + .thumb_set EMAC_IRQHandler,Default_Handler + + .weak EMAC_WKUP_IRQHandler + .thumb_set EMAC_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler ,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler ,Default_Handler + + .weak CAN2_SE_IRQHandler + .thumb_set CAN2_SE_IRQHandler,Default_Handler + + .weak OTGFS1_IRQHandler + .thumb_set OTGFS1_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EVT_IRQHandler + .thumb_set I2C3_EVT_IRQHandler,Default_Handler + + .weak I2C3_ERR_IRQHandler + .thumb_set I2C3_ERR_IRQHandler,Default_Handler + + .weak OTGFS2_WKUP_IRQHandler + .thumb_set OTGFS2_WKUP_IRQHandler,Default_Handler + + .weak OTGFS2_IRQHandler + .thumb_set OTGFS2_IRQHandler,Default_Handler + + .weak DVP_IRQHandler + .thumb_set DVP_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak QSPI2_IRQHandler + .thumb_set QSPI2_IRQHandler,Default_Handler + + .weak QSPI1_IRQHandler + .thumb_set QSPI1_IRQHandler,Default_Handler + + .weak DMAMUX_IRQHandler + .thumb_set DMAMUX_IRQHandler ,Default_Handler + + .weak SDIO2_IRQHandler + .thumb_set SDIO2_IRQHandler ,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler + + .weak TMR20_BRK_IRQHandler + .thumb_set TMR20_BRK_IRQHandler,Default_Handler + + .weak TMR20_OVF_IRQHandler + .thumb_set TMR20_OVF_IRQHandler,Default_Handler + + .weak TMR20_TRG_HALL_IRQHandler + .thumb_set TMR20_TRG_HALL_IRQHandler,Default_Handler + + .weak TMR20_CH_IRQHandler + .thumb_set TMR20_CH_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index a08ed79c8..41c291600 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -550,6 +550,44 @@ #define TUP_RHPORT_HIGHSPEED 1 #define TUD_ENDPOINT_ONE_DIRECTION_ONLY +//--------------------------------------------------------------------+ +// ArteryTek +//--------------------------------------------------------------------+ +#elif TU_CHECK_MCU(OPT_MCU_AT32F403A_407) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_AT32 + #define TUP_DCD_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(OPT_MCU_AT32F413) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_AT32 + #define TUP_DCD_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(OPT_MCU_AT32F415) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_AT32 + #define TUP_DCD_ENDPOINT_MAX 4 + +#elif TU_CHECK_MCU(OPT_MCU_AT32F435_437) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_AT32 + #define TUP_DCD_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(OPT_MCU_AT32F423) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_AT32 + #define TUP_DCD_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(OPT_MCU_AT32F402_405) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_AT32 + #define TUP_DCD_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(OPT_MCU_AT32F425) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_AT32 + #define TUP_DCD_ENDPOINT_MAX 8 + #endif //--------------------------------------------------------------------+ diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index ef58957bb..5d6033a66 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -117,6 +117,8 @@ #include "fsdev_stm32.h" #elif defined(TUP_USBIP_FSDEV_CH32) #include "fsdev_ch32.h" +#elif defined(TUP_USBIP_FSDEV_AT32) + #include "fsdev_at32.h" #else #error "Unknown USB IP" #endif diff --git a/src/portable/st/stm32_fsdev/fsdev_at32.h b/src/portable/st/stm32_fsdev/fsdev_at32.h new file mode 100644 index 000000000..5f2ce4ba2 --- /dev/null +++ b/src/portable/st/stm32_fsdev/fsdev_at32.h @@ -0,0 +1,224 @@ +/* +* The MIT License (MIT) + * + * Copyright (c) 2024, hathach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ +#ifndef TUSB_FSDEV_AT32_H +#define TUSB_FSDEV_AT32_H + +#include "common/tusb_compiler.h" + +#if CFG_TUSB_MCU == OPT_MCU_AT32F403A_407 + #include "at32f403a_407.h" + +#elif CFG_TUSB_MCU == OPT_MCU_AT32F413 + #include "at32f413.h" + +#endif + +//#include "fsdev_common.h" + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) +static const IRQn_Type fsdev_irq[] = { + USBFS_H_CAN1_TX_IRQn, + USBFS_L_CAN1_RX0_IRQn, + USBFSWakeUp_IRQn +}; +enum { FSDEV_IRQ_NUM = TU_ARRAY_SIZE(fsdev_irq) }; + +#else + #error "Unsupported MCU" +#endif + +void dcd_int_enable(uint8_t rhport) { + (void)rhport; + #if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) + // AT32F403A/407 devices allow to remap the USB interrupt vectors from + // shared USB/CAN IRQs to separate CAN and USB IRQs. + // This dynamically checks if this remap is active to enable the right IRQs. + if (CRM->intmap_bit.usbintmap) { + NVIC_DisableIRQ(USBFS_MAPH_IRQn); + NVIC_DisableIRQ(USBFS_MAPL_IRQn); + NVIC_DisableIRQ(USBFSWakeUp_IRQn); + } else + #endif + { + for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) { + NVIC_EnableIRQ(fsdev_irq[i]); + } + } +} + +void dcd_int_disable(uint8_t rhport) { + (void)rhport; + #if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) + // AT32F403A/407 devices allow to remap the USB interrupt vectors from + // shared USB/CAN IRQs to separate CAN and USB IRQs. + // This dynamically checks if this remap is active to enable the right IRQs. + if (CRM->intmap_bit.usbintmap) { + NVIC_DisableIRQ(USBFS_MAPH_IRQn); + NVIC_DisableIRQ(USBFS_MAPL_IRQn); + NVIC_DisableIRQ(USBFSWakeUp_IRQn); + } else + #endif + { + for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) { + NVIC_DisableIRQ(fsdev_irq[i]); + } + } +} + +void dcd_disconnect(uint8_t rhport) { + (void) rhport; + /* disable usb phy */ + //USB->ctrl_bit.disusb = TRUE; + *(int *)(0x40000000+0x5C00+0x40) |= (1<<1); + *(int *)(0x40000000+0x5C00+0x60) |= (1<<1); + /* D+ 1.5k pull-up disable */ + //USB->cfg_bit.puo = TRUE; +} + +void dcd_connect(uint8_t rhport) { + (void) rhport; + /* enable usb phy */ + //USB->ctrl_bit.disusb = 0; + *(int *)(0x40000000+0x5C00+0x40) &= ~(1<<1); + *(int *)(0x40000000+0x5C00+0x60) &= ~(1<<1); + /* Dp 1.5k pull-up enable */ + //USB->cfg_bit.puo = 0; +} + +#define FSDEV_PMA_SIZE (512u) +#define FSDEV_REG_BASE (APB1PERIPH_BASE + 0x00005C00UL) +#define FSDEV_PMA_BASE (APB1PERIPH_BASE + 0x00006000UL) + +/**************************** ISTR interrupt events *************************/ +#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */ +#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */ +#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */ +#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */ +#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */ +#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */ +#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */ +#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */ +#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */ +#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */ + +/* Legacy defines */ +#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR + +#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */ +#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/ +#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */ +#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */ +#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */ +#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */ +#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */ +#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */ + +/* Legacy defines */ +#define USB_CLR_PMAOVRM USB_CLR_PMAOVR + +/************************* CNTR control register bits definitions ***********/ +#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */ +#define USB_CNTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */ +#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */ +#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */ +#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */ +#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */ +#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */ +#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */ +#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */ +#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */ +#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */ +#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */ +#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */ + +/* Legacy defines */ +#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR +#define USB_CNTR_LP_MODE USB_CNTR_LPMODE + +/******************** FNR Frame Number Register bit definitions ************/ +#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */ +#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */ +#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */ +#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */ +#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */ + +/******************** DADDR Device ADDRess bit definitions ****************/ +#define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */ +#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */ + +/****************************** Endpoint register *************************/ +#define USB_EP0R USB_BASE /*!< endpoint 0 register address */ +#define USB_EP1R (USB_BASE + 0x04U) /*!< endpoint 1 register address */ +#define USB_EP2R (USB_BASE + 0x08U) /*!< endpoint 2 register address */ +#define USB_EP3R (USB_BASE + 0x0CU) /*!< endpoint 3 register address */ +#define USB_EP4R (USB_BASE + 0x10U) /*!< endpoint 4 register address */ +#define USB_EP5R (USB_BASE + 0x14U) /*!< endpoint 5 register address */ +#define USB_EP6R (USB_BASE + 0x18U) /*!< endpoint 6 register address */ +#define USB_EP7R (USB_BASE + 0x1CU) /*!< endpoint 7 register address */ +/* bit positions */ +#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */ +#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */ +#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */ +#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */ +#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */ +#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */ +#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */ +#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */ +#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */ +#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */ + +/* EndPoint REGister MASK (no toggle fields) */ +#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) + /*!< EP_TYPE[1:0] EndPoint TYPE */ +#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */ +#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */ +#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */ +#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */ +#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */ +#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK) + +#define USB_EPKIND_MASK ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ + /*!< STAT_TX[1:0] STATus for TX transfer */ +#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */ +#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */ +#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */ +#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */ +#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */ +#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */ +#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) + /*!< STAT_RX[1:0] STATus for RX transfer */ +#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */ +#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */ +#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */ +#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */ +#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */ +#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */ +#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) + +#endif diff --git a/src/portable/synopsys/dwc2/dwc2_at32.h b/src/portable/synopsys/dwc2/dwc2_at32.h new file mode 100644 index 000000000..10832a702 --- /dev/null +++ b/src/portable/synopsys/dwc2/dwc2_at32.h @@ -0,0 +1,135 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef DWC2_AT32_H_ +#define DWC2_AT32_H_ + +#define DWC2_EP_MAX TUP_DCD_ENDPOINT_MAX + +#if CFG_TUSB_MCU == OPT_MCU_AT32F415 + #include + #define OTG1_FIFO_SIZE 1280 + #define OTG1_IRQn OTGFS1_IRQn + #define DWC2_OTG1_REG_BASE 0x50000000UL +#elif CFG_TUSB_MCU == OPT_MCU_AT32F435_437 + #include + #define OTG1_FIFO_SIZE 1280 + #define OTG2_FIFO_SIZE 1280 + #define OTG1_IRQn OTGFS1_IRQn + #define OTG2_IRQn OTGFS2_IRQn + #define DWC2_OTG1_REG_BASE 0x50000000UL + #define DWC2_OTG2_REG_BASE 0x40040000UL +#elif CFG_TUSB_MCU == OPT_MCU_AT32F423 + #include + #define OTG1_FIFO_SIZE 1280 + #define OTG1_IRQn OTGFS1_IRQn + #define DWC2_OTG1_REG_BASE 0x50000000UL +#elif CFG_TUSB_MCU == OPT_MCU_AT32F402_405 + #include + #define OTG1_FIFO_SIZE 1280 + #define OTG2_FIFO_SIZE 4096 + #define OTG1_IRQn OTGFS1_IRQn + #define OTG2_IRQn OTGHS_IRQn + #define DWC2_OTG1_REG_BASE 0x50000000UL + #define DWC2_OTG2_REG_BASE 0x40040000UL //OTGHS +#elif CFG_TUSB_MCU == OPT_MCU_AT32F425 + #include + #define OTG1_FIFO_SIZE 1280 + #define OTG1_IRQn OTGFS1_IRQn + #define DWC2_OTG1_REG_BASE 0x50000000UL +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +static const dwc2_controller_t _dwc2_controller[] = +{ + { .reg_base = DWC2_OTG1_REG_BASE, .irqnum = OTG1_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG1_FIFO_SIZE }, + #if defined DWC2_OTG2_REG_BASE + { .reg_base = DWC2_OTG2_REG_BASE, .irqnum = OTG2_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG2_FIFO_SIZE } + #endif +}; + +TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) { + (void) role; + const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum; + if (enabled) { + NVIC_EnableIRQ(irqn); + } else { + NVIC_DisableIRQ(irqn); + } +} + +TU_ATTR_ALWAYS_INLINE +static inline void dwc2_dcd_int_enable(uint8_t rhport) +{ + NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum); +} + +TU_ATTR_ALWAYS_INLINE +static inline void dwc2_dcd_int_disable (uint8_t rhport) +{ + NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum); +} + +static inline void dwc2_remote_wakeup_delay(void) +{ + // try to delay for 1 ms + uint32_t count = system_core_clock / 1000; + while ( count-- ) __asm volatile ("nop"); +} + +// MCU specific PHY init, called BEFORE core reset +static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) +{ + (void) dwc2; + // Enable on-chip HS PHY + if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) + { + + } + else if(hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) + { + + } +} + +// MCU specific PHY update, it is called AFTER init() and core reset +static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) +{ + (void) dwc2; + (void) hs_phy_type; + + dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN; +} + +#ifdef __cplusplus +} +#endif + +#endif /* DWC2_GD32_H_ */ diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index e1e7d5c1a..56326d5a7 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -121,6 +121,12 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // Set 16-bit interface if supported if (ghwcfg4.phy_data_width) { gusbcfg |= GUSBCFG_PHYIF16; // 16 bit + + /* at32f402_405 does not actually support 16-bit */ + #if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 + gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit + #endif + } else { gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit } @@ -139,7 +145,13 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // - 9 if using 8-bit PHY interface // - 5 if using 16-bit PHY interface gusbcfg &= ~GUSBCFG_TRDT_Msk; - gusbcfg |= (ghwcfg4.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; + gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; + + /* at32f402_405 does not actually support 16-bit */ + #if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 + gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 9u : 9u) << GUSBCFG_TRDT_Pos; + #endif + dwc2->gusbcfg = gusbcfg; // MCU specific PHY update post reset diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h index 18b93894f..33219f786 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.h +++ b/src/portable/synopsys/dwc2/dwc2_common.h @@ -49,6 +49,8 @@ #include "dwc2_efm32.h" #elif TU_CHECK_MCU(OPT_MCU_XMC4000) #include "dwc2_xmc.h" +#elif defined(TUP_USBIP_DWC2_AT32) + #include "dwc2_at32.h" #else #error "Unsupported MCUs" #endif diff --git a/src/tusb_option.h b/src/tusb_option.h index 867babc33..ebd8d9add 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -201,6 +201,15 @@ #define OPT_MCU_MAX32650 2402 ///< ADI MAX32650/1/2 #define OPT_MCU_MAX78002 2403 ///< ADI MAX78002 +// ArteryTek +#define OPT_MCU_AT32F403A_407 2500 ///< ArteryTek AT32F403A_AT32F407 +#define OPT_MCU_AT32F415 2501 ///< ArteryTek AT32F415 +#define OPT_MCU_AT32F435_437 2502 ///< ArteryTek AT32F435_AT32F437 +#define OPT_MCU_AT32F423 2503 ///< ArteryTek AT32F423 +#define OPT_MCU_AT32F402_405 2504 ///< ArteryTek AT32F402_405 +#define OPT_MCU_AT32F425 2505 ///< ArteryTek AT32F425 +#define OPT_MCU_AT32F413 2506 ///< ArteryTek AT32F413 + // Check if configured MCU is one of listed // Apply _TU_CHECK_MCU with || as separator to list of input #define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == _m) diff --git a/tools/get_deps.py b/tools/get_deps.py index 6a36ef35d..9a5fa37d9 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -208,6 +208,27 @@ deps_optional = { 'hw/mcu/wch/ch32f20x': ['https://github.com/openwch/ch32f20x.git', '77c4095087e5ed2c548ec9058e655d0b8757663b', 'ch32f20x'], + 'hw/mcu/artery/at32f403a_407': ['https://github.com/ArteryTek/AT32F403A_407_Firmware_Library.git', + 'f2cb360c3d28fada76b374308b8c4c61d37a090b', + 'at32f403a_407'], + 'hw/mcu/artery/at32f415': ['https://github.com/ArteryTek/AT32F415_Firmware_Library.git', + '716f545aa1290ff144ccf023a8e797b951e1bc8e', + 'at32f415'], + 'hw/mcu/artery/at32f435_437': ['https://github.com/ArteryTek/AT32F435_437_Firmware_Library.git', + '25439cc6650a8ae0345934e8707a5f38c7ae41f8', + 'at32f435_437'], + 'hw/mcu/artery/at32f423': ['https://github.com/ArteryTek/AT32F423_Firmware_Library.git', + '2afa7f12852e57a9e8aab3a892c641e1a8635a18', + 'at32f423'], + 'hw/mcu/artery/at32f402_405': ['https://github.com/ArteryTek/AT32F402_405_Firmware_Library.git', + '4424515c2663e82438654e0947695295df2abdfe', + 'at32f402_405'], + 'hw/mcu/artery/at32f425': ['https://github.com/ArteryTek/AT32F425_Firmware_Library.git', + '620233e1357d5c1b7e2bde6b9dd5196822b91817', + 'at32f425'], + 'hw/mcu/artery/at32f413': ['https://github.com/ArteryTek/AT32F413_Firmware_Library.git', + 'f6fe62dfec9fd40c5b63d92fc5ef2c2b5e77a450', + 'at32f413'], 'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git', '2b7495b8535bdcb306dac29b9ded4cfb679d7e5c', 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf saml2x ' -- cgit v1.3.1 From 3682b6c6631c63f1dac2096787c0f983ac77e734 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 28 Jul 2025 22:28:22 +0700 Subject: fix pre-commit, remove svd file since they are heavy and should be in mcu/sdk instead add cmake support for f403a_407 and f423 --- .../at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/at32f402_405/at32f402_405_clock.c | 2 +- hw/bsp/at32f402_405/at32f402_405_clock.h | 1 - hw/bsp/at32f402_405/at32f402_405_int.c | 1 - hw/bsp/at32f402_405/at32f402_405_int.h | 1 - .../boards/AT_START_F402_405/AT32F405xC_FLASH.ld | 4 +- .../boards/AT_START_F402_405/AT32F405xx_v2.svd | 45983 --------------- .../at32f402_405/boards/AT_START_F402_405/board.h | 2 +- hw/bsp/at32f402_405/family.c | 23 +- hw/bsp/at32f402_405/family.mk | 1 - hw/bsp/at32f402_405/startup_at32f402_405.s | 30 +- .../at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/at32f403a_407/at32f403a_407_clock.c | 2 +- hw/bsp/at32f403a_407/at32f403a_407_clock.h | 1 - hw/bsp/at32f403a_407/at32f403a_407_conf.h | 6 +- hw/bsp/at32f403a_407/at32f403a_407_int.h | 1 - .../boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld | 4 +- .../boards/AT_START_F403A_407/AT32F407xx_v2.svd | 28047 --------- .../boards/AT_START_F403A_407/board.cmake | 9 + .../boards/AT_START_F403A_407/board.mk | 1 + hw/bsp/at32f403a_407/family.c | 110 +- hw/bsp/at32f403a_407/family.cmake | 102 + hw/bsp/at32f403a_407/family.mk | 3 +- hw/bsp/at32f403a_407/startup_at32f403a_407.s | 2 +- hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/at32f413/at32f413_clock.h | 1 - hw/bsp/at32f413/at32f413_int.c | 2 - hw/bsp/at32f413/at32f413_int.h | 1 - .../boards/AT_START_F413/AT32F413xC_FLASH.ld | 6 +- .../boards/AT_START_F413/AT32F413xx_v2.svd | 23368 -------- hw/bsp/at32f413/boards/AT_START_F413/board.h | 2 +- hw/bsp/at32f413/family.c | 12 +- hw/bsp/at32f413/family.mk | 1 - hw/bsp/at32f413/startup_at32f413.s | 2 +- hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/at32f415/at32f415_clock.c | 14 +- hw/bsp/at32f415/at32f415_clock.h | 11 +- hw/bsp/at32f415/at32f415_conf.h | 12 +- hw/bsp/at32f415/at32f415_int.c | 22 +- hw/bsp/at32f415/at32f415_int.h | 11 +- .../boards/AT_START_F415/AT32F415xC_FLASH.ld | 4 +- .../boards/AT_START_F415/AT32F415xx_v2.svd | 27108 --------- hw/bsp/at32f415/family.c | 28 +- hw/bsp/at32f415/family.mk | 1 - hw/bsp/at32f415/startup_at32f415.s | 2 +- hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/at32f423/at32f423_clock.c | 1 - hw/bsp/at32f423/at32f423_clock.h | 1 - hw/bsp/at32f423/at32f423_int.c | 1 - hw/bsp/at32f423/at32f423_int.h | 1 - .../boards/AT_START_F423/AT32F423xC_FLASH.ld | 4 +- .../boards/AT_START_F423/AT32F423xx_v2.svd | 36050 ------------ hw/bsp/at32f423/boards/AT_START_F423/board.cmake | 9 + hw/bsp/at32f423/boards/AT_START_F423/board.mk | 1 + hw/bsp/at32f423/family.c | 167 +- hw/bsp/at32f423/family.cmake | 104 + hw/bsp/at32f423/family.mk | 6 +- hw/bsp/at32f423/startup_at32f423.s | 2 +- hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/at32f425/at32f425_clock.h | 1 - hw/bsp/at32f425/at32f425_int.c | 1 - hw/bsp/at32f425/at32f425_int.h | 1 - .../boards/AT_START_F425/AT32F425x8_FLASH.ld | 4 +- .../boards/AT_START_F425/AT32F425xx_v2.svd | 30790 ---------- hw/bsp/at32f425/family.c | 28 +- hw/bsp/at32f425/family.mk | 1 - hw/bsp/at32f425/startup_at32f425.s | 2 +- .../at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/at32f435_437/at32f435_437_clock.h | 1 - hw/bsp/at32f435_437/at32f435_437_int.c | 1 - hw/bsp/at32f435_437/at32f435_437_int.h | 1 - .../boards/AT_START_F435_437/AT32F437xM_FLASH.ld | 4 +- .../boards/AT_START_F435_437/AT32F437xx_v2.svd | 58291 ------------------- hw/bsp/at32f435_437/family.c | 26 +- hw/bsp/at32f435_437/family.mk | 1 - hw/bsp/at32f435_437/startup_at32f435_437.s | 2 +- src/portable/synopsys/dwc2/dwc2_at32.h | 6 +- 77 files changed, 497 insertions(+), 249969 deletions(-) delete mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd delete mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd create mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake create mode 100644 hw/bsp/at32f403a_407/family.cmake delete mode 100644 hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd delete mode 100644 hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd delete mode 100644 hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd create mode 100644 hw/bsp/at32f423/boards/AT_START_F423/board.cmake create mode 100644 hw/bsp/at32f423/family.cmake delete mode 100644 hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd delete mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd diff --git a/hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h index d86c92542..1f75a7cb0 100644 --- a/hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h @@ -109,7 +109,7 @@ #define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 #define INCLUDE_uxTaskGetStackHighWaterMark 0 #define INCLUDE_xTaskGetIdleTaskHandle 0 #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 diff --git a/hw/bsp/at32f402_405/at32f402_405_clock.c b/hw/bsp/at32f402_405/at32f402_405_clock.c index a74cd78ca..d9a1b5eef 100644 --- a/hw/bsp/at32f402_405/at32f402_405_clock.c +++ b/hw/bsp/at32f402_405/at32f402_405_clock.c @@ -121,7 +121,7 @@ void system_clock_config(void) #endif #ifdef AT32F402xx - /* reduce power comsumption */ + /* reduce power consumption */ reduce_power_consumption(); #endif } diff --git a/hw/bsp/at32f402_405/at32f402_405_clock.h b/hw/bsp/at32f402_405/at32f402_405_clock.h index b098f3718..30f5ae45d 100644 --- a/hw/bsp/at32f402_405/at32f402_405_clock.h +++ b/hw/bsp/at32f402_405/at32f402_405_clock.h @@ -41,4 +41,3 @@ void system_clock_config(void); #endif #endif - diff --git a/hw/bsp/at32f402_405/at32f402_405_int.c b/hw/bsp/at32f402_405/at32f402_405_int.c index 924431ee2..7f2fb6fa7 100644 --- a/hw/bsp/at32f402_405/at32f402_405_int.c +++ b/hw/bsp/at32f402_405/at32f402_405_int.c @@ -137,4 +137,3 @@ void DebugMon_Handler(void) /** * @} */ - diff --git a/hw/bsp/at32f402_405/at32f402_405_int.h b/hw/bsp/at32f402_405/at32f402_405_int.h index f83964feb..207a7d6df 100644 --- a/hw/bsp/at32f402_405/at32f402_405_int.h +++ b/hw/bsp/at32f402_405/at32f402_405_int.h @@ -53,4 +53,3 @@ void SysTick_Handler(void); #endif #endif - diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xC_FLASH.ld b/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xC_FLASH.ld index 26a1ecddb..0b3550ddb 100644 --- a/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xC_FLASH.ld +++ b/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xC_FLASH.ld @@ -104,7 +104,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -119,7 +119,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd b/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd deleted file mode 100644 index 94a12b0f4..000000000 --- a/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd +++ /dev/null @@ -1,45983 +0,0 @@ - - - - - - - - Keil - ArteryTek - AT32F405xx_v2 - AT32F405 - 1.0 - ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 168MHz, etc. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - CM4 - r0p1 - little - false - true - 4 - false - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - - PWC - Power control - PWC - 0x40007000 - - 0x0 - 0x400 - registers - - - - CTRL - CTRL - Power control register - (PWC_CTRL) - 0x0 - 0x20 - read-write - 0x00000000 - - - VRSEL - Voltage regulator state select when deepsleep mode - 0 - 1 - - - LPSEL - Low power mode select when Cortex-M4F sleepdeep - 1 - 1 - - - CLSWEF - Clear SWEF flag - 2 - 1 - - - CLSEF - Clear SEF flag - 3 - 1 - - - PVMEN - Power voltage monitoring enable - 4 - 1 - - - PVMSEL - Power voltage monitoring boundary select - 5 - 3 - - - BPWEN - Battery powered domain write enable - 8 - 1 - - - - - CTRLSTS - CTRLSTS - Power control and status register - (PWC_CTRLSTS) - 0x4 - 0x20 - 0x00000000 - - - SWEF - Standby wake-up event flag - 0 - 1 - read-only - - - SEF - Standby mode entry flag - 1 - 1 - read-only - - - PVMOF - Power voltage monitoring output flag - 2 - 1 - read-only - - - SWPEN1 - Standby wake-up pin 1 enable - 8 - 1 - read-write - - - SWPEN2 - Standby wake-up pin 2 enable - 9 - 1 - read-write - - - SWPEN6 - Standby wake-up pin 6 enable - 13 - 1 - read-write - - - - - LDOOV - LDOOV - LDO output voltage register - 0x10 - 0x20 - 0x00000012 - - - LDOOVSEL - LDO output voltage select - 0 - 2 - read-write - - - VREXLPEN - Voltage regulator extra low power mode enable - 4 - 1 - read-write - - - - - - - CRM - Clock and reset management - CRM - 0x40023800 - - 0x0 - 0x400 - registers - - - CRM - CRM global interrupt - 5 - - - - CTRL - CTRL - Clock control register - 0x0 - 0x20 - 0x00000083 - - - HICKEN - High speed internal clock enable - 0 - 1 - read-write - - - HICKSTBL - High speed internal clock ready flag - 1 - 1 - read-only - - - HICKTRIM - High speed internal clock trimming - 2 - 6 - read-write - - - HICKCAL - High speed internal clock calibration - 8 - 8 - read-only - - - HEXTEN - High speed exernal crystal enable - 16 - 1 - read-write - - - HEXTSTBL - High speed exernal crystal ready flag - 17 - 1 - read-only - - - HEXTBYPS - High speed exernal crystal bypass - 18 - 1 - read-write - - - CFDEN - Clock failure detection enable - 19 - 1 - read-write - - - PLLEN - PLL enable - 24 - 1 - read-write - - - PLLSTBL - PLL clock ready flag - 25 - 1 - read-only - - - PLLUSTBL - PLLU clock ready flag - 26 - 1 - read-only - - - - - PLLCFG - PLLCFG - PLL configuration register - (CRM_PLLCFG) - 0x4 - 0x20 - 0x00033002 - - - PLL_MS - PLL pre-division - 0 - 4 - read-write - - - PLL_NS - PLL frequency multiplication factor - 6 - 9 - read-write - - - PLL_FP - PLLP post-division - 16 - 4 - read-write - - - PLL_FU - PLLU post-division - 20 - 3 - read-write - - - PLLU_EN - PLLU enable - 29 - 1 - read-write - - - PLLRCS - PLL reference clock select - 30 - 1 - read-write - - - - - CFG - CFG - Clock configuration register(CRM_CFG) - 0x8 - 0x20 - 0x00000000 - - - SCLKSEL - System clock select - 0 - 2 - read-write - - - SCLKSTS - System Clock select Status - 2 - 2 - read-only - - - AHBDIV - AHB division - 4 - 4 - read-write - - - APB1DIV - APB1 division - 10 - 3 - read-write - - - APB2DIV - APB2 division - 13 - 3 - read-write - - - ERTCDIV - HEXT division for ERTC clock - 16 - 5 - read-write - - - I2S5CLKSEL - I2S clock select - 22 - 2 - read-write - - - CLKOUTDIV1 - Clock output division1 - 27 - 3 - read-write - - - CLKOUT_SEL1 - Clock output selection1 - 30 - 2 - read-write - - - - - CLKINT - CLKINT - Clock interrupt register - (CRM_CLKINT) - 0xC - 0x20 - 0x00000000 - - - LICKSTBLF - LICK ready interrupt flag - 0 - 1 - read-only - - - LEXTSTBLF - LEXT ready interrupt flag - 1 - 1 - read-only - - - HICKSTBLF - HICK ready interrupt flag - 2 - 1 - read-only - - - HEXTSTBLF - HEXT ready interrupt flag - 3 - 1 - read-only - - - PLLSTBLF - PLL ready interrupt flag - 4 - 1 - read-only - - - CFDF - Clock failure detection interrupt flag - 7 - 1 - read-only - - - LICKSTBLIEN - LICK ready interrupt enable - 8 - 1 - read-write - - - LEXTSTBLIEN - LEXT ready interrupt enable - 9 - 1 - read-write - - - HICKSTBLIEN - HICK ready interrupt enable - 10 - 1 - read-write - - - HEXTSTBLIEN - HEXT ready interrupt enable - 11 - 1 - read-write - - - PLLSTBLIEN - PLL ready interrupt enable - 12 - 1 - read-write - - - LICKSTBLFC - LICK ready interrupt clear - 16 - 1 - write-only - - - LEXTSTBLFC - LEXT ready interrupt clear - 17 - 1 - write-only - - - HICKSTBLFC - HICK ready interrupt clear - 18 - 1 - write-only - - - HEXTSTBLFC - HEXT ready interrupt clear - 19 - 1 - write-only - - - PLLSTBLFC - PLL ready interrupt clear - 20 - 1 - write-only - - - CFDFC - Clock failure detection interrupt clear - 23 - 1 - write-only - - - - - AHBRST1 - AHBRST1 - AHB peripheral reset register1 - (CRM_AHBRST1) - 0x10 - 0x20 - read-write - 0x000000000 - - - GPIOARST - IO port A reset - 0 - 1 - - - GPIOBRST - IO port B reset - 1 - 1 - - - GPIOCRST - IO port C reset - 2 - 1 - - - GPIODRST - IO port D reset - 3 - 1 - - - GPIOFRST - IO port F reset - 5 - 1 - - - CRCRST - CRC reset - 12 - 1 - - - DMA1RST - DMA1 reset - 22 - 1 - - - DMA2RST - DMA2 reset - 24 - 1 - - - OTGHSRST - OTGHS interface reset - 29 - 1 - - - - - AHBRST2 - AHBRST2 - AHB peripheral reset register 2 - (CRM_AHBRST2) - 0x14 - 0x20 - read-write - 0x00000000 - - - OTGFS1RST - OTGFS1 reset - 7 - 1 - - - - - AHBRST3 - AHBRST3 - AHB peripheral reset register 3 - (CRM_AHBRST3) - 0x18 - 0x20 - read-write - 0x00000000 - - - QSPI1RST - QSPI1 reset - 1 - 1 - - - - - APB1RST - APB1RST - APB1 peripheral reset register - (CRM_APB1RST) - 0x20 - 0x20 - read-write - 0x00000000 - - - TMR2RST - Timer2 reset - 0 - 1 - - - TMR3RST - Timer3 reset - 1 - 1 - - - TMR4RST - Timer4 reset - 2 - 1 - - - TMR6RST - Timer6 reset - 4 - 1 - - - TMR7RST - Timer7 reset - 5 - 1 - - - TMR13RST - Timer13 reset - 7 - 1 - - - TMR14RST - Timer14 reset - 8 - 1 - - - WWDTRST - Window watchdog reset - 11 - 1 - - - SPI2RST - SPI2 reset - 14 - 1 - - - SPI3RST - SPI3 reset - 15 - 1 - - - USART2RST - USART2 reset - 17 - 1 - - - USART3RST - USART3 reset - 18 - 1 - - - USART4RST - USART4 reset - 19 - 1 - - - USART5RST - USART5 reset - 20 - 1 - - - I2C1RST - I2C1 reset - 21 - 1 - - - I2C2RST - I2C2 reset - 22 - 1 - - - I2C3RST - I2C3 reset - 23 - 1 - - - CAN1RST - CAN1 reset - 25 - 1 - - - PWCRST - PWC reset - 28 - 1 - - - UART7RST - UART7 reset - 30 - 1 - - - UART8RST - UART8 reset - 31 - 1 - - - - - APB2RST - APB2RST - APB2 peripheral reset register - (CRM_APB2RST) - 0x24 - 0x20 - read-write - 0x00000000 - - - TMR1RST - Timer1 reset - 0 - 1 - - - USART1RST - USART1 reset - 4 - 1 - - - USART6RST - USART6 reset - 5 - 1 - - - ADCRST - ADC reset - 8 - 1 - - - SPI1RST - SPI1 reset - 12 - 1 - - - SCFGRST - SCFG reset - 14 - 1 - - - TMR9RST - Timer9 reset - 16 - 1 - - - TMR10RST - Timer10 reset - 17 - 1 - - - TMR11RST - Timer 11 reset - 18 - 1 - - - I2S5RST - I2S5 reset - 20 - 1 - - - ACCRST - ACC reset - 29 - 1 - - - OTGHSPHYRST - OTGHS phy reset - 31 - 1 - - - - - AHBEN1 - AHBEN1 - AHB Peripheral Clock enable register 1 - (CRM_AHBEN1) - 0x30 - 0x20 - read-write - 0x00000000 - - - GPIOAEN - IO A clock enable - 0 - 1 - - - GPIOBEN - IO B clock enable - 1 - 1 - - - GPIOCEN - IO C clock enable - 2 - 1 - - - GPIODEN - IO D clock enable - 3 - 1 - - - GPIOFEN - IO F clock enable - 5 - 1 - - - CRCEN - CRC clock enable - 12 - 1 - - - DMA1EN - DMA1 clock enable - 22 - 1 - - - DMA2EN - DMA2 clock enable - 24 - 1 - - - OTGHSEN - OTGHS clock enable - 29 - 1 - - - - - AHBEN2 - AHBEN2 - AHB peripheral clock enable register 2 - (CRM_AHBEN2) - 0x34 - 0x20 - read-write - 0x00000000 - - - OTGFS1EN - OTGFS1 clock enable - 7 - 1 - - - - - AHBEN3 - AHBEN3 - AHB peripheral clock enable register 3 - (CRM_AHBEN3) - 0x38 - 0x20 - read-write - 0x00000000 - - - QSPI1EN - QSPI1 clock enable - 1 - 1 - - - - - APB1EN - APB1EN - APB1 peripheral clock enable register - (CRM_APB1EN) - 0x40 - 0x20 - read-write - 0x00000000 - - - TMR2EN - Timer2 clock enable - 0 - 1 - - - TMR3EN - Timer3 clock enable - 1 - 1 - - - TMR4EN - Timer4 clock enable - 2 - 1 - - - TMR6EN - Timer6 clock enable - 4 - 1 - - - TMR7EN - Timer7 clock enable - 5 - 1 - - - TMR13EN - Timer13 clock enable - 7 - 1 - - - TMR14EN - Timer14 clock enable - 8 - 1 - - - WWDTEN - WWDT clock enable - 11 - 1 - - - SPI2EN - SPI2 clock enable - 14 - 1 - - - SPI3EN - SPI3 clock enable - 15 - 1 - - - USART2EN - USART2 clock enable - 17 - 1 - - - USART3EN - USART3 clock enable - 18 - 1 - - - USART4EN - USART4 clock enable - 19 - 1 - - - USART5EN - USART5 clock enable - 20 - 1 - - - I2C1EN - I2C1 clock enable - 21 - 1 - - - I2C2EN - I2C2 clock enable - 22 - 1 - - - I2C3EN - I2C3 clock enable - 23 - 1 - - - CAN1EN - CAN1 clock enable - 25 - 1 - - - PWCEN - PWC clock enable - 28 - 1 - - - UART7EN - UART7 clock enable - 30 - 1 - - - UART8EN - UART8 clock enable - 31 - 1 - - - - - APB2EN - APB2EN - APB2 peripheral clock enable register - (CRM_APB2EN) - 0x44 - 0x20 - read-write - 0x00000000 - - - TMR1EN - Timer1 clock enable - 0 - 1 - - - USART1EN - USART1 clock enable - 4 - 1 - - - USART6EN - USART6 clock enable - 5 - 1 - - - ADC1EN - ADC1 clock enable - 8 - 1 - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - SCFGEN - SCFG clock enable - 14 - 1 - - - TMR9EN - Timer9 clock enable - 16 - 1 - - - TMR10EN - Timer10 clock enable - 17 - 1 - - - TMR11EN - Timer11 clock enable - 18 - 1 - - - I2S5EN - I2S5 clock enable - 20 - 1 - - - ACCEN - ACC clock enable - 29 - 1 - - - - - AHBLPEN1 - AHBLPEN1 - AHB Low-power Peripheral Clock enable - register 1 (CRM_AHBLPEN1) - 0x50 - 0x20 - read-write - 0x3E6390FF - - - GPIOALPEN - IO A clock enable during sleep mode - 0 - 1 - - - GPIOBLPEN - IO B clock enable during sleep mode - 1 - 1 - - - GPIOCLPEN - IO C clock enable during sleep mode - 2 - 1 - - - GPIODLPEN - IO D clock enable during sleep mode - 3 - 1 - - - GPIOFLPEN - IO F clock enable during sleep mode - 5 - 1 - - - CRCLPEN - CRC clock enable during sleep mode - 12 - 1 - - - FLASHLPEN - Flash clock enable during sleep mode - 15 - 1 - - - SRAMLPEN - SRAM clock enable during sleep mode - 16 - 1 - - - DMA1LPEN - DMA1 clock enable during sleep mode - 22 - 1 - - - DMA2LPEN - DMA2 clock enable during sleep mode - 24 - 1 - - - OTGHSLPEN - OTGHS clock enable during sleep mode - 29 - 1 - - - - - AHBLPEN2 - AHBLPEN2 - AHB peripheral Low-power clock - enable register 2 (CRM_AHBLPEN2) - 0x54 - 0x20 - read-write - 0x00008081 - - - OTGFS1LPEN - OTGFS1 clock enable during sleep mode - 7 - 1 - - - - - AHBLPEN3 - AHBLPEN3 - AHB peripheral Low-power clock - enable register 3 (CRM_AHBLPEN3) - 0x58 - 0x20 - read-write - 0x0000C003 - - - QSPI1LPEN - QSPI1 clock enable during sleep mode - 1 - 1 - - - - - APB1LPEN - APB1LPEN - APB1 peripheral Low-power clock - enable register (CRM_APB1LPEN) - 0x60 - 0x20 - read-write - 0xF6FEE9FF - - - TMR2LPEN - Timer2 clock enable during sleep mode - 0 - 1 - - - TMR3LPEN - Timer3 clock enable during sleep mode - 1 - 1 - - - TMR4LPEN - Timer4 clock enable during sleep mode - 2 - 1 - - - TMR6LPEN - Timer6 clock enable during sleep mode - 4 - 1 - - - TMR7LPEN - Timer7 clock enable during sleep mode - 5 - 1 - - - TMR13LPEN - Timer13 clock enable during sleep mode - 7 - 1 - - - TMR14LPEN - Timer14 clock enable during sleep mode - 8 - 1 - - - WWDTLPEN - WWDT clock enable during sleep mode - 11 - 1 - - - SPI2LPEN - SPI2 clock enable during sleep mode - 14 - 1 - - - SPI3LPEN - SPI3 clock enable during sleep mode - 15 - 1 - - - USART2LPEN - USART2 clock enable during sleep mode - 17 - 1 - - - USART3LPEN - USART3 clock enable during sleep mode - 18 - 1 - - - USART4LPEN - USART4 clock enable during sleep mode - 19 - 1 - - - USART5LPEN - USART5 clock enable during sleep mode - 20 - 1 - - - I2C1CPEN - I2C1 clock enable during sleep mode - 21 - 1 - - - I2C2CPEN - I2C2 clock enable during sleep mode - 22 - 1 - - - I2C3CPEN - I2C3 clock enable during sleep mode - 23 - 1 - - - CAN1LPEN - CAN1 clock enable during sleep mode - 25 - 1 - - - PWCLPEN - PWC clock enable during sleep mode - 28 - 1 - - - UART7LPEN - UART7 clock enable during sleep mode - 30 - 1 - - - UART8LPEN - UART8 clock enable during sleep mode - 31 - 1 - - - - - APB2LPEN - APB2LPEN - APB2 peripheral Low-power clock - enable register (CRM_APB2LPEN) - 0x64 - 0x20 - read-write - 0x20177733 - - - TMR1LPEN - Timer1 clock enable during sleep mode - 0 - 1 - - - USART1LPEN - USART1 clock enable during sleep mode - 4 - 1 - - - USART6LPEN - USART6 clock enable during sleep mode - 5 - 1 - - - SPI1LPEN - SPI1 clock enable during sleep mode - 12 - 1 - - - SCFGLPEN - SCFG clock enable during sleep mode - 14 - 1 - - - TMR9LPEN - Timer9 clock enable during sleep mode - 16 - 1 - - - TMR10LPEN - Timer10 clock enable during sleep mode - 17 - 1 - - - TMR11LPEN - Timer11 clock enable during sleep mode - 18 - 1 - - - I2S5LPEN - I2S5 clock enable during sleep mode - 20 - 1 - - - ACCLPEN - ACC clock enable during sleep mode - 29 - 1 - - - OTGHSPHYLPEN - OTGHS phy clock enable during sleep mode - 31 - 1 - - - - - BPDC - BPDC - Battery powered domain control register - (CRM_BPDC) - 0x70 - 0x20 - 0x00000000 - - - LEXTEN - Low speed external crystal enable - 0 - 1 - read-write - - - LEXTSTBL - Low speed external crystal ready - 1 - 1 - read-only - - - LEXTBYPS - Low speed external crystal bypass - 2 - 1 - read-write - - - ERTCSEL - ERTC clock source selection - 8 - 2 - read-write - - - ERTCEN - ERTC clock enable - 15 - 1 - read-write - - - BPDRST - Battery powered domain software reset - 16 - 1 - read-write - - - - - CTRLSTS - CTRLSTS - Control/status register - (CRM_CTRLSTS) - 0x74 - 0x20 - 0x0C000000 - - - LICKEN - Low speed internal clock enable - 0 - 1 - read-write - - - LICKSTBL - Low speed internal clock ready - 1 - 1 - read-only - - - RSTFC - Reset reset flag - 24 - 1 - read-write - - - NRSTF - PIN reset flag - 26 - 1 - read-write - - - PORRSTF - POR/LVR reset flag - 27 - 1 - read-write - - - SWRSTF - Software reset flag - 28 - 1 - read-write - - - WDTRSTF - Watchdog timer reset flag - 29 - 1 - read-write - - - WWDTRSTF - Window watchdog timer reset flag - 30 - 1 - read-write - - - LPRSTF - Low-power reset flag - 31 - 1 - read-write - - - - - OTGHS - OTGHS - OTGHS register - 0x78 - 0x20 - 0x00000000 - - - XTLSEL - PHY clock source select - 0 - 1 - read-write - - - USBHS_PHY12_SEL - USBHS phy12 select value - 3 - 2 - read-write - - - USBHS_PHY30_SEL - USBHS phy12 select value - 8 - 2 - read-write - - - - - MISC1 - MISC1 - Miscellaneous register1 - 0xA0 - 0x20 - 0x00000000 - - - HICKCAL_KEY - HICKCAL write key value - 0 - 8 - read-write - - - HICKDIV - HICK 6 divider selection - 12 - 1 - read-write - - - HICK_TO_SCLK - HICK to system clock - 14 - 1 - read-write - - - CLKOUT_SEL2 - Clock output select2 - 16 - 4 - read-write - - - CLKOUTDIV2 - Clock output division2 - 28 - 4 - read-write - - - - - MISC2 - MISC2 - Miscellaneous register2 - 0xA4 - 0x20 - 0x0000000D - - - AUTO_STEP_EN - AUTO_STEP_EN - 4 - 2 - read-write - - - PLLU_USB48_SEL - USB clock source select - 10 - 1 - read-write - - - HICK_TO_SCLK_DIV - HICK as system clock frequency division - 16 - 3 - read-write - - - HEXT_TO_SCLK_DIV - HEXT as system clock frequency division - 19 - 3 - read-write - - - - - - - GPIOA - General purpose I/Os - GPIO - 0x40020000 - - 0x0 - 0x400 - registers - - - - CFGR - CFGR - GPIO configuration register - 0x0 - 0x20 - read-write - 0x00000000 - - - IOMC15 - GPIOx pin 15 mode configurate - 30 - 2 - - - IOMC14 - GPIOx pin 14 mode configurate - 28 - 2 - - - IOMC13 - GPIOx pin 13 mode configurate - 26 - 2 - - - IOMC12 - GPIOx pin 12 mode configurate - 24 - 2 - - - IOMC11 - GPIOx pin 11 mode configurate - 22 - 2 - - - IOMC10 - GPIOx pin 10 mode configurate - 20 - 2 - - - IOMC9 - GPIOx pin 9 mode configurate - 18 - 2 - - - IOMC8 - GPIOx pin 8 mode configurate - 16 - 2 - - - IOMC7 - GPIOx pin 7 mode configurate - 14 - 2 - - - IOMC6 - GPIOx pin 6 mode configurate - 12 - 2 - - - IOMC5 - GPIOx pin 5 mode configurate - 10 - 2 - - - IOMC4 - GPIOx pin 4 mode configurate - 8 - 2 - - - IOMC3 - GPIOx pin 3 mode configurate - 6 - 2 - - - IOMC2 - GPIOx pin 2 mode configurate - 4 - 2 - - - IOMC1 - GPIOx pin 1 mode configurate - 2 - 2 - - - IOMC0 - GPIOx pin 0 mode configurate - 0 - 2 - - - - - OMODE - OMODE - GPIO output mode register - 0x4 - 0x20 - read-write - 0x00000000 - - - OM15 - GPIOx pin 15 outpu mode configurate - 15 - 1 - - - OM14 - GPIOx pin 14 outpu mode configurate - 14 - 1 - - - OM13 - GPIOx pin 13 outpu mode configurate - 13 - 1 - - - OM12 - GPIOx pin 12 outpu mode configurate - 12 - 1 - - - OM11 - GPIOx pin 11 outpu mode configurate - 11 - 1 - - - OM10 - GPIOx pin 10 outpu mode configurate - 10 - 1 - - - OM9 - GPIOx pin 9 outpu mode configurate - 9 - 1 - - - OM8 - GPIOx pin 8 outpu mode configurate - 8 - 1 - - - OM7 - GPIOx pin 7 outpu mode configurate - 7 - 1 - - - OM6 - GPIOx pin 6 outpu mode configurate - 6 - 1 - - - OM5 - GPIOx pin 5 outpu mode configurate - 5 - 1 - - - OM4 - GPIOx pin 4 outpu mode configurate - 4 - 1 - - - OM3 - GPIOx pin 3 outpu mode configurate - 3 - 1 - - - OM2 - GPIOx pin 2 outpu mode configurate - 2 - 1 - - - OM1 - GPIOx pin 1 outpu mode configurate - 1 - 1 - - - OM0 - GPIOx pin 0 outpu mode configurate - 0 - 1 - - - - - ODRVR - ODRVR - GPIO drive capability register - 0x8 - 0x20 - read-write - 0x00000000 - - - ODRV15 - GPIOx pin 15 output drive capability - 30 - 2 - - - ODRV14 - GPIOx pin 14 output drive capability - 28 - 2 - - - ODRV13 - GPIOx pin 13 output drive capability - 26 - 2 - - - ODRV12 - GPIOx pin 12 output drive capability - 24 - 2 - - - ODRV11 - GPIOx pin 11 output drive capability - 22 - 2 - - - ODRV10 - GPIOx pin 10 output drive capability - 20 - 2 - - - ODRV9 - GPIOx pin 9 output drive capability - 18 - 2 - - - ODRV8 - GPIOx pin 8 output drive capability - 16 - 2 - - - ODRV7 - GPIOx pin 7 output drive capability - 14 - 2 - - - ODRV6 - GPIOx pin 6 output drive capability - 12 - 2 - - - ODRV5 - GPIOx pin 5 output drive capability - 10 - 2 - - - ODRV4 - GPIOx pin 4 output drive capability - 8 - 2 - - - ODRV3 - GPIOx pin 3 output drive capability - 6 - 2 - - - ODRV2 - GPIOx pin 2 output drive capability - 4 - 2 - - - ODRV1 - GPIOx pin 1 output drive capability - 2 - 2 - - - ODRV0 - GPIOx pin 0 output drive capability - 0 - 2 - - - - - PULL - PULL - GPIO pull-up/pull-down register - 0xC - 0x20 - read-write - 0x00000000 - - - PULL15 - GPIOx pin 15 pull configuration - 30 - 2 - - - PULL14 - GPIOx pin 14 pull configuration - 28 - 2 - - - PULL13 - GPIOx pin 13 pull configuration - 26 - 2 - - - PULL12 - GPIOx pin 12 pull configuration - 24 - 2 - - - PULL11 - GPIOx pin 11 pull configuration - 22 - 2 - - - PULL10 - GPIOx pin 10 pull configuration - 20 - 2 - - - PULL9 - GPIOx pin 9 pull configuration - 18 - 2 - - - PULL8 - GPIOx pin 8 pull configuration - 16 - 2 - - - PULL7 - GPIOx pin 7 pull configuration - 14 - 2 - - - PULL6 - GPIOx pin 6 pull configuration - 12 - 2 - - - PULL5 - GPIOx pin 5 pull configuration - 10 - 2 - - - PULL4 - GPIOx pin 4 pull configuration - 8 - 2 - - - PULL3 - GPIOx pin 3 pull configuration - 6 - 2 - - - PULL2 - GPIOx pin 2 pull configuration - 4 - 2 - - - PULL1 - GPIOx pin 1 pull configuration - 2 - 2 - - - PULL0 - GPIOx pin 0 pull configuration - 0 - 2 - - - - - IDT - IDT - GPIO input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - IDT0 - Port input data - 0 - 1 - - - IDT1 - Port input data - 1 - 1 - - - IDT2 - Port input data - 2 - 1 - - - IDT3 - Port input data - 3 - 1 - - - IDT4 - Port input data - 4 - 1 - - - IDT5 - Port input data - 5 - 1 - - - IDT6 - Port input data - 6 - 1 - - - IDT7 - Port input data - 7 - 1 - - - IDT8 - Port input data - 8 - 1 - - - IDT9 - Port input data - 9 - 1 - - - IDT10 - Port input data - 10 - 1 - - - IDT11 - Port input data - 11 - 1 - - - IDT12 - Port input data - 12 - 1 - - - IDT13 - Port input data - 13 - 1 - - - IDT14 - Port input data - 14 - 1 - - - IDT15 - Port input data - 15 - 1 - - - - - ODT - ODT - GPIO output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - ODT0 - Port output data - 0 - 1 - - - ODT1 - Port output data - 1 - 1 - - - ODT2 - Port output data - 2 - 1 - - - ODT3 - Port output data - 3 - 1 - - - ODT4 - Port output data - 4 - 1 - - - ODT5 - Port output data - 5 - 1 - - - ODT6 - Port output data - 6 - 1 - - - ODT7 - Port output data - 7 - 1 - - - ODT8 - Port output data - 8 - 1 - - - ODT9 - Port output data - 9 - 1 - - - ODT10 - Port output data - 10 - 1 - - - ODT11 - Port output data - 11 - 1 - - - ODT12 - Port output data - 12 - 1 - - - ODT13 - Port output data - 13 - 1 - - - ODT14 - Port output data - 14 - 1 - - - ODT15 - Port output data - 15 - 1 - - - - - SCR - SCR - Port bit set/clear register - 0x18 - 0x20 - write-only - 0x00000000 - - - IOSB0 - Set bit 0 - 0 - 1 - - - IOSB1 - Set bit 1 - 1 - 1 - - - IOSB2 - Set bit 1 - 2 - 1 - - - IOSB3 - Set bit 3 - 3 - 1 - - - IOSB4 - Set bit 4 - 4 - 1 - - - IOSB5 - Set bit 5 - 5 - 1 - - - IOSB6 - Set bit 6 - 6 - 1 - - - IOSB7 - Set bit 7 - 7 - 1 - - - IOSB8 - Set bit 8 - 8 - 1 - - - IOSB9 - Set bit 9 - 9 - 1 - - - IOSB10 - Set bit 10 - 10 - 1 - - - IOSB11 - Set bit 11 - 11 - 1 - - - IOSB12 - Set bit 12 - 12 - 1 - - - IOSB13 - Set bit 13 - 13 - 1 - - - IOSB14 - Set bit 14 - 14 - 1 - - - IOSB15 - Set bit 15 - 15 - 1 - - - IOCB0 - Clear bit 0 - 16 - 1 - - - IOCB1 - Clear bit 1 - 17 - 1 - - - IOCB2 - Clear bit 2 - 18 - 1 - - - IOCB3 - Clear bit 3 - 19 - 1 - - - IOCB4 - Clear bit 4 - 20 - 1 - - - IOCB5 - Clear bit 5 - 21 - 1 - - - IOCB6 - Clear bit 6 - 22 - 1 - - - IOCB7 - Clear bit 7 - 23 - 1 - - - IOCB8 - Clear bit 8 - 24 - 1 - - - IOCB9 - Clear bit 9 - 25 - 1 - - - IOCB10 - Clear bit 10 - 26 - 1 - - - IOCB11 - Clear bit 11 - 27 - 1 - - - IOCB12 - Clear bit 12 - 28 - 1 - - - IOCB13 - Clear bit 13 - 29 - 1 - - - IOCB14 - Clear bit 14 - 30 - 1 - - - IOCB15 - Clear bit 15 - 31 - 1 - - - - - WPR - WPR - Port write protect - register - 0x1C - 0x20 - read-write - 0x00000000 - - - WPEN0 - Write protect enable 0 - 0 - 1 - - - WPEN1 - Write protect enable 1 - 1 - 1 - - - WPEN2 - Write protect enable 2 - 2 - 1 - - - WPEN3 - Write protect enable 3 - 3 - 1 - - - WPEN4 - Write protect enable 4 - 4 - 1 - - - WPEN5 - Write protect enable 5 - 5 - 1 - - - WPEN6 - Write protect enable 6 - 6 - 1 - - - WPEN7 - Write protect enable 7 - 7 - 1 - - - WPEN8 - Write protect enable 8 - 8 - 1 - - - WPEN9 - Write protect enable 9 - 9 - 1 - - - WPEN10 - Write protect enable 10 - 10 - 1 - - - WPEN11 - Write protect enable 11 - 11 - 1 - - - WPEN12 - Write protect enable 12 - 12 - 1 - - - WPEN13 - Write protect enable 13 - 13 - 1 - - - WPEN14 - Write protect enable 14 - 14 - 1 - - - WPEN15 - Write protect enable 15 - 15 - 1 - - - WPSEQ - Write protect sequence - 16 - 1 - - - - - MUXL - MUXL - GPIO muxing function low register - 0x20 - 0x20 - read-write - 0x00000000 - - - MUXL7 - GPIOx pin 7 muxing - 28 - 4 - - - MUXL6 - GPIOx pin 6 muxing - 24 - 4 - - - MUXL5 - GPIOx pin 5 muxing - 20 - 4 - - - MUXL4 - GPIOx pin 4 muxing - 16 - 4 - - - MUXL3 - GPIOx pin 3 muxing - 12 - 4 - - - MUXL2 - GPIOx pin 2 muxing - 8 - 4 - - - MUXL1 - GPIOx pin 1 muxing - 4 - 4 - - - MUXL0 - GPIOx pin 0 muxing - 0 - 4 - - - - - MUXH - MUXH - GPIO muxing function high register - 0x24 - 0x20 - read-write - 0x00000000 - - - MUXH15 - GPIOx pin 15 muxing - 28 - 4 - - - MUXH14 - GPIOx pin 14 muxing - 24 - 4 - - - MUXH13 - GPIOx pin 13 muxing - 20 - 4 - - - MUXH12 - GPIOx pin 12 muxing - 16 - 4 - - - MUXH11 - GPIOx pin 11 muxing - 12 - 4 - - - MUXH10 - GPIOx pin 10 muxing - 8 - 4 - - - MUXH9 - GPIOx pin 9 muxing - 4 - 4 - - - MUXH8 - GPIOx pin 8 muxing - 0 - 4 - - - - - CLR - CLR - GPIO bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - IOCB0 - Clear bit 0 - 0 - 1 - - - IOCB1 - Clear bit 1 - 1 - 1 - - - IOCB2 - Clear bit 1 - 2 - 1 - - - IOCB3 - Clear bit 3 - 3 - 1 - - - IOCB4 - Clear bit 4 - 4 - 1 - - - IOCB5 - Clear bit 5 - 5 - 1 - - - IOCB6 - Clear bit 6 - 6 - 1 - - - IOCB7 - Clear bit 7 - 7 - 1 - - - IOCB8 - Clear bit 8 - 8 - 1 - - - IOCB9 - Clear bit 9 - 9 - 1 - - - IOCB10 - Clear bit 10 - 10 - 1 - - - IOCB11 - Clear bit 11 - 11 - 1 - - - IOCB12 - Clear bit 12 - 12 - 1 - - - IOCB13 - Clear bit 13 - 13 - 1 - - - IOCB14 - Clear bit 14 - 14 - 1 - - - IOCB15 - Clear bit 15 - 15 - 1 - - - - - TOGR - TOGR - GPIO bit toggle register - 0x2C - 0x20 - write-only - 0x00000000 - - - IOTB0 - toggle bit 0 - 0 - 1 - - - IOTB1 - toggle bit 1 - 1 - 1 - - - IOTB2 - toggle bit 2 - 2 - 1 - - - IOTB3 - toggle bit 3 - 3 - 1 - - - IOTB4 - toggle bit 4 - 4 - 1 - - - IOTB5 - toggle bit 5 - 5 - 1 - - - IOTB6 - toggle bit 6 - 6 - 1 - - - IOTB7 - toggle bit 7 - 7 - 1 - - - IOTB8 - toggle bit 8 - 8 - 1 - - - IOTB9 - toggle bit 9 - 9 - 1 - - - IOTB10 - toggle bit 10 - 10 - 1 - - - IOTB11 - toggle bit 11 - 11 - 1 - - - IOTB12 - toggle bit 12 - 12 - 1 - - - IOTB13 - toggle bit 13 - 13 - 1 - - - IOTB14 - toggle bit 14 - 14 - 1 - - - IOTB15 - toggle bit 15 - 15 - 1 - - - - - HDRV - HDRV - Huge current driver - 0x3C - 0x20 - read-write - 0x00000000 - - - HDRV0 - Port x driver bit y - 0 - 1 - - - HDRV1 - Port x driver bit y - 1 - 1 - - - HDRV2 - Port x driver bit y - 2 - 1 - - - HDRV3 - Port x driver bit y - 3 - 1 - - - HDRV4 - Port x driver bit y - 4 - 1 - - - HDRV5 - Port x driver bit y - 5 - 1 - - - HDRV6 - Port x driver bit y - 6 - 1 - - - HDRV7 - Port x driver bit y - 7 - 1 - - - HDRV8 - Port x driver bit y - 8 - 1 - - - HDRV9 - Port x driver bit y - 9 - 1 - - - HDRV10 - Port x driver bit y - 10 - 1 - - - HDRV11 - Port x driver bit y - 11 - 1 - - - HDRV12 - Port x driver bit y - 12 - 1 - - - HDRV13 - Port x driver bit y - 13 - 1 - - - HDRV14 - Port x driver bit y - 14 - 1 - - - HDRV15 - Port x driver bit y - 15 - 1 - - - - - - - GPIOB - 0x40020400 - - - GPIOC - 0x40020800 - - - GPIOD - 0x40020C00 - - - GPIOF - 0x40021400 - - - EXINT - EXINT - EXINT - 0x40013C00 - - 0x0 - 0x400 - registers - - - EXINT0 - EXINT Line0 interrupt - 6 - - - EXINT1 - EXINT Line1 interrupt - 7 - - - EXINT2 - EXINT Line2 interrupt - 8 - - - EXINT3 - EXINT Line3 interrupt - 9 - - - EXINT4 - EXINT Line4 interrupt - 10 - - - EXINT9_5 - EXINT Line[9:5] interrupts - 23 - - - EXINT15_10 - EXINT Line[15:10] interrupts - 40 - - - PVM - PVM interrupt connect to EXINT line16 - 1 - - - ERTCALARM - ERTC Alarm interrupt connect to EXINT line17 - 41 - - - OTGFS1_WKUP - OTGFS1_WKUP interrupt connect to EXINT line18 - 42 - - - OTGHS_WKUP - OTGHS_WKUP interrupt connect to EXINT line20 - 76 - - - TAMPER - Tamper interrupt connect to EXINT line21 - 2 - - - ERTC_WKUP - ERTC Global interrupt connect to EXINT line22 - 3 - - - - INTEN - INTEN - Interrupt enable register - 0x0 - 0x20 - read-write - 0x00000000 - - - INTEN0 - Interrupt enable or disable on line 0 - 0 - 1 - - - INTEN1 - Interrupt enable or disable on line 1 - 1 - 1 - - - INTEN2 - Interrupt enable or disable on line 2 - 2 - 1 - - - INTEN3 - Interrupt enable or disable on line 3 - 3 - 1 - - - INTEN4 - Interrupt enable or disable on line 4 - 4 - 1 - - - INTEN5 - Interrupt enable or disable on line 5 - 5 - 1 - - - INTEN6 - Interrupt enable or disable on line 6 - 6 - 1 - - - INTEN7 - Interrupt enable or disable on line 7 - 7 - 1 - - - INTEN8 - Interrupt enable or disable on line 8 - 8 - 1 - - - INTEN9 - Interrupt enable or disable on line 9 - 9 - 1 - - - INTEN10 - Interrupt enable or disable on line 10 - 10 - 1 - - - INTEN11 - Interrupt enable or disable on line 11 - 11 - 1 - - - INTEN12 - Interrupt enable or disable on line 12 - 12 - 1 - - - INTEN13 - Interrupt enable or disable on line 13 - 13 - 1 - - - INTEN14 - Interrupt enable or disable on line 14 - 14 - 1 - - - INTEN15 - Interrupt enable or disable on line 15 - 15 - 1 - - - INTEN16 - Interrupt enable or disable on line 16 - 16 - 1 - - - INTEN17 - Interrupt enable or disable on line 17 - 17 - 1 - - - INTEN18 - Interrupt enable or disable on line 18 - 18 - 1 - - - INTEN19 - Interrupt enable or disable on line 19 - 19 - 1 - - - INTEN20 - Interrupt enable or disable on line 20 - 20 - 1 - - - INTEN21 - Interrupt enable or disable on line 21 - 21 - 1 - - - INTEN22 - Interrupt enable or disable on line 22 - 22 - 1 - - - - - EVTEN - EVTEN - Event enable register - 0x4 - 0x20 - read-write - 0x00000000 - - - EVTEN0 - Event enable or disable on line 0 - 0 - 1 - - - EVTEN1 - Event enable or disable on line 1 - 1 - 1 - - - EVTEN2 - Event enable or disable on line 2 - 2 - 1 - - - EVTEN3 - Event enable or disable on line 3 - 3 - 1 - - - EVTEN4 - Event enable or disable on line 4 - 4 - 1 - - - EVTEN5 - Event enable or disable on line 5 - 5 - 1 - - - EVTEN6 - Event enable or disable on line 6 - 6 - 1 - - - EVTEN7 - Event enable or disable on line 7 - 7 - 1 - - - EVTEN8 - Event enable or disable on line 8 - 8 - 1 - - - EVTEN9 - Event enable or disable on line 9 - 9 - 1 - - - EVTEN10 - Event enable or disable on line 10 - 10 - 1 - - - EVTEN11 - Event enable or disable on line 11 - 11 - 1 - - - EVTEN12 - Event enable or disable on line 12 - 12 - 1 - - - EVTEN13 - Event enable or disable on line 13 - 13 - 1 - - - EVTEN14 - Event enable or disable on line 14 - 14 - 1 - - - EVTEN15 - Event enable or disable on line 15 - 15 - 1 - - - EVTEN16 - Event enable or disable on line 16 - 16 - 1 - - - EVTEN17 - Event enable or disable on line 17 - 17 - 1 - - - EVTEN18 - Event enable or disable on line 18 - 18 - 1 - - - EVTEN19 - Event enable or disable on line 19 - 19 - 1 - - - EVTEN20 - Event enable or disable on line 20 - 20 - 1 - - - EVTEN21 - Event enable or disable on line 21 - 21 - 1 - - - EVTEN22 - Event enable or disable on line 22 - 22 - 1 - - - - - POLCFG1 - POLCFG1 - Rising polarity configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - RP0 - Rising polarity configuration bit of line 0 - 0 - 1 - - - RP1 - Rising polarity configuration bit of line 1 - 1 - 1 - - - RP2 - Rising polarity configuration bit of line 2 - 2 - 1 - - - RP3 - Rising polarity configuration bit of line 3 - 3 - 1 - - - RP4 - Rising polarity configuration bit of line 4 - 4 - 1 - - - RP5 - Rising polarity configuration bit of line 5 - 5 - 1 - - - RP6 - Rising polarity configuration bit of linee 6 - 6 - 1 - - - RP7 - Rising polarity configuration bit of line 7 - 7 - 1 - - - RP8 - Rising polarity configuration bit of line 8 - 8 - 1 - - - RP9 - Rising polarity configuration bit of line 9 - 9 - 1 - - - RP10 - Rising polarity configuration bit of line 10 - 10 - 1 - - - RP11 - Rising polarity configuration bit of line 11 - 11 - 1 - - - RP12 - Rising polarity configuration bit of line 12 - 12 - 1 - - - RP13 - Rising polarity configuration bit of line 13 - 13 - 1 - - - RP14 - Rising polarity configuration bit of line 14 - 14 - 1 - - - RP15 - Rising polarity configuration bit of line 15 - 15 - 1 - - - RP16 - Rising polarity configuration bit of line 16 - 16 - 1 - - - RP17 - Rising polarity configuration bit of line 17 - 17 - 1 - - - RP18 - Rising polarity configuration bit of line 18 - 18 - 1 - - - RP19 - Rising polarity configuration bit of line 19 - 19 - 1 - - - RP20 - Rising polarity configuration bit of line 20 - 20 - 1 - - - RP21 - Rising polarity configuration bit of line 21 - 21 - 1 - - - RP22 - Rising polarity configuration bit of line 22 - 22 - 1 - - - - - POLCFG2 - POLCFG2 - Falling polarity configuration register - 0xC - 0x20 - read-write - 0x00000000 - - - FP0 - Falling polarity event configuration bit of line 0 - 0 - 1 - - - FP1 - Falling polarity event configuration bit of line 1 - 1 - 1 - - - FP2 - Falling polarity event configuration bit of line 2 - 2 - 1 - - - FP3 - Falling polarity event configuration bit of line 3 - 3 - 1 - - - FP4 - Falling polarity event configuration bit of line 4 - 4 - 1 - - - FP5 - Falling polarity event configuration bit of line 5 - 5 - 1 - - - FP6 - Falling polarity event configuration bit of line 6 - 6 - 1 - - - FP7 - Falling polarity event configuration bit of line 7 - 7 - 1 - - - FP8 - Falling polarity event configuration bit of line 8 - 8 - 1 - - - FP9 - Falling polarity event configuration bit of line 9 - 9 - 1 - - - FP10 - Falling polarity event configuration bit of line 10 - 10 - 1 - - - FP11 - Falling polarity event configuration bit of line 11 - 11 - 1 - - - FP12 - Falling polarity event configuration bit of line 12 - 12 - 1 - - - FP13 - Falling polarity event configuration bit of line 13 - 13 - 1 - - - FP14 - Falling polarity event configuration bit of line 14 - 14 - 1 - - - FP15 - Falling polarity event configuration bit of line 15 - 15 - 1 - - - FP16 - Falling polarity event configuration bit of line 16 - 16 - 1 - - - FP17 - Falling polarity event configuration bit of line 17 - 17 - 1 - - - FP18 - Falling polarity event configuration bit of line 18 - 18 - 1 - - - FP19 - Falling polarity event configuration bit of line 19 - 19 - 1 - - - FP20 - Falling polarity event configuration bit of line 20 - 20 - 1 - - - FP21 - Falling polarity event configuration bit of line 21 - 21 - 1 - - - FP22 - Falling polarity event configuration bit of line 22 - 22 - 1 - - - - - SWTRG - SWTRG - Software triggle register - 0x10 - 0x20 - read-write - 0x00000000 - - - SWT0 - Software triggle on line 0 - 0 - 1 - - - SWT1 - Software triggle on line 1 - 1 - 1 - - - SWT2 - Software triggle on line 2 - 2 - 1 - - - SWT3 - Software triggle on line 3 - 3 - 1 - - - SWT4 - Software triggle on line 4 - 4 - 1 - - - SWT5 - Software triggle on line 5 - 5 - 1 - - - SWT6 - Software triggle on line 6 - 6 - 1 - - - SWT7 - Software triggle on line 7 - 7 - 1 - - - SWT8 - Software triggle on line 8 - 8 - 1 - - - SWT9 - Software triggle on line 9 - 9 - 1 - - - SWT10 - Software triggle on line 10 - 10 - 1 - - - SWT11 - Software triggle on line 11 - 11 - 1 - - - SWT12 - Software triggle on line 12 - 12 - 1 - - - SWT13 - Software triggle on line 13 - 13 - 1 - - - SWT14 - Software triggle on line 14 - 14 - 1 - - - SWT15 - Software triggle on line 15 - 15 - 1 - - - SWT16 - Software triggle on line 16 - 16 - 1 - - - SWT17 - Software triggle on line 17 - 17 - 1 - - - SWT18 - Software triggle on line 18 - 18 - 1 - - - SWT19 - Software triggle on line 19 - 19 - 1 - - - SWT20 - Software triggle on line 20 - 20 - 1 - - - SWT21 - Software triggle on line 21 - 21 - 1 - - - SWT22 - Software triggle on line 22 - 22 - 1 - - - - - INTSTS - INTSTS - Interrupt status register - 0x14 - 0x20 - read-write - 0x00000000 - - - LINE0 - Line 0 state bit - 0 - 1 - - - LINE1 - Line 1 state bit - 1 - 1 - - - LINE2 - Line 2 state bit - 2 - 1 - - - LINE3 - Line 3 state bit - 3 - 1 - - - LINE4 - Line 4 state bit - 4 - 1 - - - LINE5 - Line 5 state bit - 5 - 1 - - - LINE6 - Line 6 state bit - 6 - 1 - - - LINE7 - Line 7 state bit - 7 - 1 - - - LINE8 - Line 8 state bit - 8 - 1 - - - LINE9 - Line 9 state bit - 9 - 1 - - - LINE10 - Line 10 state bit - 10 - 1 - - - LINE11 - Line 11 state bit - 11 - 1 - - - LINE12 - Line 12 state bit - 12 - 1 - - - LINE13 - Line 13 state bit - 13 - 1 - - - LINE14 - Line 14 state bit - 14 - 1 - - - LINE15 - Line 15 state bit - 15 - 1 - - - LINE16 - Line 16 state bit - 16 - 1 - - - LINE17 - Line 17 state bit - 17 - 1 - - - LINE18 - Line 18 state bit - 18 - 1 - - - LINE19 - Line 19 state bit - 19 - 1 - - - LINE20 - Line 20 state bit - 20 - 1 - - - LINE21 - Line 21 state bit - 21 - 1 - - - LINE22 - Line 22 state bit - 22 - 1 - - - - - - - DMA1 - DMA controller - DMA - 0x40026000 - - 0x0 - 0x200 - registers - - - DMA1_Channel1 - DMA1 Channel1 global interrupt - 11 - - - DMA1_Channel2 - DMA1 Channel2 global interrupt - 12 - - - DMA1_Channel3 - DMA1 Channel3 global interrupt - 13 - - - DMA1_Channel4 - DMA1 Channel4 global interrupt - 14 - - - DMA1_Channel5 - DMA1 Channel5 global interrupt - 15 - - - DMA1_Channel6 - DMA1 Channel6 global interrupt - 16 - - - DMA1_Channel7 - DMA1 Channel7 global interrupt - 17 - - - - STS - STS - DMA interrupt status register - (DMA_STS) - 0x0 - 0x20 - read-only - 0x00000000 - - - GF1 - Channel 1 Global event flag - 0 - 1 - - - FDTF1 - Channel 1 full data transfer event flag - 1 - 1 - - - HDTF1 - Channel 1 half data transfer event flag - 2 - 1 - - - DTERRF1 - Channel 1 data transfer error event flag - 3 - 1 - - - GF2 - Channel 2 Global event flag - 4 - 1 - - - FDTF2 - Channel 2 full data transfer event flag - 5 - 1 - - - HDTF2 - Channel 2 half data transfer event flag - 6 - 1 - - - DTERRF2 - Channel 2 data transfer error event flag - 7 - 1 - - - GF3 - Channel 3 Global event flag - 8 - 1 - - - FDTF3 - Channel 3 full data transfer event flag - 9 - 1 - - - HDTF3 - Channel 3 half data transfer event flag - 10 - 1 - - - DTERRF3 - Channel 3 data transfer error event flag - 11 - 1 - - - GF4 - Channel 4 Global event flag - 12 - 1 - - - FDTF4 - Channel 4 full data transfer event flag - 13 - 1 - - - HDTF4 - Channel 4 half data transfer event flag - 14 - 1 - - - DTERRF4 - Channel 4 data transfer error event flag - 15 - 1 - - - GF5 - Channel 5 Global event flag - 16 - 1 - - - FDTF5 - Channel 5 full data transfer event flag - 17 - 1 - - - HDTF5 - Channel 5 half data transfer event flag - 18 - 1 - - - DTERRF5 - Channel 5 data transfer error event flag - 19 - 1 - - - GF6 - Channel 6 Global event flag - 20 - 1 - - - FDTF6 - Channel 6 full data transfer event flag - 21 - 1 - - - HDTF6 - Channel 6 half data transfer event flag - 22 - 1 - - - DTERRF6 - Channel 6 data transfer error event flag - 23 - 1 - - - GF7 - Channel 7 Global event flag - 24 - 1 - - - FDTF7 - Channel 7 full data transfer event flag - 25 - 1 - - - HDTF7 - Channel 7 half data transfer event flag - 26 - 1 - - - DTERRF7 - Channel 7 data transfer error event flag - 27 - 1 - - - - - CLR - CLR - DMA interrupt flag clear register - (DMA_CLR) - 0x4 - 0x20 - read-write - 0x00000000 - - - GFC1 - Channel 1 Global flag clear - 0 - 1 - - - GFC2 - Channel 2 Global flag clear - 4 - 1 - - - GFC3 - Channel 3 Global flag clear - 8 - 1 - - - GFC4 - Channel 4 Global flag clear - 12 - 1 - - - GFC5 - Channel 5 Global flag clear - 16 - 1 - - - GFC6 - Channel 6 Global flag clear - 20 - 1 - - - GFC7 - Channel 7 Global flag clear - 24 - 1 - - - FDTFC1 - Channel 1 full data transfer flag clear - 1 - 1 - - - FDTFC2 - Channel 2 full data transfer flag clear - 5 - 1 - - - FDTFC3 - Channel 3 full data transfer flag clear - 9 - 1 - - - FDTFC4 - Channel 4 full data transfer flag clear - 13 - 1 - - - FDTFC5 - Channel 5 full data transfer flag clear - 17 - 1 - - - FDTFC6 - Channel 6 full data transfer flag clear - 21 - 1 - - - FDTFC7 - Channel 7 full data transfer flag clear - 25 - 1 - - - HDTFC1 - Channel 1 half data transfer flag clear - 2 - 1 - - - HDTFC2 - Channel 2 half data transfer flag clear - 6 - 1 - - - HDTFC3 - Channel 3 half data transfer flag clear - 10 - 1 - - - HDTFC4 - Channel 4 half data transfer flag clear - 14 - 1 - - - HDTFC5 - Channel 5 half data transfer flag clear - 18 - 1 - - - HDTFC6 - Channel 6 half data transfer flag clear - 22 - 1 - - - HDTFC7 - Channel 7 half data transfer flag clear - 26 - 1 - - - DTERRFC1 - Channel 1 data transfer error flag clear - 3 - 1 - - - DTERRFC2 - Channel 2 data transfer error flag clear - 7 - 1 - - - DTERRFC3 - Channel 3 data transfer error flag clear - 11 - 1 - - - DTERRFC4 - Channel 4 data transfer error flag clear - 15 - 1 - - - DTERRFC5 - Channel 5 data transfer error flag clear - 19 - 1 - - - DTERRFC6 - Channel 6 data transfer error flag clear - 23 - 1 - - - DTERRFC7 - Channel 7 data transfer error flag clear - 27 - 1 - - - - - C1CTRL - C1CTRL - DMA channel configuration register(DMA_C1CTRL) - 0x8 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C1DTCNT - C1DTCNT - DMA channel 1 number of data to transfer register - 0xC - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C1PADDR - C1PADDR - DMA channel 1 peripheral base address register - 0x10 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C1MADDR - C1MADDR - DMA channel 1 memory base address register - 0x14 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C2CTRL - C2CTRL - DMA channel configuration register (DMA_C2CTRL) - 0x1C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C2DTCNT - C2DTCNT - DMA channel 2 number of data to transferregister - 0x20 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C2PADDR - C2PADDR - DMA channel 2 peripheral base address register - 0x24 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C2MADDR - C2MADDR - DMA channel 2 memory base address register - 0x28 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C3CTRL - C3CTRL - DMA channel configuration register (DMA_C3CTRL) - 0x30 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C3DTCNT - C3DTCNT - DMA channel 3 number of data to transfer register - 0x34 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C3PADDR - C3PADDR - DMA channel 3 peripheral base address register - 0x38 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C3MADDR - C3MADDR - DMA channel 3 memory base address register - 0x3C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C4CTRL - C4CTRL - DMA channel configuration register (DMA_C4CTRL) - 0x44 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C4DTCNT - C4DTCNT - DMA channel 4 number of data to transfer register - 0x48 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C4PADDR - C4PADDR - DMA channel 4 peripheral base address register - 0x4C - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C4MADDR - C4MADDR - DMA channel 4 memory base address register - 0x50 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C5CTRL - C5CTRL - DMA channel configuration register (DMA_C5CTRL) - 0x58 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C5DTCNT - C5DTCNT - DMA channel 5 number of data to transfer register - 0x5C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C5PADDR - C5PADDR - DMA channel 5 peripheral base address register - 0x60 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C5MADDR - C5MADDR - DMA channel 5 memory base address register - 0x64 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C6CTRL - C6CTRL - DMA channel configuration register(DMA_C6CTRL) - 0x6C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C6DTCNT - C6DTCNT - DMA channel 6 number of data to transfer register - 0x70 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C6PADDR - C6PADDR - DMA channel 6 peripheral address base register - 0x74 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C6MADDR - C6MADDR - DMA channel 6 memory address base register - 0x78 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C7CTRL - C7CTRL - DMA channel configuration register(DMA_C7CTRL) - 0x80 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C7DTCNT - C7DTCNT - DMA channel 7 number of data to transfer register - 0x84 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C7PADDR - C7PADDR - DMA channel 7 peripheral base address register - 0x88 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C7MADDR - C7MADDR - DMA channel 7 memory base address register - 0x8C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - DMA_MUXSEL - DMA_MUXSEL - DMAMUX Table Selection - 0x100 - 0x20 - 0x00000000 - - - TBL_SEL - Multiplexer Table Select - 0 - 1 - read-write - - - - - MUXC1CTRL - MUXC1CTRL - Channel 1 Configuration Register - 0x104 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC2CTRL - MUXC2CTRL - Channel 2 Configuration Register - 0x108 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC3CTRL - MUXC3CTRL - Channel 3 Configuration Register - 0x10C - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC4CTRL - MUXC4CTRL - Channel 4 Configuration Register - 0x110 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC5CTRL - MUXC5CTRL - Channel 5 Configuration Register - 0x114 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC6CTRL - MUXC6CTRL - Channel 6 Configuration Register - 0x118 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC7CTRL - MUXC7CTRL - Channel 7 Configuration Register - 0x11C - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXG1CTRL - MUXG1CTRL - Generator 1 Configuration Register - 0x120 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG2CTRL - MUXG2CTRL - Generator 2 Configuration Register - 0x124 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG3CTRL - MUXG3CTRL - Generator 3 Configuration Register - 0x128 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG4CTRL - MUXG4CTRL - Generator 4 Configuration Register - 0x12C - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXSYNCSTS - MUXSYNCSTS - Channel Interrupt Status Register - 0x130 - 0x20 - 0x00000000 - - - SYNCOVF1 - Synchronizaton overrun interrupt flag - 0 - 1 - read-only - - - SYNCOVF2 - Synchronizaton overrun interrupt flag - 1 - 1 - read-only - - - SYNCOVF3 - Synchronizaton overrun interrupt flag - 2 - 1 - read-only - - - SYNCOVF4 - Synchronizaton overrun interrupt flag - 3 - 1 - read-only - - - SYNCOVF5 - Synchronizaton overrun interrupt flag - 4 - 1 - read-only - - - SYNCOVF6 - Synchronizaton overrun interrupt flag - 5 - 1 - read-only - - - SYNCOVF7 - Synchronizaton overrun interrupt flag - 6 - 1 - read-only - - - - - MUXSYNCCLR - MUXSYNCCLR - Channel Interrupt Clear Flag Register - 0x134 - 0x20 - 0x00000000 - - - SYNCOVFC1 - Clear synchronizaton overrun interrupt flag - 0 - 1 - read-write - - - SYNCOVFC2 - Clear synchronizaton overrun interrupt flag - 1 - 1 - read-write - - - SYNCOVFC3 - Clear synchronizaton overrun interrupt flag - 2 - 1 - read-write - - - SYNCOVFC4 - Clear synchronizaton overrun interrupt flag - 3 - 1 - read-write - - - SYNCOVFC5 - Clear synchronizaton overrun interrupt flag - 4 - 1 - read-write - - - SYNCOVFC6 - Clear synchronizaton overrun interrupt flag - 5 - 1 - read-write - - - SYNCOVFC7 - Clear synchronizaton overrun interrupt flag - 6 - 1 - read-write - - - - - MUXGSTS - MUXGSTS - Generator Interrupt Status Register - 0x138 - 0x20 - 0x00000000 - - - TRGOVF1 - Trigger overrun interrupt flag - 0 - 1 - read-write - - - TRGOVF2 - Trigger overrun interrupt flag - 1 - 1 - read-write - - - TRGOVF3 - Trigger overrun interrupt flag - 2 - 1 - read-write - - - TRGOVF4 - Trigger overrun interrupt flag - 3 - 1 - read-write - - - - - MUXGCLR - MUXGCLR - Generator Interrupt Clear Flag Register - 0x13C - 0x20 - 0x00000000 - - - TRGOVFC1 - Clear trigger overrun interrupt flag - 0 - 1 - read-write - - - TRGOVFC2 - Clear trigger overrun interrupt flag - 1 - 1 - read-write - - - TRGOVFC3 - Clear trigger overrun interrupt flag - 2 - 1 - read-write - - - TRGOVFC4 - Clear trigger overrun interrupt flag - 3 - 1 - read-write - - - - - - - DMA2 - 0x40026400 - - - SDIO1 - Secure digital input/output - interface - SDIO - 0x4002C400 - - 0x0 - 0x400 - registers - - - SDIO1 - SDIO1 global interrupt - 49 - - - - PWRCTRL - PWRCTRL - Bits 1:0 = PWRCTRL: Power supply control - bits - 0x0 - 0x20 - read-write - 0x00000000 - - - PS - Power switch - 0 - 2 - - - - - CLKCTRL - CLKCTRL - SD clock control register - (SDIO_CLKCTRL) - 0x4 - 0x20 - read-write - 0x00000000 - - - CLKDIV - Clock division - 0 - 8 - - - CLKOEN - Clock output enable - 8 - 1 - - - PWRSVEN - Power saving mode enable - 9 - 1 - - - BYPSEN - Clock divider bypass enable - bit - 10 - 1 - - - BUSWS - Bus width selection - 11 - 2 - - - CLKEDS - SDIO_CK edge selection bit - 13 - 1 - - - HFCEN - Hardware flow control enable - 14 - 1 - - - CLKDIV98 - Clock divide factor bit9 and bit8 - 15 - 2 - - - - - ARGU - ARGU - Bits 31:0 = : Command argument - 0x8 - 0x20 - read-write - 0x00000000 - - - ARGU - Command argument - 0 - 32 - - - - - CMDCTRL - CMDCTRL - SDIO command control register - (SDIO_CMDCTRL) - 0xC - 0x20 - read-write - 0x00000000 - - - CMDIDX - CMDIDX - 0 - 6 - - - RSPWT - Wait for response - 6 - 2 - - - INTWT - CCSM wait for interrupt - 8 - 1 - - - PNDWT - CCSM wait for end of transfer - 9 - 1 - - - CCSMEN - Command channel state machine - 10 - 1 - - - IOSUSP - SD I/O suspend command - 11 - 1 - - - - - RSPCMD - RSPCMD - SDIO command register - 0x10 - 0x20 - read-only - 0x00000000 - - - RSPCMD - RSPCMD - 0 - 6 - - - - - RSP1 - RSP1 - Bits 31:0 = CARDSTATUS1 - 0x14 - 0x20 - read-only - 0x00000000 - - - CARDSTS1 - CARDSTATUS1 - 0 - 32 - - - - - RSP2 - RSP2 - Bits 31:0 = CARDSTATUS2 - 0x18 - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS2 - 0 - 32 - - - - - RSP3 - RSP3 - Bits 31:0 = CARDSTATUS3 - 0x1C - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS3 - 0 - 32 - - - - - RSP4 - RSP4 - Bits 31:0 = CARDSTATUS4 - 0x20 - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS4 - 0 - 32 - - - - - DTTMR - DTTMR - Bits 31:0 = TIMEOUT: Data timeout - period - 0x24 - 0x20 - read-write - 0x00000000 - - - TIMEOUT - Data timeout period - 0 - 32 - - - - - DTLEN - DTLEN - Bits 24:0 = DATALENGTH: Data length - value - 0x28 - 0x20 - read-write - 0x00000000 - - - DTLEN - Data length value - 0 - 25 - - - - - DTCTRL - DTCTRL - SDIO data control register - (SDIO_DCTRL) - 0x2C - 0x20 - read-write - 0x00000000 - - - TFREN - DTEN - 0 - 1 - - - TFRDIR - DTDIR - 1 - 1 - - - TFRMODE - DTMODE - 2 - 1 - - - DMAEN - DMAEN - 3 - 1 - - - BLKSIZE - DBLOCKSIZE - 4 - 4 - - - RDWTSTART - PWSTART - 8 - 1 - - - RDWTSTOP - PWSTOP - 9 - 1 - - - RDWTMODE - RWMOD - 10 - 1 - - - IOEN - SD I/O function enable - 11 - 1 - - - - - DTCNT - DTCNT - Bits 24:0 = DATACOUNT: Data count - value - 0x30 - 0x20 - read-only - 0x00000000 - - - CNT - Data count value - 0 - 25 - - - - - STS - STS - SDIO status register - (SDIO_STA) - 0x34 - 0x20 - read-only - 0x00000000 - - - CMDFAIL - Command crc fail - 0 - 1 - - - DTFAIL - Data crc fail - 1 - 1 - - - CMDTIMEOUT - Command timeout - 2 - 1 - - - DTTIMEOUT - Data timeout - 3 - 1 - - - TXERRU - Tx under run error - 4 - 1 - - - RXERRO - Rx over run error - 5 - 1 - - - CMDRSPCMPL - Command response complete - 6 - 1 - - - CMDCMPL - Command sent - 7 - 1 - - - DTCMPL - Data sent - 8 - 1 - - - SBITERR - Start bit error - 9 - 1 - - - DTBLKCMPL - Data block sent - 10 - 1 - - - DOCMD - Command transfer in progress - 11 - 1 - - - DOTX - Data transmit in progress - 12 - 1 - - - DORX - Data receive in progress - 13 - 1 - - - TXBUFH - Tx buffer half empty - 14 - 1 - - - RXBUFH - Rx buffer half empty - 15 - 1 - - - TXBUFF - Tx buffer full - 16 - 1 - - - RXBUFF - Rx buffer full - 17 - 1 - - - TXBUFE - Tx buffer empty - 18 - 1 - - - RXBUFE - Rx buffer empty - 19 - 1 - - - TXBUF - Tx data vaild - 20 - 1 - - - RXBUF - Rx data vaild - 21 - 1 - - - IOIF - SD I/O interrupt - 22 - 1 - - - - - INTCLR - INTCLR - SDIO interrupt clear register - (SDIO_INTCLR) - 0x38 - 0x20 - read-write - 0x00000000 - - - CMDFAIL - Command crc fail flag clear - 0 - 1 - - - DTFAIL - Data crc fail flag clear - 1 - 1 - - - CMDTIMEOUT - Command timeout flag clear - 2 - 1 - - - DTTIMEOUT - Data timeout flag clear - 3 - 1 - - - TXERRU - Tx under run error flag clear - 4 - 1 - - - RXERRU - Rx over run error flag clear - 5 - 1 - - - CMDRSPCMPL - Command response complete flag clear - 6 - 1 - - - CMDCMPL - Command sent flag clear - 7 - 1 - - - DTCMPL - Data sent flag clear - 8 - 1 - - - SBITERR - Start bit error flag clear - 9 - 1 - - - DTBLKCMPL - Data block sent clear - 10 - 1 - - - IOIF - SD I/O interrupt flag clear - 22 - 1 - - - - - INTEN - INTEN - SDIO mask register (SDIO_MASK) - 0x3C - 0x20 - read-write - 0x00000000 - - - CMDFAILIEN - Command crc fail interrupt enable - 0 - 1 - - - DTFAILIEN - Data crc fail interrupt enable - 1 - 1 - - - CMDTIMEOUTIEN - Command timeout interrupt enable - 2 - 1 - - - DTTIMEOUTIEN - Data timeout interrupt enable - 3 - 1 - - - TXERRUIEN - Tx under run interrupt enable - 4 - 1 - - - RXERRUIEN - Rx over run interrupt enable - 5 - 1 - - - CMDRSPCMPLIEN - Command response complete interrupt enable - 6 - 1 - - - CMDCMPLIEN - Command sent complete interrupt enable - 7 - 1 - - - DTCMPLIEN - Data sent complete interrupt enable - 8 - 1 - - - SBITERRIEN - Start bit error interrupt enable - 9 - 1 - - - DTBLKCMPLIEN - Data block sent complete interrupt enable - 10 - 1 - - - DOCMDIEN - Command acting interrupt enable - 11 - 1 - - - DOTXIEN - Data transmit acting interrupt enable - 12 - 1 - - - DORXIEN - Data receive acting interrupt enable - 13 - 1 - - - TXBUFHIEN - Tx buffer half empty interrupt enable - 14 - 1 - - - RXBUFHIEN - Rx buffer half empty interrupt enable - 15 - 1 - - - TXBUFFIEN - Tx buffer full interrupt enable - 16 - 1 - - - RXBUFFIEN - Rx buffer full interrupt enable - 17 - 1 - - - TXBUFEIEN - Tx buffer empty interrupt enable - 18 - 1 - - - RXBUFEIEN - Rx buffer empty interrupt enable - 19 - 1 - - - TXBUFIEN - Tx buffer data vaild interrupt enable - 20 - 1 - - - RXBUFIEN - Rx buffer data vaild interrupt enable - 21 - 1 - - - IOIFIEN - SD I/O interrupt enable - 22 - 1 - - - - - BUFCNT - BUFCNT - Bits 23:0 = BUFCOUNT: Remaining number of - words to be written to or read from the - FIFO - 0x48 - 0x20 - read-only - 0x00000000 - - - CNT - FIF0COUNT - 0 - 24 - - - - - BUF - BUF - bits 31:0 = Buffer Data: Receive and transmit - buffer data - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - Buffer data - 0 - 32 - - - - - - - SDIO2 - 0x50061000 - - SDIO2 - SDIO2 global interrupt - 102 - - - - ERTC - Real-time clock - ERTC - 0x40002800 - - 0x0 - 0x400 - registers - - - - TIME - TIME - time register - 0x0 - 0x20 - read-write - 0x00000000 - - - AMPM - AM/PM notation - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - DATE - DATE - date register - 0x4 - 0x20 - read-write - 0x00002101 - - - YT - Year tens - 20 - 4 - - - YU - Year units - 16 - 4 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - CTRL - CTRL - control register - 0x8 - 0x20 - read-write - 0x00000000 - - - CALOEN - Calibration output enable - 23 - 1 - - - OUTSEL - Output source selection - 21 - 2 - - - OUTP - Output polarity - 20 - 1 - - - CALOSEL - Calibration output selection - 19 - 1 - - - BPR - Battery power domain data register - 18 - 1 - - - DEC1H - Decrease 1 hour - 17 - 1 - - - ADD1H - Add 1 hour - 16 - 1 - - - TSIEN - Timestamp interrupt enable - 15 - 1 - - - WATIEN - Wakeup timer interrupt enable - 14 - 1 - - - ALBIEN - Alarm B interrupt enable - 13 - 1 - - - ALAIEN - Alarm A interrupt enable - 12 - 1 - - - TSEN - Timestamp enable - 11 - 1 - - - WATEN - Wakeup timer enable - 10 - 1 - - - ALBEN - Alarm B enable - 9 - 1 - - - ALAEN - Alarm A enable - 8 - 1 - - - CCALEN - Coarse calibration enable - 7 - 1 - - - HM - Hour mode - 6 - 1 - - - DREN - Date/time register direct read enable - 5 - 1 - - - RCDEN - Reference clock detection enable - 4 - 1 - - - TSEDG - Timestamp trigger edge - 3 - 1 - - - WATCLK - Wakeup timer clock selection - 0 - 3 - - - - - STS - STS - initialization and status - register - 0xC - 0x20 - 0x00000007 - - - ALAWF - Alarm A register allows write flag - 0 - 1 - read-only - - - ALBWF - Alarm B register allows write flag - 1 - 1 - read-only - - - WATWF - Wakeup timer register allows write flag - 2 - 1 - read-only - - - TADJF - Time adjustment flag - 3 - 1 - read-write - - - INITF - Calendar initialization flag - 4 - 1 - read-only - - - UPDF - Calendar update flag - 5 - 1 - read-write - - - IMF - Enter initialization mode flag - 6 - 1 - read-only - - - IMEN - Initialization mode enable - 7 - 1 - read-write - - - ALAF - Alarm A flag - 8 - 1 - read-write - - - ALBF - Alarm B flag - 9 - 1 - read-write - - - WATF - Wakeup timer flag - 10 - 1 - read-write - - - TSF - Timestamp flag - 11 - 1 - read-write - - - TSOF - Timestamp overflow flag - 12 - 1 - read-write - - - TP1F - Tamper detection 1 flag - 13 - 1 - read-write - - - TP2F - Tamper detection 2 flag - 14 - 1 - read-write - - - CALUPDF - Calibration value update completed flag - 16 - 1 - read-only - - - - - DIV - DIV - Diveder register - 0x10 - 0x20 - read-write - 0x007F00FF - - - DIVA - Diveder A - 16 - 7 - - - DIVB - Diveder B - 0 - 15 - - - - - WAT - WAT - Wakeup timer register - 0x14 - 0x20 - read-write - 0x0000FFFF - - - VAL - Wakeup timer reload value - 0 - 16 - - - - - CCAL - CCAL - Calibration register - 0x18 - 0x20 - read-write - 0x00000000 - - - CALDIR - Calibration direction - 7 - 1 - - - CALVAL - Calibration value - 0 - 5 - - - - - ALA - ALA - Alarm A register - 0x1C - 0x20 - read-write - 0x00000000 - - - MASK4 - Date/week mask - 31 - 1 - - - WKSEL - Date/week mode select - 30 - 1 - - - DT - Date tens - 28 - 2 - - - DU - Date units - 24 - 4 - - - MASK3 - Hours mask - 23 - 1 - - - AMPM - AM/PM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MASK2 - Minutes mask - 15 - 1 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - MASK1 - Seconds mask - 7 - 1 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - ALB - ALB - Alarm B register - 0x20 - 0x20 - read-write - 0x00000000 - - - MASK4 - Date/week mask - 31 - 1 - - - WKSEL - Date/week mode select - 30 - 1 - - - DT - Date tens - 28 - 2 - - - DU - Date units - 24 - 4 - - - MASK3 - Hours mask - 23 - 1 - - - AMPM - AM/PM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MASK2 - Minutes mask - 15 - 1 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - MASK1 - Seconds mask - 7 - 1 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - WP - WP - write protection register - 0x24 - 0x20 - write-only - 0x00000000 - - - CMD - Command register - 0 - 8 - - - - - SBS - SBS - sub second register - 0x28 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - TADJ - TADJ - time adjust register - 0x2C - 0x20 - write-only - 0x00000000 - - - ADD1S - Add 1 second - 31 - 1 - - - DECSBS - Decrease sub-second value - 0 - 15 - - - - - TSTM - TSTM - time stamp time register - 0x30 - 0x20 - read-only - 0x00000000 - - - AMPM - AMPM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - TSDT - TSDT - timestamp date register - 0x34 - 0x20 - read-only - 0x00000000 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - TSSBS - TSSBS - timestamp sub second register - 0x38 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - SCAL - SCAL - calibration register - 0x3C - 0x20 - read-write - 0x00000000 - - - ADD - Add ERTC clock - 15 - 1 - - - CAL8 - 8-second calibration period - 14 - 1 - - - CAL16 - 16 second calibration period - 13 - 1 - - - DEC - Decrease ERTC clock - 0 - 9 - - - - - TAMP - TAMP - tamper and alternate function configuration - register - 0x40 - 0x20 - read-write - 0x00000000 - - - OUTTYPE - Output type - 18 - 1 - - - TSPIN - Time stamp detection pin selection - 17 - 1 - - - TP1PIN - Tamper detection pin selection - 16 - 1 - - - TPPU - Tamper detection pull-up - 15 - 1 - - - TPPR - Tamper detection pre-charge time - 13 - 2 - - - TPFLT - Tamper detection filter time - 11 - 2 - - - TPFREQ - Tamper detection frequency - 8 - 3 - - - TPTSEN - Tamper detection timestamp enable - 7 - 1 - - - TP2EDG - Tamper detection 2 valid edge - 4 - 1 - - - TP2EN - Tamper detection 2 enable - 3 - 1 - - - TPIEN - Tamper detection interrupt enable - 2 - 1 - - - TP1EDG - Tamper detection 1 valid edge - 1 - 1 - - - TP1EN - Tamper detection 1 enable - 0 - 1 - - - - - ALASBS - ALASBS - alarm A sub second register - 0x44 - 0x20 - read-write - 0x00000000 - - - SBSMSK - Sub-second mask - 24 - 4 - - - SBS - Sub-seconds value - 0 - 15 - - - - - ALBSBS - ALBSBS - alarm B sub second register - 0x48 - 0x20 - read-write - 0x00000000 - - - SBSMSK - Sub-second mask - 24 - 4 - - - SBS - Sub-seconds value - 0 - 15 - - - - - BPR1DT - BPR1DT - Battery powered domain register - 0x50 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR2DT - BPR2DT - Battery powered domain register - 0x54 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR3DT - BPR3DT - Battery powered domain register - 0x58 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR4DT - BPR4DT - Battery powered domain register - 0x5C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR5DT - BPR5DT - Battery powered domain register - 0x60 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR6DT - BPR6DT - Battery powered domain register - 0x64 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR7DT - BPR7DT - Battery powered domain register - 0x68 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR8DT - BPR8DT - Battery powered domain register - 0x6C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR9DT - BPR9DT - Battery powered domain register - 0x70 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR10DT - BPR10DT - Battery powered domain register - 0x74 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR11DT - BPR11DT - Battery powered domain register - 0x78 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR12DT - BPR12DT - Battery powered domain register - 0x7C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR13DT - BPR13DT - Battery powered domain register - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR14DT - BPR14DT - Battery powered domain register - 0x84 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR15DT - BPR15DT - Battery powered domain register - 0x88 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR16DT - BPR16DT - Battery powered domain register - 0x8C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR17DT - BPR17DT - Battery powered domain register - 0x90 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR18DT - BPR18DT - Battery powered domain register - 0x94 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR19DT - BPR19DT - Battery powered domain register - 0x98 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR20DT - BPR20DT - Battery powered domain register - 0x9C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - - - WDT - Watchdog - WDT - 0x40003000 - - 0x0 - 0x400 - registers - - - - CMD - CMD - Command register - 0x0 - 0x20 - write-only - 0x00000000 - - - CMD - Command register - 0 - 16 - - - - - DIV - DIV - Division register - 0x4 - 0x20 - read-write - 0x00000000 - - - DIV - Division divider - 0 - 3 - - - - - RLD - RLD - Reload register - 0x8 - 0x20 - read-write - 0x00000FFF - - - RLD - Reload value - 0 - 12 - - - - - STS - STS - Status register - 0xC - 0x20 - read-only - 0x00000000 - - - DIVF - Division value update complete flag - 0 - 1 - - - RLDF - Reload value update complete flag - 1 - 1 - - - WINF - Window value update complete flag - 2 - 1 - - - - - WIN - WIN - Window register - 0x10 - 0x20 - read-write - 0x00000FFF - - - WIN - Window value - 0 - 12 - - - - - - - WWDT - Window watchdog - WWDT - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDT - Window Watchdog interrupt - 0 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - read-write - 0x0000007F - - - CNT - Decrement counter - 0 - 7 - - - WWDTEN - Window watchdog enable - 7 - 1 - - - - - CFG - CFG - Configuration register - 0x4 - 0x20 - read-write - 0x0000007F - - - WIN - Window value - 0 - 7 - - - DIV - Clock division value - 7 - 2 - - - RLDIEN - Reload counter interrupt - 9 - 1 - - - - - STS - STS - Status register - 0x8 - 0x20 - read-write - 0x00000000 - - - RLDF - Reload counter interrupt flag - 0 - 1 - - - - - - - TMR1 - Advanced timer - TIMER - 0x40010000 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - TMR1_CH - TMR1 channel interrupt - 27 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - TRGOUT2EN - TRGOUT2 enable - 31 - 1 - - - C4IOS - Channel 4 idle output state - 14 - 1 - - - C3CIOS - Channel 3 complementary idle output state - 13 - 1 - - - C3IOS - Channel 3 idle output state - 12 - 1 - - - C2CIOS - Channel 2 complementary idle output state - 11 - 1 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3CP - Channel 3 complementary polarity - 11 - 1 - - - C3CEN - Channel 3 complementary enable - 10 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - CM3_OUTPUT - CM3_OUTPUT - Channel output mode register - 0x70 - 0x20 - read-write - 0x00000000 - - - C5OSEN - Channel 5 output switch enable - 7 - 1 - - - C5OCTRL - Channel 5 output control - 4 - 3 - - - C5OBEN - Channel 5 output buffer enable - 3 - 1 - - - C5OIEN - Channel 5 output immediately enable - 2 - 1 - - - - - C5DT - C5DT - Channel 5 data register - 0x74 - 0x20 - read-write - 0x00000000 - - - C5DT - Channel 5 data register - 0 - 16 - - - - - - - TMR2 - General purpose timer - TIMER - 0x40000000 - - 0x0 - 0x400 - registers - - - TMR2 - TMR2 global interrupt - 28 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PMEN - Plus Mode Enable - 10 - 1 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 32 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 32 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 32 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 32 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 32 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 32 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - RMP - RMP - TMR2 input remap register - 0x50 - 0x20 - read-write - 0x0000 - - - TMR2_IS1_IRMP - TMR2 internal selection 3 remap - 10 - 2 - - - - - - - TMR3 - General purpose timer - TIMER - 0x40000400 - - 0x0 - 0x400 - registers - - - TMR3 - TMR3 global interrupt - 29 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR4 - 0x40000800 - - TMR4 - TMR4 global interrupt - 30 - - - - TMR9 - General purpose timer - TIMER - 0x40014000 - - 0x0 - 0x400 - registers - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C2CIOS - Channel 2 complementary idle output state - 11 - 1 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - BKF - brake input filter - 16 - 4 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR10 - General purpose timer - TIMER - 0x40014400 - - 0x0 - 0x400 - registers - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C1IEN - Channel 1 interrupt enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - BKF - brake input filter - 16 - 4 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR11 - 0x40014800 - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - - TMR13 - 0x40001C00 - - - TMR14 - 0x40002000 - - - RMP - RMP - TMR14 channel 1 input remap - 0x50 - 0x20 - read-write - 0x00000000 - - - TMR14_CH1_IRMP - TMR14 channel 1 input remap - 6 - 2 - - - - - - - TMR6 - Basic timer - TIMER - 0x40001000 - - 0x0 - 0x400 - registers - - - TMR6 - TMR6 global interrupt - 54 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - PTOS - Primary TMR output selection - 4 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - - - TMR7 - 0x40001400 - - TMR7 - TMR7 global interrupt - 55 - - - - ACC - HSI Auto Clock Calibration - ACC - 0x40017400 - - 0x0 - 0x400 - registers - - - - STS - STS - status register - 0x0 - 0x20 - 0x0000 - - - RSLOST - Reference Signal Lost - read-write - 1 - 1 - - - CALRDY - Internal high-speed clock calibration ready - read-write - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x04 - 0x20 - 0x0100 - - - STEP - STEP - read-write - 8 - 4 - - - CALRDYIEN - CALRDY interrupt enable - read-write - 5 - 1 - - - EIEN - RSLOST error interrupt enable - read-write - 4 - 1 - - - SOFSEL - SOF Select - read-write - 2 - 1 - - - ENTRIM - Enable trim - read-write - 1 - 1 - - - CALON - Calibration on - read-write - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x08 - 0x20 - 0x2080 - - - HICKTWK - Internal high-speed auto clock trimming - read-only - 8 - 6 - - - HICKCAL - Internal high-speed auto clock calibration - read-only - 0 - 8 - - - - - C1 - C1 - compare value 1 - 0x0C - 0x20 - 0x1F2C - - - C1 - Compare 1 - read-write - 0 - 16 - - - - - C2 - C2 - compare value 2 - 0x10 - 0x20 - 0x1F40 - - - C2 - Compare 2 - read-write - 0 - 16 - - - - - C3 - C3 - compare value 3 - 0x14 - 0x20 - 0x1F54 - - - C3 - Compare 3 - read-write - 0 - 16 - - - - - - - I2C1 - Inter-integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1_EVT - I2C1 event interrupt - 31 - - - I2C1_ERR - I2C1 error interrupt - 32 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - 0x00000000 - - - I2CEN - I2C peripheral enable - 0 - 1 - read-write - - - TDIEN - Transmit data interrupt enable - 1 - 1 - read-write - - - RDIEN - Receive data interrupt enable - 2 - 1 - read-write - - - ADDRIEN - Address match interrupt enable - 3 - 1 - read-write - - - ACKFAILIEN - Acknowledge fail interrupt enable - 4 - 1 - read-write - - - STOPIEN - Stop generation complete interrupt enable - 5 - 1 - read-write - - - TDCIEN - Transfer data complete interrupt enable - 6 - 1 - read-write - - - ERRIEN - Error interrupts enable - 7 - 1 - read-write - - - DFLT - Digital filter value - 8 - 4 - read-write - - - DMATEN - DMA Transmit data request enable - 14 - 1 - read-write - - - DMAREN - DMA receive data request enable - 15 - 1 - read-write - - - SCTRL - Slave receiving data control - 16 - 1 - read-write - - - STRETCH - Clock stretching mode - 17 - 1 - read-write - - - GCAEN - General call address enable - 19 - 1 - read-write - - - HADDREN - SMBus host address enable - 20 - 1 - read-write - - - DEVADDREN - SMBus device default address enable - 21 - 1 - read-write - - - SMBALERT - SMBus alert enable / pin set - 22 - 1 - read-write - - - PECEN - PEC calculation enable - 23 - 1 - read-write - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - PECTEN - Request PEC transmission enable - 26 - 1 - - - ASTOPEN - Automatically send stop condition enable - 25 - 1 - - - RLDEN - Send data reload mode enable - 24 - 1 - - - CNT - Transmit data counter - 16 - 8 - - - NACKEN - Not acknowledge enable - 15 - 1 - - - GENSTOP - Generate stop condition - 14 - 1 - - - GENSTART - Generate start condition - 13 - 1 - - - READH10 - 10-bit address header read enable - 12 - 1 - - - ADDR10 - Host send 10-bit address mode enable - 11 - 1 - - - DIR - Master data transmission direction - 10 - 1 - - - SADDR - Slave address - 0 - 10 - - - - - OADDR1 - OADDR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x00000000 - - - ADDR1 - Interface address - 0 - 10 - - - ADDR1MODE - Own Address mode - 10 - 1 - - - ADDR1EN - Own address 1 enable - 15 - 1 - - - - - OADDR2 - OADDR2 - Own address register 2 - 0xC - 0x20 - read-write - 0x00000000 - - - ADDR2 - Own address 2 - 1 - 7 - - - ADDR2MASK - Own address 2-bit mask - 8 - 3 - - - ADDR2EN - Own address 2 enable - 15 - 1 - - - - - CLKCTRL - CLKCTRL - Clock contorl register - 0x10 - 0x20 - read-write - 0x00000000 - - - SCLL - SCL low level - 0 - 8 - - - SCLH - SCL high level - 8 - 8 - - - SDAD - SDA output delay - 16 - 4 - - - SCLD - SCL output delay - 20 - 4 - - - DIVH - High 4 bits of clock divider value - 24 - 4 - - - DIVL - Low 4 bits of clock divider value - 28 - 4 - - - - - TIMEOUT - TIMEOUT - Timeout register - 0x14 - 0x20 - read-write - 0x00000000 - - - TOTIME - Clock timeout detection time - 0 - 12 - - - TOMOED - Clock timeout detection mode - 12 - 1 - - - TOEN - Detect clock low/high timeout enable - 15 - 1 - - - EXTTIME - Cumulative clock low extend timeout value - 16 - 12 - - - EXTEN - Cumulative clock low extend timeout enable - 31 - 1 - - - - - STS - STS - Interrupt and Status register - 0x18 - 0x20 - 0x00000001 - - - ADDR - Slave address matching value - 17 - 7 - read-only - - - SDIR - Slave data transmit direction - 16 - 1 - read-only - - - BUSYF - Bus busy - 15 - 1 - read-only - - - ALERTF - SMBus alert flag - 13 - 1 - read-only - - - TMOUT - SMBus timeout flag - 12 - 1 - read-only - - - PECERR - PEC receive error flag - 11 - 1 - read-only - - - OUF - Overflow or underflow flag - 10 - 1 - read-only - - - ARLOST - Arbitration lost flag - 9 - 1 - read-only - - - BUSERR - Bus error flag - 8 - 1 - read-only - - - TCRLD - Transmission is complete, waiting to load data - 7 - 1 - read-only - - - TDC - Transmit data complete flag - 6 - 1 - read-only - - - STOPF - Stop condition generation complete flag - 5 - 1 - read-only - - - ACKFAIL - Acknowledge failure flag - 4 - 1 - read-only - - - ADDRF - 0~7 bit address match flag - 3 - 1 - read-only - - - RDBF - Receive data buffer full flag - 2 - 1 - read-only - - - TDIS - Send interrupt status - 1 - 1 - read-write - - - TDBE - Transmit data buffer empty flag - 0 - 1 - read-write - - - - - CLR - CLR - Interrupt clear register - 0x1C - 0x20 - write-only - 0x00000000 - - - ALERTC - Clear SMBus alert flag - 13 - 1 - - - TMOUTC - Clear SMBus timeout flag - 12 - 1 - - - PECERRC - Clear PEC receive error flag - 11 - 1 - - - OUFC - Clear overload / underload flag - 10 - 1 - - - ARLOSTC - Clear arbitration lost flag - 9 - 1 - - - BUSERRC - Clear bus error flag - 8 - 1 - - - STOPC - Clear stop condition generation complete flag - 5 - 1 - - - ACKFAILC - Clear acknowledge failure flag - 4 - 1 - - - ADDRC - Clear 0~7 bit address match flag - 3 - 1 - - - - - PEC - PEC - PEC register - 0x20 - 0x20 - read-only - 0x00000000 - - - PECVAL - PEC value - 0 - 8 - - - - - RXDT - RXDT - Receive data register - 0x24 - 0x20 - read-only - 0x00000000 - - - DT - Receive data register - 0 - 8 - - - - - TXDT - TXDT - Transmit data register - 0x28 - 0x20 - read-write - 0x00000000 - - - DT - Transmit data register - 0 - 8 - - - - - - - I2C2 - 0x40005800 - - I2C2_EVT - I2C2 event interrupt - 33 - - - I2C2_ERR - I2C2 error interrupt - 34 - - - - I2C3 - 0x40005C00 - - I2C3_EVT - I2C3 event interrupt - 72 - - - I2C3_ERR - I2C3 error interrupt - 73 - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global interrupt - 35 - - - - CTRL1 - CTRL1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SLBEN - Single line bidirectional half-duplex enable - 15 - 1 - - - SLBTD - Single line bidirectional half-duplex transmission direction - 14 - 1 - - - CCEN - CRC calculation enable - 13 - 1 - - - NTC - Next transmission CRC - 12 - 1 - - - FBN - frame bit num - 11 - 1 - - - ORA - Only receive active - 10 - 1 - - - SWCSEN - Software CS enable - 9 - 1 - - - SWCSIL - Software CS internal level - 8 - 1 - - - LTF - LSB transmit first - 7 - 1 - - - SPIEN - SPI enable - 6 - 1 - - - MDIV2_0 - Master clock frequency division bit2-0 - 3 - 3 - - - MSTEN - Master enable - 2 - 1 - - - CLKPOL - Clock polarity - 1 - 1 - - - CLKPHA - Clock phase - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MDIV3EN - Master clock frequency3 division enable - 9 - 1 - - - MDIV3 - Master clock frequency division bit3 - 8 - 1 - - - TDBEIE - Transmit data buffer empty interrupt enable - 7 - 1 - - - RDBFIE - Receive data buffer full interrupt enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - TIEN - TI mode enable - 4 - 1 - - - HWCSOE - Hardware CS output enable - 2 - 1 - - - DMATEN - DMA transmit enable - 1 - 1 - - - DMAREN - DMA receive enable - 0 - 1 - - - - - STS - STS - status register - 0x8 - 0x20 - 0x0002 - - - CSPAS - CS pulse abnormal setting fiag - 8 - 1 - read-write - - - BF - Busy flag - 7 - 1 - read-only - - - ROERR - Receiver overflow error - 6 - 1 - read-only - - - MMERR - Master mode error - 5 - 1 - read-only - - - CCERR - CRC calculation error - 4 - 1 - read-write - - - TUERR - Transmitter underload error - 3 - 1 - read-only - - - ACS - Audio channel state - 2 - 1 - read-only - - - TDBE - Transmit data buffer empty - 1 - 1 - read-only - - - RDBF - Receive data buffer full - 0 - 1 - read-only - - - - - DT - DT - data register - 0xC - 0x20 - read-write - 0x0000 - - - DT - Data value - 0 - 16 - - - - - CPOLY - CPOLY - CRC polynomial register - 0x10 - 0x20 - read-write - 0x0007 - - - CPOLY - CRC polynomial - 0 - 16 - - - - - RCRC - RCRC - Receive CRC register - 0x14 - 0x20 - read-only - 0x0000 - - - RCRC - Receive CRC - 0 - 16 - - - - - TCRC - TCRC - Transmit CRC register - 0x18 - 0x20 - read-only - 0x0000 - - - TCRC - Transmit CRC - 0 - 16 - - - - - I2SCTRL - I2SCTRL - I2S control register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SMSEL - I2S mode select - 11 - 1 - - - I2SEN - I2S Enable - 10 - 1 - - - OPERSEL - I2S operation select - 8 - 2 - - - PCMFSSEL - PCM frame synchronization select - 7 - 1 - - - STDSEL - I2S standard select - 4 - 2 - - - I2SCLKPOL - I2S clock polarity - 3 - 1 - - - I2SDBN - I2S data bit num - 1 - 2 - - - I2SCBN - I2S channel bit num - 0 - 1 - - - - - I2SCLK - I2SCLK - I2S clock register - 0x20 - 0x20 - read-write - 00000010 - - - I2SDIV9_8 - I2S division bit9 and bit8 - 10 - 2 - - - I2SMCLKOE - I2S master clock output enable - 9 - 1 - - - I2SODD - Odd result for I2S division - 8 - 1 - - - I2SDIV7_0 - I2S division bit7 to bit0 - 0 - 8 - - - - - - - SPI2 - 0x40003800 - - SPI2 - SPI2 global interrupt - 36 - - - - SPI3 - 0x40003C00 - - SPI3 - SPI3 global interrupt - 51 - - - - I2SF5 - Serial peripheral interface - SPI - 0x40015000 - - 0x0 - 0x400 - registers - - - I2SF5 - I2SF5 global interrupt - 85 - - - - CTRL2 - CTRL2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - TDBEIE - Transmit data buffer empty interrupt enable - 7 - 1 - - - RDBFIE - Receive data buffer full interrupt enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - DMATEN - DMA transmit enable - 1 - 1 - - - DMAREN - DMA receive enable - 0 - 1 - - - - - STS - STS - status register - 0x8 - 0x20 - 0x0002 - - - CSPAS - CS pulse abnormal setting fiag - 8 - 1 - read-write - - - BF - Busy flag - 7 - 1 - read-only - - - ROERR - Receiver overflow error - 6 - 1 - read-only - - - TUERR - Transmitter underload error - 3 - 1 - read-only - - - ACS - Audio channel state - 2 - 1 - read-only - - - TDBE - Transmit data buffer empty - 1 - 1 - read-only - - - RDBF - Receive data buffer full - 0 - 1 - read-only - - - - - DT - DT - data register - 0xC - 0x20 - read-write - 0x0000 - - - DT - Data value - 0 - 16 - - - - - I2SCTRL - I2SCTRL - I2S control register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SFDUPEN - I2S full duplex mode enable - 13 - 1 - - - I2SEN - I2S Enable - 10 - 1 - - - OPERSEL - I2S operation select - 8 - 2 - - - PCMFSSEL - PCM frame synchronization select - 7 - 1 - - - STDSEL - I2S standard select - 4 - 2 - - - I2SCLKPOL - I2S clock polarity - 3 - 1 - - - I2SDBN - I2S data bit num - 1 - 2 - - - I2SCBN - I2S channel bit num - 0 - 1 - - - - - I2SCLK - I2SCLK - I2S clock register - 0x20 - 0x20 - read-write - 00000010 - - - I2SDIV9_8 - I2S division bit9 and bit8 - 10 - 2 - - - I2SMCLKOE - I2S master clock output enable - 9 - 1 - - - I2SODD - Odd result for I2S division - 8 - 1 - - - I2SDIV7_0 - I2S division bit7 to bit0 - 0 - 8 - - - - - MISC1 - MISC1 - MISC1 register - 0x30 - 0x20 - read-write - 00000000 - - - I2SFPCMCKSEL - I2S PCM clock edge select - 0 - 1 - - - - - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40011000 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global interrupt - 37 - - - - STS - STS - Status register - 0x0 - 0x20 - 0x00C0 - - - CMDF - Character match detection flag - 17 - 1 - read-write - - - RTODF - Reiceiver time out detection flag - 11 - 1 - read-write - - - CTSCF - CTS change flag - 9 - 1 - read-write - - - BFF - Break frame flag - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - 7 - 1 - read-only - - - TDC - Transmit data complete - 6 - 1 - read-write - - - RDBF - Receive data buffer full - 5 - 1 - read-write - - - IDLEF - IDLE flag - 4 - 1 - read-only - - - ROERR - Receiver overflow error - 3 - 1 - read-only - - - NERR - Noise error - 2 - 1 - read-only - - - FERR - Framing error - 1 - 1 - read-only - - - PERR - Parity error - 0 - 1 - read-only - - - - - DT - DT - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DT - Data value - 0 - 9 - - - - - BAUDR - BAUDR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV - Division - 0 - 16 - - - - - CTRL1 - CTRL1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - DBN1 - high bit for Data bit num - 28 - 1 - - - RTODEN - Receiver time out detection enable - 27 - 1 - - - RETODIE - Receiver time out detection interrupt enable - 26 - 1 - - - TSDT - transmit start delay time - 21 - 5 - - - TCDT - transmit complete delay time - 16 - 5 - - - CMDIE - Character match detection interrupt enable - 14 - 1 - - - UEN - USART enable - 13 - 1 - - - DBN0 - low bit for Data bit num - 12 - 1 - - - WUM - Wake up mode - 11 - 1 - - - PEN - Parity enable - 10 - 1 - - - PSEL - Parity selection - 9 - 1 - - - PERRIEN - PERR interrupt enable - 8 - 1 - - - TDBEIEN - TDBE interrupt enable - 7 - 1 - - - TDCIEN - TDC interrupt enable - 6 - 1 - - - RDBFIEN - RDBF interrupt enable - 5 - 1 - - - IDLEIEN - IDLE interrupt enable - 4 - 1 - - - TEN - Transmitter enable - 3 - 1 - - - REN - Receiver enable - 2 - 1 - - - RM - Receiver mute - 1 - 1 - - - SBF - Send break frame - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - IDH - bit 7-4 for usart identification - 28 - 4 - - - MTF - MSB transmit first - 19 - 1 - - - DTREV - DT register polarity reverse - 18 - 1 - - - TXREV - TX polarity reverse - 17 - 1 - - - RXREV - RX polarity reverse - 16 - 1 - - - TRPSWAP - Transmit receive pin swap - 15 - 1 - - - LINEN - LIN mode enable - 14 - 1 - - - STOPBN - STOP bit num - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CLKPOL - Clock polarity - 10 - 1 - - - CLKPHA - Clock phase - 9 - 1 - - - LBCP - Last bit clock pulse - 8 - 1 - - - BFIEN - Break frame interrupt enable - 6 - 1 - - - BFBN - Break frame bit num - 5 - 1 - - - IDBN - Identification bit num - 4 - 1 - - - IDL - bit 3-0 for usart identification - 0 - 4 - - - - - CTRL3 - CTRL3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - DEP - DE polarity selection - 15 - 1 - - - RS485EN - RS485 enable - 14 - 1 - - - CTSCFIEN - CTSCF interrupt enable - 10 - 1 - - - CTSEN - CTS enable - 9 - 1 - - - RTSEN - RTS enable - 8 - 1 - - - DMATEN - DMA transmitter enable - 7 - 1 - - - DMAREN - DMA receiver enable - 6 - 1 - - - SCMEN - Smartcard mode enable - 5 - 1 - - - SCNACKEN - Smartcard NACK enable - 4 - 1 - - - SLBEN - Single line bidirectional half-duplex enable - 3 - 1 - - - IRDALP - IrDA low-power mode - 2 - 1 - - - IRDAEN - IrDA enable - 1 - 1 - - - ERRIEN - Error interrupt enable - 0 - 1 - - - - - GDIV - GDIV - Guard time and division register - 0x18 - 0x20 - read-write - 0x0000 - - - SCGT - Smart card guard time value - 8 - 8 - - - ISDIV - IrDA/smartcard division value - 0 - 8 - - - - - RTOV - RTOV - Receiver time out value register - 0x1C - 0x20 - read-write - 0x0000 - - - RTOV - Receiver time out value - 0 - 24 - - - - - IFC - IFC - Interruption flag clear register - 0x20 - 0x20 - read-write - 0x0000 - - - CMDFC - Character match detection flag clear - 17 - 1 - - - RTODFC - Receiver time out detection flag clear - 11 - 1 - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global interrupt - 38 - - - - USART3 - 0x40004800 - - USART3 - USART3 global interrupt - 39 - - - - USART4 - 0x40004C00 - - USART4 - USART4 global interrupt - 52 - - - - USART5 - 0x40005000 - - USART5 - USART5 global interrupt - 53 - - - - USART6 - 0x40011400 - - USART6 - USART6 global interrupt - 71 - - - - UART7 - Universal asynchronous receiver transmitter - 0x40007800 - - UART7 - UART7 global interrupt - 82 - - - - UART8 - Universal asynchronous receiver transmitter - 0x40007C00 - - UART8 - UART8 global interrupt - 83 - - - - ADC1 - Analog to digital converter - ADC - 0x40012000 - - 0x0 - 0x100 - registers - - - ADC - ADC1 global interrupt - 18 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - CCE - Channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - CCEIEN - Channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - ITSRVEN - Internal temperature sensor and VINTRV enable - 23 - - - - 1 - - - OCSWTRG - Conversion trigger by software of ordinary channels - 22 - 1 - - - PCSWTRG - - Conversion trigger by software of preempted channels - 21 - 1 - - - OCTEN - Trigger mode enable for ordinary channels conversion - - 20 - 1 - - - OCTESEL - Low bit of trigger event select for ordinary channels conversion - - 17 - 3 - - - PCTEN - - Trigger mode enable for preempted channels conversion - 15 - 1 - - - PCTESEL - Low bit of trigger event select for preempted channels conversion - 12 - 3 - - - DTALIGN - Data alignment - 11 - 1 - - - OCDMAEN - DMA transfer enable of ordinary channels - 8 - 1 - - - ADCALINIT - initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 12 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 12 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 4 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - OVSP - OVSP - oversampling register - 0x80 - 0x20 - read-write - 0x00000000 - - - OOSRSEL - Ordinary oversampling recovery mode select - 10 - 1 - - - OOSTREN - Ordinary oversampling trigger mode enable - 9 - 1 - - - OSSSEL - Oversampling shift select - 5 - 4 - - - OSRSEL - Oversampling ratio select - 2 - 3 - - - POSEN - Preempted oversampling enable - 1 - 1 - - - OOSEN - Ordinary oversampling enable - 0 - 1 - - - - - - - ADCCOM - ADC common area - ADC - 0x40012300 - - 0x0 - 0x100 - registers - - - - CCTRL - CCTRL - Common control register - 0x4 - 0x20 - read-write - 0x00000000 - - - ADCDIV - ADC division - 16 - 4 - - - - - - - CAN1 - Can controller area network - CAN - 0x40006400 - - 0x0 - 0x400 - registers - - - CAN1_TX - CAN1 TX interrupt - 19 - - - CAN1_RX0 - CAN1 RX0 interrupt - 20 - - - CAN_RX1 - CAN1 RX1 interrupt - 21 - - - CAN_SE - CAN1 SE interrupt - 22 - - - - MCTRL - MCTRL - Main control register - 0x0 - 0x20 - read-write - 0x00010002 - - - PTD - Prohibit transmission when debug - 16 - 1 - - - SPRST - Software partial reset - 15 - 1 - - - TTCEN - Time triggered communication mode enable - 7 - 1 - - - AEBOEN - Automatic exit bus-off enable - 6 - 1 - - - AEDEN - Automatic exit doze mode enable - 5 - 1 - - - PRSFEN - Prohibit retransmission when sending fails enable - 4 - 1 - - - MDRSEL - Message discarding rule select when overflow - 3 - 1 - - - MMSSR - Multiple message sending sequence rule - 2 - 1 - - - DZEN - Doze mode enable - 1 - 1 - - - FZEN - Freeze mode enable - 0 - 1 - - - - - MSTS - MSTS - Main status register - 0x4 - 0x20 - 0x00000C02 - - - REALRX - Real time level of RX pin - 11 - 1 - read-only - - - LSAMPRX - Last sample level of RX pin - 10 - 1 - read-only - - - CURS - Currently receiving status - 9 - 1 - read-only - - - CUSS - Currently sending status - 8 - 1 - read-only - - - EDZIF - Enter doze mode interrupt flag - 4 - 1 - read-write - - - QDZIF - Quit doze mode interrupt flag - 3 - 1 - read-write - - - EOIF - Error occur Interrupt flag - 2 - 1 - read-write - - - DZC - Doze mode confirm - 1 - 1 - read-only - - - FZC - Freeze mode confirm - 0 - 1 - read-only - - - - - TSTS - TSTS - Transmit status register - 0x8 - 0x20 - 0x1C000000 - - - TM2LPF - Transmit mailbox 2 lowest priority flag - 31 - 1 - read-only - - - TM1LPF - Transmit mailbox 1 lowest priority flag - 30 - 1 - read-only - - - TM0LPF - Transmit mailbox 0 lowest priority flag - 29 - 1 - read-only - - - TM2EF - Transmit mailbox 2 empty flag - 28 - 1 - read-only - - - TM1EF - Transmit mailbox 1 empty flag - 27 - 1 - read-only - - - TM0EF - Transmit mailbox 0 empty flag - 26 - 1 - read-only - - - TMNR - Transmit Mailbox number record - 24 - 2 - read-only - - - TM2CT - Transmit mailbox 2 cancel transmission - 23 - 1 - read-write - - - TM2TEF - Transmit mailbox 2 transmission error flag - 19 - 1 - read-write - - - TM2ALF - Transmit mailbox 2 arbitration lost flag - 18 - 1 - read-write - - - TM2TSF - Transmit mailbox 2 transmission success flag - 17 - 1 - read-write - - - TM2TCF - transmit mailbox 2 transmission complete flag - 16 - 1 - read-write - - - TM1CT - Transmit mailbox 1 cancel transmission - 15 - 1 - read-write - - - TM1TEF - Transmit mailbox 1 transmission error flag - 11 - 1 - read-write - - - TM1ALF - Transmit mailbox 1 arbitration lost flag - 10 - 1 - read-write - - - TM1TSF - Transmit mailbox 1 transmission success flag - 9 - 1 - read-write - - - TM1TCF - Transmit mailbox 1 transmission complete flag - 8 - 1 - read-write - - - TM0CT - Transmit mailbox 0 cancel transmission - 7 - 1 - read-write - - - TM0TEF - Transmit mailbox 0 transmission error flag - 3 - 1 - read-write - - - TM0ALF - Transmit mailbox 0 arbitration lost flag - 2 - 1 - read-write - - - TM0TSF - Transmit mailbox 0 transmission success flag - 1 - 1 - read-write - - - TM0TCF - Transmit mailbox 0 transmission complete flag - 0 - 1 - read-write - - - - - RF0 - RF0 - Receive FIFO 0 register - 0xC - 0x20 - 0x00000000 - - - RF0R - Receive FIFO 0 release - 5 - 1 - read-write - - - RF0OF - Receive FIFO 0 overflow flag - 4 - 1 - read-write - - - RF0FF - Receive FIFO 0 full flag - 3 - 1 - read-write - - - RF0MN - Receive FIFO 0 message num - 0 - 2 - read-only - - - - - RF1 - RF1 - Receive FIFO 1 register - 0x10 - 0x20 - 0x00000000 - - - RF1R - Receive FIFO 1 release - 5 - 1 - read-write - - - RF1OF - Receive FIFO 1 overflow flag - 4 - 1 - read-write - - - RF1FF - Receive FIFO 1 full flag - 3 - 1 - read-write - - - RF1MN - Receive FIFO 1 message num - 0 - 2 - read-only - - - - - INTEN - INTEN - Interrupt enable register - 0x14 - 0x20 - read-write - 0x00000000 - - - EDZIEN - Enter doze mode interrupt enable - 17 - 1 - - - QDZIEN - Quit doze mode interrupt enable - 16 - 1 - - - EOIEN - Error occur interrupt enable - 15 - 1 - - - ETRIEN - Error type record interrupt enable - 11 - 1 - - - BOIEN - Bus-off interrupt enable - 10 - 1 - - - EPIEN - Error passive interrupt enable - 9 - 1 - - - EAIEN - Error active interrupt enable - 8 - 1 - - - RF1OIEN - Receive FIFO 1 overflow interrupt enable - 6 - 1 - - - RF1FIEN - Receive FIFO 1 full interrupt enable - 5 - 1 - - - RF1MIEN - FIFO 1 receive message interrupt enable - 4 - 1 - - - RF0OIEN - Receive FIFO 0 overflow interrupt enable - 3 - 1 - - - RF0FIEN - Receive FIFO 0 full interrupt enable - 2 - 1 - - - RF0MIEN - FIFO 0 receive message interrupt enable - 1 - 1 - - - TCIEN - Transmission complete interrupt enable - 0 - 1 - - - - - ESTS - ESTS - Error status register - 0x18 - 0x20 - 0x00000000 - - - REC - Receive error counter - 24 - 8 - read-only - - - TEC - Transmit error counter - 16 - 8 - read-only - - - ETR - Error type record - 4 - 3 - read-write - - - BOF - Bus-off flag - 2 - 1 - read-only - - - EPF - Error passive flag - 1 - 1 - read-only - - - EAF - Error active flag - 0 - 1 - read-only - - - - - BTMG - BTMG - Bit timing register - 0x1C - 0x20 - read-write - 0x00000000 - - - LOEN - Listen-Only mode - 31 - 1 - - - LBEN - Loop back mode - 30 - 1 - - - RSAW - Resynchronization adjust width - 24 - 2 - - - BTS2 - Bit time segment 2 - 20 - 3 - - - BTS1 - Bit time segment 1 - 16 - 4 - - - BRDIV - Baud rate division - 0 - 12 - - - - - TMI0 - TMI0 - Transmit mailbox 0 identifier register - 0x180 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC0 - TMC0 - Transmit mailbox 0 data length and time stamp register - 0x184 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL0 - TMDTL0 - Transmit mailbox 0 low byte data register - 0x188 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH0 - TMDTH0 - Transmit mailbox 0 high byte data register - 0x18C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI1 - TMI1 - Transmit mailbox 1 identifier register - 0x190 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC1 - TMC1 - Transmit mailbox 1 data length and time stamp register - 0x194 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL1 - TMDTL1 - Transmit mailbox 1 low byte data register - 0x198 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH1 - TMDTH1 - Transmit mailbox 1 high byte data register - 0x19C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI2 - TMI2 - Transmit mailbox 2 identifier register - 0x1A0 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC2 - TMC2 - Transmit mailbox 2 data length and time stamp register - 0x1A4 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL2 - TMDTL2 - Transmit mailbox 2 low byte data register - 0x1A8 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH2 - TMDTH2 - Transmit mailbox 2 high byte data register - 0x1AC - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - RFI0 - RFI0 - Receive FIFO 0 register - 0x1B0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC0 - RFC0 - Receive FIFO 0 data length and time stamp register - 0x1B4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL0 - RFDTL0 - Receive FIFO 0 low byte data register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH0 - RFDTH0 - Receive FIFO 0 high byte data register - 0x1BC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - RFI1 - RFI1 - Receive FIFO 1 register - 0x1C0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC1 - RFC1 - Receive FIFO 1 data length and time stamp register - 0x1C4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL1 - RFDTL1 - Receive FIFO 1 low byte data register - 0x1C8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH1 - RFDTH1 - Receive FIFO 1 high byte data register - 0x1CC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - FCTRL - FCTRL - Filter control register - 0x200 - 0x20 - read-write - 0x00000000 - - - FCS - Filters configure switch - 0 - 1 - - - - - FMCFG - FMCFG - Filter mode config register - 0x204 - 0x20 - read-write - 0x00000000 - - - FMSEL0 - Filter mode select - 0 - 1 - - - FMSEL1 - Filter mode select - 1 - 1 - - - FMSEL2 - Filter mode select - 2 - 1 - - - FMSEL3 - Filter mode select - 3 - 1 - - - FMSEL4 - Filter mode select - 4 - 1 - - - FMSEL5 - Filter mode select - 5 - 1 - - - FMSEL6 - Filter mode select - 6 - 1 - - - FMSEL7 - Filter mode select - 7 - 1 - - - FMSEL8 - Filter mode select - 8 - 1 - - - FMSEL9 - Filter mode select - 9 - 1 - - - FMSEL10 - Filter mode select - 10 - 1 - - - FMSEL11 - Filter mode select - 11 - 1 - - - FMSEL12 - Filter mode select - 12 - 1 - - - FMSEL13 - Filter mode select - 13 - 1 - - - - - FBWCFG - FBWCFG - Filter bit width config register - 0x20C - 0x20 - read-write - 0x00000000 - - - FBWSEL0 - Filter bit width select - 0 - 1 - - - FBWSEL1 - Filter bit width select - 1 - 1 - - - FBWSEL2 - Filter bit width select - 2 - 1 - - - FBWSEL3 - Filter bit width select - 3 - 1 - - - FBWSEL4 - Filter bit width select - 4 - 1 - - - FBWSEL5 - Filter bit width select - 5 - 1 - - - FBWSEL6 - Filter bit width select - 6 - 1 - - - FBWSEL7 - Filter bit width select - 7 - 1 - - - FBWSEL8 - Filter bit width select - 8 - 1 - - - FBWSEL9 - Filter bit width select - 9 - 1 - - - FBWSEL10 - Filter bit width select - 10 - 1 - - - FBWSEL11 - Filter bit width select - 11 - 1 - - - FBWSEL12 - Filter bit width select - 12 - 1 - - - FBWSEL13 - Filter bit width select - 13 - 1 - - - - - FRF - FRF - Filter related FIFO register - 0x214 - 0x20 - read-write - 0x00000000 - - - FRFSEL0 - Filter relation FIFO select - 0 - 1 - - - FRFSEL1 - Filter relation FIFO select - 1 - 1 - - - FRFSEL2 - Filter relation FIFO select - 2 - 1 - - - FRFSEL3 - Filter relation FIFO select - 3 - 1 - - - FRFSEL4 - Filter relation FIFO select - 4 - 1 - - - FRFSEL5 - Filter relation FIFO select - 5 - 1 - - - FRFSEL6 - Filter relation FIFO select - 6 - 1 - - - FRFSEL7 - Filter relation FIFO select - 7 - 1 - - - FRFSEL8 - Filter relation FIFO select - 8 - 1 - - - FRFSEL9 - Filter relation FIFO select - 9 - 1 - - - FRFSEL10 - Filter relation FIFO select - 10 - 1 - - - FRFSEL11 - Filter relation FIFO select - 11 - 1 - - - FRFSEL12 - Filter relation FIFO select - 12 - 1 - - - FRFSEL13 - Filter relation FIFO select - 13 - 1 - - - - - FACFG - FACFG - Filter activate configuration register - 0x21C - 0x20 - read-write - 0x00000000 - - - FAEN0 - Filter activate enable - 0 - 1 - - - FAEN1 - Filter activate enable - 1 - 1 - - - FAEN2 - Filter activate enable - 2 - 1 - - - FAEN3 - Filter activate enable - 3 - 1 - - - FAEN4 - Filter activate enable - 4 - 1 - - - FAEN5 - Filter activate enable - 5 - 1 - - - FAEN6 - Filter activate enable - 6 - 1 - - - FAEN7 - Filter activate enable - 7 - 1 - - - FAEN8 - Filter activate enable - 8 - 1 - - - FAEN9 - Filter activate enable - 9 - 1 - - - FAEN10 - Filter activate enable - 10 - 1 - - - FAEN11 - Filter activate enable - 11 - 1 - - - FAEN12 - Filter activate enable - 12 - 1 - - - FAEN13 - Filter activate enable - 13 - 1 - - - - - F0FB1 - F0FB1 - Filter bank 0 filtrate bit register 1 - 0x240 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F0FB2 - F0FB2 - Filter bank 0 filtrate bit register 2 - 0x244 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB1 - F1FB1 - Filter bank 1 filtrate bit register 1 - 0x248 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB2 - F1FB2 - Filter bank 1 filtrate bit register 2 - 0x24C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB1 - F2FB1 - Filter bank 2 filtrate bit register 1 - 0x250 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB2 - F2FB2 - Filter bank 2 filtrate bit register 2 - 0x254 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB1 - F3FB1 - Filter bank 3 filtrate bit register 1 - 0x258 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB2 - F3FB2 - Filter bank 3 filtrate bit register 2 - 0x25C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB1 - F4FB1 - Filter bank 4 filtrate bit register 1 - 0x260 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB2 - F4FB2 - Filter bank 4 filtrate bit register 2 - 0x264 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB1 - F5FB1 - Filter bank 5 filtrate bit register 1 - 0x268 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB2 - F5FB2 - Filter bank 5 filtrate bit register 2 - 0x26C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB1 - F6FB1 - Filter bank 6 filtrate bit register 1 - 0x270 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB2 - F6FB2 - Filter bank 6 filtrate bit register 2 - 0x274 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - F7FB1 - F7FB1 - Filter bank 7 filtrate bit register 1 - 0x278 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB2 - F7FB2 - Filter bank 7 filtrate bit register 2 - 0x27C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB1 - F8FB1 - Filter bank 8 filtrate bit register 1 - 0x280 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB2 - F8FB2 - Filter bank 8 filtrate bit register 2 - 0x284 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB1 - F9FB1 - Filter bank 9 filtrate bit register 1 - 0x288 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB2 - F9FB2 - Filter bank 9 filtrate bit register 2 - 0x28C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB1 - F10FB1 - Filter bank 10 filtrate bit register 1 - 0x290 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB2 - F10FB2 - Filter bank 10 filtrate bit register 2 - 0x294 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB1 - F11FB1 - Filter bank 11 filtrate bit register 1 - 0x298 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB2 - F11FB2 - Filter bank 11 filtrate bit register 2 - 0x29C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB1 - F12FB1 - Filter bank 12 filtrate bit register 1 - 0x2A0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB2 - F12FB2 - Filter bank 12 filtrate bit register 2 - 0x2A4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB1 - F13FB1 - Filter bank 13 filtrate bit register 1 - 0x2A8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB2 - F13FB2 - Filter bank 13 filtrate bit register 2 - 0x2AC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - - DEBUG - Debug support - DEBUG - 0xE0042000 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - DEBUG IDCODE - 0x0 - 0x20 - read-only - 0x0 - - - PID - Product ID - 0 - 32 - - - - - CTRL - CTRL - DEBUG CTRL - 0x4 - 0x20 - read-write - 0x0 - - - SLEEP_DEBUG - SLEEP_DEBUG - 0 - 1 - - - DEEPSLEEP_DEBUG - DEEPSLEEP_DEBUG - 1 - 1 - - - STANDBY_DEBUG - STANDBY_DEBUG - 2 - 1 - - - - - APB1_PAUSE - APB1_PAUSE - DEBUG APB1 PAUSE - 0x8 - 0x20 - read-write - 0x0 - - - TMR2_PAUSE - TMR2_PAUSE - 0 - 1 - - - TMR3_PAUSE - TMR3_PAUSE - 1 - 1 - - - TMR4_PAUSE - TMR4_PAUSE - 2 - 1 - - - TMR6_PAUSE - TMR6_PAUSE - 4 - 1 - - - TMR7_PAUSE - TMR7_PAUSE - 5 - 1 - - - TMR13_PAUSE - TMR13_PAUSE - 7 - 1 - - - TMR14_PAUSE - TMR14_PAUSE - 8 - 1 - - - ERTC_PAUSE - ERTC_PAUSE - 10 - 1 - - - WWDT_PAUSE - WWDT_PAUSE - 11 - 1 - - - WDT_PAUSE - WDT_PAUSE - 12 - 1 - - - ERTC512_PAUSE - ERTC512_PAUSE - 15 - 1 - - - I2C1_SMBUS_TIMEOUT - I2C1_SMBUS_TIMEOUT - 24 - 1 - - - CAN1_PAUSE - CAN1_PAUSE - 25 - 1 - - - I2C2_SMBUS_TIMEOUT - I2C2_SMBUS_TIMEOUT - 27 - 1 - - - I2C3_SMBUS_TIMEOUT - I2C3_SMBUS_TIMEOUT - 28 - 1 - - - - - APB2_PAUSE - APB2_PAUSE - DEBUG APB2 PAUSE - 0xC - 0x20 - read-write - 0x0 - - - TMR1_PAUSE - TMR1_PAUSE - 0 - 1 - - - TMR9_PAUSE - TMR9_PAUSE - 16 - 1 - - - TMR10_PAUSE - TMR10_PAUSE - 17 - 1 - - - TMR11_PAUSE - TMR11_PAUSE - 18 - 1 - - - - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DT - DT - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DT - Data Register - 0 - 32 - - - - - CDT - CDT - Common data register - 0x4 - 0x20 - read-write - 0x00000000 - - - CDT - Common Data - 0 - 1 - - - - - CTRL - CTRL - Control register - 0x8 - 0x20 - read-write - 0x00000000 - - - RST - Reset bit - 0 - 1 - - - REVID - Reverse input data - 5 - 2 - - - REVOD - Reverse output data - 7 - 1 - - - - - IDT - IDT - Initial data register - 0x10 - 0x20 - read-write - 0xFFFFFFFF - - - IDT - Initial Data - 0 - 32 - - - - - - - FLASH - Flash memory controler - FLASH - 0x40023C00 - - 0x0 - 0x400 - registers - - - FLASH - Flash global interrupt - 4 - - - - PSR - PSR - Performance selection register - 0x0 - 0x20 - 0x00000330 - - - NZW_BST_STS - Flash non-zero wait area boost status - 13 - 1 - read-only - - - NZW_BST - Flash non-zero wait area boost - 12 - 1 - read-write - - - - - UNLOCK - UNLOCK - Unlock register - 0x4 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - USD_UNLOCK - USD_UNLOCK - USD unlock register - 0x8 - 0x20 - write-only - 0x00000000 - - - USD_UKVAL - User system data Unlock key value - 0 - 32 - - - - - STS - STS - Status register - 0xC - 0x20 - 0x00000000 - - - ODF - Operate done flag - 5 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - PRGMERR - program error - 2 - 1 - read-write - - - OBF - Operate busy flag - 0 - 1 - read-only - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - BLKERS - Block erase - 3 - 1 - - - USDPRGM - User system data program - 4 - 1 - - - USDERS - User system data erase - 5 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - USDULKS - User system data unlock success - 9 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR - ADDR - Address register - 0x14 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - USD - USD - User system data register - 0x1C - 0x20 - read-only - 0x03FFFFFC - - - USDERR - User system data error - 0 - 1 - - - FAP - FLASH access protection - 1 - 1 - - - nWDT_ATO_EN - WDT auto enable - 2 - 1 - - - nDEPSLP_RST - Deepsleep reset - 3 - 1 - - - nSTDBY_RST - Standby reset - 4 - 1 - - - BTOPT - boot option - 5 - 1 - - - nWDT_DEPSLP - WDT deep sleep - 7 - 1 - - - nWDT_STDBY - WDT standby - 8 - 1 - - - USER_D0 - User data 0 - 10 - 8 - - - USER_D1 - User data 1 - 18 - 8 - - - - - EPPS0 - EPPS0 - Erase/program protection status register 0 - 0x20 - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - EPPS1 - EPPS1 - Erase/program protection status register 1 - 0x2C - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - UNLOCK2 - UNLOCK2 - Unlock 2 register - 0x44 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - STS2 - STS2 - Status 2 register - 0x4C - 0x20 - 0x00000000 - - - OBF - Operate busy flag - 0 - 1 - read-only - - - PRGMERR - program error - 2 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - ODF - Operate done flag - 5 - 1 - read-write - - - - - CTRL2 - CTRL2 - Control 2 register - 0x50 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - BLKERS - Block erase - 3 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR2 - ADDR2 - Address 2 register - 0x54 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - CONTR - CONTR - Flash continue read register - 0x58 - 0x20 - read-write - 0x00000080 - - - FCONTR_EN - Flash continue read enable - 31 - 1 - - - - - DIVR - DIVR - Flash divider register - 0x60 - 0x20 - 0x00000022 - - - FDIV - Flash divider - 0 - 2 - read-write - - - FDIV_STS - Flash divider status - 4 - 2 - read-only - - - - - SLIB_STS2 - SLIB_STS2 - sLib status 2 register - 0xC8 - 0x20 - 0x0000FFFF - - - SLIB_INST_SS - sLib instruction start sector - 0 - 16 - read-only - - - - - SLIB_STS0 - SLIB_STS0 - sLib status 0 register - 0xCC - 0x20 - 0x00000000 - - - SLIB_ENF - sLib enabled flag - 3 - 1 - read-only - - - - - SLIB_STS1 - SLIB_STS1 - sLib status 1 register - 0xD0 - 0x20 - 0xFFFFFFFF - - - SLIB_SS - sLib start sector - 0 - 16 - read-only - - - SLIB_ES - sLib end sector - 16 - 16 - read-only - - - - - SLIB_PWD_CLR - SLIB_PWD_CLR - SLIB password clear register - 0xD4 - 0x20 - 0x00000000 - write-only - - - SLIB_PCLR_VAL - sLib password clear value - 0 - 32 - - - - - SLIB_MISC_STS - SLIB_MISC_STS - sLib misc status register - 0xD8 - 0x20 - 0x01000000 - - - SLIB_PWD_ERR - sLib password error - 0 - 1 - read-only - - - SLIB_PWD_OK - sLib password ok - 1 - 1 - read-only - - - SLIB_ULKF - sLib unlock flag - 2 - 1 - read-only - - - SLIB_RCNT - sLib remaining count - 16 - 9 - read-only - - - - - SLIB_SET_PWD - SLIB_SET_PWD - sLib password setting register - 0xDC - 0x20 - 0x00000000 - write-only - - - SLIB_PSET_VAL - sLib password setting val - 0 - 32 - - - - - SLIB_SET_RANGE0 - SLIB_SET_RANGE0 - Configure sLib range register 0 - 0xE0 - 0x20 - 0x00000000 - write-only - - - SLIB_SS_SET - sLib start sector setting - 0 - 16 - - - SLIB_ES_SET - sLib end sector setting - 16 - 16 - - - - - SLIB_SET_RANGE1 - SLIB_SET_RANGE1 - Configure sLib range register 1 - 0xE4 - 0x20 - 0x00000000 - write-only - - - SLIB_ISS_SET - sLib instruction start sector setting - 0 - 16 - - - SET_SLIB_STRT - sLib start setting - 31 - 1 - - - - - SLIB_UNLOCK - SLIB_UNLOCK - sLib unlock register - 0xF0 - 0x20 - 0x00000000 - write-only - - - SLIB_UKVAL - sLib unlock key value - 0 - 32 - - - - - CRC_CTRL - CRC_CTRL - CRC controler register - 0xF4 - 0x20 - 0x00000000 - write-only - - - CRC_SS - CRC start sector - 0 - 12 - - - CRC_SN - CRC sector numbler - 12 - 12 - - - CRC_STRT - CRC start - 31 - 1 - - - - - CRC_CHKR - CRC_CHKR - CRC check result register - 0xF8 - 0x20 - 0x00000000 - read-only - - - CRC_CHKR - CRC check result - 0 - 32 - - - - - - - NVIC - Nested Vectored Interrupt - Controller - NVIC - 0xE000E000 - - 0x0 - 0x1001 - registers - - - - ICTR - ICTR - Interrupt Controller Type - Register - 0x4 - 0x20 - read-only - 0x00000000 - - - INTLINESNUM - Total number of interrupt lines in - groups - 0 - 4 - - - - - STIR - STIR - Software Triggered Interrupt - Register - 0xF00 - 0x20 - write-only - 0x00000000 - - - INTID - interrupt to be triggered - 0 - 9 - - - - - ISER0 - ISER0 - Interrupt Set-Enable Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER1 - ISER1 - Interrupt Set-Enable Register - 0x104 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ICER0 - ICER0 - Interrupt Clear-Enable - Register - 0x180 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear-Enable - Register - 0x184 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x200 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x204 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending - Register - 0x280 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending - Register - 0x284 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - IABR0 - IABR0 - Interrupt Active Bit Register - 0x300 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IABR1 - IABR1 - Interrupt Active Bit Register - 0x304 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IPR0 - IPR0 - Interrupt Priority Register - 0x400 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR1 - IPR1 - Interrupt Priority Register - 0x404 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR2 - IPR2 - Interrupt Priority Register - 0x408 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR3 - IPR3 - Interrupt Priority Register - 0x40C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR4 - IPR4 - Interrupt Priority Register - 0x410 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR5 - IPR5 - Interrupt Priority Register - 0x414 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR6 - IPR6 - Interrupt Priority Register - 0x418 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR7 - IPR7 - Interrupt Priority Register - 0x41C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR8 - IPR8 - Interrupt Priority Register - 0x420 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR9 - IPR9 - Interrupt Priority Register - 0x424 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR10 - IPR10 - Interrupt Priority Register - 0x428 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR11 - IPR11 - Interrupt Priority Register - 0x42C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR12 - IPR12 - Interrupt Priority Register - 0x430 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR13 - IPR13 - Interrupt Priority Register - 0x434 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR14 - IPR14 - Interrupt Priority Register - 0x438 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - - - DVP - Digital video parallel interface - DVP - 0x50050000 - - 0x0 - 0x400 - registers - - - DVP - DVP global interrupt - 78 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - 0x0000 - - - LCDS - Line capture/drop selection - 20 - 1 - read-write - - - LCDC - Line capture/drop control - - 19 - 1 - read-write - - - PCDS - Pixel capture/drop selection - - 18 - 1 - read-write - - - PCDC - Basic pixel capture/drop control - - 16 - 2 - read-write - - - ENA - DVP enable - 14 - 1 - read-write - - - PDL - Pixel data length - 10 - 2 - read-write - - - BFRC - Basic frame rate control - 8 - 2 - read-write - - - VSP - Vertical synchronization - polarity - 7 - 1 - read-write - - - HSP - Horizontal synchronization polarity - - 6 - 1 - read-write - - - CKP - Pixel clock polarity - 5 - 1 - read-write - - - SM - synchronization mode - 4 - 1 - read-write - - - JPEG - JPEG format - 3 - 1 - read-write - - - CRP - Cropping function enable - 2 - 1 - read-write - - - CFM - Capture fire mode - 1 - 1 - read-write - - - CAP - Capture function enable - 0 - 1 - read-write - - - - - STS - STS - status register - 0x4 - 0x20 - read-only - 0x0000 - - - OFNE - Output FIFO Non-empty - 2 - 1 - - - VSYN - Vertical synchronization status - 1 - 1 - - - HSYN - Horizontal synchronization status - 0 - 1 - - - - - ESTS - ESTS - Event status register - 0x8 - 0x20 - read-only - 0x0000 - - - HSES - Horizontal synchronization event status - 4 - 1 - - - VSES - Vertical synchronization event status - 3 - 1 - - - ESEES - Embedded synchronization error event status - - 2 - 1 - - - OVRES - Data FIFO overrun event status - - 1 - 1 - - - CFDES - Capture frame done event status - - 0 - 1 - - - - - IENA - IENA - interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - HSIE - Horizontal synchronization interrupt enable - - 4 - 1 - - - VSIE - Vertical synchronization interrupt enablee - - 3 - 1 - - - ESEIE - Embedded synchronization error interrupt - enable - 2 - 1 - - - OVRIE - Data FIFO overrun interrupt enable - - 1 - 1 - - - CFDIE - Capture frame done interrupt enable - - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-only - 0x0000 - - - HSIS - Horizontal synchronization interrupt - status - 4 - 1 - - - VSIS - Vertical synchronization interrupt - status - 3 - 1 - - - ESEIS - Embedded synchronization error - interrupt status - 2 - 1 - - - OVRIS - Data FIFO overrun interrupt - status - 1 - 1 - - - CFDIS - Capture frame done interrupt - status - 0 - 1 - - - - - ICLR - ICLR - Interrupt clear register - 0x14 - 0x20 - write-only - 0x0000 - - - HSIC - Horizontal synchronization - interrupt clear - 4 - 1 - - - VSIC - Vertical synchronization - interrupt clear - 3 - 1 - - - ESEIC - Embedded synchronization - error interrupt clear - 2 - 1 - - - OVRIC - Data FIFO overrun - interrupt clear - 1 - 1 - - - CFDIC - Capture frame done - interrupt clear - 0 - 1 - - - - - SCR - SCR - Synchronization code - register - 0x18 - 0x20 - read-write - 0x0000 - - - FMEC - Frame end code - 24 - 8 - - - LNEC - Line end code - 16 - 8 - - - LNSC - Line start code - 8 - 8 - - - FMSC - Frame start code - 0 - 8 - - - - - SUR - SUR - Synchronization unmask - register - 0x1C - 0x20 - read-write - 0x0000 - - - FMEU - Frame end unmask - 24 - 8 - - - LNEU - Line end unmask - 16 - 8 - - - LNSU - Line start unmask - - 8 - 8 - - - FMSU - Frame start unmask - - 0 - 8 - - - - - CWST - CWST - Crop window start - 0x20 - 0x20 - read-write - 0x0000 - - - CVSTR - Cropping window vertical start line - - 16 - 13 - - - CHSTR - Cropping window horizontal start pixel - - 0 - 14 - - - - - CWSZ - CWSZ - Crop window size - 0x24 - 0x20 - read-write - 0x0000 - - - CVNUM - Cropping window vertical line number - - 16 - 14 - - - CHNUM - Cropping window horizontal pixel number - - 0 - 14 - - - - - DT - DT - Data register - 0x28 - 0x20 - read-only - 0x0000 - - - DT - Data Port - 0 - 32 - - - - - ACTRL - ACTRL - Advanced Control register - - 0x40 - 0x20 - read-write - 0x0000 - - - VSEID - Vertical synchonization event and interrupt - definition - 17 - 1 - - - HSEID - Horizontal synchonization event and interrupt - definition - 16 - 1 - - - DMABT - DMA burst transfer configuration - - 12 - 1 - - - IDUS - Input data un-used setting - - 10 - 1 - - - IDUN - Input data un-used number - - 8 - 2 - - - EFDM - Enhanced function data format management - - 6 - 1 - - - EFDF - Enhanced function data format - - 4 - 2 - - - PCDES - Basic pixel capture/drop extended - selection - 3 - 1 - - - MIBE - Monochrome image binarization - enable - 2 - 1 - - - EFRCE - Enhanced frame rate control - enable - 1 - 1 - - - EISRE - Enhanced image scaling resize - enable - 0 - 1 - - - - - HSCF - HSCF - Horizontal scaling control flow - - 0x48 - 0x20 - read-write - 0x0000 - - - HSRTF - Horizontal scaling resize target factor - - 16 - 13 - - - HSRSF - Horizontal scaling resize source factor - - 0 - 13 - - - - - VSCF - VSCF - Vertical scaling control flow - - 0x4C - 0x20 - read-write - 0x0000 - - - VSRTF - Vertical scaling resize target factor - - 16 - 13 - - - VSRSF - Vertical scaling resize source factor - - 0 - 13 - - - - - FRF - FRF - Frame rate flow - - 0x50 - 0x20 - read-write - 0x0000 - - - EFRCTF - Enhanced frame rate control target factor - - 8 - 5 - - - EFRCSF - Enhanced frame rate contorl source factor - - 0 - 5 - - - - - BTH - BTH - Binarization threshold - - 0x54 - 0x20 - read-write - 0x0000 - - - MIBTHD - Monochrome image binarization threshold - - 0 - 8 - - - - - - - USB_OTGFS_GLOBAL - USB on-the-go full speed - USB_OTGFS - 0x50000000 - - 0x0 - 0x400 - registers - - - OTGFS - USB On The Go FS global - interrupt - 67 - - - - GOTGCTL - GOTGCTL - OTGFS control and status register - (OTGFS_GOTGCTL) - 0x0 - 0x20 - 0x00000800 - - - CONIDSTS - Connector ID status - 16 - 1 - read-only - - - CURMOD - Current Mode of Operation - 21 - 1 - read-only - - - - - GOTGINT - GOTGINT - OTGFS interrupt register - (OTGFS_GOTGINT) - 0x4 - 0x20 - 0x00000000 - - - SESENDDET - VBUS is deasserted - 2 - 1 - read-write - - - - - GAHBCFG - GAHBCFG - OTGFS AHB configuration register - (OTGFS_GAHBCFG) - 0x8 - 0x20 - read-write - 0x00000000 - - - GLBINTMSK - Global interrupt mask - 0 - 1 - - - NPTXFEMPLVL - Non-Periodic TxFIFO empty level - 7 - 1 - - - PTXFEMPLVL - Periodic TxFIFO empty - level - 8 - 1 - - - - - GUSBCFG - GUSBCFG - USB configuration register - (OTGFS_GUSBCFG) - 0xC - 0x20 - 0x00000A00 - - - TOUTCAL - FS timeout calibration - 0 - 3 - read-write - - - USBTRDTIM - USB turnaround time - 10 - 4 - read-write - - - FHSTMODE - Force host mode - 29 - 1 - read-write - - - FDEVMODE - Force device mode - 30 - 1 - read-write - - - COTXPKT - Corrupt Tx packet - 31 - 1 - read-write - - - - - GRSTCTL - GRSTCTL - OTGFS reset register - (OTGFS_GRSTCTL) - 0x10 - 0x20 - 0x20000000 - - - CSFTRST - Core soft reset - 0 - 1 - read-write - - - PIUSFTRST - PIU FS Dedicated Controller Soft Reset - 1 - 1 - read-write - - - FRMCNTRST - Host frame counter reset - 2 - 1 - read-write - - - RXFFLSH - RxFIFO flush - 4 - 1 - read-write - - - TXFFLSH - TxFIFO flush - 5 - 1 - read-write - - - TXFNUM - TxFIFO number - 6 - 5 - read-write - - - AHBIDLE - AHB master idle - 31 - 1 - read-only - - - - - GINTSTS - GINTSTS - OTGFS core interrupt register - (OTGFS_GINTSTS) - 0x14 - 0x20 - 0x04000020 - - - CURMOD - Current mode of operation - 0 - 1 - read-only - - - MODEMIS - Mode mismatch interrupt - 1 - 1 - read-write - - - OTGINT - OTG interrupt - 2 - 1 - read-only - - - SOF - Start of frame - 3 - 1 - read-write - - - RXFLVL - RxFIFO non-empty - 4 - 1 - read-only - - - NPTXFEMP - Non-periodic TxFIFO empty - 5 - 1 - read-only - - - GINNAKEFF - Global IN non-periodic NAK - effective - 6 - 1 - read-only - - - GOUTNAKEFF - Global OUT NAK effective - 7 - 1 - read-only - - - ERLYSUSP - Early suspend - 10 - 1 - read-write - - - USBSUSP - USB suspend - 11 - 1 - read-write - - - USBRST - USB reset - 12 - 1 - read-write - - - ENUMDONE - Enumeration done - 13 - 1 - read-write - - - ISOOUTDROP - Isochronous OUT packet dropped - interrupt - 14 - 1 - read-write - - - EOPF - End of periodic frame - interrupt - 15 - 1 - read-write - - - IEPTINT - IN endpoint interrupt - 18 - 1 - read-only - - - OEPTINT - OUT endpoint interrupt - 19 - 1 - read-only - - - INCOMPISOIN - Incomplete isochronous IN - transfer - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUT - Incomplete periodic transfer(Host - mode)/Incomplete isochronous OUT transfer(Device - mode) - 21 - 1 - read-write - - - PRTINT - Host port interrupt - 24 - 1 - read-only - - - HCHINT - Host channels interrupt - 25 - 1 - read-only - - - PTXFEMP - Periodic TxFIFO empty - 26 - 1 - read-only - - - CONIDSCHG - Connector ID status change - 28 - 1 - read-write - - - DISCONINT - Disconnect detected - interrupt - 29 - 1 - read-write - - - WKUPINT - Resume/remote wakeup detected - interrupt - 31 - 1 - read-write - - - - - GINTMSK - GINTMSK - OTG_FS interrupt mask register - (OTG_FS_GINTMSK) - 0x18 - 0x20 - 0x00000000 - - - MODEMISMSK - Mode mismatch interrupt - mask - 1 - 1 - read-write - - - OTGINTMSK - OTG interrupt mask - 2 - 1 - read-write - - - SOFMSK - Start of frame mask - 3 - 1 - read-write - - - RXFLVLMSK - Receive FIFO non-empty - mask - 4 - 1 - read-write - - - NPTXFEMPMSK - Non-periodic TxFIFO empty - mask - 5 - 1 - read-write - - - GINNAKEFFMSK - Global non-periodic IN NAK effective - mask - 6 - 1 - read-write - - - GOUTNAKEFFMSK - Global OUT NAK effective - mask - 7 - 1 - read-write - - - ERLYSUSPMSK - Early suspend mask - 10 - 1 - read-write - - - USBSUSPMSK - USB suspend mask - 11 - 1 - read-write - - - USBRSTMSK - USB reset mask - 12 - 1 - read-write - - - ENUMDONEMSK - Enumeration done mask - 13 - 1 - read-write - - - ISOOUTDROPMSK - Isochronous OUT packet dropped interrupt - mask - 14 - 1 - read-write - - - EOPFMSK - End of periodic frame interrupt - mask - 15 - 1 - read-write - - - IEPTINTMSK - IN endpoints interrupt - mask - 18 - 1 - read-write - - - OEPTINTMSK - OUT endpoints interrupt - mask - 19 - 1 - read-write - - - INCOMISOINMSK - Incomplete isochronous IN transfer - mask - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUTMSK - Incomplete periodic transfer mask(Host - mode)/Incomplete isochronous OUT transfer mask(Device - mode) - 21 - 1 - read-write - - - PRTINTMSK - Host port interrupt mask - 24 - 1 - read-write - - - HCHINTMSK - Host channels interrupt - mask - 25 - 1 - read-write - - - PTXFEMPMSK - Periodic TxFIFO empty mask - 26 - 1 - read-write - - - CONIDSCHGMSK - Connector ID status change - mask - 28 - 1 - read-write - - - DISCONINTMSK - Disconnect detected interrupt - mask - 29 - 1 - read-write - - - WKUPINTMSK - Resume/remote wakeup detected interrupt - mask - 31 - 1 - read-write - - - - - GRXSTSR_Device - GRXSTSR_Device - OTGFS Receive status debug read(Device - mode) - 0x1C - 0x20 - read-only - 0x00000000 - - - EPTNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - FN - Frame number - 21 - 4 - - - - - GRXSTSR_Host - GRXSTSR_Host - OTGFS Receive status debug read(Host - mode) - GRXSTSR_Device - 0x1C - 0x20 - read-only - 0x00000000 - - - CHNUM - Channel number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - - - GRXFSIZ - GRXFSIZ - OTGFS Receive FIFO size register - (OTGFS_GRXFSIZ) - 0x24 - 0x20 - read-write - 0x00000200 - - - RXFDEP - RxFIFO depth - 0 - 16 - - - - - DIEPTXF0 - DIEPTXF0 - IN Endpoint TxFIFO 0 transmit FIFO size - register (Device mode) - 0x28 - 0x20 - read-write - 0x00000200 - - - INEPT0TXSTADDR - Endpoint 0 transmit RAM start - address - 0 - 16 - - - INEPT0TXDEP - Endpoint 0 TxFIFO depth - 16 - 16 - - - - - GNPTXFSIZ - GNPTXFSIZ - OTGFS non-periodic transmit FIFO size - register (Host mode) - DIEPTXF0 - 0x28 - 0x20 - read-write - 0x00000200 - - - NPTXFSTADDR - Non-periodic Transmit RAM Start - address - 0 - 16 - - - NPTXFDEP - Non-periodic TxFIFO depth - 16 - 16 - - - - - GNPTXSTS - GNPTXSTS - OTGFS non-periodic transmit FIFO/queue - status register (OTGFS_GNPTXSTS) - 0x2C - 0x20 - read-only - 0x00080200 - - - NPTXFSPCAVAIL - Non-periodic TxFIFO space - available - 0 - 16 - - - NPTXQSPCAVAIL - Non-periodic transmit request queue - space available - 16 - 8 - - - NPTXQTOP - Top of the non-periodic transmit request - queue - 24 - 7 - - - - - GCCFG - GCCFG - OTGFS general core configuration register - (OTGFS_GCCFG) - 0x38 - 0x20 - read-write - 0x00000000 - - - PWRDOWN - Power down - 16 - 1 - - - LP_MODE - Low power mode - 17 - 1 - - - SOFOUTEN - SOF output enable - 20 - 1 - - - VBUSIG - VBUS Ignored - 21 - 1 - - - - - GUID - GUID - Product ID register - 0x3C - 0x20 - read-write - 0x00001000 - - - USERID - Product ID field - 0 - 32 - - - - - HPTXFSIZ - HPTXFSIZ - OTGFS Host periodic transmit FIFO size - register (OTGFS_HPTXFSIZ) - 0x100 - 0x20 - read-write - 0x02000600 - - - PTXFSTADDR - Host periodic TxFIFO start - address - 0 - 16 - - - PTXFSIZE - Host periodic TxFIFO depth - 16 - 16 - - - - - DIEPTXF1 - DIEPTXF1 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF1) - 0x104 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO1 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF2 - DIEPTXF2 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF2) - 0x108 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO2 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF3 - DIEPTXF3 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF3) - 0x10C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO3 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF4 - DIEPTXF4 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF4) - 0x110 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO4 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF5 - DIEPTXF5 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF5) - 0x114 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO5 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF6 - DIEPTXF6 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF6) - 0x118 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO6 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF7 - DIEPTXF7 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF7) - 0x11C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO7 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - - - USB_OTG1_HOST - USB on the go full speed - USB_OTGFS - 0x50000400 - - 0x0 - 0x400 - registers - - - - HCFG - HCFG - OTGFS host configuration register - (OTGFS_HCFG) - 0x0 - 0x20 - 0x00000000 - - - FSLSPCLKSEL - FS/LS PHY clock select - 0 - 2 - read-write - - - FSLSSUPP - FS- and LS-only support - 2 - 1 - read-only - - - - - HFIR - HFIR - OTGFS Host frame interval - register - 0x4 - 0x20 - read-write - 0x0000EA60 - - - FRINT - Frame interval - 0 - 16 - - - - - HFNUM - HFNUM - OTGFS host frame number/frame time - remaining register (OTGFS_HFNUM) - 0x8 - 0x20 - read-only - 0x00003FFF - - - FRNUM - Frame number - 0 - 16 - - - FTREM - Frame time remaining - 16 - 16 - - - - - HPTXSTS - HPTXSTS - OTGFS_Host periodic transmit FIFO/queue - status register (OTGFS_HPTXSTS) - 0x10 - 0x20 - 0x00080100 - - - PTXFSPCAVAIL - Periodic transmit data FIFO space - available - 0 - 16 - read-write - - - PTXQSPCAVAIL - Periodic transmit request queue space - available - 16 - 8 - read-only - - - PTXQTOP - Top of the periodic transmit request - queue - 24 - 8 - read-only - - - - - HAINT - HAINT - OTGFS Host all channels interrupt - register - 0x14 - 0x20 - read-only - 0x00000000 - - - HAINT - Channel interrupts - 0 - 16 - - - - - HAINTMSK - HAINTMSK - OTGFS host all channels interrupt mask - register - 0x18 - 0x20 - read-write - 0x00000000 - - - HAINTMSK - Channel interrupt mask - 0 - 16 - - - - - HPRT - HPRT - OTGFS host port control and status register - (OTGFS_HPRT) - 0x40 - 0x20 - 0x00000000 - - - PRTCONSTS - Port connect status - 0 - 1 - read-only - - - PRTCONDET - Port connect detected - 1 - 1 - read-write - - - PRTENA - Port enable - 2 - 1 - read-write - - - PRTENCHNG - Port enable/disable change - 3 - 1 - read-write - - - PRTOVRCACT - Port overcurrent active - 4 - 1 - read-only - - - PRTOVRCCHNG - Port overcurrent change - 5 - 1 - read-write - - - PRTRES - Port resume - 6 - 1 - read-write - - - PRTSUSP - Port suspend - 7 - 1 - read-write - - - PRTRST - Port reset - 8 - 1 - read-write - - - PRTLNSTS - Port line status - 10 - 2 - read-only - - - PRTPWR - Port power - 12 - 1 - read-write - - - PRTTSTCTL - Port test control - 13 - 4 - read-write - - - PRTSPD - Port speed - 17 - 2 - read-only - - - - - HCCHAR0 - HCCHAR0 - OTGFS host channel-0 characteristics - register (OTGFS_HCCHAR0) - 0x100 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR1 - HCCHAR1 - OTGFS host channel-1 characteristics - register (OTGFS_HCCHAR1) - 0x120 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR2 - HCCHAR2 - OTGFS host channel-2 characteristics - register (OTGFS_HCCHAR2) - 0x140 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR3 - HCCHAR3 - OTGFS host channel-3 characteristics - register (OTGFS_HCCHAR3) - 0x160 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR4 - HCCHAR4 - OTGFS host channel-4 characteristics - register (OTGFS_HCCHAR4) - 0x180 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR5 - HCCHAR5 - OTGFS host channel-5 characteristics - register (OTGFS_HCCHAR5) - 0x1A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR6 - HCCHAR6 - OTGFS host channel-6 characteristics - register (OTGFS_HCCHAR6) - 0x1C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR7 - HCCHAR7 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR7) - 0x1E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR8 - HCCHAR8 - OTGFS host channel-8 characteristics - register (OTGFS_HCCHAR8) - 0x200 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR9 - HCCHAR9 - OTGFS host channel-9 characteristics - register (OTGFS_HCCHAR9) - 0x220 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR10 - HCCHAR10 - OTGFS host channel-10 characteristics - register (OTGFS_HCCHAR10) - 0x240 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR11 - HCCHAR11 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR11) - 0x260 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR12 - HCCHAR12 - OTGFS host channel-12 characteristics - register (OTGFS_HCCHAR12) - 0x280 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR13 - HCCHAR13 - OTGFS host channel-13 characteristics - register (OTGFS_HCCHAR13) - 0x2A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR14 - HCCHAR14 - OTGFS host channel-14 characteristics - register (OTGFS_HCCHAR14) - 0x2C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR15 - HCCHAR15 - OTGFS host channel-15 characteristics - register (OTGFS_HCCHAR15) - 0x2E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCINT0 - HCINT0 - OTGFS host channel-0 interrupt register - (OTGFS_HCINT0) - 0x108 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT1 - HCINT1 - OTG_FS host channel-1 interrupt register - (OTG_FS_HCINT1) - 0x128 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT2 - HCINT2 - OTGFS host channel-2 interrupt register - (OTGFS_HCINT2) - 0x148 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT3 - HCINT3 - OTGFS host channel-3 interrupt register - (OTGFS_HCINT3) - 0x168 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT4 - HCINT4 - OTGFS host channel-4 interrupt register - (OTGFS_HCINT4) - 0x188 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT5 - HCINT5 - OTGFS host channel-5 interrupt register - (OTGFS_HCINT5) - 0x1A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT6 - HCINT6 - OTGFS host channel-6 interrupt register - (OTGFS_HCINT6) - 0x1C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT7 - HCINT7 - OTGFS host channel-7 interrupt register - (OTGFS_HCINT7) - 0x1E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT8 - HCINT8 - OTGFS host channel-8 interrupt register - (OTGFS_HCINT8) - 0x208 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT9 - HCINT9 - OTGFS host channel-9 interrupt register - (OTGFS_HCINT9) - 0x228 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT10 - HCINT10 - OTGFS host channel-10 interrupt register - (OTGFS_HCINT10) - 0x248 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT11 - HCINT11 - OTGFS host channel-11 interrupt register - (OTGFS_HCINT11) - 0x268 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT12 - HCINT12 - OTGFS host channel-12 interrupt register - (OTGFS_HCINT12) - 0x288 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT13 - HCINT13 - OTGFS host channel-13 interrupt register - (OTGFS_HCINT13) - 0x2A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT14 - HCINT14 - OTGFS host channel-14 interrupt register - (OTGFS_HCINT14) - 0x2C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT15 - HCINT15 - OTGFS host channel-15 interrupt register - (OTGFS_HCINT15) - 0x2E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINTMSK0 - HCINTMSK0 - OTGFS host channel-0 mask register - (OTGFS_HCINTMSK0) - 0x10C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK1 - HCINTMSK1 - OTGFS host channel-1 mask register - (OTGFS_HCINTMSK1) - 0x12C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK2 - HCINTMSK2 - OTGFS host channel-2 mask register - (OTGFS_HCINTMSK2) - 0x14C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK3 - HCINTMSK3 - OTGFS host channel-3 mask register - (OTGFS_HCINTMSK3) - 0x16C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK4 - HCINTMSK4 - OTGFS host channel-4 mask register - (OTGFS_HCINTMSK4) - 0x18C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK5 - HCINTMSK5 - OTGFS host channel-5 mask register - (OTGFS_HCINTMSK5) - 0x1AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK6 - HCINTMSK6 - OTGFS host channel-6 mask register - (OTGFS_HCINTMSK6) - 0x1CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK7 - HCINTMSK7 - OTGFS host channel-7 mask register - (OTGFS_HCINTMSK7) - 0x1EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK8 - HCINTMSK8 - OTGFS host channel-8 mask register - (OTGFS_HCINTMSK8) - 0x20C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK9 - HCINTMSK9 - OTGFS host channel-9 mask register - (OTGFS_HCINTMSK9) - 0x22C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK10 - HCINTMSK10 - OTGFS host channel-10 mask register - (OTGFS_HCINTMSK10) - 0x24C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK11 - HCINTMSK11 - OTGFS host channel-11 mask register - (OTGFS_HCINTMSK11) - 0x26C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK12 - HCINTMSK12 - OTGFS host channel-12 mask register - (OTGFS_HCINTMSK12) - 0x28C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK13 - HCINTMSK13 - OTGFS host channel-13 mask register - (OTGFS_HCINTMSK13) - 0x2AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK14 - HCINTMSK14 - OTGFS host channel-14 mask register - (OTGFS_HCINTMSK14) - 0x2CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK15 - HCINTMSK15 - OTGFS host channel-15 mask register - (OTGFS_HCINTMSK15) - 0x2EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCTSIZ0 - HCTSIZ0 - OTGFS host channel-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ1 - HCTSIZ1 - OTGFS host channel-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ2 - HCTSIZ2 - OTGFS host channel-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ3 - HCTSIZ3 - OTGFS host channel-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ4 - HCTSIZ4 - OTGFS host channel-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ5 - HCTSIZ5 - OTGFS host channel-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ6 - HCTSIZ6 - OTGFS host channel-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ7 - HCTSIZ7 - OTGFS host channel-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ8 - HCTSIZ8 - OTGFS host channel-8 transfer size - register - 0x210 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ9 - HCTSIZ9 - OTGFS host channel-9 transfer size - register - 0x230 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ10 - HCTSIZ10 - OTGFS host channel-10 transfer size - register - 0x250 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ11 - HCTSIZ11 - OTGFS host channel-11 transfer size - register - 0x270 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ12 - HCTSIZ12 - OTGFS host channel-12 transfer size - register - 0x290 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ13 - HCTSIZ13 - OTGFS host channel-13 transfer size - register - 0x2B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ14 - HCTSIZ14 - OTGFS host channel-14 transfer size - register - 0x2D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ15 - HCTSIZ15 - OTGFS host channel-15 transfer size - register - 0x2F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - - - USB_OTG1_DEVICE - USB on the go full speed - USB_OTGFS - 0x50000800 - - 0x0 - 0x400 - registers - - - - DCFG - DCFG - OTGFS device configuration register - (OTGFS_DCFG) - 0x0 - 0x20 - read-write - 0x02200000 - - - DEVSPD - Device speed - 0 - 2 - - - NZSTSOUTHSHK - Non-zero-length status OUT - handshake - 2 - 1 - - - DEVADDR - Device address - 4 - 7 - - - PERFRINT - Periodic frame interval - 11 - 2 - - - - - DCTL - DCTL - OTGFS device control register - (OTGFS_DCTL) - 0x4 - 0x20 - 0x00000000 - - - RWKUPSIG - Remote wakeup signaling - 0 - 1 - read-write - - - SFTDISCON - Soft disconnect - 1 - 1 - read-write - - - GNPINNAKSTS - Global IN NAK status - 2 - 1 - read-only - - - GOUTNAKSTS - Global OUT NAK status - 3 - 1 - read-only - - - TSTCTL - Test control - 4 - 3 - read-write - - - SGNPINNAK - Set global IN NAK - 7 - 1 - read-write - - - CGNPINNAK - Clear global IN NAK - 8 - 1 - read-write - - - SGOUTNAK - Set global OUT NAK - 9 - 1 - read-write - - - CGOUTNAK - Clear global OUT NAK - 10 - 1 - read-write - - - PWROPRGDNE - Power-on programming done - 11 - 1 - read-write - - - - - DSTS - DSTS - OTGFS device status register - (OTGFS_DSTS) - 0x8 - 0x20 - read-only - 0x00000010 - - - SUSPSTS - Suspend status - 0 - 1 - - - ENUMSPD - Enumerated speed - 1 - 2 - - - ETICERR - Erratic error - 3 - 1 - - - SOFFN - Frame number of the received - SOF - 8 - 14 - - - - - DIEPMSK - DIEPMSK - OTGFS device IN endpoint common interrupt - mask register (OTGFS_DIEPMSK) - 0x10 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - TIMEOUTMSK - Timeout condition mask (Non-isochronous - endpoints) - 3 - 1 - - - INTKNTXFEMPMSK - IN token received when TxFIFO empty - mask - 4 - 1 - - - INTKNEPTMISMSK - IN token received with EP mismatch - mask - 5 - 1 - - - INEPTNAKMSK - IN endpoint NAK effective - mask - 6 - 1 - - - TXFIFOUDRMSK - FIFO underrun - mask - 8 - 1 - - - BNAINMSK - BNA interrupt - mask - 9 - 1 - - - - - DOEPMSK - DOEPMSK - OTGFS device OUT endpoint common interrupt - mask register (OTGFS_DOEPMSK) - 0x14 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - SETUPMSK - SETUP phase done mask - 3 - 1 - - - OUTTEPDMSK - OUT token received when endpoint - disabled mask - 4 - 1 - - - B2BSETUPMSK - Back-to-back SETUP packets - received mask - 6 - 1 - - - OUTPERRMSK - OUT packet error - mask - 8 - 1 - - - BNAOUTMSK - BNA interrupt - mask - 9 - 1 - - - - - DAINT - DAINT - OTGFS device all endpoints interrupt - register (OTGFS_DAINT) - 0x18 - 0x20 - read-only - 0x00000000 - - - INEPTINT - IN endpoint interrupt bits - 0 - 16 - - - OUTEPTINT - OUT endpoint interrupt - bits - 16 - 16 - - - - - DAINTMSK - DAINTMSK - OTGFS all endpoints interrupt mask register - (OTGFS_DAINTMSK) - 0x1C - 0x20 - read-write - 0x00000000 - - - INEPTMSK - IN EP interrupt mask bits - 0 - 16 - - - OUTEPTMSK - OUT endpoint interrupt - bits - 16 - 16 - - - - - DIEPEMPMSK - DIEPEMPMSK - OTGFS device IN endpoint FIFO empty - interrupt mask register - 0x34 - 0x20 - read-write - 0x00000000 - - - INEPTXFEMSK - IN EP Tx FIFO empty interrupt mask - bits - 0 - 16 - - - - - DIEPCTL0 - DIEPCTL0 - OTGFS device control IN endpoint 0 control - register (OTGFS_DIEPCTL0) - 0x100 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 2 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-only - - - EPTENA - Endpoint enable - 31 - 1 - read-only - - - - - DIEPCTL1 - DIEPCTL1 - OTGFS device IN endpoint-1 control - register - 0x120 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL2 - DIEPCTL2 - OTGFS device IN endpoint-2 control - register - 0x140 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL3 - DIEPCTL3 - OTGFS device IN endpoint-3 control - register - 0x160 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL4 - DIEPCTL4 - OTGFS device IN endpoint-4 control - register - 0x180 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL5 - DIEPCTL5 - OTGFS device IN endpoint-5 control - register - 0x1A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL6 - DIEPCTL6 - OTGFS device IN endpoint-6 control - register - 0x1C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL7 - DIEPCTL7 - OTGFS device IN endpoint-7 control - register - 0x1E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL0 - DOEPCTL0 - OTGFS device OUT endpoint-0 control - register - 0x300 - 0x20 - 0x00008000 - - - MPS - Maximum packet size - 0 - 2 - read-only - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL1 - DOEPCTL1 - OTGFS device OUT endpoint-1 control - register - 0x320 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL2 - DOEPCTL2 - OTGFS device OUT endpoint-2 control - register - 0x340 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL3 - DOEPCTL3 - OTGFS device OUT endpoint-3 control - register - 0x360 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL4 - DOEPCTL4 - OTGFS device OUT endpoint-4 control - register - 0x380 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL5 - DOEPCTL5 - OTGFS device OUT endpoint-5 control - register - 0x3A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL6 - DOEPCTL6 - OTGFS device OUT endpoint-6 control - register - 0x3C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL7 - DOEPCTL7 - OTGFS device OUT endpoint-7 control - register - 0x3E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPINT0 - DIEPINT0 - OTGFS device IN endpoint-0 interrupt - register - 0x108 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT1 - DIEPINT1 - OTGFS device IN endpoint-1 interrupt - register - 0x128 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT2 - DIEPINT2 - OTGFS device IN endpoint-2 interrupt - register - 0x148 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT3 - DIEPINT3 - OTGFS device IN endpoint-3 interrupt - register - 0x168 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT4 - DIEPINT4 - OTGFS device IN endpoint-4 interrupt - register - 0x188 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT5 - DIEPINT5 - OTGFS device IN endpoint-5 interrupt - register - 0x1A8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT6 - DIEPINT6 - OTGFS device IN endpoint-6 interrupt - register - 0x1C8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT7 - DIEPINT7 - OTGFS device IN endpoint-7 interrupt - register - 0x1E8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DOEPINT0 - DOEPINT0 - OTGFS device OUT endpoint-0 interrupt - register - 0x308 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT1 - DOEPINT1 - OTGFS device OUT endpoint-1 interrupt - register - 0x328 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT2 - DOEPINT2 - OTGFS device OUT endpoint-2 interrupt - register - 0x348 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT3 - DOEPINT3 - OTGFS device OUT endpoint-3 interrupt - register - 0x368 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT4 - DOEPINT4 - OTGFS device OUT endpoint-4 interrupt - register - 0x388 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT5 - DOEPINT5 - OTGFS device OUT endpoint-5 interrupt - register - 0x3A8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT6 - DOEPINT6 - OTGFS device OUT endpoint-6 interrupt - register - 0x3C8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT7 - DOEPINT7 - OTGFS device OUT endpoint-7 interrupt - register - 0x3E8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DIEPTSIZ0 - DIEPTSIZ0 - OTGFS device IN endpoint-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 2 - - - - - DOEPTSIZ0 - DOEPTSIZ0 - OTGFS device OUT endpoint-0 transfer size - register - 0x310 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 1 - - - SETUPCNT - SETUP packet count - 29 - 2 - - - - - DIEPTSIZ1 - DIEPTSIZ1 - OTGFS device IN endpoint-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ2 - DIEPTSIZ2 - OTGFS device IN endpoint-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ3 - DIEPTSIZ3 - OTG device IN endpoint-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ4 - DIEPTSIZ4 - OTG device IN endpoint-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ5 - DIEPTSIZ5 - OTG device IN endpoint-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ6 - DIEPTSIZ6 - OTG device IN endpoint-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ7 - DIEPTSIZ7 - OTG device IN endpoint-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DTXFSTS0 - DTXFSTS0 - OTGFS device IN endpoint-0 transmit FIFO - status register - 0x118 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS1 - DTXFSTS1 - OTGFS device IN endpoint-1 transmit FIFO - status register - 0x138 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS2 - DTXFSTS2 - OTGFS device IN endpoint-2 transmit FIFO - status register - 0x158 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS3 - DTXFSTS3 - OTGFS device IN endpoint-3 transmit FIFO - status register - 0x178 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS4 - DTXFSTS4 - OTGFS device IN endpoint-4 transmit FIFO - status register - 0x198 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS5 - DTXFSTS5 - OTGFS device IN endpoint-5 transmit FIFO - status register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS6 - DTXFSTS6 - OTGFS device IN endpoint-6 transmit FIFO - status register - 0x1D8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS7 - DTXFSTS7 - OTGFS device IN endpoint-7 transmit FIFO - status register - 0x1F8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DOEPTSIZ1 - DOEPTSIZ1 - OTGFS device OUT endpoint-1 transfer size - register - 0x330 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ2 - DOEPTSIZ2 - OTGFS device OUT endpoint-2 transfer size - register - 0x350 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ3 - DOEPTSIZ3 - OTGFS device OUT endpoint-3 transfer size - register - 0x370 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ4 - DOEPTSIZ4 - OTGFS device OUT endpoint-4 transfer size - register - 0x390 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ5 - DOEPTSIZ5 - OTGFS device OUT endpoint-5 transfer size - register - 0x3B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ6 - DOEPTSIZ6 - OTGFS device OUT endpoint-6 transfer size - register - 0x3D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ7 - DOEPTSIZ7 - OTGFS device OUT endpoint-7 transfer size - register - 0x3F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - - - USB_OTG1_PWRCLK - USB on the go full speed - USB_OTGFS - 0x50000E00 - - 0x0 - 0x400 - registers - - - - PCGCCTL - PCGCCTL - OTGFS power and clock gating control - register (OTGFS_PCGCCTL) - 0x0 - 0x20 - 0x00000000 - - - STOPPCLK - Stop PHY clock - 0 - 1 - read-write - - - SUSPENDM - PHY Suspended - 4 - 1 - read-only - - - - - - - USB_OTGHS_GLOBAL - USB on the go high speed - USB_OTGHS - 0x40040000 - - 0x0 - 0x400 - registers - - - OTGHS - USB On The Go HS global - interrupt - 77 - - - - GOTGCTL - GOTGCTL - OTGHS control and status register - (OTGHS_GOTGCTL) - 0x0 - 0x20 - 0x00000800 - - - CONIDSTS - Connector ID status - 16 - 1 - read-only - - - CURMOD - Current Mode of Operation - 21 - 1 - read-only - - - - - GOTGINT - GOTGINT - OTGHS interrupt register - (OTGHS_GOTGINT) - 0x4 - 0x20 - 0x00000000 - - - SESENDDET - VBUS is deasserted - 2 - 1 - read-write - - - - - GAHBCFG - GAHBCFG - OTGHS AHB configuration register - (OTGHS_GAHBCFG) - 0x8 - 0x20 - read-write - 0x00000000 - - - GLBINTMSK - Global interrupt mask - 0 - 1 - - - HBSTLEN - Burst Length - 1 - 4 - - - DMAEN - DMA Enable - 5 - 1 - - - NPTXFEMPLVL - Non-Periodic TxFIFO empty level - 7 - 1 - - - PTXFEMPLVL - Periodic TxFIFO empty - level - 8 - 1 - - - - - GUSBCFG - GUSBCFG - USB configuration register - (OTGHS_GUSBCFG) - 0xC - 0x20 - 0x00000A00 - - - TOUTCAL - HS timeout calibration - 0 - 3 - read-write - - - PHYIF - PHY Interface - 3 - 1 - read-write - - - PHYSEL - USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial - Transceiver Select - 6 - 1 - read-write - - - USBTRDTIM - USB turnaround time - 10 - 4 - read-write - - - FHSTMODE - Force host mode - 29 - 1 - read-write - - - FDEVMODE - Force device mode - 30 - 1 - read-write - - - COTXPKT - Corrupt Tx packet - 31 - 1 - read-write - - - - - GRSTCTL - GRSTCTL - OTGHS reset register - (OTGHS_GRSTCTL) - 0x10 - 0x20 - 0x20000000 - - - CSFTRST - Core soft reset - 0 - 1 - read-write - - - PIUSFTRST - PIU FS Dedicated Controller Soft Reset - 1 - 1 - read-write - - - FRMCNTRST - Host frame counter reset - 2 - 1 - read-write - - - RXFFLSH - RxFIFO flush - 4 - 1 - read-write - - - TXFFLSH - TxFIFO flush - 5 - 1 - read-write - - - TXFNUM - TxFIFO number - 6 - 5 - read-write - - - DMAREQ - DMA Request Signal - 30 - 1 - read-only - - - AHBIDLE - AHB master idle - 31 - 1 - read-only - - - - - GINTSTS - GINTSTS - OTGHS core interrupt register - (OTGHS_GINTSTS) - 0x14 - 0x20 - 0x04000020 - - - CURMOD - Current mode of operation - 0 - 1 - read-only - - - MODEMIS - Mode mismatch interrupt - 1 - 1 - read-write - - - OTGINT - OTG interrupt - 2 - 1 - read-only - - - SOF - Start of frame - 3 - 1 - read-write - - - RXFLVL - RxFIFO non-empty - 4 - 1 - read-only - - - NPTXFEMP - Non-periodic TxFIFO empty - 5 - 1 - read-only - - - GINNAKEFF - Global IN non-periodic NAK - effective - 6 - 1 - read-only - - - GOUTNAKEFF - Global OUT NAK effective - 7 - 1 - read-only - - - ERLYSUSP - Early suspend - 10 - 1 - read-write - - - USBSUSP - USB suspend - 11 - 1 - read-write - - - USBRST - USB reset - 12 - 1 - read-write - - - ENUMDONE - Enumeration done - 13 - 1 - read-write - - - ISOOUTDROP - Isochronous OUT packet dropped - interrupt - 14 - 1 - read-write - - - EOPF - End of periodic frame - interrupt - 15 - 1 - read-write - - - IEPTINT - IN endpoint interrupt - 18 - 1 - read-only - - - OEPTINT - OUT endpoint interrupt - 19 - 1 - read-only - - - INCOMPISOIN - Incomplete isochronous IN - transfer - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUT - Incomplete periodic transfer(Host - mode)/Incomplete isochronous OUT transfer(Device - mode) - 21 - 1 - read-write - - - PRTINT - Host port interrupt - 24 - 1 - read-only - - - HCHINT - Host channels interrupt - 25 - 1 - read-only - - - PTXFEMP - Periodic TxFIFO empty - 26 - 1 - read-only - - - CONIDSCHG - Connector ID status change - 28 - 1 - read-write - - - DISCONINT - Disconnect detected - interrupt - 29 - 1 - read-write - - - WKUPINT - Resume/remote wakeup detected - interrupt - 31 - 1 - read-write - - - - - GINTMSK - GINTMSK - OTGHS interrupt mask register - (OTGHS_GINTMSK) - 0x18 - 0x20 - 0x00000000 - - - MODEMISMSK - Mode mismatch interrupt - mask - 1 - 1 - read-write - - - OTGINTMSK - OTG interrupt mask - 2 - 1 - read-write - - - SOFMSK - Start of frame mask - 3 - 1 - read-write - - - RXFLVLMSK - Receive FIFO non-empty - mask - 4 - 1 - read-write - - - NPTXFEMPMSK - Non-periodic TxFIFO empty - mask - 5 - 1 - read-write - - - GINNAKEFFMSK - Global non-periodic IN NAK effective - mask - 6 - 1 - read-write - - - GOUTNAKEFFMSK - Global OUT NAK effective - mask - 7 - 1 - read-write - - - ERLYSUSPMSK - Early suspend mask - 10 - 1 - read-write - - - USBSUSPMSK - USB suspend mask - 11 - 1 - read-write - - - USBRSTMSK - USB reset mask - 12 - 1 - read-write - - - ENUMDONEMSK - Enumeration done mask - 13 - 1 - read-write - - - ISOOUTDROPMSK - Isochronous OUT packet dropped interrupt - mask - 14 - 1 - read-write - - - EOPFMSK - End of periodic frame interrupt - mask - 15 - 1 - read-write - - - IEPTINTMSK - IN endpoints interrupt - mask - 18 - 1 - read-write - - - OEPTINTMSK - OUT endpoints interrupt - mask - 19 - 1 - read-write - - - INCOMISOINMSK - Incomplete isochronous IN transfer - mask - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUTMSK - Incomplete periodic transfer mask(Host - mode)/Incomplete isochronous OUT transfer mask(Device - mode) - 21 - 1 - read-write - - - PRTINTMSK - Host port interrupt mask - 24 - 1 - read-only - - - HCHINTMSK - Host channels interrupt - mask - 25 - 1 - read-write - - - PTXFEMPMSK - Periodic TxFIFO empty mask - 26 - 1 - read-write - - - CONIDSCHGMSK - Connector ID status change - mask - 28 - 1 - read-write - - - DISCONINTMSK - Disconnect detected interrupt - mask - 29 - 1 - read-write - - - WKUPINTMSK - Resume/remote wakeup detected interrupt - mask - 31 - 1 - read-write - - - - - GRXSTSR_Device - GRXSTSR_Device - OTGHS Receive status debug read(Device - mode) - 0x1C - 0x20 - read-only - 0x00000000 - - - EPTNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - FN - Frame number - 21 - 4 - - - - - GRXSTSR_Host - GRXSTSR_Host - OTGHS Receive status debug read(Host - mode) - GRXSTSR_Device - 0x1C - 0x20 - read-only - 0x00000000 - - - CHNUM - Channel number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - - - GRXFSIZ - GRXFSIZ - OTGHS Receive FIFO size register - (OTGHS_GRXFSIZ) - 0x24 - 0x20 - read-write - 0x00000200 - - - RXFDEP - RxFIFO depth - 0 - 16 - - - - - DIEPTXF0 - DIEPTXF0 - IN Endpoint TxFIFO 0 transmit FIFO size - register (Device mode) - 0x28 - 0x20 - read-write - 0x00000200 - - - INEPT0TXSTADDR - Endpoint 0 transmit RAM start - address - 0 - 16 - - - INEPT0TXDEP - Endpoint 0 TxFIFO depth - 16 - 16 - - - - - GNPTXFSIZ - GNPTXFSIZ - OTGHS non-periodic transmit FIFO size - register (Host mode) - DIEPTXF0 - 0x28 - 0x20 - read-write - 0x00000200 - - - NPTXFSTADDR - Non-periodic Transmit RAM Start - address - 0 - 16 - - - NPTXFDEP - Non-periodic TxFIFO depth - 16 - 16 - - - - - GNPTXSTS - GNPTXSTS - OTGHS non-periodic transmit FIFO/queue - status register (OTGHS_GNPTXSTS) - 0x2C - 0x20 - read-only - 0x00080200 - - - NPTXFSPCAVAIL - Non-periodic TxFIFO space - available - 0 - 16 - - - NPTXQSPCAVAIL - Non-periodic transmit request queue - space available - 16 - 8 - - - NPTXQTOP - Top of the non-periodic transmit request - queue - 24 - 7 - - - - - GCCFG - GCCFG - OTGHS general core configuration register - (OTGHS_GCCFG) - 0x38 - 0x20 - read-write - 0x00000000 - - - PWRDOWN - Power down - 16 - 1 - - - SOFOUTEN - SOF output enable - 20 - 1 - - - VBUSIG - VBUS Ignored - 21 - 1 - - - WAIT_CLK_RCV - Wait Clock Soure Recover - 22 - 1 - - - - - GUID - GUID - Product ID register - 0x3C - 0x20 - read-write - 0x00001000 - - - USERID - Product ID field - 0 - 32 - - - - - HPTXFSIZ - HPTXFSIZ - OTGHS Host periodic transmit FIFO size - register (OTGHS_HPTXFSIZ) - 0x100 - 0x20 - read-write - 0x02000600 - - - PTXFSTADDR - Host periodic TxFIFO start - address - 0 - 16 - - - PTXFSIZE - Host periodic TxFIFO depth - 16 - 16 - - - - - DIEPTXF1 - DIEPTXF1 - OTGHS device IN endpoint transmit FIFO size - register (OTGHS_DIEPTXF1) - 0x104 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO1 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF2 - DIEPTXF2 - OTGHS device IN endpoint transmit FIFO size - register (OTGHS_DIEPTXF2) - 0x108 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO2 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF3 - DIEPTXF3 - OTGHS device IN endpoint transmit FIFO size - register (OTGHS_DIEPTXF3) - 0x10C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO3 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF4 - DIEPTXF4 - OTGHS device IN endpoint transmit FIFO size - register (OTGHS_DIEPTXF4) - 0x110 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO4 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF5 - DIEPTXF5 - OTGHS device IN endpoint transmit FIFO size - register (OTGHS_DIEPTXF5) - 0x114 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO5 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF6 - DIEPTXF6 - OTGHS device IN endpoint transmit FIFO size - register (OTGHS_DIEPTXF6) - 0x118 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO6 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF7 - DIEPTXF7 - OTGHS device IN endpoint transmit FIFO size - register (OTGHS_DIEPTXF7) - 0x11C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO7 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - - - USB_OTGHS_HOST - USB on the go high speed - USB_OTGHS - 0x40040400 - - 0x0 - 0x400 - registers - - - - HCFG - HCFG - OTGHS host configuration register - (OTGHS_HCFG) - 0x0 - 0x20 - 0x00000000 - - - FSLSPCLKSEL - FS/LS PHY clock select - 0 - 2 - read-write - - - FSLSSUPP - FS- and LS-only support - 2 - 1 - read-only - - - - - HFIR - HFIR - OTGHS Host frame interval - register - 0x4 - 0x20 - read-write - 0x0000EA60 - - - FRINT - Frame interval - 0 - 16 - - - - - HFNUM - HFNUM - OTGHS host frame number/frame time - remaining register (OTGHS_HFNUM) - 0x8 - 0x20 - read-only - 0x00003FFF - - - FRNUM - Frame number - 0 - 16 - - - FTREM - Frame time remaining - 16 - 16 - - - - - HPTXSTS - HPTXSTS - OTGHS_Host periodic transmit FIFO/queue - status register (OTGHS_HPTXSTS) - 0x10 - 0x20 - 0x00080100 - - - PTXFSPCAVAIL - Periodic transmit data FIFO space - available - 0 - 16 - read-only - - - PTXQSPCAVAIL - Periodic transmit request queue space - available - 16 - 8 - read-only - - - PTXQTOP - Top of the periodic transmit request - queue - 24 - 8 - read-only - - - - - HAINT - HAINT - OTGHS Host all channels interrupt - register - 0x14 - 0x20 - read-only - 0x00000000 - - - HAINT - Channel interrupts - 0 - 16 - - - - - HAINTMSK - HAINTMSK - OTGHS host all channels interrupt mask - register - 0x18 - 0x20 - read-write - 0x00000000 - - - HAINTMSK - Channel interrupt mask - 0 - 16 - - - - - HPRT - HPRT - OTGHS host port control and status register - (OTGHS_HPRT) - 0x40 - 0x20 - 0x00000000 - - - PRTCONSTS - Port connect status - 0 - 1 - read-only - - - PRTCONDET - Port connect detected - 1 - 1 - read-write - - - PRTENA - Port enable - 2 - 1 - read-write - - - PRTENCHNG - Port enable/disable change - 3 - 1 - read-write - - - PRTOVRCACT - Port overcurrent active - 4 - 1 - read-only - - - PRTOVRCCHNG - Port overcurrent change - 5 - 1 - read-write - - - PRTRES - Port resume - 6 - 1 - read-write - - - PRTSUSP - Port suspend - 7 - 1 - read-write - - - PRTRST - Port reset - 8 - 1 - read-write - - - PRTLNSTS - Port line status - 10 - 2 - read-only - - - PRTPWR - Port power - 12 - 1 - read-write - - - PRTTSTCTL - Port test control - 13 - 4 - read-write - - - PRTSPD - Port speed - 17 - 2 - read-only - - - - - HCCHAR0 - HCCHAR0 - OTGHS host channel-0 characteristics - register (OTGHS_HCCHAR0) - 0x100 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR1 - HCCHAR1 - OTGHS host channel-1 characteristics - register (OTGHS_HCCHAR1) - 0x120 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR2 - HCCHAR2 - OTGHS host channel-2 characteristics - register (OTGHS_HCCHAR2) - 0x140 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR3 - HCCHAR3 - OTGHS host channel-3 characteristics - register (OTGHS_HCCHAR3) - 0x160 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR4 - HCCHAR4 - OTGHS host channel-4 characteristics - register (OTGHS_HCCHAR4) - 0x180 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR5 - HCCHAR5 - OTGHS host channel-5 characteristics - register (OTGHS_HCCHAR5) - 0x1A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR6 - HCCHAR6 - OTGHS host channel-6 characteristics - register (OTGHS_HCCHAR6) - 0x1C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR7 - HCCHAR7 - OTGHS host channel-7 characteristics - register (OTGHS_HCCHAR7) - 0x1E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR8 - HCCHAR8 - OTGHS host channel-8 characteristics - register (OTGHS_HCCHAR8) - 0x200 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR9 - HCCHAR9 - OTGHS host channel-9 characteristics - register (OTGHS_HCCHAR9) - 0x220 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR10 - HCCHAR10 - OTGHS host channel-10 characteristics - register (OTGHS_HCCHAR10) - 0x240 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR11 - HCCHAR11 - OTGHS host channel-7 characteristics - register (OTGHS_HCCHAR11) - 0x260 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR12 - HCCHAR12 - OTGHS host channel-12 characteristics - register (OTGHS_HCCHAR12) - 0x280 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR13 - HCCHAR13 - OTGHS host channel-13 characteristics - register (OTGHS_HCCHAR13) - 0x2A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR14 - HCCHAR14 - OTGHS host channel-14 characteristics - register (OTGHS_HCCHAR14) - 0x2C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR15 - HCCHAR15 - OTGHS host channel-15 characteristics - register (OTGHS_HCCHAR15) - 0x2E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCSPLT0 - HCSPLT0 - Host Channel 0 Split Control Register - 0x104 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT1 - HCSPLT1 - Host Channel 1 Split Control Register - 0x124 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT2 - HCSPLT2 - Host Channel 2 Split Control Register - 0x144 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT3 - HCSPLT3 - Host Channel 3 Split Control Register - 0x164 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT4 - HCSPLT4 - Host Channel 1 Split Control Register - 0x184 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT5 - HCSPLT5 - Host Channel 5 Split Control Register - 0x1A4 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT6 - HCSPLT6 - Host Channel 6 Split Control Register - 0x1C4 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT7 - HCSPLT7 - Host Channel 7 Split Control Register - 0x1E4 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT8 - HCSPLT8 - Host Channel 8 Split Control Register - 0x204 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT9 - HCSPLT9 - Host Channel 9 Split Control Register - 0x224 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT10 - HCSPLT10 - Host Channel 10 Split Control Register - 0x244 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT11 - HCSPLT11 - Host Channel 11 Split Control Register - 0x264 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT12 - HCSPLT12 - Host Channel 12 Split Control Register - 0x284 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT13 - HCSPLT13 - Host Channel 13 Split Control Register - 0x2A4 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT14 - HCSPLT14 - Host Channel 14 Split Control Register - 0x2C4 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT15 - HCSPLT15 - Host Channel 15 Split Control Register - 0x2E4 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCINT0 - HCINT0 - OTGHS host channel-0 interrupt register - (OTGHS_HCINT0) - 0x108 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT1 - HCINT1 - OTGHS host channel-1 interrupt register - (OTGHS_HCINT1) - 0x128 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT2 - HCINT2 - OTGHS host channel-2 interrupt register - (OTGHS_HCINT2) - 0x148 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT3 - HCINT3 - OTGHS host channel-3 interrupt register - (OTGHS_HCINT3) - 0x168 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT4 - HCINT4 - OTGHS host channel-4 interrupt register - (OTGHS_HCINT4) - 0x188 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT5 - HCINT5 - OTGHS host channel-5 interrupt register - (OTGHS_HCINT5) - 0x1A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT6 - HCINT6 - OTGHS host channel-6 interrupt register - (OTGHS_HCINT6) - 0x1C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT7 - HCINT7 - OTGHS host channel-7 interrupt register - (OTGHS_HCINT7) - 0x1E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT8 - HCINT8 - OTGHS host channel-8 interrupt register - (OTGHS_HCINT8) - 0x208 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT9 - HCINT9 - OTGHS host channel-9 interrupt register - (OTGHS_HCINT9) - 0x228 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT10 - HCINT10 - OTGHS host channel-10 interrupt register - (OTGHS_HCINT10) - 0x248 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT11 - HCINT11 - OTGHS host channel-11 interrupt register - (OTGHS_HCINT11) - 0x268 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT12 - HCINT12 - OTGHS host channel-12 interrupt register - (OTGHS_HCINT12) - 0x288 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT13 - HCINT13 - OTGHS host channel-13 interrupt register - (OTGHS_HCINT13) - 0x2A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT14 - HCINT14 - OTGHS host channel-14 interrupt register - (OTGHS_HCINT14) - 0x2C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT15 - HCINT15 - OTGHS host channel-15 interrupt register - (OTGHS_HCINT15) - 0x2E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINTMSK0 - HCINTMSK0 - OTGHS host channel-0 mask register - (OTGHS_HCINTMSK0) - 0x10C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK1 - HCINTMSK1 - OTGHS host channel-1 mask register - (OTGHS_HCINTMSK1) - 0x12C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK2 - HCINTMSK2 - OTGHS host channel-2 mask register - (OTGHS_HCINTMSK2) - 0x14C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK3 - HCINTMSK3 - OTGHS host channel-3 mask register - (OTGHS_HCINTMSK3) - 0x16C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK4 - HCINTMSK4 - OTGHS host channel-4 mask register - (OTGHS_HCINTMSK4) - 0x18C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK5 - HCINTMSK5 - OTGHS host channel-5 mask register - (OTGHS_HCINTMSK5) - 0x1AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK6 - HCINTMSK6 - OTGHS host channel-6 mask register - (OTGHS_HCINTMSK6) - 0x1CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK7 - HCINTMSK7 - OTGHS host channel-7 mask register - (OTGHS_HCINTMSK7) - 0x1EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK8 - HCINTMSK8 - OTGHS host channel-8 mask register - (OTGHS_HCINTMSK8) - 0x20C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK9 - HCINTMSK9 - OTGHS host channel-9 mask register - (OTGHS_HCINTMSK9) - 0x22C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK10 - HCINTMSK10 - OTGHS host channel-10 mask register - (OTGHS_HCINTMSK10) - 0x24C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK11 - HCINTMSK11 - OTGHS host channel-11 mask register - (OTGHS_HCINTMSK11) - 0x26C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK12 - HCINTMSK12 - OTGHS host channel-12 mask register - (OTGHS_HCINTMSK12) - 0x28C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK13 - HCINTMSK13 - OTGHS host channel-13 mask register - (OTGHS_HCINTMSK13) - 0x2AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK14 - HCINTMSK14 - OTGHS host channel-14 mask register - (OTGHS_HCINTMSK14) - 0x2CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK15 - HCINTMSK15 - OTGHS host channel-15 mask register - (OTGHS_HCINTMSK15) - 0x2EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCTSIZ0 - HCTSIZ0 - OTGHS host channel-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ1 - HCTSIZ1 - OTGHS host channel-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ2 - HCTSIZ2 - OTGHS host channel-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ3 - HCTSIZ3 - OTGHS host channel-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ4 - HCTSIZ4 - OTGHS host channel-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ5 - HCTSIZ5 - OTGHS host channel-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ6 - HCTSIZ6 - OTGHS host channel-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ7 - HCTSIZ7 - OTGHS host channel-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ8 - HCTSIZ8 - OTGHS host channel-8 transfer size - register - 0x210 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ9 - HCTSIZ9 - OTGHS host channel-9 transfer size - register - 0x230 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ10 - HCTSIZ10 - OTGHS host channel-10 transfer size - register - 0x250 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ11 - HCTSIZ11 - OTGHS host channel-11 transfer size - register - 0x270 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ12 - HCTSIZ12 - OTGHS host channel-12 transfer size - register - 0x290 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ13 - HCTSIZ13 - OTGHS host channel-13 transfer size - register - 0x2B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ14 - HCTSIZ14 - OTGHS host channel-14 transfer size - register - 0x2D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ15 - HCTSIZ15 - OTGHS host channel-15 transfer size - register - 0x2F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCDMA0 - HCDMA0 - Host channel 0 DMA address - register - 0x114 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA1 - HCDMA1 - Host channel 1 DMA address - register - 0x134 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA2 - HCDMA2 - Host channel 2 DMA address - register - 0x154 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA3 - HCDMA3 - Host channel 3 DMA address - register - 0x174 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA4 - HCDMA4 - Host channel 4 DMA address - register - 0x194 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA5 - HCDMA5 - Host channel 5 DMA address - register - 0x1B4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA6 - HCDMA6 - Host channel 6 DMA address - register - 0x1D4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA7 - HCDMA7 - Host channel 7 DMA address - register - 0x1F4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA8 - HCDMA8 - Host channel 8 DMA address - register - 0x214 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA9 - HCDMA9 - Host channel 9 DMA address - register - 0x234 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA10 - HCDMA10 - Host channel 10 DMA address - register - 0x254 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA11 - HCDMA11 - Host channel 11 DMA address - register - 0x274 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA12 - HCDMA12 - Host channel 12 DMA address - register - 0x294 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA13 - HCDMA13 - Host channel 13 DMA address - register - 0x2B4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA14 - HCDMA14 - Host channel 14 DMA address - register - 0x2D4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA15 - HCDMA15 - Host channel 15 DMA address - register - 0x2F4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - - - USB_OTGHS_DEVICE - USB on the go high speed - USB_OTGHS - 0x40040800 - - 0x0 - 0x400 - registers - - - - DCFG - DCFG - OTGHS device configuration register - (OTGHS_DCFG) - 0x0 - 0x20 - read-write - 0x02200000 - - - DEVSPD - Device speed - 0 - 2 - - - NZSTSOUTHSHK - Non-zero-length status OUT - handshake - 2 - 1 - - - DEVADDR - Device address - 4 - 7 - - - PERFRINT - Periodic frame interval - 11 - 2 - - - - - DCTL - DCTL - OTGHS device control register - (OTGHS_DCTL) - 0x4 - 0x20 - 0x00000000 - - - RWKUPSIG - Remote wakeup signaling - 0 - 1 - read-write - - - SFTDISCON - Soft disconnect - 1 - 1 - read-write - - - GNPINNAKSTS - Global IN NAK status - 2 - 1 - read-only - - - GOUTNAKSTS - Global OUT NAK status - 3 - 1 - read-only - - - TSTCTL - Test control - 4 - 3 - read-write - - - SGNPINNAK - Set global IN NAK - 7 - 1 - read-write - - - CGNPINNAK - Clear global IN NAK - 8 - 1 - read-write - - - SGOUTNAK - Set global OUT NAK - 9 - 1 - read-write - - - CGOUTNAK - Clear global OUT NAK - 10 - 1 - read-write - - - PWROPRGDNE - Power-on programming done - 11 - 1 - read-write - - - - - DSTS - DSTS - OTGFS device status register - (OTGFS_DSTS) - 0x8 - 0x20 - read-only - 0x00000010 - - - SUSPSTS - Suspend status - 0 - 1 - - - ENUMSPD - Enumerated speed - 1 - 2 - - - ETICERR - Erratic error - 3 - 1 - - - SOFFN - Frame number of the received - SOF - 8 - 14 - - - DEVLNSTS - Device Line Status - 22 - 2 - - - - - DIEPMSK - DIEPMSK - OTGHS device IN endpoint common interrupt - mask register (OTGHS_DIEPMSK) - 0x10 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - AHBERRMSK - AHB Error - mask - 2 - 1 - - - TIMEOUTMSK - Timeout condition mask (Non-isochronous - endpoints) - 3 - 1 - - - INTKNTXFEMPMSK - IN token received when TxFIFO empty - mask - 4 - 1 - - - INTKNEPTMISMSK - IN token received with EP mismatch - mask - 5 - 1 - - - INEPTNAKMSK - IN endpoint NAK effective - mask - 6 - 1 - - - TXFIFOUDRMSK - FIFO underrun - mask - 8 - 1 - - - BNAINMSK - BNA interrupt - mask - 9 - 1 - - - NAKMSK - NAK interrupt - mask - 13 - 1 - - - - - DOEPMSK - DOEPMSK - OTGHS device OUT endpoint common interrupt - mask register (OTGHS_DOEPMSK) - 0x14 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - AHBERRMSK - AHB Error - mask - 2 - 1 - - - SETUPMSK - SETUP phase done mask - 3 - 1 - - - OUTTEPDMSK - OUT token received when endpoint - disabled mask - 4 - 1 - - - STSPHSERCVDMSK - Status Phase Received - mask - 5 - 1 - - - B2BSETUPMSK - Back-to-back SETUP packets - received mask - 6 - 1 - - - OUTPERRMSK - OUT packet error - mask - 8 - 1 - - - BNAOUTMSK - BNA interrupt - mask - 9 - 1 - - - BBLEERRMSK - Babble Error interrupt - mask - 12 - 1 - - - NAKMSK - NAK interrupt - mask - 13 - 1 - - - NYETMSK - NYET interrupt - mask - 14 - 1 - - - - - DAINT - DAINT - OTGHS device all endpoints interrupt - register (OTGHS_DAINT) - 0x18 - 0x20 - read-only - 0x00000000 - - - INEPTINT - IN endpoint interrupt bits - 0 - 16 - - - OUTEPTINT - OUT endpoint interrupt - bits - 16 - 16 - - - - - DAINTMSK - DAINTMSK - OTGHS all endpoints interrupt mask register - (OTGHS_DAINTMSK) - 0x1C - 0x20 - read-write - 0x00000000 - - - INEPTMSK - IN EP interrupt mask bits - 0 - 16 - - - OUTEPTMSK - OUT endpoint interrupt - bits - 16 - 16 - - - - - DIEPEMPMSK - DIEPEMPMSK - OTGHS device IN endpoint FIFO empty - interrupt mask register - 0x34 - 0x20 - read-write - 0x00000000 - - - INEPTXFEMSK - IN EP Tx FIFO empty interrupt mask - bits - 0 - 16 - - - - - DEACHINT - DEACHINT - ODevice Each Endpoints - Interrupt Register - 0x38 - 0x20 - read-write - 0x00000000 - - - ECHINEPINT - Each IN Endpoint Interrupt - bits - 0 - 16 - - - ECHOUTEPINT - Each OUT Endpoint Interrupt - bits - 16 - 16 - - - - - DEACHINTMSK - DEACHINTMSK - Device Each Endpoints - Interrupt Mask Register - 0x3C - 0x20 - read-write - 0x00000000 - - - ECHINEPINTMSK - Each IN Endpoint Interrupt Mask - bits - 0 - 16 - - - ECHOUTEPINTMSK - Each OUT Endpoint Interrupt Mask - bits - 16 - 16 - - - - - DIEPEACHMSK1 - DIEPEACHMSK1 - Device Each IN Endpoint 1 Interrupt Register - 0x44 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - AHBERRMSK - AHB Error - mask - 2 - 1 - - - TIMEOUTMSK - Timeout condition mask (Non-isochronous - endpoints) - 3 - 1 - - - INTKNTXFEMPMSK - IN token received when TxFIFO empty - mask - 4 - 1 - - - INTKNEPTMISMSK - IN token received with EP mismatch - mask - 5 - 1 - - - INEPTNAKMSK - IN endpoint NAK effective - mask - 6 - 1 - - - TXFIFOUDRMSK - FIFO underrun - mask - 8 - 1 - - - BNAINMSK - BNA interrupt - mask - 9 - 1 - - - NAKMSK - NAK interrupt - mask - 13 - 1 - - - - - DOEPEACHMSK1 - DOEPEACHMSK1 - Device Each OUT Endpoint 1 Interrupt Register - 0x84 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - AHBERRMSK - AHB Error - mask - 2 - 1 - - - SETUPMSK - SETUP phase done mask - 3 - 1 - - - OUTTEPDMSK - OUT token received when endpoint - disabled mask - 4 - 1 - - - STSPHSERCVDMSK - Status Phase Received - mask - 5 - 1 - - - B2BSETUPMSK - Back-to-back SETUP packets - received mask - 6 - 1 - - - OUTPERRMSK - OUT packet error - mask - 8 - 1 - - - BNAOUTMSK - BNA interrupt - mask - 9 - 1 - - - BBLEERRMSK - Babble Error interrupt - mask - 12 - 1 - - - NAKMSK - NAK interrupt - mask - 13 - 1 - - - NYETMSK - NYET interrupt - mask - 14 - 1 - - - - - DIEPCTL0 - DIEPCTL0 - OTGHS device control IN endpoint 0 control - register (OTGHS_DIEPCTL0) - 0x100 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 2 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL1 - DIEPCTL1 - OTGHS device IN endpoint-1 control - register - 0x120 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL2 - DIEPCTL2 - OTGHS device IN endpoint-2 control - register - 0x140 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL3 - DIEPCTL3 - OTGHS device IN endpoint-3 control - register - 0x160 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL4 - DIEPCTL4 - OTGHS device IN endpoint-4 control - register - 0x180 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL5 - DIEPCTL5 - OTGHS device IN endpoint-5 control - register - 0x1A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL6 - DIEPCTL6 - OTGHS device IN endpoint-6 control - register - 0x1C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL7 - DIEPCTL7 - OTGHS device IN endpoint-7 control - register - 0x1E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL0 - DOEPCTL0 - OTGHS device OUT endpoint-0 control - register - 0x300 - 0x20 - 0x00008000 - - - MPS - Maximum packet size - 0 - 2 - read-only - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL1 - DOEPCTL1 - OTGHS device OUT endpoint-1 control - register - 0x320 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL2 - DOEPCTL2 - OTGHS device OUT endpoint-2 control - register - 0x340 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL3 - DOEPCTL3 - OTGHS device OUT endpoint-3 control - register - 0x360 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL4 - DOEPCTL4 - OTGHS device OUT endpoint-4 control - register - 0x380 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL5 - DOEPCTL5 - OTGHS device OUT endpoint-5 control - register - 0x3A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL6 - DOEPCTL6 - OTGHS device OUT endpoint-6 control - register - 0x3C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL7 - DOEPCTL7 - OTGHS device OUT endpoint-7 control - register - 0x3E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPINT0 - DIEPINT0 - OTGHS device IN endpoint-0 interrupt - register - 0x108 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - AHBERR - AHB Error - interrupt - 2 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - TXFIFOUNDRN - Fifo Underrun - 8 - 1 - read-write - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - - - DIEPINT1 - DIEPINT1 - OTGHS device IN endpoint-1 interrupt - register - 0x128 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - AHBERR - AHB Error - interrupt - 2 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - TXFIFOUNDRN - Fifo Underrun - 8 - 1 - read-write - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - - - DIEPINT2 - DIEPINT2 - OTGHS device IN endpoint-2 interrupt - register - 0x148 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - AHBERR - AHB Error - interrupt - 2 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - TXFIFOUNDRN - Fifo Underrun - 8 - 1 - read-write - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - - - DIEPINT3 - DIEPINT3 - OTGHS device IN endpoint-3 interrupt - register - 0x168 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - AHBERR - AHB Error - interrupt - 2 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - TXFIFOUNDRN - Fifo Underrun - 8 - 1 - read-write - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - - - DIEPINT4 - DIEPINT4 - OTGHS device IN endpoint-4 interrupt - register - 0x188 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - AHBERR - AHB Error - interrupt - 2 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - TXFIFOUNDRN - Fifo Underrun - 8 - 1 - read-write - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - - - DIEPINT5 - DIEPINT5 - OTGHS device IN endpoint-5 interrupt - register - 0x1A8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - AHBERR - AHB Error - interrupt - 2 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - TXFIFOUNDRN - Fifo Underrun - 8 - 1 - read-write - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - - - DIEPINT6 - DIEPINT6 - OTGHS device IN endpoint-6 interrupt - register - 0x1C8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - AHBERR - AHB Error - interrupt - 2 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - TXFIFOUNDRN - Fifo Underrun - 8 - 1 - read-write - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - - - DIEPINT7 - DIEPINT7 - OTGHS device IN endpoint-7 interrupt - register - 0x1E8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - AHBERR - AHB Error - interrupt - 2 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - TXFIFOUNDRN - Fifo Underrun - 8 - 1 - read-write - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - - - DOEPINT0 - DOEPINT0 - OTGHS device OUT endpoint-0 interrupt - register - 0x308 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - OUTPKTERR - OUT Packet Error - 8 - 1 - - - BNAINTR - Buffer Not Available Error - 9 - 1 - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - BBLEERR - BBLE error - 12 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - STUPPKTRCVD - Setup Packet Received - 15 - 1 - read-write - - - - - DOEPINT1 - DOEPINT1 - OTGHS device OUT endpoint-1 interrupt - register - 0x328 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - OUTPKTERR - OUT Packet Error - 8 - 1 - - - BNAINTR - Buffer Not Available Error - 9 - 1 - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - BBLEERR - BBLE error - 12 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - STUPPKTRCVD - Setup Packet Received - 15 - 1 - read-write - - - - - DOEPINT2 - DOEPINT2 - OTGHS device OUT endpoint-2 interrupt - register - 0x348 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - OUTPKTERR - OUT Packet Error - 8 - 1 - - - BNAINTR - Buffer Not Available Error - 9 - 1 - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - BBLEERR - BBLE error - 12 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - STUPPKTRCVD - Setup Packet Received - 15 - 1 - read-write - - - - - DOEPINT3 - DOEPINT3 - OTGHS device OUT endpoint-3 interrupt - register - 0x368 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - OUTPKTERR - OUT Packet Error - 8 - 1 - - - BNAINTR - Buffer Not Available Error - 9 - 1 - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - BBLEERR - BBLE error - 12 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - STUPPKTRCVD - Setup Packet Received - 15 - 1 - read-write - - - - - DOEPINT4 - DOEPINT4 - OTGHS device OUT endpoint-4 interrupt - register - 0x388 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - OUTPKTERR - OUT Packet Error - 8 - 1 - - - BNAINTR - Buffer Not Available Error - 9 - 1 - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - BBLEERR - BBLE error - 12 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - STUPPKTRCVD - Setup Packet Received - 15 - 1 - read-write - - - - - DOEPINT5 - DOEPINT5 - OTGHS device OUT endpoint-5 interrupt - register - 0x3A8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - OUTPKTERR - OUT Packet Error - 8 - 1 - - - BNAINTR - Buffer Not Available Error - 9 - 1 - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - BBLEERR - BBLE error - 12 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - STUPPKTRCVD - Setup Packet Received - 15 - 1 - read-write - - - - - DOEPINT6 - DOEPINT6 - OTGHS device OUT endpoint-6 interrupt - register - 0x3C8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - OUTPKTERR - OUT Packet Error - 8 - 1 - - - BNAINTR - Buffer Not Available Error - 9 - 1 - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - BBLEERR - BBLE error - 12 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - STUPPKTRCVD - Setup Packet Received - 15 - 1 - read-write - - - - - DOEPINT7 - DOEPINT7 - OTGHS device OUT endpoint-7 interrupt - register - 0x3E8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - OUTPKTERR - OUT Packet Error - 8 - 1 - - - BNAINTR - Buffer Not Available Error - 9 - 1 - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - BBLEERR - BBLE error - 12 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - STUPPKTRCVD - Setup Packet Received - 15 - 1 - read-write - - - - - DIEPTSIZ0 - DIEPTSIZ0 - OTGHS device IN endpoint-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 2 - - - - - DOEPTSIZ0 - DOEPTSIZ0 - OTGHS device OUT endpoint-0 transfer size - register - 0x310 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 1 - - - SETUPCNT - SETUP packet count - 29 - 2 - - - - - DIEPTSIZ1 - DIEPTSIZ1 - OTGHS device IN endpoint-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ2 - DIEPTSIZ2 - OTGHS device IN endpoint-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ3 - DIEPTSIZ3 - OTG device IN endpoint-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ4 - DIEPTSIZ4 - OTG device IN endpoint-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ5 - DIEPTSIZ5 - OTG device IN endpoint-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ6 - DIEPTSIZ6 - OTG device IN endpoint-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ7 - DIEPTSIZ7 - OTG device IN endpoint-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPDMA0 - DIEPDMA0 - Device IN Endpoint 0 DMA Address - register - 0x114 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DIEPDMA1 - DIEPDMA1 - Device IN Endpoint 1 DMA Address - register - 0x134 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DIEPDMA2 - DIEPDMA2 - Device IN Endpoint 2 DMA Address - register - 0x154 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DIEPDMA3 - DIEPDMA3 - Device IN Endpoint 3 DMA Address - register - 0x174 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DIEPDMA4 - DIEPDMA4 - Device IN Endpoint 4 DMA Address - register - 0x194 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DIEPDMA5 - DIEPDMA5 - Device IN Endpoint 5 DMA Address - register - 0x1B4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DIEPDMA6 - DIEPDMA6 - Device IN Endpoint 6 DMA Address - register - 0x1D4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DIEPDMA7 - DIEPDMA7 - Device IN Endpoint 7 DMA Address - register - 0x1F4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DTXFSTS0 - DTXFSTS0 - OTGHS device IN endpoint-0 transmit FIFO - status register - 0x118 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS1 - DTXFSTS1 - OTGHS device IN endpoint-1 transmit FIFO - status register - 0x138 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS2 - DTXFSTS2 - OTGHS device IN endpoint-2 transmit FIFO - status register - 0x158 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS3 - DTXFSTS3 - OTGHS device IN endpoint-3 transmit FIFO - status register - 0x178 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS4 - DTXFSTS4 - OTGHS device IN endpoint-4 transmit FIFO - status register - 0x198 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS5 - DTXFSTS5 - OTGHS device IN endpoint-5 transmit FIFO - status register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS6 - DTXFSTS6 - OTGHS device IN endpoint-6 transmit FIFO - status register - 0x1D8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS7 - DTXFSTS7 - OTGHS device IN endpoint-7 transmit FIFO - status register - 0x1F8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DOEPTSIZ1 - DOEPTSIZ1 - OTGHS device OUT endpoint-1 transfer size - register - 0x330 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ2 - DOEPTSIZ2 - OTGHS device OUT endpoint-2 transfer size - register - 0x350 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ3 - DOEPTSIZ3 - OTGHS device OUT endpoint-3 transfer size - register - 0x370 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ4 - DOEPTSIZ4 - OTGHS device OUT endpoint-4 transfer size - register - 0x390 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ5 - DOEPTSIZ5 - OTGHS device OUT endpoint-5 transfer size - register - 0x3B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ6 - DOEPTSIZ6 - OTGHS device OUT endpoint-6 transfer size - register - 0x3D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ7 - DOEPTSIZ7 - OTGHS device OUT endpoint-7 transfer size - register - 0x3F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPDMA0 - DOEPDMA0 - Device OUT Endpoint 0 DMA Address - register - 0x314 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DOEPDMA1 - DOEPDMA1 - Device OUT Endpoint 1 DMA Address - register - 0x334 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DOEPDMA2 - DOEPDMA2 - Device OUT Endpoint 2 DMA Address - register - 0x354 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DOEPDMA3 - DOEPDMA3 - Device OUT Endpoint 3 DMA Address - register - 0x374 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DOEPDMA4 - DOEPDMA4 - Device OUT Endpoint 4 DMA Address - register - 0x394 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DOEPDMA5 - DOEPDMA5 - Device OUT Endpoint 5 DMA Address - register - 0x3B4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DOEPDMA6 - DOEPDMA6 - Device OUT Endpoint 6 DMA Address - register - 0x3D4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DOEPDMA7 - DOEPDMA7 - Device OUT Endpoint 7 DMA Address - register - 0x3F4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - - - USB_OTGHS_PWRCLK - USB on the go high speed - USB_OTGHS - 0x40040E00 - - 0x0 - 0x400 - registers - - - - PCGCCTL - PCGCCTL - OTGHS power and clock gating control - register (OTGHS_PCGCCTL) - 0x0 - 0x20 - 0x00000000 - - - STOPPCLK - Stop PHY clock - 0 - 1 - read-write - - - SUSPENDM - PHY Suspended - 4 - 1 - read-only - - - - - - - SCFG - System configuration controller - SCFG - 0x40013800 - - 0x0 - 0x400 - registers - - - - CFG1 - CFG1 - configuration register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - MEM_MAP_SEL - Memory address mapping selection bits - 0 - 3 - - - IR_POL - IR output polarity selection - 5 - 1 - - - IR_SRC_SEL - IR signal source selection - 6 - 2 - - - - - CFG2 - CFG2 - configuration register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - LOCKUP_LK - CM4F LOCKUP bit enable - 0 - 1 - - - SRAM_OPERR_LK - SRAM odd parity error lock enable - 1 - 1 - - - PVM_LK - PVM lock enable - 2 - 1 - - - SRAM_OPERR_STS - SRAM odd parity error status - 8 - 1 - - - I2S_FD - I2S full duplex config - 30 - 2 - - - - - EXINTC1 - EXINTC1 - external interrupt configuration register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - EXINT3 - EXINT 3 configuration bits - 12 - 4 - - - EXINT2 - EXINT 2 configuration bits - 8 - 4 - - - EXINT1 - EXINT 1 configuration bits - 4 - 4 - - - EXINT0 - EXINT 0 configuration bits - 0 - 4 - - - - - EXINTC2 - EXINTC2 - external interrupt configuration register 2 - 0xC - 0x20 - read-write - 0x0000 - - - EXINT7 - EXINT 7 configuration bits - 12 - 4 - - - EXINT6 - EXINT 6 configuration bits - 8 - 4 - - - EXINT5 - EXINT 5 configuration bits - 4 - 4 - - - EXINT4 - EXINT 4 configuration bits - 0 - 4 - - - - - EXINTC3 - EXINTC3 - external interrupt configuration register 3 - 0x10 - 0x20 - read-write - 0x0000 - - - EXINT11 - EXINT 11 configuration bits - 12 - 4 - - - EXINT10 - EXINT 10 configuration bits - 8 - 4 - - - EXINT9 - EXINT 9 configuration bits - 4 - 4 - - - EXINT8 - EXINT 8 configuration bits - 0 - 4 - - - - - EXINTC4 - EXINTC4 - external interrupt configuration register - 4 - 0x14 - 0x20 - read-write - 0x0000 - - - EXINT15 - EXINT 15 configuration bits - 12 - 4 - - - EXINT14 - EXINT 14 configuration bits - 8 - 4 - - - EXINT13 - EXINT 13 configuration bits - 4 - 4 - - - EXINT12 - EXINT 12 configuration bits - 0 - 4 - - - - - UHDRV - UHDRV - Ultra high drive register - 0x2C - 0x20 - read-write - 0x0000 - - - PB10_UH - PB10 ultra high sourcing/sinking strength - 2 - 1 - - - PB9_UH - PB9 ultra high sourcing/sinking strength - 1 - 1 - - - PB3_UH - PB3 ultra high sourcing/sinking strength - 0 - 1 - - - - - - - QSPI1 - Quad SPI Controller - QSPI - 0xA0001000 - - 0x0 - 0x400 - registers - - - QSPI1 - QSPI1 global interrupt - 92 - - - - CMD_W0 - CMD_W0 - Command word 0 - 0x0 - 0x20 - read-write - 0x00000000 - - - SPIADR - SPI flash address - 0 - 32 - - - - - CMD_W1 - CMD_W1 - Command word 1 - 0x4 - 0x20 - read-write - 0x01000003 - - - ADRLEN - SPI address length - 0 - 3 - - - DUM2 - Second dummy state cycle - 16 - 8 - - - INSLEN - Instruction code length - 24 - 2 - - - PEMEN - Perfrmance enhance mode enable - 28 - 1 - - - - - CMD_W2 - CMD_W2 - Command word 2 - 0x8 - 0x20 - read-write - 0x01000003 - - - DCNT - Read write data counter - 0 - 32 - - - - - CMD_W3 - CMD_W3 - Command word 3 - 0xC - 0x20 - read-write - 0x00000000 - - - WEN - Write data enable - 1 - 1 - - - RSTSEN - Read spi status enable - 2 - 1 - - - RSTSC - Read spi status configure - 3 - 1 - - - OPMODE - SPI operate mode - 5 - 3 - - - PEMOPC - Performance enhance mode operate code - 16 - 8 - - - INSC - Instruction code - 24 - 8 - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00000000 - - - CLKDIV - SPI clock divider - 0 - 3 - - - SCKMODE - Sckout mode - 4 - 1 - - - XIPIDLE - XIP port idle status - 7 - 1 - - - ABORT - Abort instruction - 8 - 1 - - - BUSY - Busy bit of spi status - 16 - 3 - - - XIPRCMDF - XIP read command flush - 19 - 1 - - - XIPSEL - XIP port selection - 20 - 1 - - - KEYEN - encryption key enable - 21 - 1 - - - - - FIFOSTS - FIFOSTS - FIFO Status register - 0x18 - 0x20 - read-only - 0x00000001 - - - TXFIFORDY - TxFIFO ready status - 0 - 1 - - - RXFIFORDY - RxFIFO ready status - 1 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x20 - 0x20 - read-write - 0x00000001 - - - DMAEN - DMA handshake enable - 0 - 1 - - - CMDIE - Command complete interrupt enable - 1 - 1 - - - TXFIFOTHOD - TxFIFO thod - 8 - 2 - - - RXFIFOTHOD - RxFIFO thod - 12 - 2 - - - - - CMDSTS - CMDSTS - CMD status register - 0x24 - 0x20 - read-only - 0x00000000 - - - CMDSTS - Command complete status - 0 - 1 - - - - - RSTS - RSTS - SPI read status register - 0x28 - 0x20 - read-only - 0x00000000 - - - SPISTS - SPI read status - 0 - 8 - - - - - FSIZE - FSIZE - SPI flash size - 0x2C - 0x20 - read-write - 0x00000000 - - - SPIFSIZE - SPI flash size - 0 - 32 - - - - - XIP_CMD_W0 - XIP_CMD_W0 - XIP command word 0 - 0x30 - 0x20 - read-write - 0x00000000 - - - XIPR_DUM2 - XIP read second dummy cycle - 0 - 8 - - - XIPR_OPMODE - XIP read operate mode - 8 - 3 - - - XIPR_ADRLEN - XIP read address length - 11 - 1 - - - XIPR_INSC - XIP read instruction code - 12 - 8 - - - - - XIP_CMD_W1 - XIP_CMD_W1 - XIP command word 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - XIPW_DUM2 - XIP write second dummy cycle - 0 - 8 - - - XIPW_OPMODE - XIP write operate mode - 8 - 3 - - - XIPW_ADRLEN - XIP write address length - 11 - 1 - - - XIPW_INSC - XIP write instruction code - 12 - 8 - - - - - XIP_CMD_W2 - XIP_CMD_W2 - XIP command word 2 - 0x38 - 0x20 - read-write - 0x00000000 - - - XIPR_DCNT - XIP read data counter - 0 - 5 - - - XIPR_TCNT - XIP continue read cycle counter - 8 - 7 - - - XIPR_SEL - XIP read continue mode select - 15 - 1 - - - XIPW_DCNT - XIP write data counter - 16 - 5 - - - XIPW_TCNT - XIP continue write cycle counter - 24 - 7 - - - XIPW_SEL - XIP write continue mode select - 31 - 1 - - - - - XIP_CMD_W3 - XIP_CMD_W3 - XIP command word 3 - 0x3C - 0x20 - read-write - 0x00000000 - - - BYPASSC - Bypass cache function - 0 - 1 - - - CSTS - Cache status - 3 - 1 - - - - - REV - REV - Revision - 0x50 - 0x20 - read-write - 0x00010500 - - - REVISION - Revision number - 0 - 31 - - - - - DT - DT - 32/16/8 bit data port register - 0x100 - 0x20 - read-write - 0x00000000 - - - - - diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h index 9c07bf192..0061fd242 100644 --- a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h +++ b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h @@ -55,7 +55,7 @@ #define PRINT_UART_TX_PIN_SOURCE GPIO_PINS_SOURCE9 #define PRINT_UART_TX_PIN_MUX_NUM GPIO_MUX_7 -//USB +//USB #ifdef BOARD_TUD_RHPORT #if BOARD_TUD_RHPORT == 0 #define USB_ID USB_OTG1_ID diff --git a/hw/bsp/at32f402_405/family.c b/hw/bsp/at32f402_405/family.c index dd8e7de10..e6a3bce22 100644 --- a/hw/bsp/at32f402_405/family.c +++ b/hw/bsp/at32f402_405/family.c @@ -36,11 +36,11 @@ void usb_gpio_config(void); //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void OTGFS1_IRQHandler(void) +void OTGFS1_IRQHandler(void) { tusb_int_handler(0, true); } -void OTGHS_IRQHandler(void) +void OTGHS_IRQHandler(void) { tusb_int_handler(1, true); } @@ -53,7 +53,7 @@ void OTGHS_WKUP_IRQHandler(void) tusb_int_handler(1, true); } -void board_init(void) +void board_init(void) { /* config nvic priority group */ nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); @@ -94,7 +94,7 @@ void board_init(void) //--------------------------------------------------------------------+ // Board porting API //--------------------------------------------------------------------+ -void led_and_botton_init(void) +void led_and_botton_init(void) { /* LED */ gpio_init_type gpio_led_init_struct; @@ -217,7 +217,7 @@ int board_uart_write(void const *buf, int len) #if CFG_TUSB_OS == OPT_OS_NONE int txsize = len; u16 timeout = 0xffff; - while (txsize--) + while (txsize--) { while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) { @@ -238,17 +238,17 @@ int board_uart_write(void const *buf, int len) #endif } -void board_led_write(bool state) +void board_led_write(bool state) { gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); } -uint32_t board_button_read(void) +uint32_t board_button_read(void) { return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); } -size_t board_get_unique_id(uint8_t id[], size_t max_len) +size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); @@ -264,11 +264,11 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; - void SysTick_Handler(void) + void SysTick_Handler(void) { system_ticks++; } - uint32_t board_millis(void) + uint32_t board_millis(void) { return system_ticks; } @@ -280,7 +280,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) } #endif -void HardFault_Handler(void) +void HardFault_Handler(void) { __asm("BKPT #0\n"); } @@ -294,4 +294,3 @@ void assert_failed(const char *file, uint32_t line) /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ - diff --git a/hw/bsp/at32f402_405/family.mk b/hw/bsp/at32f402_405/family.mk index 9dbdb1a55..461264561 100644 --- a/hw/bsp/at32f402_405/family.mk +++ b/hw/bsp/at32f402_405/family.mk @@ -1,6 +1,5 @@ # Submodules AT32F402_405_SDK = hw/mcu/artery/at32f402_405 -DEPS_SUBMODULES += $(AT32F402_405_SDK) # AT32 SDK path AT32F402_405_SDK_SRC = $(AT32F402_405_SDK)/libraries diff --git a/hw/bsp/at32f402_405/startup_at32f402_405.s b/hw/bsp/at32f402_405/startup_at32f402_405.s index 251ec5058..9b0dad9ef 100644 --- a/hw/bsp/at32f402_405/startup_at32f402_405.s +++ b/hw/bsp/at32f402_405/startup_at32f402_405.s @@ -78,7 +78,7 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -104,7 +104,7 @@ Infinite_Loop: * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. -* +* *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object @@ -128,7 +128,7 @@ g_pfnVectors: .word 0 .word PendSV_Handler .word SysTick_Handler - + /* External Interrupts */ .word WWDT_IRQHandler /* Window Watchdog Timer */ .word PVM_IRQHandler /* PVM through EXINT Line detect */ @@ -237,20 +237,20 @@ g_pfnVectors: /******************************************************************************* * -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override * this definition. -* +* *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler - + .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler - + .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler - + .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler @@ -267,10 +267,10 @@ g_pfnVectors: .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - + .thumb_set SysTick_Handler,Default_Handler + .weak WWDT_IRQHandler - .thumb_set WWDT_IRQHandler,Default_Handler + .thumb_set WWDT_IRQHandler,Default_Handler .weak PVM_IRQHandler .thumb_set PVM_IRQHandler,Default_Handler @@ -294,7 +294,7 @@ g_pfnVectors: .thumb_set EXINT1_IRQHandler,Default_Handler .weak EXINT2_IRQHandler - .thumb_set EXINT2_IRQHandler,Default_Handler + .thumb_set EXINT2_IRQHandler,Default_Handler .weak EXINT3_IRQHandler .thumb_set EXINT3_IRQHandler,Default_Handler @@ -312,7 +312,7 @@ g_pfnVectors: .thumb_set DMA1_Channel3_IRQHandler,Default_Handler .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler .weak DMA1_Channel5_IRQHandler .thumb_set DMA1_Channel5_IRQHandler,Default_Handler @@ -479,7 +479,7 @@ g_pfnVectors: .weak QSPI1_IRQHandler .thumb_set QSPI1_IRQHandler,Default_Handler - .weak DMAMUX_IRQHandler + .weak DMAMUX_IRQHandler .thumb_set DMAMUX_IRQHandler ,Default_Handler .weak ACC_IRQHandler diff --git a/hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h index d63959c4e..a89d8c282 100644 --- a/hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h @@ -109,7 +109,7 @@ #define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 #define INCLUDE_uxTaskGetStackHighWaterMark 0 #define INCLUDE_xTaskGetIdleTaskHandle 0 #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 diff --git a/hw/bsp/at32f403a_407/at32f403a_407_clock.c b/hw/bsp/at32f403a_407/at32f403a_407_clock.c index 38b20c8a3..7a028cebd 100644 --- a/hw/bsp/at32f403a_407/at32f403a_407_clock.c +++ b/hw/bsp/at32f403a_407/at32f403a_407_clock.c @@ -84,4 +84,4 @@ void system_clock_config(void) /* update system_core_clock global variable */ system_core_clock_update(); -} \ No newline at end of file +} diff --git a/hw/bsp/at32f403a_407/at32f403a_407_clock.h b/hw/bsp/at32f403a_407/at32f403a_407_clock.h index bed47d7ea..ddedfa619 100644 --- a/hw/bsp/at32f403a_407/at32f403a_407_clock.h +++ b/hw/bsp/at32f403a_407/at32f403a_407_clock.h @@ -41,4 +41,3 @@ void system_clock_config(void); #endif #endif /* __AT32F403A_407_CLOCK_H */ - diff --git a/hw/bsp/at32f403a_407/at32f403a_407_conf.h b/hw/bsp/at32f403a_407/at32f403a_407_conf.h index 856f34fda..172e972d2 100644 --- a/hw/bsp/at32f403a_407/at32f403a_407_conf.h +++ b/hw/bsp/at32f403a_407/at32f403a_407_conf.h @@ -32,7 +32,7 @@ extern "C" { /** - * @brief in the following line adjust the value of high speed exernal crystal (hext) + * @brief in the following line adjust the value of high speed external crystal (hext) * used in your application * * tip: to avoid modifying this file each time you need to use different hext, you @@ -40,11 +40,11 @@ extern "C" { * */ #if !defined HEXT_VALUE -#define HEXT_VALUE ((uint32_t)8000000) /*!< value of the high speed exernal crystal in hz */ +#define HEXT_VALUE ((uint32_t)8000000) /*!< value of the high speed external crystal in hz */ #endif /** - * @brief in the following line adjust the high speed exernal crystal (hext) startup + * @brief in the following line adjust the high speed external crystal (hext) startup * timeout value */ #define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ diff --git a/hw/bsp/at32f403a_407/at32f403a_407_int.h b/hw/bsp/at32f403a_407/at32f403a_407_int.h index f82b6a499..6d85c70ca 100644 --- a/hw/bsp/at32f403a_407/at32f403a_407_int.h +++ b/hw/bsp/at32f403a_407/at32f403a_407_int.h @@ -53,4 +53,3 @@ void SysTick_Handler(void); #endif #endif - diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld index 00475df6f..c3d8aca80 100644 --- a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld +++ b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld @@ -104,7 +104,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -119,7 +119,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd deleted file mode 100644 index 323218b23..000000000 --- a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd +++ /dev/null @@ -1,28047 +0,0 @@ - - - - - - - - Keil - ArteryTek - AT32F407xx_v2 - AT32F407 - 1.0 - ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 200MHz, etc. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - CM4 - r0p1 - little - false - true - 4 - false - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - - XMC - Flexible static memory controller - XMC - 0xA0000000 - - 0x0 - 0x1000 - registers - - - XMC - XMC global interrupt - 48 - - - - BK1CTRL1 - BK1CTRL1 - SRAM/NOR-Flash chip-select control register - 1 - 0x0 - 0x20 - read-write - 0x000030DB - - - MWMC - Memory write mode control - 19 - 1 - - - CRPGS - CRAM page size - 16 - 3 - - - NWASEN - NWAIT in asynchronous transfer enable - 15 - 1 - - - RWTD - Read-write timing different - 14 - 1 - - - NWSEN - NWAIT in synchronous transfer enable - 13 - 1 - - - WEN - Write enable - 12 - 1 - - - NWTCFG - Wait timing configuration - 11 - 1 - - - WRAPEN - Wrapped enable - 10 - 1 - - - NWPOL - NWAIT polarity - 9 - 1 - - - SYNCBEN - Synchronous burst enable - 8 - 1 - - - NOREN - Nor flash access enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 2 - 2 - - - ADMUXEN - Address and data multiplexing enable - 1 - 1 - - - EN - Memory bank enable - 0 - 1 - - - - - BK1TMG1 - BK1TMG1 - SRAM/NOR-Flash chip-select timing register - 1 - 0x4 - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - DTLAT - Data latency - 24 - 4 - - - CLKPSC - Clock prescale - 20 - 4 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1CTRL4 - BK1CTRL4 - SRAM/NOR-Flash chip-select control register 4 - 0x18 - 0x20 - read-write - 0x000030D2 - - - MWMC - Memory write mode control - 19 - 1 - - - CRPGS - CRAM page size - 16 - 3 - - - NWASEN - NWAIT in asynchronous transfer enable - 15 - 1 - - - RWTD - Read-write timing different - 14 - 1 - - - NWSEN - NWAIT in synchronous transfer enable - 13 - 1 - - - WEN - Write enable - 12 - 1 - - - NWTCFG - Wait timing configuration - 11 - 1 - - - WRAPEN - Wrapped enable - 10 - 1 - - - NWPOL - NWAIT polarity - 9 - 1 - - - SYNCBEN - Synchronous burst enable - 8 - 1 - - - NOREN - Nor flash access enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 2 - 2 - - - ADMUXEN - Address and data multiplexing enable - 1 - 1 - - - EN - Memory bank enable - 0 - 1 - - - - - BK1TMG4 - BK1TMG4 - SRAM/NOR-Flash chip-select timing register - 4 - 0x1C - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - DTLAT - Data latency - 24 - 4 - - - CLKPSC - Clock prescale - 20 - 4 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK2CTRL - BK2CTRL - PC Card/NAND Flash control register 2 - 0x60 - 0x20 - read-write - 0x00000018 - - - ECCPGS - ECC page size - 17 - 3 - - - TAR - ALE to RE delay - 13 - 4 - - - TCR - CLE to RE delay - 9 - 4 - - - ECCEN - ECC enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 3 - 1 - - - EN - Memory bank enable - 2 - 1 - - - NWEN - Wait feature enable - 1 - 1 - - - - - BK2IS - BK2IS - FIFO status and interrupt register 2 - 0x64 - 0x20 - 0x00000040 - - - FIFOE - FIFO empty - 6 - 1 - read-only - - - FEIEN - Falling edge interrupt enable - 5 - 1 - read-write - - - HLIEN - High-level interrupt enable - 4 - 1 - read-write - - - REIEN - Rising edge interrupt enable - 3 - 1 - read-write - - - FES - Falling edge status - 2 - 1 - read-write - - - HLS - High-level status - 1 - 1 - read-write - - - RES - Rising edge capture status - 0 - 1 - read-write - - - - - BK2TMGMEM - BK2TMGMEM - Regular memory space timing register 2 - 0x68 - 0x20 - read-write - 0xFCFCFCFC - - - RGDHIZT - Regular memory databus High resistance time - 24 - 8 - - - RGHT - Regular memory hold time - 16 - 8 - - - RGWT - Regular memory wait time - 8 - 8 - - - RGST - Regular memory setup time - 0 - 8 - - - - - BK2TMGATT - BK2TMGATT - special memory space timing register 2 - 0x6C - 0x20 - read-write - 0xFCFCFCFC - - - SPDHIZT - special memory databus High resistance time - 24 - 8 - - - SPHT - special memory hold time - 16 - 8 - - - SPWT - special memory wait time - 8 - 8 - - - SPST - special memory setup time - 0 - 8 - - - - - BK2ECC - BK2ECC - ECC result register 2 - 0x74 - 0x20 - read-write - 0x00000000 - - - ECC - ECC result - 0 - 32 - - - - - BK1TMGWR1 - BK1TMGWR1 - SRAM/NOR-Flash write timing registers - 1 - 0x104 - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1TMGWR4 - BK1TMGWR4 - SRAM/NOR-Flash write timing registers - 4 - 0x11C - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - EXT1 - EXT1 - externl timeing register 1 - 0x220 - 0x20 - read-write - 0x00000808 - - - BUSLATW2W - Bus turnaround phase for consecutive write duration - 0 - 8 - - - BUSLATR2R - Bus turnaround phase for consecutive read duration - 8 - 8 - - - - - EXT4 - EXT4 - externl timeing register 4 - 0x22C - 0x20 - read-write - 0x00000808 - - - BUSLATW2W - BUSLATW2W - 0 - 8 - - - BUSLATR2R - BUSLATR2R - 8 - 8 - - - - - - - PWC - Power control - PWC - 0x40007000 - - 0x0 - 0x400 - registers - - - - CTRL - CTRL - Power control register - (PWC_CTRL) - 0x0 - 0x20 - read-write - 0x00000000 - - - VRSEL - Voltage regulator state select when deepsleep mode - 0 - 1 - - - LPSEL - Low power mode select when Cortex-M4F sleepdeep - 1 - 1 - - - CLSWEF - Clear SWEF flag - 2 - 1 - - - CLSEF - Clear SEF flag - 3 - 1 - - - PVMEN - Power voltage monitoring enable - 4 - 1 - - - PVMSEL - Power voltage monitoring boundary select - 5 - 3 - - - BPWEN - Battery powered domain write enable - 8 - 1 - - - - - CTRLSTS - CTRLSTS - Power control and status register - (PWC_CTRLSTS) - 0x4 - 0x20 - 0x00000000 - - - SWEF - Standby wake-up event flag - 0 - 1 - read-only - - - SEF - Standby mode entry flag - 1 - 1 - read-only - - - PVMOF - Power voltage monitoring output flag - 2 - 1 - read-only - - - SWPEN - Standby wake-up pin enable - 8 - 1 - read-write - - - - - - - CRM - Clock and reset management - CRM - 0x40021000 - - 0x0 - 0x400 - registers - - - CRM - CRM global interrupt - 5 - - - - CTRL - CTRL - Clock control register - 0x0 - 0x20 - 0x00000083 - - - HICKEN - High speed internal clock enable - 0 - 1 - read-write - - - HICKSTBL - High speed internal clock ready flag - 1 - 1 - read-only - - - HICKTRIM - High speed internal clock trimming - 2 - 6 - read-write - - - HICKCAL - High speed internal clock calibration - 8 - 8 - read-only - - - HEXTEN - High speed exernal crystal enable - 16 - 1 - read-write - - - HEXTSTBL - High speed exernal crystal ready flag - 17 - 1 - read-only - - - HEXTBYPS - High speed exernal crystal bypass - 18 - 1 - read-write - - - CFDEN - Clock failure detection enable - 19 - 1 - read-write - - - PLLEN - PLL enable - 24 - 1 - read-write - - - PLLSTBL - PLL clock ready flag - 25 - 1 - read-only - - - - - CFG - CFG - Clock configuration register - (CRM_CFG) - 0x4 - 0x20 - 0x00000000 - - - SCLKSEL - System clock select - 0 - 2 - read-write - - - SCLKSTS - System Clock select Status - 2 - 2 - read-only - - - AHBDIV - AHB division - 4 - 4 - read-write - - - APB1DIV - APB1 division - 8 - 3 - read-write - - - APB2DIV - APB2 division - 11 - 3 - read-write - - - ADCDIV1_0 - ADC division bit1 and bit0 - 14 - 2 - read-write - - - PLLRCS - PLL reference clock select - 16 - 1 - read-write - - - PLLHEXTDIV - HEXT division selection for PLL entry clock - 17 - 1 - read-write - - - PLLMULT3_0 - PLL Multiplication Factor bit3 to bit0 - 18 - 4 - read-write - - - USBDIV1_0 - USB division bit1 and bit0 - 22 - 2 - read-write - - - CLKOUT_SEL - Clock output selection bit2 to bit0 - 24 - 3 - read-write - - - USBDIV2 - USB division bit2 - 27 - 1 - read-write - - - ADCDIV2 - ADC division bit2 - 28 - 1 - read-write - - - PLLMULT5_4 - PLL Multiplication Factor bit5 and bit4 - 29 - 2 - read-write - - - PLLRANGE - PLL clock output frequency up 72MHz or not - 31 - 1 - read-write - - - - - CLKINT - CLKINT - Clock interrupt register - (CRM_CLKINT) - 0x8 - 0x20 - 0x00000000 - - - LICKSTBLF - LICK ready interrupt flag - 0 - 1 - read-only - - - LEXTSTBLF - LEXT ready interrupt flag - 1 - 1 - read-only - - - HICKSTBLF - HICK ready interrupt flag - 2 - 1 - read-only - - - HEXTSTBLF - HEXT ready interrupt flag - 3 - 1 - read-only - - - PLLSTBLF - PLL ready interrupt flag - 4 - 1 - read-only - - - CFDF - Clock failure detection interrupt flag - 7 - 1 - read-only - - - LICKSTBLIEN - LICK ready interrupt enable - 8 - 1 - read-write - - - LEXTSTBLIEN - LEXT ready interrupt enable - 9 - 1 - read-write - - - HICKSTBLIEN - HICK ready interrupt enable - 10 - 1 - read-write - - - HEXTSTBLIEN - HEXT ready interrupt enable - 11 - 1 - read-write - - - PLLSTBLIEN - PLL ready interrupt enable - 12 - 1 - read-write - - - LICKSTBLFC - LICK ready interrupt clear - 16 - 1 - write-only - - - LEXTSTBLFC - LEXT ready interrupt clear - 17 - 1 - write-only - - - HICKSTBLFC - HICK ready interrupt clear - 18 - 1 - write-only - - - HEXTSTBLFC - HEXT ready interrupt clear - 19 - 1 - write-only - - - PLLSTBLFC - PLL ready interrupt clear - 20 - 1 - write-only - - - CFDFC - Clock failure detection interrupt clear - 23 - 1 - write-only - - - - - APB2RST - APB2RST - APB2 peripheral reset register - (CRM_APB2RST) - 0xC - 0x20 - read-write - 0x000000000 - - - IOMUXRST - MUX function I/O - reset - 0 - 1 - - - EXINTRST - External interrupt reset - 1 - 1 - - - GPIOARST - IO port A reset - 2 - 1 - - - GPIOBRST - IO port B reset - 3 - 1 - - - GPIOCRST - IO port C reset - 4 - 1 - - - GPIODRST - IO port D reset - 5 - 1 - - - GPIOERST - IO port E reset - 6 - 1 - - - ADC1RST - ADC1 reset - 9 - 1 - - - ADC2RST - ADC2 reset - 10 - 1 - - - TMR1RST - Timer1 reset - 11 - 1 - - - SPI1RST - SPI1 reset - 12 - 1 - - - TMR8RST - Timer8 reset - 13 - 1 - - - USART1RST - USART1 reset - 14 - 1 - - - ADC3RST - ADC3 reset - 15 - 1 - - - TMR9RST - Timer9 reset - 19 - 1 - - - TMR10RST - Timer10 reset - 20 - 1 - - - TMR11RST - Timer11 reset - 21 - 1 - - - ACCRST - ACC reset - 22 - 1 - - - I2C3RST - I2C3 reset - 23 - 1 - - - USART6RST - USART6 reset - 24 - 1 - - - UART7RST - UART7 reset - 25 - 1 - - - UART8RST - UART8 reset - 26 - 1 - - - - - APB1RST - APB1RST - APB1 peripheral reset register - (CRM_APB1RST) - 0x10 - 0x20 - read-write - 0x00000000 - - - TMR2RST - Timer 2 reset - 0 - 1 - - - TMR3RST - Timer 3 reset - 1 - 1 - - - TMR4RST - Timer 4 reset - 2 - 1 - - - TMR5RST - Timer 5 reset - 3 - 1 - - - TMR6RST - Timer 6 reset - 4 - 1 - - - TMR7RST - Timer 7 reset - 5 - 1 - - - TMR12RST - Timer 12 reset - 6 - 1 - - - TMR13RST - Timer 13 reset - 7 - 1 - - - TMR14RST - Timer 14 reset - 8 - 1 - - - WWDTRST - Window watchdog timer reset - 11 - 1 - - - SPI2RST - SPI2 reset - 14 - 1 - - - SPI3RST - SPI3 reset - 15 - 1 - - - SPI4RST - SPI4 reset - 16 - 1 - - - USART2RST - USART 2 reset - 17 - 1 - - - USART3RST - USART 3 reset - 18 - 1 - - - UART4RST - UART 4 reset - 19 - 1 - - - UART5RST - UART 5 reset - 20 - 1 - - - I2C1RST - I2C1 reset - 21 - 1 - - - I2C2RST - I2C2 reset - 22 - 1 - - - USBRST - USB reset - 23 - 1 - - - CAN1RST - CAN1 reset - 25 - 1 - - - CAN2RST - CAN2 reset - 26 - 1 - - - BPRRST - Battery powered domain register reset - 27 - 1 - - - PWCRST - Power controller reset - 28 - 1 - - - DACRST - DAC reset - 29 - 1 - - - - - AHBEN - AHBEN - AHB Peripheral Clock enable register - (CRM_AHBEN) - 0x14 - 0x20 - read-write - 0x00000014 - - - DMA1EN - DMA1 clock enable - 0 - 1 - - - DMA2EN - DMA2 clock enable - 1 - 1 - - - SRAMEN - SRAM interface clock - enable - 2 - 1 - - - FLASHEN - FLASH clock enable - 4 - 1 - - - CRCEN - CRC clock enable - 6 - 1 - - - XMCEN - XMC clock enable - 8 - 1 - - - SDIO1EN - SDIO1 clock enable - 10 - 1 - - - SDIO2EN - SDIO2 clock enable - 11 - 1 - - - EMACEN - EMACEN clock enable - 14 - 1 - - - EMACTXEN - EMACEN Tx clock enable - 15 - 1 - - - EMACRXEN - EMACEN Rx clock enable - 16 - 1 - - - EMACPTPEN - EMACPTP clock enable - 28 - 1 - - - - - APB2EN - APB2EN - APB2 peripheral clock enable register - (CRM_APB2EN) - 0x18 - 0x20 - read-write - 0x00000000 - - - IOMUXEN - MUX function I/O clock - enable - 0 - 1 - - - GPIOAEN - I/O port A clock enable - 2 - 1 - - - GPIOBEN - I/O port B clock enable - 3 - 1 - - - GPIOCEN - I/O port C clock enable - 4 - 1 - - - GPIODEN - I/O port D clock enable - 5 - 1 - - - GPIOEEN - I/O port E clock enable - 6 - 1 - - - ADC1EN - ADC1 clock - enable - 9 - 1 - - - ADC2EN - ADC2 clock - enable - 10 - 1 - - - TMR1EN - Timer1 clock enable - 11 - 1 - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - TMR8EN - Timer8 clock enable - 13 - 1 - - - USART1EN - USART1 clock enable - 14 - 1 - - - ADC3EN - ADC3 clock enable - 15 - 1 - - - TMR9EN - Timer9 clock enable - 19 - 1 - - - TMR10EN - Timer10 clock enable - 20 - 1 - - - TMR11EN - Timer11 clock enable - 21 - 1 - - - ACCEN - ACC clock enable - 22 - 1 - - - I2C3EN - I2C3 clock enable - 23 - 1 - - - USART6EN - USART6 clock enable - 24 - 1 - - - UART7EN - UART7 clock enable - 25 - 1 - - - UART8EN - UART8 clock enable - 26 - 1 - - - - - APB1EN - APB1EN - APB1 peripheral clock enable register - (CRM_APB1EN) - 0x1C - 0x20 - read-write - 0x00000000 - - - TMR2EN - Timer2 clock enable - 0 - 1 - - - TMR3EN - Timer3 clock enable - 1 - 1 - - - TMR4EN - Timer4 clock enable - 2 - 1 - - - TMR5EN - Timer5 clock enable - 3 - 1 - - - TMR6EN - Timer6 clock enable - 4 - 1 - - - TMR7EN - Timer7 clock enable - 5 - 1 - - - TMR12EN - Timer12 clock enable - 6 - 1 - - - TMR13EN - Timer13 clock enable - 7 - 1 - - - TMR14EN - Timer14 clock enable - 8 - 1 - - - WWDTEN - Window watchdog timer clock - enable - 11 - 1 - - - SPI2EN - SPI2 clock enable - 14 - 1 - - - SPI3EN - SPI3 clock enable - 15 - 1 - - - SPI4EN - SPI4 clock enable - 16 - 1 - - - USART2EN - USART2 clock enable - 17 - 1 - - - USART3EN - USART3 clock enable - 18 - 1 - - - UART4EN - UART4 clock enable - 19 - 1 - - - UART5EN - UART5 clock enable - 20 - 1 - - - I2C1EN - I2C1 clock enable - 21 - 1 - - - I2C2EN - I2C2 clock enable - 22 - 1 - - - USBEN - USB clock enable - 23 - 1 - - - CAN1EN - CAN1 clock enable - 25 - 1 - - - CAN2EN - CAN2 clock enable - 26 - 1 - - - BPREN - Barrery powered domain register clock - enable - 27 - 1 - - - PWCEN - Power clock enable - 28 - 1 - - - DACEN - DAC clock enable - 29 - 1 - - - - - BPDC - BPDC - Battery powered domain control register - (CRM_BPDC) - 0x20 - 0x20 - 0x00000000 - - - LEXTEN - Low speed external crystal enable - 0 - 1 - read-write - - - LEXTSTBL - Low speed external crystal ready - 1 - 1 - read-only - - - LEXTBYPS - Low speed external crystal bypass - 2 - 1 - read-write - - - RTCSEL - RTC clock selection - 8 - 2 - read-write - - - RTCEN - RTC clock enable - 15 - 1 - read-write - - - BPDRST - Battery powered domain software reset - 16 - 1 - read-write - - - - - CTRLSTS - CTRLSTS - Control/status register - (CRM_CTRLSTS) - 0x24 - 0x20 - 0x0C000000 - - - LICKEN - Low speed internal clock enable - 0 - 1 - read-write - - - LICKSTBL - Low speed internal clock ready - 1 - 1 - read-only - - - RSTFC - Reset flag clear - 24 - 1 - read-write - - - NRSTF - PIN reset flag - 26 - 1 - read-write - - - PORRSTF - POR/LVR reset flag - 27 - 1 - read-write - - - SWRSTF - Software reset flag - 28 - 1 - read-write - - - WDTRSTF - Watchdog timer reset flag - 29 - 1 - read-write - - - WWDTRSTF - Window watchdog timer reset flag - 30 - 1 - read-write - - - LPRSTF - Low-power reset flag - 31 - 1 - read-write - - - - - AHBRST - AHBRST - AHB reset register - - 0x28 - 0x20 - 0x00000000 - - - EMACRST - EMAC reset - 14 - 1 - read-write - - - - - MISC1 - MISC1 - Miscellaneous register1 - 0x30 - 0x20 - 0x00000000 - - - HICKCAL_KEY - HICKCAL write key value - 0 - 8 - read-write - - - CLKOUT_SEL3 - Clock output bit3 - 16 - 1 - read-write - - - USBBUFS - USB buffer size selection - 24 - 1 - read-write - - - HICKDIV - HICK 6 divider selection - 25 - 1 - read-write - - - CLKOUTDIV - Clock output division - 28 - 4 - read-write - - - - - MISC2 - MISC2 - Miscellaneous register2 - 0x50 - 0x20 - 0x00000000 - - - CLK_TO_TMR - Clock output internal connect to timer10 - 16 - 1 - read-write - - - - - MISC3 - MISC3 - Miscellaneous register3 - 0x54 - 0x20 - 0x00000000 - - - AUTO_STEP_EN - AUTO_STEP_EN - 4 - 2 - read-write - - - HICK_TO_USB - HICK to usb clock - 8 - 1 - read-write - - - HICK_TO_SCLK - HICK to system clock - 9 - 1 - read-write - - - HEXTDIV - HEXT division - 12 - 2 - read-write - - - EMAC_PPS_SEL - Ethernet pulse width Select - 15 - 1 - read-write - - - - - INTMAP - INTMAP - Interrupt remap register - 0x5C - 0x20 - 0x00000000 - - - USB_INT_MAP - USBDEV interrupt remap - 0 - 1 - read-write - - - - - - - GPIOA - General purpose IO - GPIO - 0x40010800 - - 0x0 - 0x400 - registers - - - - CFGLR - CFGLR - GPIO function configurate low register - 0x0 - 0x20 - read-write - 0x44444444 - - - IOMC0 - Port n.0 mode configurate bits - 0 - 2 - - - IOFC0 - Port n.0 function configurate - bits - 2 - 2 - - - IOMC1 - Port n.1 mode configurate bits - 4 - 2 - - - IOFC1 - Port n.1 function configurate - bits - 6 - 2 - - - IOMC2 - Port n.2 mode configurate bits - 8 - 2 - - - IOFC2 - Port n.2 function configurate - bits - 10 - 2 - - - IOMC3 - Port n.3 mode configurate bits - 12 - 2 - - - IOFC3 - Port n.3 function configurate - bits - 14 - 2 - - - IOMC4 - Port n.4 mode configurate bits - 16 - 2 - - - IOFC4 - Port n.4 function configurate - bits - 18 - 2 - - - IOMC5 - Port n.5 mode configurate bits - 20 - 2 - - - IOFC5 - Port n.5 function configurate - bits - 22 - 2 - - - IOMC6 - Port n.6 mode configurate bits - 24 - 2 - - - IOFC6 - Port n.6 function configurate - bits - 26 - 2 - - - IOMC7 - Port n.7 mode configurate bits - 28 - 2 - - - IOFC7 - Port n.7 function configurate - bits - 30 - 2 - - - - - CFGHR - CFGHR - GPIO function configurate high register - 0x4 - 0x20 - read-write - 0x44444444 - - - IOMC8 - Port n.8 mode configurate bits - 0 - 2 - - - IOFC8 - Port n.8 function configurate - bits - 2 - 2 - - - IOMC9 - Port n.9 mode configurate bits - 4 - 2 - - - IOFC9 - Port n.9 function configurate - bits - 6 - 2 - - - IOMC10 - Port n.10 mode configurate bits - 8 - 2 - - - IOFC10 - Port n.10 function configurate - bits - 10 - 2 - - - IOMC11 - Port n.11 mode configurate bits - 12 - 2 - - - IOFC11 - Port n.11 function configurate - bits - 14 - 2 - - - IOMC12 - Port n.12 mode configurate bits - 16 - 2 - - - IOFC12 - Port n.12 function configurate - bits - 18 - 2 - - - IOMC13 - Port n.13 mode configurate bits - 20 - 2 - - - IOFC13 - Port n.13 function configurate - bits - 22 - 2 - - - IOMC14 - Port n.14 mode configurate bits - 24 - 2 - - - IOFC14 - Port n.14 function configurate - bits - 26 - 2 - - - IOMC15 - Port n.15 mode configurate bits - 28 - 2 - - - IOFC15 - Port n.15 function configurate - bits - 30 - 2 - - - - - IDT - IDT - Port input data register - 0x8 - 0x20 - read-only - 0x00000000 - - - IDT0 - Port input data - 0 - 1 - - - IDT1 - Port input data - 1 - 1 - - - IDT2 - Port input data - 2 - 1 - - - IDT3 - Port input data - 3 - 1 - - - IDT4 - Port input data - 4 - 1 - - - IDT5 - Port input data - 5 - 1 - - - IDT6 - Port input data - 6 - 1 - - - IDT7 - Port input data - 7 - 1 - - - IDT8 - Port input data - 8 - 1 - - - IDT9 - Port input data - 9 - 1 - - - IDT10 - Port input data - 10 - 1 - - - IDT11 - Port input data - 11 - 1 - - - IDT12 - Port input data - 12 - 1 - - - IDT13 - Port input data - 13 - 1 - - - IDT14 - Port input data - 14 - 1 - - - IDT15 - Port input data - 15 - 1 - - - - - ODT - ODT - Port output data register - 0xC - 0x20 - read-write - 0x00000000 - - - ODT0 - Port output data - 0 - 1 - - - ODT1 - Port output data - 1 - 1 - - - ODT2 - Port output data - 2 - 1 - - - ODT3 - Port output data - 3 - 1 - - - ODT4 - Port output data - 4 - 1 - - - ODT5 - Port output data - 5 - 1 - - - ODT6 - Port output data - 6 - 1 - - - ODT7 - Port output data - 7 - 1 - - - ODT8 - Port output data - 8 - 1 - - - ODT9 - Port output data - 9 - 1 - - - ODT10 - Port output data - 10 - 1 - - - ODT11 - Port output data - 11 - 1 - - - ODT12 - Port output data - 12 - 1 - - - ODT13 - Port output data - 13 - 1 - - - ODT14 - Port output data - 14 - 1 - - - ODT15 - Port output data - 15 - 1 - - - - - SCR - SCR - Port bit set/clear register - 0x10 - 0x20 - read-write - 0x00000000 - - - IOSB0 - Set bit 0 - 0 - 1 - - - IOSB1 - Set bit 1 - 1 - 1 - - - IOSB2 - Set bit 1 - 2 - 1 - - - IOSB3 - Set bit 3 - 3 - 1 - - - IOSB4 - Set bit 4 - 4 - 1 - - - IOSB5 - Set bit 5 - 5 - 1 - - - IOSB6 - Set bit 6 - 6 - 1 - - - IOSB7 - Set bit 7 - 7 - 1 - - - IOSB8 - Set bit 8 - 8 - 1 - - - IOSB9 - Set bit 9 - 9 - 1 - - - IOSB10 - Set bit 10 - 10 - 1 - - - IOSB11 - Set bit 11 - 11 - 1 - - - IOSB12 - Set bit 12 - 12 - 1 - - - IOSB13 - Set bit 13 - 13 - 1 - - - IOSB14 - Set bit 14 - 14 - 1 - - - IOSB15 - Set bit 15 - 15 - 1 - - - IOCB0 - Clear bit 0 - 16 - 1 - - - IOCB1 - Clear bit 1 - 17 - 1 - - - IOCB2 - Clear bit 2 - 18 - 1 - - - IOCB3 - Clear bit 3 - 19 - 1 - - - IOCB4 - Clear bit 4 - 20 - 1 - - - IOCB5 - Clear bit 5 - 21 - 1 - - - IOCB6 - Clear bit 6 - 22 - 1 - - - IOCB7 - Clear bit 7 - 23 - 1 - - - IOCB8 - Clear bit 8 - 24 - 1 - - - IOCB9 - Clear bit 9 - 25 - 1 - - - IOCB10 - Clear bit 10 - 26 - 1 - - - IOCB11 - Clear bit 11 - 27 - 1 - - - IOCB12 - Clear bit 12 - 28 - 1 - - - IOCB13 - Clear bit 13 - 29 - 1 - - - IOCB14 - Clear bit 14 - 30 - 1 - - - IOCB15 - Clear bit 15 - 31 - 1 - - - - - CLR - CLR - Port bit reset register - 0x14 - 0x20 - read-write - 0x00000000 - - - IOCB0 - Clear bit 0 - 0 - 1 - - - IOCB1 - Clear bit 1 - 1 - 1 - - - IOCB2 - Clear bit 1 - 2 - 1 - - - IOCB3 - Clear bit 3 - 3 - 1 - - - IOCB4 - Clear bit 4 - 4 - 1 - - - IOCB5 - Clear bit 5 - 5 - 1 - - - IOCB6 - Clear bit 6 - 6 - 1 - - - IOCB7 - Clear bit 7 - 7 - 1 - - - IOCB8 - Clear bit 8 - 8 - 1 - - - IOCB9 - Clear bit 9 - 9 - 1 - - - IOCB10 - Clear bit 10 - 10 - 1 - - - IOCB11 - Clear bit 11 - 11 - 1 - - - IOCB12 - Clear bit 12 - 12 - 1 - - - IOCB13 - Clear bit 13 - 13 - 1 - - - IOCB14 - Clear bit 14 - 14 - 1 - - - IOCB15 - Clear bit 15 - 15 - 1 - - - - - WPR - WPR - Port write protect - register - 0x18 - 0x20 - read-write - 0x00000000 - - - WPEN0 - Write protect enable 0 - 0 - 1 - - - WPEN1 - Write protect enable 1 - 1 - 1 - - - WPEN2 - Write protect enable 2 - 2 - 1 - - - WPEN3 - Write protect enable 3 - 3 - 1 - - - WPEN4 - Write protect enable 4 - 4 - 1 - - - WPEN5 - Write protect enable 5 - 5 - 1 - - - WPEN6 - Write protect enable 6 - 6 - 1 - - - WPEN7 - Write protect enable 7 - 7 - 1 - - - WPEN8 - Write protect enable 8 - 8 - 1 - - - WPEN9 - Write protect enable 9 - 9 - 1 - - - WPEN10 - Write protect enable 10 - 10 - 1 - - - WPEN11 - Write protect enable 11 - 11 - 1 - - - WPEN12 - Write protect enable 12 - 12 - 1 - - - WPEN13 - Write protect enable 13 - 13 - 1 - - - WPEN14 - Write protect enable 14 - 14 - 1 - - - WPEN15 - Write protect enable 15 - 15 - 1 - - - WPSEQ - Write protect sequence - 16 - 1 - - - - - HDRV - HDRV - Port configuration driver - register - 0x3C - 0x20 - read-write - 0x00000000 - - - HDRV0 - Port hdrv bit 0 - 0 - 1 - - - HDRV1 - Port hdrv bit 1 - 1 - 1 - - - HDRV2 - Port hdrv bit 2 - 2 - 1 - - - HDRV3 - Port hdrv bit 3 - 3 - 1 - - - HDRV4 - Port hdrv bit 4 - 4 - 1 - - - HDRV5 - Port hdrv bit 5 - 5 - 1 - - - HDRV6 - Port hdrv bit 6 - 6 - 1 - - - HDRV7 - Port hdrv bit 7 - 7 - 1 - - - HDRV8 - Port hdrv bit 8 - 8 - 1 - - - HDRV9 - Port hdrv bit 9 - 9 - 1 - - - HDRV10 - Port hdrv bit 10 - 10 - 1 - - - HDRV11 - Port hdrv bit 11 - 11 - 1 - - - HDRV12 - Port hdrv bit 12 - 12 - 1 - - - HDRV13 - Port hdrv bit 13 - 13 - 1 - - - HDRV14 - Port hdrv bit 14 - 14 - 1 - - - HDRV15 - Port hdrv bit 15 - 15 - 1 - - - - - - - GPIOB - 0x40010C00 - - - GPIOC - 0x40011000 - - - GPIOD - 0x40011400 - - - GPIOE - 0x40011800 - - - IOMUX - IO MUX function - IOMUX - 0x40010000 - - 0x0 - 0x400 - registers - - - - EVTOUT - EVTOUT - Event output register - (IOMUX_EVTOUT) - 0x0 - 0x20 - read-write - 0x00000000 - - - SELPIN - Select pin - 0 - 4 - - - SELPORT - Select port - 4 - 3 - - - EVOEN - Event output enable - 7 - 1 - - - - - REMAP - REMAP - IO MUX remap register - (IOMUX_REMAP) - 0x4 - 0x20 - 0x00000000 - - - SPI1_MUX0 - SPI1 muxing bit0 - 0 - 1 - read-write - - - I2C1_MUX - I2C1 muxing - 1 - 1 - read-write - - - USART1_MUX - USART1 muxing - 2 - 1 - read-write - - - USART2_MUX - USART2 muxing - 3 - 1 - read-write - - - USART3_MUX - USART3 muxing - 4 - 2 - read-write - - - TMR1_MUX - TMR1 muxing - 6 - 2 - read-write - - - TMR2_MUX - TMR2 muxing - 8 - 2 - read-write - - - TMR3_MUX - TMR3 muxing - 10 - 2 - read-write - - - TMR4_MUX - TMR4 muxing - 12 - 1 - read-write - - - CAN_MUX - CAN1 muxing - 13 - 2 - read-write - - - PD01_MUX - PD0/PD1 muxing on - OSCIN/OSCOUT - 15 - 1 - read-write - - - TMR5CH4_MUX - TMR5 channel4 internal muxing - 16 - 1 - read-write - - - ADC1_ETP_MUX - ADC1 external trigger preempted - conversion muxing - 17 - 1 - read-write - - - ADC1_ETO_MUX - ADC1 external trigger ordinary - conversion muxing - 18 - 1 - read-write - - - ADC2_ETP_MUX - ADC2 external trigger preempted - conversion muxing - 19 - 1 - read-write - - - ADC2_ETO_MUX - ADC2 external trigger ordinary - conversion muxing - 20 - 1 - read-write - - - EMAC_MUX - Ethernet MAC muxing - 21 - 1 - read-write - - - CAN2_MUX - CAN2 muxing - 22 - 1 - read-write - - - MII_RMII_SEL_MUX - MII_RMII select muxing - 23 - 1 - read-write - - - SWJTAG_MUX - SWD JTAG muxing - 24 - 3 - read-write - - - SPI3_MUX - SPI3 muxing - 28 - 1 - read-write - - - TMR2ITR1_MUX - TMR2 internal trigger 1 - muxing - 29 - 1 - read-write - - - PTP_PPS_MUX - PTP_PPS muxing - 30 - 1 - read-write - - - SPI1_MUX1 - SPI1 muxing bit1 - 31 - 1 - read-write - - - - - EXINTC1 - EXINTC1 - External interrupt configuration register 1 - (IOMUX_EXINTC1) - 0x8 - 0x20 - read-write - 0x00000000 - - - EXINT0 - Configure EXINT0 source - 0 - 4 - - - EXINT1 - Configure EXINT1 source - 4 - 4 - - - EXINT2 - Configure EXINT2 source - 8 - 4 - - - EXINT3 - Configure EXINT3 source - 12 - 4 - - - - - EXINTC2 - EXINTC2 - External interrupt configuration register 2 - (IOMUX_EXINTC2) - 0xC - 0x20 - read-write - 0x00000000 - - - EXINT4 - Configure EXINT4 source - 0 - 4 - - - EXINT5 - Configure EXINT5 source - 4 - 4 - - - EXINT6 - Configure EXINT6 source - 8 - 4 - - - EXINT7 - Configure EXINT7 source - 12 - 4 - - - - - EXINTC3 - EXINTC3 - External interrupt configuration register 3 - (IOMUX_EXINTC3) - 0x10 - 0x20 - read-write - 0x00000000 - - - EXINT8 - Configure EXINT8 source - 0 - 4 - - - EXINT9 - Configure EXINT9 source - 4 - 4 - - - EXINT10 - Configure EXINT10 source - 8 - 4 - - - EXINT11 - Configure EXINT11 source - 12 - 4 - - - - - EXINTC4 - EXINTC4 - External interrupt configuration register 4 - (IOMUX_EXINTC4) - 0x14 - 0x20 - read-write - 0x00000000 - - - EXINT12 - Configure EXINT12 source - 0 - 4 - - - EXINT13 - Configure EXINT13 source - 4 - 4 - - - EXINT14 - Configure EXINT14 source - 8 - 4 - - - EXINT15 - Configure EXINT15 source - 12 - 4 - - - - - REMAP2 - REMAP2 - IO MUX remap register 2 - (IOMUX_REMAP2) - 0x1C - 0x20 - read-write - 0x00000000 - - - TMR9_MUX - TMR9 muxing - 5 - 1 - - - XMC_NADV_MUX - NADV connect/disconnect - 10 - 1 - - - SPI4_MUX - SPI4 muxing - 17 - 1 - - - I2C3_MUX - I2C3 muxing - 18 - 1 - - - SDIO2_MUX - SDIO2 muxing - 19 - 2 - - - EXT_SPIM_EN_MUX - SPIM enable muxing - 21 - 1 - - - - - REMAP3 - REMAP3 - IO MUX remap register 3 - (IOMUX_REMAP3) - 0x20 - 0x20 - read-write - 0x00000000 - - - TMR9_GMUX - TMR9 muxing - 0 - 4 - - - - - REMAP4 - REMAP4 - IO MUX remap register 4 - (IOMUX_REMAP4) - 0x24 - 0x20 - read-write - 0x00000000 - - - TMR1_GMUX - TMR1 muxing - 0 - 4 - - - TMR2_GMUX - TMR2 muxing - 4 - 2 - - - TMR2ITR1_GMUX - TMR2 internal trigger 1 - muxing - 6 - 2 - - - TMR3_GMUX - TMR3 muxing - 8 - 4 - - - TMR4_GMUX - TMR4 muxing - 12 - 4 - - - TMR5CH4_GMUX - TMR5 channel4 internal - muxing - 19 - 1 - - - - - REMAP5 - REMAP5 - IO MUX remap register 5 - (IOMUX_REMAP5) - 0x28 - 0x20 - read-write - 0x00000000 - - - USART5_GMUX - USART5 muxing - 0 - 4 - - - I2C1_GMUX - I2C1 muxing - 4 - 4 - - - I2C3_GMUX - I2C3 muxing - 12 - 4 - - - SPI1_GMUX - SPI1 muxing - 16 - 4 - - - SPI2_GMUX - SPI2 muxing - 20 - 4 - - - SPI3_GMUX - SPI3 muxing - 24 - 4 - - - SPI4_GMUX - SPI4 muxing - 28 - 4 - - - - - REMAP6 - REMAP6 - IO MUX remap register 6 - (IOMUX_REMAP6) - 0x2C - 0x20 - read-write - 0x00000000 - - - CAN1_GMUX - CAN1 muxing - 0 - 4 - - - CAN2_GMUX - CAN2 muxing - 4 - 4 - - - SDIO2_GMUX - SDIO2 muxing - 12 - 4 - - - USART1_GMUX - USART1 muxing - 16 - 4 - - - USART2_GMUX - USART2 muxing - 20 - 4 - - - USART3_GMUX - USART3 muxing - 24 - 4 - - - UART4_GMUX - UART4 muxing - 28 - 4 - - - - - REMAP7 - REMAP7 - IO MUX remap register 7 - (IOMUX_REMAP7) - 0x30 - 0x20 - read-write - 0x00000000 - - - EXT_SPIM_GMUX - SPIM muxing - 0 - 3 - - - EXT_SPIM_GEN - SPIM enable - 3 - 1 - - - ADC1_ETP_GMUX - ADC1 external trigger preempted - conversion muxing - 4 - 1 - - - ADC1_ETO_GMUX - ADC1 external trigger ordinary - conversion muxing - 5 - 1 - - - ADC2_ETP_GMUX - ADC2 external trigger preempted - conversion muxing - 8 - 1 - - - ADC2_ETO_GMUX - ADC2 external trigger ordinary - conversion muxing - 9 - 1 - - - SWJTAG_GMUX - Serial wire JTAG muxing - 16 - 3 - - - PD01_GMUX - PortD0/PortD1 mappingon - OSC_IN/OSC_OUT - 20 - 1 - - - XMC_GMUX - XMC muxing - 24 - 3 - - - XMC_NADV_GMUX - XMC_NADV muxing - 27 - 1 - - - - - REMAP8 - REMAP8 - IO MUX remap register 8 - (IOMUX_REMAP8) - 0x34 - 0x20 - read-write - 0x00000000 - - - EMAC_GMUX - Ethernet MAC muxing - 16 - 2 - - - MII_RMII_SEL_GMUX - MII_RMII select muxing - 18 - 1 - - - PTP_PPS_GMUX - PTP_PPS muxing - 19 - 1 - - - USART6_GMUX - USART6 muxing - 20 - 4 - - - UART7_GMUX - UART7 muxing - 24 - 4 - - - UART8_GMUX - UART8 muxing - 28 - 4 - - - - - - - EXINT - EXINT - EXINT - 0x40010400 - - 0x0 - 0x400 - registers - - - TAMPER - Tamper interrupt - 2 - - - EXINT0 - EXINT Line0 interrupt - 6 - - - EXINT1 - EXINT Line1 interrupt - 7 - - - EXINT2 - EXINT Line2 interrupt - 8 - - - EXINT3 - EXINT Line3 interrupt - 9 - - - EXINT4 - EXINT Line4 interrupt - 10 - - - EXINT9_5 - EXINT Line[9:5] interrupts - 23 - - - EXINT15_10 - EXINT Line[15:10] interrupts - 40 - - - PVM - PVM interrupt connect to EXINT line16 - 1 - - - RTCALARM - RTC Alarm interrupt connect to EXINT line17 - 41 - - - USBFSWakeUp - USB Device FS Wakeup interrupt connect to EXINT line18 - 42 - - - EMAC_WKUP - EMAC_WKUP interrupt connect to EXINT line19 - 80 - - - - INTEN - INTEN - Interrupt enable register - 0x0 - 0x20 - read-write - 0x00000000 - - - INTEN0 - Interrupt enable or disable on line 0 - 0 - 1 - - - INTEN1 - Interrupt enable or disable on line 1 - 1 - 1 - - - INTEN2 - Interrupt enable or disable on line 2 - 2 - 1 - - - INTEN3 - Interrupt enable or disable on line 3 - 3 - 1 - - - INTEN4 - Interrupt enable or disable on line 4 - 4 - 1 - - - INTEN5 - Interrupt enable or disable on line 5 - 5 - 1 - - - INTEN6 - Interrupt enable or disable on line 6 - 6 - 1 - - - INTEN7 - Interrupt enable or disable on line 7 - 7 - 1 - - - INTEN8 - Interrupt enable or disable on line 8 - 8 - 1 - - - INTEN9 - Interrupt enable or disable on line 9 - 9 - 1 - - - INTEN10 - Interrupt enable or disable on line 10 - 10 - 1 - - - INTEN11 - Interrupt enable or disable on line 11 - 11 - 1 - - - INTEN12 - Interrupt enable or disable on line 12 - 12 - 1 - - - INTEN13 - Interrupt enable or disable on line 13 - 13 - 1 - - - INTEN14 - Interrupt enable or disable on line 14 - 14 - 1 - - - INTEN15 - Interrupt enable or disable on line 15 - 15 - 1 - - - INTEN16 - Interrupt enable or disable on line 16 - 16 - 1 - - - INTEN17 - Interrupt enable or disable on line 17 - 17 - 1 - - - INTEN18 - Interrupt enable or disable on line 18 - 18 - 1 - - - INTEN19 - Interrupt enable or disable on line 19 - 19 - 1 - - - - - EVTEN - EVTEN - Event enable register - 0x4 - 0x20 - read-write - 0x00000000 - - - EVTEN0 - Event enable or disable on line 0 - 0 - 1 - - - EVTEN1 - Event enable or disable on line 1 - 1 - 1 - - - EVTEN2 - Event enable or disable on line 2 - 2 - 1 - - - EVTEN3 - Event enable or disable on line 3 - 3 - 1 - - - EVTEN4 - Event enable or disable on line 4 - 4 - 1 - - - EVTEN5 - Event enable or disable on line 5 - 5 - 1 - - - EVTEN6 - Event enable or disable on line 6 - 6 - 1 - - - EVTEN7 - Event enable or disable on line 7 - 7 - 1 - - - EVTEN8 - Event enable or disable on line 8 - 8 - 1 - - - EVTEN9 - Event enable or disable on line 9 - 9 - 1 - - - EVTEN10 - Event enable or disable on line 10 - 10 - 1 - - - EVTEN11 - Event enable or disable on line 11 - 11 - 1 - - - EVTEN12 - Event enable or disable on line 12 - 12 - 1 - - - EVTEN13 - Event enable or disable on line 13 - 13 - 1 - - - EVTEN14 - Event enable or disable on line 14 - 14 - 1 - - - EVTEN15 - Event enable or disable on line 15 - 15 - 1 - - - EVTEN16 - Event enable or disable on line 16 - 16 - 1 - - - EVTEN17 - Event enable or disable on line 17 - 17 - 1 - - - EVTEN18 - Event enable or disable on line 18 - 18 - 1 - - - EVTEN19 - Event enable or disable on line 19 - 19 - 1 - - - - - POLCFG1 - POLCFG1 - Rising polarity configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - RP0 - Rising polarity configuration bit of line 0 - 0 - 1 - - - RP1 - Rising polarity configuration bit of line 1 - 1 - 1 - - - RP2 - Rising polarity configuration bit of line 2 - 2 - 1 - - - RP3 - Rising polarity configuration bit of line 3 - 3 - 1 - - - RP4 - Rising polarity configuration bit of line 4 - 4 - 1 - - - RP5 - Rising polarity configuration bit of line 5 - 5 - 1 - - - RP6 - Rising polarity configuration bit of linee 6 - 6 - 1 - - - RP7 - Rising polarity configuration bit of line 7 - 7 - 1 - - - RP8 - Rising polarity configuration bit of line 8 - 8 - 1 - - - RP9 - Rising polarity configuration bit of line 9 - 9 - 1 - - - RP10 - Rising polarity configuration bit of line 10 - 10 - 1 - - - RP11 - Rising polarity configuration bit of line 11 - 11 - 1 - - - RP12 - Rising polarity configuration bit of line 12 - 12 - 1 - - - RP13 - Rising polarity configuration bit of line 13 - 13 - 1 - - - RP14 - Rising polarity configuration bit of line 14 - 14 - 1 - - - RP15 - Rising polarity configuration bit of line 15 - 15 - 1 - - - RP16 - Rising polarity configuration bit of line 16 - 16 - 1 - - - RP17 - Rising polarity configuration bit of line 17 - 17 - 1 - - - RP18 - Rising polarity configuration bit of line 18 - 18 - 1 - - - RP19 - Rising polarity configuration bit of line 19 - 19 - 1 - - - - - POLCFG2 - POLCFG2 - Falling polarity configuration register - 0xC - 0x20 - read-write - 0x00000000 - - - FP0 - Falling polarity event configuration bit of line 0 - 0 - 1 - - - FP1 - Falling polarity event configuration bit of line 1 - 1 - 1 - - - FP2 - Falling polarity event configuration bit of line 2 - 2 - 1 - - - FP3 - Falling polarity event configuration bit of line 3 - 3 - 1 - - - FP4 - Falling polarity event configuration bit of line 4 - 4 - 1 - - - FP5 - Falling polarity event configuration bit of line 5 - 5 - 1 - - - FP6 - Falling polarity event configuration bit of line 6 - 6 - 1 - - - FP7 - Falling polarity event configuration bit of line 7 - 7 - 1 - - - FP8 - Falling polarity event configuration bit of line 8 - 8 - 1 - - - FP9 - Falling polarity event configuration bit of line 9 - 9 - 1 - - - FP10 - Falling polarity event configuration bit of line 10 - 10 - 1 - - - FP11 - Falling polarity event configuration bit of line 11 - 11 - 1 - - - FP12 - Falling polarity event configuration bit of line 12 - 12 - 1 - - - FP13 - Falling polarity event configuration bit of line 13 - 13 - 1 - - - FP14 - Falling polarity event configuration bit of line 14 - 14 - 1 - - - FP15 - Falling polarity event configuration bit of line 15 - 15 - 1 - - - FP16 - Falling polarity event configuration bit of line 16 - 16 - 1 - - - FP17 - Falling polarity event configuration bit of line 17 - 17 - 1 - - - FP18 - Falling polarity event configuration bit of line 18 - 18 - 1 - - - FP19 - Falling polarity event configuration bit of line 19 - 19 - 1 - - - - - SWTRG - SWTRG - Software triggle register - 0x10 - 0x20 - read-write - 0x00000000 - - - SWT0 - Software triggle on line 0 - 0 - 1 - - - SWT1 - Software triggle on line 1 - 1 - 1 - - - SWT2 - Software triggle on line 2 - 2 - 1 - - - SWT3 - Software triggle on line 3 - 3 - 1 - - - SWT4 - Software triggle on line 4 - 4 - 1 - - - SWT5 - Software triggle on line 5 - 5 - 1 - - - SWT6 - Software triggle on line 6 - 6 - 1 - - - SWT7 - Software triggle on line 7 - 7 - 1 - - - SWT8 - Software triggle on line 8 - 8 - 1 - - - SWT9 - Software triggle on line 9 - 9 - 1 - - - SWT10 - Software triggle on line 10 - 10 - 1 - - - SWT11 - Software triggle on line 11 - 11 - 1 - - - SWT12 - Software triggle on line 12 - 12 - 1 - - - SWT13 - Software triggle on line 13 - 13 - 1 - - - SWT14 - Software triggle on line 14 - 14 - 1 - - - SWT15 - Software triggle on line 15 - 15 - 1 - - - SWT16 - Software triggle on line 16 - 16 - 1 - - - SWT17 - Software triggle on line 17 - 17 - 1 - - - SWT18 - Software triggle on line 18 - 18 - 1 - - - SWT19 - Software triggle on line 19 - 19 - 1 - - - - - INTSTS - INTSTS - Interrupt status register - 0x14 - 0x20 - read-write - 0x00000000 - - - LINE0 - Line 0 state bit - 0 - 1 - - - LINE1 - Line 1 state bit - 1 - 1 - - - LINE2 - Line 2 state bit - 2 - 1 - - - LINE3 - Line 3 state bit - 3 - 1 - - - LINE4 - Line 4 state bit - 4 - 1 - - - LINE5 - Line 5 state bit - 5 - 1 - - - LINE6 - Line 6 state bit - 6 - 1 - - - LINE7 - Line 7 state bit - 7 - 1 - - - LINE8 - Line 8 state bit - 8 - 1 - - - LINE9 - Line 9 state bit - 9 - 1 - - - LINE10 - Line 10 state bit - 10 - 1 - - - LINE11 - Line 11 state bit - 11 - 1 - - - LINE12 - Line 12 state bit - 12 - 1 - - - LINE13 - Line 13 state bit - 13 - 1 - - - LINE14 - Line 14 state bit - 14 - 1 - - - LINE15 - Line 15 state bit - 15 - 1 - - - LINE16 - Line 16 state bit - 16 - 1 - - - LINE17 - Line 17 state bit - 17 - 1 - - - LINE18 - Line 18 state bit - 18 - 1 - - - LINE19 - Line 19 state bit - 19 - 1 - - - - - - - DMA1 - DMA controller - DMA - 0x40020000 - - 0x0 - 0x400 - registers - - - DMA1_Channel1 - DMA1 Channel1 global interrupt - 11 - - - DMA1_Channel2 - DMA1 Channel2 global interrupt - 12 - - - DMA1_Channel3 - DMA1 Channel3 global interrupt - 13 - - - DMA1_Channel4 - DMA1 Channel4 global interrupt - 14 - - - DMA1_Channel5 - DMA1 Channel5 global interrupt - 15 - - - DMA1_Channel6 - DMA1 Channel6 global interrupt - 16 - - - DMA1_Channel7 - DMA1 Channel7 global interrupt - 17 - - - - STS - STS - DMA interrupt status register (DMA_STS) - 0x0 - 0x20 - read-only - 0x00000000 - - - GF1 - Channel 1 Global event flag - 0 - 1 - - - GF2 - Channel 2 Global event flag - 4 - 1 - - - GF3 - Channel 3 Global event flag - 8 - 1 - - - GF4 - Channel 4 Global event flag - 12 - 1 - - - GF5 - Channel 5 Global event flag - 16 - 1 - - - GF6 - Channel 6 Global event flag - 20 - 1 - - - GF7 - Channel 7 Global event flag - 24 - 1 - - - FDTF1 - Channel 1 full data transfer event flag - 1 - 1 - - - FDTF2 - Channel 2 full data transfer event flag - 5 - 1 - - - FDTF3 - Channel 3 full data transfer event flag - 9 - 1 - - - FDTF4 - Channel 4 full data transfer event flag - 13 - 1 - - - FDTF5 - Channel 5 full data transfer event flag - 17 - 1 - - - FDTF6 - Channel 6 full data transfer event flag - 21 - 1 - - - FDTF7 - Channel 7 full data transfer event flag - 25 - 1 - - - HDTF1 - Channel 1 half data transfer event flag - 2 - 1 - - - HDTF2 - Channel 2 half data transfer event flag - 6 - 1 - - - HDTF3 - Channel 3 half data transfer event flag - 10 - 1 - - - HDTF4 - Channel 4 half data transfer event flag - 14 - 1 - - - HDTF5 - Channel 5 half data transfer event flag - 18 - 1 - - - HDTF6 - Channel 6 half data transfer event flag - 22 - 1 - - - HDTF7 - Channel 7 half data transfer event flag - 26 - 1 - - - DTERRF1 - Channel 1 data transfer error event flag - 3 - 1 - - - DTERRF2 - Channel 2 data transfer error event flag - 7 - 1 - - - DTERRF3 - Channel 3 data transfer error event flag - 11 - 1 - - - DTERRF4 - Channel 4 data transfer error event flag - 15 - 1 - - - DTERRF5 - Channel 5 data transfer error event flag - 19 - 1 - - - DTERRF6 - Channel 6 data transfer error event flag - 23 - 1 - - - DTERRF7 - Channel 7 data transfer error event flag - 27 - 1 - - - - - CLR - CLR - DMA interrupt flag clear register (DMA_CLR) - 0x4 - 0x20 - read-write - 0x00000000 - - - GFC1 - Channel 1 Global flag clear - 0 - 1 - - - GFC2 - Channel 2 Global flag clear - 4 - 1 - - - GFC3 - Channel 3 Global flag clear - 8 - 1 - - - GFC4 - Channel 4 Global flag clear - 12 - 1 - - - GFC5 - Channel 5 Global flag clear - 16 - 1 - - - GFC6 - Channel 6 Global flag clear - 20 - 1 - - - GFC7 - Channel 7 Global flag clear - 24 - 1 - - - FDTFC1 - Channel 1 full data transfer flag clear - 1 - 1 - - - FDTFC2 - Channel 2 full data transfer flag clear - 5 - 1 - - - FDTFC3 - Channel 3 full data transfer flag clear - 9 - 1 - - - FDTFC4 - Channel 4 full data transfer flag clear - 13 - 1 - - - FDTFC5 - Channel 5 full data transfer flag clear - 17 - 1 - - - FDTFC6 - Channel 6 full data transfer flag clear - 21 - 1 - - - FDTFC7 - Channel 7 full data transfer flag clear - 25 - 1 - - - HDTFC1 - Channel 1 half data transfer flag clear - 2 - 1 - - - HDTFC2 - Channel 2 half data transfer flag clear - 6 - 1 - - - HDTFC3 - Channel 3 half data transfer flag clear - 10 - 1 - - - HDTFC4 - Channel 4 half data transfer flag clear - 14 - 1 - - - HDTFC5 - Channel 5 half data transfer flag clear - 18 - 1 - - - HDTFC6 - Channel 6 half data transfer flag clear - 22 - 1 - - - HDTFC7 - Channel 7 half data transfer flag clear - 26 - 1 - - - DTERRFC1 - Channel 1 data transfer error flag clear - 3 - 1 - - - DTERRFC2 - Channel 2 data transfer error flag clear - 7 - 1 - - - DTERRFC3 - Channel 3 data transfer error flag clear - 11 - 1 - - - DTERRFC4 - Channel 4 data transfer error flag clear - 15 - 1 - - - DTERRFC5 - Channel 5 data transfer error flag clear - 19 - 1 - - - DTERRFC6 - Channel 6 data transfer error flag clear - 23 - 1 - - - DTERRFC7 - Channel 7 data transfer error flag clear - 27 - 1 - - - - - C1CTRL - C1CTRL - DMA channel configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C1DTCNT - C1DTCNT - DMA channel 1 number of data to transfer register - 0xC - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C1PADDR - C1PADDR - DMA channel 1 peripheral base address register - 0x10 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C1MADDR - C1MADDR - DMA channel 1 memory base address register - 0x14 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C2CTRL - C2CTRL - DMA channel configuration register - 0x1C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C2DTCNT - C2DTCNT - DMA channel 2 number of data to transferregister - 0x20 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C2PADDR - C2PADDR - DMA channel 2 peripheral base address register - 0x24 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C2MADDR - C2MADDR - DMA channel 2 memory base address register - 0x28 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C3CTRL - C3CTRL - DMA channel configuration register - 0x30 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C3DTCNT - C3DTCNT - DMA channel 3 number of data to transfer register - 0x34 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C3PADDR - C3PADDR - DMA channel 3 peripheral base address register - 0x38 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C3MADDR - C3MADDR - DMA channel 3 memory base address register - 0x3C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C4CTRL - C4CTRL - DMA channel configuration register - 0x44 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C4DTCNT - C4DTCNT - DMA channel 4 number of data to transfer register - 0x48 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C4PADDR - C4PADDR - DMA channel 4 peripheral base address register - 0x4C - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C4MADDR - C4MADDR - DMA channel 4 memory base address register - 0x50 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C5CTRL - C5CTRL - DMA channel configuration register - 0x58 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C5DTCNT - C5DTCNT - DMA channel 5 number of data to transfer register - 0x5C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C5PADDR - C5PADDR - DMA channel 5 peripheral base address register - 0x60 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C5MADDR - C5MADDR - DMA channel 5 memory base address register - 0x64 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C6CTRL - C6CTRL - DMA channel configuration register - 0x6C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C6DTCNT - C6DTCNT - DMA channel 6 number of data to transfer register - 0x70 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C6PADDR - C6PADDR - DMA channel 6 peripheral address base register - 0x74 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C6MADDR - C6MADDR - DMA channel 6 memory address base register - 0x78 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C7CTRL - C7CTRL - DMA channel configuration register - 0x80 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C7DTCNT - C7DTCNT - DMA channel 7 number of data to transfer register - 0x84 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C7PADDR - C7PADDR - DMA channel 7 peripheral base address register - 0x88 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C7MADDR - C7MADDR - DMA channel 7 memory base address register - 0x8C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - DMA_SRC_SEL0 - DMA_SRC_SEL0 - DMA channel source assignment register - 0xA0 - 0x20 - read-write - 0x00000000 - - - CH1_SRC - CH1 SRC select - 0 - 8 - - - CH2_SRC - CH2 SRC select - 8 - 8 - - - CH3_SRC - CH3 SRC select - 16 - 8 - - - CH4_SRC - CH4 SRC select - 24 - 8 - - - - - DMA_SRC_SEL1 - DMA_SRC_SEL1 - DMA channel source assignment register - 0xA4 - 0x20 - read-write - 0x00000000 - - - CH5_SRC - CH5 SRC select - 0 - 8 - - - CH6_SRC - CH6 SRC select - 8 - 8 - - - CH7_SRC - CH7 SRC select - 16 - 8 - - - DMA_FLEX_EN - DMA FLEX Enable - 24 - 1 - - - - - - - DMA2 - 0x40020400 - - DMA2_Channel1 - DMA2 Channel1 global interrupt - 56 - - - DMA2_Channel2 - DMA2 Channel2 global interrupt - 57 - - - DMA2_Channel3 - DMA2 Channel3 global interrupt - 58 - - - DMA2_Channel4_5 - DMA2 Channel4 and DMA2 Channel5 global - interrupt - 59 - - - DMA2_Channel6_7 - DMA2 Channel6 and DMA2 Channel7 global - interrupt - 75 - - - - SDIO1 - Secure digital input/output - interface - SDIO - 0x40018000 - - 0x0 - 0x400 - registers - - - SDIO1 - SDIO1 global interrupt - 49 - - - - PWRCTRL - PWRCTRL - Bits 1:0 = PWRCTRL: Power supply control - bits - 0x0 - 0x20 - read-write - 0x00000000 - - - PS - Power switch - 0 - 2 - - - - - CLKCTRL - CLKCTRL - SD clock control register - (SDIO_CLKCTRL) - 0x4 - 0x20 - read-write - 0x00000000 - - - CLKDIV - Clock division - 0 - 8 - - - CLKOEN - Clock output enable - 8 - 1 - - - PWRSVEN - Power saving mode enable - 9 - 1 - - - BYPSEN - Clock divider bypass enable - bit - 10 - 1 - - - BUSWS - Bus width selection - 11 - 2 - - - CLKEDS - SDIO_CK edge selection bit - 13 - 1 - - - HFCEN - Hardware flow control enable - 14 - 1 - - - CLKDIV98 - Clock divide factor bit9 and bit8 - 15 - 2 - - - - - ARGU - ARGU - Bits 31:0 = : Command argument - 0x8 - 0x20 - read-write - 0x00000000 - - - ARGU - Command argument - 0 - 32 - - - - - CMDCTRL - CMDCTRL - SDIO command control register - (SDIO_CMDCTRL) - 0xC - 0x20 - read-write - 0x00000000 - - - CMDIDX - CMDIDX - 0 - 6 - - - RSPWT - Wait for response - 6 - 2 - - - INTWT - CCSM wait for interrupt - 8 - 1 - - - PNDWT - CCSM wait for end of transfer - 9 - 1 - - - CCSMEN - Command channel state machine - 10 - 1 - - - IOSUSP - SD I/O suspend command - 11 - 1 - - - - - RSPCMD - RSPCMD - SDIO command register - 0x10 - 0x20 - read-only - 0x00000000 - - - RSPCMD - RSPCMD - 0 - 6 - - - - - RSP1 - RSP1 - Bits 31:0 = CARDSTATUS1 - 0x14 - 0x20 - read-only - 0x00000000 - - - CARDSTS1 - CARDSTATUS1 - 0 - 32 - - - - - RSP2 - RSP2 - Bits 31:0 = CARDSTATUS2 - 0x18 - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS2 - 0 - 32 - - - - - RSP3 - RSP3 - Bits 31:0 = CARDSTATUS3 - 0x1C - 0x20 - read-only - 0x00000000 - - - CARDSTS3 - CARDSTATUS3 - 0 - 32 - - - - - RSP4 - RSP4 - Bits 31:0 = CARDSTATUS4 - 0x20 - 0x20 - read-only - 0x00000000 - - - CARDSTS4 - CARDSTATUS4 - 0 - 32 - - - - - DTTMR - DTTMR - Bits 31:0 = TIMEOUT: Data timeout - period - 0x24 - 0x20 - read-write - 0x00000000 - - - TIMEOUT - Data timeout period - 0 - 32 - - - - - DTLEN - DTLEN - Bits 24:0 = DATALENGTH: Data length - value - 0x28 - 0x20 - read-write - 0x00000000 - - - DTLEN - Data length value - 0 - 25 - - - - - DTCTRL - DTCTRL - SDIO data control register - (SDIO_DCTRL) - 0x2C - 0x20 - read-write - 0x00000000 - - - TFREN - DTEN - 0 - 1 - - - TFRDIR - DTDIR - 1 - 1 - - - TFRMODE - DTMODE - 2 - 1 - - - DMAEN - DMAEN - 3 - 1 - - - BLKSIZE - DBLOCKSIZE - 4 - 4 - - - RDWTSTART - PWSTART - 8 - 1 - - - RDWTSTOP - PWSTOP - 9 - 1 - - - RDWTMODE - RWMOD - 10 - 1 - - - IOEN - SD I/O function enable - 11 - 1 - - - - - DTCNT - DTCNT - Bits 24:0 = DATACOUNT: Data count - value - 0x30 - 0x20 - read-only - 0x00000000 - - - CNT - Data count value - 0 - 25 - - - - - STS - STS - SDIO status register - (SDIO_STS) - 0x34 - 0x20 - read-only - 0x00000000 - - - CMDFAIL - Command crc fail - 0 - 1 - - - DTFAIL - Data crc fail - 1 - 1 - - - CMDTIMEOUT - Command timeout - 2 - 1 - - - DTTIMEOUT - Data timeout - 3 - 1 - - - TXERRU - Tx under run error - 4 - 1 - - - RXERRO - Rx over run error - 5 - 1 - - - CMDRSPCMPL - Command response complete - 6 - 1 - - - CMDCMPL - Command sent - 7 - 1 - - - DTCMPL - Data sent - 8 - 1 - - - SBITERR - Start bit error - 9 - 1 - - - DTBLKCMPL - Data block sent - 10 - 1 - - - DOCMD - Command transfer in progress - 11 - 1 - - - DOTX - Data transmit in progress - 12 - 1 - - - DORX - Data receive in progress - 13 - 1 - - - TXBUFH - Tx buffer half empty - 14 - 1 - - - RXBUFH - Rx buffer half empty - 15 - 1 - - - TXBUFF - Tx buffer full - 16 - 1 - - - RXBUFF - Rx buffer full - 17 - 1 - - - TXBUFE - Tx buffer empty - 18 - 1 - - - RXBUFE - Rx buffer empty - 19 - 1 - - - TXBUF - Tx data vaild - 20 - 1 - - - RXBUF - Rx data vaild - 21 - 1 - - - IOIF - SD I/O interrupt - 22 - 1 - - - - - INTCLR - INTCLR - SDIO interrupt clear register - (SDIO_INTCLR) - 0x38 - 0x20 - read-write - 0x00000000 - - - CMDFAIL - Command crc fail flag clear - 0 - 1 - - - DTFAIL - Data crc fail flag clear - 1 - 1 - - - CMDTIMEOUT - Command timeout flag clear - 2 - 1 - - - DTTIMEOUT - Data timeout flag clear - 3 - 1 - - - TXERRU - Tx under run error flag clear - 4 - 1 - - - RXERRU - Rx over run error flag clear - 5 - 1 - - - CMDRSPCMPL - Command response complete flag clear - 6 - 1 - - - CMDCMPL - Command sent flag clear - 7 - 1 - - - DTCMPL - Data sent flag clear - 8 - 1 - - - SBITERR - Start bit error flag clear - 9 - 1 - - - DTBLKCMPL - Data block sent clear - 10 - 1 - - - IOIF - SD I/O interrupt flag clear - 22 - 1 - - - - - INTEN - INTEN - SDIO interrupt enable register - (SDIO_INTEN) - 0x3C - 0x20 - read-write - 0x00000000 - - - CMDFAILIEN - Command crc fail interrupt enable - 0 - 1 - - - DTFAILIEN - Data crc fail interrupt enable - 1 - 1 - - - CMDTIMEOUTIEN - Command timeout interrupt enable - 2 - 1 - - - DTTIMEOUTIEN - Data timeout interrupt enable - 3 - 1 - - - TXERRUIEN - Tx under run interrupt enable - 4 - 1 - - - RXERRUIEN - Rx over run interrupt enable - 5 - 1 - - - CMDRSPCMPLIEN - Command response complete interrupt enable - 6 - 1 - - - CMDCMPLIEN - Command sent complete interrupt enable - 7 - 1 - - - DTCMPLIEN - Data sent complete interrupt enable - 8 - 1 - - - SBITERRIEN - Start bit error interrupt enable - 9 - 1 - - - DTBLKCMPLIEN - Data block sent complete interrupt enable - 10 - 1 - - - DOCMDIEN - Command acting interrupt enable - 11 - 1 - - - DOTXIEN - Data transmit acting interrupt enable - 12 - 1 - - - DORXIEN - Data receive acting interrupt enable - 13 - 1 - - - TXBUFHIEN - Tx buffer half empty interrupt enable - 14 - 1 - - - RXBUFHIEN - Rx buffer half empty interrupt enable - 15 - 1 - - - TXBUFFIEN - Tx buffer full interrupt enable - 16 - 1 - - - RXBUFFIEN - Rx buffer full interrupt enable - 17 - 1 - - - TXBUFEIEN - Tx buffer empty interrupt enable - 18 - 1 - - - RXBUFEIEN - Rx buffer empty interrupt enable - 19 - 1 - - - TXBUFIEN - Tx buffer data vaild interrupt enable - 20 - 1 - - - RXBUFIEN - Rx buffer data vaild interrupt enable - 21 - 1 - - - IOIFIEN - SD I/O interrupt enable - 22 - 1 - - - - - BUFCNT - BUFCNT - Bits 23:0 = BUFCOUNT: Remaining number of - words to be written to or read from the - FIFO - 0x48 - 0x20 - read-only - 0x00000000 - - - CNT - FIF0COUNT - 0 - 24 - - - - - BUF - BUF - bits 31:0 = Buffer Data: Receive and transmit - buffer data - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - Buffer data - 0 - 32 - - - - - - - SDIO2 - 0x40023400 - - SDIO2 - SDIO2 global interrupt - 60 - - - - RTC - Real time clock - RTC - 0x40002800 - - 0x0 - 0x400 - registers - - - RTC - RTC global interrupt - 3 - - - - CTRLH - CTRLH - RTC Control Register High - 0x0 - 0x20 - read-write - 0x00000000 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - TAIEN - Time alarm interrupt enable - 1 - 1 - - - TSIEN - Time second interrupt enable - 2 - 1 - - - - - CTRLL - CTRLL - RTC Control Register Low - 0x4 - 0x20 - 0x00000020 - - - TSF - Time second flag - 0 - 1 - read-write - - - TAF - Time alarm flag - 1 - 1 - read-write - - - OVFF - Overflow Flag - 2 - 1 - read-write - - - UPDF - RTC update finish - 3 - 1 - read-write - - - CFGEN - RTC configuration enable - 4 - 1 - read-write - - - CFGF - RTC configuration finish - 5 - 1 - read-only - - - - - DIVH - DIVH - RTC Divider Register - High - 0x8 - 0x20 - write-only - 0x00000000 - - - DIV - RTC divider high - 0 - 4 - - - - - DIVL - DIVL - RTC Divider Register - Low - 0xC - 0x20 - write-only - 0x8000 - - - DIV - RTC divider low - 0 - 16 - - - - - DIVCNTH - DIVCNTH - RTC Divider Register High - 0x10 - 0x20 - read-write - 0x00000000 - - - DIVCNT - RTC divider register high - 0 - 4 - - - - - DIVCNTL - DIVCNTL - RTC Divider Register Low - 0x14 - 0x20 - read-write - 0x8000 - - - DIVCNT - RTC divider register low - 0 - 16 - - - - - CNTH - CNTH - RTC Counter Register High - 0x18 - 0x20 - read-write - 0x00000000 - - - CNT - RTC counter register high - 0 - 16 - - - - - CNTL - CNTL - RTC Counter Register Low - 0x1C - 0x20 - read-write - 0x00000000 - - - CNT - RTC counter register low - 0 - 16 - - - - - TAH - TAH - RTC Alarm Register High - 0x20 - 0x20 - write-only - 0xFFFF - - - TA - Time alarm register high - 0 - 16 - - - - - TAL - TAL - Time alarm register low - 0x24 - 0x20 - write-only - 0xFFFF - - - TA - RTC alarm register low - 0 - 16 - - - - - - - BPR - Battery powered register - BPR - 0x40006C04 - - 0x0 - 0x3FC - registers - - - - DT1 - DT1 - Battery powered domain data - register (BPR_DTx) - 0x0 - 0x20 - read-write - 0x00000000 - - - DT1 - BPR data1 - 0 - 16 - - - - - DT2 - DT2 - Battery powered domain data - register (BPR_DTx) - 0x4 - 0x20 - read-write - 0x00000000 - - - DT2 - BPR data2 - 0 - 16 - - - - - DT3 - DT3 - Battery powered domain data - register (BPR_DTx) - 0x8 - 0x20 - read-write - 0x00000000 - - - DT3 - BPR data3 - 0 - 16 - - - - - DT4 - DT4 - Battery powered domain data - register (BPR_DTx) - 0xC - 0x20 - read-write - 0x00000000 - - - DT4 - BPR data4 - 0 - 16 - - - - - DT5 - DT5 - Battery powered domain data - register (BPR_DTx) - 0x10 - 0x20 - read-write - 0x00000000 - - - DT5 - BPR data5 - 0 - 16 - - - - - DT6 - DT6 - Battery powered domain data - register (BPR_DTx) - 0x14 - 0x20 - read-write - 0x00000000 - - - DT6 - BPR data6 - 0 - 16 - - - - - DT7 - DT7 - Battery powered domain data - register (BPR_DTx) - 0x18 - 0x20 - read-write - 0x00000000 - - - DT7 - BPR data7 - 0 - 16 - - - - - DT8 - DT8 - Battery powered domain data - register (BPR_DTx) - 0x1C - 0x20 - read-write - 0x00000000 - - - DT8 - BPR data8 - 0 - 16 - - - - - DT9 - DT9 - Battery powered domain data - register (BPR_DTx) - 0x20 - 0x20 - read-write - 0x00000000 - - - DT9 - BPR data9 - 0 - 16 - - - - - DT10 - DT10 - Battery powered domain data - register (BPR_DTx) - 0x24 - 0x20 - read-write - 0x00000000 - - - DT10 - BPR data10 - 0 - 16 - - - - - DT11 - DT11 - Battery powered domain data - register (BPR_DTx) - 0x3C - 0x20 - read-write - 0x00000000 - - - DT11 - BPR data11 - 0 - 16 - - - - - DT12 - DT12 - Battery powered domain data - register (BPR_DTx) - 0x40 - 0x20 - read-write - 0x00000000 - - - DT12 - BPR data12 - 0 - 16 - - - - - DT13 - DT13 - Battery powered domain data - register (BPR_DTx) - 0x44 - 0x20 - read-write - 0x00000000 - - - DT13 - BPR data13 - 0 - 16 - - - - - DT14 - DT14 - Battery powered domain data - register (BPR_DTx) - 0x48 - 0x20 - read-write - 0x00000000 - - - DT14 - BPR data14 - 0 - 16 - - - - - DT15 - DT15 - Battery powered domain data - register (BPR_DTx) - 0x4C - 0x20 - read-write - 0x00000000 - - - DT15 - BPR data15 - 0 - 16 - - - - - DT16 - DT16 - Battery powered domain data - register (BPR_DTx) - 0x50 - 0x20 - read-write - 0x00000000 - - - DT16 - BPR data16 - 0 - 16 - - - - - DT17 - DT17 - Battery powered domain data - register (BPR_DTx) - 0x54 - 0x20 - read-write - 0x00000000 - - - DT17 - BPR data17 - 0 - 16 - - - - - DT18 - DT18 - Battery powered domain data - register (BPR_DTx) - 0x58 - 0x20 - read-write - 0x00000000 - - - DT18 - BPR data18 - 0 - 16 - - - - - DT19 - DT19 - Battery powered domain data - register (BPR_DTx) - 0x5C - 0x20 - read-write - 0x00000000 - - - DT19 - BPR data19 - 0 - 16 - - - - - DT20 - DT20 - Battery powered domain data - register (BPR_DTx) - 0x60 - 0x20 - read-write - 0x00000000 - - - DT20 - BPR data20 - 0 - 16 - - - - - DT21 - DT21 - Battery powered domain data - register (BPR_DTx) - 0x64 - 0x20 - read-write - 0x00000000 - - - DT21 - BPR data21 - 0 - 16 - - - - - DT22 - DT22 - Battery powered domain data - register (BPR_DTx) - 0x68 - 0x20 - read-write - 0x00000000 - - - DT22 - BPR data22 - 0 - 16 - - - - - DT23 - DT23 - Battery powered domain data - register (BPR_DTx) - 0x6C - 0x20 - read-write - 0x00000000 - - - DT23 - BPR data23 - 0 - 16 - - - - - DT24 - DT24 - Battery powered domain data - register (BPR_DTx) - 0x70 - 0x20 - read-write - 0x00000000 - - - DT24 - BPR data24 - 0 - 16 - - - - - DT25 - DT25 - Battery powered domain data - register (BPR_DTx) - 0x74 - 0x20 - read-write - 0x00000000 - - - DT25 - BPR data25 - 0 - 16 - - - - - DT26 - DT26 - Battery powered domain data - register (BPR_DTx) - 0x78 - 0x20 - read-write - 0x00000000 - - - DT26 - BPR data26 - 0 - 16 - - - - - DT27 - DT27 - Battery powered domain data - register (BPR_DTx) - 0x7C - 0x20 - read-write - 0x00000000 - - - DT27 - BPR data27 - 0 - 16 - - - - - DT28 - DT28 - Battery powered domain data - register (BPR_DTx) - 0x80 - 0x20 - read-write - 0x00000000 - - - DT28 - BPR data28 - 0 - 16 - - - - - DT29 - DT29 - Battery powered domain data - register (BPR_DTx) - 0x84 - 0x20 - read-write - 0x00000000 - - - DT29 - BPR data29 - 0 - 16 - - - - - DT30 - DT30 - Battery powered domain data - register (BPR_DTx) - 0x88 - 0x20 - read-write - 0x00000000 - - - DT30 - BPR data30 - 0 - 16 - - - - - DT31 - DT31 - Battery powered domain data - register (BPR_DTx) - 0x8C - 0x20 - read-write - 0x00000000 - - - DT31 - BPR data31 - 0 - 16 - - - - - DT32 - DT32 - Battery powered domain data - register (BPR_DTx) - 0x90 - 0x20 - read-write - 0x00000000 - - - DT32 - BPR data32 - 0 - 16 - - - - - DT33 - DT33 - Battery powered domain data - register (BPR_DTx) - 0x94 - 0x20 - read-write - 0x00000000 - - - DT33 - BPR data33 - 0 - 16 - - - - - DT34 - DT34 - Battery powered domain data - register (BPR_DTx) - 0x98 - 0x20 - read-write - 0x00000000 - - - DT34 - BPR data34 - 0 - 16 - - - - - DT35 - DT35 - Battery powered domain data - register (BPR_DTx) - 0x9C - 0x20 - read-write - 0x00000000 - - - DT35 - BPR data35 - 0 - 16 - - - - - DT36 - DT36 - Battery powered domain data - register (BPR_DTx) - 0xA0 - 0x20 - read-write - 0x00000000 - - - DT36 - BPR data36 - 0 - 16 - - - - - DT37 - DT37 - Battery powered domain data - register (BPR_DTx) - 0xA4 - 0x20 - read-write - 0x00000000 - - - DT37 - BPR data37 - 0 - 16 - - - - - DT38 - DT38 - Battery powered domain data - register (BPR_DTx) - 0xA8 - 0x20 - read-write - 0x00000000 - - - DT38 - BPR data38 - 0 - 16 - - - - - DT39 - DT39 - Battery powered domain data - register (BPR_DTx) - 0xAC - 0x20 - read-write - 0x00000000 - - - DT39 - BPR data39 - 0 - 16 - - - - - DT40 - DT40 - Battery powered domain data - register (BPR_DTx) - 0xB0 - 0x20 - read-write - 0x00000000 - - - DT40 - BPR data40 - 0 - 16 - - - - - DT41 - DT41 - Battery powered domain data - register (BPR_DTx) - 0xB4 - 0x20 - read-write - 0x00000000 - - - DT41 - BPR data41 - 0 - 16 - - - - - DT42 - DT42 - Battery powered domain data - register (BPR_DTx) - 0xB8 - 0x20 - read-write - 0x00000000 - - - DT42 - BPR data42 - 0 - 16 - - - - - RTCCAL - RTCCAL - RTC clock calibration register - (BPR_RTCCAL) - 0x28 - 0x20 - read-write - 0x00000000 - - - CALVAL - Calibration value - 0 - 7 - - - CALOUT - Calibration Clock Output - 7 - 1 - - - OUTEN - Output enable - 8 - 1 - - - OUTSEL - Output selection - 9 - 1 - - - CCOS - Calibration clock output selection - 10 - 1 - - - OUTM - Output mode - 11 - 1 - - - - - CTRL - CTRL - BPR control register - (BPR_CTRL) - 0x2C - 0x20 - read-write - 0x00000000 - - - TPEN - Tamper pin enable - 0 - 1 - - - TPP - TAMPER pin polarity - 1 - 1 - - - - - CTRLSTS - CTRLSTS - BPR control/status register - (BPR_CTRLSTS) - 0x30 - 0x20 - 0x00000000 - - - TPEFCLR - Tamper event flag clear - 0 - 1 - write-only - - - TPIFCLR - Tamper interrupt flag clear - 1 - 1 - write-only - - - TPIEN - Tamper pin interrupt enable - 2 - 1 - read-write - - - TPEF - Tamper event flag - 8 - 1 - read-write - - - TPIF - Tamper interrupt flag - 9 - 1 - read-write - - - - - - - WDT - Watchdog - WDT - 0x40003000 - - 0x0 - 0x400 - registers - - - - CMD - CMD - Command register - 0x0 - 0x20 - read-write - 0x00000000 - - - CMD - Command register - 0 - 16 - - - - - DIV - DIV - Division register - 0x4 - 0x20 - read-write - 0x00000000 - - - DIV - Division divider - 0 - 3 - - - - - RLD - RLD - Reload register - 0x8 - 0x20 - read-write - 0x00000FFF - - - RLD - Reload value - 0 - 12 - - - - - STS - STS - Status register - 0xC - 0x20 - read-write - 0x00000000 - - - DIVF - Division value update complete flag - 0 - 1 - - - RLDF - Reload value update complete flag - 1 - 1 - - - - - - - WWDT - Window watchdog - WWDT - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDT - Window Watchdog interrupt - 0 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - read-write - 0x0000007F - - - CNT - Decrement counter - 0 - 7 - - - WWDTEN - Window watchdog enable - 7 - 1 - - - - - CFG - CFG - Configuration register - 0x4 - 0x20 - read-write - 0x0000007F - - - WIN - Window value - 0 - 7 - - - DIV - Clock division value - 7 - 2 - - - RLDIEN - Reload counter interrupt - 9 - 1 - - - - - STS - STS - Status register - 0x8 - 0x20 - read-write - 0x00000000 - - - RLDF - Reload counter interrupt flag - 0 - 1 - - - - - - - TMR1 - Advanced timer - TIMER - 0x40012C00 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - TMR1_CH - TMR1 channel interrupt - 27 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C4IOS - Channel 4 idle output state - 14 - 1 - - - C3CIOS - Channel 3 complementary idle output state - 13 - 1 - - - C3IOS - Channel 3 idle output state - 12 - 1 - - - C2CIOS - Channel 2 complementary idle output state - 11 - 1 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3CP - Channel 3 complementary polarity - 11 - 1 - - - C3CEN - Channel 3 complementary enable - 10 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR8 - 0x40013400 - - TMR8_BRK_TMR12 - TMR8 brake interrupt and TMR12 global interrupt - 43 - - - TMR8_OVF_TMR13 - TMR8 overflow interrupt and TMR13 global interrupt - 44 - - - TMR8_TRG_HALL_TMR14 - TMR8 trigger and HALL interrupts and TMR14 global interrupt - 45 - - - TMR8_CH - TMR8 channel interrupt - 46 - - - - TMR2 - General purpose timer - TIMER - 0x40000000 - - 0x0 - 0x400 - registers - - - TMR2 - TMR2 global interrupt - 28 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PMEN - Plus Mode Enable - 10 - 1 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 32 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 32 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 32 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 32 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 32 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 32 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR3 - General purpose timer - TIMER - 0x40000400 - - 0x0 - 0x400 - registers - - - TMR3 - TMR3 global interrupt - 29 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR4 - 0x40000800 - - TMR4 - TMR4 global interrupt - 30 - - - - TMR5 - 0x40000C00 - - TMR5 - TMR5 global interrupt - 50 - - - - TMR9 - General purpose timer - TIMER - 0x40014C00 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - - - TMR12 - 0x40001800 - - TMR8_BRK_TMR12 - TMR8 brake interrupt and TMR12 global - interrupt - 43 - - - - TMR10 - General purpose timer - TIMER - 0x40015000 - - 0x0 - 0x400 - registers - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - - - TMR11 - 0x40015400 - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - - ACC - HICK Auto Clock Calibration - ACC - 0x40015800 - - 0x0 - 0x400 - registers - - - - STS - STS - status register - 0x0 - 0x20 - 0x0000 - - - RSLOST - Reference Signal Lost - read-write - 1 - 1 - - - CALRDY - Internal high-speed clock calibration ready - read-write - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x04 - 0x20 - 0x0100 - - - STEP - STEP - read-write - 8 - 4 - - - CALRDYIEN - CALRDY interrupt enable - read-write - 5 - 1 - - - EIEN - RSLOST error interrupt enable - read-write - 4 - 1 - - - ENTRIM - Enable trim - read-write - 1 - 1 - - - CALON - Calibration on - read-write - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x08 - 0x20 - 0x2080 - - - HICKTWK - Internal high-speed auto clock trimming - read-only - 8 - 6 - - - HICKCAL - Internal high-speed auto clock calibration - read-only - 0 - 8 - - - - - C1 - C1 - compare value 1 - 0x0C - 0x20 - 0x1F2C - - - C1 - Compare 1 - read-write - 0 - 16 - - - - - C2 - C2 - compare value 2 - 0x10 - 0x20 - 0x1F40 - - - C2 - Compare 2 - read-write - 0 - 16 - - - - - C3 - C3 - compare value 3 - 0x14 - 0x20 - 0x1F54 - - - C3 - Compare 3 - read-write - 0 - 16 - - - - - - - TMR13 - 0x40001C00 - - TMR8_OVF_TMR13 - TMR8 overflow interrupt and TMR13 global - interrupt - 44 - - - - TMR14 - 0x40002000 - - TMR8_TRG_HALL_TMR14 - TMR8 trigger and HALL interrupts and - TMR14 global interrupt - 45 - - - - TMR6 - Basic timer - TIMER - 0x40001000 - - 0x0 - 0x400 - registers - - - TMR6 - TMR6 global interrupt - 54 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - PTOS - Primary TMR output selection - 4 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - - - TMR7 - 0x40001400 - - TMR7 - TMR7 global interrupt - 55 - - - - I2C1 - Inter integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1_EVT - I2C1 event interrupt - 31 - - - I2C1_ERR - I2C1 error interrupt - 32 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - RESET - I2C peripheral reset - 15 - 1 - - - SMBALERT - SMBus alert pin set - 13 - 1 - - - PECTEN - Request PEC transmission enable - 12 - 1 - - - MACKCTRL - Master receiving mode acknowledge control - 11 - 1 - - - ACKEN - Acknowledge enable - 10 - 1 - - - GENSTOP - Stop generation - 9 - 1 - - - GENSTART - Start generation - 8 - 1 - - - STRETCH - Clock stretching mode - 7 - 1 - - - GCAEN - General call address enable - 6 - 1 - - - PECEN - PEC calculation enable - 5 - 1 - - - ARPEN - SMBus address resolution protocol enable - 4 - 1 - - - SMBMODE - SMBus device mode - 3 - 1 - - - PERMODE - I2C peripheral mode - 1 - 1 - - - I2CEN - Peripheral enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - DMAEND - DMA transfer end indication - 12 - 1 - - - DMAEN - DMA transfer enable - 11 - 1 - - - DATAIEN - Data transmission interrupt enable - 10 - 1 - - - EVTIEN - Event interrupt enable - 9 - 1 - - - ERRIEN - Error interrupt enable - 8 - 1 - - - CLKFREQ - Input clock frequency - 0 - 8 - - - - - OADDR1 - OADDR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - ADDR1MODE - Address mode - 15 - 1 - - - ADDR1 - Own address 1 - 0 - 10 - - - - - OADDR2 - OADDR2 - Own address register 2 - 0xC - 0x20 - read-write - 0x0000 - - - ADDR2 - Own address 2 - 1 - 7 - - - ADDR2EN - Own address 2 enable - 0 - 1 - - - - - DT - DT - Data register - 0x10 - 0x20 - read-write - 0x0000 - - - DT - data register - 0 - 8 - - - - - STS1 - STS1 - Status register 1 - 0x14 - 0x20 - 0x0000 - - - ALERTF - SMBus alert - 15 - 1 - read-write - - - TMOUT - Timeout error - 14 - 1 - read-write - - - PECERR - PEC receive error - 12 - 1 - read-write - - - OUF - Overflow or underflow - 11 - 1 - read-write - - - ACKFAIL - Acknowledge failure - 10 - 1 - read-write - - - ARLOST - Arbitration lost (master - mode) - 9 - 1 - read-write - - - BUSERR - Bus error - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - (transmitters) - 7 - 1 - read-only - - - RDBF - Receive data buffer full - (receivers) - 6 - 1 - read-only - - - STOPF - Stop detection (slave - mode) - 4 - 1 - read-only - - - ADDRHF - address header match (Master - mode) - 3 - 1 - read-only - - - TDC - Transmit data complete - 2 - 1 - read-only - - - ADDR7F - Address sent (master mode)/matched - (slave mode) - 1 - 1 - read-only - - - STARTF - Start bit (Master mode) - 0 - 1 - read-only - - - - - STS2 - STS2 - Status register 2 - 0x18 - 0x20 - read-only - 0x0000 - - - PECVAL - PEC value - 8 - 8 - - - ADDR2F - Received address 2 - 7 - 1 - - - HOSTADDRF - SMBus host address receiving - 6 - 1 - - - DEVADDRF - SMBus device address receiving - 5 - 1 - - - GCADDRF - General call address reception - 4 - 1 - - - DIRF - Transmission direction - 2 - 1 - - - BUSYF - Bus busy - 1 - 1 - - - TRMODE - Transmission mode - 0 - 1 - - - - - CLKCTRL - CLKCTRL - Clock control register - 0x1C - 0x20 - read-write - 0x0000 - - - SPEEDMODE - Speed mode selection - 15 - 1 - - - DUTYMODE - Fast mode duty cycle - 14 - 1 - - - SPEED - I2C bus speed config - 0 - 12 - - - - - TMRISE - TMRISE - TRISE register - 0x20 - 0x20 - read-write - 0x0002 - - - RISETIME - I2C bus rise time - 0 - 6 - - - - - - - I2C2 - 0x40005800 - - I2C2_EVT - I2C2 event interrupt - 33 - - - I2C2_ERR - I2C2 error interrupt - 34 - - - - I2C3 - 0x40015C00 - - I2C3_EVT - I2C3 event interrupt - 61 - - - I2C3_ERR - I2C3 error interrupt - 62 - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global interrupt - 35 - - - - CTRL1 - CTRL1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SLBEN - Single line bidirectional half-duplex enable - 15 - 1 - - - SLBTD - Single line bidirectional half-duplex transmission direction - 14 - 1 - - - CCEN - CRC calculation enable - 13 - 1 - - - NTC - Next transmission CRC - 12 - 1 - - - FBN - frame bit num - 11 - 1 - - - ORA - Only receive active - 10 - 1 - - - SWCSEN - Software CS enable - 9 - 1 - - - SWCSIL - Software CS internal level - 8 - 1 - - - LTF - LSB transmit first - 7 - 1 - - - SPIEN - SPI enable - 6 - 1 - - - MDIV2_0 - Master clock frequency division bit2-0 - 3 - 3 - - - MSTEN - Master enable - 2 - 1 - - - CLKPOL - Clock polarity - 1 - 1 - - - CLKPHA - Clock phase - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MDIV3 - Master clock frequency division bit3 - 8 - 1 - - - TDBEIE - Transmit data buffer empty interrupt enable - 7 - 1 - - - RDBFIE - Receive data buffer full interrupt enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - HWCSOE - Hardware CS output enable - 2 - 1 - - - DMATEN - DMA transmit enable - 1 - 1 - - - DMAREN - DMA receive enable - 0 - 1 - - - - - STS - STS - status register - 0x8 - 0x20 - 0x0002 - - - BF - Busy flag - 7 - 1 - read-only - - - ROERR - Receiver overflow error - 6 - 1 - read-only - - - MMERR - Master mode error - 5 - 1 - read-only - - - CCERR - CRC calculation error - 4 - 1 - read-write - - - TUERR - Transmitter underload error - 3 - 1 - read-only - - - ACS - Audio channel state - 2 - 1 - read-only - - - TDBE - Transmit data buffer empty - 1 - 1 - read-only - - - RDBF - Receive data buffer full - 0 - 1 - read-only - - - - - DT - DT - data register - 0xC - 0x20 - read-write - 0x0000 - - - DT - Data value - 0 - 16 - - - - - CPOLY - CPOLY - CRC polynomial register - 0x10 - 0x20 - read-write - 0x0007 - - - CPOLY - CRC polynomial - 0 - 16 - - - - - RCRC - RCRC - Receive CRC register - 0x14 - 0x20 - read-only - 0x0000 - - - RCRC - Receive CRC - 0 - 16 - - - - - TCRC - TCRC - Transmit CRC register - 0x18 - 0x20 - read-only - 0x0000 - - - TCRC - Transmit CRC - 0 - 16 - - - - - I2SCTRL - I2SCTRL - I2S control register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SMSEL - I2S mode select - 11 - 1 - - - I2SEN - I2S Enable - 10 - 1 - - - OPERSEL - I2S operation select - 8 - 2 - - - PCMFSSEL - PCM frame synchronization select - 7 - 1 - - - STDSEL - I2S standard select - 4 - 2 - - - I2SCLKPOL - I2S clock polarity - 3 - 1 - - - I2SDBN - I2S data bit num - 1 - 2 - - - I2SCBN - I2S channel bit num - 0 - 1 - - - - - I2SCLK - I2SCLK - I2S clock register - 0x20 - 0x20 - read-write - 00000010 - - - I2SDIV9_8 - I2S division bit9 and bit8 - 10 - 2 - - - I2SMCLKOE - I2S master clock output enable - 9 - 1 - - - I2SODD - Odd result for I2S division - 8 - 1 - - - I2SDIV7_0 - I2S division bit7 to bit0 - 0 - 8 - - - - - - - SPI2 - 0x40003800 - - SPI2 - SPI2 global interrupt - 36 - - - - SPI3 - 0x40003C00 - - SPI3 - SPI3 global interrupt - 51 - - - - SPI4 - 0x40004000 - - SPI4 - SPI4 global interrupt - 63 - - - - I2S2_EXT - 0x40016C00 - - - I2S3_EXT - 0x40017000 - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40013800 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global interrupt - 37 - - - - STS - STS - Status register - 0x0 - 0x20 - 0x00C0 - - - CTSCF - CTS change flag - 9 - 1 - read-write - - - BFF - Break frame flag - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - 7 - 1 - read-only - - - TDC - Transmit data complete - 6 - 1 - read-write - - - RDBF - Receive data buffer full - 5 - 1 - read-write - - - IDLEF - IDLE flag - 4 - 1 - read-only - - - ROERR - Receiver overflow error - 3 - 1 - read-only - - - NERR - Noise error - 2 - 1 - read-only - - - FERR - Framing error - 1 - 1 - read-only - - - PERR - Parity error - 0 - 1 - read-only - - - - - DT - DT - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DT - Data value - 0 - 9 - - - - - BAUDR - BAUDR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV - Division - 0 - 16 - - - - - CTRL1 - CTRL1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - UEN - USART enable - 13 - 1 - - - DBN - Data bit num - 12 - 1 - - - WUM - Wake up mode - 11 - 1 - - - PEN - Parity enable - 10 - 1 - - - PSEL - Parity selection - 9 - 1 - - - PERRIEN - PERR interrupt enable - 8 - 1 - - - TDBEIEN - TDBE interrupt enable - 7 - 1 - - - TDCIEN - TDC interrupt enable - 6 - 1 - - - RDBFIEN - RDBF interrupt enable - 5 - 1 - - - IDLEIEN - IDLE interrupt enable - 4 - 1 - - - TEN - Transmitter enable - 3 - 1 - - - REN - Receiver enable - 2 - 1 - - - RM - Receiver mute - 1 - 1 - - - SBF - Send break frame - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - LINEN - LIN mode enable - 14 - 1 - - - STOPBN - STOP bit num - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CLKPOL - Clock polarity - 10 - 1 - - - CLKPHA - Clock phase - 9 - 1 - - - LBCP - Last bit clock pulse - 8 - 1 - - - BFIEN - Break frame interrupt enable - 6 - 1 - - - BFBN - Break frame bit num - 5 - 1 - - - ID - USART identification - 0 - 4 - - - - - CTRL3 - CTRL3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - CTSCFIEN - CTSCF interrupt enable - 10 - 1 - - - CTSEN - CTS enable - 9 - 1 - - - RTSEN - RTS enable - 8 - 1 - - - DMATEN - DMA transmitter enable - 7 - 1 - - - DMAREN - DMA receiver enable - 6 - 1 - - - SCMEN - Smartcard mode enable - 5 - 1 - - - SCNACKEN - Smartcard NACK enable - 4 - 1 - - - SLBEN - Single line bidirectional half-duplex enable - 3 - 1 - - - IRDALP - IrDA low-power mode - 2 - 1 - - - IRDAEN - IrDA enable - 1 - 1 - - - ERRIEN - Error interrupt enable - 0 - 1 - - - - - GDIV - GDIV - Guard time and division register - 0x18 - 0x20 - read-write - 0x0000 - - - SCGT - Smart card guard time value - 8 - 8 - - - ISDIV - IrDA/smartcard division value - 0 - 8 - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global interrupt - 38 - - - - USART3 - 0x40004800 - - USART3 - USART3 global interrupt - 39 - - - - USART6 - 0x40016000 - - USART6 - USART6 global interrupt - 76 - - - - ADC1 - Analog to digital converter - ADC - 0x40012400 - - 0x0 - 0x400 - registers - - - ADC1_2 - ADC1 and ADC2 global interrupt - 18 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - CCE - Channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - MSSEL - Master slave mode select - 16 - 4 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - CCEIEN - Channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - OCTESEL_H - High bit of trigger event select for ordinary channels conversion - 25 - 1 - - - PCTESEL_H - High bit of trigger event select for preempted channels conversion - 24 - 1 - - - ITSRVEN - Internal temperature sensor and VINTRV enable - 23 - 1 - - - OCSWTRG - Conversion trigger by software of ordinary channels - 22 - 1 - - - PCSWTRG - Conversion trigger by software of preempted channels - 21 - 1 - - - OCTEN - Trigger mode enable for ordinary channels conversion - 20 - 1 - - - OCTESEL_L - Low bit of trigger event select for ordinary channels conversion - 17 - 3 - - - PCTEN - Trigger mode enable for preempted channels conversion - 15 - 1 - - - PCTESEL_L - Low bit of trigger event select for preempted channels conversion - 12 - 3 - - - DTALIGN - Data alignment - 11 - 1 - - - OCDMAEN - DMA transfer enable of ordinary channels - 8 - 1 - - - ADCALINIT - initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 12 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 12 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 4 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ADC2ODT - ADC2 conversion data of ordinary channel - 16 - 16 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - - - ADC2 - Analog to digital converter - ADC - 0x40012800 - - 0x0 - 0x400 - registers - - - ADC1_2 - ADC1 and ADC2 global interrupt - 18 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - CCE - Channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - CCEIEN - Channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - OCTESEL_H - High bit of trigger event select for ordinary channels conversion - 25 - 1 - - - PCTESEL_H - High bit of trigger event select for preempted channels conversion - 24 - 1 - - - OCSWTRG - Conversion trigger by software of ordinary channels - 22 - 1 - - - PCSWTRG - Conversion trigger by software of preempted channels - 21 - 1 - - - OCTEN - Trigger mode enable for ordinary channels conversion - 20 - 1 - - - OCTESEL_L - Low bit of trigger event select for ordinary channels conversion - 17 - 3 - - - PCTEN - Trigger mode enable for preempted channels conversion - 15 - 1 - - - PCTESEL_L - Low bit of trigger event select for preempted channels conversion - 12 - 3 - - - DTALIGN - Data alignment - 11 - 1 - - - ADCALINIT - initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 12 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 12 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 4 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - - - ADC3 - Analog to digital converter - ADC - 0x40013C00 - - 0x0 - 0x400 - registers - - - ADC3 - ADC3 global interrupt - 47 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - CCE - Channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - CCEIEN - Channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - OCTESEL_H - High bit of trigger event select for ordinary channels conversion - 25 - 1 - - - PCTESEL_H - High bit of trigger event select for preempted channels conversion - 24 - 1 - - - OCSWTRG - Conversion trigger by software of ordinary channels - 22 - 1 - - - PCSWTRG - Conversion trigger by software of preempted channels - 21 - 1 - - - OCTEN - Trigger mode enable for ordinary channels conversion - 20 - 1 - - - OCTESEL_L - Low bit of trigger event select for ordinary channels conversion - 17 - 3 - - - PCTEN - Trigger mode enable for preempted channels conversion - 15 - 1 - - - PCTESEL_L - Low bit of trigger event select for preempted channels conversion - 12 - 3 - - - DTALIGN - Data alignment - 11 - 1 - - - OCDMAEN - DMA transfer enable of ordinary channels - 8 - 1 - - - ADCALINIT - initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 12 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 12 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 4 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - - - CAN1 - Can controller area network - CAN - 0x40006400 - - 0x0 - 0x400 - registers - - - USBFS_H_CAN1_TX - CAN1 TX interrupt - 19 - - - USBFS_L_CAN1_RX0 - CAN1 RX0 interrupt - 20 - - - CAN_RX1 - CAN1 RX1 interrupt - 21 - - - CAN_SE - CAN1 SE interrupt - 22 - - - - MCTRL - MCTRL - Main control register - 0x0 - 0x20 - read-write - 0x00010002 - - - PTD - Prohibit transmission when debug - 16 - 1 - - - SPRST - Software partial reset - 15 - 1 - - - TTCEN - Time triggered communication mode enable - 7 - 1 - - - AEBOEN - Automatic exit bus-off enable - 6 - 1 - - - AEDEN - Automatic exit doze mode enable - 5 - 1 - - - PRSFEN - Prohibit retransmission when sending fails enable - 4 - 1 - - - MDRSEL - Message discarding rule select when overflow - 3 - 1 - - - MMSSR - Multiple message sending sequence rule - 2 - 1 - - - DZEN - Doze mode enable - 1 - 1 - - - FZEN - Freeze mode enable - 0 - 1 - - - - - MSTS - MSTS - Main status register - 0x4 - 0x20 - 0x00000C02 - - - REALRX - Real time level of RX pin - 11 - 1 - read-only - - - LSAMPRX - Last sample level of RX pin - 10 - 1 - read-only - - - CURS - Currently receiving status - 9 - 1 - read-only - - - CUSS - Currently sending status - 8 - 1 - read-only - - - EDZIF - Enter doze mode interrupt flag - 4 - 1 - read-write - - - QDZIF - Quit doze mode interrupt flag - 3 - 1 - read-write - - - EOIF - Error occur Interrupt flag - 2 - 1 - read-write - - - DZC - Doze mode confirm - 1 - 1 - read-only - - - FZC - Freeze mode confirm - 0 - 1 - read-only - - - - - TSTS - TSTS - Transmit status register - 0x8 - 0x20 - 0x1C000000 - - - TM2LPF - Transmit mailbox 2 lowest priority flag - 31 - 1 - read-only - - - TM1LPF - Transmit mailbox 1 lowest priority flag - 30 - 1 - read-only - - - TM0LPF - Transmit mailbox 0 lowest priority flag - 29 - 1 - read-only - - - TM2EF - Transmit mailbox 2 empty flag - 28 - 1 - read-only - - - TM1EF - Transmit mailbox 1 empty flag - 27 - 1 - read-only - - - TM0EF - Transmit mailbox 0 empty flag - 26 - 1 - read-only - - - TMNR - Transmit Mailbox number record - 24 - 2 - read-only - - - TM2CT - Transmit mailbox 2 cancel transmission - 23 - 1 - read-write - - - TM2TEF - Transmit mailbox 2 transmission error flag - 19 - 1 - read-write - - - TM2ALF - Transmit mailbox 2 arbitration lost flag - 18 - 1 - read-write - - - TM2TSF - Transmit mailbox 2 transmission success flag - 17 - 1 - read-write - - - TM2TCF - transmit mailbox 2 transmission complete flag - 16 - 1 - read-write - - - TM1CT - Transmit mailbox 1 cancel transmission - 15 - 1 - read-write - - - TM1TEF - Transmit mailbox 1 transmission error flag - 11 - 1 - read-write - - - TM1ALF - Transmit mailbox 1 arbitration lost flag - 10 - 1 - read-write - - - TM1TSF - Transmit mailbox 1 transmission success flag - 9 - 1 - read-write - - - TM1TCF - Transmit mailbox 1 transmission complete flag - 8 - 1 - read-write - - - TM0CT - Transmit mailbox 0 cancel transmission - 7 - 1 - read-write - - - TM0TEF - Transmit mailbox 0 transmission error flag - 3 - 1 - read-write - - - TM0ALF - Transmit mailbox 0 arbitration lost flag - 2 - 1 - read-write - - - TM0TSF - Transmit mailbox 0 transmission success flag - 1 - 1 - read-write - - - TM0TCF - Transmit mailbox 0 transmission complete flag - 0 - 1 - read-write - - - - - RF0 - RF0 - Receive FIFO 0 register - 0xC - 0x20 - 0x00000000 - - - RF0R - Receive FIFO 0 release - 5 - 1 - read-write - - - RF0OF - Receive FIFO 0 overflow flag - 4 - 1 - read-write - - - RF0FF - Receive FIFO 0 full flag - 3 - 1 - read-write - - - RF0MN - Receive FIFO 0 message num - 0 - 2 - read-only - - - - - RF1 - RF1 - Receive FIFO 1 register - 0x10 - 0x20 - 0x00000000 - - - RF1R - Receive FIFO 1 release - 5 - 1 - read-write - - - RF1OF - Receive FIFO 1 overflow flag - 4 - 1 - read-write - - - RF1FF - Receive FIFO 1 full flag - 3 - 1 - read-write - - - RF1MN - Receive FIFO 1 message num - 0 - 2 - read-only - - - - - INTEN - INTEN - Interrupt enable register - 0x14 - 0x20 - read-write - 0x00000000 - - - EDZIEN - Enter doze mode interrupt enable - 17 - 1 - - - QDZIEN - Quit doze mode interrupt enable - 16 - 1 - - - EOIEN - Error occur interrupt enable - 15 - 1 - - - ETRIEN - Error type record interrupt enable - 11 - 1 - - - BOIEN - Bus-off interrupt enable - 10 - 1 - - - EPIEN - Error passive interrupt enable - 9 - 1 - - - EAIEN - Error active interrupt enable - 8 - 1 - - - RF1OIEN - Receive FIFO 1 overflow interrupt enable - 6 - 1 - - - RF1FIEN - Receive FIFO 1 full interrupt enable - 5 - 1 - - - RF1MIEN - FIFO 1 receive message interrupt enable - 4 - 1 - - - RF0OIEN - Receive FIFO 0 overflow interrupt enable - 3 - 1 - - - RF0FIEN - Receive FIFO 0 full interrupt enable - 2 - 1 - - - RF0MIEN - FIFO 0 receive message interrupt enable - 1 - 1 - - - TCIEN - Transmission complete interrupt enable - 0 - 1 - - - - - ESTS - ESTS - Error status register - 0x18 - 0x20 - 0x00000000 - - - REC - Receive error counter - 24 - 8 - read-only - - - TEC - Transmit error counter - 16 - 8 - read-only - - - ETR - Error type record - 4 - 3 - read-write - - - BOF - Bus-off flag - 2 - 1 - read-only - - - EPF - Error passive flag - 1 - 1 - read-only - - - EAF - Error active flag - 0 - 1 - read-only - - - - - BTMG - BTMG - Bit timing register - 0x1C - 0x20 - read-write - 0x00000000 - - - LOEN - Listen-Only mode - 31 - 1 - - - LBEN - Loop back mode - 30 - 1 - - - RSAW - Resynchronization adjust width - 24 - 2 - - - BTS2 - Bit time segment 2 - 20 - 3 - - - BTS1 - Bit time segment 1 - 16 - 4 - - - BRDIV - Baud rate division - 0 - 12 - - - - - TMI0 - TMI0 - Transmit mailbox 0 identifier register - 0x180 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC0 - TMC0 - Transmit mailbox 0 data length and time stamp register - 0x184 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL0 - TMDTL0 - Transmit mailbox 0 low byte data register - 0x188 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH0 - TMDTH0 - Transmit mailbox 0 high byte data register - 0x18C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI1 - TMI1 - Transmit mailbox 1 identifier register - 0x190 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC1 - TMC1 - Transmit mailbox 1 data length and time stamp register - 0x194 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL1 - TMDTL1 - Transmit mailbox 1 low byte data register - 0x198 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH1 - TMDTH1 - Transmit mailbox 1 high byte data register - 0x19C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI2 - TMI2 - Transmit mailbox 2 identifier register - 0x1A0 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC2 - TMC2 - Transmit mailbox 2 data length and time stamp register - 0x1A4 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL2 - TMDTL2 - Transmit mailbox 2 low byte data register - 0x1A8 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH2 - TMDTH2 - Transmit mailbox 2 high byte data register - 0x1AC - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - RFI0 - RFI0 - Receive FIFO 0 register - 0x1B0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC0 - RFC0 - Receive FIFO 0 data length and time stamp register - 0x1B4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL0 - RFDTL0 - Receive FIFO 0 low byte data register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH0 - RFDTH0 - Receive FIFO 0 high byte data register - 0x1BC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - RFI1 - RFI1 - Receive FIFO 1 register - 0x1C0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC1 - RFC1 - Receive FIFO 1 data length and time stamp register - 0x1C4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL1 - RFDTL1 - Receive FIFO 1 low byte data register - 0x1C8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH1 - RFDTH1 - Receive FIFO 1 high byte data register - 0x1CC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - FCTRL - FCTRL - Filter control register - 0x200 - 0x20 - read-write - 0x00000000 - - - FCS - Filters configure switch - 0 - 1 - - - - - FMCFG - FMCFG - Filter mode config register - 0x204 - 0x20 - read-write - 0x00000000 - - - FMSEL0 - Filter mode select - 0 - 1 - - - FMSEL1 - Filter mode select - 1 - 1 - - - FMSEL2 - Filter mode select - 2 - 1 - - - FMSEL3 - Filter mode select - 3 - 1 - - - FMSEL4 - Filter mode select - 4 - 1 - - - FMSEL5 - Filter mode select - 5 - 1 - - - FMSEL6 - Filter mode select - 6 - 1 - - - FMSEL7 - Filter mode select - 7 - 1 - - - FMSEL8 - Filter mode select - 8 - 1 - - - FMSEL9 - Filter mode select - 9 - 1 - - - FMSEL10 - Filter mode select - 10 - 1 - - - FMSEL11 - Filter mode select - 11 - 1 - - - FMSEL12 - Filter mode select - 12 - 1 - - - FMSEL13 - Filter mode select - 13 - 1 - - - - - FBWCFG - FBWCFG - Filter bit width config register - 0x20C - 0x20 - read-write - 0x00000000 - - - FBWSEL0 - Filter bit width select - 0 - 1 - - - FBWSEL1 - Filter bit width select - 1 - 1 - - - FBWSEL2 - Filter bit width select - 2 - 1 - - - FBWSEL3 - Filter bit width select - 3 - 1 - - - FBWSEL4 - Filter bit width select - 4 - 1 - - - FBWSEL5 - Filter bit width select - 5 - 1 - - - FBWSEL6 - Filter bit width select - 6 - 1 - - - FBWSEL7 - Filter bit width select - 7 - 1 - - - FBWSEL8 - Filter bit width select - 8 - 1 - - - FBWSEL9 - Filter bit width select - 9 - 1 - - - FBWSEL10 - Filter bit width select - 10 - 1 - - - FBWSEL11 - Filter bit width select - 11 - 1 - - - FBWSEL12 - Filter bit width select - 12 - 1 - - - FBWSEL13 - Filter bit width select - 13 - 1 - - - - - FRF - FRF - Filter related FIFO register - 0x214 - 0x20 - read-write - 0x00000000 - - - FRFSEL0 - Filter relation FIFO select - 0 - 1 - - - FRFSEL1 - Filter relation FIFO select - 1 - 1 - - - FRFSEL2 - Filter relation FIFO select - 2 - 1 - - - FRFSEL3 - Filter relation FIFO select - 3 - 1 - - - FRFSEL4 - Filter relation FIFO select - 4 - 1 - - - FRFSEL5 - Filter relation FIFO select - 5 - 1 - - - FRFSEL6 - Filter relation FIFO select - 6 - 1 - - - FRFSEL7 - Filter relation FIFO select - 7 - 1 - - - FRFSEL8 - Filter relation FIFO select - 8 - 1 - - - FRFSEL9 - Filter relation FIFO select - 9 - 1 - - - FRFSEL10 - Filter relation FIFO select - 10 - 1 - - - FRFSEL11 - Filter relation FIFO select - 11 - 1 - - - FRFSEL12 - Filter relation FIFO select - 12 - 1 - - - FRFSEL13 - Filter relation FIFO select - 13 - 1 - - - - - FACFG - FACFG - Filter activate configuration register - 0x21C - 0x20 - read-write - 0x00000000 - - - FAEN0 - Filter activate enable - 0 - 1 - - - FAEN1 - Filter activate enable - 1 - 1 - - - FAEN2 - Filter activate enable - 2 - 1 - - - FAEN3 - Filter activate enable - 3 - 1 - - - FAEN4 - Filter activate enable - 4 - 1 - - - FAEN5 - Filter activate enable - 5 - 1 - - - FAEN6 - Filter activate enable - 6 - 1 - - - FAEN7 - Filter activate enable - 7 - 1 - - - FAEN8 - Filter activate enable - 8 - 1 - - - FAEN9 - Filter activate enable - 9 - 1 - - - FAEN10 - Filter activate enable - 10 - 1 - - - FAEN11 - Filter activate enable - 11 - 1 - - - FAEN12 - Filter activate enable - 12 - 1 - - - FAEN13 - Filter activate enable - 13 - 1 - - - - - F0FB1 - F0FB1 - Filter bank 0 filtrate bit register 1 - 0x240 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F0FB2 - F0FB2 - Filter bank 0 filtrate bit register 2 - 0x244 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB1 - F1FB1 - Filter bank 1 filtrate bit register 1 - 0x248 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB2 - F1FB2 - Filter bank 1 filtrate bit register 2 - 0x24C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB1 - F2FB1 - Filter bank 2 filtrate bit register 1 - 0x250 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB2 - F2FB2 - Filter bank 2 filtrate bit register 2 - 0x254 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB1 - F3FB1 - Filter bank 3 filtrate bit register 1 - 0x258 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB2 - F3FB2 - Filter bank 3 filtrate bit register 2 - 0x25C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB1 - F4FB1 - Filter bank 4 filtrate bit register 1 - 0x260 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB2 - F4FB2 - Filter bank 4 filtrate bit register 2 - 0x264 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB1 - F5FB1 - Filter bank 5 filtrate bit register 1 - 0x268 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB2 - F5FB2 - Filter bank 5 filtrate bit register 2 - 0x26C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB1 - F6FB1 - Filter bank 6 filtrate bit register 1 - 0x270 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB2 - F6FB2 - Filter bank 6 filtrate bit register 2 - 0x274 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB1 - F7FB1 - Filter bank 7 filtrate bit register 1 - 0x278 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB2 - F7FB2 - Filter bank 7 filtrate bit register 2 - 0x27C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB1 - F8FB1 - Filter bank 8 filtrate bit filtrate bit register 1 - 0x280 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB2 - F8FB2 - Filter bank 8 filtrate bit filtrate bit register 2 - 0x284 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB1 - F9FB1 - Filter bank 9 filtrate bit filtrate bit filtrate bit filtrate bit filtrate bit register 1 - 0x288 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB2 - F9FB2 - Filter bank 9 filtrate bit filtrate bit filtrate bit filtrate bit filtrate bit register 2 - 0x28C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB1 - F10FB1 - Filter bank 10 filtrate bit register 1 - 0x290 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB2 - F10FB2 - Filter bank 10 filtrate bit register 2 - 0x294 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB1 - F11FB1 - Filter bank 11 filtrate bit register 1 - 0x298 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB2 - F11FB2 - Filter bank 11 filtrate bit register 2 - 0x29C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB1 - F12FB1 - Filter bank 12 filtrate bit filtrate bit register 1 - 0x2A0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB2 - F12FB2 - Filter bank 12 filtrate bit filtrate bit register 2 - 0x2A4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB1 - F13FB1 - Filter bank 13 filtrate bit filtrate bit register 1 - 0x2A8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB2 - F13FB2 - Filter bank 13 filtrate bit filtrate bit register 2 - 0x2AC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - - CAN2 - 0x40006800 - - CAN2_TX - CAN2 TX interrupt - 68 - - - CAN2_RX0 - CAN2 RX0 interrupt - 69 - - - CAN2_RX1 - CAN2 RX1 interrupt - 70 - - - CAN2_SE - CAN2 SE interrupt - 71 - - - - DAC - Digital to analog converter - DAC - 0x40007400 - - 0x0 - 0x400 - registers - - - - CTRL - CTRL - Control register (DAC_CTRL) - 0x0 - 0x20 - read-write - 0x00000000 - - - D1EN - DAC1 enable - 0 - 1 - - - D1OBDIS - DAC1 output buffer disable - 1 - 1 - - - D1TRGEN - DAC1 trigger enable - 2 - 1 - - - D1TRGSEL - DAC1 trigger selection - 3 - 3 - - - D1NM - DAC1 noise/triangle wave generation enable - 6 - 2 - - - D1NBSEL - DAC1 mask/amplitude selector - 8 - 4 - - - D1DMAEN - DAC1 DMA enable - 12 - 1 - - - D2EN - DAC2 enable - 16 - 1 - - - D2OBDIS - DAC2 output buffer disable - 17 - 1 - - - D2TRGEN - DAC2 trigger enable - 18 - 1 - - - D2TRGSEL - DAC2 trigger selection - 19 - 3 - - - D2NM - DAC2 noise/triangle wave generation enable - 22 - 2 - - - D2NBSEL - DAC2 mask/amplitude selector - 24 - 4 - - - D2DMAEN - DAC2 DMA enable - 28 - 1 - - - - - SWTRG - SWTRG - DAC software trigger register(DAC_SWTRIGR) - 0x4 - 0x20 - write-only - 0x00000000 - - - D1SWTRG - DAC1 software trigger - 0 - 1 - - - D2SWTRG - DAC2 software trigger - 1 - 1 - - - - - D1DTH12R - D1DTH12R - DAC1 12-bit right-aligned data holding register(DAC_D1DTH12R) - 0x8 - 0x20 - read-write - 0x00000000 - - - D1DT12R - DAC1 12-bit right-aligned data - 0 - 12 - - - - - D1DTH12L - D1DTH12L - DAC1 12-bit left aligned data holding register (DAC_D1DTH12L) - 0xC - 0x20 - read-write - 0x00000000 - - - D1DT12L - DAC1 12-bit left-aligned data - 4 - 12 - - - - - D1DTH8R - D1DTH8R - DAC1 8-bit right aligned data holding register (DAC_D1DTH8R) - 0x10 - 0x20 - read-write - 0x00000000 - - - D1DT8R - DAC1 8-bit right-aligned data - 0 - 8 - - - - - D2DTH12R - D2DTH12R - DAC2 12-bit right aligned data holding register (DAC_D2DTH12R) - 0x14 - 0x20 - read-write - 0x00000000 - - - D2DT12R - DAC2 12-bit right-aligned - data - 0 - 12 - - - - - D2DTH12L - D2DTH12L - DAC2 12-bit left aligned data holding register (DAC_D2DTH12L) - 0x18 - 0x20 - read-write - 0x00000000 - - - D2DT12L - DAC2 12-bit left-aligned data - 4 - 12 - - - - - D2DTH8R - D2DTH8R - DAC2 8-bit right-aligned data holding register (DAC_D2DTH8R) - 0x1C - 0x20 - read-write - 0x00000000 - - - D2DT8R - DAC2 8-bit right-aligned - data - 0 - 8 - - - - - DDTH12R - DDTH12R - Dual DAC 12-bit right-aligned data holding register (DAC_DDTH12R), Bits 31:28 Reserved, Bits 15:12 Reserved - 0x20 - 0x20 - read-write - 0x00000000 - - - DD1DT12R - DAC1 12-bit right-aligned data - 0 - 12 - - - DD2DT12R - DAC2 12-bit right-aligned data - 16 - 12 - - - - - DDTH12L - DDTH12L - DUAL DAC 12-bit left aligned data holding register (DAC_DDTH12L), Bits 19:16 Reserved, Bits 3:0 Reserved - 0x24 - 0x20 - read-write - 0x00000000 - - - DD1DT12L - DAC1 12-bit left-aligned data - 4 - 12 - - - DD2DT12L - DAC2 12-bit right-aligned data - 20 - 12 - - - - - DDTH8R - DDTH8R - DUAL DAC 8-bit right aligned data holding register (DAC_DDTH8R), Bits 31:16 Reserved - 0x28 - 0x20 - read-write - 0x00000000 - - - DD1DT8R - DAC1 8-bit right-aligned data - 0 - 8 - - - DD2DT8R - DAC2 8-bit right-aligned data - 8 - 8 - - - - - D1ODT - D1ODT - DAC1 data output register (DAC_D1ODT) - 0x2C - 0x20 - read-only - 0x00000000 - - - D1ODT - DAC1 data output - 0 - 12 - - - - - D2ODT - D2ODT - DAC2 data output register (DAC_D2ODT) - 0x30 - 0x20 - read-only - 0x00000000 - - - D2ODT - DAC2 data output - 0 - 12 - - - - - - - DEBUG - Debug support - DEBUG - 0xE0042000 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - DEBUG_IDCODE - 0x0 - 0x20 - read-only - 0x0 - - - PID - PID - 0 - 32 - - - - - CTRL - CTRL - DEBUG_CTRL - 0x4 - 0x20 - read-write - 0x0 - - - SLEEP_DEBUG - SLEEP_DEBUG - 0 - 1 - - - DEEPSLEEP_DEBUG - DEEPSLEEP_DEBUG - 1 - 1 - - - STANDBY_DEBUG - STANDBY_DEBUG - 2 - 1 - - - TRACE_IOEN - TRACE_IOEN - 5 - 1 - - - TRACE_MODE - TRACE_MODE - 6 - 2 - - - WDT_PAUSE - WDT_PAUSE - 8 - 1 - - - WWDT_PAUSE - WWDT_PAUSE - 9 - 1 - - - TMR1_PAUSE - TMR1_PAUSE - 10 - 1 - - - TMR2_PAUSE - TMR2_PAUSE - 11 - 1 - - - TMR3_PAUSE - TMR3_PAUSE - 12 - 1 - - - TMR4_PAUSE - TMR4_PAUSE - 13 - 1 - - - CAN1_PAUSE - CAN1_PAUSE - 14 - 1 - - - I2C1_SMBUS_TIMEOUT - I2C1_SMBUS_TIMEOUT - 15 - 1 - - - I2C2_SMBUS_TIMEOUT - I2C2_SMBUS_TIMEOUT - 16 - 1 - - - TMR8_PAUSE - TMR8_PAUSE - 17 - 1 - - - TMR5_PAUSE - TMR5_PAUSE - 18 - 1 - - - TMR6_PAUSE - TMR6_PAUSE - 19 - 1 - - - TMR7_PAUSE - TMR7_PAUSE - 20 - 1 - - - CAN2_PAUSE - CAN2_PAUSE - 21 - 1 - - - TMR12_PAUSE - TMR12_PAUSE - 25 - 1 - - - TMR13_PAUSE - TMR13_PAUSE - 26 - 1 - - - TMR14_PAUSE - TMR14_PAUSE - 27 - 1 - - - TMR9_PAUSE - TMR9_PAUSE - 28 - 1 - - - TMR10_PAUSE - TMR10_PAUSE - 29 - 1 - - - TMR11_PAUSE - TMR11_PAUSE - 30 - 1 - - - I2C3_SMBUS_TIMEOUT - I2C3_SMBUS_TIMEOUT - 31 - 1 - - - - - - - UART4 - Universal asynchronous receiver transmitter - 0x40004C00 - - UART4 - UART4 global interrupt - 52 - - - - UART5 - Universal asynchronous receiver transmitter - 0x40005000 - - UART5 - UART5 global interrupt - 53 - - - - UART7 - Universal asynchronous receiver transmitter - 0x40016400 - - UART7 - UART7 global interrupt - 77 - - - - UART8 - Universal asynchronous receiver transmitter - 0x40016800 - - UART8 - UART8 global interrupt - 78 - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DT - DT - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DT - Data Register - 0 - 32 - - - - - CDT - CDT - Common data register - 0x4 - 0x20 - read-write - 0x00000000 - - - CDT - Common Data - 0 - 1 - - - - - CTRL - CTRL - Control register - 0x8 - 0x20 - read-write - 0x00000000 - - - RST - Reset bit - 0 - 1 - - - REVID - Reverse input data - 5 - 2 - - - REVOD - Reverse output data - 7 - 1 - - - - - IDT - IDT - Initial data register - 0x10 - 0x20 - read-write - 0xFFFFFFFF - - - IDT - Initial Data - 0 - 32 - - - - - - - FLASH - Flash memory controler - FLASH - 0x40022000 - - 0x0 - 0x400 - registers - - - FLASH - Flash global interrupt - 4 - - - - PSR - PSR - Performance selection register - 0x0 - 0x20 - 0x00000030 - - - - - UNLOCK - UNLOCK - Unlock register - 0x4 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - USD_UNLOCK - USD_UNLOCK - USD unlock register - 0x8 - 0x20 - write-only - 0x00000000 - - - USD_UKVAL - User system data Unlock key value - 0 - 32 - - - - - STS - STS - Status register - 0xC - 0x20 - 0x00000000 - - - ODF - Operate done flag - 5 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - PRGMERR - program error - 2 - 1 - read-write - - - OBF - Operate busy flag - 0 - 1 - read-only - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - USDPRGM - User system data program - 4 - 1 - - - USDERS - User system data erase - 5 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - USDULKS - User system data unlock success - 9 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR - ADDR - Address register - 0x14 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - USD - USD - User system data register - 0x1C - 0x20 - read-only - 0x03FFFFFC - - - USDERR - User system data error - 0 - 1 - - - FAP - FLASH access protection - 1 - 1 - - - nWDT_ATO_EN - WDT auto enable - 2 - 1 - - - nDEPSLP_RST - Deepsleep reset - 3 - 1 - - - nSTDBY_RST - Standby reset - 4 - 1 - - - BTOPT - boot option - 5 - 1 - - - USER_D0 - User data 0 - 10 - 8 - - - USER_D1 - User data 1 - 18 - 8 - - - - - EPPS - EPPS - Erase/program protection status register - 0x20 - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - UNLOCK2 - UNLOCK2 - Unlock 2 register - 0x44 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - STS2 - STS2 - Status 2 register - 0x4C - 0x20 - 0x00000000 - - - OBF - Operate busy flag - 0 - 1 - read-only - - - PRGMERR - program error - 2 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - ODF - Operate done flag - 5 - 1 - read-write - - - - - CTRL2 - CTRL2 - Control 2 register - 0x50 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR2 - ADDR2 - Address 2 register - 0x54 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - UNLOCK3 - UNLOCK3 - Unlock 3 register - 0x84 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - SELECT - SELECT - Select register - 0x88 - 0x20 - write-only - 0x00000000 - - - SELECT - spim type selection - 0 - 32 - - - - - STS3 - STS3 - Status 3 register - 0x8C - 0x20 - 0x00000000 - - - OBF - Operate busy flag - 0 - 1 - read-only - - - PRGMERR - program error - 2 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - ODF - Operate done flag - 5 - 1 - read-write - - - - - CTRL3 - CTRL3 - Control 3 register - 0x90 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - CHPERS - Chip erase - 2 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR3 - ADDR3 - Address 3 register - 0x94 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - DA - DA - Spim decryption address - 0x98 - 0x20 - write-only - 0x00000000 - - - FDA - Flash decryption address - 0 - 32 - - - - - SLIB_STS0 - SLIB_STS0 - sLib status 0 register - 0xCC - 0x20 - 0x00000000 - - - SLIB_ENF - sLib enabled flag - 3 - 1 - read-only - - - - - SLIB_STS1 - SLIB_STS1 - sLib status 1 register - 0xD0 - 0x20 - 0x00000000 - - - SLIB_SS - sLib start sector - 0 - 11 - read-only - - - SLIB_DAT_SS - sLib data start sector - 11 - 11 - read-only - - - SLIB_ES - sLib end sector - 22 - 10 - read-only - - - - - SLIB_PWD_CLR - SLIB_PWD_CLR - SLIB password clear register - 0xD4 - 0x20 - 0x00000000 - write-only - - - SLIB_PCLR_VAL - sLib password clear value - 0 - 32 - - - - - SLIB_MISC_STS - SLIB_MISC_STS - sLib misc status register - 0xD8 - 0x20 - 0x01000000 - - - SLIB_PWD_ERR - sLib password error - 0 - 1 - read-only - - - SLIB_PWD_OK - sLib password ok - 1 - 1 - read-only - - - SLIB_ULKF - sLib unlock flag - 2 - 1 - read-only - - - SLIB_RCNT - sLib remaining count - 16 - 9 - read-only - - - - - SLIB_SET_PWD - SLIB_SET_PWD - sLib password setting register - 0xDC - 0x20 - 0x00000000 - write-only - - - SLIB_PSET_VAL - sLib password setting val - 0 - 32 - - - - - SLIB_SET_RANGE - SLIB_SET_RANGE - Configure sLib range register - 0xE0 - 0x20 - 0x00000000 - write-only - - - SLIB_SS_SET - sLib start sector setting,valid input: 0~511 - 0 - 11 - - - SLIB_DSS_SET - sLib data start sector setting,valid input: 0~511, 0 means no data area - 11 - 11 - - - SLIB_ES_SET - sLib end sector setting,valid input: 0~511 - 22 - 10 - - - - - SLIB_UNLOCK - SLIB_UNLOCK - sLib unlock register - 0xF0 - 0x20 - 0x00000000 - write-only - - - SLIB_UKVAL - sLib unlock key value - 0 - 32 - - - - - CRC_CTRL - CRC_CTRL - CRC controler register - 0xF4 - 0x20 - 0x00000000 - write-only - - - CRC_SS - CRC start sector - 0 - 12 - - - CRC_SN - CRC sector numbler - 12 - 12 - - - CRC_STRT - CRC start - 31 - 1 - - - - - CRC_CHKR - CRC_CHKR - CRC check result register - 0xF8 - 0x20 - 0x00000000 - read-only - - - CRC_CHKR - CRC check result - 0 - 32 - - - - - - - NVIC - Nested Vectored Interrupt - Controller - NVIC - 0xE000E000 - - 0x0 - 0x1001 - registers - - - - ICTR - ICTR - Interrupt Controller Type - Register - 0x4 - 0x20 - read-only - 0x00000000 - - - INTLINESNUM - Total number of interrupt lines in - groups - 0 - 4 - - - - - STIR - STIR - Software Triggered Interrupt - Register - 0xF00 - 0x20 - write-only - 0x00000000 - - - INTID - interrupt to be triggered - 0 - 9 - - - - - ISER0 - ISER0 - Interrupt Set-Enable Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER1 - ISER1 - Interrupt Set-Enable Register - 0x104 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ICER0 - ICER0 - Interrupt Clear-Enable - Register - 0x180 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear-Enable - Register - 0x184 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x200 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x204 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending - Register - 0x280 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending - Register - 0x284 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - IABR0 - IABR0 - Interrupt Active Bit Register - 0x300 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IABR1 - IABR1 - Interrupt Active Bit Register - 0x304 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IPR0 - IPR0 - Interrupt Priority Register - 0x400 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR1 - IPR1 - Interrupt Priority Register - 0x404 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR2 - IPR2 - Interrupt Priority Register - 0x408 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR3 - IPR3 - Interrupt Priority Register - 0x40C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR4 - IPR4 - Interrupt Priority Register - 0x410 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR5 - IPR5 - Interrupt Priority Register - 0x414 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR6 - IPR6 - Interrupt Priority Register - 0x418 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR7 - IPR7 - Interrupt Priority Register - 0x41C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR8 - IPR8 - Interrupt Priority Register - 0x420 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR9 - IPR9 - Interrupt Priority Register - 0x424 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR10 - IPR10 - Interrupt Priority Register - 0x428 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR11 - IPR11 - Interrupt Priority Register - 0x42C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR12 - IPR12 - Interrupt Priority Register - 0x430 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR13 - IPR13 - Interrupt Priority Register - 0x434 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR14 - IPR14 - Interrupt Priority Register - 0x438 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - - - USBFS - Universal serial bus full-speed device - interface - USBFS - 0x40005C00 - - 0x0 - 0x400 - registers - - - - EPT0 - EPT0 - endpoint 0 register - 0x0 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT1 - EPT1 - endpoint 1 register - 0x4 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT2 - EPT2 - endpoint 2 register - 0x8 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT3 - EPT3 - endpoint 3 register - 0xC - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT4 - EPT4 - endpoint 4 register - 0x10 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT5 - EPT5 - endpoint 5 register - 0x14 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT6 - EPT6 - endpoint 6 register - 0x18 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT7 - EPT7 - endpoint 7 register - 0x1C - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - CTRL - CTRL - control register - 0x40 - 0x20 - read-write - 0x00000003 - - - CSRST - Core soft reset - 0 - 1 - - - DISUSB - Disable usb phy - 1 - 1 - - - LPM - Low power mode - 2 - 1 - - - SSP - Soft suspend config - 3 - 1 - - - GRESUME - Generate resume request - 4 - 1 - - - LSOFIEN - Lost start of frame interrupt enable - 8 - 1 - - - SOFIEN - Start of frame interrupt - enable - 9 - 1 - - - RSTIEN - Bus reset interrupt enable - 10 - 1 - - - SPIEN - Bus suspend mode interrupt - enable - 11 - 1 - - - WKIEN - Wakeup/Remote wakeup interrupt enable - 12 - 1 - - - BEIEN - Bus error interrupt enable - 13 - 1 - - - UCFORIEN - USB Core fifo overrun - interrupt enable - 14 - 1 - - - TCIEN - transmission completed interrupt - enable - 15 - 1 - - - - - INTSTS - INTSTS - interrupt status register - 0x44 - 0x20 - read-write - 0x00000000 - - - EPT_NUM - Endpoint number - 0 - 4 - - - INOUT - In/Out transaction - 4 - 1 - - - LSOF - Lost start of frame - 8 - 1 - - - SOF - start of frame - 9 - 1 - - - RST - Bus reset - 10 - 1 - - - SP - Bus suspend - 11 - 1 - - - WK - Wakeup - 12 - 1 - - - BE - Bus error - 13 - 1 - - - UCFOR - USB core fifo overrun memory - 14 - 1 - - - TC - transaction completed - 15 - 1 - - - - - SOFRNUM - SOFRNUM - frame number register - 0x48 - 0x20 - read-write - 0x0000 - - - SOFNUM - Start of frame number - 0 - 11 - - - LSOFNUM - Lost start of frame number - 11 - 2 - - - CLCK - Connect locked - 13 - 1 - - - DMSTS - DM status - 14 - 1 - - - DPSTS - DP status - 15 - 1 - - - - - DEVADDR - DEVADDR - device address - 0x4C - 0x20 - read-write - 0x0000 - - - ADDR - Host assign device address - 0 - 7 - - - CEN - USB core enable - 7 - 1 - - - - - BUFTBL - BUFTBL - Buffer table address - 0x50 - 0x20 - read-write - 0x0000 - - - BTADDR - Endpoint buffer table start address - 3 - 13 - - - - - CFG - CFG - CFG control register - 0x60 - 0x20 - read-write - 0x0000 - - - PUO - DP pullup off - 1 - 1 - - - SOFOUTEN - SOF output enable - 0 - 1 - - - - - - - ETHERNET_MAC - Ethernet: media access control - ETHERNET - 0x40028000 - - 0x0 - 0x100 - registers - - - EMAC - Ethernet mac global interrupt - 79 - - - - MACCTRL - MACCTRL - Ethernet MAC configuration register - 0x0 - 0x20 - read-write - 0x00008000 - - - RE - Receiver enable - 2 - 1 - - - TE - Transmitter enable - 3 - 1 - - - DC - Deferral check - 4 - 1 - - - BL - Back-off limit - 5 - 2 - - - ACS - Automatic pad/CRC - stripping - 7 - 1 - - - DR - Disable retry - 9 - 1 - - - IPC - IPv4 checksum offload - 10 - 1 - - - DM - Duplex mode - 11 - 1 - - - LM - Loopback mode - 12 - 1 - - - DRO - Disable receive own - 13 - 1 - - - FES - Fast EMAC speed - 14 - 1 - - - DCS - Disable carrier sense - 16 - 1 - - - IFG - Interframe gap - 17 - 3 - - - JD - Jabber disable - 22 - 1 - - - WD - Watchdog disable - 23 - 1 - - - - - MACFRMF - MACFRMF - Ethernet MAC frame filter register - 0x4 - 0x20 - read-write - 0x00000000 - - - PR - Promiscuous mode - 0 - 1 - - - HUC - Hash unicast - 1 - 1 - - - HMC - Hash multicast - 2 - 1 - - - DAIF - Destination address inverse - filtering - 3 - 1 - - - PMC - Pass multicast - 4 - 1 - - - DBF - Disable broadcast frames - 5 - 1 - - - PCF - Pass control frames - 6 - 2 - - - SAIF - Source address inverse - filtering - 8 - 1 - - - SAF - Source address filter - 9 - 1 - - - HPF - Hash or perfect filter - 10 - 1 - - - RA - Receive all - 31 - 1 - - - - - MACHTH - MACHTH - Ethernet MAC hash table high register - 0x8 - 0x20 - read-write - 0x00000000 - - - HTH - Hash table high - 0 - 32 - - - - - MACHTL - MACHTL - Ethernet MAC hash table low register - 0xC - 0x20 - read-write - 0x00000000 - - - HTL - Hash table low - 0 - 32 - - - - - MACMIIADDR - MACMIIADDR - Ethernet MAC MII address register - 0x10 - 0x20 - read-write - 0x00000000 - - - MB - MII busy - 0 - 1 - - - MW - MII write - 1 - 1 - - - CR - Clock range - 2 - 3 - - - MII - MII register - 6 - 5 - - - PA - PHY address - 11 - 5 - - - - - MACMIIDT - MACMIIDT - Ethernet MAC MII data register - 0x14 - 0x20 - read-write - 0x00000000 - - - MD - MII data - 0 - 16 - - - - - MACFCTRL - MACFCTRL - Ethernet MAC flow control register - 0x18 - 0x20 - read-write - 0x00000000 - - - FCB_BPA - Flow control busy/back pressure - activate - 0 - 1 - - - ETF - Enable transmit flow control - - 1 - 1 - - - ERF - Enable receive flow control - - 2 - 1 - - - DUP - Detect unicast pause frame - 3 - 1 - - - PLT - Pause low threshold - 4 - 2 - - - DZQP - Disable zero-quanta pause - 7 - 1 - - - PT - Pass time - 16 - 16 - - - - - MACVLT - MACVLT - Ethernet MAC VLAN tag register - 0x1C - 0x20 - read-write - 0x00000000 - - - VTI - VLAN tag identifier (for receive - frames) - 0 - 16 - - - ETV - Enable 12-bit VLAN tag comparison - 16 - 1 - - - - - MACRWFF - MACRWFF - Ethernet MAC remote wakeup frame filter register - 0x28 - 0x20 - read-write - 0x00000000 - - - MACPMTCTRLSTS - MACPMTCTRLSTS - Ethernet MAC PMT control and status register - 0x2C - 0x20 - read-write - 0x00000000 - - - PD - Power down - 0 - 1 - - - EMP - Enable magic packet - 1 - 1 - - - ERWF - Enable remote wakeup frame - 2 - 1 - - - RMP - Received magic packet - 5 - 1 - - - RRWF - Recevied remote wakeup frame - 6 - 1 - - - GUC - Global unicast - 9 - 1 - - - RWFFPR - Remote wakeup frame filter register pointer - reset - 31 - 1 - - - - - MACISTS - MACISTS - Ethernet MAC interrupt status register - 0x38 - 0x20 - read-write - 0x00000000 - - - PIS - PMT interrupt status - 3 - 1 - - - MIS - MMC interrupt status - 4 - 1 - - - MRIS - MMC receive interrupt status - 5 - 1 - - - MTIS - MMC transmit interrupt status - 6 - 1 - - - TIS - Timestamp interrupt status - 9 - 1 - - - - - MACIMR - MACIMR - Ethernet MAC interrupt mask register - 0x3C - 0x20 - read-write - 0x00000000 - - - PIM - PMT interrupt mask - 3 - 1 - - - TIM - Timestamp interrupt mask - 9 - 1 - - - - - MACA0H - MACA0H - Ethernet MAC address 0 high register - 0x40 - 0x20 - 0x0010FFFF - - - MA0H - MAC address0 high - 0 - 16 - read-write - - - AE - Address enable - 31 - 1 - read-only - - - - - MACA0L - MACA0L - Ethernet MAC address 0 low register - 0x44 - 0x20 - read-write - 0xFFFFFFFF - - - MA0L - MAC address0 low - 0 - 32 - - - - - MACA1H - MACA1H - Ethernet MAC address 1 high register - 0x48 - 0x20 - read-write - 0x0000FFFF - - - MA1H - MAC address1 high - 0 - 16 - - - MBC - Mask byte control - 24 - 6 - - - SA - Source address - 30 - 1 - - - AE - Address enable - 31 - 1 - - - - - MACA1L - MACA1L - Ethernet MAC address1 low register - 0x4C - 0x20 - read-write - 0xFFFFFFFF - - - MA1L - MAC address1 low - 0 - 32 - - - - - MACA2H - MACA2H - Ethernet MAC address 2 high register - 0x50 - 0x20 - read-write - 0x0050 - - - MA2H - MAC address 2 high - 0 - 16 - - - MBC - Mask byte control - 24 - 6 - - - SA - Source address - 30 - 1 - - - AE - Address enable - 31 - 1 - - - - - MACA2L - MACA2L - Ethernet MAC address 2 low register - 0x54 - 0x20 - read-write - 0xFFFFFFFF - - - MA2L - MAC address2 low - 0 - 31 - - - - - MACA3H - MACA3H - Ethernet MAC address 3 high register - 0x58 - 0x20 - read-write - 0x0000FFFF - - - MA3H - MAC address3 high - 0 - 16 - - - MBC - Mask byte control - 24 - 6 - - - SA - Source address - 30 - 1 - - - AE - Address enable - 31 - 1 - - - - - MACA3L - MACA3L - Ethernet MAC address 3 low register - 0x5C - 0x20 - read-write - 0xFFFFFFFF - - - MA3L - MAC address3 low - 0 - 32 - - - - - - - ETHERNET_MMC - Ethernet: MAC management counters - ETHERNET - 0x40028100 - - 0x0 - 0x100 - registers - - - - MMCCTRL - MMCCTRL - Ethernet MMC control register - 0x0 - 0x20 - read-write - 0x00000000 - - - RC - Reset counter - 0 - 1 - - - SCR - Stop counter rollover - 1 - 1 - - - RR - Reset on read - 2 - 1 - - - FMC - Freeze MMC counter - 31 - 1 - - - - - MMCRI - MMCRI - Ethernet MMC receive interrupt register - 0x4 - 0x20 - read-write - 0x00000000 - - - RFCE - Received frames CRC error - 5 - 1 - - - RFAE - Received frames alignment error - 6 - 1 - - - RGUF - Received good unicast frames - 17 - 1 - - - - - MMCTI - MMCTI - Ethernet MMC transmit interrupt register - 0x8 - 0x20 - read-write - 0x00000000 - - - TSCGFCI - Transmit single collision good frame - counter interrupt - 14 - 1 - - - TGFMSC - Transmit good frames more single - collision - 15 - 1 - - - TGF - Transmitted good frames - 21 - 1 - - - - - MMCRIM - MMCRIM - Ethernet MMC receive interrupt mask register - 0xC - 0x20 - read-write - 0x00000000 - - - RCEFCIM - Received CRC error frame counter interrupt - mask - 5 - 1 - - - RAEFACIM - Received alignment error frame alignment - counter interrupt mask - 6 - 1 - - - RUGFCIM - Received unicast good frame counter - interrupt mask - 17 - 1 - - - - - MMCTIM - MMCTIM - Ethernet MMC transmit interrupt mask register - 0x10 - 0x20 - read-write - 0x00000000 - - - TSCGFCIM - Transmit single collision good frame - counter interrupt mask - 14 - 1 - - - TMCGFCIM - Transmit multiple collision good frame - counter interrupt mask - 15 - 1 - - - TGFCIM - Transmitted good frame counter interrupt - mask - 21 - 1 - - - - - MMCTFSCC - MMCTFSCC - Ethernet MMC transmitted good frames after a single collision counter - 0x4C - 0x20 - read-only - 0x00000000 - - - TGFSCC - Transmitted good frames single - collision counter - 0 - 32 - - - - - MMCTFMSCC - MMCTFMSCC - Ethernet MMC transmitted good frames after more than a single collision - 0x50 - 0x20 - read-only - 0x00000000 - - - TGFMSCC - Transmitted good frame more single - collision counter - 0 - 32 - - - - - MMCTFCNT - MMCTFCNT - Ethernet MMC transmitted good frames counter register - 0x68 - 0x20 - read-only - 0x00000000 - - - TGFC - Transmitted good frames - counter - 0 - 32 - - - - - MMCRFCECNT - MMCRFCECNT - Ethernet MMC received frames with CRC error counter register - 0x94 - 0x20 - read-only - 0x00000000 - - - RFCEC - Received frames CRC error counter - 0 - 32 - - - - - MMCRFAECNT - MMCRFAECNT - Ethernet MMC received frames with alignment error counter register - 0x98 - 0x20 - read-only - 0x00000000 - - - RFAEC - Received frames alignment error counter - 0 - 32 - - - - - MMCRGUFCNT - MMCRGUFCNT - MMC received good unicast frames counter register - 0xC4 - 0x20 - read-only - 0x00000000 - - - RGUFC - Received good unicast frames - counter - 0 - 32 - - - - - - - ETHERNET_PTP - Ethernet: Precision time protocol - ETHERNET - 0x40028700 - - 0x0 - 0x100 - registers - - - - PTPTSCTRL - PTPTSCTRL - Ethernet PTP time stamp control register - 0x0 - 0x20 - read-write - 0x2000 - - - TE - Timestamp enable - 0 - 1 - - - TFCU - Timestamp fine or coarse - update - 1 - 1 - - - TI - Timestamp initialize - 2 - 1 - - - TU - Timestamp update - 3 - 1 - - - TITE - Timestamp interrupt trigger - enable - 4 - 1 - - - ARU - Addend register update - 5 - 1 - - - ETAF - Enable timestamp for all frames - 8 - 1 - - - TDBRC - Timestamp digital or binary - rollover control - 9 - 1 - - - EPPV2F - Enable PTP packet processing for - version2 format - 10 - 1 - - - EPPEF - Enable processing of PTP - over EMAC frames - 11 - 1 - - - EPPFSIP6U - Enable processing of PTP frames - sent over IPv6-UDP - 12 - 1 - - - EPPFSIP4U - Enable processing of PTP frames - sent over IPv4-UDP - 13 - 1 - - - ETSFEM - Enable timestamp snapshot for - event message - 14 - 1 - - - ESFMRTM - Enable snapshot for message - relevant to master - 15 - 1 - - - SPPFTS - Select PTP packet for taking snapshot - 16 - 2 - - - EMAFPFF - Enable MAC address for PTP frame filtering - 18 - 1 - - - - - PTPSSINC - PTPSSINC - Ethernet PTP subsecond increment register - 0x4 - 0x20 - read-write - 0x00000000 - - - SSIV - Sub-second increment value - 0 - 8 - - - - - PTPTSH - PTPTSH - Ethernet PTP time stamp high register - 0x8 - 0x20 - read-only - 0x00000000 - - - TS - Timestamp second - 0 - 32 - - - - - PTPTSL - PTPTSL - Ethernet PTP time stamp low register - 0xC - 0x20 - read-only - 0x00000000 - - - TSS - Timestamp subseconds - 0 - 31 - - - AST - Add or subtract time - 31 - 1 - - - - - PTPTSHUD - PTPTSHUD - Ethernet PTP time stamp high update register - 0x10 - 0x20 - read-write - 0x00000000 - - - TS - Timestamp second - 0 - 32 - - - - - PTPTSLUD - PTPTSLUD - Ethernet PTP time stamp low update register - 0x14 - 0x20 - read-write - 0x00000000 - - - TSS - Timestamp subseconds - 0 - 31 - - - AST - Add or subtract time - 31 - 1 - - - - - PTPTSAD - PTPTSAD - Ethernet PTP time stamp addend register - 0x18 - 0x20 - read-write - 0x00000000 - - - TAR - Timestamp addend register - 0 - 32 - - - - - PTPTTH - PTPTTH - Ethernet PTP target time high register - 0x1C - 0x20 - read-write - 0x00000000 - - - TTSR - Target time seconds register - 0 - 32 - - - - - PTPTTL - PTPTTL - Ethernet PTP target time low register - 0x20 - 0x20 - read-write - 0x00000000 - - - TTLR - Target timestamp low register - 0 - 32 - - - - - PTPTSSR - PTPTSSR - Ethernet PTP time stamp status register - 0x28 - 0x20 - read-only - 0x00000000 - - - TSO - Timestamp second overflow - 0 - 1 - - - TTTR - Timestamp target time reached - 1 - 1 - - - - - PTPPPSCR - PTPPPSCR - Ethernet PTP PPS control register - 0x2C - 0x20 - read-only - 0x00000000 - - - POFC - PPS Output frequency control - 0 - 4 - - - - - - - ETHERNET_DMA - Ethernet: DMA controller operation - ETHERNET - 0x40029000 - - 0x0 - 0x100 - registers - - - - DMABM - DMABM - Ethernet DMA bus mode register - 0x0 - 0x20 - read-write - 0x20101 - - - SWR - Software reset - 0 - 1 - - - DA - DMA Arbitration - 1 - 1 - - - DSL - Descriptor skip length - 2 - 5 - - - PBL - Programmable burst length - 8 - 6 - - - PR - Priority ratio - 14 - 2 - - - FB - Fixed burst - 16 - 1 - - - RDP - Rx DMA PBL - 17 - 6 - - - USP - Use separate PBL - 23 - 1 - - - PBLx8 - PNLx8 mode - 24 - 1 - - - AAB - Address-aligned beats - 25 - 1 - - - - - DMATPD - DMATPD - Ethernet DMA transmit poll demand register - 0x4 - 0x20 - read-write - 0x00000000 - - - TPD - Transmit poll demand - 0 - 32 - - - - - DMARPD - DMARPD - EHERNET DMA receive poll demand register - 0x8 - 0x20 - read-write - 0x00000000 - - - RPD - Receive poll demand - 0 - 32 - - - - - DMARDLADDR - DMARDLADDR - Ethernet DMA receive descriptor list address register - 0xC - 0x20 - read-write - 0x00000000 - - - SRL - Start of receive list - 0 - 32 - - - - - DMATDLADDR - DMATDLADDR - Ethernet DMA transmit descriptor list address register - 0x10 - 0x20 - read-write - 0x00000000 - - - STL - Start of transmit list - 0 - 32 - - - - - DMASTS - DMASTS - Ethernet DMA status register - 0x14 - 0x20 - 0x00000000 - - - TI - Transmit interrupt - 0 - 1 - read-write - - - TPS - Transmit process stopped - 1 - 1 - read-write - - - TBU - Transmit buffer unavailable - 2 - 1 - read-write - - - TJT - Transmit jabber timeout - 3 - 1 - read-write - - - OVF - Receive overflow - 4 - 1 - read-write - - - UNF - Transmit underflow - 5 - 1 - read-write - - - RI - Receive interrupt - 6 - 1 - read-write - - - RBU - Receive buffer unavailable - 7 - 1 - read-write - - - RPS - Receive process stopped - 8 - 1 - read-write - - - RWT - Receive watchdog timeout - 9 - 1 - read-write - - - ETI - Early transmit interrupt - 10 - 1 - read-write - - - FBEI - Fatal bus error interrupt - 13 - 1 - read-write - - - ERI - Early receive interrupt - 14 - 1 - read-write - - - AIS - Abnormal interrupt summary - 15 - 1 - read-write - - - NIS - Normal interrupt summary - 16 - 1 - read-write - - - RS - Receive process state - 17 - 3 - read-only - - - TS - Transmit process state - 20 - 3 - read-only - - - EB - Error bits - 23 - 3 - read-only - - - MMI - MAC MMC interrupt - 27 - 1 - read-only - - - MPI - MAC PMT interrupt - 28 - 1 - read-only - - - TTI - Timestamp trigger interrupt - 29 - 1 - read-only - - - - - DMAOPM - DMAOPM - Ethernet DMA operation mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - SSR - Start or stop receive - 1 - 1 - - - OSF - Operate on second frame - 2 - 1 - - - RTC - Receive threshold control - 3 - 2 - - - FUGF - Forward undersized good frames - 6 - 1 - - - FEF - Forward error frames - 7 - 1 - - - SSTC - Start of stop transmission command - 13 - 1 - - - TTC - Transmit threshold control - 14 - 3 - - - FTF - Flush transmit FIFO - 20 - 1 - - - TSF - Transmit store and forward - 21 - 1 - - - DFRF - Disable flushing of received - frames - 24 - 1 - - - RSF - Receive store and forward - 25 - 1 - - - DT - Disable dropping of TCP/IP - checksum error frames - 26 - 1 - - - - - DMAIE - DMAIE - Ethernet DMA interrupt enable register - 0x1C - 0x20 - read-write - 0x00000000 - - - TIE - Transmit interrupt enable - 0 - 1 - - - TSE - Transmit stopped enable - 1 - 1 - - - TUE - Transmit buffer unavailable enable - 2 - 1 - - - TJE - Transmit jabber timeout enable - 3 - 1 - - - OVE - Overflow interrupt enable - 4 - 1 - - - UNE - Underflow interrupt enable - 5 - 1 - - - RIE - Receive interrupt enable - 6 - 1 - - - RBUE - Receive buffer unavailable enable - 7 - 1 - - - RSE - Receive stopped enable - 8 - 1 - - - RWTE - receive watchdog timeout enable - 9 - 1 - - - EIE - Early transmit interrupt enable - 10 - 1 - - - FBEE - Fatal bus error enable - 13 - 1 - - - ERE - Early receive interrupt - enable - 14 - 1 - - - AIE - Abnormal interrupt enable - 15 - 1 - - - NIE - Normal interrupt enable - 16 - 1 - - - - - DMAMFBOCNT - DMAMFBOCNT - Ethernet DMA missed frame and buffer overflow counter register - 0x20 - 0x20 - read-only - 0x00000000 - - - MFC - Missed frames control - 0 - 16 - - - OBMFC - Overflow bit for missed frame - counter - 16 - 1 - - - OFC - Overflow frame counter - 17 - 11 - - - OBFOC - Overflow bit for FIFO overflow - counter - 28 - 1 - - - - - DMACTD - DMACTD - Ethernet DMA current host transmit descriptor register - 0x48 - 0x20 - read-only - 0x00000000 - - - HTDAP - Host transmit descriptor address pointer - 0 - 32 - - - - - DMACRD - DMACRD - Ethernet DMA current host receive descriptor register - 0x4C - 0x20 - read-only - 0x00000000 - - - HRDAP - Host receive descriptor address pointer - 0 - 32 - - - - - DMACTBADDR - DMACTBADDR - Ethernet DMA current host transmit buffer address register - 0x50 - 0x20 - read-only - 0x00000000 - - - HTBAP - Host transmit buffer address pointer - 0 - 32 - - - - - DMACRBADDR - DMACRBADDR - Ethernet DMA current host receive buffer address register - 0x54 - 0x20 - read-only - 0x00000000 - - - HRBAP - Host receive buffer address pointer - 0 - 32 - - - - - - - diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake new file mode 100644 index 000000000..fb45caf23 --- /dev/null +++ b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake @@ -0,0 +1,9 @@ +set(MCU_VARIANT AT32F403ACGU7) +set(JLINK_DEVICE ${MCU_VARIANT}) + +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/AT32F403AxG_FLASH.ld) +set(LD_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxG.icf) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT}) +endfunction() diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk index 58b3fdb11..e309c86bb 100644 --- a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk +++ b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk @@ -1,3 +1,4 @@ +JLINK_DEVICE = at32f403acgu7 LD_FILE = $(BOARD_PATH)/AT32F403AxG_FLASH.ld CFLAGS += \ diff --git a/hw/bsp/at32f403a_407/family.c b/hw/bsp/at32f403a_407/family.c index 23798526f..f9a6dd70d 100644 --- a/hw/bsp/at32f403a_407/family.c +++ b/hw/bsp/at32f403a_407/family.c @@ -25,8 +25,8 @@ */ #include "at32f403a_407_clock.h" -#include "bsp/board_api.h" #include "board.h" +#include "bsp/board_api.h" void usb_clock48m_select(usb_clk48_s clk_s); void uart_print_init(uint32_t baudrate); @@ -50,8 +50,7 @@ void USBFSWakeUp_IRQHandler(void) { tud_int_handler(0); } -void board_init(void) -{ +void board_init(void) { system_clock_config(); /* config nvic priority group */ @@ -62,7 +61,7 @@ void board_init(void) /* configure systick */ systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); - + /* enable usb clock */ crm_periph_clock_enable(CRM_USB_PERIPH_CLOCK, TRUE); @@ -82,7 +81,7 @@ void board_init(void) gpio_default_para_init(&gpio_led_init_struct); /* configure the led gpio */ gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; gpio_led_init_struct.gpio_pins = LED_PIN; gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; @@ -114,10 +113,8 @@ void board_init(void) * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT * @retval none */ -void usb_clock48m_select(usb_clk48_s clk_s) -{ - if(clk_s == USB_CLK_HICK) - { +void usb_clock48m_select(usb_clk48_s clk_s) { + if (clk_s == USB_CLK_HICK) { crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); /* enable the acc calibration ready interrupt */ @@ -130,11 +127,8 @@ void usb_clock48m_select(usb_clk48_s clk_s) /* open acc calibration */ acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); - } - else - { - switch(system_core_clock) - { + } else { + switch (system_core_clock) { /* 48MHz */ case 48000000: crm_usb_clock_div_set(CRM_USB_DIV_1); @@ -172,13 +166,11 @@ void usb_clock48m_select(usb_clk48_s clk_s) default: break; - } } } -void uart_print_init(uint32_t baudrate) -{ +void uart_print_init(uint32_t baudrate) { gpio_init_type gpio_init_struct; /* enable the uart and gpio clock */ crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); @@ -186,7 +178,7 @@ void uart_print_init(uint32_t baudrate) gpio_default_para_init(&gpio_init_struct); /* configure the uart tx pin */ gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_init_struct.gpio_mode = GPIO_MODE_MUX; gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; gpio_init_struct.gpio_pull = GPIO_PULL_NONE; @@ -207,8 +199,8 @@ uint32_t board_button_read(void) { size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; - volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); - uint32_t* id32 = (uint32_t*) (uintptr_t) id; + volatile uint32_t *at32_uuid = ((volatile uint32_t *) 0x1FFFF7E8); + uint32_t *id32 = (uint32_t *) (uintptr_t) id; uint8_t const len = 12; id32[0] = at32_uuid[0]; @@ -224,61 +216,57 @@ int board_uart_read(uint8_t *buf, int len) { return 0; } -int board_uart_write(void const *buf, int len) -{ - #if CFG_TUSB_OS == OPT_OS_NONE - int txsize = len; - u16 timeout = 0xffff; - while (txsize--) - { - while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) - { - timeout--; - if(timeout == 0) - { - return 0; - } +int board_uart_write(void const *buf, int len) { +#if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) { + while (usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) { + timeout--; + if (timeout == 0) { + return 0; } - PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); - buf++; } - return len; - #else - (void) buf; - (void) len; - return 0; - #endif + PRINT_UART->dt = (*((uint8_t const *) buf) & 0x01FF); + buf++; + } + return len; +#else + (void) buf; + (void) len; + return 0; +#endif } #if CFG_TUSB_OS == OPT_OS_NONE - volatile uint32_t system_ticks = 0; - void SysTick_Handler(void) - { - system_ticks++; - } +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) { + system_ticks++; +} - uint32_t board_millis(void) - { - return system_ticks; - } - - void SVC_Handler(void) - { - } +uint32_t board_millis(void) { + return system_ticks; +} - void PendSV_Handler(void) - { - } +void SVC_Handler(void) { +} + +void PendSV_Handler(void) { +} #endif void HardFault_Handler(void) { __asm("BKPT #0\n"); } -#ifdef USE_FULL_ASSERT -void assert_failed(const char *file, uint32_t line) -{ +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) { /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ diff --git a/hw/bsp/at32f403a_407/family.cmake b/hw/bsp/at32f403a_407/family.cmake new file mode 100644 index 000000000..c121b166b --- /dev/null +++ b/hw/bsp/at32f403a_407/family.cmake @@ -0,0 +1,102 @@ +include_guard() + +set(AT_FAMILY at32f403a_407) +set(AT_SDK_LIB ${TOP}/hw/mcu/artery/${AT_FAMILY}/libraries) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS AT32F403A_407 CACHE INTERNAL "") + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/startup_${AT_FAMILY}.s) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT_FAMILY}.s) + + set(LD_FILE_Clang ${LD_FILE_GNU}) + + add_library(${BOARD_TARGET} STATIC + ${AT_SDK_LIB}/cmsis/cm4/device_support/system_${AT_FAMILY}.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_gpio.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_misc.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_usart.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_acc.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_crm.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${AT_SDK_LIB}/cmsis/cm4/core_support + ${AT_SDK_LIB}/cmsis/cm4/device_support + ${AT_SDK_LIB}/drivers/inc + ) + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT_FAMILY}_clock.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT_FAMILY}_int.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_AT32F403A_407) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + ) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + + # Flashing + family_add_bin_hex(${TARGET}) + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/at32f403a_407/family.mk b/hw/bsp/at32f403a_407/family.mk index 4a1c3949c..b3210a6d4 100644 --- a/hw/bsp/at32f403a_407/family.mk +++ b/hw/bsp/at32f403a_407/family.mk @@ -1,6 +1,5 @@ # Submodules AT32F403A_407_SDK = hw/mcu/artery/at32f403a_407 -DEPS_SUBMODULES += $(AT32F403A_407_SDK) # AT32 SDK path AT32F403A_407_SDK_SRC = $(AT32F403A_407_SDK)/libraries @@ -16,7 +15,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_AT32F403A_407 LDFLAGS_GCC += \ - -flto --specs=nosys.specs + -flto --specs=nosys.specs -nostdlib -nostartfiles SRC_C += \ src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ diff --git a/hw/bsp/at32f403a_407/startup_at32f403a_407.s b/hw/bsp/at32f403a_407/startup_at32f403a_407.s index 8bb76a062..3b81f2043 100644 --- a/hw/bsp/at32f403a_407/startup_at32f403a_407.s +++ b/hw/bsp/at32f403a_407/startup_at32f403a_407.s @@ -78,7 +78,7 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array diff --git a/hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h index 599d22ffc..0a4184f34 100644 --- a/hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h @@ -109,7 +109,7 @@ #define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 #define INCLUDE_uxTaskGetStackHighWaterMark 0 #define INCLUDE_xTaskGetIdleTaskHandle 0 #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 diff --git a/hw/bsp/at32f413/at32f413_clock.h b/hw/bsp/at32f413/at32f413_clock.h index 702948364..28c47d1e6 100644 --- a/hw/bsp/at32f413/at32f413_clock.h +++ b/hw/bsp/at32f413/at32f413_clock.h @@ -41,4 +41,3 @@ void system_clock_config(void); #endif #endif /* __AT32F413_CLOCK_H */ - diff --git a/hw/bsp/at32f413/at32f413_int.c b/hw/bsp/at32f413/at32f413_int.c index 8b18bdbe1..7612e52f0 100644 --- a/hw/bsp/at32f413/at32f413_int.c +++ b/hw/bsp/at32f413/at32f413_int.c @@ -137,5 +137,3 @@ void DebugMon_Handler(void) /** * @} */ - - diff --git a/hw/bsp/at32f413/at32f413_int.h b/hw/bsp/at32f413/at32f413_int.h index 2b477475e..fbbf30dbc 100644 --- a/hw/bsp/at32f413/at32f413_int.h +++ b/hw/bsp/at32f413/at32f413_int.h @@ -53,4 +53,3 @@ void SysTick_Handler(void); #endif #endif - diff --git a/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xC_FLASH.ld b/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xC_FLASH.ld index e654b3bbc..9d95a7d3d 100644 --- a/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xC_FLASH.ld +++ b/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xC_FLASH.ld @@ -105,7 +105,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -118,7 +118,7 @@ SECTIONS _spim_init_base = LOADADDR(.spim); _spim_init_length = SIZEOF(.spim); - + .spim : { . = ALIGN(4); @@ -133,7 +133,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd b/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd deleted file mode 100644 index a4a95208e..000000000 --- a/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd +++ /dev/null @@ -1,23368 +0,0 @@ - - - - - - - - Keil - ArteryTek - AT32F413xx_v2 - AT32F413 - 1.0 - ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 200MHz, etc. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - CM4 - r0p1 - little - false - true - 4 - false - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - - PWC - Power control - PWC - 0x40007000 - - 0x0 - 0x400 - registers - - - - CTRL - CTRL - Power control register - 0x0 - 0x20 - read-write - 0x00000000 - - - LPSEL - Low power mode select when Cortex-M4F sleepdeep - 1 - 1 - - - CLSWEF - Clear SWEF flag - 2 - 1 - - - CLSEF - Clear SEF flag - 3 - 1 - - - PVMEN - Power voltage monitoring enable - 4 - 1 - - - PVMSEL - Power voltage monitoring boundary select - 5 - 3 - - - BPWEN - Battery powered domain write enable - 8 - 1 - - - - - CTRLSTS - CTRLSTS - Power control and status register - 0x4 - 0x20 - 0x00000000 - - - SWEF - Standby wake-up event flag - 0 - 1 - read-only - - - SEF - Standby mode entry flag - 1 - 1 - read-only - - - PVMOF - Power voltage monitoring output flag - 2 - 1 - read-only - - - SWPEN - Standby wake-up pin enable - 8 - 1 - read-write - - - - - - - CRM - Clock and reset management - CRM - 0x40021000 - - 0x0 - 0x400 - registers - - - CRM - CRM global interrupt - 5 - - - - CTRL - CTRL - Clock control register - 0x0 - 0x20 - 0x00000083 - - - HICKEN - High speed internal clock enable - 0 - 1 - read-write - - - HICKSTBL - High speed internal clock ready flag - 1 - 1 - read-only - - - HICKTRIM - High speed internal clock trimming - 2 - 6 - read-write - - - HICKCAL - High speed internal clock calibration - 8 - 8 - read-only - - - HEXTEN - High speed exernal crystal enable - 16 - 1 - read-write - - - HEXTSTBL - High speed exernal crystal ready flag - 17 - 1 - read-only - - - HEXTBYPS - High speed exernal crystal bypass - 18 - 1 - read-write - - - CFDEN - Clock failure detection enable - 19 - 1 - read-write - - - PLLEN - PLL enable - 24 - 1 - read-write - - - PLLSTBL - PLL clock ready flag - 25 - 1 - read-only - - - - - CFG - CFG - Clock configuration register - 0x4 - 0x20 - 0x00000000 - - - SCLKSEL - System clock select - 0 - 2 - read-write - - - SCLKSTS - System Clock select Status - 2 - 2 - read-only - - - AHBDIV - AHB division - 4 - 4 - read-write - - - APB1DIV - APB1 division - 8 - 3 - read-write - - - APB2DIV - APB2 division - 11 - 3 - read-write - - - ADCDIV1_0 - ADC division bit1 and bit0 - 14 - 2 - read-write - - - PLLRCS - PLL reference clock select - 16 - 1 - read-write - - - PLLHEXTDIV - HEXT division selection for PLL entry clock - 17 - 1 - read-write - - - PLLMULT3_0 - PLL Multiplication Factor bit3 to bit0 - 18 - 4 - read-write - - - USBDIV1_0 - USB division bit1 and bit0 - 22 - 2 - read-write - - - CLKOUT_SEL - Clock output selection bit2 to bit0 - 24 - 3 - read-write - - - USBDIV2 - USB division bit2 - 27 - 1 - read-write - - - ADCDIV2 - ADC division bit2 - 28 - 1 - read-write - - - PLLMULT5_4 - PLL Multiplication Factor bit5 and bit4 - 29 - 2 - read-write - - - PLLRANGE - PLL clock output frequency up 72MHz or not - 31 - 1 - read-write - - - - - CLKINT - CLKINT - Clock interrupt register - 0x8 - 0x20 - 0x00000000 - - - LICKSTBLF - LICK ready interrupt flag - 0 - 1 - read-only - - - LEXTSTBLF - LEXT ready interrupt flag - 1 - 1 - read-only - - - HICKSTBLF - HICK ready interrupt flag - 2 - 1 - read-only - - - HEXTSTBLF - HEXT ready interrupt flag - 3 - 1 - read-only - - - PLLSTBLF - PLL ready interrupt flag - 4 - 1 - read-only - - - CFDF - Clock failure detection interrupt flag - 7 - 1 - read-only - - - LICKSTBLIEN - LICK ready interrupt enable - 8 - 1 - read-write - - - LEXTSTBLIEN - LEXT ready interrupt enable - 9 - 1 - read-write - - - HICKSTBLIEN - HICK ready interrupt enable - 10 - 1 - read-write - - - HEXTSTBLIEN - HEXT ready interrupt enable - 11 - 1 - read-write - - - PLLSTBLIEN - PLL ready interrupt enable - 12 - 1 - read-write - - - LICKSTBLFC - LICK ready interrupt clear - 16 - 1 - write-only - - - LEXTSTBLFC - LEXT ready interrupt clear - 17 - 1 - write-only - - - HICKSTBLFC - HICK ready interrupt clear - 18 - 1 - write-only - - - HEXTSTBLFC - HEXT ready interrupt clear - 19 - 1 - write-only - - - PLLSTBLFC - PLL ready interrupt clear - 20 - 1 - write-only - - - CFDFC - Clock failure detection interrupt clear - 23 - 1 - write-only - - - - - APB2RST - APB2RST - APB2 peripheral reset register - 0xC - 0x20 - read-write - 0x000000000 - - - IOMUXRST - MUX function I/O reset - 0 - 1 - - - GPIOARST - IO port A reset - 2 - 1 - - - GPIOBRST - IO port B reset - 3 - 1 - - - GPIOCRST - IO port C reset - 4 - 1 - - - GPIODRST - IO port D reset - 5 - 1 - - - GPIOFRST - IO port F reset - 7 - 1 - - - ADC1RST - ADC1 reset - 9 - 1 - - - ADC2RST - ADC2 reset - 10 - 1 - - - TMR1RST - Timer1 reset - 11 - 1 - - - SPI1RST - SPI1 reset - 12 - 1 - - - TMR8RST - Timer8 reset - 13 - 1 - - - USART1RST - USART1 reset - 14 - 1 - - - TMR9RST - Timer9 reset - 19 - 1 - - - TMR10RST - Timer10 reset - 20 - 1 - - - TMR11RST - Timer11 reset - 21 - 1 - - - ACCRST - ACC reset - 22 - 1 - - - - - APB1RST - APB1RST - APB1 peripheral reset register - 0x10 - 0x20 - read-write - 0x00000000 - - - TMR2RST - Timer 2 reset - 0 - 1 - - - TMR3RST - Timer 3 reset - 1 - 1 - - - TMR4RST - Timer 4 reset - 2 - 1 - - - TMR5RST - Timer 5 reset - 3 - 1 - - - WWDTRST - Window watchdog timer reset - 11 - 1 - - - SPI2RST - SPI2 reset - 14 - 1 - - - USART2RST - USART 2 reset - 17 - 1 - - - USART3RST - USART 3 reset - 18 - 1 - - - UART4RST - UART 4 reset - 19 - 1 - - - UART5RST - UART 5 reset - 20 - 1 - - - I2C1RST - I2C1 reset - 21 - 1 - - - I2C2RST - I2C2 reset - 22 - 1 - - - USBRST - USB reset - 23 - 1 - - - CAN1RST - CAN1 reset - 25 - 1 - - - BPRRST - Battery powered domain register reset - 27 - 1 - - - PWCRST - Power controller reset - 28 - 1 - - - CAN2RST - CAN2 reset - 31 - 1 - - - - - AHBEN - AHBEN - AHB Peripheral Clock enable register - 0x14 - 0x20 - read-write - 0x00000014 - - - DMA1EN - DMA1 clock enable - 0 - 1 - - - DMA2EN - DMA2 clock enable - 1 - 1 - - - SRAMEN - SRAM interface clock enable - 2 - 1 - - - FLASHEN - FLASH clock enable - 4 - 1 - - - CRCEN - CRC clock enable - 6 - 1 - - - SDIO1EN - SDIO1 clock enable - 10 - 1 - - - - - APB2EN - APB2EN - APB2 peripheral clock enable register - 0x18 - 0x20 - read-write - 0x00000000 - - - IOMUXEN - MUX function I/O clock enable - 0 - 1 - - - GPIOAEN - I/O port A clock enable - 2 - 1 - - - GPIOBEN - I/O port B clock enable - 3 - 1 - - - GPIOCEN - I/O port C clock enable - 4 - 1 - - - GPIODEN - I/O port D clock enable - 5 - 1 - - - GPIOFEN - I/O port F clock enable - 7 - 1 - - - ADC1EN - ADC1 clock enable - 9 - 1 - - - ADC2EN - ADC2 clock enable - 10 - 1 - - - TMR1EN - Timer1 clock enable - 11 - 1 - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - TMR8EN - Timer8 clock enable - 13 - 1 - - - USART1EN - USART1 clock enable - 14 - 1 - - - TMR9EN - Timer9 clock enable - 19 - 1 - - - TMR10EN - Timer10 clock enable - 20 - 1 - - - TMR11EN - Timer11 clock enable - 21 - 1 - - - ACCEN - ACC clock enable - 22 - 1 - - - - - APB1EN - APB1EN - APB1 peripheral clock enable register - 0x1C - 0x20 - read-write - 0x00000000 - - - TMR2EN - Timer2 clock enable - 0 - 1 - - - TMR3EN - Timer3 clock enable - 1 - 1 - - - TMR4EN - Timer4 clock enable - 2 - 1 - - - TMR5EN - Timer5 clock enable - 3 - 1 - - - WWDTEN - Window watchdog timer clock enable - 11 - 1 - - - SPI2EN - SPI2 clock enable - 14 - 1 - - - USART2EN - USART2 clock enable - 17 - 1 - - - USART3EN - USART3 clock enable - 18 - 1 - - - UART4EN - UART4 clock enable - 19 - 1 - - - UART5EN - UART5 clock enable - 20 - 1 - - - I2C1EN - I2C1 clock enable - 21 - 1 - - - I2C2EN - I2C2 clock enable - 22 - 1 - - - USBEN - USB clock enable - 23 - 1 - - - CAN1EN - CAN1 clock enable - 25 - 1 - - - BPREN - Barrery powered domain register clock enable - 27 - 1 - - - PWCEN - Power clock enable - 28 - 1 - - - CAN2EN - CAN2 clock enable - 31 - 1 - - - - - BPDC - BPDC - Battery powered domain control register - 0x20 - 0x20 - 0x00000000 - - - LEXTEN - Low speed external crystal enable - 0 - 1 - read-write - - - LEXTSTBL - Low speed external crystal ready - 1 - 1 - read-only - - - LEXTBYPS - Low speed external crystal bypass - 2 - 1 - read-write - - - RTCSEL - RTC clock selection - 8 - 2 - read-write - - - RTCEN - RTC clock enable - 15 - 1 - read-write - - - BPDRST - Battery powered domain software reset - 16 - 1 - read-write - - - - - CTRLSTS - CTRLSTS - Control/status register - 0x24 - 0x20 - 0x0C000000 - - - LICKEN - Low speed internal clock enable - 0 - 1 - read-write - - - LICKSTBL - Low speed internal clock ready - 1 - 1 - read-only - - - RSTFC - Reset flag clear - 24 - 1 - read-write - - - NRSTF - PIN reset flag - 26 - 1 - read-write - - - PORRSTF - POR/LVR reset flag - 27 - 1 - read-write - - - SWRSTF - Software reset flag - 28 - 1 - read-write - - - WDTRSTF - Watchdog timer reset flag - 29 - 1 - read-write - - - WWDTRSTF - Window watchdog timer reset flag - 30 - 1 - read-write - - - LPRSTF - Low-power reset flag - 31 - 1 - read-write - - - - - MISC1 - MISC1 - Miscellaneous register 1 - 0x30 - 0x20 - 0x00000000 - - - HICKCAL_KEY - HICKCAL write key value - 0 - 8 - read-write - - - CLKOUT_SEL3 - Clock output bit3 - 16 - 1 - read-write - - - USBBUFS - USB buffer size selection - 24 - 1 - read-write - - - HICKDIV - HICK 6 divider selection - 25 - 1 - read-write - - - CLKOUTDIV - Clock output division - 28 - 4 - read-write - - - - - MISC2 - MISC2 - Miscellaneous register 2 - 0x50 - 0x20 - 0x00000000 - - - CLK_TO_TMR - Clock output internal connect to timer10 - 16 - 1 - read-write - - - - - MISC3 - MISC3 - Miscellaneous register 3 - 0x54 - 0x20 - 0x00000000 - - - AUTO_STEP_EN - Auto step en - 4 - 2 - read-write - - - HICK_TO_USB - HICK to usb clock - 8 - 1 - read-write - - - HICK_TO_SCLK - HICK to system clock - 9 - 1 - read-write - - - - - INTMAP - INTMAP - Interrupt remap register - 0x5C - 0x20 - 0x00000000 - - - USB_INT_MAP - USBDEV interrupt remap - 0 - 1 - read-write - - - - - - - GPIOA - General purpose IO - GPIO - 0x40010800 - - 0x0 - 0x400 - registers - - - - CFGLR - CFGLR - GPIO function configurate low register - 0x0 - 0x20 - read-write - 0x44444444 - - - IOMC0 - Port n.0 mode configurate bits - 0 - 2 - - - IOFC0 - Port n.0 function configurate - bits - 2 - 2 - - - IOMC1 - Port n.1 mode configurate bits - 4 - 2 - - - IOFC1 - Port n.1 function configurate - bits - 6 - 2 - - - IOMC2 - Port n.2 mode configurate bits - 8 - 2 - - - IOFC2 - Port n.2 function configurate - bits - 10 - 2 - - - IOMC3 - Port n.3 mode configurate bits - 12 - 2 - - - IOFC3 - Port n.3 function configurate - bits - 14 - 2 - - - IOMC4 - Port n.4 mode configurate bits - 16 - 2 - - - IOFC4 - Port n.4 function configurate - bits - 18 - 2 - - - IOMC5 - Port n.5 mode configurate bits - 20 - 2 - - - IOFC5 - Port n.5 function configurate - bits - 22 - 2 - - - IOMC6 - Port n.6 mode configurate bits - 24 - 2 - - - IOFC6 - Port n.6 function configurate - bits - 26 - 2 - - - IOMC7 - Port n.7 mode configurate bits - 28 - 2 - - - IOFC7 - Port n.7 function configurate - bits - 30 - 2 - - - - - CFGHR - CFGHR - GPIO function configurate high register - 0x4 - 0x20 - read-write - 0x44444444 - - - IOMC8 - Port n.8 mode configurate bits - 0 - 2 - - - IOFC8 - Port n.8 function configurate - bits - 2 - 2 - - - IOMC9 - Port n.9 mode configurate bits - 4 - 2 - - - IOFC9 - Port n.9 function configurate - bits - 6 - 2 - - - IOMC10 - Port n.10 mode configurate bits - 8 - 2 - - - IOFC10 - Port n.10 function configurate - bits - 10 - 2 - - - IOMC11 - Port n.11 mode configurate bits - 12 - 2 - - - IOFC11 - Port n.11 function configurate - bits - 14 - 2 - - - IOMC12 - Port n.12 mode configurate bits - 16 - 2 - - - IOFC12 - Port n.12 function configurate - bits - 18 - 2 - - - IOMC13 - Port n.13 mode configurate bits - 20 - 2 - - - IOFC13 - Port n.13 function configurate - bits - 22 - 2 - - - IOMC14 - Port n.14 mode configurate bits - 24 - 2 - - - IOFC14 - Port n.14 function configurate - bits - 26 - 2 - - - IOMC15 - Port n.15 mode configurate bits - 28 - 2 - - - IOFC15 - Port n.15 function configurate - bits - 30 - 2 - - - - - IDT - IDT - Port input data register - 0x8 - 0x20 - read-only - 0x00000000 - - - IDT0 - Port input data - 0 - 1 - - - IDT1 - Port input data - 1 - 1 - - - IDT2 - Port input data - 2 - 1 - - - IDT3 - Port input data - 3 - 1 - - - IDT4 - Port input data - 4 - 1 - - - IDT5 - Port input data - 5 - 1 - - - IDT6 - Port input data - 6 - 1 - - - IDT7 - Port input data - 7 - 1 - - - IDT8 - Port input data - 8 - 1 - - - IDT9 - Port input data - 9 - 1 - - - IDT10 - Port input data - 10 - 1 - - - IDT11 - Port input data - 11 - 1 - - - IDT12 - Port input data - 12 - 1 - - - IDT13 - Port input data - 13 - 1 - - - IDT14 - Port input data - 14 - 1 - - - IDT15 - Port input data - 15 - 1 - - - - - ODT - ODT - Port output data register - 0xC - 0x20 - read-write - 0x00000000 - - - ODT0 - Port output data - 0 - 1 - - - ODT1 - Port output data - 1 - 1 - - - ODT2 - Port output data - 2 - 1 - - - ODT3 - Port output data - 3 - 1 - - - ODT4 - Port output data - 4 - 1 - - - ODT5 - Port output data - 5 - 1 - - - ODT6 - Port output data - 6 - 1 - - - ODT7 - Port output data - 7 - 1 - - - ODT8 - Port output data - 8 - 1 - - - ODT9 - Port output data - 9 - 1 - - - ODT10 - Port output data - 10 - 1 - - - ODT11 - Port output data - 11 - 1 - - - ODT12 - Port output data - 12 - 1 - - - ODT13 - Port output data - 13 - 1 - - - ODT14 - Port output data - 14 - 1 - - - ODT15 - Port output data - 15 - 1 - - - - - SCR - SCR - Port bit set/clear register - 0x10 - 0x20 - read-write - 0x00000000 - - - IOSB0 - Set bit 0 - 0 - 1 - - - IOSB1 - Set bit 1 - 1 - 1 - - - IOSB2 - Set bit 1 - 2 - 1 - - - IOSB3 - Set bit 3 - 3 - 1 - - - IOSB4 - Set bit 4 - 4 - 1 - - - IOSB5 - Set bit 5 - 5 - 1 - - - IOSB6 - Set bit 6 - 6 - 1 - - - IOSB7 - Set bit 7 - 7 - 1 - - - IOSB8 - Set bit 8 - 8 - 1 - - - IOSB9 - Set bit 9 - 9 - 1 - - - IOSB10 - Set bit 10 - 10 - 1 - - - IOSB11 - Set bit 11 - 11 - 1 - - - IOSB12 - Set bit 12 - 12 - 1 - - - IOSB13 - Set bit 13 - 13 - 1 - - - IOSB14 - Set bit 14 - 14 - 1 - - - IOSB15 - Set bit 15 - 15 - 1 - - - IOCB0 - Clear bit 0 - 16 - 1 - - - IOCB1 - Clear bit 1 - 17 - 1 - - - IOCB2 - Clear bit 2 - 18 - 1 - - - IOCB3 - Clear bit 3 - 19 - 1 - - - IOCB4 - Clear bit 4 - 20 - 1 - - - IOCB5 - Clear bit 5 - 21 - 1 - - - IOCB6 - Clear bit 6 - 22 - 1 - - - IOCB7 - Clear bit 7 - 23 - 1 - - - IOCB8 - Clear bit 8 - 24 - 1 - - - IOCB9 - Clear bit 9 - 25 - 1 - - - IOCB10 - Clear bit 10 - 26 - 1 - - - IOCB11 - Clear bit 11 - 27 - 1 - - - IOCB12 - Clear bit 12 - 28 - 1 - - - IOCB13 - Clear bit 13 - 29 - 1 - - - IOCB14 - Clear bit 14 - 30 - 1 - - - IOCB15 - Clear bit 15 - 31 - 1 - - - - - CLR - CLR - Port bit reset register - 0x14 - 0x20 - read-write - 0x00000000 - - - IOCB0 - Clear bit 0 - 0 - 1 - - - IOCB1 - Clear bit 1 - 1 - 1 - - - IOCB2 - Clear bit 1 - 2 - 1 - - - IOCB3 - Clear bit 3 - 3 - 1 - - - IOCB4 - Clear bit 4 - 4 - 1 - - - IOCB5 - Clear bit 5 - 5 - 1 - - - IOCB6 - Clear bit 6 - 6 - 1 - - - IOCB7 - Clear bit 7 - 7 - 1 - - - IOCB8 - Clear bit 8 - 8 - 1 - - - IOCB9 - Clear bit 9 - 9 - 1 - - - IOCB10 - Clear bit 10 - 10 - 1 - - - IOCB11 - Clear bit 11 - 11 - 1 - - - IOCB12 - Clear bit 12 - 12 - 1 - - - IOCB13 - Clear bit 13 - 13 - 1 - - - IOCB14 - Clear bit 14 - 14 - 1 - - - IOCB15 - Clear bit 15 - 15 - 1 - - - - - WPR - WPR - Port write protect register - 0x18 - 0x20 - read-write - 0x00000000 - - - WPEN0 - Write protect enable 0 - 0 - 1 - - - WPEN1 - Write protect enable 1 - 1 - 1 - - - WPEN2 - Write protect enable 2 - 2 - 1 - - - WPEN3 - Write protect enable 3 - 3 - 1 - - - WPEN4 - Write protect enable 4 - 4 - 1 - - - WPEN5 - Write protect enable 5 - 5 - 1 - - - WPEN6 - Write protect enable 6 - 6 - 1 - - - WPEN7 - Write protect enable 7 - 7 - 1 - - - WPEN8 - Write protect enable 8 - 8 - 1 - - - WPEN9 - Write protect enable 9 - 9 - 1 - - - WPEN10 - Write protect enable 10 - 10 - 1 - - - WPEN11 - Write protect enable 11 - 11 - 1 - - - WPEN12 - Write protect enable 12 - 12 - 1 - - - WPEN13 - Write protect enable 13 - 13 - 1 - - - WPEN14 - Write protect enable 14 - 14 - 1 - - - WPEN15 - Write protect enable 15 - 15 - 1 - - - WPSEQ - Write protect sequence - 16 - 1 - - - - - - - GPIOB - 0x40010C00 - - - GPIOC - 0x40011000 - - - GPIOD - 0x40011400 - - - GPIOE - 0x40011800 - - - IOMUX - IO MUX function - IOMUX - 0x40010000 - - 0x0 - 0x400 - registers - - - - EVTOUT - EVTOUT - Event output register - 0x0 - 0x20 - read-write - 0x00000000 - - - SELPIN - Select pin - 0 - 4 - - - SELPORT - Select port - 4 - 3 - - - EVOEN - Event output enable - 7 - 1 - - - - - REMAP - REMAP - IO MUX remap register - 0x4 - 0x20 - 0x00000000 - - - SPI1_MUX0 - SPI1 muxing bit0 - 0 - 1 - read-write - - - I2C1_MUX - I2C1 muxing - 1 - 1 - read-write - - - USART1_MUX - USART1 muxing - 2 - 1 - read-write - - - USART3_MUX - USART3 muxing - 4 - 2 - read-write - - - TMR1_MUX - TMR1 muxing - 6 - 2 - read-write - - - TMR2_MUX - TMR2 muxing - 8 - 2 - read-write - - - TMR3_MUX - TMR3 muxing - 10 - 2 - read-write - - - CAN_MUX - CAN1 muxing - 13 - 2 - read-write - - - PD01_MUX - PD0/PD1 muxing on - OSCIN/OSCOUT - 15 - 1 - read-write - - - TMR5CH4_MUX - TMR5 channel4 internal muxing - 16 - 1 - read-write - - - ADC1_ETP_MUX - ADC1 external trigger preempted - conversion muxing - 17 - 1 - read-write - - - ADC1_ETO_MUX - ADC1 external trigger ordinary - conversion muxing - 18 - 1 - read-write - - - ADC2_ETP_MUX - ADC2 external trigger preempted - conversion muxing - 19 - 1 - read-write - - - ADC2_ETO_MUX - ADC2 external trigger ordinary - conversion muxing - 20 - 1 - read-write - - - SWJTAG_MUX - SWD JTAG muxing - 24 - 3 - read-write - - - SPI1_MUX1 - SPI1 muxing bit1 - 31 - 1 - read-write - - - - - EXINTC1 - EXINTC1 - External interrupt configuration register 1 - 0x8 - 0x20 - read-write - 0x00000000 - - - EXINT0 - Configure EXINT0 source - 0 - 4 - - - EXINT1 - Configure EXINT1 source - 4 - 4 - - - EXINT2 - Configure EXINT2 source - 8 - 4 - - - EXINT3 - Configure EXINT3 source - 12 - 4 - - - - - EXINTC2 - EXINTC2 - External interrupt configuration register 2 - 0xC - 0x20 - read-write - 0x00000000 - - - EXINT4 - Configure EXINT4 source - 0 - 4 - - - EXINT5 - Configure EXINT5 source - 4 - 4 - - - EXINT6 - Configure EXINT6 source - 8 - 4 - - - EXINT7 - Configure EXINT7 source - 12 - 4 - - - - - EXINTC3 - EXINTC3 - External interrupt configuration register 3 - 0x10 - 0x20 - read-write - 0x00000000 - - - EXINT8 - Configure EXINT8 source - 0 - 4 - - - EXINT9 - Configure EXINT9 source - 4 - 4 - - - EXINT10 - Configure EXINT10 source - 8 - 4 - - - EXINT11 - Configure EXINT11 source - 12 - 4 - - - - - EXINTC4 - EXINTC4 - External interrupt configuration register 4 - 0x14 - 0x20 - read-write - 0x00000000 - - - EXINT12 - Configure EXINT12 source - 0 - 4 - - - EXINT13 - Configure EXINT13 source - 4 - 4 - - - EXINT14 - Configure EXINT14 source - 8 - 4 - - - EXINT15 - Configure EXINT15 source - 12 - 4 - - - - - REMAP2 - REMAP2 - IO MUX remap register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - EXT_SPIM_EN_MUX - SPIM enable - 21 - 1 - - - - - REMAP3 - REMAP3 - IO MUX remap register 3 - 0x20 - 0x20 - read-write - 0x00000000 - - - TMR9_GMUX - TMR9 muxing - 0 - 4 - - - TMR10_GMUX - TMR10 muxing - 4 - 4 - - - TMR11_GMUX - TMR11 muxing - 8 - 4 - - - - - REMAP4 - REMAP4 - IO MUX remap register 4 - 0x24 - 0x20 - read-write - 0x00000000 - - - TMR1_GMUX - TMR1 muxing - 0 - 4 - - - TMR2_GMUX - TMR2 muxing - 4 - 3 - - - TMR2ITR1_GMUX - TMR2 internal trigger 1 muxing - 7 - 1 - - - TMR3_GMUX - TMR3 muxing - 8 - 4 - - - TMR5_GMUX - TMR5 muxing - 16 - 3 - - - TMR5CH4_GMUX - TMR5 channel4 internal muxing - 19 - 1 - - - - - REMAP5 - REMAP5 - IO MUX remap register 5 - 0x28 - 0x20 - read-write - 0x00000000 - - - I2C1_GMUX - I2C1 muxing - 4 - 4 - - - I2C2_GMUX - I2C2 muxing - 8 - 4 - - - SPI1_GMUX - SPI1 muxing - 16 - 4 - - - SPI2_GMUX - SPI2 muxing - 20 - 4 - - - - - REMAP6 - REMAP6 - IO MUX remap register 6 - 0x2C - 0x20 - read-write - 0x00000000 - - - CAN1_GMUX - CAN1 muxing - 0 - 4 - - - CAN2_GMUX - CAN2 muxing - 4 - 4 - - - SDIO1_GMUX - SDIO1 muxing - 8 - 4 - - - USART1_GMUX - USART1 muxing - 16 - 4 - - - USART3_GMUX - USART3 muxing - 24 - 4 - - - UART4_GMUX - UART4 muxing - 28 - 4 - - - - - REMAP7 - REMAP7 - IO MUX remap register 7 - 0x30 - 0x20 - read-write - 0x00000000 - - - EXT_SPIM_GMUX - SPIM muxing - 0 - 3 - - - EXT_SPIM_GEN - SPIM enable - 3 - 1 - - - ADC1_ETP_GMUX - ADC1 external trigger preempted - conversion muxing - 4 - 1 - - - ADC1_ETO_GMUX - ADC1 external trigger ordinary - conversion muxing - 5 - 1 - - - ADC2_ETP_GMUX - ADC2 external trigger preempted - conversion muxing - 8 - 1 - - - ADC2_ETO_GMUX - ADC2 external trigger ordinary - conversion muxing - 9 - 1 - - - SWJTAG_GMUX - Serial wire JTAG muxing - 16 - 3 - - - PD01_GMUX - PortD0/PortD1 mappingon - OSC_IN/OSC_OUT - 20 - 1 - - - - - - - EXINT - EXINT - EXINT - 0x40010400 - - 0x0 - 0x400 - registers - - - TAMPER - Tamper interrupt - 2 - - - EXINT0 - EXINT Line0 interrupt - 6 - - - EXINT1 - EXINT Line1 interrupt - 7 - - - EXINT2 - EXINT Line2 interrupt - 8 - - - EXINT3 - EXINT Line3 interrupt - 9 - - - EXINT4 - EXINT Line4 interrupt - 10 - - - EXINT9_5 - EXINT Line[9:5] interrupts - 23 - - - EXINT15_10 - EXINT Line[15:10] interrupts - 40 - - - PVM - PVM interrupt connect to EXINT line16 - 1 - - - RTCALARM - RTC Alarm interrupt connect to EXINT line17 - 41 - - - USBFSWakeUp - USB Device FS Wakeup interrupt connect to EXINT line18 - 42 - - - - INTEN - INTEN - Interrupt enable register - 0x0 - 0x20 - read-write - 0x00000000 - - - INTEN0 - Interrupt enable or disable on line 0 - 0 - 1 - - - INTEN1 - Interrupt enable or disable on line 1 - 1 - 1 - - - INTEN2 - Interrupt enable or disable on line 2 - 2 - 1 - - - INTEN3 - Interrupt enable or disable on line 3 - 3 - 1 - - - INTEN4 - Interrupt enable or disable on line 4 - 4 - 1 - - - INTEN5 - Interrupt enable or disable on line 5 - 5 - 1 - - - INTEN6 - Interrupt enable or disable on line 6 - 6 - 1 - - - INTEN7 - Interrupt enable or disable on line 7 - 7 - 1 - - - INTEN8 - Interrupt enable or disable on line 8 - 8 - 1 - - - INTEN9 - Interrupt enable or disable on line 9 - 9 - 1 - - - INTEN10 - Interrupt enable or disable on line 10 - 10 - 1 - - - INTEN11 - Interrupt enable or disable on line 11 - 11 - 1 - - - INTEN12 - Interrupt enable or disable on line 12 - 12 - 1 - - - INTEN13 - Interrupt enable or disable on line 13 - 13 - 1 - - - INTEN14 - Interrupt enable or disable on line 14 - 14 - 1 - - - INTEN15 - Interrupt enable or disable on line 15 - 15 - 1 - - - INTEN16 - Interrupt enable or disable on line 16 - 16 - 1 - - - INTEN17 - Interrupt enable or disable on line 17 - 17 - 1 - - - INTEN18 - Interrupt enable or disable on line 18 - 18 - 1 - - - - - EVTEN - EVTEN - Event enable register - 0x4 - 0x20 - read-write - 0x00000000 - - - EVTEN0 - Event enable or disable on line 0 - 0 - 1 - - - EVTEN1 - Event enable or disable on line 1 - 1 - 1 - - - EVTEN2 - Event enable or disable on line 2 - 2 - 1 - - - EVTEN3 - Event enable or disable on line 3 - 3 - 1 - - - EVTEN4 - Event enable or disable on line 4 - 4 - 1 - - - EVTEN5 - Event enable or disable on line 5 - 5 - 1 - - - EVTEN6 - Event enable or disable on line 6 - 6 - 1 - - - EVTEN7 - Event enable or disable on line 7 - 7 - 1 - - - EVTEN8 - Event enable or disable on line 8 - 8 - 1 - - - EVTEN9 - Event enable or disable on line 9 - 9 - 1 - - - EVTEN10 - Event enable or disable on line 10 - 10 - 1 - - - EVTEN11 - Event enable or disable on line 11 - 11 - 1 - - - EVTEN12 - Event enable or disable on line 12 - 12 - 1 - - - EVTEN13 - Event enable or disable on line 13 - 13 - 1 - - - EVTEN14 - Event enable or disable on line 14 - 14 - 1 - - - EVTEN15 - Event enable or disable on line 15 - 15 - 1 - - - EVTEN16 - Event enable or disable on line 16 - 16 - 1 - - - EVTEN17 - Event enable or disable on line 17 - 17 - 1 - - - EVTEN18 - Event enable or disable on line 18 - 18 - 1 - - - - - POLCFG1 - POLCFG1 - Rising polarity configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - RP0 - Rising polarity configuration bit of line 0 - 0 - 1 - - - RP1 - Rising polarity configuration bit of line 1 - 1 - 1 - - - RP2 - Rising polarity configuration bit of line 2 - 2 - 1 - - - RP3 - Rising polarity configuration bit of line 3 - 3 - 1 - - - RP4 - Rising polarity configuration bit of line 4 - 4 - 1 - - - RP5 - Rising polarity configuration bit of line 5 - 5 - 1 - - - RP6 - Rising polarity configuration bit of linee 6 - 6 - 1 - - - RP7 - Rising polarity configuration bit of line 7 - 7 - 1 - - - RP8 - Rising polarity configuration bit of line 8 - 8 - 1 - - - RP9 - Rising polarity configuration bit of line 9 - 9 - 1 - - - RP10 - Rising polarity configuration bit of line 10 - 10 - 1 - - - RP11 - Rising polarity configuration bit of line 11 - 11 - 1 - - - RP12 - Rising polarity configuration bit of line 12 - 12 - 1 - - - RP13 - Rising polarity configuration bit of line 13 - 13 - 1 - - - RP14 - Rising polarity configuration bit of line 14 - 14 - 1 - - - RP15 - Rising polarity configuration bit of line 15 - 15 - 1 - - - RP16 - Rising polarity configuration bit of line 16 - 16 - 1 - - - RP17 - Rising polarity configuration bit of line 17 - 17 - 1 - - - RP18 - Rising polarity configuration bit of line 18 - 18 - 1 - - - - - POLCFG2 - POLCFG2 - Falling polarity configuration register - 0xC - 0x20 - read-write - 0x00000000 - - - FP0 - Falling polarity event configuration bit of line 0 - 0 - 1 - - - FP1 - Falling polarity event configuration bit of line 1 - 1 - 1 - - - FP2 - Falling polarity event configuration bit of line 2 - 2 - 1 - - - FP3 - Falling polarity event configuration bit of line 3 - 3 - 1 - - - FP4 - Falling polarity event configuration bit of line 4 - 4 - 1 - - - FP5 - Falling polarity event configuration bit of line 5 - 5 - 1 - - - FP6 - Falling polarity event configuration bit of line 6 - 6 - 1 - - - FP7 - Falling polarity event configuration bit of line 7 - 7 - 1 - - - FP8 - Falling polarity event configuration bit of line 8 - 8 - 1 - - - FP9 - Falling polarity event configuration bit of line 9 - 9 - 1 - - - FP10 - Falling polarity event configuration bit of line 10 - 10 - 1 - - - FP11 - Falling polarity event configuration bit of line 11 - 11 - 1 - - - FP12 - Falling polarity event configuration bit of line 12 - 12 - 1 - - - FP13 - Falling polarity event configuration bit of line 13 - 13 - 1 - - - FP14 - Falling polarity event configuration bit of line 14 - 14 - 1 - - - FP15 - Falling polarity event configuration bit of line 15 - 15 - 1 - - - FP16 - Falling polarity event configuration bit of line 16 - 16 - 1 - - - FP17 - Falling polarity event configuration bit of line 17 - 17 - 1 - - - FP18 - Falling polarity event configuration bit of line 18 - 18 - 1 - - - - - SWTRG - SWTRG - Software triggle register - 0x10 - 0x20 - read-write - 0x00000000 - - - SWT0 - Software triggle on line 0 - 0 - 1 - - - SWT1 - Software triggle on line 1 - 1 - 1 - - - SWT2 - Software triggle on line 2 - 2 - 1 - - - SWT3 - Software triggle on line 3 - 3 - 1 - - - SWT4 - Software triggle on line 4 - 4 - 1 - - - SWT5 - Software triggle on line 5 - 5 - 1 - - - SWT6 - Software triggle on line 6 - 6 - 1 - - - SWT7 - Software triggle on line 7 - 7 - 1 - - - SWT8 - Software triggle on line 8 - 8 - 1 - - - SWT9 - Software triggle on line 9 - 9 - 1 - - - SWT10 - Software triggle on line 10 - 10 - 1 - - - SWT11 - Software triggle on line 11 - 11 - 1 - - - SWT12 - Software triggle on line 12 - 12 - 1 - - - SWT13 - Software triggle on line 13 - 13 - 1 - - - SWT14 - Software triggle on line 14 - 14 - 1 - - - SWT15 - Software triggle on line 15 - 15 - 1 - - - SWT16 - Software triggle on line 16 - 16 - 1 - - - SWT17 - Software triggle on line 17 - 17 - 1 - - - SWT18 - Software triggle on line 18 - 18 - 1 - - - - - INTSTS - INTSTS - Interrupt status register - 0x14 - 0x20 - read-write - 0x00000000 - - - LINE0 - Line 0 state bit - 0 - 1 - - - LINE1 - Line 1 state bit - 1 - 1 - - - LINE2 - Line 2 state bit - 2 - 1 - - - LINE3 - Line 3 state bit - 3 - 1 - - - LINE4 - Line 4 state bit - 4 - 1 - - - LINE5 - Line 5 state bit - 5 - 1 - - - LINE6 - Line 6 state bit - 6 - 1 - - - LINE7 - Line 7 state bit - 7 - 1 - - - LINE8 - Line 8 state bit - 8 - 1 - - - LINE9 - Line 9 state bit - 9 - 1 - - - LINE10 - Line 10 state bit - 10 - 1 - - - LINE11 - Line 11 state bit - 11 - 1 - - - LINE12 - Line 12 state bit - 12 - 1 - - - LINE13 - Line 13 state bit - 13 - 1 - - - LINE14 - Line 14 state bit - 14 - 1 - - - LINE15 - Line 15 state bit - 15 - 1 - - - LINE16 - Line 16 state bit - 16 - 1 - - - LINE17 - Line 17 state bit - 17 - 1 - - - LINE18 - Line 18 state bit - 18 - 1 - - - - - - - DMA1 - DMA controller - DMA - 0x40020000 - - 0x0 - 0x400 - registers - - - DMA1_Channel1 - DMA1 Channel1 global interrupt - 11 - - - DMA1_Channel2 - DMA1 Channel2 global interrupt - 12 - - - DMA1_Channel3 - DMA1 Channel3 global interrupt - 13 - - - DMA1_Channel4 - DMA1 Channel4 global interrupt - 14 - - - DMA1_Channel5 - DMA1 Channel5 global interrupt - 15 - - - DMA1_Channel6 - DMA1 Channel6 global interrupt - 16 - - - DMA1_Channel7 - DMA1 Channel7 global interrupt - 17 - - - - STS - STS - DMA status register (DMA_STS) - 0x0 - 0x20 - read-only - 0x00000000 - - - GF1 - Channel 1 Global event flag - 0 - 1 - - - GF2 - Channel 2 Global event flag - 4 - 1 - - - GF3 - Channel 3 Global event flag - 8 - 1 - - - GF4 - Channel 4 Global event flag - 12 - 1 - - - GF5 - Channel 5 Global event flag - 16 - 1 - - - GF6 - Channel 6 Global event flag - 20 - 1 - - - GF7 - Channel 7 Global event flag - 24 - 1 - - - FDTF1 - Channel 1 full data transfer event flag - 1 - 1 - - - FDTF2 - Channel 2 full data transfer event flag - 5 - 1 - - - FDTF3 - Channel 3 full data transfer event flag - 9 - 1 - - - FDTF4 - Channel 4 full data transfer event flag - 13 - 1 - - - FDTF5 - Channel 5 full data transfer event flag - 17 - 1 - - - FDTF6 - Channel 6 full data transfer event flag - 21 - 1 - - - FDTF7 - Channel 7 full data transfer event flag - 25 - 1 - - - HDTF1 - Channel 1 half data transfer event flag - 2 - 1 - - - HDTF2 - Channel 2 half data transfer event flag - 6 - 1 - - - HDTF3 - Channel 3 half data transfer event flag - 10 - 1 - - - HDTF4 - Channel 4 half data transfer event flag - 14 - 1 - - - HDTF5 - Channel 5 half data transfer event flag - 18 - 1 - - - HDTF6 - Channel 6 half data transfer event flag - 22 - 1 - - - HDTF7 - Channel 7 half data transfer event flag - 26 - 1 - - - DTERRF1 - Channel 1 data transfer error event flag - 3 - 1 - - - DTERRF2 - Channel 2 data transfer error event flag - 7 - 1 - - - DTERRF3 - Channel 3 data transfer error event flag - 11 - 1 - - - DTERRF4 - Channel 4 data transfer error event flag - 15 - 1 - - - DTERRF5 - Channel 5 data transfer error event flag - 19 - 1 - - - DTERRF6 - Channel 6 data transfer error event flag - 23 - 1 - - - DTERRF7 - Channel 7 data transfer error event flag - 27 - 1 - - - - - CLR - CLR - DMA flag clear register (DMA_CLR) - 0x4 - 0x20 - read-write - 0x00000000 - - - GFC1 - Channel 1 Global flag clear - 0 - 1 - - - GFC2 - Channel 2 Global flag clear - 4 - 1 - - - GFC3 - Channel 3 Global flag clear - 8 - 1 - - - GFC4 - Channel 4 Global flag clear - 12 - 1 - - - GFC5 - Channel 5 Global flag clear - 16 - 1 - - - GFC6 - Channel 6 Global flag clear - 20 - 1 - - - GFC7 - Channel 7 Global flag clear - 24 - 1 - - - FDTFC1 - Channel 1 full data transfer flag clear - 1 - 1 - - - FDTFC2 - Channel 2 full data transfer flag clear - 5 - 1 - - - FDTFC3 - Channel 3 full data transfer flag clear - 9 - 1 - - - FDTFC4 - Channel 4 full data transfer flag clear - 13 - 1 - - - FDTFC5 - Channel 5 full data transfer flag clear - 17 - 1 - - - FDTFC6 - Channel 6 full data transfer flag clear - 21 - 1 - - - FDTFC7 - Channel 7 full data transfer flag clear - 25 - 1 - - - HDTFC1 - Channel 1 half data transfer flag clear - 2 - 1 - - - HDTFC2 - Channel 2 half data transfer flag clear - 6 - 1 - - - HDTFC3 - Channel 3 half data transfer flag clear - 10 - 1 - - - HDTFC4 - Channel 4 half data transfer flag clear - 14 - 1 - - - HDTFC5 - Channel 5 half data transfer flag clear - 18 - 1 - - - HDTFC6 - Channel 6 half data transfer flag clear - 22 - 1 - - - HDTFC7 - Channel 7 half data transfer flag clear - 26 - 1 - - - DTERRFC1 - Channel 1 data transfer error flag clear - 3 - 1 - - - DTERRFC2 - Channel 2 data transfer error flag clear - 7 - 1 - - - DTERRFC3 - Channel 3 data transfer error flag clear - 11 - 1 - - - DTERRFC4 - Channel 4 data transfer error flag clear - 15 - 1 - - - DTERRFC5 - Channel 5 data transfer error flag clear - 19 - 1 - - - DTERRFC6 - Channel 6 data transfer error flag clear - 23 - 1 - - - DTERRFC7 - Channel 7 data transfer error flag clear - 27 - 1 - - - - - C1CTRL - C1CTRL - DMA channel configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C1DTCNT - C1DTCNT - DMA channel 1 number of data to transfer register - 0xC - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C1PADDR - C1PADDR - DMA channel 1 peripheral base address register - 0x10 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C1MADDR - C1MADDR - DMA channel 1 memory base address register - 0x14 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C2CTRL - C2CTRL - DMA channel configuration register - 0x1C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C2DTCNT - C2DTCNT - DMA channel 2 number of data to transferregister - 0x20 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C2PADDR - C2PADDR - DMA channel 2 peripheral base address register - 0x24 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C2MADDR - C2MADDR - DMA channel 2 memory base address register - 0x28 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C3CTRL - C3CTRL - DMA channel configuration register - 0x30 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C3DTCNT - C3DTCNT - DMA channel 3 number of data to transfer register - 0x34 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C3PADDR - C3PADDR - DMA channel 3 peripheral base address register - 0x38 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C3MADDR - C3MADDR - DMA channel 3 memory base address register - 0x3C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C4CTRL - C4CTRL - DMA channel configuration register - 0x44 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C4DTCNT - C4DTCNT - DMA channel 4 number of data to transfer register - 0x48 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C4PADDR - C4PADDR - DMA channel 4 peripheral base address register - 0x4C - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C4MADDR - C4MADDR - DMA channel 4 memory base address register - 0x50 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C5CTRL - C5CTRL - DMA channel configuration register - 0x58 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C5DTCNT - C5DTCNT - DMA channel 5 number of data to transfer register - 0x5C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C5PADDR - C5PADDR - DMA channel 5 peripheral base address register - 0x60 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C5MADDR - C5MADDR - DMA channel 5 memory base address register - 0x64 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C6CTRL - C6CTRL - DMA channel configuration register - 0x6C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C6DTCNT - C6DTCNT - DMA channel 6 number of data to transfer register - 0x70 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C6PADDR - C6PADDR - DMA channel 6 peripheral address base register - 0x74 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C6MADDR - C6MADDR - DMA channel 6 memory address base register - 0x78 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C7CTRL - C7CTRL - DMA channel configuration register - 0x80 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C7DTCNT - C7DTCNT - DMA channel 7 number of data to transfer register - 0x84 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C7PADDR - C7PADDR - DMA channel 7 peripheral base address register - 0x88 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C7MADDR - C7MADDR - DMA channel 7 memory base address register - 0x8C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - DMA_SRC_SEL0 - DMA_SRC_SEL0 - DMA channel source assignment register - 0xA0 - 0x20 - read-write - 0x00000000 - - - CH1_SRC - CH1 SRC select - 0 - 8 - - - CH2_SRC - CH2 SRC select - 8 - 8 - - - CH3_SRC - CH3 SRC select - 16 - 8 - - - CH4_SRC - CH4 SRC select - 24 - 8 - - - - - DMA_SRC_SEL1 - DMA_SRC_SEL1 - DMA channel source assignment register - 0xA4 - 0x20 - read-write - 0x00000000 - - - CH5_SRC - CH5 SRC select - 0 - 8 - - - CH6_SRC - CH6 SRC select - 8 - 8 - - - CH7_SRC - CH7 SRC select - 16 - 8 - - - DMA_FLEX_EN - DMA FLEX Enable - 24 - 1 - - - - - - - DMA2 - 0x40020400 - - DMA2_Channel1 - DMA2 Channel1 global interrupt - 56 - - - DMA2_Channel2 - DMA2 Channel2 global interrupt - 57 - - - DMA2_Channel3 - DMA2 Channel3 global interrupt - 58 - - - DMA2_Channel4_5 - DMA2 Channel4 and DMA2 Channel5 global interrupt - 59 - - - DMA2_Channel6_7 - DMA2 Channel6 and DMA2 Channel7 global interrupt - 75 - - - - SDIO - Secure digital input/output interface - SDIO - 0x40018000 - - 0x0 - 0x400 - registers - - - SDIO - SDIO global interrupt - 49 - - - - PWRCTRL - PWRCTRL - Bits 1:0 = PWRCTRL: Power supply control - bits - 0x0 - 0x20 - read-write - 0x00000000 - - - PS - Power switch - 0 - 2 - - - - - CLKCTRL - CLKCTRL - SD clock control register - (SDIO_CLKCTRL) - 0x4 - 0x20 - read-write - 0x00000000 - - - CLKDIV - Clock division - 0 - 8 - - - CLKOEN - Clock output enable - 8 - 1 - - - PWRSVEN - Power saving mode enable - 9 - 1 - - - BYPSEN - Clock divider bypass enable - bit - 10 - 1 - - - BUSWS - Bus width selection - 11 - 2 - - - CLKEDS - SDIO_CK edge selection bit - 13 - 1 - - - HFCEN - Hardware flow control enable - 14 - 1 - - - CLKDIV98 - Clock divide factor bit9 and bit8 - 15 - 2 - - - - - ARGU - ARGU - Bits 31:0 = : Command argument - 0x8 - 0x20 - read-write - 0x00000000 - - - ARGU - Command argument - 0 - 32 - - - - - CMDCTRL - CMDCTRL - SDIO command control register - (SDIO_CMDCTRL) - 0xC - 0x20 - read-write - 0x00000000 - - - CMDIDX - CMDIDX - 0 - 6 - - - RSPWT - Wait for response - 6 - 2 - - - INTWT - CCSM wait for interrupt - 8 - 1 - - - PNDWT - CCSM wait for end of transfer - 9 - 1 - - - CCSMEN - Command channel state machine - 10 - 1 - - - IOSUSP - SD I/O suspend command - 11 - 1 - - - - - RSPCMD - RSPCMD - SDIO command register - 0x10 - 0x20 - read-only - 0x00000000 - - - RSPCMD - RSPCMD - 0 - 6 - - - - - RSP1 - RSP1 - Bits 31:0 = CARDSTATUS1 - 0x14 - 0x20 - read-only - 0x00000000 - - - CARDSTS1 - CARDSTATUS1 - 0 - 32 - - - - - RSP2 - RSP2 - Bits 31:0 = CARDSTATUS2 - 0x18 - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS2 - 0 - 32 - - - - - RSP3 - RSP3 - Bits 31:0 = CARDSTATUS3 - 0x1C - 0x20 - read-only - 0x00000000 - - - CARDSTS3 - CARDSTATUS3 - 0 - 32 - - - - - RSP4 - RSP4 - Bits 31:0 = CARDSTATUS4 - 0x20 - 0x20 - read-only - 0x00000000 - - - CARDSTS4 - CARDSTATUS4 - 0 - 32 - - - - - DTTMR - DTTMR - Bits 31:0 = TIMEOUT: Data timeout - period - 0x24 - 0x20 - read-write - 0x00000000 - - - TIMEOUT - Data timeout period - 0 - 32 - - - - - DTLEN - DTLEN - Bits 24:0 = DATALENGTH: Data length - value - 0x28 - 0x20 - read-write - 0x00000000 - - - DTLEN - Data length value - 0 - 25 - - - - - DTCTRL - DTCTRL - SDIO data control register - (SDIO_DCTRL) - 0x2C - 0x20 - read-write - 0x00000000 - - - TFREN - DTEN - 0 - 1 - - - TFRDIR - DTDIR - 1 - 1 - - - TFRMODE - DTMODE - 2 - 1 - - - DMAEN - DMAEN - 3 - 1 - - - BLKSIZE - DBLOCKSIZE - 4 - 4 - - - RDWTSTART - PWSTART - 8 - 1 - - - RDWTSTOP - PWSTOP - 9 - 1 - - - RDWTMODE - RWMOD - 10 - 1 - - - IOEN - SD I/O function enable - 11 - 1 - - - - - DTCNT - DTCNT - Bits 24:0 = DATACOUNT: Data count - value - 0x30 - 0x20 - read-only - 0x00000000 - - - CNT - Data count value - 0 - 25 - - - - - STS - STS - SDIO status register - (SDIO_STS) - 0x34 - 0x20 - read-only - 0x00000000 - - - CMDFAIL - Command crc fail - 0 - 1 - - - DTFAIL - Data crc fail - 1 - 1 - - - CMDTIMEOUT - Command timeout - 2 - 1 - - - DTTIMEOUT - Data timeout - 3 - 1 - - - TXERRU - Tx under run error - 4 - 1 - - - RXERRO - Rx over run error - 5 - 1 - - - CMDRSPCMPL - Command response complete - 6 - 1 - - - CMDCMPL - Command sent - 7 - 1 - - - DTCMPL - Data sent - 8 - 1 - - - SBITERR - Start bit error - 9 - 1 - - - DTBLKCMPL - Data block sent - 10 - 1 - - - DOCMD - Command transfer in progress - 11 - 1 - - - DOTX - Data transmit in progress - 12 - 1 - - - DORX - Data receive in progress - 13 - 1 - - - TXBUFH - Tx buffer half empty - 14 - 1 - - - RXBUFH - Rx buffer half empty - 15 - 1 - - - TXBUFF - Tx buffer full - 16 - 1 - - - RXBUFF - Rx buffer full - 17 - 1 - - - TXBUFE - Tx buffer empty - 18 - 1 - - - RXBUFE - Rx buffer empty - 19 - 1 - - - TXBUF - Tx data vaild - 20 - 1 - - - RXBUF - Rx data vaild - 21 - 1 - - - IOIF - SD I/O interrupt - 22 - 1 - - - - - INTCLR - INTCLR - SDIO interrupt clear register - (SDIO_INTCLR) - 0x38 - 0x20 - read-write - 0x00000000 - - - CMDFAIL - Command crc fail flag clear - 0 - 1 - - - DTFAIL - Data crc fail flag clear - 1 - 1 - - - CMDTIMEOUT - Command timeout flag clear - 2 - 1 - - - DTTIMEOUT - Data timeout flag clear - 3 - 1 - - - TXERRU - Tx under run error flag clear - 4 - 1 - - - RXERRU - Rx over run error flag clear - 5 - 1 - - - CMDRSPCMPL - Command response complete flag clear - 6 - 1 - - - CMDCMPL - Command sent flag clear - 7 - 1 - - - DTCMPL - Data sent flag clear - 8 - 1 - - - SBITERR - Start bit error flag clear - 9 - 1 - - - DTBLKCMPL - Data block sent clear - 10 - 1 - - - IOIF - SD I/O interrupt flag clear - 22 - 1 - - - - - INTEN - INTEN - SDIO mask register - (SDIO_INTEN) - 0x3C - 0x20 - read-write - 0x00000000 - - - CMDFAILIEN - Command crc fail interrupt enable - 0 - 1 - - - DTFAILIEN - Data crc fail interrupt enable - 1 - 1 - - - CMDTIMEOUTIEN - Command timeout interrupt enable - 2 - 1 - - - DTTIMEOUTIEN - Data timeout interrupt enable - 3 - 1 - - - TXERRUIEN - Tx under run interrupt enable - 4 - 1 - - - RXERRUIEN - Rx over run interrupt enable - 5 - 1 - - - CMDRSPCMPLIEN - Command response complete interrupt enable - 6 - 1 - - - CMDCMPLIEN - Command sent complete interrupt enable - 7 - 1 - - - DTCMPLIEN - Data sent complete interrupt enable - 8 - 1 - - - SBITERRIEN - Start bit error interrupt enable - 9 - 1 - - - DTBLKCMPLIEN - Data block sent complete interrupt enable - 10 - 1 - - - DOCMDIEN - Command acting interrupt enable - 11 - 1 - - - DOTXIEN - Data transmit acting interrupt enable - 12 - 1 - - - DORXIEN - Data receive acting interrupt enable - 13 - 1 - - - TXBUFHIEN - Tx buffer half empty interrupt enable - 14 - 1 - - - RXBUFHIEN - Rx buffer half empty interrupt enable - 15 - 1 - - - TXBUFFIEN - Tx buffer full interrupt enable - 16 - 1 - - - RXBUFFIEN - Rx buffer full interrupt enable - 17 - 1 - - - TXBUFEIEN - Tx buffer empty interrupt enable - 18 - 1 - - - RXBUFEIEN - Rx buffer empty interrupt enable - 19 - 1 - - - TXBUFIEN - Tx buffer data vaild interrupt enable - 20 - 1 - - - RXBUFIEN - Rx buffer data vaild interrupt enable - 21 - 1 - - - IOIFIEN - SD I/O interrupt enable - 22 - 1 - - - - - BUFCNT - BUFCNT - Bits 23:0 = BUFCOUNT: Remaining number of - words to be written to or read from the - FIFO - 0x48 - 0x20 - read-only - 0x00000000 - - - CNT - FIF0COUNT - 0 - 24 - - - - - BUF - BUF - bits 31:0 = Buffer Data: Receive and transmit - buffer data - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - Buffer data - 0 - 32 - - - - - - - RTC - Real time clock - RTC - 0x40002800 - - 0x0 - 0x400 - registers - - - RTC - RTC global interrupt - 3 - - - - CTRLH - CTRLH - RTC Control Register High - 0x0 - 0x20 - read-write - 0x00000000 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - TAIEN - Time alarm interrupt enable - 1 - 1 - - - TSIEN - Time second interrupt enable - 2 - 1 - - - - - CTRLL - CTRLL - RTC Control Register Low - 0x4 - 0x20 - 0x00000020 - - - TSF - Time second flag - 0 - 1 - read-write - - - TAF - Time alarm flag - 1 - 1 - read-write - - - OVFF - Overflow Flag - 2 - 1 - read-write - - - UPDF - RTC update finish - 3 - 1 - read-write - - - CFGEN - RTC configuration enable - 4 - 1 - read-write - - - CFGF - RTC configuration finish - 5 - 1 - read-only - - - - - DIVH - DIVH - RTC Divider Register - High - 0x8 - 0x20 - write-only - 0x00000000 - - - DIV - RTC divider high - 0 - 4 - - - - - DIVL - DIVL - RTC Divider Register - Low - 0xC - 0x20 - write-only - 0x8000 - - - DIV - RTC divider low - 0 - 16 - - - - - DIVCNTH - DIVCNTH - RTC Divider Register High - 0x10 - 0x20 - read-write - 0x00000000 - - - DIVCNT - RTC divider register high - 0 - 4 - - - - - DIVCNTL - DIVCNTL - RTC Divider Register Low - 0x14 - 0x20 - read-write - 0x8000 - - - DIVCNT - RTC divider register low - 0 - 16 - - - - - CNTH - CNTH - RTC Counter Register High - 0x18 - 0x20 - read-write - 0x00000000 - - - CNT - RTC counter register high - 0 - 16 - - - - - CNTL - CNTL - RTC Counter Register Low - 0x1C - 0x20 - read-write - 0x00000000 - - - CNT - RTC counter register low - 0 - 16 - - - - - TAH - TAH - RTC Alarm Register High - 0x20 - 0x20 - write-only - 0xFFFF - - - TA - Time alarm register high - 0 - 16 - - - - - TAL - TAL - Time alarm register low - 0x24 - 0x20 - write-only - 0xFFFF - - - TA - RTC alarm register low - 0 - 16 - - - - - - - BPR - Battery powered register - BPR - 0x40006C04 - - 0x0 - 0x3FC - registers - - - - DT1 - DT1 - Battery powered domain data - register (BPR_DTx) - 0x0 - 0x20 - read-write - 0x00000000 - - - DT1 - BPR data1 - 0 - 16 - - - - - DT2 - DT2 - Battery powered domain data - register (BPR_DTx) - 0x4 - 0x20 - read-write - 0x00000000 - - - DT2 - BPR data2 - 0 - 16 - - - - - DT3 - DT3 - Battery powered domain data - register (BPR_DTx) - 0x8 - 0x20 - read-write - 0x00000000 - - - DT3 - BPR data3 - 0 - 16 - - - - - DT4 - DT4 - Battery powered domain data - register (BPR_DTx) - 0xC - 0x20 - read-write - 0x00000000 - - - DT4 - BPR data4 - 0 - 16 - - - - - DT5 - DT5 - Battery powered domain data - register (BPR_DTx) - 0x10 - 0x20 - read-write - 0x00000000 - - - DT5 - BPR data5 - 0 - 16 - - - - - DT6 - DT6 - Battery powered domain data - register (BPR_DTx) - 0x14 - 0x20 - read-write - 0x00000000 - - - DT6 - BPR data6 - 0 - 16 - - - - - DT7 - DT7 - Battery powered domain data - register (BPR_DTx) - 0x18 - 0x20 - read-write - 0x00000000 - - - DT7 - BPR data7 - 0 - 16 - - - - - DT8 - DT8 - Battery powered domain data - register (BPR_DTx) - 0x1C - 0x20 - read-write - 0x00000000 - - - DT8 - BPR data8 - 0 - 16 - - - - - DT9 - DT9 - Battery powered domain data - register (BPR_DTx) - 0x20 - 0x20 - read-write - 0x00000000 - - - DT9 - BPR data9 - 0 - 16 - - - - - DT10 - DT10 - Battery powered domain data - register (BPR_DTx) - 0x24 - 0x20 - read-write - 0x00000000 - - - DT10 - BPR data10 - 0 - 16 - - - - - DT11 - DT11 - Battery powered domain data - register (BPR_DTx) - 0x3C - 0x20 - read-write - 0x00000000 - - - DT11 - BPR data11 - 0 - 16 - - - - - DT12 - DT12 - Battery powered domain data - register (BPR_DTx) - 0x40 - 0x20 - read-write - 0x00000000 - - - DT12 - BPR data12 - 0 - 16 - - - - - DT13 - DT13 - Battery powered domain data - register (BPR_DTx) - 0x44 - 0x20 - read-write - 0x00000000 - - - DT13 - BPR data13 - 0 - 16 - - - - - DT14 - DT14 - Battery powered domain data - register (BPR_DTx) - 0x48 - 0x20 - read-write - 0x00000000 - - - DT14 - BPR data14 - 0 - 16 - - - - - DT15 - DT15 - Battery powered domain data - register (BPR_DTx) - 0x4C - 0x20 - read-write - 0x00000000 - - - DT15 - BPR data15 - 0 - 16 - - - - - DT16 - DT16 - Battery powered domain data - register (BPR_DTx) - 0x50 - 0x20 - read-write - 0x00000000 - - - DT16 - BPR data16 - 0 - 16 - - - - - DT17 - DT17 - Battery powered domain data - register (BPR_DTx) - 0x54 - 0x20 - read-write - 0x00000000 - - - DT17 - BPR data17 - 0 - 16 - - - - - DT18 - DT18 - Battery powered domain data - register (BPR_DTx) - 0x58 - 0x20 - read-write - 0x00000000 - - - DT18 - BPR data18 - 0 - 16 - - - - - DT19 - DT19 - Battery powered domain data - register (BPR_DTx) - 0x5C - 0x20 - read-write - 0x00000000 - - - DT19 - BPR data19 - 0 - 16 - - - - - DT20 - DT20 - Battery powered domain data - register (BPR_DTx) - 0x60 - 0x20 - read-write - 0x00000000 - - - DT20 - BPR data20 - 0 - 16 - - - - - DT21 - DT21 - Battery powered domain data - register (BPR_DTx) - 0x64 - 0x20 - read-write - 0x00000000 - - - DT21 - BPR data21 - 0 - 16 - - - - - DT22 - DT22 - Battery powered domain data - register (BPR_DTx) - 0x68 - 0x20 - read-write - 0x00000000 - - - DT22 - BPR data22 - 0 - 16 - - - - - DT23 - DT23 - Battery powered domain data - register (BPR_DTx) - 0x6C - 0x20 - read-write - 0x00000000 - - - DT23 - BPR data23 - 0 - 16 - - - - - DT24 - DT24 - Battery powered domain data - register (BPR_DTx) - 0x70 - 0x20 - read-write - 0x00000000 - - - DT24 - BPR data24 - 0 - 16 - - - - - DT25 - DT25 - Battery powered domain data - register (BPR_DTx) - 0x74 - 0x20 - read-write - 0x00000000 - - - DT25 - BPR data25 - 0 - 16 - - - - - DT26 - DT26 - Battery powered domain data - register (BPR_DTx) - 0x78 - 0x20 - read-write - 0x00000000 - - - DT26 - BPR data26 - 0 - 16 - - - - - DT27 - DT27 - Battery powered domain data - register (BPR_DTx) - 0x7C - 0x20 - read-write - 0x00000000 - - - DT27 - BPR data27 - 0 - 16 - - - - - DT28 - DT28 - Battery powered domain data - register (BPR_DTx) - 0x80 - 0x20 - read-write - 0x00000000 - - - DT28 - BPR data28 - 0 - 16 - - - - - DT29 - DT29 - Battery powered domain data - register (BPR_DTx) - 0x84 - 0x20 - read-write - 0x00000000 - - - DT29 - BPR data29 - 0 - 16 - - - - - DT30 - DT30 - Battery powered domain data - register (BPR_DTx) - 0x88 - 0x20 - read-write - 0x00000000 - - - DT30 - BPR data30 - 0 - 16 - - - - - DT31 - DT31 - Battery powered domain data - register (BPR_DTx) - 0x8C - 0x20 - read-write - 0x00000000 - - - DT31 - BPR data31 - 0 - 16 - - - - - DT32 - DT32 - Battery powered domain data - register (BPR_DTx) - 0x90 - 0x20 - read-write - 0x00000000 - - - DT32 - BPR data32 - 0 - 16 - - - - - DT33 - DT33 - Battery powered domain data - register (BPR_DTx) - 0x94 - 0x20 - read-write - 0x00000000 - - - DT33 - BPR data33 - 0 - 16 - - - - - DT34 - DT34 - Battery powered domain data - register (BPR_DTx) - 0x98 - 0x20 - read-write - 0x00000000 - - - DT34 - BPR data34 - 0 - 16 - - - - - DT35 - DT35 - Battery powered domain data - register (BPR_DTx) - 0x9C - 0x20 - read-write - 0x00000000 - - - DT35 - BPR data35 - 0 - 16 - - - - - DT36 - DT36 - Battery powered domain data - register (BPR_DTx) - 0xA0 - 0x20 - read-write - 0x00000000 - - - DT36 - BPR data36 - 0 - 16 - - - - - DT37 - DT37 - Battery powered domain data - register (BPR_DTx) - 0xA4 - 0x20 - read-write - 0x00000000 - - - DT37 - BPR data37 - 0 - 16 - - - - - DT38 - DT38 - Battery powered domain data - register (BPR_DTx) - 0xA8 - 0x20 - read-write - 0x00000000 - - - DT38 - BPR data38 - 0 - 16 - - - - - DT39 - DT39 - Battery powered domain data - register (BPR_DTx) - 0xAC - 0x20 - read-write - 0x00000000 - - - DT39 - BPR data39 - 0 - 16 - - - - - DT40 - DT40 - Battery powered domain data - register (BPR_DTx) - 0xB0 - 0x20 - read-write - 0x00000000 - - - DT40 - BPR data40 - 0 - 16 - - - - - DT41 - DT41 - Battery powered domain data - register (BPR_DTx) - 0xB4 - 0x20 - read-write - 0x00000000 - - - DT41 - BPR data41 - 0 - 16 - - - - - DT42 - DT42 - Battery powered domain data - register (BPR_DTx) - 0xB8 - 0x20 - read-write - 0x00000000 - - - DT42 - BPR data42 - 0 - 16 - - - - - RTCCAL - RTCCAL - RTC clock calibration register - (BPR_RTCCAL) - 0x28 - 0x20 - read-write - 0x00000000 - - - CALVAL - Calibration value - 0 - 7 - - - CALOUT - Calibration Clock Output - 7 - 1 - - - OUTEN - Output enable - 8 - 1 - - - OUTSEL - Output selection - 9 - 1 - - - - - CTRL - CTRL - BPR control register - (BPR_CTRL) - 0x2C - 0x20 - read-write - 0x00000000 - - - TPEN - Tamper pin enable - 0 - 1 - - - TPP - TAMPER pin polarity - 1 - 1 - - - - - CTRLSTS - CTRLSTS - BPR control/status register - (BPR_CTRLSTS) - 0x30 - 0x20 - 0x00000000 - - - TPEFCLR - Tamper event flag clear - 0 - 1 - write-only - - - TPIFCLR - Tamper interrupt flag clear - 1 - 1 - write-only - - - TPIEN - Tamper pin interrupt enable - 2 - 1 - read-write - - - TPEF - Tamper event flag - 8 - 1 - read-write - - - TPIF - Tamper interrupt flag - 9 - 1 - read-write - - - - - - - WDT - Watchdog - WDT - 0x40003000 - - 0x0 - 0x400 - registers - - - - CMD - CMD - Command register - 0x0 - 0x20 - read-write - 0x00000000 - - - CMD - Command register - 0 - 16 - - - - - DIV - DIV - Division register - 0x4 - 0x20 - read-write - 0x00000000 - - - DIV - Division divider - 0 - 3 - - - - - RLD - RLD - Reload register - 0x8 - 0x20 - read-write - 0x00000FFF - - - RLD - Reload value - 0 - 12 - - - - - STS - STS - Status register - 0xC - 0x20 - read-write - 0x00000000 - - - DIVF - Division value update complete flag - 0 - 1 - - - RLDF - Reload value update complete flag - 1 - 1 - - - - - - - WWDT - Window watchdog - WWDT - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDT - Window Watchdog interrupt - 0 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - read-write - 0x0000007F - - - CNT - Decrement counter - 0 - 7 - - - WWDTEN - Window watchdog enable - 7 - 1 - - - - - CFG - CFG - Configuration register - 0x4 - 0x20 - read-write - 0x0000007F - - - WIN - Window value - 0 - 7 - - - DIV - Clock division value - 7 - 2 - - - RLDIEN - Reload counter interrupt - 9 - 1 - - - - - STS - STS - Status register - 0x8 - 0x20 - read-write - 0x00000000 - - - RLDF - Reload counter interrupt flag - 0 - 1 - - - - - - - TMR1 - Advanced timer - TIMER - 0x40012C00 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - TMR1_CH - TMR1 channel interrupt - 27 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C4IOS - Channel 4 idle output state - 14 - 1 - - - C3CIOS - Channel 3 complementary idle output state - 13 - 1 - - - C3IOS - Channel 3 idle output state - 12 - 1 - - - C2CIOS - Channel 2 complementary idle output state - 11 - 1 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3CP - Channel 3 complementary polarity - 11 - 1 - - - C3CEN - Channel 3 complementary enable - 10 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR8 - 0x40013400 - - TMR8_BRK_TMR12 - TMR8 brake interrupt and TMR12 global - interrupt - 43 - - - TMR8_OVF_TMR13 - TMR8 overflow interrupt and TMR13 global - interrupt - 44 - - - TMR8_TRG_HALL_TMR14 - TMR8 trigger and HALL interrupts and - TMR14 global interrupt - 45 - - - TMR8_CH - TMR8 channel interrupt - 46 - - - - TMR2 - General purpose timer - TIMER - 0x40000000 - - 0x0 - 0x400 - registers - - - TMR2 - TMR2 global interrupt - 28 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PMEN - Plus Mode Enable - 10 - 1 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 32 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 32 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 32 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 32 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 32 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 32 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR3 - General purpose timer - TIMER - 0x40000400 - - 0x0 - 0x400 - registers - - - TMR3 - TMR3 global interrupt - 29 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR4 - 0x40000800 - - TMR4 - TMR4 global interrupt - 30 - - - - TMR5 - 0x40000C00 - - TMR5 - TMR5 global interrupt - 50 - - - - TMR9 - General purpose timer - TIMER - 0x40014C00 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - - - TMR10 - General purpose timer - TIMER - 0x40015000 - - 0x0 - 0x400 - registers - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - - - TMR11 - 0x40015400 - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - - ACC - HICK Auto Clock Calibration - ACC - 0x40015800 - - 0x0 - 0x400 - registers - - - - STS - STS - status register - 0x0 - 0x20 - 0x0000 - - - RSLOST - Reference Signal Lost - read-write - 1 - 1 - - - CALRDY - Internal high-speed clock calibration ready - read-write - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x04 - 0x20 - 0x0100 - - - STEP - STEP - read-write - 8 - 4 - - - CALRDYIEN - CALRDY interrupt enable - read-write - 5 - 1 - - - EIEN - RSLOST error interrupt enable - read-write - 4 - 1 - - - ENTRIM - Enable trim - read-write - 1 - 1 - - - CALON - Calibration on - read-write - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x08 - 0x20 - 0x2080 - - - HICKTWK - Internal high-speed auto clock trimming - read-only - 8 - 6 - - - HICKCAL - Internal high-speed auto clock calibration - read-only - 0 - 8 - - - - - C1 - C1 - compare value 1 - 0x0C - 0x20 - 0x1F2C - - - C1 - Compare 1 - read-write - 0 - 16 - - - - - C2 - C2 - compare value 2 - 0x10 - 0x20 - 0x1F40 - - - C2 - Compare 2 - read-write - 0 - 16 - - - - - C3 - C3 - compare value 3 - 0x14 - 0x20 - 0x1F54 - - - C3 - Compare 3 - read-write - 0 - 16 - - - - - - - I2C1 - Inter integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1_EVT - I2C1 event interrupt - 31 - - - I2C1_ERR - I2C1 error interrupt - 32 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - RESET - I2C peripheral reset - 15 - 1 - - - SMBALERT - SMBus alert pin set - 13 - 1 - - - PECTEN - Request PEC transmission enable - 12 - 1 - - - MACKCTRL - Master receiving mode acknowledge control - 11 - 1 - - - ACKEN - Acknowledge enable - 10 - 1 - - - GENSTOP - Stop generation - 9 - 1 - - - GENSTART - Start generation - 8 - 1 - - - STRETCH - Clock stretching mode - 7 - 1 - - - GCAEN - General call address enable - 6 - 1 - - - PECEN - PEC calculation enable - 5 - 1 - - - ARPEN - SMBus address resolution protocol enable - 4 - 1 - - - SMBMODE - SMBus device mode - 3 - 1 - - - PERMODE - I2C peripheral mode - 1 - 1 - - - I2CEN - Peripheral enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - DMAEND - DMA transfer end indication - 12 - 1 - - - DMAEN - DMA transfer enable - 11 - 1 - - - DATAIEN - Data transmission interrupt enable - 10 - 1 - - - EVTIEN - Event interrupt enable - 9 - 1 - - - ERRIEN - Error interrupt enable - 8 - 1 - - - CLKFREQ - Input clock frequency - 0 - 8 - - - - - OADDR1 - OADDR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - ADDR1MODE - Address mode - 15 - 1 - - - ADDR1 - Own address 1 - 0 - 10 - - - - - OADDR2 - OADDR2 - Own address register 2 - 0xC - 0x20 - read-write - 0x0000 - - - ADDR2 - Own address 2 - 1 - 7 - - - ADDR2EN - Own address 2 enable - 0 - 1 - - - - - DT - DT - Data register - 0x10 - 0x20 - read-write - 0x0000 - - - DT - data register - 0 - 8 - - - - - STS1 - STS1 - Status register 1 - 0x14 - 0x20 - 0x0000 - - - ALERTF - SMBus alert - 15 - 1 - read-write - - - TMOUT - Timeout error - 14 - 1 - read-write - - - PECERR - PEC receive error - 12 - 1 - read-write - - - OUF - Overflow or underflow - 11 - 1 - read-write - - - ACKFAIL - Acknowledge failure - 10 - 1 - read-write - - - ARLOST - Arbitration lost (master - mode) - 9 - 1 - read-write - - - BUSERR - Bus error - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - (transmitters) - 7 - 1 - read-only - - - RDBF - Receive data buffer full - (receivers) - 6 - 1 - read-only - - - STOPF - Stop detection (slave - mode) - 4 - 1 - read-only - - - ADDRHF - address header match (Master - mode) - 3 - 1 - read-only - - - TDC - Transmit data complete - 2 - 1 - read-only - - - ADDR7F - Address sent (master mode)/matched - (slave mode) - 1 - 1 - read-only - - - STARTF - Start bit (Master mode) - 0 - 1 - read-only - - - - - STS2 - STS2 - Status register 2 - 0x18 - 0x20 - read-only - 0x0000 - - - PECVAL - PEC value - 8 - 8 - - - ADDR2F - Received address 2 - 7 - 1 - - - HOSTADDRF - SMBus host address receiving - 6 - 1 - - - DEVADDRF - SMBus device address receiving - 5 - 1 - - - GCADDRF - General call address reception - 4 - 1 - - - DIRF - Transmission direction - 2 - 1 - - - BUSYF - Bus busy - 1 - 1 - - - TRMODE - Transmission mode - 0 - 1 - - - - - CLKCTRL - CLKCTRL - Clock control register - 0x1C - 0x20 - read-write - 0x0000 - - - SPEEDMODE - Speed mode selection - 15 - 1 - - - DUTYMODE - Fast mode duty cycle - 14 - 1 - - - SPEED - I2C bus speed config - 0 - 12 - - - - - TMRISE - TMRISE - TRISE register - 0x20 - 0x20 - read-write - 0x0002 - - - RISETIME - I2C bus rise time - 0 - 6 - - - - - - - I2C2 - 0x40005800 - - I2C2_EVT - I2C2 event interrupt - 33 - - - I2C2_ERR - I2C2 error interrupt - 34 - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global interrupt - 35 - - - - CTRL1 - CTRL1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SLBEN - Single line bidirectional half-duplex enable - 15 - 1 - - - SLBTD - Single line bidirectional half-duplex transmission direction - 14 - 1 - - - CCEN - CRC calculation enable - 13 - 1 - - - NTC - Next transmission CRC - 12 - 1 - - - FBN - frame bit num - 11 - 1 - - - ORA - Only receive active - 10 - 1 - - - SWCSEN - Software CS enable - 9 - 1 - - - SWCSIL - Software CS internal level - 8 - 1 - - - LTF - LSB transmit first - 7 - 1 - - - SPIEN - SPI enable - 6 - 1 - - - MDIV2_0 - Master clock frequency division bit2-0 - 3 - 3 - - - MSTEN - Master enable - 2 - 1 - - - CLKPOL - Clock polarity - 1 - 1 - - - CLKPHA - Clock phase - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MDIV3 - Master clock frequency division bit3 - 8 - 1 - - - TDBEIE - Transmit data buffer empty interrupt enable - 7 - 1 - - - RDBFIE - Receive data buffer full interrupt enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - HWCSOE - Hardware CS output enable - 2 - 1 - - - DMATEN - DMA transmit enable - 1 - 1 - - - DMAREN - DMA receive enable - 0 - 1 - - - - - STS - STS - status register - 0x8 - 0x20 - 0x0002 - - - BF - Busy flag - 7 - 1 - read-only - - - ROERR - Receiver overflow error - 6 - 1 - read-only - - - MMERR - Master mode error - 5 - 1 - read-only - - - CCERR - CRC calculation error - 4 - 1 - read-write - - - TUERR - Transmitter underload error - 3 - 1 - read-only - - - ACS - Audio channel state - 2 - 1 - read-only - - - TDBE - Transmit data buffer empty - 1 - 1 - read-only - - - RDBF - Receive data buffer full - 0 - 1 - read-only - - - - - DT - DT - data register - 0xC - 0x20 - read-write - 0x0000 - - - DT - Data value - 0 - 16 - - - - - CPOLY - CPOLY - CRC polynomial register - 0x10 - 0x20 - read-write - 0x0007 - - - CPOLY - CRC polynomial - 0 - 16 - - - - - RCRC - RCRC - Receive CRC register - 0x14 - 0x20 - read-only - 0x0000 - - - RCRC - Receive CRC - 0 - 16 - - - - - TCRC - TCRC - Transmit CRC register - 0x18 - 0x20 - read-only - 0x0000 - - - TCRC - Transmit CRC - 0 - 16 - - - - - I2SCTRL - I2SCTRL - I2S control register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SMSEL - I2S mode select - 11 - 1 - - - I2SEN - I2S Enable - 10 - 1 - - - OPERSEL - I2S operation select - 8 - 2 - - - PCMFSSEL - PCM frame synchronization select - 7 - 1 - - - STDSEL - I2S standard select - 4 - 2 - - - I2SCLKPOL - I2S clock polarity - 3 - 1 - - - I2SDBN - I2S data bit num - 1 - 2 - - - I2SCBN - I2S channel bit num - 0 - 1 - - - - - I2SCLK - I2SCLK - I2S clock register - 0x20 - 0x20 - read-write - 00000010 - - - I2SDIV9_8 - I2S division bit9 and bit8 - 10 - 2 - - - I2SMCLKOE - I2S master clock output enable - 9 - 1 - - - I2SODD - Odd result for I2S division - 8 - 1 - - - I2SDIV7_0 - I2S division bit7 to bit0 - 0 - 8 - - - - - - - SPI2 - 0x40003800 - - SPI2 - SPI2 global interrupt - 36 - - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40013800 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global interrupt - 37 - - - - STS - STS - Status register - 0x0 - 0x20 - 0x00C0 - - - CTSCF - CTS change flag - 9 - 1 - read-write - - - BFF - Break frame flag - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - 7 - 1 - read-only - - - TDC - Transmit data complete - 6 - 1 - read-write - - - RDBF - Receive data buffer full - 5 - 1 - read-write - - - IDLEF - IDLE flag - 4 - 1 - read-only - - - ROERR - Receiver overflow error - 3 - 1 - read-only - - - NERR - Noise error - 2 - 1 - read-only - - - FERR - Framing error - 1 - 1 - read-only - - - PERR - Parity error - 0 - 1 - read-only - - - - - DT - DT - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DT - Data value - 0 - 9 - - - - - BAUDR - BAUDR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV - Division - 0 - 16 - - - - - CTRL1 - CTRL1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - UEN - USART enable - 13 - 1 - - - DBN - Data bit num - 12 - 1 - - - WUM - Wake up mode - 11 - 1 - - - PEN - Parity enable - 10 - 1 - - - PSEL - Parity selection - 9 - 1 - - - PERRIEN - PERR interrupt enable - 8 - 1 - - - TDBEIEN - TDBE interrupt enable - 7 - 1 - - - TDCIEN - TDC interrupt enable - 6 - 1 - - - RDBFIEN - RDBF interrupt enable - 5 - 1 - - - IDLEIEN - IDLE interrupt enable - 4 - 1 - - - TEN - Transmitter enable - 3 - 1 - - - REN - Receiver enable - 2 - 1 - - - RM - Receiver mute - 1 - 1 - - - SBF - Send break frame - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - LINEN - LIN mode enable - 14 - 1 - - - STOPBN - STOP bit num - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CLKPOL - Clock polarity - 10 - 1 - - - CLKPHA - Clock phase - 9 - 1 - - - LBCP - Last bit clock pulse - 8 - 1 - - - BFIEN - Break frame interrupt enable - 6 - 1 - - - BFBN - Break frame bit num - 5 - 1 - - - ID - USART identification - 0 - 4 - - - - - CTRL3 - CTRL3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - CTSCFIEN - CTSCF interrupt enable - 10 - 1 - - - CTSEN - CTS enable - 9 - 1 - - - RTSEN - RTS enable - 8 - 1 - - - DMATEN - DMA transmitter enable - 7 - 1 - - - DMAREN - DMA receiver enable - 6 - 1 - - - SCMEN - Smartcard mode enable - 5 - 1 - - - SCNACKEN - Smartcard NACK enable - 4 - 1 - - - SLBEN - Single line bidirectional half-duplex enable - 3 - 1 - - - IRDALP - IrDA low-power mode - 2 - 1 - - - IRDAEN - IrDA enable - 1 - 1 - - - ERRIEN - Error interrupt enable - 0 - 1 - - - - - GDIV - GDIV - Guard time and division register - 0x18 - 0x20 - read-write - 0x0000 - - - SCGT - Smart card guard time value - 8 - 8 - - - ISDIV - IrDA/smartcard division value - 0 - 8 - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global interrupt - 38 - - - - USART3 - 0x40004800 - - USART3 - USART3 global interrupt - 39 - - - - ADC1 - Analog to digital converter - ADC - 0x40012400 - - 0x0 - 0x400 - registers - - - ADC1_2 - ADC1 and ADC2 global interrupt - 18 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - CCE - Channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - MSSEL - Master slave mode select - 16 - 4 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - CCEIEN - Channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - OCTESEL_H - High bit of trigger event select for ordinary channels conversion - 25 - 1 - - - PCTESEL_H - High bit of trigger event select for preempted channels conversion - 24 - 1 - - - ITSRVEN - Internal temperature sensor and VINTRV enable - 23 - 1 - - - OCSWTRG - Conversion trigger by software of ordinary channels - 22 - 1 - - - PCSWTRG - Conversion trigger by software of preempted channels - 21 - 1 - - - OCTEN - Trigger mode enable for ordinary channels conversion - 20 - 1 - - - OCTESEL_L - Low bit of trigger event select for ordinary channels conversion - 17 - 3 - - - PCTEN - Trigger mode enable for preempted channels conversion - 15 - 1 - - - PCTESEL_L - Low bit of trigger event select for preempted channels conversion - 12 - 3 - - - DTALIGN - Data alignment - 11 - 1 - - - OCDMAEN - DMA transfer enable of ordinary channels - 8 - 1 - - - ADCALINIT - initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 12 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 12 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 4 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ADC2ODT - ADC2 conversion data of ordinary channel - 16 - 16 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - - - ADC2 - Analog to digital converter - ADC - 0x40012800 - - 0x0 - 0x400 - registers - - - ADC1_2 - ADC1 and ADC2 global interrupt - 18 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - CCE - Channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - CCEIEN - Channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - OCTESEL_H - High bit of trigger event select for ordinary channels conversion - 25 - 1 - - - PCTESEL_H - High bit of trigger event select for preempted channels conversion - 24 - 1 - - - OCSWTRG - Conversion trigger by software of ordinary channels - 22 - 1 - - - PCSWTRG - Conversion trigger by software of preempted channels - 21 - 1 - - - OCTEN - Trigger mode enable for ordinary channels conversion - 20 - 1 - - - OCTESEL_L - Low bit of trigger event select for ordinary channels conversion - 17 - 3 - - - PCTEN - Trigger mode enable for preempted channels conversion - 15 - 1 - - - PCTESEL_L - Low bit of trigger event select for preempted channels conversion - 12 - 3 - - - DTALIGN - Data alignment - 11 - 1 - - - ADCALINIT - initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 12 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 12 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 4 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - - - CAN1 - Can controller area network - CAN - 0x40006400 - - 0x0 - 0x400 - registers - - - USBFS_H_CAN1_TX - CAN1 TX interrupt - 19 - - - USBFS_L_CAN1_RX0 - CAN1 RX0 interrupt - 20 - - - CAN_RX1 - CAN1 RX1 interrupt - 21 - - - CAN_SE - CAN1 SE interrupt - 22 - - - - MCTRL - MCTRL - Main control register - 0x0 - 0x20 - read-write - 0x00010002 - - - PTD - Prohibit transmission when debug - 16 - 1 - - - SPRST - Software partial reset - 15 - 1 - - - TTCEN - Time triggered communication mode enable - 7 - 1 - - - AEBOEN - Automatic exit bus-off enable - 6 - 1 - - - AEDEN - Automatic exit doze mode enable - 5 - 1 - - - PRSFEN - Prohibit retransmission when sending fails enable - 4 - 1 - - - MDRSEL - Message discarding rule select when overflow - 3 - 1 - - - MMSSR - Multiple message sending sequence rule - 2 - 1 - - - DZEN - Doze mode enable - 1 - 1 - - - FZEN - Freeze mode enable - 0 - 1 - - - - - MSTS - MSTS - Main status register - 0x4 - 0x20 - 0x00000C02 - - - REALRX - Real time level of RX pin - 11 - 1 - read-only - - - LSAMPRX - Last sample level of RX pin - 10 - 1 - read-only - - - CURS - Currently receiving status - 9 - 1 - read-only - - - CUSS - Currently sending status - 8 - 1 - read-only - - - EDZIF - Enter doze mode interrupt flag - 4 - 1 - read-write - - - QDZIF - Quit doze mode interrupt flag - 3 - 1 - read-write - - - EOIF - Error occur Interrupt flag - 2 - 1 - read-write - - - DZC - Doze mode confirm - 1 - 1 - read-only - - - FZC - Freeze mode confirm - 0 - 1 - read-only - - - - - TSTS - TSTS - Transmit status register - 0x8 - 0x20 - 0x1C000000 - - - TM2LPF - Transmit mailbox 2 lowest priority flag - 31 - 1 - read-only - - - TM1LPF - Transmit mailbox 1 lowest priority flag - 30 - 1 - read-only - - - TM0LPF - Transmit mailbox 0 lowest priority flag - 29 - 1 - read-only - - - TM2EF - Transmit mailbox 2 empty flag - 28 - 1 - read-only - - - TM1EF - Transmit mailbox 1 empty flag - 27 - 1 - read-only - - - TM0EF - Transmit mailbox 0 empty flag - 26 - 1 - read-only - - - TMNR - Transmit Mailbox number record - 24 - 2 - read-only - - - TM2CT - Transmit mailbox 2 cancel transmission - 23 - 1 - read-write - - - TM2TEF - Transmit mailbox 2 transmission error flag - 19 - 1 - read-write - - - TM2ALF - Transmit mailbox 2 arbitration lost flag - 18 - 1 - read-write - - - TM2TSF - Transmit mailbox 2 transmission success flag - 17 - 1 - read-write - - - TM2TCF - transmit mailbox 2 transmission complete flag - 16 - 1 - read-write - - - TM1CT - Transmit mailbox 1 cancel transmission - 15 - 1 - read-write - - - TM1TEF - Transmit mailbox 1 transmission error flag - 11 - 1 - read-write - - - TM1ALF - Transmit mailbox 1 arbitration lost flag - 10 - 1 - read-write - - - TM1TSF - Transmit mailbox 1 transmission success flag - 9 - 1 - read-write - - - TM1TCF - Transmit mailbox 1 transmission complete flag - 8 - 1 - read-write - - - TM0CT - Transmit mailbox 0 cancel transmission - 7 - 1 - read-write - - - TM0TEF - Transmit mailbox 0 transmission error flag - 3 - 1 - read-write - - - TM0ALF - Transmit mailbox 0 arbitration lost flag - 2 - 1 - read-write - - - TM0TSF - Transmit mailbox 0 transmission success flag - 1 - 1 - read-write - - - TM0TCF - Transmit mailbox 0 transmission complete flag - 0 - 1 - read-write - - - - - RF0 - RF0 - Receive FIFO 0 register - 0xC - 0x20 - 0x00000000 - - - RF0R - Receive FIFO 0 release - 5 - 1 - read-write - - - RF0OF - Receive FIFO 0 overflow flag - 4 - 1 - read-write - - - RF0FF - Receive FIFO 0 full flag - 3 - 1 - read-write - - - RF0MN - Receive FIFO 0 message num - 0 - 2 - read-only - - - - - RF1 - RF1 - Receive FIFO 1 register - 0x10 - 0x20 - 0x00000000 - - - RF1R - Receive FIFO 1 release - 5 - 1 - read-write - - - RF1OF - Receive FIFO 1 overflow flag - 4 - 1 - read-write - - - RF1FF - Receive FIFO 1 full flag - 3 - 1 - read-write - - - RF1MN - Receive FIFO 1 message num - 0 - 2 - read-only - - - - - INTEN - INTEN - Interrupt enable register - 0x14 - 0x20 - read-write - 0x00000000 - - - EDZIEN - Enter doze mode interrupt enable - 17 - 1 - - - QDZIEN - Quit doze mode interrupt enable - 16 - 1 - - - EOIEN - Error occur interrupt enable - 15 - 1 - - - ETRIEN - Error type record interrupt enable - 11 - 1 - - - BOIEN - Bus-off interrupt enable - 10 - 1 - - - EPIEN - Error passive interrupt enable - 9 - 1 - - - EAIEN - Error active interrupt enable - 8 - 1 - - - RF1OIEN - Receive FIFO 1 overflow interrupt enable - 6 - 1 - - - RF1FIEN - Receive FIFO 1 full interrupt enable - 5 - 1 - - - RF1MIEN - FIFO 1 receive message interrupt enable - 4 - 1 - - - RF0OIEN - Receive FIFO 0 overflow interrupt enable - 3 - 1 - - - RF0FIEN - Receive FIFO 0 full interrupt enable - 2 - 1 - - - RF0MIEN - FIFO 0 receive message interrupt enable - 1 - 1 - - - TCIEN - Transmission complete interrupt enable - 0 - 1 - - - - - ESTS - ESTS - Error status register - 0x18 - 0x20 - 0x00000000 - - - REC - Receive error counter - 24 - 8 - read-only - - - TEC - Transmit error counter - 16 - 8 - read-only - - - ETR - Error type record - 4 - 3 - read-write - - - BOF - Bus-off flag - 2 - 1 - read-only - - - EPF - Error passive flag - 1 - 1 - read-only - - - EAF - Error active flag - 0 - 1 - read-only - - - - - BTMG - BTMG - Bit timing register - 0x1C - 0x20 - read-write - 0x00000000 - - - LOEN - Listen-Only mode - 31 - 1 - - - LBEN - Loop back mode - 30 - 1 - - - RSAW - Resynchronization adjust width - 24 - 2 - - - BTS2 - Bit time segment 2 - 20 - 3 - - - BTS1 - Bit time segment 1 - 16 - 4 - - - BRDIV - Baud rate division - 0 - 12 - - - - - TMI0 - TMI0 - Transmit mailbox 0 identifier register - 0x180 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC0 - TMC0 - Transmit mailbox 0 data length and time stamp register - 0x184 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL0 - TMDTL0 - Transmit mailbox 0 low byte data register - 0x188 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH0 - TMDTH0 - Transmit mailbox 0 high byte data register - 0x18C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI1 - TMI1 - Transmit mailbox 1 identifier register - 0x190 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC1 - TMC1 - Transmit mailbox 1 data length and time stamp register - 0x194 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL1 - TMDTL1 - Transmit mailbox 1 low byte data register - 0x198 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH1 - TMDTH1 - Transmit mailbox 1 high byte data register - 0x19C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI2 - TMI2 - Transmit mailbox 2 identifier register - 0x1A0 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC2 - TMC2 - Transmit mailbox 2 data length and time stamp register - 0x1A4 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL2 - TMDTL2 - Transmit mailbox 2 low byte data register - 0x1A8 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH2 - TMDTH2 - Transmit mailbox 2 high byte data register - 0x1AC - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - RFI0 - RFI0 - Receive FIFO 0 register - 0x1B0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC0 - RFC0 - Receive FIFO 0 data length and time stamp register - 0x1B4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL0 - RFDTL0 - Receive FIFO 0 low byte data register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH0 - RFDTH0 - Receive FIFO 0 high byte data register - 0x1BC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - RFI1 - RFI1 - Receive FIFO 1 register - 0x1C0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC1 - RFC1 - Receive FIFO 1 data length and time stamp register - 0x1C4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL1 - RFDTL1 - Receive FIFO 1 low byte data register - 0x1C8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH1 - RFDTH1 - Receive FIFO 1 high byte data register - 0x1CC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - FCTRL - FCTRL - Filter control register - 0x200 - 0x20 - read-write - 0x00000000 - - - FCS - Filters configure switch - 0 - 1 - - - - - FMCFG - FMCFG - Filter mode config register - 0x204 - 0x20 - read-write - 0x00000000 - - - FMSEL0 - Filter mode select - 0 - 1 - - - FMSEL1 - Filter mode select - 1 - 1 - - - FMSEL2 - Filter mode select - 2 - 1 - - - FMSEL3 - Filter mode select - 3 - 1 - - - FMSEL4 - Filter mode select - 4 - 1 - - - FMSEL5 - Filter mode select - 5 - 1 - - - FMSEL6 - Filter mode select - 6 - 1 - - - FMSEL7 - Filter mode select - 7 - 1 - - - FMSEL8 - Filter mode select - 8 - 1 - - - FMSEL9 - Filter mode select - 9 - 1 - - - FMSEL10 - Filter mode select - 10 - 1 - - - FMSEL11 - Filter mode select - 11 - 1 - - - FMSEL12 - Filter mode select - 12 - 1 - - - FMSEL13 - Filter mode select - 13 - 1 - - - - - FBWCFG - FBWCFG - Filter bit width config register - 0x20C - 0x20 - read-write - 0x00000000 - - - FBWSEL0 - Filter bit width select - 0 - 1 - - - FBWSEL1 - Filter bit width select - 1 - 1 - - - FBWSEL2 - Filter bit width select - 2 - 1 - - - FBWSEL3 - Filter bit width select - 3 - 1 - - - FBWSEL4 - Filter bit width select - 4 - 1 - - - FBWSEL5 - Filter bit width select - 5 - 1 - - - FBWSEL6 - Filter bit width select - 6 - 1 - - - FBWSEL7 - Filter bit width select - 7 - 1 - - - FBWSEL8 - Filter bit width select - 8 - 1 - - - FBWSEL9 - Filter bit width select - 9 - 1 - - - FBWSEL10 - Filter bit width select - 10 - 1 - - - FBWSEL11 - Filter bit width select - 11 - 1 - - - FBWSEL12 - Filter bit width select - 12 - 1 - - - FBWSEL13 - Filter bit width select - 13 - 1 - - - - - FRF - FRF - Filter related FIFO register - 0x214 - 0x20 - read-write - 0x00000000 - - - FRFSEL0 - Filter relation FIFO select - 0 - 1 - - - FRFSEL1 - Filter relation FIFO select - 1 - 1 - - - FRFSEL2 - Filter relation FIFO select - 2 - 1 - - - FRFSEL3 - Filter relation FIFO select - 3 - 1 - - - FRFSEL4 - Filter relation FIFO select - 4 - 1 - - - FRFSEL5 - Filter relation FIFO select - 5 - 1 - - - FRFSEL6 - Filter relation FIFO select - 6 - 1 - - - FRFSEL7 - Filter relation FIFO select - 7 - 1 - - - FRFSEL8 - Filter relation FIFO select - 8 - 1 - - - FRFSEL9 - Filter relation FIFO select - 9 - 1 - - - FRFSEL10 - Filter relation FIFO select - 10 - 1 - - - FRFSEL11 - Filter relation FIFO select - 11 - 1 - - - FRFSEL12 - Filter relation FIFO select - 12 - 1 - - - FRFSEL13 - Filter relation FIFO select - 13 - 1 - - - - - FACFG - FACFG - Filter activate configuration register - 0x21C - 0x20 - read-write - 0x00000000 - - - FAEN0 - Filter activate enable - 0 - 1 - - - FAEN1 - Filter activate enable - 1 - 1 - - - FAEN2 - Filter activate enable - 2 - 1 - - - FAEN3 - Filter activate enable - 3 - 1 - - - FAEN4 - Filter activate enable - 4 - 1 - - - FAEN5 - Filter activate enable - 5 - 1 - - - FAEN6 - Filter activate enable - 6 - 1 - - - FAEN7 - Filter activate enable - 7 - 1 - - - FAEN8 - Filter activate enable - 8 - 1 - - - FAEN9 - Filter activate enable - 9 - 1 - - - FAEN10 - Filter activate enable - 10 - 1 - - - FAEN11 - Filter activate enable - 11 - 1 - - - FAEN12 - Filter activate enable - 12 - 1 - - - FAEN13 - Filter activate enable - 13 - 1 - - - - - F0FB1 - F0FB1 - Filter bank 0 filtrate bit register 1 - 0x240 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F0FB2 - F0FB2 - Filter bank 0 filtrate bit register 2 - 0x244 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB1 - F1FB1 - Filter bank 1 filtrate bit register 1 - 0x248 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB2 - F1FB2 - Filter bank 1 filtrate bit register 2 - 0x24C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB1 - F2FB1 - Filter bank 2 filtrate bit register 1 - 0x250 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB2 - F2FB2 - Filter bank 2 filtrate bit register 2 - 0x254 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB1 - F3FB1 - Filter bank 3 filtrate bit register 1 - 0x258 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB2 - F3FB2 - Filter bank 3 filtrate bit register 2 - 0x25C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB1 - F4FB1 - Filter bank 4 filtrate bit register 1 - 0x260 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB2 - F4FB2 - Filter bank 4 filtrate bit register 2 - 0x264 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB1 - F5FB1 - Filter bank 5 filtrate bit register 1 - 0x268 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB2 - F5FB2 - Filter bank 5 filtrate bit register 2 - 0x26C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB1 - F6FB1 - Filter bank 6 filtrate bit register 1 - 0x270 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB2 - F6FB2 - Filter bank 6 filtrate bit register 2 - 0x274 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - F7FB1 - F7FB1 - Filter bank 7 filtrate bit register 1 - 0x278 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB2 - F7FB2 - Filter bank 7 filtrate bit register 2 - 0x27C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB1 - F8FB1 - Filter bank 8 filtrate bit filtrate bit register 1 - 0x280 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB2 - F8FB2 - Filter bank 8 filtrate bit filtrate bit register 2 - 0x284 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB1 - F9FB1 - Filter bank 9 filtrate bit filtrate bit filtrate bit filtrate bit filtrate bit register 1 - 0x288 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB2 - F9FB2 - Filter bank 9 filtrate bit filtrate bit filtrate bit filtrate bit filtrate bit register 2 - 0x28C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB1 - F10FB1 - Filter bank 10 filtrate bit register 1 - 0x290 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB2 - F10FB2 - Filter bank 10 filtrate bit register 2 - 0x294 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB1 - F11FB1 - Filter bank 11 filtrate bit register 1 - 0x298 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB2 - F11FB2 - Filter bank 11 filtrate bit register 2 - 0x29C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB1 - F12FB1 - Filter bank 12 filtrate bit filtrate bit register 1 - 0x2A0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB2 - F12FB2 - Filter bank 12 filtrate bit filtrate bit register 2 - 0x2A4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB1 - F13FB1 - Filter bank 13 filtrate bit filtrate bit register 1 - 0x2A8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB2 - F13FB2 - Filter bank 13 filtrate bit filtrate bit register 2 - 0x2AC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - - CAN2 - 0x40006800 - - CAN2_TX - CAN2 TX interrupt - 68 - - - CAN2_RX0 - CAN2 RX0 interrupt - 69 - - - CAN2_RX1 - CAN2 RX1 interrupt - 70 - - - CAN2_SE - CAN2 SE interrupt - 71 - - - - DEBUG - Debug support - DEBUG - 0xE0042000 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - DEBUG_IDCODE - 0x0 - 0x20 - read-only - 0x0 - - - PID - PID - 0 - 32 - - - - - CTRL - CTRL - DEBUG_CTRL - 0x4 - 0x20 - read-write - 0x0 - - - SLEEP_DEBUG - SLEEP_DEBUG - 0 - 1 - - - DEEPSLEEP_DEBUG - DEEPSLEEP_DEBUG - 1 - 1 - - - STANDBY_DEBUG - STANDBY_DEBUG - 2 - 1 - - - TRACE_IOEN - TRACE_IOEN - 5 - 1 - - - TRACE_MODE - TRACE_MODE - 6 - 2 - - - WDT_PAUSE - WDT_PAUSE - 8 - 1 - - - WWDT_PAUSE - WWDT_PAUSE - 9 - 1 - - - TMR1_PAUSE - TMR1_PAUSE - 10 - 1 - - - TMR2_PAUSE - TMR2_PAUSE - 11 - 1 - - - TMR3_PAUSE - TMR3_PAUSE - 12 - 1 - - - TMR4_PAUSE - TMR4_PAUSE - 13 - 1 - - - CAN1_PAUSE - CAN1_PAUSE - 14 - 1 - - - I2C1_SMBUS_TIMEOUT - I2C1_SMBUS_TIMEOUT - 15 - 1 - - - I2C2_SMBUS_TIMEOUT - I2C2_SMBUS_TIMEOUT - 16 - 1 - - - TMR8_PAUSE - TMR8_PAUSE - 17 - 1 - - - TMR5_PAUSE - TMR5_PAUSE - 18 - 1 - - - CAN2_PAUSE - CAN2_PAUSE - 21 - 1 - - - TMR9_PAUSE - TMR9_PAUSE - 28 - 1 - - - TMR10_PAUSE - TMR10_PAUSE - 29 - 1 - - - TMR11_PAUSE - TMR11_PAUSE - 30 - 1 - - - - - - - UART4 - Universal asynchronous receiver transmitter - 0x40004C00 - - UART4 - UART4 global interrupt - 52 - - - - UART5 - Universal asynchronous receiver transmitter - 0x40005000 - - UART5 - UART5 global interrupt - 53 - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DT - DT - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DT - Data Register - 0 - 32 - - - - - CDT - CDT - Common data register - 0x4 - 0x20 - read-write - 0x00000000 - - - CDT - Common Data - 0 - 1 - - - - - CTRL - CTRL - Control register - 0x8 - 0x20 - read-write - 0x00000000 - - - RST - Reset bit - 0 - 1 - - - REVID - Reverse input data - 5 - 2 - - - REVOD - Reverse output data - 7 - 1 - - - - - IDT - IDT - Initial data register - 0x10 - 0x20 - read-write - 0xFFFFFFFF - - - IDT - Initial Data - 0 - 32 - - - - - - - FLASH - Flash memory controler - FLASH - 0x40022000 - - 0x0 - 0x400 - registers - - - FLASH - Flash global interrupt - 4 - - - - PSR - PSR - Performance selection register - 0x0 - 0x20 - 0x00000030 - - - - - UNLOCK - UNLOCK - Unlock register - 0x4 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - USD_UNLOCK - USD_UNLOCK - USD unlock register - 0x8 - 0x20 - write-only - 0x00000000 - - - USD_UKVAL - User system data Unlock key value - 0 - 32 - - - - - STS - STS - Status register - 0xC - 0x20 - 0x00000000 - - - ODF - Operate done flag - 5 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - PRGMERR - program error - 2 - 1 - read-write - - - OBF - Operate busy flag - 0 - 1 - read-only - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - USDPRGM - User system data program - 4 - 1 - - - USDERS - User system data erase - 5 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - USDULKS - User system data unlock success - 9 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR - ADDR - Address register - 0x14 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - USD - USD - User system data register - 0x1C - 0x20 - read-only - 0x03FFFFFC - - - USDERR - User system data error - 0 - 1 - - - FAP - FLASH access protection - 1 - 1 - - - nWDT_ATO_EN - WDT auto enable - 2 - 1 - - - nDEPSLP_RST - Deepsleep reset - 3 - 1 - - - nSTDBY_RST - Standby reset - 4 - 1 - - - BTOPT - boot option - 5 - 1 - - - USER_D0 - User data 0 - 10 - 8 - - - USER_D1 - User data 1 - 18 - 8 - - - - - EPPS - EPPS - Erase/program protection status register - 0x20 - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - UNLOCK3 - UNLOCK3 - Unlock 3 register - 0x84 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - SELECT - SELECT - Select register - 0x88 - 0x20 - write-only - 0x00000000 - - - SELECT - spim type selection - 0 - 32 - - - - - STS3 - STS3 - Status 3 register - 0x8C - 0x20 - 0x00000000 - - - OBF - Operate busy flag - 0 - 1 - read-only - - - PRGMERR - program error - 2 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - ODF - Operate done flag - 5 - 1 - read-write - - - - - CTRL3 - CTRL3 - Control 3 register - 0x90 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - CHPERS - Chip erase - 2 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR3 - ADDR3 - Address 3 register - 0x94 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - DA - DA - Spim decryption address - 0x98 - 0x20 - write-only - 0x00000000 - - - FDA - Flash decryption address - 0 - 32 - - - - - SLIB_STS0 - SLIB_STS0 - sLib status 0 register - 0xCC - 0x20 - 0x00000000 - - - SLIB_ENF - sLib enabled flag - 3 - 1 - read-only - - - - - SLIB_STS1 - SLIB_STS1 - sLib status 1 register - 0xD0 - 0x20 - 0x00000000 - - - SLIB_SS - sLib start sector - 0 - 11 - read-only - - - SLIB_DAT_SS - sLib data start sector - 11 - 11 - read-only - - - SLIB_ES - sLib end sector - 22 - 10 - read-only - - - - - SLIB_PWD_CLR - SLIB_PWD_CLR - SLIB password clear register - 0xD4 - 0x20 - 0x00000000 - write-only - - - SLIB_PCLR_VAL - sLib password clear value - 0 - 32 - - - - - SLIB_MISC_STS - SLIB_MISC_STS - sLib misc status register - 0xD8 - 0x20 - 0x01000000 - - - SLIB_PWD_ERR - sLib password error - 0 - 1 - read-only - - - SLIB_PWD_OK - sLib password ok - 1 - 1 - read-only - - - SLIB_ULKF - sLib unlock flag - 2 - 1 - read-only - - - SLIB_RCNT - sLib remaining count - 16 - 9 - read-only - - - - - SLIB_SET_PWD - SLIB_SET_PWD - sLib password setting register - 0xDC - 0x20 - 0x00000000 - write-only - - - SLIB_PSET_VAL - sLib password setting val - 0 - 32 - - - - - SLIB_SET_RANGE - SLIB_SET_RANGE - Configure sLib range register - 0xE0 - 0x20 - 0x00000000 - write-only - - - SLIB_SS_SET - sLib start sector setting - 0 - 11 - - - SLIB_DSS_SET - sLib data start sector setting - 11 - 11 - - - SLIB_ES_SET - sLib end sector setting - 22 - 10 - - - - - SLIB_UNLOCK - SLIB_UNLOCK - sLib unlock register - 0xF0 - 0x20 - 0x00000000 - write-only - - - SLIB_UKVAL - sLib unlock key value - 0 - 32 - - - - - CRC_CTRL - CRC_CTRL - Flash CRC controler register - 0xF4 - 0x20 - 0x00000000 - write-only - - - CRC_SS - CRC start sector - 0 - 7 - - - CRC_SN - CRC sector numbler - 7 - 7 - - - CRC_STRT - CRC start - 14 - 1 - - - - - CRC_CHKR - CRC_CHKR - FLASH CRC check result register - 0xF8 - 0x20 - 0x00000000 - read-only - - - CRC_CHKR - CRC check result - 0 - 32 - - - - - - - NVIC - Nested Vectored Interrupt - Controller - NVIC - 0xE000E000 - - 0x0 - 0x1001 - registers - - - - ICTR - ICTR - Interrupt Controller Type - Register - 0x4 - 0x20 - read-only - 0x00000000 - - - INTLINESNUM - Total number of interrupt lines in - groups - 0 - 4 - - - - - STIR - STIR - Software Triggered Interrupt - Register - 0xF00 - 0x20 - write-only - 0x00000000 - - - INTID - interrupt to be triggered - 0 - 9 - - - - - ISER0 - ISER0 - Interrupt Set-Enable Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER1 - ISER1 - Interrupt Set-Enable Register - 0x104 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ICER0 - ICER0 - Interrupt Clear-Enable - Register - 0x180 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear-Enable - Register - 0x184 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x200 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x204 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending - Register - 0x280 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending - Register - 0x284 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - IABR0 - IABR0 - Interrupt Active Bit Register - 0x300 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IABR1 - IABR1 - Interrupt Active Bit Register - 0x304 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IPR0 - IPR0 - Interrupt Priority Register - 0x400 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR1 - IPR1 - Interrupt Priority Register - 0x404 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR2 - IPR2 - Interrupt Priority Register - 0x408 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR3 - IPR3 - Interrupt Priority Register - 0x40C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR4 - IPR4 - Interrupt Priority Register - 0x410 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR5 - IPR5 - Interrupt Priority Register - 0x414 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR6 - IPR6 - Interrupt Priority Register - 0x418 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR7 - IPR7 - Interrupt Priority Register - 0x41C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR8 - IPR8 - Interrupt Priority Register - 0x420 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR9 - IPR9 - Interrupt Priority Register - 0x424 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR10 - IPR10 - Interrupt Priority Register - 0x428 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR11 - IPR11 - Interrupt Priority Register - 0x42C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR12 - IPR12 - Interrupt Priority Register - 0x430 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR13 - IPR13 - Interrupt Priority Register - 0x434 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR14 - IPR14 - Interrupt Priority Register - 0x438 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - - - USBFS - Universal serial bus full-speed device - interface - USBFS - 0x40005C00 - - 0x0 - 0x400 - registers - - - - EPT0 - EPT0 - endpoint 0 register - 0x0 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT1 - EPT1 - endpoint 1 register - 0x4 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT2 - EPT2 - endpoint 2 register - 0x8 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT3 - EPT3 - endpoint 3 register - 0xC - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT4 - EPT4 - endpoint 4 register - 0x10 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT5 - EPT5 - endpoint 5 register - 0x14 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT6 - EPT6 - endpoint 6 register - 0x18 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT7 - EPT7 - endpoint 7 register - 0x1C - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - CTRL - CTRL - control register - 0x40 - 0x20 - read-write - 0x00000003 - - - CSRST - Core soft reset - 0 - 1 - - - DISUSB - Disable usb phy - 1 - 1 - - - LPM - Low power mode - 2 - 1 - - - SSP - Soft suspend config - 3 - 1 - - - GRESUME - Generate resume request - 4 - 1 - - - LSOFIEN - Lost start of frame interrupt enable - 8 - 1 - - - SOFIEN - Start of frame interrupt - enable - 9 - 1 - - - RSTIEN - Bus reset interrupt enable - 10 - 1 - - - SPIEN - Bus suspend mode interrupt - enable - 11 - 1 - - - WKIEN - Wakeup/Remote wakeup interrupt enable - 12 - 1 - - - BEIEN - Bus error interrupt enable - 13 - 1 - - - UCFORIEN - USB Core fifo overrun - interrupt enable - 14 - 1 - - - TCIEN - transmission completed interrupt - enable - 15 - 1 - - - - - INTSTS - INTSTS - interrupt status register - 0x44 - 0x20 - read-write - 0x00000000 - - - EPT_NUM - Endpoint number - 0 - 4 - - - INOUT - In/Out transaction - 4 - 1 - - - LSOF - Lost start of frame - 8 - 1 - - - SOF - start of frame - 9 - 1 - - - RST - Bus reset - 10 - 1 - - - SP - Bus suspend - 11 - 1 - - - WK - Wakeup - 12 - 1 - - - BE - Bus error - 13 - 1 - - - UCFOR - USB core fifo overrun memory - 14 - 1 - - - TC - transaction completed - 15 - 1 - - - - - SOFRNUM - SOFRNUM - frame number register - 0x48 - 0x20 - read-write - 0x0000 - - - SOFNUM - Start of frame number - 0 - 11 - - - LSOFNUM - Lost start of frame number - 11 - 2 - - - CLCK - Connect locked - 13 - 1 - - - DMSTS - DM status - 14 - 1 - - - DPSTS - DP status - 15 - 1 - - - - - DEVADDR - DEVADDR - device address - 0x4C - 0x20 - read-write - 0x0000 - - - ADDR - Host assign device address - 0 - 7 - - - CEN - USB core enable - 7 - 1 - - - - - BUFTBL - BUFTBL - Buffer table address - 0x50 - 0x20 - read-write - 0x0000 - - - BTADDR - Endpoint buffer table start address - 3 - 13 - - - - - CFG - CFG - CFG control register - 0x60 - 0x20 - read-write - 0x0000 - - - SOFOUTEN - SOF output enable - 0 - 1 - - - - - - - diff --git a/hw/bsp/at32f413/boards/AT_START_F413/board.h b/hw/bsp/at32f413/boards/AT_START_F413/board.h index f0bf0e4ae..13ec7a207 100644 --- a/hw/bsp/at32f413/boards/AT_START_F413/board.h +++ b/hw/bsp/at32f413/boards/AT_START_F413/board.h @@ -52,7 +52,7 @@ static inline void board_vbus_sense_init(void) { - + } #ifdef __cplusplus diff --git a/hw/bsp/at32f413/family.c b/hw/bsp/at32f413/family.c index a38fe450e..ffaf892e7 100644 --- a/hw/bsp/at32f413/family.c +++ b/hw/bsp/at32f413/family.c @@ -50,7 +50,7 @@ void USBFSWakeUp_IRQHandler(void) { tud_int_handler(0); } -void board_init(void) +void board_init(void) { system_clock_config(); @@ -62,7 +62,7 @@ void board_init(void) /* configure systick */ systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); - + /* enable usb clock */ crm_periph_clock_enable(CRM_USB_PERIPH_CLOCK, TRUE); @@ -228,7 +228,7 @@ int board_uart_write(void const *buf, int len) #if CFG_TUSB_OS == OPT_OS_NONE int txsize = len; u16 timeout = 0xffff; - while (txsize--) + while (txsize--) { while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) { @@ -252,16 +252,16 @@ int board_uart_write(void const *buf, int len) #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; - void SysTick_Handler(void) + void SysTick_Handler(void) { system_ticks++; } - uint32_t board_millis(void) + uint32_t board_millis(void) { return system_ticks; } - + void SVC_Handler(void) { } diff --git a/hw/bsp/at32f413/family.mk b/hw/bsp/at32f413/family.mk index c56d1064c..a88c248dd 100644 --- a/hw/bsp/at32f413/family.mk +++ b/hw/bsp/at32f413/family.mk @@ -1,6 +1,5 @@ # Submodules AT32F413_SDK = hw/mcu/artery/at32f413 -DEPS_SUBMODULES += $(AT32F413_SDK) # AT32 SDK path AT32F413_SDK_SRC = $(AT32F413_SDK)/libraries diff --git a/hw/bsp/at32f413/startup_at32f413.s b/hw/bsp/at32f413/startup_at32f413.s index 4fc1f2a86..42631da93 100644 --- a/hw/bsp/at32f413/startup_at32f413.s +++ b/hw/bsp/at32f413/startup_at32f413.s @@ -78,7 +78,7 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array diff --git a/hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h index 73889ebf9..c7932efc0 100644 --- a/hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h @@ -109,7 +109,7 @@ #define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 #define INCLUDE_uxTaskGetStackHighWaterMark 0 #define INCLUDE_xTaskGetIdleTaskHandle 0 #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 diff --git a/hw/bsp/at32f415/at32f415_clock.c b/hw/bsp/at32f415/at32f415_clock.c index d78f1bb8a..3d137fcd2 100644 --- a/hw/bsp/at32f415/at32f415_clock.c +++ b/hw/bsp/at32f415/at32f415_clock.c @@ -5,11 +5,11 @@ ************************************************************************** * Copyright notice & Disclaimer * - * The software Board Support Package (BSP) that is made available to - * download from Artery official website is the copyrighted work of Artery. - * Artery authorizes customers to use, copy, and distribute the BSP - * software and its related documentation for the purpose of design and - * development in conjunction with Artery microcontrollers. Use of the + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the * software is governed by this copyright notice and the following disclaimer. * * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, @@ -46,8 +46,8 @@ void system_clock_config(void) { /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - + flash_psr_set(FLASH_WAIT_CYCLE_4); + /* reset crm */ crm_reset(); diff --git a/hw/bsp/at32f415/at32f415_clock.h b/hw/bsp/at32f415/at32f415_clock.h index a4a2ec1cf..71f204f8b 100644 --- a/hw/bsp/at32f415/at32f415_clock.h +++ b/hw/bsp/at32f415/at32f415_clock.h @@ -5,11 +5,11 @@ ************************************************************************** * Copyright notice & Disclaimer * - * The software Board Support Package (BSP) that is made available to - * download from Artery official website is the copyrighted work of Artery. - * Artery authorizes customers to use, copy, and distribute the BSP - * software and its related documentation for the purpose of design and - * development in conjunction with Artery microcontrollers. Use of the + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the * software is governed by this copyright notice and the following disclaimer. * * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, @@ -41,4 +41,3 @@ void system_clock_config(void); #endif #endif /* __AT32F415_CLOCK_H */ - diff --git a/hw/bsp/at32f415/at32f415_conf.h b/hw/bsp/at32f415/at32f415_conf.h index ddee93c75..284eee7d2 100644 --- a/hw/bsp/at32f415/at32f415_conf.h +++ b/hw/bsp/at32f415/at32f415_conf.h @@ -5,11 +5,11 @@ ************************************************************************** * Copyright notice & Disclaimer * - * The software Board Support Package (BSP) that is made available to - * download from Artery official website is the copyrighted work of Artery. - * Artery authorizes customers to use, copy, and distribute the BSP - * software and its related documentation for the purpose of design and - * development in conjunction with Artery microcontrollers. Use of the + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the * software is governed by this copyright notice and the following disclaimer. * * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, @@ -141,5 +141,3 @@ extern "C" { #endif #endif /* __AT32F415_CONF_H */ - - diff --git a/hw/bsp/at32f415/at32f415_int.c b/hw/bsp/at32f415/at32f415_int.c index 40d2d44fb..c52adaf9a 100644 --- a/hw/bsp/at32f415/at32f415_int.c +++ b/hw/bsp/at32f415/at32f415_int.c @@ -5,11 +5,11 @@ ************************************************************************** * Copyright notice & Disclaimer * - * The software Board Support Package (BSP) that is made available to - * download from Artery official website is the copyrighted work of Artery. - * Artery authorizes customers to use, copy, and distribute the BSP - * software and its related documentation for the purpose of design and - * development in conjunction with Artery microcontrollers. Use of the + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the * software is governed by this copyright notice and the following disclaimer. * * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, @@ -28,11 +28,11 @@ /** @addtogroup AT32F415_periph_examples * @{ */ - + /** @addtogroup 415_CRC_calculation * @{ */ - + /** * @brief this function handles nmi exception. * @param none @@ -52,9 +52,9 @@ void MemManage_Handler(void) /* go to infinite loop when memory manage exception occurs */ while(1) - { + { } - + } /** @@ -112,8 +112,8 @@ void DebugMon_Handler(void) /** * @} - */ + */ /** * @} - */ + */ diff --git a/hw/bsp/at32f415/at32f415_int.h b/hw/bsp/at32f415/at32f415_int.h index 21119e52d..2106538b6 100644 --- a/hw/bsp/at32f415/at32f415_int.h +++ b/hw/bsp/at32f415/at32f415_int.h @@ -5,11 +5,11 @@ ************************************************************************** * Copyright notice & Disclaimer * - * The software Board Support Package (BSP) that is made available to - * download from Artery official website is the copyrighted work of Artery. - * Artery authorizes customers to use, copy, and distribute the BSP - * software and its related documentation for the purpose of design and - * development in conjunction with Artery microcontrollers. Use of the + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the * software is governed by this copyright notice and the following disclaimer. * * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, @@ -53,4 +53,3 @@ void SysTick_Handler(void); #endif #endif - diff --git a/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xC_FLASH.ld b/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xC_FLASH.ld index baf2e7d71..6da817705 100644 --- a/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xC_FLASH.ld +++ b/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xC_FLASH.ld @@ -104,7 +104,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -119,7 +119,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd b/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd deleted file mode 100644 index cd22346c7..000000000 --- a/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd +++ /dev/null @@ -1,27108 +0,0 @@ - - - - - - - - Keil - ArteryTek - AT32F415xx_v2 - AT32F415 - 1.0 - ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 150MHz, etc. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - CM4 - r0p1 - little - false - true - 4 - false - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - - PWC - Power control - PWC - 0x40007000 - - 0x0 - 0x400 - registers - - - - CTRL - CTRL - Power control register - (PWC_CTRL) - 0x0 - 0x20 - read-write - 0x00000000 - - - VRSEL - Voltage regulator state select when deepsleep mode - 0 - 1 - - - LPSEL - Low power mode select when Cortex-M4F sleepdeep - 1 - 1 - - - CLSWEF - Clear SWEF flag - 2 - 1 - - - CLSEF - Clear SEF flag - 3 - 1 - - - PVMEN - Power voltage monitoring enable - 4 - 1 - - - PVMSEL - Power voltage monitoring boundary select - 5 - 3 - - - BPWEN - Battery powered domain write enable - 8 - 1 - - - - - CTRLSTS - CTRLSTS - Power control register - (PWC_CTRLST) - 0x4 - 0x20 - 0x00000000 - - - SWEF - Standby wake-up event flag - 0 - 1 - read-only - - - SEF - Standby mode entry flag - 1 - 1 - read-only - - - PVMOF - Power voltage monitoring output flag - 2 - 1 - read-only - - - SWPEN - Standby wake-up pin enable - 8 - 1 - read-write - - - - - - - CRM - Clock and reset management - CRM - 0x40021000 - - 0x0 - 0x400 - registers - - - CRM - CRM global interrupt - 5 - - - - CTRL - CTRL - Clock control register - 0x0 - 0x20 - 0x00000083 - - - HICKEN - High speed internal clock enable - 0 - 1 - read-write - - - HICKSTBL - High speed internal clock ready flag - 1 - 1 - read-only - - - HICKTRIM - High speed internal clock trimming - 2 - 6 - read-write - - - HICKCAL - High speed internal clock calibration - 8 - 8 - read-only - - - HEXTEN - High speed exernal crystal enable - 16 - 1 - read-write - - - HEXTSTBL - High speed exernal crystal ready flag - 17 - 1 - read-only - - - HEXTBYPS - High speed exernal crystal bypass - 18 - 1 - read-write - - - CFDEN - Clock failure detection enable - 19 - 1 - read-write - - - PLLEN - PLL enable - 24 - 1 - read-write - - - PLLSTBL - PLL clock ready flag - 25 - 1 - read-only - - - - - CFG - CFG - Clock configuration register - (CRM_CFG) - 0x4 - 0x20 - 0x00000000 - - - SCLKSEL - System clock select - 0 - 2 - read-write - - - SCLKSTS - System Clock select Status - 2 - 2 - read-only - - - AHBDIV - AHB division - 4 - 4 - read-write - - - APB1DIV - APB1 division - 8 - 3 - read-write - - - APB2DIV - APB2 division - 11 - 3 - read-write - - - ADCDIV1_0 - ADC division bit1 and bit0 - 14 - 2 - read-write - - - PLLRCS - PLL reference clock select - 16 - 1 - read-write - - - PLLHEXTDIV - HEXT division selection for PLL entry clock - 17 - 1 - read-write - - - PLLMULT3_0 - PLL Multiplication Factor bit3 to bit0 - 18 - 4 - read-write - - - USBDIV1_0 - USB division bit1 and bit0 - 22 - 2 - read-write - - - CLKOUT_SEL - Clock output selection bit2 to bit0 - 24 - 3 - read-write - - - USBDIV2 - USB division bit2 - 27 - 1 - read-write - - - ADCDIV2 - ADC division bit2 - 28 - 1 - read-write - - - PLLMULT5_4 - PLL Multiplication Factor bit5 and bit4 - 29 - 2 - read-write - - - - - CLKINT - CLKINT - Clock interrupt register - (CRM_CLKINT) - 0x8 - 0x20 - 0x00000000 - - - LICKSTBLF - LICK ready interrupt flag - 0 - 1 - read-only - - - LEXTSTBLF - LEXT ready interrupt flag - 1 - 1 - read-only - - - HICKSTBLF - HICK ready interrupt flag - 2 - 1 - read-only - - - HEXTSTBLF - HEXT ready interrupt flag - 3 - 1 - read-only - - - PLLSTBLF - PLL ready interrupt flag - 4 - 1 - read-only - - - CFDF - Clock failure detection interrupt flag - 7 - 1 - read-only - - - LICKSTBLIEN - LICK ready interrupt enable - 8 - 1 - read-write - - - LEXTSTBLIEN - LEXT ready interrupt enable - 9 - 1 - read-write - - - HICKSTBLIEN - HICK ready interrupt enable - 10 - 1 - read-write - - - HEXTSTBLIEN - HEXT ready interrupt enable - 11 - 1 - read-write - - - PLLSTBLIEN - PLL ready interrupt enable - 12 - 1 - read-write - - - LICKSTBLFC - LICK ready interrupt clear - 16 - 1 - write-only - - - LEXTSTBLFC - LEXT ready interrupt clear - 17 - 1 - write-only - - - HICKSTBLFC - HICK ready interrupt clear - 18 - 1 - write-only - - - HEXTSTBLFC - HEXT ready interrupt clear - 19 - 1 - write-only - - - PLLSTBLFC - PLL ready interrupt clear - 20 - 1 - write-only - - - CFDFC - Clock failure detection interrupt clear - 23 - 1 - write-only - - - - - APB2RST - APB2RST - APB2 peripheral reset register - (CRM_APB2RST) - 0xC - 0x20 - read-write - 0x000000000 - - - IOMUXRST - MUX function I/O - reset - 0 - 1 - - - EXINTRST - External interrupt reset - 1 - 1 - - - GPIOARST - IO port A reset - 2 - 1 - - - GPIOBRST - IO port B reset - 3 - 1 - - - GPIOCRST - IO port C reset - 4 - 1 - - - GPIODRST - IO port D reset - 5 - 1 - - - GPIOFRST - IO port F reset - 7 - 1 - - - ADC1RST - ADC1 reset - 9 - 1 - - - TMR1RST - Timer1 reset - 11 - 1 - - - SPI1RST - SPI1 reset - 12 - 1 - - - USART1RST - USART1 reset - 14 - 1 - - - TMR9RST - Timer9 reset - 19 - 1 - - - TMR10RST - Timer10 reset - 20 - 1 - - - TMR11RST - Timer11 reset - 21 - 1 - - - ACCRST - ACC reset - 22 - 1 - - - - - APB1RST - APB1RST - APB1 peripheral reset register - (CRM_APB1RST) - 0x10 - 0x20 - read-write - 0x00000000 - - - TMR2RST - Timer 2 reset - 0 - 1 - - - TMR3RST - Timer 3 reset - 1 - 1 - - - TMR4RST - Timer 4 reset - 2 - 1 - - - TMR5RST - Timer 5 reset - 3 - 1 - - - CMPRST - Comparator reset - 9 - 1 - - - WWDTRST - Window watchdog timer reset - 11 - 1 - - - SPI2RST - SPI2 reset - 14 - 1 - - - USART2RST - USART 2 reset - 17 - 1 - - - USART3RST - USART 3 reset - 18 - 1 - - - UART4RST - UART 4 reset - 19 - 1 - - - UART5RST - UART 5 reset - 20 - 1 - - - I2C1RST - I2C1 reset - 21 - 1 - - - I2C2RST - I2C2 reset - 22 - 1 - - - CAN1RST - CAN1 reset - 25 - 1 - - - PWCRST - Power controller reset - 28 - 1 - - - - - AHBEN - AHBEN - AHB Peripheral Clock enable register - (CRM_AHBEN) - 0x14 - 0x20 - read-write - 0x00000014 - - - DMA1EN - DMA1 clock enable - 0 - 1 - - - DMA2EN - DMA2 clock enable - 1 - 1 - - - SRAMEN - SRAM interface clock - enable - 2 - 1 - - - FLASHEN - FLASH clock enable - 4 - 1 - - - CRCEN - CRC clock enable - 6 - 1 - - - SDIO1EN - SDIO1 clock enable - 10 - 1 - - - OTGFS1EN - OTGFS1 clock enable - 12 - 1 - - - - - APB2EN - APB2EN - APB2 peripheral clock enable register - (CRM_APB2EN) - 0x18 - 0x20 - read-write - 0x00000000 - - - IOMUXEN - MUX function I/O clock - enable - 0 - 1 - - - GPIOAEN - I/O port A clock enable - 2 - 1 - - - GPIOBEN - I/O port B clock enable - 3 - 1 - - - GPIOCEN - I/O port C clock enable - 4 - 1 - - - GPIODEN - I/O port D clock enable - 5 - 1 - - - GPIOFEN - I/O port F clock enable - 7 - 1 - - - ADC1EN - ADC1 clock - enable - 9 - 1 - - - TMR1EN - Timer1 clock enable - 11 - 1 - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - USART1EN - USART1 clock enable - 14 - 1 - - - TMR9EN - Timer9 clock enable - 19 - 1 - - - TMR10EN - Timer10 clock enable - 20 - 1 - - - TMR11EN - Timer11 clock enable - 21 - 1 - - - ACCEN - ACC clock enable - 22 - 1 - - - - - APB1EN - APB1EN - APB1 peripheral clock enable register - (CRM_APB1EN) - 0x1C - 0x20 - read-write - 0x00000000 - - - TMR2EN - Timer2 clock enable - 0 - 1 - - - TMR3EN - Timer3 clock enable - 1 - 1 - - - TMR4EN - Timer4 clock enable - 2 - 1 - - - TMR5EN - Timer5 clock enable - 3 - 1 - - - CMPEN - Comparator clock enable - 9 - 1 - - - WWDTEN - Window watchdog timer clock - enable - 11 - 1 - - - SPI2EN - SPI2 clock enable - 14 - 1 - - - USART2EN - USART2 clock enable - 17 - 1 - - - USART3EN - USART3 clock enable - 18 - 1 - - - UART4EN - UART4 clock enable - 19 - 1 - - - UART5EN - UART5 clock enable - 20 - 1 - - - I2C1EN - I2C1 clock enable - 21 - 1 - - - I2C2EN - I2C2 clock enable - 22 - 1 - - - CAN1EN - CAN1 clock enable - 25 - 1 - - - PWCEN - Power clock enable - 28 - 1 - - - - - BPDC - BPDC - Battery powered domain control register - (CRM_BPDC) - 0x20 - 0x20 - 0x00000000 - - - LEXTEN - Low speed external crystal enable - 0 - 1 - read-write - - - LEXTSTBL - Low speed external crystal ready - 1 - 1 - read-only - - - LEXTBYPS - Low speed external crystal bypass - 2 - 1 - read-write - - - ERTCSEL - ERTC clock selection - 8 - 2 - read-write - - - ERTCEN - ERTC clock enable - 15 - 1 - read-write - - - BPDRST - Battery powered domain software reset - 16 - 1 - read-write - - - - - CTRLSTS - CTRLSTS - Control/status register - (CRM_CTRLSTS) - 0x24 - 0x20 - 0x0C000000 - - - LICKEN - Low speed internal clock enable - 0 - 1 - read-write - - - LICKSTBL - Low speed internal clock ready - 1 - 1 - read-only - - - RSTFC - Reset flag clear - 24 - 1 - read-write - - - NRSTF - PIN reset flag - 26 - 1 - read-write - - - PORRSTF - POR/LVR reset flag - 27 - 1 - read-write - - - SWRSTF - Software reset flag - 28 - 1 - read-write - - - WDTRSTF - Watchdog timer reset flag - 29 - 1 - read-write - - - WWDTRSTF - Window watchdog timer reset flag - 30 - 1 - read-write - - - LPRSTF - Low-power reset flag - 31 - 1 - read-write - - - - - AHBRST - AHBRST - AHB reset register - - 0x28 - 0x20 - 0x00000000 - - - OTGFS1RST - OTGFS1 reset - 12 - 1 - read-write - - - - - PLL - PLL - PLL configuration register - (RCC_PLL) - 0x2C - 0x20 - 0x00001F10 - - - PLL_FR - PLL_FR - 0 - 3 - read-write - - - PLL_MS - PLL_MS - 4 - 4 - read-write - - - PLL_NS - PLL_NS - 8 - 9 - read-write - - - PLL_FREF - PLL entry clock reference frequency - 24 - 3 - read-write - - - PLLCFGEN - PLL config enable - 31 - 1 - read-write - - - - - MISC1 - MISC1 - Miscellaneous register1 - 0x30 - 0x20 - 0x00000000 - - - HICKCAL_KEY - HICKCAL write key value - 0 - 8 - read-write - - - CLKOUT_SEL3 - Clock output bit3 - 16 - 1 - read-write - - - HICKDIV - HICK 6 divider selection - 25 - 1 - read-write - - - CLKOUTDIV - Clock output division - 28 - 4 - read-write - - - - - OTG_EXTCTRL - OTG_EXTCTRL - OTGFS external ctrl register1 - 0x44 - 0x20 - 0x00000000 - - - USBDIV_RST - USB divider reset - 30 - 1 - read-write - - - EP3_RMPEN - OTGFS end-point 3 remap enable - 31 - 1 - read-write - - - - - MISC2 - MISC2 - Miscellaneous register2 - 0x54 - 0x20 - 0x0000000D - - - AUTO_STEP_EN - AUTO_STEP_EN - 4 - 2 - read-write - - - HICK_TO_USB - HICK to usb clock - 8 - 1 - read-write - - - HICK_TO_SCLK - HICK to system clock - 9 - 1 - read-write - - - - - - - GPIOA - General purpose IO - GPIO - 0x40010800 - - 0x0 - 0x400 - registers - - - - CFGLR - CFGLR - GPIO function configurate low register - 0x0 - 0x20 - read-write - 0x44444444 - - - IOMC0 - Port n.0 mode configurate bits - 0 - 2 - - - IOFC0 - Port n.0 function configurate - bits - 2 - 2 - - - IOMC1 - Port n.1 mode configurate bits - 4 - 2 - - - IOFC1 - Port n.1 function configurate - bits - 6 - 2 - - - IOMC2 - Port n.2 mode configurate bits - 8 - 2 - - - IOFC2 - Port n.2 function configurate - bits - 10 - 2 - - - IOMC3 - Port n.3 mode configurate bits - 12 - 2 - - - IOFC3 - Port n.3 function configurate - bits - 14 - 2 - - - IOMC4 - Port n.4 mode configurate bits - 16 - 2 - - - IOFC4 - Port n.4 function configurate - bits - 18 - 2 - - - IOMC5 - Port n.5 mode configurate bits - 20 - 2 - - - IOFC5 - Port n.5 function configurate - bits - 22 - 2 - - - IOMC6 - Port n.6 mode configurate bits - 24 - 2 - - - IOFC6 - Port n.6 function configurate - bits - 26 - 2 - - - IOMC7 - Port n.7 mode configurate bits - 28 - 2 - - - IOFC7 - Port n.7 function configurate - bits - 30 - 2 - - - - - CFGHR - CFGHR - GPIO function configurate high register - 0x4 - 0x20 - read-write - 0x44444444 - - - IOMC8 - Port n.8 mode configurate bits - 0 - 2 - - - IOFC8 - Port n.8 function configurate - bits - 2 - 2 - - - IOMC9 - Port n.9 mode configurate bits - 4 - 2 - - - IOFC9 - Port n.9 function configurate - bits - 6 - 2 - - - IOMC10 - Port n.10 mode configurate bits - 8 - 2 - - - IOFC10 - Port n.10 function configurate - bits - 10 - 2 - - - IOMC11 - Port n.11 mode configurate bits - 12 - 2 - - - IOFC11 - Port n.11 function configurate - bits - 14 - 2 - - - IOMC12 - Port n.12 mode configurate bits - 16 - 2 - - - IOFC12 - Port n.12 function configurate - bits - 18 - 2 - - - IOMC13 - Port n.13 mode configurate bits - 20 - 2 - - - IOFC13 - Port n.13 function configurate - bits - 22 - 2 - - - IOMC14 - Port n.14 mode configurate bits - 24 - 2 - - - IOFC14 - Port n.14 function configurate - bits - 26 - 2 - - - IOMC15 - Port n.15 mode configurate bits - 28 - 2 - - - IOFC15 - Port n.15 function configurate - bits - 30 - 2 - - - - - IDT - IDT - Port input data register - 0x8 - 0x20 - read-only - 0x00000000 - - - IDT0 - Port input data - 0 - 1 - - - IDT1 - Port input data - 1 - 1 - - - IDT2 - Port input data - 2 - 1 - - - IDT3 - Port input data - 3 - 1 - - - IDT4 - Port input data - 4 - 1 - - - IDT5 - Port input data - 5 - 1 - - - IDT6 - Port input data - 6 - 1 - - - IDT7 - Port input data - 7 - 1 - - - IDT8 - Port input data - 8 - 1 - - - IDT9 - Port input data - 9 - 1 - - - IDT10 - Port input data - 10 - 1 - - - IDT11 - Port input data - 11 - 1 - - - IDT12 - Port input data - 12 - 1 - - - IDT13 - Port input data - 13 - 1 - - - IDT14 - Port input data - 14 - 1 - - - IDT15 - Port input data - 15 - 1 - - - - - ODT - ODT - Port output data register - 0xC - 0x20 - read-write - 0x00000000 - - - ODT0 - Port output data - 0 - 1 - - - ODT1 - Port output data - 1 - 1 - - - ODT2 - Port output data - 2 - 1 - - - ODT3 - Port output data - 3 - 1 - - - ODT4 - Port output data - 4 - 1 - - - ODT5 - Port output data - 5 - 1 - - - ODT6 - Port output data - 6 - 1 - - - ODT7 - Port output data - 7 - 1 - - - ODT8 - Port output data - 8 - 1 - - - ODT9 - Port output data - 9 - 1 - - - ODT10 - Port output data - 10 - 1 - - - ODT11 - Port output data - 11 - 1 - - - ODT12 - Port output data - 12 - 1 - - - ODT13 - Port output data - 13 - 1 - - - ODT14 - Port output data - 14 - 1 - - - ODT15 - Port output data - 15 - 1 - - - - - SCR - SCR - Port bit set/clear register - 0x10 - 0x20 - read-write - 0x00000000 - - - IOSB0 - Set bit 0 - 0 - 1 - - - IOSB1 - Set bit 1 - 1 - 1 - - - IOSB2 - Set bit 1 - 2 - 1 - - - IOSB3 - Set bit 3 - 3 - 1 - - - IOSB4 - Set bit 4 - 4 - 1 - - - IOSB5 - Set bit 5 - 5 - 1 - - - IOSB6 - Set bit 6 - 6 - 1 - - - IOSB7 - Set bit 7 - 7 - 1 - - - IOSB8 - Set bit 8 - 8 - 1 - - - IOSB9 - Set bit 9 - 9 - 1 - - - IOSB10 - Set bit 10 - 10 - 1 - - - IOSB11 - Set bit 11 - 11 - 1 - - - IOSB12 - Set bit 12 - 12 - 1 - - - IOSB13 - Set bit 13 - 13 - 1 - - - IOSB14 - Set bit 14 - 14 - 1 - - - IOSB15 - Set bit 15 - 15 - 1 - - - IOCB0 - Clear bit 0 - 16 - 1 - - - IOCB1 - Clear bit 1 - 17 - 1 - - - IOCB2 - Clear bit 2 - 18 - 1 - - - IOCB3 - Clear bit 3 - 19 - 1 - - - IOCB4 - Clear bit 4 - 20 - 1 - - - IOCB5 - Clear bit 5 - 21 - 1 - - - IOCB6 - Clear bit 6 - 22 - 1 - - - IOCB7 - Clear bit 7 - 23 - 1 - - - IOCB8 - Clear bit 8 - 24 - 1 - - - IOCB9 - Clear bit 9 - 25 - 1 - - - IOCB10 - Clear bit 10 - 26 - 1 - - - IOCB11 - Clear bit 11 - 27 - 1 - - - IOCB12 - Clear bit 12 - 28 - 1 - - - IOCB13 - Clear bit 13 - 29 - 1 - - - IOCB14 - Clear bit 14 - 30 - 1 - - - IOCB15 - Clear bit 15 - 31 - 1 - - - - - CLR - CLR - Port bit reset register - 0x14 - 0x20 - read-write - 0x00000000 - - - IOCB0 - Clear bit 0 - 0 - 1 - - - IOCB1 - Clear bit 1 - 1 - 1 - - - IOCB2 - Clear bit 1 - 2 - 1 - - - IOCB3 - Clear bit 3 - 3 - 1 - - - IOCB4 - Clear bit 4 - 4 - 1 - - - IOCB5 - Clear bit 5 - 5 - 1 - - - IOCB6 - Clear bit 6 - 6 - 1 - - - IOCB7 - Clear bit 7 - 7 - 1 - - - IOCB8 - Clear bit 8 - 8 - 1 - - - IOCB9 - Clear bit 9 - 9 - 1 - - - IOCB10 - Clear bit 10 - 10 - 1 - - - IOCB11 - Clear bit 11 - 11 - 1 - - - IOCB12 - Clear bit 12 - 12 - 1 - - - IOCB13 - Clear bit 13 - 13 - 1 - - - IOCB14 - Clear bit 14 - 14 - 1 - - - IOCB15 - Clear bit 15 - 15 - 1 - - - - - WPR - WPR - Port write protect - register - 0x18 - 0x20 - read-write - 0x00000000 - - - WPEN0 - Write protect enable 0 - 0 - 1 - - - WPEN1 - Write protect enable 1 - 1 - 1 - - - WPEN2 - Write protect enable 2 - 2 - 1 - - - WPEN3 - Write protect enable 3 - 3 - 1 - - - WPEN4 - Write protect enable 4 - 4 - 1 - - - WPEN5 - Write protect enable 5 - 5 - 1 - - - WPEN6 - Write protect enable 6 - 6 - 1 - - - WPEN7 - Write protect enable 7 - 7 - 1 - - - WPEN8 - Write protect enable 8 - 8 - 1 - - - WPEN9 - Write protect enable 9 - 9 - 1 - - - WPEN10 - Write protect enable 10 - 10 - 1 - - - WPEN11 - Write protect enable 11 - 11 - 1 - - - WPEN12 - Write protect enable 12 - 12 - 1 - - - WPEN13 - Write protect enable 13 - 13 - 1 - - - WPEN14 - Write protect enable 14 - 14 - 1 - - - WPEN15 - Write protect enable 15 - 15 - 1 - - - WPSEQ - Write protect sequence - 16 - 1 - - - - - - - GPIOB - 0x40010C00 - - - GPIOC - 0x40011000 - - - GPIOD - 0x40011400 - - - GPIOF - 0x40011C00 - - - IOMUX - IO MUX function - IOMUX - 0x40010000 - - 0x0 - 0x400 - registers - - - - EVTOUT - EVTOUT - Event output register - (IOMUX_EVTOUT) - 0x0 - 0x20 - read-write - 0x00000000 - - - SELPIN - Select pin - 0 - 4 - - - SELPORT - Select port - 4 - 3 - - - EVOEN - Event output enable - 7 - 1 - - - - - REMAP - REMAP - IO MUX remap register - 0x4 - 0x20 - 0x00000000 - - - SPI1_MUX0 - SPI1 muxing bit0 - 0 - 1 - read-write - - - I2C1_MUX - I2C1 muxing - 1 - 1 - read-write - - - USART1_MUX - USART1 muxing - 2 - 1 - read-write - - - USART3_MUX - USART3 muxing - 4 - 2 - read-write - - - TMR1_MUX - TMR1 muxing - 6 - 2 - read-write - - - TMR2_MUX - TMR2 muxing - 8 - 2 - read-write - - - TMR3_MUX - TMR3 muxing - 10 - 2 - read-write - - - CAN_MUX - CAN1 muxing - 13 - 2 - read-write - - - PD01_MUX - PD0/PD1 muxing on OSCIN/OSCOUT - 15 - 1 - read-write - - - TMR5CH4_MUX - TMR5 channel4 internal muxing - 16 - 1 - read-write - - - ADC1_ETP_MUX - ADC1 external trigger preempted conversion muxing - 17 - 1 - read-write - - - ADC1_ETO_MUX - ADC1 external trigger ordinary conversion muxing - 18 - 1 - read-write - - - SWJTAG_MUX - SWD JTAG muxing - 24 - 3 - read-write - - - SPI1_MUX1 - SPI1 muxing bit1 - 31 - 1 - read-write - - - - - EXINTC1 - EXINTC1 - External interrupt configuration register 1 - (IOMUX_EXINTC1) - 0x8 - 0x20 - read-write - 0x00000000 - - - EXINT0 - Configure EXINT0 source - 0 - 4 - - - EXINT1 - Configure EXINT1 source - 4 - 4 - - - EXINT2 - Configure EXINT2 source - 8 - 4 - - - EXINT3 - Configure EXINT3 source - 12 - 4 - - - - - EXINTC2 - EXINTC2 - External interrupt configuration register 2 - (IOMUX_EXINTC2) - 0xC - 0x20 - read-write - 0x00000000 - - - EXINT4 - Configure EXINT4 source - 0 - 4 - - - EXINT5 - Configure EXINT5 source - 4 - 4 - - - EXINT6 - Configure EXINT6 source - 8 - 4 - - - EXINT7 - Configure EXINT7 source - 12 - 4 - - - - - EXINTC3 - EXINTC3 - External interrupt configuration register 3 - (IOMUX_EXINTC3) - 0x10 - 0x20 - read-write - 0x00000000 - - - EXINT8 - Configure EXINT8 source - 0 - 4 - - - EXINT9 - Configure EXINT9 source - 4 - 4 - - - EXINT10 - Configure EXINT10 source - 8 - 4 - - - EXINT11 - Configure EXINT11 source - 12 - 4 - - - - - EXINTC4 - EXINTC4 - External interrupt configuration register 4 - (IOMUX_EXINTC4) - 0x14 - 0x20 - read-write - 0x00000000 - - - EXINT12 - Configure EXINT12 source - 0 - 4 - - - EXINT13 - Configure EXINT13 source - 4 - 4 - - - EXINT14 - Configure EXINT14 source - 8 - 4 - - - EXINT15 - Configure EXINT15 source - 12 - 4 - - - - - REMAP2 - REMAP2 - IO MUX remap register 2 - 0x1C - 0x20 - write-only - 0x00000000 - - - CMP_MUX - CMP internal muxing - 26 - 2 - - - - - REMAP3 - REMAP3 - IO MUX remap register 3 - 0x20 - 0x20 - read-write - 0x00000000 - - - TMR11_GMUX - TMR11 muxing - 8 - 4 - - - TMR10_GMUX - TMR10 muxing - 4 - 4 - - - TMR9_GMUX - TMR9 muxing - 0 - 4 - - - - - REMAP4 - REMAP4 - IO MUX remap register 4 - 0x24 - 0x20 - read-write - 0x00000000 - - - TMR5CH4_GMUX - TMR5CH4 muxing - 19 - 1 - - - TMR5_GMUX - TMR5 muxing - 16 - 3 - - - TMR3_GMUX - TMR3 muxing - 8 - 4 - - - TMR2_GMUX - TMR2 muxing - 4 - 3 - - - TMR1_GMUX - TMR1 muxing - 0 - 4 - - - - - REMAP5 - REMAP5 - IO MUX remap register 5 - 0x28 - 0x20 - read-write - 0x00000000 - - - SPI2_GMUX - SPI2 muxing - 20 - 4 - - - SPI1_GMUX - SPI1 muxing - 16 - 4 - - - I2C2_GMUX - I2C2 muxing - 8 - 4 - - - I2C1_GMUX - I2C1 muxing - 4 - 4 - - - - - REMAP6 - REMAP6 - IO MUX remap register 6 - 0x2C - 0x20 - read-write - 0x00000000 - - - UART4_GMUX - UART4 muxing - 28 - 4 - - - USART3_GMUX - USART3 muxing - 24 - 4 - - - USART1_GMUX - USART1 muxing - 16 - 4 - - - SDIO1_GMUX - SDIO1 muxing - 8 - 4 - - - CAN1_GMUX - CAN1 muxing - 0 - 4 - - - - - REMAP7 - REMAP7 - IO MUX remap register 7 - 0x30 - 0x20 - read-write - 0x00000000 - - - PD01_GMUX - PortD0/PortD1 muxing on OSC_IN/OSC_OUT - 20 - 1 - - - SWJTAG_GMUX - Serial wire JTAG muxing - 16 - 3 - - - ADC1_ETO_GMUX - ADC1 external trigger ordinary conversion muxing - 5 - 1 - - - ADC1_ETP_GMUX - ADC1 external trigger preempted conversion muxing - 4 - 1 - - - - - REMAP8 - REMAP8 - IO MUX remap register 8 - 0x34 - 0x20 - read-write - 0x00000000 - - - TMR3_CH1_CMP_GMUX - TMR3 CH1 CMP muxing - 6 - 2 - - - TMR2_CH4_CMP_GMUX - TMR2 CH4 CMP muxing - 4 - 2 - - - TMR1_CH1_CMP_GMUX - TMR1 CH1 CMP muxing - 2 - 2 - - - TMR1_BK1_CMP_GMUX - TMR1 BK1 CMP muxing - 0 - 2 - - - - - - - EXINT - EXINT - EXINT - 0x40010400 - - 0x0 - 0x400 - registers - - - PVM - PVD interrupt - 1 - - - ERTC - ERTC interrupt - 3 - - - TAMPER - Tamper interrupt - 2 - - - ERTCAlarm - ERTCAlarm interrupt - 41 - - - CMP1 - CMP1 interrupt - 70 - - - CMP2 - CMP2 interrupt - 71 - - - EXTINT0 - EXTI Line0 interrupt - 6 - - - EXTINT1 - EXTI Line1 interrupt - 7 - - - EXTINT2 - EXTI Line2 interrupt - 8 - - - EXTINT3 - EXTI Line3 interrupt - 9 - - - EXTINT4 - EXTI Line4 interrupt - 10 - - - EXTINT9_5 - EXTI Line[9:5] interrupts - 23 - - - EXTINT15_10 - EXTI Line[15:10] interrupts - 40 - - - - INTEN - INTEN - Interrupt enable register - 0x0 - 0x20 - read-write - 0x00000000 - - - INTEN0 - Interrupt enable or disable on line 0 - 0 - 1 - - - INTEN1 - Interrupt enable or disable on line 1 - 1 - 1 - - - INTEN2 - Interrupt enable or disable on line 2 - 2 - 1 - - - INTEN3 - Interrupt enable or disable on line 3 - 3 - 1 - - - INTEN4 - Interrupt enable or disable on line 4 - 4 - 1 - - - INTEN5 - Interrupt enable or disable on line 5 - 5 - 1 - - - INTEN6 - Interrupt enable or disable on line 6 - 6 - 1 - - - INTEN7 - Interrupt enable or disable on line 7 - 7 - 1 - - - INTEN8 - Interrupt enable or disable on line 8 - 8 - 1 - - - INTEN9 - Interrupt enable or disable on line 9 - 9 - 1 - - - INTEN10 - Interrupt enable or disable on line 10 - 10 - 1 - - - INTEN11 - Interrupt enable or disable on line 11 - 11 - 1 - - - INTEN12 - Interrupt enable or disable on line 12 - 12 - 1 - - - INTEN13 - Interrupt enable or disable on line 13 - 13 - 1 - - - INTEN14 - Interrupt enable or disable on line 14 - 14 - 1 - - - INTEN15 - Interrupt enable or disable on line 15 - 15 - 1 - - - INTEN16 - Interrupt enable or disable on line 16 - 16 - 1 - - - INTEN17 - Interrupt enable or disable on line 17 - 17 - 1 - - - INTEN18 - Interrupt enable or disable on line 18 - 18 - 1 - - - INTEN19 - Interrupt enable or disable on line 19 - 19 - 1 - - - INTEN20 - Interrupt enable or disable on line 20 - 20 - 1 - - - INTEN21 - Interrupt enable or disable on line 21 - 21 - 1 - - - INTEN22 - Interrupt enable or disable on line 22 - 22 - 1 - - - - - EVTEN - EVTEN - Event enable register - 0x4 - 0x20 - read-write - 0x00000000 - - - EVTEN0 - Event enable or disable on line 0 - 0 - 1 - - - EVTEN1 - Event enable or disable on line 1 - 1 - 1 - - - EVTEN2 - Event enable or disable on line 2 - 2 - 1 - - - EVTEN3 - Event enable or disable on line 3 - 3 - 1 - - - EVTEN4 - Event enable or disable on line 4 - 4 - 1 - - - EVTEN5 - Event enable or disable on line 5 - 5 - 1 - - - EVTEN6 - Event enable or disable on line 6 - 6 - 1 - - - EVTEN7 - Event enable or disable on line 7 - 7 - 1 - - - EVTEN8 - Event enable or disable on line 8 - 8 - 1 - - - EVTEN9 - Event enable or disable on line 9 - 9 - 1 - - - EVTEN10 - Event enable or disable on line 10 - 10 - 1 - - - EVTEN11 - Event enable or disable on line 11 - 11 - 1 - - - EVTEN12 - Event enable or disable on line 12 - 12 - 1 - - - EVTEN13 - Event enable or disable on line 13 - 13 - 1 - - - EVTEN14 - Event enable or disable on line 14 - 14 - 1 - - - EVTEN15 - Event enable or disable on line 15 - 15 - 1 - - - EVTEN16 - Event enable or disable on line 16 - 16 - 1 - - - EVTEN17 - Event enable or disable on line 17 - 17 - 1 - - - EVTEN18 - Event enable or disable on line 18 - 18 - 1 - - - EVTEN19 - Event enable or disable on line 19 - 19 - 1 - - - EVTEN20 - Event enable or disable on line 20 - 20 - 1 - - - EVTEN21 - Event enable or disable on line 21 - 21 - 1 - - - EVTEN22 - Event enable or disable on line 22 - 22 - 1 - - - - - POLCFG1 - POLCFG1 - Rising polarity configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - RP0 - Rising polarity configuration bit of line 0 - 0 - 1 - - - RP1 - Rising polarity configuration bit of line 1 - 1 - 1 - - - RP2 - Rising polarity configuration bit of line 2 - 2 - 1 - - - RP3 - Rising polarity configuration bit of line 3 - 3 - 1 - - - RP4 - Rising polarity configuration bit of line 4 - 4 - 1 - - - RP5 - Rising polarity configuration bit of line 5 - 5 - 1 - - - RP6 - Rising polarity configuration bit of linee 6 - 6 - 1 - - - RP7 - Rising polarity configuration bit of line 7 - 7 - 1 - - - RP8 - Rising polarity configuration bit of line 8 - 8 - 1 - - - RP9 - Rising polarity configuration bit of line 9 - 9 - 1 - - - RP10 - Rising polarity configuration bit of line 10 - 10 - 1 - - - RP11 - Rising polarity configuration bit of line 11 - 11 - 1 - - - RP12 - Rising polarity configuration bit of line 12 - 12 - 1 - - - RP13 - Rising polarity configuration bit of line 13 - 13 - 1 - - - RP14 - Rising polarity configuration bit of line 14 - 14 - 1 - - - RP15 - Rising polarity configuration bit of line 15 - 15 - 1 - - - RP16 - Rising polarity configuration bit of line 16 - 16 - 1 - - - RP17 - Rising polarity configuration bit of line 17 - 17 - 1 - - - RP18 - Rising polarity configuration bit of line 18 - 18 - 1 - - - RP19 - Rising polarity configuration bit of line 19 - 19 - 1 - - - RP20 - Rising polarity configuration bit of line 20 - 20 - 1 - - - RP21 - Rising polarity configuration bit of line 21 - 21 - 1 - - - RP22 - Rising polarity configuration bit of line 22 - 22 - 1 - - - - - POLCFG2 - POLCFG2 - Falling polarity configuration register - 0xC - 0x20 - read-write - 0x00000000 - - - FP0 - Falling polarity event configuration bit of line 0 - 0 - 1 - - - FP1 - Falling polarity event configuration bit of line 1 - 1 - 1 - - - FP2 - Falling polarity event configuration bit of line 2 - 2 - 1 - - - FP3 - Falling polarity event configuration bit of line 3 - 3 - 1 - - - FP4 - Falling polarity event configuration bit of line 4 - 4 - 1 - - - FP5 - Falling polarity event configuration bit of line 5 - 5 - 1 - - - FP6 - Falling polarity event configuration bit of line 6 - 6 - 1 - - - FP7 - Falling polarity event configuration bit of line 7 - 7 - 1 - - - FP8 - Falling polarity event configuration bit of line 8 - 8 - 1 - - - FP9 - Falling polarity event configuration bit of line 9 - 9 - 1 - - - FP10 - Falling polarity event configuration bit of line 10 - 10 - 1 - - - FP11 - Falling polarity event configuration bit of line 11 - 11 - 1 - - - FP12 - Falling polarity event configuration bit of line 12 - 12 - 1 - - - FP13 - Falling polarity event configuration bit of line 13 - 13 - 1 - - - FP14 - Falling polarity event configuration bit of line 14 - 14 - 1 - - - FP15 - Falling polarity event configuration bit of line 15 - 15 - 1 - - - FP16 - Falling polarity event configuration bit of line 16 - 16 - 1 - - - FP17 - Falling polarity event configuration bit of line 17 - 17 - 1 - - - FP18 - Falling polarity event configuration bit of line 18 - 18 - 1 - - - FP19 - Falling polarity event configuration bit of line 19 - 19 - 1 - - - FP20 - Falling polarity event configuration bit of line 20 - 20 - 1 - - - FP21 - Falling polarity event configuration bit of line 21 - 21 - 1 - - - FP22 - Falling polarity event configuration bit of line 22 - 22 - 1 - - - - - SWTRG - SWTRG - Software triggle register - 0x10 - 0x20 - read-write - 0x00000000 - - - SWT0 - Software triggle on line 0 - 0 - 1 - - - SWT1 - Software triggle on line 1 - 1 - 1 - - - SWT2 - Software triggle on line 2 - 2 - 1 - - - SWT3 - Software triggle on line 3 - 3 - 1 - - - SWT4 - Software triggle on line 4 - 4 - 1 - - - SWT5 - Software triggle on line 5 - 5 - 1 - - - SWT6 - Software triggle on line 6 - 6 - 1 - - - SWT7 - Software triggle on line 7 - 7 - 1 - - - SWT8 - Software triggle on line 8 - 8 - 1 - - - SWT9 - Software triggle on line 9 - 9 - 1 - - - SWT10 - Software triggle on line 10 - 10 - 1 - - - SWT11 - Software triggle on line 11 - 11 - 1 - - - SWT12 - Software triggle on line 12 - 12 - 1 - - - SWT13 - Software triggle on line 13 - 13 - 1 - - - SWT14 - Software triggle on line 14 - 14 - 1 - - - SWT15 - Software triggle on line 15 - 15 - 1 - - - SWT16 - Software triggle on line 16 - 16 - 1 - - - SWT17 - Software triggle on line 17 - 17 - 1 - - - SWT18 - Software triggle on line 18 - 18 - 1 - - - SWT19 - Software triggle on line 19 - 19 - 1 - - - SWT20 - Software triggle on line 20 - 20 - 1 - - - SWT21 - Software triggle on line 21 - 21 - 1 - - - SWT22 - Software triggle on line 22 - 22 - 1 - - - - - INTSTS - INTSTS - Interrupt status register - 0x14 - 0x20 - read-write - 0x00000000 - - - LINE0 - Line 0 state bit - 0 - 1 - - - LINE1 - Line 1 state bit - 1 - 1 - - - LINE2 - Line 2 state bit - 2 - 1 - - - LINE3 - Line 3 state bit - 3 - 1 - - - LINE4 - Line 4 state bit - 4 - 1 - - - LINE5 - Line 5 state bit - 5 - 1 - - - LINE6 - Line 6 state bit - 6 - 1 - - - LINE7 - Line 7 state bit - 7 - 1 - - - LINE8 - Line 8 state bit - 8 - 1 - - - LINE9 - Line 9 state bit - 9 - 1 - - - LINE10 - Line 10 state bit - 10 - 1 - - - LINE11 - Line 11 state bit - 11 - 1 - - - LINE12 - Line 12 state bit - 12 - 1 - - - LINE13 - Line 13 state bit - 13 - 1 - - - LINE14 - Line 14 state bit - 14 - 1 - - - LINE15 - Line 15 state bit - 15 - 1 - - - LINE16 - Line 16 state bit - 16 - 1 - - - LINE17 - Line 17 state bit - 17 - 1 - - - LINE18 - Line 18 state bit - 18 - 1 - - - LINE19 - Line 19 state bit - 19 - 1 - - - LINE20 - Line 20 state bit - 20 - 1 - - - LINE21 - Line 21 state bit - 21 - 1 - - - LINE22 - Line 22 state bit - 22 - 1 - - - - - - - DMA1 - DMA controller - DMA - 0x40020000 - - 0x0 - 0x400 - registers - - - DMA1_Channel1 - DMA1 Channel1 global interrupt - 11 - - - DMA1_Channel2 - DMA1 Channel2 global interrupt - 12 - - - DMA1_Channel3 - DMA1 Channel3 global interrupt - 13 - - - DMA1_Channel4 - DMA1 Channel4 global interrupt - 14 - - - DMA1_Channel5 - DMA1 Channel5 global interrupt - 15 - - - DMA1_Channel6 - DMA1 Channel6 global interrupt - 16 - - - DMA1_Channel7 - DMA1 Channel7 global interrupt - 17 - - - - STS - STS - DMA status register (DMA_STS) - 0x0 - 0x20 - read-only - 0x00000000 - - - GF1 - Channel 1 Global event flag - 0 - 1 - - - GF2 - Channel 2 Global event flag - 4 - 1 - - - GF3 - Channel 3 Global event flag - 8 - 1 - - - GF4 - Channel 4 Global event flag - 12 - 1 - - - GF5 - Channel 5 Global event flag - 16 - 1 - - - GF6 - Channel 6 Global event flag - 20 - 1 - - - GF7 - Channel 7 Global event flag - 24 - 1 - - - FDTF1 - Channel 1 full data transfer event flag - 1 - 1 - - - FDTF2 - Channel 2 full data transfer event flag - 5 - 1 - - - FDTF3 - Channel 3 full data transfer event flag - 9 - 1 - - - FDTF4 - Channel 4 full data transfer event flag - 13 - 1 - - - FDTF5 - Channel 5 full data transfer event flag - 17 - 1 - - - FDTF6 - Channel 6 full data transfer event flag - 21 - 1 - - - FDTF7 - Channel 7 full data transfer event flag - 25 - 1 - - - HDTF1 - Channel 1 half data transfer event flag - 2 - 1 - - - HDTF2 - Channel 2 half data transfer event flag - 6 - 1 - - - HDTF3 - Channel 3 half data transfer event flag - 10 - 1 - - - HDTF4 - Channel 4 half data transfer event flag - 14 - 1 - - - HDTF5 - Channel 5 half data transfer event flag - 18 - 1 - - - HDTF6 - Channel 6 half data transfer event flag - 22 - 1 - - - HDTF7 - Channel 7 half data transfer event flag - 26 - 1 - - - DTERRF1 - Channel 1 data transfer error event flag - 3 - 1 - - - DTERRF2 - Channel 2 data transfer error event flag - 7 - 1 - - - DTERRF3 - Channel 3 data transfer error event flag - 11 - 1 - - - DTERRF4 - Channel 4 data transfer error event flag - 15 - 1 - - - DTERRF5 - Channel 5 data transfer error event flag - 19 - 1 - - - DTERRF6 - Channel 6 data transfer error event flag - 23 - 1 - - - DTERRF7 - Channel 7 data transfer error event flag - 27 - 1 - - - - - CLR - CLR - DMA flag clear register (DMA_CLR) - 0x4 - 0x20 - read-write - 0x00000000 - - - GFC1 - Channel 1 Global flag clear - 0 - 1 - - - GFC2 - Channel 2 Global flag clear - 4 - 1 - - - GFC3 - Channel 3 Global flag clear - 8 - 1 - - - GFC4 - Channel 4 Global flag clear - 12 - 1 - - - GFC5 - Channel 5 Global flag clear - 16 - 1 - - - GFC6 - Channel 6 Global flag clear - 20 - 1 - - - GFC7 - Channel 7 Global flag clear - 24 - 1 - - - FDTFC1 - Channel 1 full data transfer flag clear - 1 - 1 - - - FDTFC2 - Channel 2 full data transfer flag clear - 5 - 1 - - - FDTFC3 - Channel 3 full data transfer flag clear - 9 - 1 - - - FDTFC4 - Channel 4 full data transfer flag clear - 13 - 1 - - - FDTFC5 - Channel 5 full data transfer flag clear - 17 - 1 - - - FDTFC6 - Channel 6 full data transfer flag clear - 21 - 1 - - - FDTFC7 - Channel 7 full data transfer flag clear - 25 - 1 - - - HDTFC1 - Channel 1 half data transfer flag clear - 2 - 1 - - - HDTFC2 - Channel 2 half data transfer flag clear - 6 - 1 - - - HDTFC3 - Channel 3 half data transfer flag clear - 10 - 1 - - - HDTFC4 - Channel 4 half data transfer flag clear - 14 - 1 - - - HDTFC5 - Channel 5 half data transfer flag clear - 18 - 1 - - - HDTFC6 - Channel 6 half data transfer flag clear - 22 - 1 - - - HDTFC7 - Channel 7 half data transfer flag clear - 26 - 1 - - - DTERRFC1 - Channel 1 data transfer error flag clear - 3 - 1 - - - DTERRFC2 - Channel 2 data transfer error flag clear - 7 - 1 - - - DTERRFC3 - Channel 3 data transfer error flag clear - 11 - 1 - - - DTERRFC4 - Channel 4 data transfer error flag clear - 15 - 1 - - - DTERRFC5 - Channel 5 data transfer error flag clear - 19 - 1 - - - DTERRFC6 - Channel 6 data transfer error flag clear - 23 - 1 - - - DTERRFC7 - Channel 7 data transfer error flag clear - 27 - 1 - - - - - C1CTRL - C1CTRL - DMA channel configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C1DTCNT - C1DTCNT - DMA channel 1 number of data to transfer register - 0xC - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C1PADDR - C1PADDR - DMA channel 1 peripheral base address register - 0x10 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C1MADDR - C1MADDR - DMA channel 1 memory base address register - 0x14 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C2CTRL - C2CTRL - DMA channel configuration register - 0x1C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C2DTCNT - C2DTCNT - DMA channel 2 number of data to transferregister - 0x20 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C2PADDR - C2PADDR - DMA channel 2 peripheral base address register - 0x24 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C2MADDR - C2MADDR - DMA channel 2 memory base address register - 0x28 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C3CTRL - C3CTRL - DMA channel configuration register - 0x30 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C3DTCNT - C3DTCNT - DMA channel 3 number of data to transfer register - 0x34 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C3PADDR - C3PADDR - DMA channel 3 peripheral base address register - 0x38 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C3MADDR - C3MADDR - DMA channel 3 memory base address register - 0x3C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C4CTRL - C4CTRL - DMA channel configuration register - 0x44 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C4DTCNT - C4DTCNT - DMA channel 4 number of data to transfer register - 0x48 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C4PADDR - C4PADDR - DMA channel 4 peripheral base address register - 0x4C - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C4MADDR - C4MADDR - DMA channel 4 memory base address register - 0x50 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C5CTRL - C5CTRL - DMA channel configuration register - 0x58 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C5DTCNT - C5DTCNT - DMA channel 5 number of data to transfer register - 0x5C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C5PADDR - C5PADDR - DMA channel 5 peripheral base address register - 0x60 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C5MADDR - C5MADDR - DMA channel 5 memory base address register - 0x64 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C6CTRL - C6CTRL - DMA channel configuration register - 0x6C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C6DTCNT - C6DTCNT - DMA channel 6 number of data to transfer register - 0x70 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C6PADDR - C6PADDR - DMA channel 6 peripheral address base register - 0x74 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C6MADDR - C6MADDR - DMA channel 6 memory address base register - 0x78 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C7CTRL - C7CTRL - DMA channel configuration register - 0x80 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C7DTCNT - C7DTCNT - DMA channel 7 number of data to transfer register - 0x84 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C7PADDR - C7PADDR - DMA channel 7 peripheral base address register - 0x88 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C7MADDR - C7MADDR - DMA channel 7 memory base address register - 0x8C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - DMA_SRC_SEL0 - DMA_SRC_SEL0 - DMA channel source assignment register - 0xA0 - 0x20 - read-write - 0x00000000 - - - CH1_SRC - CH1 SRC select - 0 - 8 - - - CH2_SRC - CH2 SRC select - 8 - 8 - - - CH3_SRC - CH3 SRC select - 16 - 8 - - - CH4_SRC - CH4 SRC select - 24 - 8 - - - - - DMA_SRC_SEL1 - DMA_SRC_SEL1 - DMA channel source assignment register - 0xA4 - 0x20 - read-write - 0x00000000 - - - CH5_SRC - CH5 SRC select - 0 - 8 - - - CH6_SRC - CH6 SRC select - 8 - 8 - - - CH7_SRC - CH7 SRC select - 16 - 8 - - - DMA_FLEX_EN - DMA FLEX Enable - 24 - 1 - - - - - - - DMA2 - 0x40020400 - - DMA2_Channel1 - DMA2 Channel1 global interrupt - 56 - - - DMA2_Channel2 - DMA2 Channel2 global interrupt - 57 - - - DMA2_Channel3 - DMA2 Channel3 global interrupt - 58 - - - DMA2_Channel4_5 - DMA2 Channel4 and DMA2 Channel5 global - interrupt - 59 - - - DMA2_Channel6_7 - DMA2 Channel6 and DMA2 Channel7 global - interrupt - 75 - - - - SDIO1 - Secure digital input/output - interface - SDIO - 0x40018000 - - 0x0 - 0x400 - registers - - - SDIO1 - SDIO1 global interrupt - 49 - - - - POWER - POWER - Bits 1:0 = PWRCTRL: Power supply control - bits - 0x0 - 0x20 - read-write - 0x00000000 - - - PWRCTRL - PWRCTRL - 0 - 2 - - - - - CLKCTRL - CLKCTRL - SDI clock control register - (SDIO_CLKCTRL) - 0x4 - 0x20 - read-write - 0x00000000 - - - CLKPSC - Clock divide factor - 0 - 8 - - - CLKEN - Clock enable bit - 8 - 1 - - - PWRSVG - Power saving configuration - bit - 9 - 1 - - - BYPS - Clock divider bypass enable - bit - 10 - 1 - - - BUSWIDTH - Wide bus mode enable bit - 11 - 2 - - - CLKEDG - SDIO_CK dephasing selection - bit - 13 - 1 - - - FLWCTRLEN - HW Flow Control enable - 14 - 1 - - - CLKPSC98 - Clock divide factor bit9 and bit8 - 15 - 2 - - - - - ARG - ARG - Bits 31:0 = : Command argument - 0x8 - 0x20 - read-write - 0x00000000 - - - ARG - Command argument - 0 - 32 - - - - - CMD - CMD - SDIO command register - (SDIO_CMD) - 0xC - 0x20 - read-write - 0x00000000 - - - CMDIDX - CMDIDX - 0 - 6 - - - RSPWT - WAITRESP - 6 - 2 - - - INTWT - WAITINT - 8 - 1 - - - PNDWT - WAITPEND - 9 - 1 - - - CMDMEN - CPSMEN - 10 - 1 - - - SDIOSUSP - SDIOSuspend - 11 - 1 - - - - - RSPCMD - RSPCMD - SDIO command register - 0x10 - 0x20 - read-only - 0x00000000 - - - RSPCMD - RSPCMD - 0 - 6 - - - - - RSP1 - RSP1 - Bits 31:0 = CARDSTATUS1 - 0x14 - 0x20 - read-only - 0x00000000 - - - CARDSTS1 - CARDSTATUS1 - 0 - 32 - - - - - RSP2 - RSP2 - Bits 31:0 = CARDSTATUS2 - 0x18 - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS2 - 0 - 32 - - - - - RSP3 - RSP3 - Bits 31:0 = CARDSTATUS3 - 0x1C - 0x20 - read-only - 0x00000000 - - - CARDSTS3 - CARDSTATUS3 - 0 - 32 - - - - - RSP4 - RSP4 - Bits 31:0 = CARDSTATUS4 - 0x20 - 0x20 - read-only - 0x00000000 - - - CARDSTS4 - CARDSTATUS4 - 0 - 32 - - - - - DTTMR - DTTMR - Bits 31:0 = DATATIME: Data timeout - period - 0x24 - 0x20 - read-write - 0x00000000 - - - TIMEOUT - Data timeout period - 0 - 32 - - - - - DTLEN - DTLEN - Bits 24:0 = DATALENGTH: Data length - value - 0x28 - 0x20 - read-write - 0x00000000 - - - DTLEN - Data length value - 0 - 25 - - - - - DTCTRL - DTCTRL - SDIO data control register - (SDIO_DCTRL) - 0x2C - 0x20 - read-write - 0x00000000 - - - TFREN - DTEN - 0 - 1 - - - TFRDIR - DTDIR - 1 - 1 - - - TFRMODE - DTMODE - 2 - 1 - - - DMAEN - DMAEN - 3 - 1 - - - BLKSIZE - DBLOCKSIZE - 4 - 4 - - - RDWTSTART - PWSTART - 8 - 1 - - - RDWTSTOP - PWSTOP - 9 - 1 - - - RDWTMODE - RWMOD - 10 - 1 - - - SDIOEN - SDIOEN - 11 - 1 - - - - - DTCNTR - DTCNTR - Bits 24:0 = DATACOUNT: Data count - value - 0x30 - 0x20 - read-only - 0x00000000 - - - CNT - Data count value - 0 - 25 - - - - - STS - STS - SDIO status register - (SDIO_STS) - 0x34 - 0x20 - read-only - 0x00000000 - - - CMDFAIL - CCRCFAIL - 0 - 1 - - - DTFAIL - DCRCFAIL - 1 - 1 - - - CMDTIMEOUT - CTIMEOUT - 2 - 1 - - - DTTIMEOUT - DTIMEOUT - 3 - 1 - - - TXERRU - TXUNDERR - 4 - 1 - - - RXERRO - RXOVERR - 5 - 1 - - - CMDRSPCMPL - CMDREND - 6 - 1 - - - CMDCMPL - CMDSENT - 7 - 1 - - - DTCMPL - DATAEND - 8 - 1 - - - SBITERR - STBITERR - 9 - 1 - - - DTBLKCMPL - DBCKEND - 10 - 1 - - - DOCMD - CMDACT - 11 - 1 - - - DOTX - TXACT - 12 - 1 - - - DORX - RXACT - 13 - 1 - - - TXBUF_H - TXFIFOHE - 14 - 1 - - - RXBUF_H - RXFIFOHF - 15 - 1 - - - TXBUF_F - TXFIFOF - 16 - 1 - - - RXBUF_F - RXFIFOF - 17 - 1 - - - TXBUF_E - TXFIFOE - 18 - 1 - - - RXBUF_E - RXFIFOE - 19 - 1 - - - TXBUF - TXDAVL - 20 - 1 - - - RXBUF - RXDAVL - 21 - 1 - - - SDIOIF - SDIOIT - 22 - 1 - - - - - INTCLR - INTCLR - SDIO interrupt clear register - (SDIO_INTCLR) - 0x38 - 0x20 - read-write - 0x00000000 - - - CMDFAIL - CCRCFAILC - 0 - 1 - - - DTFAIL - DCRCFAILC - 1 - 1 - - - CMDTIMEOUT - CTIMEOUTC - 2 - 1 - - - DTTIMEOUT - DTIMEOUTC - 3 - 1 - - - TXERRU - TXUNDERRC - 4 - 1 - - - RXERRU - RXOVERRC - 5 - 1 - - - CMDRSPCMPL - CMDRENDC - 6 - 1 - - - CMDCMPL - CMDSENTC - 7 - 1 - - - DTCMPL - DATAENDC - 8 - 1 - - - SBITERR - STBITERRC - 9 - 1 - - - DTBLKCMPL - DBCKENDC - 10 - 1 - - - SDIOIF - SDIOITC - 22 - 1 - - - - - INTEN - INTEN - SDIO interrupt enable register - (SDIO_INTEN) - 0x3C - 0x20 - read-write - 0x00000000 - - - CMDFAIL - CCRCFAILIE - 0 - 1 - - - DTFAIL - DCRCFAILIE - 1 - 1 - - - CMDTIMEOUT - CTIMEOUTIE - 2 - 1 - - - DTTIMEOUT - DTIMEOUTIE - 3 - 1 - - - TXERRU - TXUNDERRIE - 4 - 1 - - - RXERRU - RXOVERRIE - 5 - 1 - - - CMDRSPCMPL - CMDRENDIE - 6 - 1 - - - CMDCMPL - CMDSENTIE - 7 - 1 - - - DTCMPL - DATAENDIE - 8 - 1 - - - SBITERR - STBITERRIE - 9 - 1 - - - DTBLKCMPL - DBACKENDIE - 10 - 1 - - - DOCMD - CMDACTIE - 11 - 1 - - - DOTX - TXACTIE - 12 - 1 - - - DORX - RXACTIE - 13 - 1 - - - TXBUF_H - TXFIFOHEIE - 14 - 1 - - - RXBUF_H - RXFIFOHFIE - 15 - 1 - - - TXBUF_F - TXFIFOFIE - 16 - 1 - - - RXBUF_F - RXFIFOFIE - 17 - 1 - - - TXBUF_E - TXFIFOEIE - 18 - 1 - - - RXBUF_E - RXFIFOEIE - 19 - 1 - - - TXBUF - TXDAVLIE - 20 - 1 - - - RXBUF - RXDAVLIE - 21 - 1 - - - SDIOIF - SDIOITIE - 22 - 1 - - - - - BUFCNTR - BUFCNTR - Bits 23:0 = FIFOCOUNT: Remaining number of - words to be written to or read from the - FIFO - 0x48 - 0x20 - read-only - 0x00000000 - - - CNT - FIF0COUNT - 0 - 24 - - - - - BUF - BUF - bits 31:0 = FIFOData: Receive and transmit - FIFO data - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - FIFOData - 0 - 32 - - - - - - - ACC - HICK Auto Clock Calibration - ACC - 0x40015800 - - 0x0 - 0x400 - registers - - - ACC - ACC global interrupt - 72 - - - - STS - STS - Status register - 0x0 - 0x20 - read-write - 0x00000000 - - - CALRDY - Internal high-speed clock calibration ready - 0 - 1 - - - RSLOST - Reference Signal Lost - 1 - 1 - - - - - CTRL1 - CTRL1 - Control register 1 - 0x4 - 0x20 - read-write - 0x00000100 - - - CALON - Internal high-speed clock calibration ready - 0 - 1 - - - ENTRIM - Enable trim - 1 - 1 - - - EIEN - RSLOST error interrupt enable - 4 - 1 - - - CALRDYIEN - CALRDY interrupt enable - 5 - 1 - - - STEP - STEP - 8 - 4 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x8 - 0x20 - read-only - 0x00002080 - - - ACC_HSICAL - Internal high-speed auto clock calibration - 0 - 8 - - - ACC_HSITRIM - Internal high-speed auto clock trimming - 8 - 6 - - - - - C1 - C1 - Compare 1 - 0xC - 0x20 - read-write - 0x00001F2C - - - C1 - Compare 1 - 0 - 16 - - - - - C2 - C2 - Compare 2 - 0x10 - 0x20 - read-write - 0x00001F40 - - - C2 - Compare 2 - 0 - 16 - - - - - C3 - C3 - Compare 3 - 0x14 - 0x20 - read-write - 0x00001F54 - - - C3 - Compare 3 - 0 - 16 - - - - - - - ERTC - Real-time clock - ERTC - 0x40002800 - - 0x0 - 0x400 - registers - - - - TIME - TIME - time register - 0x0 - 0x20 - read-write - 0x00000000 - - - AMPM - AM/PM notation - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - DATE - DATE - date register - 0x4 - 0x20 - read-write - 0x00002101 - - - YT - Year tens - 20 - 4 - - - YU - Year units - 16 - 4 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - CTRL - CTRL - control register - 0x8 - 0x20 - read-write - 0x00000000 - - - CALOEN - Calibration output enable - 23 - 1 - - - OUTSEL - Output source selection - 21 - 2 - - - OUTP - Output polarity - 20 - 1 - - - CALOSEL - Calibration output selection - 19 - 1 - - - BPR - Battery power domain data register - 18 - 1 - - - DEC1H - Decrease 1 hour - 17 - 1 - - - ADD1H - Add 1 hour - 16 - 1 - - - TSIEN - Timestamp interrupt enable - 15 - 1 - - - WATIEN - Wakeup timer interrupt enable - 14 - 1 - - - ALBIEN - Alarm B interrupt enable - 13 - 1 - - - ALAIEN - Alarm A interrupt enable - 12 - 1 - - - TSEN - Timestamp enable - 11 - 1 - - - WATEN - Wakeup timer enable - 10 - 1 - - - ALBEN - Alarm B enable - 9 - 1 - - - ALAEN - Alarm A enable - 8 - 1 - - - CCALEN - Coarse calibration enable - 7 - 1 - - - HM - Hour mode - 6 - 1 - - - DREN - Date/time register direct read enable - 5 - 1 - - - RCDEN - Reference clock detection enable - 4 - 1 - - - TSEDG - Timestamp trigger edge - 3 - 1 - - - WATCLK - Wakeup timer clock selection - 0 - 3 - - - - - STS - STS - initialization and status - register - 0xC - 0x20 - 0x00000007 - - - ALAWF - Alarm A register allows write flag - 0 - 1 - read-only - - - ALBWF - Alarm B register allows write flag - 1 - 1 - read-only - - - WATWF - Wakeup timer register allows write flag - 2 - 1 - read-only - - - TADJF - Time adjustment flag - 3 - 1 - read-write - - - INITF - Calendar initialization flag - 4 - 1 - read-only - - - UPDF - Calendar update flag - 5 - 1 - read-write - - - IMF - Enter initialization mode flag - 6 - 1 - read-only - - - IMEN - Initialization mode enable - 7 - 1 - read-write - - - ALAF - Alarm A flag - 8 - 1 - read-write - - - ALBF - Alarm B flag - 9 - 1 - read-write - - - WATF - Wakeup timer flag - 10 - 1 - read-write - - - TSF - Timestamp flag - 11 - 1 - read-write - - - TSOF - Timestamp overflow flag - 12 - 1 - read-write - - - TP1F - Tamper detection 1 flag - 13 - 1 - read-write - - - CALUPDF - Calibration value update completed flag - 16 - 1 - read-only - - - - - DIV - DIV - Diveder register - 0x10 - 0x20 - read-write - 0x007F00FF - - - DIVA - Diveder A - 16 - 7 - - - DIVB - Diveder B - 0 - 15 - - - - - WAT - WAT - Wakeup timer register - 0x14 - 0x20 - read-write - 0x0000FFFF - - - VAL - Wakeup timer reload value - 0 - 16 - - - - - CCAL - CCAL - Calibration register - 0x18 - 0x20 - read-write - 0x00000000 - - - CALDIR - Calibration direction - 7 - 1 - - - CALVAL - Calibration value - 0 - 5 - - - - - ALA - ALA - Alarm A register - 0x1C - 0x20 - read-write - 0x00000000 - - - MASK4 - Date/week mask - 31 - 1 - - - WKSEL - Date/week mode select - 30 - 1 - - - DT - Date tens - 28 - 2 - - - DU - Date units - 24 - 4 - - - MASK3 - Hours mask - 23 - 1 - - - AMPM - AM/PM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MASK2 - Minutes mask - 15 - 1 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - MASK1 - Seconds mask - 7 - 1 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - ALB - ALB - Alarm B register - 0x20 - 0x20 - read-write - 0x00000000 - - - MASK4 - Date/week mask - 31 - 1 - - - WKSEL - Date/week mode select - 30 - 1 - - - DT - Date tens - 28 - 2 - - - DU - Date units - 24 - 4 - - - MASK3 - Hours mask - 23 - 1 - - - AMPM - AM/PM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MASK2 - Minutes mask - 15 - 1 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - MASK1 - Seconds mask - 7 - 1 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - WP - WP - write protection register - 0x24 - 0x20 - write-only - 0x00000000 - - - CMD - Command register - 0 - 8 - - - - - SBS - SBS - sub second register - 0x28 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - TADJ - TADJ - time adjust register - 0x2C - 0x20 - write-only - 0x00000000 - - - ADD1S - Add 1 second - 31 - 1 - - - DECSBS - Decrease sub-second value - 0 - 15 - - - - - TSTM - TSTM - time stamp time register - 0x30 - 0x20 - read-only - 0x00000000 - - - AMPM - AMPM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - TSDT - TSDT - timestamp date register - 0x34 - 0x20 - read-only - 0x00000000 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - TSSBS - TSSBS - timestamp sub second register - 0x38 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - SCAL - SCAL - calibration register - 0x3C - 0x20 - read-write - 0x00000000 - - - ADD - Add ERTC clock - 15 - 1 - - - CAL8 - 8-second calibration period - 14 - 1 - - - CAL16 - 16 second calibration period - 13 - 1 - - - DEC - Decrease ERTC clock - 0 - 9 - - - - - TAMP - TAMP - tamper and alternate function configuration - register - 0x40 - 0x20 - read-write - 0x00000000 - - - OUTTYPE - Output type - 18 - 1 - - - TPPU - Tamper detection pull-up - 15 - 1 - - - TPPR - Tamper detection pre-charge time - 13 - 2 - - - TPFLT - Tamper detection filter time - 11 - 2 - - - TPFREQ - Tamper detection frequency - 8 - 3 - - - TPTSEN - Tamper detection timestamp enable - 7 - 1 - - - TPIEN - Tamper detection interrupt enable - 2 - 1 - - - TP1EDG - Tamper detection 1 valid edge - 1 - 1 - - - TP1EN - Tamper detection 1 enable - 0 - 1 - - - - - ALASBS - ALASBS - alarm A sub second register - 0x44 - 0x20 - read-write - 0x00000000 - - - SBSMSK - Sub-second mask - 24 - 4 - - - SBS - Sub-seconds value - 0 - 15 - - - - - ALBSBS - ALBSBS - alarm B sub second register - 0x48 - 0x20 - read-write - 0x00000000 - - - SBSMSK - Sub-second mask - 24 - 4 - - - SBS - Sub-seconds value - 0 - 15 - - - - - BPR1DT - BPR1DT - Battery powered domain register - 0x50 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR2DT - BPR2DT - Battery powered domain register - 0x54 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR3DT - BPR3DT - Battery powered domain register - 0x58 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR4DT - BPR4DT - Battery powered domain register - 0x5C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR5DT - BPR5DT - Battery powered domain register - 0x60 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR6DT - BPR6DT - Battery powered domain register - 0x64 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR7DT - BPR7DT - Battery powered domain register - 0x68 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR8DT - BPR8DT - Battery powered domain register - 0x6C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR9DT - BPR9DT - Battery powered domain register - 0x70 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR10DT - BPR10DT - Battery powered domain register - 0x74 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR11DT - BPR11DT - Battery powered domain register - 0x78 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR12DT - BPR12DT - Battery powered domain register - 0x7C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR13DT - BPR13DT - Battery powered domain register - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR14DT - BPR14DT - Battery powered domain register - 0x84 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR15DT - BPR15DT - Battery powered domain register - 0x88 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR16DT - BPR16DT - Battery powered domain register - 0x8C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR17DT - BPR17DT - Battery powered domain register - 0x90 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR18DT - BPR18DT - Battery powered domain register - 0x94 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR19DT - BPR19DT - Battery powered domain register - 0x98 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR20DT - BPR20DT - Battery powered domain register - 0x9C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - - - WDT - Watchdog - WDT - 0x40003000 - - 0x0 - 0x400 - registers - - - - CMD - CMD - Command register - 0x0 - 0x20 - read-write - 0x00000000 - - - CMD - Command register - 0 - 16 - - - - - DIV - DIV - Division register - 0x4 - 0x20 - read-write - 0x00000000 - - - DIV - Division divider - 0 - 3 - - - - - RLD - RLD - Reload register - 0x8 - 0x20 - read-write - 0x00000FFF - - - RLD - Reload value - 0 - 12 - - - - - STS - STS - Status register - 0xC - 0x20 - read-write - 0x00000000 - - - DIVF - Division value update complete flag - 0 - 1 - - - RLDF - Reload value update complete flag - 1 - 1 - - - - - - - WWDT - Window watchdog - WWDT - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDT - Window Watchdog interrupt - 0 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - read-write - 0x0000007F - - - CNT - Decrement counter - 0 - 7 - - - WWDTEN - Window watchdog enable - 7 - 1 - - - - - CFG - CFG - Configuration register - 0x4 - 0x20 - read-write - 0x0000007F - - - WIN - Window value - 0 - 7 - - - DIV - Clock division value - 7 - 2 - - - RLDIEN - Reload counter interrupt - 9 - 1 - - - - - STS - STS - Status register - 0x8 - 0x20 - read-write - 0x00000000 - - - RLDF - Reload counter interrupt flag - 0 - 1 - - - - - - - TMR1 - Advanced timer - TIMER - 0x40012C00 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - TMR1_CH - TMR1 channel interrupt - 27 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C4IOS - Channel 4 idle output state - 14 - 1 - - - C3CIOS - Channel 3 complementary idle output state - 13 - 1 - - - C3IOS - Channel 3 idle output state - 12 - 1 - - - C2CIOS - Channel 2 complementary idle output state - 11 - 1 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3CP - Channel 3 complementary polarity - 11 - 1 - - - C3CEN - Channel 3 complementary enable - 10 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR2 - General purpose timer - TIMER - 0x40000000 - - 0x0 - 0x400 - registers - - - TMR2 - TMR2 global interrupt - 28 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PMEN - Plus Mode Enable - 10 - 1 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 32 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 32 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 32 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 32 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 32 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 32 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR3 - General purpose timer - TIMER - 0x40000400 - - 0x0 - 0x400 - registers - - - TMR3 - TMR3 global interrupt - 29 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR4 - 0x40000800 - - TMR4 - TMR4 global interrupt - 30 - - - - TMR5 - 0x40000C00 - - TMR5 - TMR5 global interrupt - 50 - - - - TMR9 - General purpose timer - TIMER - 0x40014C00 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - - - TMR10 - General purpose timer - TIMER - 0x40015000 - - 0x0 - 0x400 - registers - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - - - TMR11 - 0x40015400 - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - - I2C1 - Inter integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1_EVT - I2C1 event interrupt - 31 - - - I2C1_ERR - I2C1 error interrupt - 32 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - RESET - I2C peripheral reset - 15 - 1 - - - SMBALERT - SMBus alert pin set - 13 - 1 - - - PECTEN - Request PEC transmission enable - 12 - 1 - - - MACKCTRL - Master receiving mode acknowledge control - 11 - 1 - - - ACKEN - Acknowledge enable - 10 - 1 - - - GENSTOP - Stop generation - 9 - 1 - - - GENSTART - Start generation - 8 - 1 - - - STRETCH - Clock stretching mode - 7 - 1 - - - GCAEN - General call address enable - 6 - 1 - - - PECEN - PEC calculation enable - 5 - 1 - - - ARPEN - SMBus address resolution protocol enable - 4 - 1 - - - SMBMODE - SMBus device mode - 3 - 1 - - - PERMODE - I2C peripheral mode - 1 - 1 - - - I2CEN - Peripheral enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - DMAEND - DMA transfer end indication - 12 - 1 - - - DMAEN - DMA transfer enable - 11 - 1 - - - DATAIEN - Data transmission interrupt enable - 10 - 1 - - - EVTIEN - Event interrupt enable - 9 - 1 - - - ERRIEN - Error interrupt enable - 8 - 1 - - - CLKFREQ - Input clock frequency - 0 - 8 - - - - - OADDR1 - OADDR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - ADDR1MODE - Address mode - 15 - 1 - - - ADDR1 - Own address 1 - 0 - 10 - - - - - OADDR2 - OADDR2 - Own address register 2 - 0xC - 0x20 - read-write - 0x0000 - - - ADDR2 - Own address 2 - 1 - 7 - - - ADDR2EN - Own address 2 enable - 0 - 1 - - - - - DT - DT - Data register - 0x10 - 0x20 - read-write - 0x0000 - - - DT - data register - 0 - 8 - - - - - STS1 - STS1 - Status register 1 - 0x14 - 0x20 - 0x0000 - - - ALERTF - SMBus alert - 15 - 1 - read-write - - - TMOUT - Timeout error - 14 - 1 - read-write - - - PECERR - PEC receive error - 12 - 1 - read-write - - - OUF - Overflow or underflow - 11 - 1 - read-write - - - ACKFAIL - Acknowledge failure - 10 - 1 - read-write - - - ARLOST - Arbitration lost (master - mode) - 9 - 1 - read-write - - - BUSERR - Bus error - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - (transmitters) - 7 - 1 - read-only - - - RDBF - Receive data buffer full - (receivers) - 6 - 1 - read-only - - - STOPF - Stop detection (slave - mode) - 4 - 1 - read-only - - - ADDRHF - address header match (Master - mode) - 3 - 1 - read-only - - - TDC - Transmit data complete - 2 - 1 - read-only - - - ADDR7F - Address sent (master mode)/matched - (slave mode) - 1 - 1 - read-only - - - STARTF - Start bit (Master mode) - 0 - 1 - read-only - - - - - STS2 - STS2 - Status register 2 - 0x18 - 0x20 - read-only - 0x0000 - - - PECVAL - PEC value - 8 - 8 - - - ADDR2F - Received address 2 - 7 - 1 - - - HOSTADDRF - SMBus host address receiving - 6 - 1 - - - DEVADDRF - SMBus device address receiving - 5 - 1 - - - GCADDRF - General call address reception - 4 - 1 - - - DIRF - Transmission direction - 2 - 1 - - - BUSYF - Bus busy - 1 - 1 - - - TRMODE - Transmission mode - 0 - 1 - - - - - CLKCTRL - CLKCTRL - Clock control register - 0x1C - 0x20 - read-write - 0x0000 - - - SPEEDMODE - Speed mode selection - 15 - 1 - - - DUTYMODE - Fast mode duty cycle - 14 - 1 - - - SPEED - I2C bus speed config - 0 - 12 - - - - - TMRISE - TMRISE - TRISE register - 0x20 - 0x20 - read-write - 0x0002 - - - RISETIME - I2C bus rise time - 0 - 6 - - - - - - - I2C2 - 0x40005800 - - I2C2_EVT - I2C2 event interrupt - 33 - - - I2C2_ERR - I2C2 error interrupt - 34 - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global interrupt - 35 - - - - CTRL1 - CTRL1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SLBEN - Single line bidirectional half-duplex enable - 15 - 1 - - - SLBTD - Single line bidirectional half-duplex transmission direction - 14 - 1 - - - CCEN - CRC calculation enable - 13 - 1 - - - NTC - Next transmission CRC - 12 - 1 - - - FBN - frame bit num - 11 - 1 - - - ORA - Only receive active - 10 - 1 - - - SWCSEN - Software CS enable - 9 - 1 - - - SWCSIL - Software CS internal level - 8 - 1 - - - LTF - LSB transmit first - 7 - 1 - - - SPIEN - SPI enable - 6 - 1 - - - MDIV2_0 - Master clock frequency division bit2-0 - 3 - 3 - - - MSTEN - Master enable - 2 - 1 - - - CLKPOL - Clock polarity - 1 - 1 - - - CLKPHA - Clock phase - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MDIV3 - Master clock frequency division bit3 - 8 - 1 - - - TDBEIE - Transmit data buffer empty interrupt enable - 7 - 1 - - - RDBFIE - Receive data buffer full interrupt enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - HWCSOE - Hardware CS output enable - 2 - 1 - - - DMATEN - DMA transmit enable - 1 - 1 - - - DMAREN - DMA receive enable - 0 - 1 - - - - - STS - STS - status register - 0x8 - 0x20 - 0x0002 - - - BF - Busy flag - 7 - 1 - read-only - - - ROERR - Receiver overflow error - 6 - 1 - read-only - - - MMERR - Master mode error - 5 - 1 - read-only - - - CCERR - CRC calculation error - 4 - 1 - read-write - - - TUERR - Transmitter underload error - 3 - 1 - read-only - - - ACS - Audio channel state - 2 - 1 - read-only - - - TDBE - Transmit data buffer empty - 1 - 1 - read-only - - - RDBF - Receive data buffer full - 0 - 1 - read-only - - - - - DT - DT - data register - 0xC - 0x20 - read-write - 0x0000 - - - DT - Data value - 0 - 16 - - - - - CPOLY - CPOLY - CRC polynomial register - 0x10 - 0x20 - read-write - 0x0007 - - - CPOLY - CRC polynomial - 0 - 16 - - - - - RCRC - RCRC - Receive CRC register - 0x14 - 0x20 - read-only - 0x0000 - - - RCRC - Receive CRC - 0 - 16 - - - - - TCRC - TCRC - Transmit CRC register - 0x18 - 0x20 - read-only - 0x0000 - - - TCRC - Transmit CRC - 0 - 16 - - - - - I2SCTRL - I2SCTRL - I2S control register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SMSEL - I2S mode select - 11 - 1 - - - I2SEN - I2S Enable - 10 - 1 - - - OPERSEL - I2S operation select - 8 - 2 - - - PCMFSSEL - PCM frame synchronization select - 7 - 1 - - - STDSEL - I2S standard select - 4 - 2 - - - I2SCLKPOL - I2S clock polarity - 3 - 1 - - - I2SDBN - I2S data bit num - 1 - 2 - - - I2SCBN - I2S channel bit num - 0 - 1 - - - - - I2SCLK - I2SCLK - I2S clock register - 0x20 - 0x20 - read-write - 00000010 - - - I2SDIV9_8 - I2S division bit9 and bit8 - 10 - 2 - - - I2SMCLKOE - I2S master clock output enable - 9 - 1 - - - I2SODD - Odd result for I2S division - 8 - 1 - - - I2SDIV7_0 - I2S division bit7 to bit0 - 0 - 8 - - - - - - - SPI2 - 0x40003800 - - SPI2 - SPI2 global interrupt - 36 - - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40013800 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global interrupt - 37 - - - - STS - STS - Status register - 0x0 - 0x20 - 0x00C0 - - - CTSCF - CTS change flag - 9 - 1 - read-write - - - BFF - Break frame flag - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - 7 - 1 - read-only - - - TDC - Transmit data complete - 6 - 1 - read-write - - - RDBF - Receive data buffer full - 5 - 1 - read-write - - - IDLEF - IDLE flag - 4 - 1 - read-only - - - ROERR - Receiver overflow error - 3 - 1 - read-only - - - NERR - Noise error - 2 - 1 - read-only - - - FERR - Framing error - 1 - 1 - read-only - - - PERR - Parity error - 0 - 1 - read-only - - - - - DT - DT - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DT - Data value - 0 - 9 - - - - - BAUDR - BAUDR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV - Division - 0 - 16 - - - - - CTRL1 - CTRL1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - UEN - USART enable - 13 - 1 - - - DBN - Data bit num - 12 - 1 - - - WUM - Wake up mode - 11 - 1 - - - PEN - Parity enable - 10 - 1 - - - PSEL - Parity selection - 9 - 1 - - - PERRIEN - PERR interrupt enable - 8 - 1 - - - TDBEIEN - TDBE interrupt enable - 7 - 1 - - - TDCIEN - TDC interrupt enable - 6 - 1 - - - RDBFIEN - RDBF interrupt enable - 5 - 1 - - - IDLEIEN - IDLE interrupt enable - 4 - 1 - - - TEN - Transmitter enable - 3 - 1 - - - REN - Receiver enable - 2 - 1 - - - RM - Receiver mute - 1 - 1 - - - SBF - Send break frame - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - LINEN - LIN mode enable - 14 - 1 - - - STOPBN - STOP bit num - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CLKPOL - Clock polarity - 10 - 1 - - - CLKPHA - Clock phase - 9 - 1 - - - LBCP - Last bit clock pulse - 8 - 1 - - - BFIEN - Break frame interrupt enable - 6 - 1 - - - BFBN - Break frame bit num - 5 - 1 - - - ID - USART identification - 0 - 4 - - - - - CTRL3 - CTRL3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - CTSCFIEN - CTSCF interrupt enable - 10 - 1 - - - CTSEN - CTS enable - 9 - 1 - - - RTSEN - RTS enable - 8 - 1 - - - DMATEN - DMA transmitter enable - 7 - 1 - - - DMAREN - DMA receiver enable - 6 - 1 - - - SCMEN - Smartcard mode enable - 5 - 1 - - - SCNACKEN - Smartcard NACK enable - 4 - 1 - - - SLBEN - Single line bidirectional half-duplex enable - 3 - 1 - - - IRDALP - IrDA low-power mode - 2 - 1 - - - IRDAEN - IrDA enable - 1 - 1 - - - ERRIEN - Error interrupt enable - 0 - 1 - - - - - GDIV - GDIV - Guard time and division register - 0x18 - 0x20 - read-write - 0x0000 - - - SCGT - Smart card guard time value - 8 - 8 - - - ISDIV - IrDA/smartcard division value - 0 - 8 - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global interrupt - 38 - - - - USART3 - 0x40004800 - - USART3 - USART3 global interrupt - 39 - - - - ADC1 - Analog to digital converter - ADC1 - 0x40012400 - - 0x0 - 0x400 - registers - - - ADC1 - ADC1 global interrupt - 18 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - CCE - Channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - CCEIEN - Channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - OCTESEL_H - High bit of trigger event select for ordinary channels conversion - 25 - 1 - - - PCTESEL_H - High bit of trigger event select for preempted channels conversion - 24 - 1 - - - ITSRVEN - Internal temperature sensor and VINTRV enable - 23 - 1 - - - OCSWTRG - Conversion trigger by software of ordinary channels - 22 - 1 - - - PCSWTRG - Conversion trigger by software of preempted channels - 21 - 1 - - - OCTEN - Trigger mode enable for ordinary channels conversion - 20 - 1 - - - OCTESEL_L - Low bit of trigger event select for ordinary channels conversion - 17 - 3 - - - PCTEN - Trigger mode enable for preempted channels conversion - 15 - 1 - - - PCTESEL_L - Low bit of trigger event select for preempted channels conversion - 12 - 3 - - - DTALIGN - Data alignment - 11 - 1 - - - OCDMAEN - DMA transfer enable of ordinary channels - 8 - 1 - - - ADCALINIT - initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 12 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 12 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 4 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - - - CAN1 - Can controller area network - CAN - 0x40006400 - - 0x0 - 0x400 - registers - - - CAN1_TX - CAN1 TX interrupt - 19 - - - CAN1_RX0 - CAN1 RX0 interrupt - 20 - - - CAN1_RX1 - CAN1 RX1 interrupt - 21 - - - CAN1_SE - CAN1 SE interrupt - 22 - - - - MCTRL - MCTRL - Main control register - 0x0 - 0x20 - read-write - 0x00010002 - - - PTD - Prohibit transmission when debug - 16 - 1 - - - SPRST - Software partial reset - 15 - 1 - - - TTCEN - Time triggered communication mode enable - 7 - 1 - - - AEBOEN - Automatic exit bus-off enable - 6 - 1 - - - AEDEN - Automatic exit doze mode enable - 5 - 1 - - - PRSFEN - Prohibit retransmission when sending fails enable - 4 - 1 - - - MDRSEL - Message discarding rule select when overflow - 3 - 1 - - - MMSSR - Multiple message sending sequence rule - 2 - 1 - - - DZEN - Doze mode enable - 1 - 1 - - - FZEN - Freeze mode enable - 0 - 1 - - - - - MSTS - MSTS - Main status register - 0x4 - 0x20 - 0x00000C02 - - - REALRX - Real time level of RX pin - 11 - 1 - read-only - - - LSAMPRX - Last sample level of RX pin - 10 - 1 - read-only - - - CURS - Currently receiving status - 9 - 1 - read-only - - - CUSS - Currently sending status - 8 - 1 - read-only - - - EDZIF - Enter doze mode interrupt flag - 4 - 1 - read-write - - - QDZIF - Quit doze mode interrupt flag - 3 - 1 - read-write - - - EOIF - Error occur Interrupt flag - 2 - 1 - read-write - - - DZC - Doze mode confirm - 1 - 1 - read-only - - - FZC - Freeze mode confirm - 0 - 1 - read-only - - - - - TSTS - TSTS - Transmit status register - 0x8 - 0x20 - 0x1C000000 - - - TM2LPF - Transmit mailbox 2 lowest priority flag - 31 - 1 - read-only - - - TM1LPF - Transmit mailbox 1 lowest priority flag - 30 - 1 - read-only - - - TM0LPF - Transmit mailbox 0 lowest priority flag - 29 - 1 - read-only - - - TM2EF - Transmit mailbox 2 empty flag - 28 - 1 - read-only - - - TM1EF - Transmit mailbox 1 empty flag - 27 - 1 - read-only - - - TM0EF - Transmit mailbox 0 empty flag - 26 - 1 - read-only - - - TMNR - Transmit Mailbox number record - 24 - 2 - read-only - - - TM2CT - Transmit mailbox 2 cancel transmission - 23 - 1 - read-write - - - TM2TEF - Transmit mailbox 2 transmission error flag - 19 - 1 - read-write - - - TM2ALF - Transmit mailbox 2 arbitration lost flag - 18 - 1 - read-write - - - TM2TSF - Transmit mailbox 2 transmission success flag - 17 - 1 - read-write - - - TM2TCF - transmit mailbox 2 transmission complete flag - 16 - 1 - read-write - - - TM1CT - Transmit mailbox 1 cancel transmission - 15 - 1 - read-write - - - TM1TEF - Transmit mailbox 1 transmission error flag - 11 - 1 - read-write - - - TM1ALF - Transmit mailbox 1 arbitration lost flag - 10 - 1 - read-write - - - TM1TSF - Transmit mailbox 1 transmission success flag - 9 - 1 - read-write - - - TM1TCF - Transmit mailbox 1 transmission complete flag - 8 - 1 - read-write - - - TM0CT - Transmit mailbox 0 cancel transmission - 7 - 1 - read-write - - - TM0TEF - Transmit mailbox 0 transmission error flag - 3 - 1 - read-write - - - TM0ALF - Transmit mailbox 0 arbitration lost flag - 2 - 1 - read-write - - - TM0TSF - Transmit mailbox 0 transmission success flag - 1 - 1 - read-write - - - TM0TCF - Transmit mailbox 0 transmission complete flag - 0 - 1 - read-write - - - - - RF0 - RF0 - Receive FIFO 0 register - 0xC - 0x20 - 0x00000000 - - - RF0R - Receive FIFO 0 release - 5 - 1 - read-write - - - RF0OF - Receive FIFO 0 overflow flag - 4 - 1 - read-write - - - RF0FF - Receive FIFO 0 full flag - 3 - 1 - read-write - - - RF0MN - Receive FIFO 0 message num - 0 - 2 - read-only - - - - - RF1 - RF1 - Receive FIFO 1 register - 0x10 - 0x20 - 0x00000000 - - - RF1R - Receive FIFO 1 release - 5 - 1 - read-write - - - RF1OF - Receive FIFO 1 overflow flag - 4 - 1 - read-write - - - RF1FF - Receive FIFO 1 full flag - 3 - 1 - read-write - - - RF1MN - Receive FIFO 1 message num - 0 - 2 - read-only - - - - - INTEN - INTEN - Interrupt enable register - 0x14 - 0x20 - read-write - 0x00000000 - - - EDZIEN - Enter doze mode interrupt enable - 17 - 1 - - - QDZIEN - Quit doze mode interrupt enable - 16 - 1 - - - EOIEN - Error occur interrupt enable - 15 - 1 - - - ETRIEN - Error type record interrupt enable - 11 - 1 - - - BOIEN - Bus-off interrupt enable - 10 - 1 - - - EPIEN - Error passive interrupt enable - 9 - 1 - - - EAIEN - Error active interrupt enable - 8 - 1 - - - RF1OIEN - Receive FIFO 1 overflow interrupt enable - 6 - 1 - - - RF1FIEN - Receive FIFO 1 full interrupt enable - 5 - 1 - - - RF1MIEN - FIFO 1 receive message interrupt enable - 4 - 1 - - - RF0OIEN - Receive FIFO 0 overflow interrupt enable - 3 - 1 - - - RF0FIEN - Receive FIFO 0 full interrupt enable - 2 - 1 - - - RF0MIEN - FIFO 0 receive message interrupt enable - 1 - 1 - - - TCIEN - Transmission complete interrupt enable - 0 - 1 - - - - - ESTS - ESTS - Error status register - 0x18 - 0x20 - 0x00000000 - - - REC - Receive error counter - 24 - 8 - read-only - - - TEC - Transmit error counter - 16 - 8 - read-only - - - ETR - Error type record - 4 - 3 - read-write - - - BOF - Bus-off flag - 2 - 1 - read-only - - - EPF - Error passive flag - 1 - 1 - read-only - - - EAF - Error active flag - 0 - 1 - read-only - - - - - BTMG - BTMG - Bit timing register - 0x1C - 0x20 - read-write - 0x00000000 - - - LOEN - Listen-Only mode - 31 - 1 - - - LBEN - Loop back mode - 30 - 1 - - - RSAW - Resynchronization adjust width - 24 - 2 - - - BTS2 - Bit time segment 2 - 20 - 3 - - - BTS1 - Bit time segment 1 - 16 - 4 - - - BRDIV - Baud rate division - 0 - 12 - - - - - TMI0 - TMI0 - Transmit mailbox 0 identifier register - 0x180 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC0 - TMC0 - Transmit mailbox 0 data length and time stamp register - 0x184 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL0 - TMDTL0 - Transmit mailbox 0 low byte data register - 0x188 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH0 - TMDTH0 - Transmit mailbox 0 high byte data register - 0x18C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI1 - TMI1 - Transmit mailbox 1 identifier register - 0x190 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC1 - TMC1 - Transmit mailbox 1 data length and time stamp register - 0x194 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL1 - TMDTL1 - Transmit mailbox 1 low byte data register - 0x198 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH1 - TMDTH1 - Transmit mailbox 1 high byte data register - 0x19C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI2 - TMI2 - Transmit mailbox 2 identifier register - 0x1A0 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC2 - TMC2 - Transmit mailbox 2 data length and time stamp register - 0x1A4 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL2 - TMDTL2 - Transmit mailbox 2 low byte data register - 0x1A8 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH2 - TMDTH2 - Transmit mailbox 2 high byte data register - 0x1AC - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - RFI0 - RFI0 - Receive FIFO 0 register - 0x1B0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC0 - RFC0 - Receive FIFO 0 data length and time stamp register - 0x1B4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL0 - RFDTL0 - Receive FIFO 0 low byte data register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH0 - RFDTH0 - Receive FIFO 0 high byte data register - 0x1BC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - RFI1 - RFI1 - Receive FIFO 1 register - 0x1C0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC1 - RFC1 - Receive FIFO 1 data length and time stamp register - 0x1C4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL1 - RFDTL1 - Receive FIFO 1 low byte data register - 0x1C8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH1 - RFDTH1 - Receive FIFO 1 high byte data register - 0x1CC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - FCTRL - FCTRL - Filter control register - 0x200 - 0x20 - read-write - 0x00000000 - - - FCS - Filters configure switch - 0 - 1 - - - - - FMCFG - FMCFG - Filter mode config register - 0x204 - 0x20 - read-write - 0x00000000 - - - FMSEL0 - Filter mode select - 0 - 1 - - - FMSEL1 - Filter mode select - 1 - 1 - - - FMSEL2 - Filter mode select - 2 - 1 - - - FMSEL3 - Filter mode select - 3 - 1 - - - FMSEL4 - Filter mode select - 4 - 1 - - - FMSEL5 - Filter mode select - 5 - 1 - - - FMSEL6 - Filter mode select - 6 - 1 - - - FMSEL7 - Filter mode select - 7 - 1 - - - FMSEL8 - Filter mode select - 8 - 1 - - - FMSEL9 - Filter mode select - 9 - 1 - - - FMSEL10 - Filter mode select - 10 - 1 - - - FMSEL11 - Filter mode select - 11 - 1 - - - FMSEL12 - Filter mode select - 12 - 1 - - - FMSEL13 - Filter mode select - 13 - 1 - - - - - FBWCFG - FBWCFG - Filter bit width config register - 0x20C - 0x20 - read-write - 0x00000000 - - - FBWSEL0 - Filter bit width select - 0 - 1 - - - FBWSEL1 - Filter bit width select - 1 - 1 - - - FBWSEL2 - Filter bit width select - 2 - 1 - - - FBWSEL3 - Filter bit width select - 3 - 1 - - - FBWSEL4 - Filter bit width select - 4 - 1 - - - FBWSEL5 - Filter bit width select - 5 - 1 - - - FBWSEL6 - Filter bit width select - 6 - 1 - - - FBWSEL7 - Filter bit width select - 7 - 1 - - - FBWSEL8 - Filter bit width select - 8 - 1 - - - FBWSEL9 - Filter bit width select - 9 - 1 - - - FBWSEL10 - Filter bit width select - 10 - 1 - - - FBWSEL11 - Filter bit width select - 11 - 1 - - - FBWSEL12 - Filter bit width select - 12 - 1 - - - FBWSEL13 - Filter bit width select - 13 - 1 - - - - - FRF - FRF - Filter related FIFO register - 0x214 - 0x20 - read-write - 0x00000000 - - - FRFSEL0 - Filter relation FIFO select - 0 - 1 - - - FRFSEL1 - Filter relation FIFO select - 1 - 1 - - - FRFSEL2 - Filter relation FIFO select - 2 - 1 - - - FRFSEL3 - Filter relation FIFO select - 3 - 1 - - - FRFSEL4 - Filter relation FIFO select - 4 - 1 - - - FRFSEL5 - Filter relation FIFO select - 5 - 1 - - - FRFSEL6 - Filter relation FIFO select - 6 - 1 - - - FRFSEL7 - Filter relation FIFO select - 7 - 1 - - - FRFSEL8 - Filter relation FIFO select - 8 - 1 - - - FRFSEL9 - Filter relation FIFO select - 9 - 1 - - - FRFSEL10 - Filter relation FIFO select - 10 - 1 - - - FRFSEL11 - Filter relation FIFO select - 11 - 1 - - - FRFSEL12 - Filter relation FIFO select - 12 - 1 - - - FRFSEL13 - Filter relation FIFO select - 13 - 1 - - - - - FACFG - FACFG - Filter activate configuration register - 0x21C - 0x20 - read-write - 0x00000000 - - - FAEN0 - Filter activate enable - 0 - 1 - - - FAEN1 - Filter activate enable - 1 - 1 - - - FAEN2 - Filter activate enable - 2 - 1 - - - FAEN3 - Filter activate enable - 3 - 1 - - - FAEN4 - Filter activate enable - 4 - 1 - - - FAEN5 - Filter activate enable - 5 - 1 - - - FAEN6 - Filter activate enable - 6 - 1 - - - FAEN7 - Filter activate enable - 7 - 1 - - - FAEN8 - Filter activate enable - 8 - 1 - - - FAEN9 - Filter activate enable - 9 - 1 - - - FAEN10 - Filter activate enable - 10 - 1 - - - FAEN11 - Filter activate enable - 11 - 1 - - - FAEN12 - Filter activate enable - 12 - 1 - - - FAEN13 - Filter activate enable - 13 - 1 - - - - - F0FB1 - F0FB1 - Filter bank 0 filtrate bit register 1 - 0x240 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F0FB2 - F0FB2 - Filter bank 0 filtrate bit register 2 - 0x244 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB1 - F1FB1 - Filter bank 1 filtrate bit register 1 - 0x248 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB2 - F1FB2 - Filter bank 1 filtrate bit register 2 - 0x24C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB1 - F2FB1 - Filter bank 2 filtrate bit register 1 - 0x250 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB2 - F2FB2 - Filter bank 2 filtrate bit register 2 - 0x254 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB1 - F3FB1 - Filter bank 3 filtrate bit register 1 - 0x258 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB2 - F3FB2 - Filter bank 3 filtrate bit register 2 - 0x25C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB1 - F4FB1 - Filter bank 4 filtrate bit register 1 - 0x260 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB2 - F4FB2 - Filter bank 4 filtrate bit register 2 - 0x264 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB1 - F5FB1 - Filter bank 5 filtrate bit register 1 - 0x268 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB2 - F5FB2 - Filter bank 5 filtrate bit register 2 - 0x26C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB1 - F6FB1 - Filter bank 6 filtrate bit register 1 - 0x270 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB2 - F6FB2 - Filter bank 6 filtrate bit register 2 - 0x274 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB1 - F7FB1 - Filter bank 7 filtrate bit register 1 - 0x278 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB2 - F7FB2 - Filter bank 7 filtrate bit register 2 - 0x27C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB1 - F8FB1 - Filter bank 8 filtrate bit filtrate bit register 1 - 0x280 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB2 - F8FB2 - Filter bank 8 filtrate bit filtrate bit register 2 - 0x284 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB1 - F9FB1 - Filter bank 9 filtrate bit filtrate bit filtrate bit filtrate bit filtrate bit register 1 - 0x288 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB2 - F9FB2 - Filter bank 9 filtrate bit filtrate bit filtrate bit filtrate bit filtrate bit register 2 - 0x28C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB1 - F10FB1 - Filter bank 10 filtrate bit register 1 - 0x290 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB2 - F10FB2 - Filter bank 10 filtrate bit register 2 - 0x294 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB1 - F11FB1 - Filter bank 11 filtrate bit register 1 - 0x298 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB2 - F11FB2 - Filter bank 11 filtrate bit register 2 - 0x29C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB1 - F12FB1 - Filter bank 12 filtrate bit filtrate bit register 1 - 0x2A0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB2 - F12FB2 - Filter bank 12 filtrate bit filtrate bit register 2 - 0x2A4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB1 - F13FB1 - Filter bank 13 filtrate bit filtrate bit register 1 - 0x2A8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB2 - F13FB2 - Filter bank 13 filtrate bit filtrate bit register 2 - 0x2AC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - - CMP - Comparator - CMP - 0x40002400 - - 0x0 - 0x3FF - registers - - - CMP1 - CMP1 interrupt - 70 - - - CMP2 - CMP2 interrupt - 71 - - - - CTRLSTS1 - CTRLSTS1 - CMP control/status register1 - 0x0 - 0x20 - 0x00000000 - - - CMP1EN - Comparator1 enable bit - 0 - 1 - read-write - - - CMP1IS - Comparator1 input shift - 1 - 1 - read-write - - - CMP1SSEL - Comparator1 speed selection - 2 - 2 - read-write - - - CMP1INVSEL - Comparator1 inverting selection - 4 - 3 - read-write - - - CMP1TAG - Comparator1 output target - 8 - 3 - read-write - - - CMP1P - Comparator1 polarity - 11 - 1 - read-write - - - CMP1HYST - Comparator1 hysteresis - 12 - 2 - read-write - - - CMP1VALUE - Comparator1 output value - 14 - 1 - read-only - - - CMP1WP - Comparator1 write protect - 15 - 1 - read-write - - - CMP2EN - Comparator2 enable bit - 16 - 1 - read-write - - - CMP2SSEL - Comparator2 speed selection - 18 - 2 - read-write - - - CMP2INVSEL - Comparator2 inverting selection - 20 - 3 - read-write - - - DCMPEN - Double comparator mode enable - 23 - 1 - read-write - - - CMP2TAG - Comparator2 output target - 24 - 3 - read-write - - - CMP2P - Comparator2 polarity - 27 - 1 - read-write - - - CMP2HYST - Comparator2 hysteresis - 28 - 2 - read-write - - - CMP2VALUE - Comparator2 output value - 30 - 1 - read-only - - - CMP2WP - Comparator2 write protect - 31 - 1 - read-write - - - - - CTRLSTS2 - CTRLSTS2 - CMP control/status register2 - 0x4 - 0x20 - 0x00000000 - - - COMP1NINVSEL - Comparator1 non-inverting input selection - 0 - 2 - read-write - - - COMP2NINVSEL - Comparator2 non-inverting input selection - 16 - 2 - read-write - - - - - - - DEBUG - Debug support - DEBUG - 0xE0042000 - - 0x0 - 0x400 - registers - - - - DEBUG_IDCODE - DEBUG_IDCODE - DEBUG IDCODE - 0x0 - 0x20 - read-only - 0x0 - - - PID - PID - 0 - 32 - - - - - CTRL - CTRL - MCUDBG_CTRL - 0x4 - 0x20 - read-write - 0x0 - - - SLEEP_DEBUG - SLEEP_DEBUG - 0 - 1 - - - DEEPSLEEP_DEBUG - DEEPSLEEP_DEBUG - 1 - 1 - - - STANDBY_DEBUG - STANDBY_DEBUG - 2 - 1 - - - TRACE_IOEN - TRACE_IOEN - 5 - 1 - - - TRACE_MODE - TRACE_MODE - 6 - 2 - - - WDT_PAUSE - WDT_PAUSE - 8 - 1 - - - WWDT_PAUSE - WWDT_PAUSE - 9 - 1 - - - TMR1_PAUSE - TMR1_PAUSE - 10 - 1 - - - TMR2_PAUSE - TMR2_PAUSE - 11 - 1 - - - TMR3_PAUSE - TMR3_PAUSE - 12 - 1 - - - TMR4_PAUSE - TMR4_PAUSE - 13 - 1 - - - CAN1_PAUSE - CAN1_PAUSE - 14 - 1 - - - I2C1_SMBUS_TIMEOUT - I2C1_SMBUS_TIMEOUT - 15 - 1 - - - I2C2_SMBUS_TIMEOUT - I2C2_SMBUS_TIMEOUT - 16 - 1 - - - TMR5_PAUSE - TMR5_PAUSE - 18 - 1 - - - TMR9_PAUSE - TMR9_PAUSE - 28 - 1 - - - TMR10_PAUSE - TMR10_PAUSE - 29 - 1 - - - TMR11_PAUSE - TMR11_PAUSE - 30 - 1 - - - - - - - UART4 - Universal asynchronous receiver transmitter - 0x40004C00 - - UART4 - UART4 global interrupt - 52 - - - - UART5 - Universal asynchronous receiver transmitter - 0x40005000 - - UART5 - UART5 global interrupt - 53 - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DT - DT - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DT - Data Register - 0 - 32 - - - - - CDT - CDT - Common data register - 0x4 - 0x20 - read-write - 0x00000000 - - - CDT - Common Data - 0 - 1 - - - - - CTRL - CTRL - Control register - 0x8 - 0x20 - read-write - 0x00000000 - - - RST - Reset bit - 0 - 1 - - - REVID - Reverse input data - 5 - 2 - - - REVOD - Reverse output data - 7 - 1 - - - - - IDT - IDT - Initial data register - 0x10 - 0x20 - read-write - 0xFFFFFFFF - - - IDT - Initial Data - 0 - 32 - - - - - - - FLASH - Flash memory controler - FLASH - 0x40022000 - - 0x0 - 0x400 - registers - - - FLASH - Flash global interrupt - 4 - - - - PSR - PSR - Performance selection register - 0x0 - 0x20 - 0x00000030 - - - WTCYC - Wait cycle - 0 - 3 - read-write - - - HFCYC_EN - Half cycle acceleration access enable - 3 - 1 - read-write - - - PFT_EN - Prefetch enable - 4 - 1 - read-write - - - PFT_ENF - Prefetch enabled flag - 5 - 1 - read-only - - - - - UNLOCK - UNLOCK - Unlock register - 0x4 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - USD_UNLOCK - USD_UNLOCK - USD unlock register - 0x8 - 0x20 - write-only - 0x00000000 - - - USD_UKVAL - User system data Unlock key value - 0 - 32 - - - - - STS - STS - Status register - 0xC - 0x20 - 0x00000000 - - - ODF - Operate done flag - 5 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - PRGMERR - program error - 2 - 1 - read-write - - - OBF - Operate busy flag - 0 - 1 - read-only - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - USDPRGM - User system data program - 4 - 1 - - - USDERS - User system data erase - 5 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - USDULKS - User system data unlock success - 9 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - FAP_HL_DIS - FAP high level disable - 16 - 1 - - - - - ADDR - ADDR - Address register - 0x14 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - USD - USD - User system data register - 0x1C - 0x20 - read-only - 0x03FFFFFC - - - USDERR - User system data error - 0 - 1 - - - FAP - FLASH access protection - 1 - 1 - - - nWDT_ATO_EN - WDT auto enable - 2 - 1 - - - nDEPSLP_RST - Deepsleep reset - 3 - 1 - - - nSTDBY_RST - Standby reset - 4 - 1 - - - USER_D0 - User data 0 - 10 - 8 - - - USER_D1 - User data 1 - 18 - 8 - - - FAP_HL - FAP high level - 26 - 1 - - - - - EPPS - EPPS - Erase/program protection status register - 0x20 - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - SLIB_STS0 - SLIB_STS0 - sLib status 0 register - 0x74 - 0x20 - read-only - 0x00000000 - - - BTM_AP_ENF - Boot memory store application code enabled flag - 0 - 1 - - - EM_SLIB_ENF - Extension memory sLib enabled flag - 2 - 1 - - - SLIB_ENF - sLib enabled flag - 3 - 1 - - - EM_SLIB_DAT_SS - Extension memory sLib data start sector - 16 - 8 - - - - - SLIB_STS1 - SLIB_STS1 - sLib status 1 register - 0x78 - 0x20 - read-only - 0xFFFFFFFF - - - SLIB_SS - sLib start sector - 0 - 11 - - - SLIB_DAT_SS - sLib data start sector - 11 - 11 - - - SLIB_ES - sLib end sector - 22 - 10 - - - - - SLIB_PWD_CLR - SLIB_PWD_CLR - SLIB password clear register - 0x7C - 0x20 - 0x00000000 - write-only - - - SLIB_PCLR_VAL - sLib password clear value - 0 - 32 - - - - - SLIB_MISC_STS - SLIB_MISC_STS - sLib misc status register - 0x80 - 0x20 - 0x00000000 - - - SLIB_PWD_ERR - sLib password error - 0 - 1 - read-only - - - SLIB_PWD_OK - sLib password ok - 1 - 1 - read-only - - - SLIB_ULKF - sLib unlock flag - 2 - 1 - read-only - - - - - CRC_ADDR - CRC_ADDR - Flash CRC data start address register - 0x84 - 0x20 - write-only - 0x00000000 - - - CRC_ADDR - CRC address - 0 - 32 - - - - - CRC_CTRL - CRC_CTRL - Flash CRC controll register - 0x88 - 0x20 - 0x00000000 - - - CRC_SN - CRC sector numbler - 0 - 16 - read-write - - - CRC_STRT - CRC start - 16 - 1 - write-only - - - - - CRC_CHKR - CRC_CHKR - FLASH CRC check result register - 0x8C - 0x20 - read-only - 0x00000000 - - - FCRC_OUT - CRC32 verification result of flash user code or SLIB code - 0 - 32 - - - - - SLIB_SET_PWD - SLIB_SET_PWD - sLib password setting register - 0x160 - 0x20 - write-only - 0x00000000 - - - SLIB_PSET_VAL - sLib password setting val - 0 - 32 - - - - - SLIB_SET_RANGE - SLIB_SET_RANGE - Configure sLib range register - 0x164 - 0x20 - write-only - 0x00000000 - - - SLIB_SS_SET - sLib start sector setting - 0 - 11 - - - SLIB_DSS_SET - sLib data start sector setting - 11 - 11 - - - SLIB_ES_SET - sLib end sector setting - 22 - 10 - - - - - EM_SLIB_SET - EM_SLIB_SET - Extension momery slib set register - 0x168 - 0x20 - write-only - 0x00000000 - - - EM_SLIB_SET - Extension memory sLib setting - 0 - 16 - - - EM_SLIB_DSS_SET - Extension memory sLib data start sector setting - 16 - 8 - - - - - BTM_MODE_SET - BTM_MODE_SET - Boot memory mode setting register - 0x16C - 0x20 - write-only - 0x00000000 - - - BTM_MODE_SET - Boot memory mode setting - 0 - 8 - - - - - SLIB_UNLOCK - SLIB_UNLOCK - sLib unlock register - 0x170 - 0x20 - write-only - 0x00000000 - - - SLIB_UKVAL - sLib unlock key value - 0 - 32 - - - - - - - NVIC - Nested Vectored Interrupt - Controller - NVIC - 0xE000E000 - - 0x0 - 0x1001 - registers - - - - ICTR - ICTR - Interrupt Controller Type - Register - 0x4 - 0x20 - read-only - 0x00000000 - - - INTLINESNUM - Total number of interrupt lines in - groups - 0 - 4 - - - - - STIR - STIR - Software Triggered Interrupt - Register - 0xF00 - 0x20 - write-only - 0x00000000 - - - INTID - interrupt to be triggered - 0 - 9 - - - - - ISER0 - ISER0 - Interrupt Set-Enable Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER1 - ISER1 - Interrupt Set-Enable Register - 0x104 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ICER0 - ICER0 - Interrupt Clear-Enable - Register - 0x180 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear-Enable - Register - 0x184 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x200 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x204 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending - Register - 0x280 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending - Register - 0x284 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - IABR0 - IABR0 - Interrupt Active Bit Register - 0x300 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IABR1 - IABR1 - Interrupt Active Bit Register - 0x304 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IPR0 - IPR0 - Interrupt Priority Register - 0x400 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR1 - IPR1 - Interrupt Priority Register - 0x404 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR2 - IPR2 - Interrupt Priority Register - 0x408 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR3 - IPR3 - Interrupt Priority Register - 0x40C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR4 - IPR4 - Interrupt Priority Register - 0x410 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR5 - IPR5 - Interrupt Priority Register - 0x414 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR6 - IPR6 - Interrupt Priority Register - 0x418 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR7 - IPR7 - Interrupt Priority Register - 0x41C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR8 - IPR8 - Interrupt Priority Register - 0x420 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR9 - IPR9 - Interrupt Priority Register - 0x424 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR10 - IPR10 - Interrupt Priority Register - 0x428 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR11 - IPR11 - Interrupt Priority Register - 0x42C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR12 - IPR12 - Interrupt Priority Register - 0x430 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR13 - IPR13 - Interrupt Priority Register - 0x434 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR14 - IPR14 - Interrupt Priority Register - 0x438 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - - - USB_OTG_GLOBAL - USB on the go full speed - USB_OTG - 0x50000000 - - 0x0 - 0x400 - registers - - - OTGFS - USB On The Go FS global - interrupt - 77 - - - - GOTGCTL - GOTGCTL - OTGFS control and status register - (OTGFS_GOTGCTL) - 0x0 - 0x20 - 0x00000800 - - - CONIDSTS - Connector ID status - 16 - 1 - read-only - - - CURMOD - Current Mode of Operation - 21 - 1 - read-only - - - - - GOTGINT - GOTGINT - OTGFS interrupt register - (OTGFS_GOTGINT) - 0x4 - 0x20 - 0x00000000 - - - SESENDDET - VBUS is deasserted - 2 - 1 - read-write - - - - - GAHBCFG - GAHBCFG - OTGFS AHB configuration register - (OTGFS_GAHBCFG) - 0x8 - 0x20 - read-write - 0x00000000 - - - GLBINTMSK - Global interrupt mask - 0 - 1 - - - NPTXFEMPLVL - Non-Periodic TxFIFO empty level - 7 - 1 - - - PTXFEMPLVL - Periodic TxFIFO empty - level - 8 - 1 - - - - - GUSBCFG - GUSBCFG - USB configuration register - (OTGFS_GUSBCFG) - 0xC - 0x20 - 0x00000A00 - - - TOUTCAL - FS timeout calibration - 0 - 3 - read-write - - - USBTRDTIM - USB turnaround time - 10 - 4 - read-write - - - FHSTMODE - Force host mode - 29 - 1 - read-write - - - FDEVMODE - Force device mode - 30 - 1 - read-write - - - COTXPKT - Corrupt Tx packet - 31 - 1 - read-write - - - - - GRSTCTL - GRSTCTL - OTGFS reset register - (OTGFS_GRSTCTL) - 0x10 - 0x20 - 0x20000000 - - - CSFTRST - Core soft reset - 0 - 1 - read-write - - - PIUSFTRST - PIU FS Dedicated Controller Soft Reset - 1 - 1 - read-write - - - FRMCNTRST - Host frame counter reset - 2 - 1 - read-write - - - RXFFLSH - RxFIFO flush - 4 - 1 - read-write - - - TXFFLSH - TxFIFO flush - 5 - 1 - read-write - - - TXFNUM - TxFIFO number - 6 - 5 - read-write - - - AHBIDLE - AHB master idle - 31 - 1 - read-only - - - - - GINTSTS - GINTSTS - OTGFS core interrupt register - (OTGFS_GINTSTS) - 0x14 - 0x20 - 0x04000020 - - - CURMOD - Current mode of operation - 0 - 1 - read-only - - - MODEMIS - Mode mismatch interrupt - 1 - 1 - read-write - - - OTGINT - OTG interrupt - 2 - 1 - read-only - - - SOF - Start of frame - 3 - 1 - read-write - - - RXFLVL - RxFIFO non-empty - 4 - 1 - read-only - - - NPTXFEMP - Non-periodic TxFIFO empty - 5 - 1 - read-only - - - GINNAKEFF - Global IN non-periodic NAK - effective - 6 - 1 - read-only - - - GOUTNAKEFF - Global OUT NAK effective - 7 - 1 - read-only - - - ERLYSUSP - Early suspend - 10 - 1 - read-write - - - USBSUSP - USB suspend - 11 - 1 - read-write - - - USBRST - USB reset - 12 - 1 - read-write - - - ENUMDONE - Enumeration done - 13 - 1 - read-write - - - ISOOUTDROP - Isochronous OUT packet dropped - interrupt - 14 - 1 - read-write - - - EOPF - End of periodic frame - interrupt - 15 - 1 - read-write - - - IEPTINT - IN endpoint interrupt - 18 - 1 - read-only - - - OEPTINT - OUT endpoint interrupt - 19 - 1 - read-only - - - INCOMPISOIN - Incomplete isochronous IN - transfer - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUT - Incomplete periodic transfer(Host - mode)/Incomplete isochronous OUT transfer(Device - mode) - 21 - 1 - read-write - - - PRTINT - Host port interrupt - 24 - 1 - read-only - - - HCHINT - Host channels interrupt - 25 - 1 - read-only - - - PTXFEMP - Periodic TxFIFO empty - 26 - 1 - read-only - - - CONIDSCHG - Connector ID status change - 28 - 1 - read-write - - - DISCONINT - Disconnect detected - interrupt - 29 - 1 - read-write - - - WKUPINT - Resume/remote wakeup detected - interrupt - 31 - 1 - read-write - - - - - GINTMSK - GINTMSK - OTG_FS interrupt mask register - (OTG_FS_GINTMSK) - 0x18 - 0x20 - 0x00000000 - - - MODEMISMSK - Mode mismatch interrupt - mask - 1 - 1 - read-write - - - OTGINTMSK - OTG interrupt mask - 2 - 1 - read-write - - - SOFMSK - Start of frame mask - 3 - 1 - read-write - - - RXFLVLMSK - Receive FIFO non-empty - mask - 4 - 1 - read-write - - - NPTXFEMPMSK - Non-periodic TxFIFO empty - mask - 5 - 1 - read-write - - - GINNAKEFFMSK - Global non-periodic IN NAK effective - mask - 6 - 1 - read-write - - - GOUTNAKEFFMSK - Global OUT NAK effective - mask - 7 - 1 - read-write - - - ERLYSUSPMSK - Early suspend mask - 10 - 1 - read-write - - - USBSUSPMSK - USB suspend mask - 11 - 1 - read-write - - - USBRSTMSK - USB reset mask - 12 - 1 - read-write - - - ENUMDONEMSK - Enumeration done mask - 13 - 1 - read-write - - - ISOOUTDROPMSK - Isochronous OUT packet dropped interrupt - mask - 14 - 1 - read-write - - - EOPFMSK - End of periodic frame interrupt - mask - 15 - 1 - read-write - - - IEPTINTMSK - IN endpoints interrupt - mask - 18 - 1 - read-write - - - OEPTINTMSK - OUT endpoints interrupt - mask - 19 - 1 - read-write - - - INCOMISOINMSK - Incomplete isochronous IN transfer - mask - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUTMSK - Incomplete periodic transfer mask(Host - mode)/Incomplete isochronous OUT transfer mask(Device - mode) - 21 - 1 - read-write - - - PRTINTMSK - Host port interrupt mask - 24 - 1 - read-only - - - HCHINTMSK - Host channels interrupt - mask - 25 - 1 - read-write - - - PTXFEMPMSK - Periodic TxFIFO empty mask - 26 - 1 - read-write - - - CONIDSCHGMSK - Connector ID status change - mask - 28 - 1 - read-write - - - DISCONINTMSK - Disconnect detected interrupt - mask - 29 - 1 - read-write - - - WKUPINTMSK - Resume/remote wakeup detected interrupt - mask - 31 - 1 - read-write - - - - - GRXSTSR_Device - GRXSTSR_Device - OTGFS Receive status debug read(Device - mode) - 0x1C - 0x20 - read-only - 0x00000000 - - - EPTNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - FN - Frame number - 21 - 4 - - - - - GRXSTSR_Host - GRXSTSR_Host - OTGFS Receive status debug read(Host - mode) - GRXSTSR_Device - 0x1C - 0x20 - read-only - 0x00000000 - - - CHNUM - Channel number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - - - GRXFSIZ - GRXFSIZ - OTGFS Receive FIFO size register - (OTGFS_GRXFSIZ) - 0x24 - 0x20 - read-write - 0x00000200 - - - RXFDEP - RxFIFO depth - 0 - 16 - - - - - DIEPTXF0 - DIEPTXF0 - IN Endpoint TxFIFO 0 transmit FIFO size - register (Device mode) - 0x28 - 0x20 - read-write - 0x00000200 - - - INEPT0TXSTADDR - Endpoint 0 transmit RAM start - address - 0 - 16 - - - INEPT0TXDEP - Endpoint 0 TxFIFO depth - 16 - 16 - - - - - GNPTXFSIZ - GNPTXFSIZ - OTGFS non-periodic transmit FIFO size - register (Host mode) - DIEPTXF0 - 0x28 - 0x20 - read-write - 0x00000200 - - - NPTXFSTADDR - Non-periodic Transmit RAM Start - address - 0 - 16 - - - NPTXFDEP - Non-periodic TxFIFO depth - 16 - 16 - - - - - GNPTXSTS - GNPTXSTS - OTGFS non-periodic transmit FIFO/queue - status register (OTGFS_GNPTXSTS) - 0x2C - 0x20 - read-only - 0x00080200 - - - NPTXFSPCAVAIL - Non-periodic TxFIFO space - available - 0 - 16 - - - NPTXQSPCAVAIL - Non-periodic transmit request queue - space available - 16 - 8 - - - NPTXQTOP - Top of the non-periodic transmit request - queue - 24 - 7 - - - - - GCCFG - GCCFG - OTGFS general core configuration register - (OTGFS_GCCFG) - 0x38 - 0x20 - read-write - 0x00000000 - - - PWRDOWN - Power down - 16 - 1 - - - AVALIDSESEN - sense Avalid enable - 18 - 1 - - - BVALIDSESEN - sense Bvalid enable - 19 - 1 - - - SOFOUTEN - SOF output enable - 20 - 1 - - - VBUSIG - VBUS Ignored - 21 - 1 - - - - - GUID - GUID - Product ID register - 0x3C - 0x20 - read-write - 0x00001000 - - - USERID - Product ID field - 0 - 32 - - - - - HPTXFSIZ - HPTXFSIZ - OTGFS Host periodic transmit FIFO size - register (OTGFS_HPTXFSIZ) - 0x100 - 0x20 - read-write - 0x02000600 - - - PTXFSTADDR - Host periodic TxFIFO start - address - 0 - 16 - - - PTXFSIZE - Host periodic TxFIFO depth - 16 - 16 - - - - - DIEPTXF1 - DIEPTXF1 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF1) - 0x104 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO1 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF2 - DIEPTXF2 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF2) - 0x108 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO2 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF3 - DIEPTXF3 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF3) - 0x10C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO3 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - - - USB_OTG_HOST - USB on the go full speed - USB_OTG - 0x50000400 - - 0x0 - 0x400 - registers - - - - HCFG - HCFG - OTGFS host configuration register - (OTGFS_HCFG) - 0x0 - 0x20 - 0x00000000 - - - FSLSPCLKSEL - FS/LS PHY clock select - 0 - 2 - read-write - - - FSLSSUPP - FS- and LS-only support - 2 - 1 - read-only - - - - - HFIR - HFIR - OTGFS Host frame interval - register - 0x4 - 0x20 - read-write - 0x0000EA60 - - - FRINT - Frame interval - 0 - 16 - - - - - HFNUM - HFNUM - OTGFS host frame number/frame time - remaining register (OTGFS_HFNUM) - 0x8 - 0x20 - read-only - 0x00003FFF - - - FRNUM - Frame number - 0 - 16 - - - FTREM - Frame time remaining - 16 - 16 - - - - - HPTXSTS - HPTXSTS - OTGFS_Host periodic transmit FIFO/queue - status register (OTGFS_HPTXSTS) - 0x10 - 0x20 - 0x00080100 - - - PTXFSPCAVAIL - Periodic transmit data FIFO space - available - 0 - 16 - read-write - - - PTXQSPCAVAIL - Periodic transmit request queue space - available - 16 - 8 - read-only - - - PTXQTOP - Top of the periodic transmit request - queue - 24 - 8 - read-only - - - - - HAINT - HAINT - OTGFS Host all channels interrupt - register - 0x14 - 0x20 - read-only - 0x00000000 - - - HAINT - Channel interrupts - 0 - 16 - - - - - HAINTMSK - HAINTMSK - OTGFS host all channels interrupt mask - register - 0x18 - 0x20 - read-write - 0x00000000 - - - HAINTMSK - Channel interrupt mask - 0 - 16 - - - - - HPRT - HPRT - OTGFS host port control and status register - (OTGFS_HPRT) - 0x40 - 0x20 - 0x00000000 - - - PRTCONSTS - Port connect status - 0 - 1 - read-only - - - PRTCONDET - Port connect detected - 1 - 1 - read-write - - - PRTENA - Port enable - 2 - 1 - read-write - - - PRTENCHNG - Port enable/disable change - 3 - 1 - read-write - - - PRTOVRCACT - Port overcurrent active - 4 - 1 - read-only - - - PRTOVRCCHNG - Port overcurrent change - 5 - 1 - read-write - - - PRTRES - Port resume - 6 - 1 - read-write - - - PRTSUSP - Port suspend - 7 - 1 - read-write - - - PRTRST - Port reset - 8 - 1 - read-write - - - PRTLNSTS - Port line status - 10 - 2 - read-only - - - PRTPWR - Port power - 12 - 1 - read-write - - - PRTTSTCTL - Port test control - 13 - 4 - read-write - - - PRTSPD - Port speed - 17 - 2 - read-only - - - - - HCCHAR0 - HCCHAR0 - OTGFS host channel-0 characteristics - register (OTGFS_HCCHAR0) - 0x100 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR1 - HCCHAR1 - OTGFS host channel-1 characteristics - register (OTGFS_HCCHAR1) - 0x120 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR2 - HCCHAR2 - OTGFS host channel-2 characteristics - register (OTGFS_HCCHAR2) - 0x140 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR3 - HCCHAR3 - OTGFS host channel-3 characteristics - register (OTGFS_HCCHAR3) - 0x160 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR4 - HCCHAR4 - OTGFS host channel-4 characteristics - register (OTGFS_HCCHAR4) - 0x180 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR5 - HCCHAR5 - OTGFS host channel-5 characteristics - register (OTGFS_HCCHAR5) - 0x1A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR6 - HCCHAR6 - OTGFS host channel-6 characteristics - register (OTGFS_HCCHAR6) - 0x1C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR7 - HCCHAR7 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR7) - 0x1E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCINT0 - HCINT0 - OTGFS host channel-0 interrupt register - (OTGFS_HCINT0) - 0x108 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT1 - HCINT1 - OTG_FS host channel-1 interrupt register - (OTG_FS_HCINT1) - 0x128 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT2 - HCINT2 - OTGFS host channel-2 interrupt register - (OTGFS_HCINT2) - 0x148 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT3 - HCINT3 - OTGFS host channel-3 interrupt register - (OTGFS_HCINT3) - 0x168 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT4 - HCINT4 - OTGFS host channel-4 interrupt register - (OTGFS_HCINT4) - 0x188 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT5 - HCINT5 - OTGFS host channel-5 interrupt register - (OTGFS_HCINT5) - 0x1A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT6 - HCINT6 - OTGFS host channel-6 interrupt register - (OTGFS_HCINT6) - 0x1C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT7 - HCINT7 - OTGFS host channel-7 interrupt register - (OTGFS_HCINT7) - 0x1E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINTMSK0 - HCINTMSK0 - OTGFS host channel-0 mask register - (OTGFS_HCINTMSK0) - 0x10C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK1 - HCINTMSK1 - OTGFS host channel-1 mask register - (OTGFS_HCINTMSK1) - 0x12C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK2 - HCINTMSK2 - OTGFS host channel-2 mask register - (OTGFS_HCINTMSK2) - 0x14C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK3 - HCINTMSK3 - OTGFS host channel-3 mask register - (OTGFS_HCINTMSK3) - 0x16C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK4 - HCINTMSK4 - OTGFS host channel-4 mask register - (OTGFS_HCINTMSK4) - 0x18C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK5 - HCINTMSK5 - OTGFS host channel-5 mask register - (OTGFS_HCINTMSK5) - 0x1AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK6 - HCINTMSK6 - OTGFS host channel-6 mask register - (OTGFS_HCINTMSK6) - 0x1CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK7 - HCINTMSK7 - OTGFS host channel-7 mask register - (OTGFS_HCINTMSK7) - 0x1EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCTSIZ0 - HCTSIZ0 - OTGFS host channel-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ1 - HCTSIZ1 - OTGFS host channel-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ2 - HCTSIZ2 - OTGFS host channel-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ3 - HCTSIZ3 - OTGFS host channel-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ4 - HCTSIZ4 - OTGFS host channel-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ5 - HCTSIZ5 - OTGFS host channel-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ6 - HCTSIZ6 - OTGFS host channel-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ7 - HCTSIZ7 - OTGFS host channel-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - - - USB_OTG_DEVICE - USB on the go full speed - USB_OTG - 0x50000800 - - 0x0 - 0x400 - registers - - - - DCFG - DCFG - OTGFS device configuration register - (OTGFS_DCFG) - 0x0 - 0x20 - read-write - 0x02200000 - - - DEVSPD - Device speed - 0 - 2 - - - NZSTSOUTHSHK - Non-zero-length status OUT - handshake - 2 - 1 - - - DEVADDR - Device address - 4 - 7 - - - PERFRINT - Periodic frame interval - 11 - 2 - - - - - DCTL - DCTL - OTGFS device control register - (OTGFS_DCTL) - 0x4 - 0x20 - 0x00000000 - - - RWKUPSIG - Remote wakeup signaling - 0 - 1 - read-write - - - SFTDISCON - Soft disconnect - 1 - 1 - read-write - - - GNPINNAKSTS - Global IN NAK status - 2 - 1 - read-only - - - GOUTNAKSTS - Global OUT NAK status - 3 - 1 - read-only - - - TSTCTL - Test control - 4 - 3 - read-write - - - SGNPINNAK - Set global IN NAK - 7 - 1 - read-write - - - CGNPINNAK - Clear global IN NAK - 8 - 1 - read-write - - - SGOUTNAK - Set global OUT NAK - 9 - 1 - read-write - - - CGOUTNAK - Clear global OUT NAK - 10 - 1 - read-write - - - PWROPRGDNE - Power-on programming done - 11 - 1 - read-write - - - - - DSTS - DSTS - OTGFS device status register - (OTGFS_DSTS) - 0x8 - 0x20 - read-only - 0x00000010 - - - SUSPSTS - Suspend status - 0 - 1 - - - ENUMSPD - Enumerated speed - 1 - 2 - - - ETICERR - Erratic error - 3 - 1 - - - SOFFN - Frame number of the received - SOF - 8 - 14 - - - - - DIEPMSK - DIEPMSK - OTGFS device IN endpoint common interrupt - mask register (OTGFS_DIEPMSK) - 0x10 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - TIMEOUTMSK - Timeout condition mask (Non-isochronous - endpoints) - 3 - 1 - - - INTKNTXFEMPMSK - IN token received when TxFIFO empty - mask - 4 - 1 - - - INTKNEPTMISMSK - IN token received with EP mismatch - mask - 5 - 1 - - - INEPTNAKMSK - IN endpoint NAK effective - mask - 6 - 1 - - - TXFIFOUDRMSK - FIFO underrun - mask - 8 - 1 - - - BNAINMSK - BNA interrupt - mask - 9 - 1 - - - - - DOEPMSK - DOEPMSK - OTGFS device OUT endpoint common interrupt - mask register (OTGFS_DOEPMSK) - 0x14 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - SETUPMSK - SETUP phase done mask - 3 - 1 - - - OUTTEPDMSK - OUT token received when endpoint - disabled mask - 4 - 1 - - - B2BSETUPMSK - Back-to-back SETUP packets - received mask - 6 - 1 - - - OUTPERRMSK - OUT packet error - mask - 8 - 1 - - - BNAOUTMSK - BNA interrupt - mask - 9 - 1 - - - - - DAINT - DAINT - OTGFS device all endpoints interrupt - register (OTGFS_DAINT) - 0x18 - 0x20 - read-only - 0x00000000 - - - INEPTINT - IN endpoint interrupt bits - 0 - 16 - - - OUTEPTINT - OUT endpoint interrupt - bits - 16 - 16 - - - - - DAINTMSK - DAINTMSK - OTGFS all endpoints interrupt mask register - (OTGFS_DAINTMSK) - 0x1C - 0x20 - read-write - 0x00000000 - - - INEPTMSK - IN EP interrupt mask bits - 0 - 16 - - - OUTEPTMSK - OUT endpoint interrupt - bits - 16 - 16 - - - - - DIEPEMPMSK - DIEPEMPMSK - OTGFS device IN endpoint FIFO empty - interrupt mask register - 0x34 - 0x20 - read-write - 0x00000000 - - - INEPTXFEMSK - IN EP Tx FIFO empty interrupt mask - bits - 0 - 16 - - - - - DIEPCTL0 - DIEPCTL0 - OTGFS device control IN endpoint 0 control - register (OTGFS_DIEPCTL0) - 0x100 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 2 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-only - - - EPTENA - Endpoint enable - 31 - 1 - read-only - - - - - DIEPCTL1 - DIEPCTL1 - OTGFS device IN endpoint-1 control - register - 0x120 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL2 - DIEPCTL2 - OTGFS device IN endpoint-2 control - register - 0x140 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL3 - DIEPCTL3 - OTGFS device IN endpoint-3 control - register - 0x160 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL0 - DOEPCTL0 - OTGFS device OUT endpoint-0 control - register - 0x300 - 0x20 - 0x00008000 - - - MPS - Maximum packet size - 0 - 2 - read-only - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL1 - DOEPCTL1 - OTGFS device OUT endpoint-1 control - register - 0x320 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL2 - DOEPCTL2 - OTGFS device OUT endpoint-2 control - register - 0x340 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL3 - DOEPCTL3 - OTGFS device OUT endpoint-3 control - register - 0x360 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPINT0 - DIEPINT0 - OTGFS device IN endpoint-0 interrupt - register - 0x108 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT1 - DIEPINT1 - OTGFS device IN endpoint-1 interrupt - register - 0x128 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT2 - DIEPINT2 - OTGFS device IN endpoint-2 interrupt - register - 0x148 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT3 - DIEPINT3 - OTGFS device IN endpoint-3 interrupt - register - 0x168 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DOEPINT0 - DOEPINT0 - OTGFS device OUT endpoint-0 interrupt - register - 0x308 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT1 - DOEPINT1 - OTGFS device OUT endpoint-1 interrupt - register - 0x328 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT2 - DOEPINT2 - OTGFS device OUT endpoint-2 interrupt - register - 0x348 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT3 - DOEPINT3 - OTGFS device OUT endpoint-3 interrupt - register - 0x368 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DIEPTSIZ0 - DIEPTSIZ0 - OTGFS device IN endpoint-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 2 - - - - - DOEPTSIZ0 - DOEPTSIZ0 - OTGFS device OUT endpoint-0 transfer size - register - 0x310 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 1 - - - SETUPCNT - SETUP packet count - 29 - 2 - - - - - DIEPTSIZ1 - DIEPTSIZ1 - OTGFS device IN endpoint-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ2 - DIEPTSIZ2 - OTGFS device IN endpoint-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ3 - DIEPTSIZ3 - OTG device IN endpoint-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DTXFSTS0 - DTXFSTS0 - OTGFS device IN endpoint-0 transmit FIFO - status register - 0x118 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS1 - DTXFSTS1 - OTGFS device IN endpoint-1 transmit FIFO - status register - 0x138 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS2 - DTXFSTS2 - OTGFS device IN endpoint-2 transmit FIFO - status register - 0x158 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS3 - DTXFSTS3 - OTGFS device IN endpoint-3 transmit FIFO - status register - 0x178 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DOEPTSIZ1 - DOEPTSIZ1 - OTGFS device OUT endpoint-1 transfer size - register - 0x330 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ2 - DOEPTSIZ2 - OTGFS device OUT endpoint-2 transfer size - register - 0x350 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ3 - DOEPTSIZ3 - OTGFS device OUT endpoint-3 transfer size - register - 0x370 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - - - USB_OTG_PWRCLK - USB on the go full speed - USB_OTG - 0x50000E00 - - 0x0 - 0x400 - registers - - - - PCGCCTL - PCGCCTL - OTGFS power and clock gating control - register (OTGFS_PCGCCTL) - 0x0 - 0x20 - 0x00000000 - - - STOPPCLK - Stop PHY clock - 0 - 1 - read-write - - - SUSPENDM - PHY Suspended - 4 - 1 - read-only - - - - - - - diff --git a/hw/bsp/at32f415/family.c b/hw/bsp/at32f415/family.c index 6c7600783..53897243a 100644 --- a/hw/bsp/at32f415/family.c +++ b/hw/bsp/at32f415/family.c @@ -35,16 +35,16 @@ void led_and_button_init(void); //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void OTGFS1_IRQHandler(void) +void OTGFS1_IRQHandler(void) { tusb_int_handler(0, true); } -void OTGFS1_WKUP_IRQHandler(void) +void OTGFS1_WKUP_IRQHandler(void) { tusb_int_handler(0, true); } -void board_init(void) +void board_init(void) { /* config nvic priority group */ nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); @@ -85,7 +85,7 @@ void board_init(void) /* config led and key */ led_and_button_init(); - + /* config usart printf */ uart_print_init(115200); printf("usart printf config success!\r\n"); @@ -128,13 +128,13 @@ void usb_clock48m_select(usb_clk48_s clk_s) case 144000000: crm_usb_clock_div_set(CRM_USB_DIV_3); break; - + default: break; } } -void led_and_button_init(void) +void led_and_button_init(void) { /* LED */ gpio_init_type gpio_led_init_struct; @@ -190,7 +190,7 @@ void uart_print_init(uint32_t baudrate) } // Get characters from UART. Return number of read bytes -int board_uart_read(uint8_t *buf, int len) +int board_uart_read(uint8_t *buf, int len) { (void) buf; (void) len; @@ -203,7 +203,7 @@ int board_uart_write(void const *buf, int len) #if CFG_TUSB_OS == OPT_OS_NONE int txsize = len; u16 timeout = 0xffff; - while (txsize--) + while (txsize--) { while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) { @@ -224,17 +224,17 @@ int board_uart_write(void const *buf, int len) #endif } -void board_led_write(bool state) +void board_led_write(bool state) { gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); } -uint32_t board_button_read(void) +uint32_t board_button_read(void) { return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); } -size_t board_get_unique_id(uint8_t id[], size_t max_len) +size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); @@ -252,12 +252,12 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; - void SysTick_Handler(void) + void SysTick_Handler(void) { system_ticks++; } - uint32_t board_millis(void) + uint32_t board_millis(void) { return system_ticks; } @@ -271,7 +271,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) } #endif -void HardFault_Handler(void) +void HardFault_Handler(void) { __asm("BKPT #0\n"); } diff --git a/hw/bsp/at32f415/family.mk b/hw/bsp/at32f415/family.mk index d0cca67ab..7af6a8cb8 100644 --- a/hw/bsp/at32f415/family.mk +++ b/hw/bsp/at32f415/family.mk @@ -1,6 +1,5 @@ # Submodules AT32F415_SDK = hw/mcu/artery/at32f415 -DEPS_SUBMODULES += $(AT32F415_SDK) # AT32 SDK path AT32F415_SDK_SRC = $(AT32F415_SDK)/libraries diff --git a/hw/bsp/at32f415/startup_at32f415.s b/hw/bsp/at32f415/startup_at32f415.s index 47a913e36..2c4dbc9ef 100644 --- a/hw/bsp/at32f415/startup_at32f415.s +++ b/hw/bsp/at32f415/startup_at32f415.s @@ -78,7 +78,7 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array diff --git a/hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h index 06afc3860..d5f8aafb0 100644 --- a/hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h @@ -109,7 +109,7 @@ #define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 #define INCLUDE_uxTaskGetStackHighWaterMark 0 #define INCLUDE_xTaskGetIdleTaskHandle 0 #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 diff --git a/hw/bsp/at32f423/at32f423_clock.c b/hw/bsp/at32f423/at32f423_clock.c index 1c9467588..564208fcb 100644 --- a/hw/bsp/at32f423/at32f423_clock.c +++ b/hw/bsp/at32f423/at32f423_clock.c @@ -125,4 +125,3 @@ void system_clock_config(void) /** * @} */ - diff --git a/hw/bsp/at32f423/at32f423_clock.h b/hw/bsp/at32f423/at32f423_clock.h index 183748b39..27079924d 100644 --- a/hw/bsp/at32f423/at32f423_clock.h +++ b/hw/bsp/at32f423/at32f423_clock.h @@ -41,4 +41,3 @@ void system_clock_config(void); #endif #endif - diff --git a/hw/bsp/at32f423/at32f423_int.c b/hw/bsp/at32f423/at32f423_int.c index a39c7bdda..2b623e053 100644 --- a/hw/bsp/at32f423/at32f423_int.c +++ b/hw/bsp/at32f423/at32f423_int.c @@ -137,4 +137,3 @@ void DebugMon_Handler(void) /** * @} */ - diff --git a/hw/bsp/at32f423/at32f423_int.h b/hw/bsp/at32f423/at32f423_int.h index 0a807d6d6..28550331e 100644 --- a/hw/bsp/at32f423/at32f423_int.h +++ b/hw/bsp/at32f423/at32f423_int.h @@ -53,4 +53,3 @@ void SysTick_Handler(void); #endif #endif - diff --git a/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xC_FLASH.ld b/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xC_FLASH.ld index c6333cb1c..ee08e979a 100644 --- a/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xC_FLASH.ld +++ b/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xC_FLASH.ld @@ -104,7 +104,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -119,7 +119,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd b/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd deleted file mode 100644 index 4954c417f..000000000 --- a/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd +++ /dev/null @@ -1,36050 +0,0 @@ - - - - - - - - Keil - ArteryTek - AT32F423xx_v2 - AT32F423 - 1.0 - ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 288MHz, etc. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - CM4 - r0p1 - little - false - true - 4 - false - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - - XMC - Flexible static memory controller - XMC - 0xA0000000 - - 0x0 - 0x1000 - registers - - - XMC - XMC global interrupt - 48 - - - - BK1CTRL1 - BK1CTRL1 - SRAM/NOR-Flash chip-select control register - 1 - 0x0 - 0x20 - read-write - 0x000030DB - - - MWMC - Memory write mode control - 19 - 1 - - - CRPGS - CRAM page size - 16 - 3 - - - NWASEN - NWAIT in asynchronous transfer enable - 15 - 1 - - - RWTD - Read-write timing different - 14 - 1 - - - NWSEN - NWAIT in synchronous transfer enable - 13 - 1 - - - WEN - Write enable - 12 - 1 - - - NWTCFG - Wait timing configuration - 11 - 1 - - - WRAPEN - Wrapped enable - 10 - 1 - - - NWPOL - NWAIT polarity - 9 - 1 - - - SYNCBEN - Synchronous burst enable - 8 - 1 - - - NOREN - Nor flash access enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 2 - 2 - - - ADMUXEN - Address and data multiplexing enable - 1 - 1 - - - EN - Memory bank enable - 0 - 1 - - - - - BK1TMG1 - BK1TMG1 - SRAM/NOR-Flash chip-select timing register - 1 - 0x4 - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - DTLAT - Data latency - 24 - 4 - - - CLKPSC - Clock prescale - 20 - 4 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1CTRL2 - BK1CTRL2 - SRAM/NOR-Flash chip-select control register - 2 - 0x8 - 0x20 - read-write - 0x000030D2 - - - MWMC - Memory write mode control - 19 - 1 - - - CRPGS - CRAM page size - 16 - 3 - - - NWASEN - NWAIT in asynchronous transfer enable - 15 - 1 - - - RWTD - Read-write timing different - 14 - 1 - - - NWSEN - NWAIT in synchronous transfer enable - 13 - 1 - - - WEN - Write enable - 12 - 1 - - - NWTCFG - Wait timing configuration - 11 - 1 - - - WRAPEN - Wrapped enable - 10 - 1 - - - NWPOL - NWAIT polarity - 9 - 1 - - - SYNCBEN - Synchronous burst enable - 8 - 1 - - - NOREN - Nor flash access enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 2 - 2 - - - ADMUXEN - Address and data multiplexing enable - 1 - 1 - - - EN - Memory bank enable - 0 - 1 - - - - - BK1TMG2 - BK1TMG2 - SRAM/NOR-Flash chip-select timing register - 2 - 0xC - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - DTLAT - Data latency - 24 - 4 - - - CLKPSC - Clock prescale - 20 - 4 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1CTRL4 - BK1CTRL4 - SRAM/NOR-Flash chip-select control register - 4 - 0x18 - 0x20 - read-write - 0x000030D2 - - - MWMC - Memory write mode control - 19 - 1 - - - CRPGS - CRAM page size - 16 - 3 - - - NWASEN - NWAIT in asynchronous transfer enable - 15 - 1 - - - RWTD - Read-write timing different - 14 - 1 - - - NWSEN - NWAIT in synchronous transfer enable - 13 - 1 - - - WEN - Write enable - 12 - 1 - - - NWTCFG - Wait timing configuration - 11 - 1 - - - WRAPEN - Wrapped enable - 10 - 1 - - - NWPOL - NWAIT polarity - 9 - 1 - - - SYNCBEN - Synchronous burst enable - 8 - 1 - - - NOREN - Nor flash access enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 2 - 2 - - - ADMUXEN - Address and data multiplexing enable - 1 - 1 - - - EN - Memory bank enable - 0 - 1 - - - - - BK1TMG4 - BK1TMG4 - SRAM/NOR-Flash chip-select timing register - 4 - 0x1C - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - DTLAT - Data latency - 24 - 4 - - - CLKPSC - Clock prescale - 20 - 4 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1TMGWR1 - BK1TMGWR1 - SRAM/NOR-Flash write timing registers - 1 - 0x104 - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1TMGWR2 - BK1TMGWR2 - SRAM/NOR-Flash write timing registers - 2 - 0x10C - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1TMGWR4 - BK1TMGWR4 - SRAM/NOR-Flash write timing registers - 4 - 0x11C - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - EXT1 - EXT1 - externl timeing register 1 - 0x220 - 0x20 - read-write - 0x00000808 - - - BUSLATW2W - Bus turnaround phase for consecutive write duration - 0 - 8 - - - BUSLATR2R - Bus turnaround phase for consecutive read duration - 8 - 8 - - - - - EXT2 - EXT2 - externl timeing register 2 - 0x224 - 0x20 - read-write - 0x00000808 - - - BUSLATW2W - Bus turnaround phase for consecutive write duration - 0 - 8 - - - BUSLATR2R - Bus turnaround phase for consecutive read duration - 8 - 8 - - - - - EXT4 - EXT4 - externl timeing register 4 - 0x22C - 0x20 - read-write - 0x00000808 - - - BUSLATW2W - Bus turnaround phase for consecutive write duration - 0 - 8 - - - BUSLATR2R - Bus turnaround phase for consecutive read duration - 8 - 8 - - - - - - - PWC - Power control - PWC - 0x40007000 - - 0x0 - 0x400 - registers - - - - CTRL - CTRL - Power control register - (PWC_CTRL) - 0x0 - 0x20 - read-write - 0x00000000 - - - VRSEL - Voltage regulator state select when deepsleep mode - 0 - 1 - - - LPSEL - Low power mode select when Cortex-M4F sleepdeep - 1 - 1 - - - CLSWEF - Clear SWEF flag - 2 - 1 - - - CLSEF - Clear SEF flag - 3 - 1 - - - PVMEN - Power voltage monitoring enable - 4 - 1 - - - PVMSEL - Power voltage monitoring boundary select - 5 - 3 - - - BPWEN - Battery powered domain write enable - 8 - 1 - - - - - CTRLSTS - CTRLSTS - Power control and status register - (PWC_CTRLSTS) - 0x4 - 0x20 - 0x00000000 - - - SWEF - Standby wake-up event flag - 0 - 1 - read-only - - - SEF - Standby mode entry flag - 1 - 1 - read-only - - - PVMOF - Power voltage monitoring output flag - 2 - 1 - read-only - - - SWPEN1 - Standby wake-up pin 1 enable - 8 - 1 - read-write - - - SWPEN2 - Standby wake-up pin 2 enable - 9 - 1 - read-write - - - SWPEN6 - Standby wake-up pin 6 enable - 13 - 1 - read-write - - - SWPEN7 - Standby wake-up pin 7 enable - 14 - 1 - read-write - - - - - LDOOV - LDOOV - LDO output voltage register - 0x10 - 0x20 - 0x00000000 - - - LDOOVSEL - LDO output voltage select - 0 - 2 - read-write - - - VREXLPEN - Voltage regulator extra low power mode enable - 4 - 1 - read-write - - - - - - - CRM - Clock and reset management - CRM - 0x40023800 - - 0x0 - 0x400 - registers - - - CRM - CRM global interrupt - 5 - - - - CTRL - CTRL - Clock control register - 0x0 - 0x20 - 0x00000083 - - - HICKEN - High speed internal clock enable - 0 - 1 - read-write - - - HICKSTBL - High speed internal clock ready flag - 1 - 1 - read-only - - - HICKTRIM - High speed internal clock trimming - 2 - 6 - read-write - - - HICKCAL - High speed internal clock calibration - 8 - 8 - read-only - - - HEXTEN - High speed exernal crystal enable - 16 - 1 - read-write - - - HEXTSTBL - High speed exernal crystal ready flag - 17 - 1 - read-only - - - HEXTBYPS - High speed exernal crystal bypass - 18 - 1 - read-write - - - CFDEN - Clock failure detection enable - 19 - 1 - read-write - - - PLLEN - PLL enable - 24 - 1 - read-write - - - PLLSTBL - PLL clock ready flag - 25 - 1 - read-only - - - - - PLLCFG - PLLCFG - PLL configuration register - (CRM_PLLCFG) - 0x4 - 0x20 - 0x00033002 - - - PLL_MS - PLL pre-division - 0 - 4 - read-write - - - PLL_NS - PLL frequency multiplication factor - 6 - 9 - read-write - - - PLL_FR - PLL post-division - 16 - 3 - read-write - - - PLLRCS - PLL reference clock select - 22 - 1 - read-write - - - - - CFG - CFG - Clock configuration register(CRM_CFG) - 0x8 - 0x20 - 0x00000000 - - - SCLKSEL - System clock select - 0 - 2 - read-write - - - SCLKSTS - System Clock select Status - 2 - 2 - read-only - - - AHBDIV - AHB division - 4 - 4 - read-write - - - APB1DIV - APB1 division - 10 - 3 - read-write - - - APB2DIV - APB2 division - 13 - 3 - read-write - - - ERTCDIV - HEXT division for ERTC clock - 16 - 5 - read-write - - - CLKOUTDIV1 - Clock output division1 - 27 - 3 - read-write - - - CLKOUT_SEL1 - Clock output selection1 - 30 - 2 - read-write - - - - - CLKINT - CLKINT - Clock interrupt register - (CRM_CLKINT) - 0xC - 0x20 - 0x00000000 - - - LICKSTBLF - LICK ready interrupt flag - 0 - 1 - read-only - - - LEXTSTBLF - LEXT ready interrupt flag - 1 - 1 - read-only - - - HICKSTBLF - HICK ready interrupt flag - 2 - 1 - read-only - - - HEXTSTBLF - HEXT ready interrupt flag - 3 - 1 - read-only - - - PLLSTBLF - PLL ready interrupt flag - 4 - 1 - read-only - - - CFDF - Clock failure detection interrupt flag - 7 - 1 - read-only - - - LICKSTBLIEN - LICK ready interrupt enable - 8 - 1 - read-write - - - LEXTSTBLIEN - LEXT ready interrupt enable - 9 - 1 - read-write - - - HICKSTBLIEN - HICK ready interrupt enable - 10 - 1 - read-write - - - HEXTSTBLIEN - HEXT ready interrupt enable - 11 - 1 - read-write - - - PLLSTBLIEN - PLL ready interrupt enable - 12 - 1 - read-write - - - LICKSTBLFC - LICK ready interrupt clear - 16 - 1 - write-only - - - LEXTSTBLFC - LEXT ready interrupt clear - 17 - 1 - write-only - - - HICKSTBLFC - HICK ready interrupt clear - 18 - 1 - write-only - - - HEXTSTBLFC - HEXT ready interrupt clear - 19 - 1 - write-only - - - PLLSTBLFC - PLL ready interrupt clear - 20 - 1 - write-only - - - CFDFC - Clock failure detection interrupt clear - 23 - 1 - write-only - - - - - AHBRST1 - AHBRST1 - AHB peripheral reset register1 - (CRM_AHBRST1) - 0x10 - 0x20 - read-write - 0x000000000 - - - GPIOARST - IO port A reset - 0 - 1 - - - GPIOBRST - IO port B reset - 1 - 1 - - - GPIOCRST - IO port C reset - 2 - 1 - - - GPIODRST - IO port D reset - 3 - 1 - - - GPIOERST - IO port E reset - 4 - 1 - - - GPIOFRST - IO port F reset - 5 - 1 - - - CRCRST - CRC reset - 12 - 1 - - - DMA1RST - DMA1 reset - 22 - 1 - - - DMA2RST - DMA2 reset - 24 - 1 - - - - - AHBRST2 - AHBRST2 - AHB peripheral reset register 2 - (CRM_AHBRST2) - 0x14 - 0x20 - read-write - 0x00000000 - - - OTGFS1RST - OTGFS1 reset - 7 - 1 - - - - - AHBRST3 - AHBRST3 - AHB peripheral reset register 3 - (CRM_AHBRST3) - 0x18 - 0x20 - read-write - 0x00000000 - - - XMCRST - XMC reset - 0 - 1 - - - - - APB1RST - APB1RST - APB1 peripheral reset register - (CRM_APB1RST) - 0x20 - 0x20 - read-write - 0x00000000 - - - TMR2RST - Timer2 reset - 0 - 1 - - - TMR3RST - Timer3 reset - 1 - 1 - - - TMR4RST - Timer4 reset - 2 - 1 - - - TMR6RST - Timer6 reset - 4 - 1 - - - TMR7RST - Timer7 reset - 5 - 1 - - - TMR12RST - Timer12 reset - 6 - 1 - - - TMR13RST - Timer13 reset - 7 - 1 - - - TMR14RST - Timer14 reset - 8 - 1 - - - WWDTRST - Window watchdog reset - 11 - 1 - - - SPI2RST - SPI2 reset - 14 - 1 - - - SPI3RST - SPI3 reset - 15 - 1 - - - USART2RST - USART2 reset - 17 - 1 - - - USART3RST - USART3 reset - 18 - 1 - - - USART4RST - USART4 reset - 19 - 1 - - - USART5RST - USART5 reset - 20 - 1 - - - I2C1RST - I2C1 reset - 21 - 1 - - - I2C2RST - I2C2 reset - 22 - 1 - - - I2C3RST - I2C3 reset - 23 - 1 - - - CAN1RST - CAN1 reset - 25 - 1 - - - CAN2RST - CAN2 reset - 26 - 1 - - - PWCRST - PWC reset - 28 - 1 - - - DACRST - DAC reset - 29 - 1 - - - USART7RST - USART7 reset - 30 - 1 - - - USART8RST - USART8 reset - 31 - 1 - - - - - APB2RST - APB2RST - APB2 peripheral reset register - (CRM_APB2RST) - 0x24 - 0x20 - read-write - 0x00000000 - - - TMR1RST - Timer1 reset - 0 - 1 - - - USART1RST - USART1 reset - 4 - 1 - - - USART6RST - USART6 reset - 5 - 1 - - - ADCRST - ADC reset - 8 - 1 - - - SPI1RST - SPI1 reset - 12 - 1 - - - SCFGRST - SCFG reset - 14 - 1 - - - TMR9RST - Timer9 reset - 16 - 1 - - - TMR10RST - Timer10 reset - 17 - 1 - - - TMR11RST - Timer 11 reset - 18 - 1 - - - ACCRST - ACC reset - 29 - 1 - - - - - AHBEN1 - AHBEN1 - AHB Peripheral Clock enable register 1 - (CRM_AHBEN1) - 0x30 - 0x20 - read-write - 0x00000000 - - - GPIOAEN - IO A clock enable - 0 - 1 - - - GPIOBEN - IO B clock enable - 1 - 1 - - - GPIOCEN - IO C clock enable - 2 - 1 - - - GPIODEN - IO D clock enable - 3 - 1 - - - GPIOEEN - IO E clock enable - 4 - 1 - - - GPIOFEN - IO F clock enable - 5 - 1 - - - CRCEN - CRC clock enable - 12 - 1 - - - DMA1EN - DMA1 clock enable - 22 - 1 - - - DMA2EN - DMA2 clock enable - 24 - 1 - - - - - AHBEN2 - AHBEN2 - AHB peripheral clock enable register 2 - (CRM_AHBEN2) - 0x34 - 0x20 - read-write - 0x00000000 - - - OTGFS1EN - OTGFS1 clock enable - 7 - 1 - - - - - AHBEN3 - AHBEN3 - AHB peripheral clock enable register 3 - (CRM_AHBEN3) - 0x38 - 0x20 - read-write - 0x00000000 - - - XMCEN - XMC clock enable - 0 - 1 - - - - - APB1EN - APB1EN - APB1 peripheral clock enable register - (CRM_APB1EN) - 0x40 - 0x20 - read-write - 0x00000000 - - - TMR2EN - Timer2 clock enable - 0 - 1 - - - TMR3EN - Timer3 clock enable - 1 - 1 - - - TMR4EN - Timer4 clock enable - 2 - 1 - - - TMR6EN - Timer6 clock enable - 4 - 1 - - - TMR7EN - Timer7 clock enable - 5 - 1 - - - TMR12EN - Timer12 clock enable - 6 - 1 - - - TMR13EN - Timer13 clock enable - 7 - 1 - - - TMR14EN - Timer14 clock enable - 8 - 1 - - - WWDTEN - WWDT clock enable - 11 - 1 - - - SPI2EN - SPI2 clock enable - 14 - 1 - - - SPI3EN - SPI3 clock enable - 15 - 1 - - - USART2EN - USART2 clock enable - 17 - 1 - - - USART3EN - USART3 clock enable - 18 - 1 - - - USART4EN - USART4 clock enable - 19 - 1 - - - USART5EN - USART5 clock enable - 20 - 1 - - - I2C1EN - I2C1 clock enable - 21 - 1 - - - I2C2EN - I2C2 clock enable - 22 - 1 - - - I2C3EN - I2C3 clock enable - 23 - 1 - - - CAN1EN - CAN1 clock enable - 25 - 1 - - - CAN2EN - CAN2 clock enable - 26 - 1 - - - PWCEN - PWC clock enable - 28 - 1 - - - DACEN - DAC clock enable - 29 - 1 - - - USART7EN - USART7 clock enable - 30 - 1 - - - USART8EN - USART8 clock enable - 31 - 1 - - - - - APB2EN - APB2EN - APB2 peripheral clock enable register - (CRM_APB2EN) - 0x44 - 0x20 - read-write - 0x00000000 - - - TMR1EN - Timer1 clock enable - 0 - 1 - - - USART1EN - USART1 clock enable - 4 - 1 - - - USART6EN - USART6 clock enable - 5 - 1 - - - ADCEN - ADC clock enable - 8 - 1 - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - SCFGEN - SCFG clock enable - 14 - 1 - - - TMR9EN - Timer9 clock enable - 16 - 1 - - - TMR10EN - Timer10 clock enable - 17 - 1 - - - TMR11EN - Timer11 clock enable - 18 - 1 - - - ACCEN - ACC clock enable - 29 - 1 - - - - - AHBLPEN1 - AHBLPEN1 - AHB Low-power Peripheral Clock enable - register 1 (CRM_AHBLPEN1) - 0x50 - 0x20 - read-write - 0x3E6390FF - - - GPIOALPEN - IO A clock enable during sleep mode - 0 - 1 - - - GPIOBLPEN - IO B clock enable during sleep mode - 1 - 1 - - - GPIOCLPEN - IO C clock enable during sleep mode - 2 - 1 - - - GPIODLPEN - IO D clock enable during sleep mode - 3 - 1 - - - GPIOELPEN - IO E clock enable during sleep mode - 4 - 1 - - - GPIOFLPEN - IO F clock enable during sleep mode - 5 - 1 - - - CRCLPEN - CRC clock enable during sleep mode - 12 - 1 - - - FLASHLPEN - Flash clock enable during sleep mode - 15 - 1 - - - SRAMLPEN - SRAM clock enable during sleep mode - 16 - 1 - - - DMA1LPEN - DMA1 clock enable during sleep mode - 22 - 1 - - - DMA2LPEN - DMA2 clock enable during sleep mode - 24 - 1 - - - - - AHBLPEN2 - AHBLPEN2 - AHB peripheral Low-power clock - enable register 2 (CRM_AHBLPEN2) - 0x54 - 0x20 - read-write - 0x00008081 - - - OTGFS1LPEN - OTGFS1 clock enable during sleep mode - 7 - 1 - - - - - AHBLPEN3 - AHBLPEN3 - AHB peripheral Low-power clock - enable register 3 (CRM_AHBLPEN3) - 0x58 - 0x20 - read-write - 0x0000C003 - - - XMCLPEN - XMC clock enable during sleep mode - 0 - 1 - - - - - APB1LPEN - APB1LPEN - APB1 peripheral Low-power clock - enable register (CRM_APB1LPEN) - 0x60 - 0x20 - read-write - 0xF6FEE9FF - - - TMR2LPEN - Timer2 clock enable during sleep mode - 0 - 1 - - - TMR3LPEN - Timer3 clock enable during sleep mode - 1 - 1 - - - TMR4LPEN - Timer4 clock enable during sleep mode - 2 - 1 - - - TMR6LPEN - Timer6 clock enable during sleep mode - 4 - 1 - - - TMR7LPEN - Timer7 clock enable during sleep mode - 5 - 1 - - - TMR12LPEN - Timer12 clock enable during sleep mode - 6 - 1 - - - TMR13LPEN - Timer13 clock enable during sleep mode - 7 - 1 - - - TMR14LPEN - Timer14 clock enable during sleep mode - 8 - 1 - - - WWDTLPEN - WWDT clock enable during sleep mode - 11 - 1 - - - SPI2LPEN - SPI2 clock enable during sleep mode - 14 - 1 - - - SPI3LPEN - SPI3 clock enable during sleep mode - 15 - 1 - - - USART2LPEN - USART2 clock enable during sleep mode - 17 - 1 - - - USART3LPEN - USART3 clock enable during sleep mode - 18 - 1 - - - USART4LPEN - USART4 clock enable during sleep mode - 19 - 1 - - - USART5LPEN - USART5 clock enable during sleep mode - 20 - 1 - - - I2C1CPEN - I2C1 clock enable during sleep mode - 21 - 1 - - - I2C2CPEN - I2C2 clock enable during sleep mode - 22 - 1 - - - I2C3CPEN - I2C3 clock enable during sleep mode - 23 - 1 - - - CAN1LPEN - CAN1 clock enable during sleep mode - 25 - 1 - - - CAN2LPEN - CAN2 clock enable during sleep mode - 26 - 1 - - - PWCLPEN - PWC clock enable during sleep mode - 28 - 1 - - - DACLPEN - DAC clock enable during sleep mode - 29 - 1 - - - USART7LPEN - USART7 clock enable during sleep mode - 30 - 1 - - - USART8LPEN - USART8 clock enable during sleep mode - 31 - 1 - - - - - APB2LPEN - APB2LPEN - APB2 peripheral Low-power clock - enable register (CRM_APB2LPEN) - 0x64 - 0x20 - read-write - 0x20177733 - - - TMR1LPEN - Timer1 clock enable during sleep mode - 0 - 1 - - - USART1LPEN - USART1 clock enable during sleep mode - 4 - 1 - - - USART6LPEN - USART6 clock enable during sleep mode - 5 - 1 - - - ADCLPEN - ADC clock enable during sleep mode - 8 - 1 - - - SPI1LPEN - SPI1 clock enable during sleep mode - 12 - 1 - - - SCFGLPEN - SCFG clock enable during sleep mode - 14 - 1 - - - TMR9LPEN - Timer9 clock enable during sleep mode - 16 - 1 - - - TMR10LPEN - Timer10 clock enable during sleep mode - 17 - 1 - - - TMR11LPEN - Timer11 clock enable during sleep mode - 18 - 1 - - - ACCLPEN - ACC clock enable during sleep mode - 29 - 1 - - - - - PICLKS - PICLKS - Peripheral independent clock register - (CRM_PICLKS) - 0x68 - 0x20 - 0x00000000 - - - USART1SEL - USART1 clock select - 0 - 2 - read-write - - - USART2SEL - USART2 clock select - 2 - 2 - read-write - - - USART3SEL - USART3 clock select - 4 - 2 - read-write - - - I2C1SEL - I2C1 clock select - 12 - 2 - read-write - - - - - BPDC - BPDC - Battery powered domain control register - (CRM_BPDC) - 0x70 - 0x20 - 0x00000000 - - - LEXTEN - Low speed external crystal enable - 0 - 1 - read-write - - - LEXTSTBL - Low speed external crystal ready - 1 - 1 - read-only - - - LEXTBYPS - Low speed external crystal bypass - 2 - 1 - read-write - - - ERTCSEL - ERTC clock source selection - 8 - 2 - read-write - - - ERTCEN - ERTC clock enable - 15 - 1 - read-write - - - BPDRST - Battery powered domain software reset - 16 - 1 - read-write - - - - - CTRLSTS - CTRLSTS - Control/status register - (CRM_CTRLSTS) - 0x74 - 0x20 - 0x0C000000 - - - LICKEN - Low speed internal clock enable - 0 - 1 - read-write - - - LICKSTBL - Low speed internal clock ready - 1 - 1 - read-only - - - RSTFC - Reset reset flag - 24 - 1 - read-write - - - NRSTF - PIN reset flag - 26 - 1 - read-write - - - PORRSTF - POR/LVR reset flag - 27 - 1 - read-write - - - SWRSTF - Software reset flag - 28 - 1 - read-write - - - WDTRSTF - Watchdog timer reset flag - 29 - 1 - read-write - - - WWDTRSTF - Window watchdog timer reset flag - 30 - 1 - read-write - - - LPRSTF - Low-power reset flag - 31 - 1 - read-write - - - - - MISC1 - MISC1 - Miscellaneous register1 - 0xA0 - 0x20 - 0x00000000 - - - HICKCAL_KEY - HICKCAL write key value - 0 - 8 - read-write - - - HICKDIV - HICK 6 divider selection - 12 - 1 - read-write - - - HICK_TO_USB - HICK to usb clock - 13 - 1 - read-write - - - HICK_TO_SCLK - HICK to system clock - 14 - 1 - read-write - - - PLLCLK_TO_ADC - ADC clock source select - 15 - 1 - read-write - - - CLKOUT_SEL2 - Clock output select2 - 16 - 4 - read-write - - - CLKOUTDIV2 - Clock output division2 - 28 - 4 - read-write - - - - - MISC2 - MISC2 - Miscellaneous register2 - 0xA4 - 0x20 - 0x0000000D - - - AUTO_STEP_EN - AUTO_STEP_EN - 4 - 2 - read-write - - - USBDIV - USB division - 12 - 4 - read-write - - - HICK_TO_SCLK_DIV - HICK as system clock frequency division - 16 - 3 - read-write - - - HEXT_TO_SCLK_DIV - HEXT as system clock frequency division - 19 - 3 - read-write - - - - - - - GPIOA - General purpose I/Os - GPIO - 0x40020000 - - 0x0 - 0x400 - registers - - - - CFGR - CFGR - GPIO configuration register - 0x0 - 0x20 - read-write - 0x00000000 - - - IOMC15 - GPIOx pin 15 mode configurate - 30 - 2 - - - IOMC14 - GPIOx pin 14 mode configurate - 28 - 2 - - - IOMC13 - GPIOx pin 13 mode configurate - 26 - 2 - - - IOMC12 - GPIOx pin 12 mode configurate - 24 - 2 - - - IOMC11 - GPIOx pin 11 mode configurate - 22 - 2 - - - IOMC10 - GPIOx pin 10 mode configurate - 20 - 2 - - - IOMC9 - GPIOx pin 9 mode configurate - 18 - 2 - - - IOMC8 - GPIOx pin 8 mode configurate - 16 - 2 - - - IOMC7 - GPIOx pin 7 mode configurate - 14 - 2 - - - IOMC6 - GPIOx pin 6 mode configurate - 12 - 2 - - - IOMC5 - GPIOx pin 5 mode configurate - 10 - 2 - - - IOMC4 - GPIOx pin 4 mode configurate - 8 - 2 - - - IOMC3 - GPIOx pin 3 mode configurate - 6 - 2 - - - IOMC2 - GPIOx pin 2 mode configurate - 4 - 2 - - - IOMC1 - GPIOx pin 1 mode configurate - 2 - 2 - - - IOMC0 - GPIOx pin 0 mode configurate - 0 - 2 - - - - - OMODE - OMODE - GPIO output mode register - 0x4 - 0x20 - read-write - 0x00000000 - - - OM15 - GPIOx pin 15 outpu mode configurate - 15 - 1 - - - OM14 - GPIOx pin 14 outpu mode configurate - 14 - 1 - - - OM13 - GPIOx pin 13 outpu mode configurate - 13 - 1 - - - OM12 - GPIOx pin 12 outpu mode configurate - 12 - 1 - - - OM11 - GPIOx pin 11 outpu mode configurate - 11 - 1 - - - OM10 - GPIOx pin 10 outpu mode configurate - 10 - 1 - - - OM9 - GPIOx pin 9 outpu mode configurate - 9 - 1 - - - OM8 - GPIOx pin 8 outpu mode configurate - 8 - 1 - - - OM7 - GPIOx pin 7 outpu mode configurate - 7 - 1 - - - OM6 - GPIOx pin 6 outpu mode configurate - 6 - 1 - - - OM5 - GPIOx pin 5 outpu mode configurate - 5 - 1 - - - OM4 - GPIOx pin 4 outpu mode configurate - 4 - 1 - - - OM3 - GPIOx pin 3 outpu mode configurate - 3 - 1 - - - OM2 - GPIOx pin 2 outpu mode configurate - 2 - 1 - - - OM1 - GPIOx pin 1 outpu mode configurate - 1 - 1 - - - OM0 - GPIOx pin 0 outpu mode configurate - 0 - 1 - - - - - ODRVR - ODRVR - GPIO drive capability register - 0x8 - 0x20 - read-write - 0x00000000 - - - ODRV15 - GPIOx pin 15 output drive capability - 30 - 2 - - - ODRV14 - GPIOx pin 14 output drive capability - 28 - 2 - - - ODRV13 - GPIOx pin 13 output drive capability - 26 - 2 - - - ODRV12 - GPIOx pin 12 output drive capability - 24 - 2 - - - ODRV11 - GPIOx pin 11 output drive capability - 22 - 2 - - - ODRV10 - GPIOx pin 10 output drive capability - 20 - 2 - - - ODRV9 - GPIOx pin 9 output drive capability - 18 - 2 - - - ODRV8 - GPIOx pin 8 output drive capability - 16 - 2 - - - ODRV7 - GPIOx pin 7 output drive capability - 14 - 2 - - - ODRV6 - GPIOx pin 6 output drive capability - 12 - 2 - - - ODRV5 - GPIOx pin 5 output drive capability - 10 - 2 - - - ODRV4 - GPIOx pin 4 output drive capability - 8 - 2 - - - ODRV3 - GPIOx pin 3 output drive capability - 6 - 2 - - - ODRV2 - GPIOx pin 2 output drive capability - 4 - 2 - - - ODRV1 - GPIOx pin 1 output drive capability - 2 - 2 - - - ODRV0 - GPIOx pin 0 output drive capability - 0 - 2 - - - - - PULL - PULL - GPIO pull-up/pull-down register - 0xC - 0x20 - read-write - 0x00000000 - - - PULL15 - GPIOx pin 15 pull configuration - 30 - 2 - - - PULL14 - GPIOx pin 14 pull configuration - 28 - 2 - - - PULL13 - GPIOx pin 13 pull configuration - 26 - 2 - - - PULL12 - GPIOx pin 12 pull configuration - 24 - 2 - - - PULL11 - GPIOx pin 11 pull configuration - 22 - 2 - - - PULL10 - GPIOx pin 10 pull configuration - 20 - 2 - - - PULL9 - GPIOx pin 9 pull configuration - 18 - 2 - - - PULL8 - GPIOx pin 8 pull configuration - 16 - 2 - - - PULL7 - GPIOx pin 7 pull configuration - 14 - 2 - - - PULL6 - GPIOx pin 6 pull configuration - 12 - 2 - - - PULL5 - GPIOx pin 5 pull configuration - 10 - 2 - - - PULL4 - GPIOx pin 4 pull configuration - 8 - 2 - - - PULL3 - GPIOx pin 3 pull configuration - 6 - 2 - - - PULL2 - GPIOx pin 2 pull configuration - 4 - 2 - - - PULL1 - GPIOx pin 1 pull configuration - 2 - 2 - - - PULL0 - GPIOx pin 0 pull configuration - 0 - 2 - - - - - IDT - IDT - GPIO input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - IDT0 - Port input data - 0 - 1 - - - IDT1 - Port input data - 1 - 1 - - - IDT2 - Port input data - 2 - 1 - - - IDT3 - Port input data - 3 - 1 - - - IDT4 - Port input data - 4 - 1 - - - IDT5 - Port input data - 5 - 1 - - - IDT6 - Port input data - 6 - 1 - - - IDT7 - Port input data - 7 - 1 - - - IDT8 - Port input data - 8 - 1 - - - IDT9 - Port input data - 9 - 1 - - - IDT10 - Port input data - 10 - 1 - - - IDT11 - Port input data - 11 - 1 - - - IDT12 - Port input data - 12 - 1 - - - IDT13 - Port input data - 13 - 1 - - - IDT14 - Port input data - 14 - 1 - - - IDT15 - Port input data - 15 - 1 - - - - - ODT - ODT - GPIO output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - ODT0 - Port output data - 0 - 1 - - - ODT1 - Port output data - 1 - 1 - - - ODT2 - Port output data - 2 - 1 - - - ODT3 - Port output data - 3 - 1 - - - ODT4 - Port output data - 4 - 1 - - - ODT5 - Port output data - 5 - 1 - - - ODT6 - Port output data - 6 - 1 - - - ODT7 - Port output data - 7 - 1 - - - ODT8 - Port output data - 8 - 1 - - - ODT9 - Port output data - 9 - 1 - - - ODT10 - Port output data - 10 - 1 - - - ODT11 - Port output data - 11 - 1 - - - ODT12 - Port output data - 12 - 1 - - - ODT13 - Port output data - 13 - 1 - - - ODT14 - Port output data - 14 - 1 - - - ODT15 - Port output data - 15 - 1 - - - - - SCR - SCR - Port bit set/clear register - 0x18 - 0x20 - write-only - 0x00000000 - - - IOSB0 - Set bit 0 - 0 - 1 - - - IOSB1 - Set bit 1 - 1 - 1 - - - IOSB2 - Set bit 1 - 2 - 1 - - - IOSB3 - Set bit 3 - 3 - 1 - - - IOSB4 - Set bit 4 - 4 - 1 - - - IOSB5 - Set bit 5 - 5 - 1 - - - IOSB6 - Set bit 6 - 6 - 1 - - - IOSB7 - Set bit 7 - 7 - 1 - - - IOSB8 - Set bit 8 - 8 - 1 - - - IOSB9 - Set bit 9 - 9 - 1 - - - IOSB10 - Set bit 10 - 10 - 1 - - - IOSB11 - Set bit 11 - 11 - 1 - - - IOSB12 - Set bit 12 - 12 - 1 - - - IOSB13 - Set bit 13 - 13 - 1 - - - IOSB14 - Set bit 14 - 14 - 1 - - - IOSB15 - Set bit 15 - 15 - 1 - - - IOCB0 - Clear bit 0 - 16 - 1 - - - IOCB1 - Clear bit 1 - 17 - 1 - - - IOCB2 - Clear bit 2 - 18 - 1 - - - IOCB3 - Clear bit 3 - 19 - 1 - - - IOCB4 - Clear bit 4 - 20 - 1 - - - IOCB5 - Clear bit 5 - 21 - 1 - - - IOCB6 - Clear bit 6 - 22 - 1 - - - IOCB7 - Clear bit 7 - 23 - 1 - - - IOCB8 - Clear bit 8 - 24 - 1 - - - IOCB9 - Clear bit 9 - 25 - 1 - - - IOCB10 - Clear bit 10 - 26 - 1 - - - IOCB11 - Clear bit 11 - 27 - 1 - - - IOCB12 - Clear bit 12 - 28 - 1 - - - IOCB13 - Clear bit 13 - 29 - 1 - - - IOCB14 - Clear bit 14 - 30 - 1 - - - IOCB15 - Clear bit 15 - 31 - 1 - - - - - WPR - WPR - Port write protect - register - 0x1C - 0x20 - read-write - 0x00000000 - - - WPEN0 - Write protect enable 0 - 0 - 1 - - - WPEN1 - Write protect enable 1 - 1 - 1 - - - WPEN2 - Write protect enable 2 - 2 - 1 - - - WPEN3 - Write protect enable 3 - 3 - 1 - - - WPEN4 - Write protect enable 4 - 4 - 1 - - - WPEN5 - Write protect enable 5 - 5 - 1 - - - WPEN6 - Write protect enable 6 - 6 - 1 - - - WPEN7 - Write protect enable 7 - 7 - 1 - - - WPEN8 - Write protect enable 8 - 8 - 1 - - - WPEN9 - Write protect enable 9 - 9 - 1 - - - WPEN10 - Write protect enable 10 - 10 - 1 - - - WPEN11 - Write protect enable 11 - 11 - 1 - - - WPEN12 - Write protect enable 12 - 12 - 1 - - - WPEN13 - Write protect enable 13 - 13 - 1 - - - WPEN14 - Write protect enable 14 - 14 - 1 - - - WPEN15 - Write protect enable 15 - 15 - 1 - - - WPSEQ - Write protect sequence - 16 - 1 - - - - - MUXL - MUXL - GPIO muxing function low register - 0x20 - 0x20 - read-write - 0x00000000 - - - MUXL7 - GPIOx pin 7 muxing - 28 - 4 - - - MUXL6 - GPIOx pin 6 muxing - 24 - 4 - - - MUXL5 - GPIOx pin 5 muxing - 20 - 4 - - - MUXL4 - GPIOx pin 4 muxing - 16 - 4 - - - MUXL3 - GPIOx pin 3 muxing - 12 - 4 - - - MUXL2 - GPIOx pin 2 muxing - 8 - 4 - - - MUXL1 - GPIOx pin 1 muxing - 4 - 4 - - - MUXL0 - GPIOx pin 0 muxing - 0 - 4 - - - - - MUXH - MUXH - GPIO muxing function high register - 0x24 - 0x20 - read-write - 0x00000000 - - - MUXH15 - GPIOx pin 15 muxing - 28 - 4 - - - MUXH14 - GPIOx pin 14 muxing - 24 - 4 - - - MUXH13 - GPIOx pin 13 muxing - 20 - 4 - - - MUXH12 - GPIOx pin 12 muxing - 16 - 4 - - - MUXH11 - GPIOx pin 11 muxing - 12 - 4 - - - MUXH10 - GPIOx pin 10 muxing - 8 - 4 - - - MUXH9 - GPIOx pin 9 muxing - 4 - 4 - - - MUXH8 - GPIOx pin 8 muxing - 0 - 4 - - - - - CLR - CLR - GPIO bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - IOCB0 - Clear bit 0 - 0 - 1 - - - IOCB1 - Clear bit 1 - 1 - 1 - - - IOCB2 - Clear bit 2 - 2 - 1 - - - IOCB3 - Clear bit 3 - 3 - 1 - - - IOCB4 - Clear bit 4 - 4 - 1 - - - IOCB5 - Clear bit 5 - 5 - 1 - - - IOCB6 - Clear bit 6 - 6 - 1 - - - IOCB7 - Clear bit 7 - 7 - 1 - - - IOCB8 - Clear bit 8 - 8 - 1 - - - IOCB9 - Clear bit 9 - 9 - 1 - - - IOCB10 - Clear bit 10 - 10 - 1 - - - IOCB11 - Clear bit 11 - 11 - 1 - - - IOCB12 - Clear bit 12 - 12 - 1 - - - IOCB13 - Clear bit 13 - 13 - 1 - - - IOCB14 - Clear bit 14 - 14 - 1 - - - IOCB15 - Clear bit 15 - 15 - 1 - - - - - TOGR - TOGR - GPIO bit toggle register - 0x2C - 0x20 - write-only - 0x00000000 - - - IOTB0 - Toggle bit 0 - 0 - 1 - - - IOTB1 - Toggle bit 1 - 1 - 1 - - - IOTB2 - Toggle bit 2 - 2 - 1 - - - IOTB3 - Toggle bit 3 - 3 - 1 - - - IOTB4 - Toggle bit 4 - 4 - 1 - - - IOTB5 - Toggle bit 5 - 5 - 1 - - - IOTB6 - Toggle bit 6 - 6 - 1 - - - IOTB7 - Toggle bit 7 - 7 - 1 - - - IOTB8 - Toggle bit 8 - 8 - 1 - - - IOTB9 - Toggle bit 9 - 9 - 1 - - - IOTB10 - Toggle bit 10 - 10 - 1 - - - IOTB11 - Toggle bit 11 - 11 - 1 - - - IOTB12 - Toggle bit 12 - 12 - 1 - - - IOTB13 - Toggle bit 13 - 13 - 1 - - - IOTB14 - Toggle bit 14 - 14 - 1 - - - IOTB15 - Toggle bit 15 - 15 - 1 - - - - - HDRV - HDRV - Huge current driver - 0x3C - 0x20 - read-write - 0x00000000 - - - HDRV0 - Port x driver bit y - 0 - 1 - - - HDRV1 - Port x driver bit y - 1 - 1 - - - HDRV2 - Port x driver bit y - 2 - 1 - - - HDRV3 - Port x driver bit y - 3 - 1 - - - HDRV4 - Port x driver bit y - 4 - 1 - - - HDRV5 - Port x driver bit y - 5 - 1 - - - HDRV6 - Port x driver bit y - 6 - 1 - - - HDRV7 - Port x driver bit y - 7 - 1 - - - HDRV8 - Port x driver bit y - 8 - 1 - - - HDRV9 - Port x driver bit y - 9 - 1 - - - HDRV10 - Port x driver bit y - 10 - 1 - - - HDRV11 - Port x driver bit y - 11 - 1 - - - HDRV12 - Port x driver bit y - 12 - 1 - - - HDRV13 - Port x driver bit y - 13 - 1 - - - HDRV14 - Port x driver bit y - 14 - 1 - - - HDRV15 - Port x driver bit y - 15 - 1 - - - - - - - GPIOB - 0x40020400 - - - GPIOC - 0x40020800 - - - GPIOD - 0x40020C00 - - - GPIOE - 0x40021000 - - - GPIOF - 0x40021400 - - - EXINT - EXINT - EXINT - 0x40013C00 - - 0x0 - 0x400 - registers - - - EXINT0 - EXINT Line0 interrupt - 6 - - - EXINT1 - EXINT Line1 interrupt - 7 - - - EXINT2 - EXINT Line2 interrupt - 8 - - - EXINT3 - EXINT Line3 interrupt - 9 - - - EXINT4 - EXINT Line4 interrupt - 10 - - - EXINT9_5 - EXINT Line[9:5] interrupts - 23 - - - EXINT15_10 - EXINT Line[15:10] interrupts - 40 - - - PVM - PVM interrupt connect to EXINT line16 - 1 - - - ERTCALARM - ERTC Alarm interrupt connect to EXINT line17 - 41 - - - OTGFS1_WKUP - OTGFS1_WKUP interrupt connect to EXINT line18 - 42 - - - TAMPER - Tamper interrupt connect to EXINT line21 - 2 - - - ERTC_WKUP - ERTC Global interrupt connect to EXINT line22 - 3 - - - I2C1_EVT - I2C1_EVT interrupt connect to EXINT line23 - 31 - - - USART1 - ERTC Global interrupt connect to EXINT line25 - 37 - - - USART2 - ERTC Global interrupt connect to EXINT line26 - 38 - - - USART3 - USART3 Global interrupt connect to EXINT line28 - 39 - - - - INTEN - INTEN - Interrupt enable register - 0x0 - 0x20 - read-write - 0x00000000 - - - INTEN0 - Interrupt enable or disable on line 0 - 0 - 1 - - - INTEN1 - Interrupt enable or disable on line 1 - 1 - 1 - - - INTEN2 - Interrupt enable or disable on line 2 - 2 - 1 - - - INTEN3 - Interrupt enable or disable on line 3 - 3 - 1 - - - INTEN4 - Interrupt enable or disable on line 4 - 4 - 1 - - - INTEN5 - Interrupt enable or disable on line 5 - 5 - 1 - - - INTEN6 - Interrupt enable or disable on line 6 - 6 - 1 - - - INTEN7 - Interrupt enable or disable on line 7 - 7 - 1 - - - INTEN8 - Interrupt enable or disable on line 8 - 8 - 1 - - - INTEN9 - Interrupt enable or disable on line 9 - 9 - 1 - - - INTEN10 - Interrupt enable or disable on line 10 - 10 - 1 - - - INTEN11 - Interrupt enable or disable on line 11 - 11 - 1 - - - INTEN12 - Interrupt enable or disable on line 12 - 12 - 1 - - - INTEN13 - Interrupt enable or disable on line 13 - 13 - 1 - - - INTEN14 - Interrupt enable or disable on line 14 - 14 - 1 - - - INTEN15 - Interrupt enable or disable on line 15 - 15 - 1 - - - INTEN16 - Interrupt enable or disable on line 16 - 16 - 1 - - - INTEN17 - Interrupt enable or disable on line 17 - 17 - 1 - - - INTEN18 - Interrupt enable or disable on line 18 - 18 - 1 - - - INTEN21 - Interrupt enable or disable on line 21 - 21 - 1 - - - INTEN22 - Interrupt enable or disable on line 22 - 22 - 1 - - - INTEN23 - Interrupt enable or disable on line 23 - 23 - 1 - - - INTEN25 - Interrupt enable or disable on line 25 - 25 - 1 - - - INTEN26 - Interrupt enable or disable on line 26 - 26 - 1 - - - INTEN28 - Interrupt enable or disable on line 28 - 28 - 1 - - - - - EVTEN - EVTEN - Event enable register - 0x4 - 0x20 - read-write - 0x00000000 - - - EVTEN0 - Event enable or disable on line 0 - 0 - 1 - - - EVTEN1 - Event enable or disable on line 1 - 1 - 1 - - - EVTEN2 - Event enable or disable on line 2 - 2 - 1 - - - EVTEN3 - Event enable or disable on line 3 - 3 - 1 - - - EVTEN4 - Event enable or disable on line 4 - 4 - 1 - - - EVTEN5 - Event enable or disable on line 5 - 5 - 1 - - - EVTEN6 - Event enable or disable on line 6 - 6 - 1 - - - EVTEN7 - Event enable or disable on line 7 - 7 - 1 - - - EVTEN8 - Event enable or disable on line 8 - 8 - 1 - - - EVTEN9 - Event enable or disable on line 9 - 9 - 1 - - - EVTEN10 - Event enable or disable on line 10 - 10 - 1 - - - EVTEN11 - Event enable or disable on line 11 - 11 - 1 - - - EVTEN12 - Event enable or disable on line 12 - 12 - 1 - - - EVTEN13 - Event enable or disable on line 13 - 13 - 1 - - - EVTEN14 - Event enable or disable on line 14 - 14 - 1 - - - EVTEN15 - Event enable or disable on line 15 - 15 - 1 - - - EVTEN16 - Event enable or disable on line 16 - 16 - 1 - - - EVTEN17 - Event enable or disable on line 17 - 17 - 1 - - - EVTEN18 - Event enable or disable on line 18 - 18 - 1 - - - EVTEN21 - Event enable or disable on line 21 - 21 - 1 - - - EVTEN22 - Event enable or disable on line 22 - 22 - 1 - - - EVTEN23 - Event enable or disable on line 23 - 23 - 1 - - - EVTEN25 - Event enable or disable on line 25 - 25 - 1 - - - EVTEN26 - Event enable or disable on line 26 - 26 - 1 - - - EVTEN28 - Event enable or disable on line 28 - 28 - 1 - - - - - POLCFG1 - POLCFG1 - Rising polarity configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - RP0 - Rising polarity configuration bit of line 0 - 0 - 1 - - - RP1 - Rising polarity configuration bit of line 1 - 1 - 1 - - - RP2 - Rising polarity configuration bit of line 2 - 2 - 1 - - - RP3 - Rising polarity configuration bit of line 3 - 3 - 1 - - - RP4 - Rising polarity configuration bit of line 4 - 4 - 1 - - - RP5 - Rising polarity configuration bit of line 5 - 5 - 1 - - - RP6 - Rising polarity configuration bit of linee 6 - 6 - 1 - - - RP7 - Rising polarity configuration bit of line 7 - 7 - 1 - - - RP8 - Rising polarity configuration bit of line 8 - 8 - 1 - - - RP9 - Rising polarity configuration bit of line 9 - 9 - 1 - - - RP10 - Rising polarity configuration bit of line 10 - 10 - 1 - - - RP11 - Rising polarity configuration bit of line 11 - 11 - 1 - - - RP12 - Rising polarity configuration bit of line 12 - 12 - 1 - - - RP13 - Rising polarity configuration bit of line 13 - 13 - 1 - - - RP14 - Rising polarity configuration bit of line 14 - 14 - 1 - - - RP15 - Rising polarity configuration bit of line 15 - 15 - 1 - - - RP16 - Rising polarity configuration bit of line 16 - 16 - 1 - - - RP17 - Rising polarity configuration bit of line 17 - 17 - 1 - - - RP18 - Rising polarity configuration bit of line 18 - 18 - 1 - - - RP21 - Rising polarity configuration bit of line 21 - 21 - 1 - - - RP22 - Rising polarity configuration bit of line 22 - 22 - 1 - - - RP23 - Rising polarity configuration bit of line 23 - 23 - 1 - - - RP25 - Rising polarity configuration bit of line 25 - 25 - 1 - - - RP26 - Rising polarity configuration bit of line 26 - 26 - 1 - - - RP28 - Rising polarity configuration bit of line 28 - 28 - 1 - - - - - POLCFG2 - POLCFG2 - Falling polarity configuration register - 0xC - 0x20 - read-write - 0x00000000 - - - FP0 - Falling polarity event configuration bit of line 0 - 0 - 1 - - - FP1 - Falling polarity event configuration bit of line 1 - 1 - 1 - - - FP2 - Falling polarity event configuration bit of line 2 - 2 - 1 - - - FP3 - Falling polarity event configuration bit of line 3 - 3 - 1 - - - FP4 - Falling polarity event configuration bit of line 4 - 4 - 1 - - - FP5 - Falling polarity event configuration bit of line 5 - 5 - 1 - - - FP6 - Falling polarity event configuration bit of line 6 - 6 - 1 - - - FP7 - Falling polarity event configuration bit of line 7 - 7 - 1 - - - FP8 - Falling polarity event configuration bit of line 8 - 8 - 1 - - - FP9 - Falling polarity event configuration bit of line 9 - 9 - 1 - - - FP10 - Falling polarity event configuration bit of line 10 - 10 - 1 - - - FP11 - Falling polarity event configuration bit of line 11 - 11 - 1 - - - FP12 - Falling polarity event configuration bit of line 12 - 12 - 1 - - - FP13 - Falling polarity event configuration bit of line 13 - 13 - 1 - - - FP14 - Falling polarity event configuration bit of line 14 - 14 - 1 - - - FP15 - Falling polarity event configuration bit of line 15 - 15 - 1 - - - FP16 - Falling polarity event configuration bit of line 16 - 16 - 1 - - - FP17 - Falling polarity event configuration bit of line 17 - 17 - 1 - - - FP18 - Falling polarity event configuration bit of line 18 - 18 - 1 - - - FP21 - Falling polarity event configuration bit of line 21 - 21 - 1 - - - FP22 - Falling polarity event configuration bit of line 22 - 22 - 1 - - - FP23 - Falling polarity event configuration bit of line 23 - 23 - 1 - - - FP25 - Falling polarity event configuration bit of line 25 - 25 - 1 - - - FP26 - Falling polarity event configuration bit of line 26 - 26 - 1 - - - FP28 - Falling polarity event configuration bit of line 28 - 28 - 1 - - - - - SWTRG - SWTRG - Software triggle register - 0x10 - 0x20 - read-write - 0x00000000 - - - SWT0 - Software triggle on line 0 - 0 - 1 - - - SWT1 - Software triggle on line 1 - 1 - 1 - - - SWT2 - Software triggle on line 2 - 2 - 1 - - - SWT3 - Software triggle on line 3 - 3 - 1 - - - SWT4 - Software triggle on line 4 - 4 - 1 - - - SWT5 - Software triggle on line 5 - 5 - 1 - - - SWT6 - Software triggle on line 6 - 6 - 1 - - - SWT7 - Software triggle on line 7 - 7 - 1 - - - SWT8 - Software triggle on line 8 - 8 - 1 - - - SWT9 - Software triggle on line 9 - 9 - 1 - - - SWT10 - Software triggle on line 10 - 10 - 1 - - - SWT11 - Software triggle on line 11 - 11 - 1 - - - SWT12 - Software triggle on line 12 - 12 - 1 - - - SWT13 - Software triggle on line 13 - 13 - 1 - - - SWT14 - Software triggle on line 14 - 14 - 1 - - - SWT15 - Software triggle on line 15 - 15 - 1 - - - SWT16 - Software triggle on line 16 - 16 - 1 - - - SWT17 - Software triggle on line 17 - 17 - 1 - - - SWT18 - Software triggle on line 18 - 18 - 1 - - - SWT21 - Software triggle on line 21 - 21 - 1 - - - SWT22 - Software triggle on line 22 - 22 - 1 - - - SWT23 - Software triggle on line 233 - 23 - 1 - - - SWT25 - Software triggle on line 255 - 25 - 1 - - - SWT26 - Software triggle on line 26 - 26 - 1 - - - SWT28 - Software triggle on line 28 - 28 - 1 - - - - - INTSTS - INTSTS - Interrupt status register - 0x14 - 0x20 - read-write - 0x00000000 - - - LINE0 - Line 0 state bit - 0 - 1 - - - LINE1 - Line 1 state bit - 1 - 1 - - - LINE2 - Line 2 state bit - 2 - 1 - - - LINE3 - Line 3 state bit - 3 - 1 - - - LINE4 - Line 4 state bit - 4 - 1 - - - LINE5 - Line 5 state bit - 5 - 1 - - - LINE6 - Line 6 state bit - 6 - 1 - - - LINE7 - Line 7 state bit - 7 - 1 - - - LINE8 - Line 8 state bit - 8 - 1 - - - LINE9 - Line 9 state bit - 9 - 1 - - - LINE10 - Line 10 state bit - 10 - 1 - - - LINE11 - Line 11 state bit - 11 - 1 - - - LINE12 - Line 12 state bit - 12 - 1 - - - LINE13 - Line 13 state bit - 13 - 1 - - - LINE14 - Line 14 state bit - 14 - 1 - - - LINE15 - Line 15 state bit - 15 - 1 - - - LINE16 - Line 16 state bit - 16 - 1 - - - LINE17 - Line 17 state bit - 17 - 1 - - - LINE18 - Line 18 state bit - 18 - 1 - - - LINE21 - Line 21 state bit - 21 - 1 - - - LINE22 - Line 22 state bit - 22 - 1 - - - LINE23 - Line 23 state bit - 23 - 1 - - - LINE25 - Line 25 state bit - 25 - 1 - - - LINE26 - Line 26 state bit - 26 - 1 - - - LINE28 - Line 28 state bit - 28 - 1 - - - - - - - DMA1 - DMA controller - DMA - 0x40026000 - - 0x0 - 0x200 - registers - - - DMA1_Channel1 - DMA1 Channel1 global interrupt - 11 - - - DMA1_Channel2 - DMA1 Channel2 global interrupt - 12 - - - DMA1_Channel3 - DMA1 Channel3 global interrupt - 13 - - - DMA1_Channel4 - DMA1 Channel4 global interrupt - 14 - - - DMA1_Channel5 - DMA1 Channel5 global interrupt - 15 - - - DMA1_Channel6 - DMA1 Channel6 global interrupt - 16 - - - DMA1_Channel7 - DMA1 Channel7 global interrupt - 17 - - - - STS - STS - DMA interrupt status register - (DMA_STS) - 0x0 - 0x20 - read-only - 0x00000000 - - - GF1 - Channel 1 Global event flag - 0 - 1 - - - FDTF1 - Channel 1 full data transfer event flag - 1 - 1 - - - HDTF1 - Channel 1 half data transfer event flag - 2 - 1 - - - DTERRF1 - Channel 1 data transfer error event flag - 3 - 1 - - - GF2 - Channel 2 Global event flag - 4 - 1 - - - FDTF2 - Channel 2 full data transfer event flag - 5 - 1 - - - HDTF2 - Channel 2 half data transfer event flag - 6 - 1 - - - DTERRF2 - Channel 2 data transfer error event flag - 7 - 1 - - - GF3 - Channel 3 Global event flag - 8 - 1 - - - FDTF3 - Channel 3 full data transfer event flag - 9 - 1 - - - HDTF3 - Channel 3 half data transfer event flag - 10 - 1 - - - DTERRF3 - Channel 3 data transfer error event flag - 11 - 1 - - - GF4 - Channel 4 Global event flag - 12 - 1 - - - FDTF4 - Channel 4 full data transfer event flag - 13 - 1 - - - HDTF4 - Channel 4 half data transfer event flag - 14 - 1 - - - DTERRF4 - Channel 4 data transfer error event flag - 15 - 1 - - - GF5 - Channel 5 Global event flag - 16 - 1 - - - FDTF5 - Channel 5 full data transfer event flag - 17 - 1 - - - HDTF5 - Channel 5 half data transfer event flag - 18 - 1 - - - DTERRF5 - Channel 5 data transfer error event flag - 19 - 1 - - - GF6 - Channel 6 Global event flag - 20 - 1 - - - FDTF6 - Channel 6 full data transfer event flag - 21 - 1 - - - HDTF6 - Channel 6 half data transfer event flag - 22 - 1 - - - DTERRF6 - Channel 6 data transfer error event flag - 23 - 1 - - - GF7 - Channel 7 Global event flag - 24 - 1 - - - FDTF7 - Channel 7 full data transfer event flag - 25 - 1 - - - HDTF7 - Channel 7 half data transfer event flag - 26 - 1 - - - DTERRF7 - Channel 7 data transfer error event flag - 27 - 1 - - - - - CLR - CLR - DMA interrupt flag clear register - (DMA_CLR) - 0x4 - 0x20 - read-write - 0x00000000 - - - GFC1 - Channel 1 Global flag clear - 0 - 1 - - - GFC2 - Channel 2 Global flag clear - 4 - 1 - - - GFC3 - Channel 3 Global flag clear - 8 - 1 - - - GFC4 - Channel 4 Global flag clear - 12 - 1 - - - GFC5 - Channel 5 Global flag clear - 16 - 1 - - - GFC6 - Channel 6 Global flag clear - 20 - 1 - - - GFC7 - Channel 7 Global flag clear - 24 - 1 - - - FDTFC1 - Channel 1 full data transfer flag clear - 1 - 1 - - - FDTFC2 - Channel 2 full data transfer flag clear - 5 - 1 - - - FDTFC3 - Channel 3 full data transfer flag clear - 9 - 1 - - - FDTFC4 - Channel 4 full data transfer flag clear - 13 - 1 - - - FDTFC5 - Channel 5 full data transfer flag clear - 17 - 1 - - - FDTFC6 - Channel 6 full data transfer flag clear - 21 - 1 - - - FDTFC7 - Channel 7 full data transfer flag clear - 25 - 1 - - - HDTFC1 - Channel 1 half data transfer flag clear - 2 - 1 - - - HDTFC2 - Channel 2 half data transfer flag clear - 6 - 1 - - - HDTFC3 - Channel 3 half data transfer flag clear - 10 - 1 - - - HDTFC4 - Channel 4 half data transfer flag clear - 14 - 1 - - - HDTFC5 - Channel 5 half data transfer flag clear - 18 - 1 - - - HDTFC6 - Channel 6 half data transfer flag clear - 22 - 1 - - - HDTFC7 - Channel 7 half data transfer flag clear - 26 - 1 - - - DTERRFC1 - Channel 1 data transfer error flag clear - 3 - 1 - - - DTERRFC2 - Channel 2 data transfer error flag clear - 7 - 1 - - - DTERRFC3 - Channel 3 data transfer error flag clear - 11 - 1 - - - DTERRFC4 - Channel 4 data transfer error flag clear - 15 - 1 - - - DTERRFC5 - Channel 5 data transfer error flag clear - 19 - 1 - - - DTERRFC6 - Channel 6 data transfer error flag clear - 23 - 1 - - - DTERRFC7 - Channel 7 data transfer error flag clear - 27 - 1 - - - - - C1CTRL - C1CTRL - DMA channel configuration register(DMA_C1CTRL) - 0x8 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C1DTCNT - C1DTCNT - DMA channel 1 number of data to transfer register - 0xC - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C1PADDR - C1PADDR - DMA channel 1 peripheral base address register - 0x10 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C1MADDR - C1MADDR - DMA channel 1 memory base address register - 0x14 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C2CTRL - C2CTRL - DMA channel configuration register (DMA_C2CTRL) - 0x1C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C2DTCNT - C2DTCNT - DMA channel 2 number of data to transferregister - 0x20 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C2PADDR - C2PADDR - DMA channel 2 peripheral base address register - 0x24 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C2MADDR - C2MADDR - DMA channel 2 memory base address register - 0x28 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C3CTRL - C3CTRL - DMA channel configuration register (DMA_C3CTRL) - 0x30 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C3DTCNT - C3DTCNT - DMA channel 3 number of data to transfer register - 0x34 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C3PADDR - C3PADDR - DMA channel 3 peripheral base address register - 0x38 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C3MADDR - C3MADDR - DMA channel 3 memory base address register - 0x3C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C4CTRL - C4CTRL - DMA channel configuration register (DMA_C4CTRL) - 0x44 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C4DTCNT - C4DTCNT - DMA channel 4 number of data to transfer register - 0x48 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C4PADDR - C4PADDR - DMA channel 4 peripheral base address register - 0x4C - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C4MADDR - C4MADDR - DMA channel 4 memory base address register - 0x50 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C5CTRL - C5CTRL - DMA channel configuration register (DMA_C5CTRL) - 0x58 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C5DTCNT - C5DTCNT - DMA channel 5 number of data to transfer register - 0x5C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C5PADDR - C5PADDR - DMA channel 5 peripheral base address register - 0x60 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C5MADDR - C5MADDR - DMA channel 5 memory base address register - 0x64 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C6CTRL - C6CTRL - DMA channel configuration register(DMA_C6CTRL) - 0x6C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C6DTCNT - C6DTCNT - DMA channel 6 number of data to transfer register - 0x70 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C6PADDR - C6PADDR - DMA channel 6 peripheral address base register - 0x74 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C6MADDR - C6MADDR - DMA channel 6 memory address base register - 0x78 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C7CTRL - C7CTRL - DMA channel configuration register(DMA_C7CTRL) - 0x80 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C7DTCNT - C7DTCNT - DMA channel 7 number of data to transfer register - 0x84 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C7PADDR - C7PADDR - DMA channel 7 peripheral base address register - 0x88 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C7MADDR - C7MADDR - DMA channel 7 memory base address register - 0x8C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - DMA_MUXSEL - DMA_MUXSEL - DMAMUX Table Selection - 0x100 - 0x20 - 0x00000000 - - - TBL_SEL - Multiplexer Table Select - 0 - 1 - read-write - - - - - MUXC1CTRL - MUXC1CTRL - Channel 1 Configuration Register - 0x104 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC2CTRL - MUXC2CTRL - Channel 2 Configuration Register - 0x108 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC3CTRL - MUXC3CTRL - Channel 3 Configuration Register - 0x10C - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC4CTRL - MUXC4CTRL - Channel 4 Configuration Register - 0x110 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC5CTRL - MUXC5CTRL - Channel 5 Configuration Register - 0x114 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC6CTRL - MUXC6CTRL - Channel 6 Configuration Register - 0x118 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC7CTRL - MUXC7CTRL - Channel 7 Configuration Register - 0x11C - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXG1CTRL - MUXG1CTRL - Generator 1 Configuration Register - 0x120 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG2CTRL - MUXG2CTRL - Generator 2 Configuration Register - 0x124 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG3CTRL - MUXG3CTRL - Generator 3 Configuration Register - 0x128 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG4CTRL - MUXG4CTRL - Generator 4 Configuration Register - 0x12C - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXSYNCSTS - MUXSYNCSTS - Channel Interrupt Status Register - 0x130 - 0x20 - 0x00000000 - - - SYNCOVF1 - Synchronizaton overrun interrupt flag - 0 - 1 - read-only - - - SYNCOVF2 - Synchronizaton overrun interrupt flag - 1 - 1 - read-only - - - SYNCOVF3 - Synchronizaton overrun interrupt flag - 2 - 1 - read-only - - - SYNCOVF4 - Synchronizaton overrun interrupt flag - 3 - 1 - read-only - - - SYNCOVF5 - Synchronizaton overrun interrupt flag - 4 - 1 - read-only - - - SYNCOVF6 - Synchronizaton overrun interrupt flag - 5 - 1 - read-only - - - SYNCOVF7 - Synchronizaton overrun interrupt flag - 6 - 1 - read-only - - - - - MUXSYNCCLR - MUXSYNCCLR - Channel Interrupt Clear Flag Register - 0x134 - 0x20 - 0x00000000 - - - SYNCOVFC1 - Clear synchronizaton overrun interrupt flag - 0 - 1 - read-write - - - SYNCOVFC2 - Clear synchronizaton overrun interrupt flag - 1 - 1 - read-write - - - SYNCOVFC3 - Clear synchronizaton overrun interrupt flag - 2 - 1 - read-write - - - SYNCOVFC4 - Clear synchronizaton overrun interrupt flag - 3 - 1 - read-write - - - SYNCOVFC5 - Clear synchronizaton overrun interrupt flag - 4 - 1 - read-write - - - SYNCOVFC6 - Clear synchronizaton overrun interrupt flag - 5 - 1 - read-write - - - SYNCOVFC7 - Clear synchronizaton overrun interrupt flag - 6 - 1 - read-write - - - - - MUXGSTS - MUXGSTS - Generator Interrupt Status Register - 0x138 - 0x20 - 0x00000000 - - - TRGOVF1 - Trigger overrun interrupt flag - 0 - 1 - read-write - - - TRGOVF2 - Trigger overrun interrupt flag - 1 - 1 - read-write - - - TRGOVF3 - Trigger overrun interrupt flag - 2 - 1 - read-write - - - TRGOVF4 - Trigger overrun interrupt flag - 3 - 1 - read-write - - - - - MUXGCLR - MUXGCLR - Generator Interrupt Clear Flag Register - 0x13C - 0x20 - 0x00000000 - - - TRGOVFC1 - Clear trigger overrun interrupt flag - 0 - 1 - read-write - - - TRGOVFC2 - Clear trigger overrun interrupt flag - 1 - 1 - read-write - - - TRGOVFC3 - Clear trigger overrun interrupt flag - 2 - 1 - read-write - - - TRGOVFC4 - Clear trigger overrun interrupt flag - 3 - 1 - read-write - - - - - - - DMA2 - 0x40026400 - - - SDIO1 - Secure digital input/output - interface - SDIO - 0x4002C400 - - 0x0 - 0x400 - registers - - - SDIO1 - SDIO1 global interrupt - 49 - - - - PWRCTRL - PWRCTRL - Bits 1:0 = PWRCTRL: Power supply control - bits - 0x0 - 0x20 - read-write - 0x00000000 - - - PS - Power switch - 0 - 2 - - - - - CLKCTRL - CLKCTRL - SD clock control register - (SDIO_CLKCTRL) - 0x4 - 0x20 - read-write - 0x00000000 - - - CLKDIV - Clock division - 0 - 8 - - - CLKOEN - Clock output enable - 8 - 1 - - - PWRSVEN - Power saving mode enable - 9 - 1 - - - BYPSEN - Clock divider bypass enable - bit - 10 - 1 - - - BUSWS - Bus width selection - 11 - 2 - - - CLKEDS - SDIO_CK edge selection bit - 13 - 1 - - - HFCEN - Hardware flow control enable - 14 - 1 - - - CLKDIV98 - Clock divide factor bit9 and bit8 - 15 - 2 - - - - - ARGU - ARGU - Bits 31:0 = : Command argument - 0x8 - 0x20 - read-write - 0x00000000 - - - ARGU - Command argument - 0 - 32 - - - - - CMDCTRL - CMDCTRL - SDIO command control register - (SDIO_CMDCTRL) - 0xC - 0x20 - read-write - 0x00000000 - - - CMDIDX - CMDIDX - 0 - 6 - - - RSPWT - Wait for response - 6 - 2 - - - INTWT - CCSM wait for interrupt - 8 - 1 - - - PNDWT - CCSM wait for end of transfer - 9 - 1 - - - CCSMEN - Command channel state machine - 10 - 1 - - - IOSUSP - SD I/O suspend command - 11 - 1 - - - - - RSPCMD - RSPCMD - SDIO command register - 0x10 - 0x20 - read-only - 0x00000000 - - - RSPCMD - RSPCMD - 0 - 6 - - - - - RSP1 - RSP1 - Bits 31:0 = CARDSTATUS1 - 0x14 - 0x20 - read-only - 0x00000000 - - - CARDSTS1 - CARDSTATUS1 - 0 - 32 - - - - - RSP2 - RSP2 - Bits 31:0 = CARDSTATUS2 - 0x18 - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS2 - 0 - 32 - - - - - RSP3 - RSP3 - Bits 31:0 = CARDSTATUS3 - 0x1C - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS3 - 0 - 32 - - - - - RSP4 - RSP4 - Bits 31:0 = CARDSTATUS4 - 0x20 - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS4 - 0 - 32 - - - - - DTTMR - DTTMR - Bits 31:0 = TIMEOUT: Data timeout - period - 0x24 - 0x20 - read-write - 0x00000000 - - - TIMEOUT - Data timeout period - 0 - 32 - - - - - DTLEN - DTLEN - Bits 24:0 = DATALENGTH: Data length - value - 0x28 - 0x20 - read-write - 0x00000000 - - - DTLEN - Data length value - 0 - 25 - - - - - DTCTRL - DTCTRL - SDIO data control register - (SDIO_DCTRL) - 0x2C - 0x20 - read-write - 0x00000000 - - - TFREN - DTEN - 0 - 1 - - - TFRDIR - DTDIR - 1 - 1 - - - TFRMODE - DTMODE - 2 - 1 - - - DMAEN - DMAEN - 3 - 1 - - - BLKSIZE - DBLOCKSIZE - 4 - 4 - - - RDWTSTART - PWSTART - 8 - 1 - - - RDWTSTOP - PWSTOP - 9 - 1 - - - RDWTMODE - RWMOD - 10 - 1 - - - IOEN - SD I/O function enable - 11 - 1 - - - - - DTCNT - DTCNT - Bits 24:0 = DATACOUNT: Data count - value - 0x30 - 0x20 - read-only - 0x00000000 - - - CNT - Data count value - 0 - 25 - - - - - STS - STS - SDIO status register - (SDIO_STA) - 0x34 - 0x20 - read-only - 0x00000000 - - - CMDFAIL - Command crc fail - 0 - 1 - - - DTFAIL - Data crc fail - 1 - 1 - - - CMDTIMEOUT - Command timeout - 2 - 1 - - - DTTIMEOUT - Data timeout - 3 - 1 - - - TXERRU - Tx under run error - 4 - 1 - - - RXERRO - Rx over run error - 5 - 1 - - - CMDRSPCMPL - Command response complete - 6 - 1 - - - CMDCMPL - Command sent - 7 - 1 - - - DTCMPL - Data sent - 8 - 1 - - - SBITERR - Start bit error - 9 - 1 - - - DTBLKCMPL - Data block sent - 10 - 1 - - - DOCMD - Command transfer in progress - 11 - 1 - - - DOTX - Data transmit in progress - 12 - 1 - - - DORX - Data receive in progress - 13 - 1 - - - TXBUFH - Tx buffer half empty - 14 - 1 - - - RXBUFH - Rx buffer half empty - 15 - 1 - - - TXBUFF - Tx buffer full - 16 - 1 - - - RXBUFF - Rx buffer full - 17 - 1 - - - TXBUFE - Tx buffer empty - 18 - 1 - - - RXBUFE - Rx buffer empty - 19 - 1 - - - TXBUF - Tx data vaild - 20 - 1 - - - RXBUF - Rx data vaild - 21 - 1 - - - IOIF - SD I/O interrupt - 22 - 1 - - - - - INTCLR - INTCLR - SDIO interrupt clear register - (SDIO_INTCLR) - 0x38 - 0x20 - read-write - 0x00000000 - - - CMDFAIL - Command crc fail flag clear - 0 - 1 - - - DTFAIL - Data crc fail flag clear - 1 - 1 - - - CMDTIMEOUT - Command timeout flag clear - 2 - 1 - - - DTTIMEOUT - Data timeout flag clear - 3 - 1 - - - TXERRU - Tx under run error flag clear - 4 - 1 - - - RXERRU - Rx over run error flag clear - 5 - 1 - - - CMDRSPCMPL - Command response complete flag clear - 6 - 1 - - - CMDCMPL - Command sent flag clear - 7 - 1 - - - DTCMPL - Data sent flag clear - 8 - 1 - - - SBITERR - Start bit error flag clear - 9 - 1 - - - DTBLKCMPL - Data block sent clear - 10 - 1 - - - IOIF - SD I/O interrupt flag clear - 22 - 1 - - - - - INTEN - INTEN - SDIO mask register (SDIO_MASK) - 0x3C - 0x20 - read-write - 0x00000000 - - - CMDFAILIEN - Command crc fail interrupt enable - 0 - 1 - - - DTFAILIEN - Data crc fail interrupt enable - 1 - 1 - - - CMDTIMEOUTIEN - Command timeout interrupt enable - 2 - 1 - - - DTTIMEOUTIEN - Data timeout interrupt enable - 3 - 1 - - - TXERRUIEN - Tx under run interrupt enable - 4 - 1 - - - RXERRUIEN - Rx over run interrupt enable - 5 - 1 - - - CMDRSPCMPLIEN - Command response complete interrupt enable - 6 - 1 - - - CMDCMPLIEN - Command sent complete interrupt enable - 7 - 1 - - - DTCMPLIEN - Data sent complete interrupt enable - 8 - 1 - - - SBITERRIEN - Start bit error interrupt enable - 9 - 1 - - - DTBLKCMPLIEN - Data block sent complete interrupt enable - 10 - 1 - - - DOCMDIEN - Command acting interrupt enable - 11 - 1 - - - DOTXIEN - Data transmit acting interrupt enable - 12 - 1 - - - DORXIEN - Data receive acting interrupt enable - 13 - 1 - - - TXBUFHIEN - Tx buffer half empty interrupt enable - 14 - 1 - - - RXBUFHIEN - Rx buffer half empty interrupt enable - 15 - 1 - - - TXBUFFIEN - Tx buffer full interrupt enable - 16 - 1 - - - RXBUFFIEN - Rx buffer full interrupt enable - 17 - 1 - - - TXBUFEIEN - Tx buffer empty interrupt enable - 18 - 1 - - - RXBUFEIEN - Rx buffer empty interrupt enable - 19 - 1 - - - TXBUFIEN - Tx buffer data vaild interrupt enable - 20 - 1 - - - RXBUFIEN - Rx buffer data vaild interrupt enable - 21 - 1 - - - IOIFIEN - SD I/O interrupt enable - 22 - 1 - - - - - BUFCNT - BUFCNT - Bits 23:0 = BUFCOUNT: Remaining number of - words to be written to or read from the - FIFO - 0x48 - 0x20 - read-only - 0x00000000 - - - CNT - FIF0COUNT - 0 - 24 - - - - - BUF - BUF - bits 31:0 = Buffer Data: Receive and transmit - buffer data - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - Buffer data - 0 - 32 - - - - - - - SDIO2 - 0x50061000 - - SDIO2 - SDIO2 global interrupt - 102 - - - - ERTC - Real-time clock - ERTC - 0x40002800 - - 0x0 - 0x400 - registers - - - - TIME - TIME - time register - 0x0 - 0x20 - read-write - 0x00000000 - - - AMPM - AM/PM notation - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - DATE - DATE - date register - 0x4 - 0x20 - read-write - 0x00002101 - - - YT - Year tens - 20 - 4 - - - YU - Year units - 16 - 4 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - CTRL - CTRL - control register - 0x8 - 0x20 - read-write - 0x00000000 - - - CALOEN - Calibration output enable - 23 - 1 - - - OUTSEL - Output source selection - 21 - 2 - - - OUTP - Output polarity - 20 - 1 - - - CALOSEL - Calibration output selection - 19 - 1 - - - BPR - Battery power domain data register - 18 - 1 - - - DEC1H - Decrease 1 hour - 17 - 1 - - - ADD1H - Add 1 hour - 16 - 1 - - - TSIEN - Timestamp interrupt enable - 15 - 1 - - - WATIEN - Wakeup timer interrupt enable - 14 - 1 - - - ALBIEN - Alarm B interrupt enable - 13 - 1 - - - ALAIEN - Alarm A interrupt enable - 12 - 1 - - - TSEN - Timestamp enable - 11 - 1 - - - WATEN - Wakeup timer enable - 10 - 1 - - - ALBEN - Alarm B enable - 9 - 1 - - - ALAEN - Alarm A enable - 8 - 1 - - - CCALEN - Coarse calibration enable - 7 - 1 - - - HM - Hour mode - 6 - 1 - - - DREN - Date/time register direct read enable - 5 - 1 - - - RCDEN - Reference clock detection enable - 4 - 1 - - - TSEDG - Timestamp trigger edge - 3 - 1 - - - WATCLK - Wakeup timer clock selection - 0 - 3 - - - - - STS - STS - initialization and status - register - 0xC - 0x20 - 0x00000007 - - - ALAWF - Alarm A register allows write flag - 0 - 1 - read-only - - - ALBWF - Alarm B register allows write flag - 1 - 1 - read-only - - - WATWF - Wakeup timer register allows write flag - 2 - 1 - read-only - - - TADJF - Time adjustment flag - 3 - 1 - read-write - - - INITF - Calendar initialization flag - 4 - 1 - read-only - - - UPDF - Calendar update flag - 5 - 1 - read-write - - - IMF - Enter initialization mode flag - 6 - 1 - read-only - - - IMEN - Initialization mode enable - 7 - 1 - read-write - - - ALAF - Alarm A flag - 8 - 1 - read-write - - - ALBF - Alarm B flag - 9 - 1 - read-write - - - WATF - Wakeup timer flag - 10 - 1 - read-write - - - TSF - Timestamp flag - 11 - 1 - read-write - - - TSOF - Timestamp overflow flag - 12 - 1 - read-write - - - TP1F - Tamper detection 1 flag - 13 - 1 - read-write - - - TP2F - Tamper detection 2 flag - 14 - 1 - read-write - - - CALUPDF - Calibration value update completed flag - 16 - 1 - read-only - - - - - DIV - DIV - Diveder register - 0x10 - 0x20 - read-write - 0x007F00FF - - - DIVA - Diveder A - 16 - 7 - - - DIVB - Diveder B - 0 - 15 - - - - - WAT - WAT - Wakeup timer register - 0x14 - 0x20 - read-write - 0x0000FFFF - - - VAL - Wakeup timer reload value - 0 - 16 - - - - - CCAL - CCAL - Calibration register - 0x18 - 0x20 - read-write - 0x00000000 - - - CALDIR - Calibration direction - 7 - 1 - - - CALVAL - Calibration value - 0 - 5 - - - - - ALA - ALA - Alarm A register - 0x1C - 0x20 - read-write - 0x00000000 - - - MASK4 - Date/week mask - 31 - 1 - - - WKSEL - Date/week mode select - 30 - 1 - - - DT - Date tens - 28 - 2 - - - DU - Date units - 24 - 4 - - - MASK3 - Hours mask - 23 - 1 - - - AMPM - AM/PM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MASK2 - Minutes mask - 15 - 1 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - MASK1 - Seconds mask - 7 - 1 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - ALB - ALB - Alarm B register - 0x20 - 0x20 - read-write - 0x00000000 - - - MASK4 - Date/week mask - 31 - 1 - - - WKSEL - Date/week mode select - 30 - 1 - - - DT - Date tens - 28 - 2 - - - DU - Date units - 24 - 4 - - - MASK3 - Hours mask - 23 - 1 - - - AMPM - AM/PM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MASK2 - Minutes mask - 15 - 1 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - MASK1 - Seconds mask - 7 - 1 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - WP - WP - write protection register - 0x24 - 0x20 - write-only - 0x00000000 - - - CMD - Command register - 0 - 8 - - - - - SBS - SBS - sub second register - 0x28 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - TADJ - TADJ - time adjust register - 0x2C - 0x20 - write-only - 0x00000000 - - - ADD1S - Add 1 second - 31 - 1 - - - DECSBS - Decrease sub-second value - 0 - 15 - - - - - TSTM - TSTM - time stamp time register - 0x30 - 0x20 - read-only - 0x00000000 - - - AMPM - AMPM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - TSDT - TSDT - timestamp date register - 0x34 - 0x20 - read-only - 0x00000000 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - TSSBS - TSSBS - timestamp sub second register - 0x38 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - SCAL - SCAL - calibration register - 0x3C - 0x20 - read-write - 0x00000000 - - - ADD - Add ERTC clock - 15 - 1 - - - CAL8 - 8-second calibration period - 14 - 1 - - - CAL16 - 16 second calibration period - 13 - 1 - - - DEC - Decrease ERTC clock - 0 - 9 - - - - - TAMP - TAMP - tamper and alternate function configuration - register - 0x40 - 0x20 - read-write - 0x00000000 - - - OUTTYPE - Output type - 18 - 1 - - - TSPIN - Time stamp detection pin selection - 17 - 1 - - - TP1PIN - Tamper detection pin selection - 16 - 1 - - - TPPU - Tamper detection pull-up - 15 - 1 - - - TPPR - Tamper detection pre-charge time - 13 - 2 - - - TPFLT - Tamper detection filter time - 11 - 2 - - - TPFREQ - Tamper detection frequency - 8 - 3 - - - TPTSEN - Tamper detection timestamp enable - 7 - 1 - - - TP2EDG - Tamper detection 2 valid edge - 4 - 1 - - - TP2EN - Tamper detection 2 enable - 3 - 1 - - - TPIEN - Tamper detection interrupt enable - 2 - 1 - - - TP1EDG - Tamper detection 1 valid edge - 1 - 1 - - - TP1EN - Tamper detection 1 enable - 0 - 1 - - - - - ALASBS - ALASBS - alarm A sub second register - 0x44 - 0x20 - read-write - 0x00000000 - - - SBSMSK - Sub-second mask - 24 - 4 - - - SBS - Sub-seconds value - 0 - 15 - - - - - ALBSBS - ALBSBS - alarm B sub second register - 0x48 - 0x20 - read-write - 0x00000000 - - - SBSMSK - Sub-second mask - 24 - 4 - - - SBS - Sub-seconds value - 0 - 15 - - - - - BPR1DT - BPR1DT - Battery powered domain register - 0x50 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR2DT - BPR2DT - Battery powered domain register - 0x54 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR3DT - BPR3DT - Battery powered domain register - 0x58 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR4DT - BPR4DT - Battery powered domain register - 0x5C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR5DT - BPR5DT - Battery powered domain register - 0x60 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR6DT - BPR6DT - Battery powered domain register - 0x64 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR7DT - BPR7DT - Battery powered domain register - 0x68 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR8DT - BPR8DT - Battery powered domain register - 0x6C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR9DT - BPR9DT - Battery powered domain register - 0x70 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR10DT - BPR10DT - Battery powered domain register - 0x74 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR11DT - BPR11DT - Battery powered domain register - 0x78 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR12DT - BPR12DT - Battery powered domain register - 0x7C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR13DT - BPR13DT - Battery powered domain register - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR14DT - BPR14DT - Battery powered domain register - 0x84 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR15DT - BPR15DT - Battery powered domain register - 0x88 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR16DT - BPR16DT - Battery powered domain register - 0x8C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR17DT - BPR17DT - Battery powered domain register - 0x90 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR18DT - BPR18DT - Battery powered domain register - 0x94 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR19DT - BPR19DT - Battery powered domain register - 0x98 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR20DT - BPR20DT - Battery powered domain register - 0x9C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - - - WDT - Watchdog - WDT - 0x40003000 - - 0x0 - 0x400 - registers - - - - CMD - CMD - Command register - 0x0 - 0x20 - write-only - 0x00000000 - - - CMD - Command register - 0 - 16 - - - - - DIV - DIV - Division register - 0x4 - 0x20 - read-write - 0x00000000 - - - DIV - Division divider - 0 - 3 - - - - - RLD - RLD - Reload register - 0x8 - 0x20 - read-write - 0x00000FFF - - - RLD - Reload value - 0 - 12 - - - - - STS - STS - Status register - 0xC - 0x20 - read-only - 0x00000000 - - - DIVF - Division value update complete flag - 0 - 1 - - - RLDF - Reload value update complete flag - 1 - 1 - - - WINF - Window value update complete flag - 2 - 1 - - - - - WIN - WIN - Window register - 0x10 - 0x20 - read-write - 0x00000FFF - - - WIN - Window value - 0 - 12 - - - - - - - WWDT - Window watchdog - WWDT - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDT - Window Watchdog interrupt - 0 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - read-write - 0x0000007F - - - CNT - Decrement counter - 0 - 7 - - - WWDTEN - Window watchdog enable - 7 - 1 - - - - - CFG - CFG - Configuration register - 0x4 - 0x20 - read-write - 0x0000007F - - - WIN - Window value - 0 - 7 - - - DIV - Clock division value - 7 - 2 - - - RLDIEN - Reload counter interrupt - 9 - 1 - - - - - STS - STS - Status register - 0x8 - 0x20 - read-write - 0x00000000 - - - RLDF - Reload counter interrupt flag - 0 - 1 - - - - - - - TMR1 - Advanced timer - TIMER - 0x40010000 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - TMR1_CH - TMR1 channel interrupt - 27 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - TRGOUT2EN - TRGOUT2 enable - 31 - 1 - - - C4IOS - Channel 4 idle output state - 14 - 1 - - - C3CIOS - Channel 3 complementary idle output state - 13 - 1 - - - C3IOS - Channel 3 idle output state - 12 - 1 - - - C2CIOS - Channel 2 complementary idle output state - 11 - 1 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3CP - Channel 3 complementary polarity - 11 - 1 - - - C3CEN - Channel 3 complementary enable - 10 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - BKF - brake input filter - 16 - 4 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - CM3_OUTPUT - CM3_OUTPUT - Channel output mode register - 0x70 - 0x20 - read-write - 0x00000000 - - - C5OSEN - Channel 5 output switch enable - 7 - 1 - - - C5OCTRL - Channel 5 output control - 4 - 3 - - - C5OBEN - Channel 5 output buffer enable - 3 - 1 - - - C5OIEN - Channel 5 output immediately enable - 2 - 1 - - - - - C5DT - C5DT - Channel 5 data register - 0x74 - 0x20 - read-write - 0x00000000 - - - C5DT - Channel 5 data register - 0 - 16 - - - - - - - TMR2 - General purpose timer - TIMER - 0x40000000 - - 0x0 - 0x400 - registers - - - TMR2 - TMR2 global interrupt - 28 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PMEN - Plus Mode Enable - 10 - 1 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 32 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 32 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 32 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 32 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 32 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 32 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - TMR2_RMP - TMR2_RMP - TMR2 channel input remap register - 0x50 - 0x20 - read-write - 0x0000 - - - TMR2_CH1_IRMP - TMR2 channel 1 input remap - 10 - 2 - - - - - - - TMR3 - General purpose timer - TIMER - 0x40000400 - - 0x0 - 0x400 - registers - - - TMR3 - TMR3 global interrupt - 29 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR4 - 0x40000800 - - TMR4 - TMR4 global interrupt - 30 - - - - TMR9 - General purpose timer - TIMER - 0x40014000 - - 0x0 - 0x400 - registers - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C2CIOS - Channel 2 complementary idle output state - 11 - 1 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - BKF - brake input filter - 16 - 4 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR12 - 0x40001800 - - - TMR10 - General purpose timer - TIMER - 0x40014400 - - 0x0 - 0x400 - registers - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C1IEN - Channel 1 interrupt enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - BKF - brake input filter - 16 - 4 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR11 - 0x40014800 - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - - TMR13 - 0x40001C00 - - - TMR14 - 0x40002000 - - - RMP - RMP - TMR14 channel 1 input remap - 0x50 - 0x20 - read-write - 0x00000000 - - - TMR14_CH1_IRMP - TMR14 channel 1 input remap - 6 - 2 - - - - - - - TMR6 - Basic timer - TIMER - 0x40001000 - - 0x0 - 0x400 - registers - - - TMR6 - TMR6 global interrupt - 54 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - PTOS - Primary TMR output selection - 4 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - - - TMR7 - 0x40001400 - - TMR7 - TMR7 global interrupt - 55 - - - - ACC - HICK Auto Clock Calibration - ACC - 0x40017400 - - 0x0 - 0x400 - registers - - - - STS - STS - status register - 0x0 - 0x20 - 0x0000 - - - RSLOST - Reference Signal Lost - read-write - 1 - 1 - - - CALRDY - Internal high-speed clock calibration ready - read-write - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x04 - 0x20 - 0x0100 - - - STEP - STEP - read-write - 8 - 4 - - - CALRDYIEN - CALRDY interrupt enable - read-write - 5 - 1 - - - EIEN - RSLOST error interrupt enable - read-write - 4 - 1 - - - ENTRIM - Enable trim - read-write - 1 - 1 - - - CALON - Calibration on - read-write - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x08 - 0x20 - 0x2080 - - - HICKTWK - Internal high-speed auto clock trimming - read-only - 8 - 6 - - - HICKCAL - Internal high-speed auto clock calibration - read-only - 0 - 8 - - - - - C1 - C1 - compare value 1 - 0x0C - 0x20 - 0x1F2C - - - C1 - Compare 1 - read-write - 0 - 16 - - - - - C2 - C2 - compare value 2 - 0x10 - 0x20 - 0x1F40 - - - C2 - Compare 2 - read-write - 0 - 16 - - - - - C3 - C3 - compare value 3 - 0x14 - 0x20 - 0x1F54 - - - C3 - Compare 3 - read-write - 0 - 16 - - - - - - - I2C1 - Inter-integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1_EVT - I2C1 event interrupt - 31 - - - I2C1_ERR - I2C1 error interrupt - 32 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - 0x00000000 - - - I2CEN - I2C peripheral enable - 0 - 1 - read-write - - - TDIEN - Transmit data interrupt enable - 1 - 1 - read-write - - - RDIEN - Receive data interrupt enable - 2 - 1 - read-write - - - ADDRIEN - Address match interrupt enable - 3 - 1 - read-write - - - ACKFAILIEN - Acknowledge fail interrupt enable - 4 - 1 - read-write - - - STOPIEN - Stop generation complete interrupt enable - 5 - 1 - read-write - - - TDCIEN - Transfer data complete interrupt enable - 6 - 1 - read-write - - - ERRIEN - Error interrupts enable - 7 - 1 - read-write - - - DFLT - Digital filter value - 8 - 4 - read-write - - - DMATEN - DMA Transmit data request enable - 14 - 1 - read-write - - - DMAREN - DMA receive data request enable - 15 - 1 - read-write - - - SCTRL - Slave receiving data control - 16 - 1 - read-write - - - STRETCH - Clock stretching mode - 17 - 1 - read-write - - - GCAEN - General call address enable - 19 - 1 - read-write - - - HADDREN - SMBus host address enable - 20 - 1 - read-write - - - DEVADDREN - SMBus device default address enable - 21 - 1 - read-write - - - SMBALERT - SMBus alert enable / pin set - 22 - 1 - read-write - - - PECEN - PEC calculation enable - 23 - 1 - read-write - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - PECTEN - Request PEC transmission enable - 26 - 1 - - - ASTOPEN - Automatically send stop condition enable - 25 - 1 - - - RLDEN - Send data reload mode enable - 24 - 1 - - - CNT - Transmit data counter - 16 - 8 - - - NACKEN - Not acknowledge enable - 15 - 1 - - - GENSTOP - Generate stop condition - 14 - 1 - - - GENSTART - Generate start condition - 13 - 1 - - - READH10 - 10-bit address header read enable - 12 - 1 - - - ADDR10 - Host send 10-bit address mode enable - 11 - 1 - - - DIR - Master data transmission direction - 10 - 1 - - - SADDR - Slave address - 0 - 10 - - - - - OADDR1 - OADDR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x00000000 - - - ADDR1 - Interface address - 0 - 10 - - - ADDR1MODE - Own Address mode - 10 - 1 - - - ADDR1EN - Own address 1 enable - 15 - 1 - - - - - OADDR2 - OADDR2 - Own address register 2 - 0xC - 0x20 - read-write - 0x00000000 - - - ADDR2 - Own address 2 - 1 - 7 - - - ADDR2MASK - Own address 2-bit mask - 8 - 3 - - - ADDR2EN - Own address 2 enable - 15 - 1 - - - - - CLKCTRL - CLKCTRL - Clock contorl register - 0x10 - 0x20 - read-write - 0x00000000 - - - SCLL - SCL low level - 0 - 8 - - - SCLH - SCL high level - 8 - 8 - - - SDAD - SDA output delay - 16 - 4 - - - SCLD - SCL output delay - 20 - 4 - - - DIVH - High 4 bits of clock divider value - 24 - 4 - - - DIVL - Low 4 bits of clock divider value - 28 - 4 - - - - - TIMEOUT - TIMEOUT - Timeout register - 0x14 - 0x20 - read-write - 0x00000000 - - - TOTIME - Clock timeout detection time - 0 - 12 - - - TOMOED - Clock timeout detection mode - 12 - 1 - - - TOEN - Detect clock low/high timeout enable - 15 - 1 - - - EXTTIME - Cumulative clock low extend timeout value - 16 - 12 - - - EXTEN - Cumulative clock low extend timeout enable - 31 - 1 - - - - - STS - STS - Interrupt and Status register - 0x18 - 0x20 - 0x00000001 - - - ADDR - Slave address matching value - 17 - 7 - read-only - - - SDIR - Slave data transmit direction - 16 - 1 - read-only - - - BUSYF - Bus busy - 15 - 1 - read-only - - - ALERTF - SMBus alert flag - 13 - 1 - read-only - - - TMOUT - SMBus timeout flag - 12 - 1 - read-only - - - PECERR - PEC receive error flag - 11 - 1 - read-only - - - OUF - Overflow or underflow flag - 10 - 1 - read-only - - - ARLOST - Arbitration lost flag - 9 - 1 - read-only - - - BUSERR - Bus error flag - 8 - 1 - read-only - - - TCRLD - Transmission is complete, waiting to load data - 7 - 1 - read-only - - - TDC - Transmit data complete flag - 6 - 1 - read-only - - - STOPF - Stop condition generation complete flag - 5 - 1 - read-only - - - ACKFAIL - Acknowledge failure flag - 4 - 1 - read-only - - - ADDRF - 0~7 bit address match flag - 3 - 1 - read-only - - - RDBF - Receive data buffer full flag - 2 - 1 - read-only - - - TDIS - Send interrupt status - 1 - 1 - read-write - - - TDBE - Transmit data buffer empty flag - 0 - 1 - read-write - - - - - CLR - CLR - Interrupt clear register - 0x1C - 0x20 - write-only - 0x00000000 - - - ALERTC - Clear SMBus alert flag - 13 - 1 - - - TMOUTC - Clear SMBus timeout flag - 12 - 1 - - - PECERRC - Clear PEC receive error flag - 11 - 1 - - - OUFC - Clear overload / underload flag - 10 - 1 - - - ARLOSTC - Clear arbitration lost flag - 9 - 1 - - - BUSERRC - Clear bus error flag - 8 - 1 - - - STOPC - Clear stop condition generation complete flag - 5 - 1 - - - ACKFAILC - Clear acknowledge failure flag - 4 - 1 - - - ADDRC - Clear 0~7 bit address match flag - 3 - 1 - - - - - PEC - PEC - PEC register - 0x20 - 0x20 - read-only - 0x00000000 - - - PECVAL - PEC value - 0 - 8 - - - - - RXDT - RXDT - Receive data register - 0x24 - 0x20 - read-only - 0x00000000 - - - DT - Receive data register - 0 - 8 - - - - - TXDT - TXDT - Transmit data register - 0x28 - 0x20 - read-write - 0x00000000 - - - DT - Transmit data register - 0 - 8 - - - - - - - I2C2 - 0x40005800 - - I2C2_EVT - I2C2 event interrupt - 33 - - - I2C2_ERR - I2C2 error interrupt - 34 - - - - I2C3 - 0x40005C00 - - I2C3_EVT - I2C3 event interrupt - 72 - - - I2C3_ERR - I2C3 error interrupt - 73 - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global interrupt - 35 - - - - CTRL1 - CTRL1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SLBEN - Single line bidirectional half-duplex enable - 15 - 1 - - - SLBTD - Single line bidirectional half-duplex transmission direction - 14 - 1 - - - CCEN - CRC calculation enable - 13 - 1 - - - NTC - Next transmission CRC - 12 - 1 - - - FBN - frame bit num - 11 - 1 - - - ORA - Only receive active - 10 - 1 - - - SWCSEN - Software CS enable - 9 - 1 - - - SWCSIL - Software CS internal level - 8 - 1 - - - LTF - LSB transmit first - 7 - 1 - - - SPIEN - SPI enable - 6 - 1 - - - MDIV2_0 - Master clock frequency division bit2-0 - 3 - 3 - - - MSTEN - Master enable - 2 - 1 - - - CLKPOL - Clock polarity - 1 - 1 - - - CLKPHA - Clock phase - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MDIV3EN - Master clock frequency3 division enable - 9 - 1 - - - MDIV3 - Master clock frequency division bit3 - 8 - 1 - - - TDBEIE - Transmit data buffer empty interrupt enable - 7 - 1 - - - RDBFIE - Receive data buffer full interrupt enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - TIEN - TI mode enable - 4 - 1 - - - HWCSOE - Hardware CS output enable - 2 - 1 - - - DMATEN - DMA transmit enable - 1 - 1 - - - DMAREN - DMA receive enable - 0 - 1 - - - - - STS - STS - status register - 0x8 - 0x20 - 0x0002 - - - CSPAS - CS pulse abnormal setting fiag - 8 - 1 - read-write - - - BF - Busy flag - 7 - 1 - read-only - - - ROERR - Receiver overflow error - 6 - 1 - read-only - - - MMERR - Master mode error - 5 - 1 - read-only - - - CCERR - CRC calculation error - 4 - 1 - read-write - - - TUERR - Transmitter underload error - 3 - 1 - read-only - - - ACS - Audio channel state - 2 - 1 - read-only - - - TDBE - Transmit data buffer empty - 1 - 1 - read-only - - - RDBF - Receive data buffer full - 0 - 1 - read-only - - - - - DT - DT - data register - 0xC - 0x20 - read-write - 0x0000 - - - DT - Data value - 0 - 16 - - - - - CPOLY - CPOLY - CRC polynomial register - 0x10 - 0x20 - read-write - 0x0007 - - - CPOLY - CRC polynomial - 0 - 16 - - - - - RCRC - RCRC - Receive CRC register - 0x14 - 0x20 - read-only - 0x0000 - - - RCRC - Receive CRC - 0 - 16 - - - - - TCRC - TCRC - Transmit CRC register - 0x18 - 0x20 - read-only - 0x0000 - - - TCRC - Transmit CRC - 0 - 16 - - - - - I2SCTRL - I2SCTRL - I2S control register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SMSEL - I2S mode select - 11 - 1 - - - I2SEN - I2S Enable - 10 - 1 - - - OPERSEL - I2S operation select - 8 - 2 - - - PCMFSSEL - PCM frame synchronization select - 7 - 1 - - - STDSEL - I2S standard select - 4 - 2 - - - I2SCLKPOL - I2S clock polarity - 3 - 1 - - - I2SDBN - I2S data bit num - 1 - 2 - - - I2SCBN - I2S channel bit num - 0 - 1 - - - - - I2SCLKP - I2SCLKP - I2S clock register - 0x20 - 0x20 - read-write - 00000010 - - - I2SDIV9_8 - I2S division bit9 and bit8 - 10 - 2 - - - I2SMCLKOE - I2S master clock output enable - 9 - 1 - - - I2SODD - Odd result for I2S division - 8 - 1 - - - I2SDIV7_0 - I2S division bit7 to bit0 - 0 - 8 - - - - - - - SPI2 - 0x40003800 - - SPI2 - SPI2 global interrupt - 36 - - - - SPI3 - 0x40003C00 - - SPI3 - SPI3 global interrupt - 51 - - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40011000 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global interrupt - 37 - - - - STS - STS - Status register - 0x0 - 0x20 - 0x00C0 - - - CTSCF - CTS change flag - 9 - 1 - read-write - - - BFF - Break frame flag - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - 7 - 1 - read-only - - - TDC - Transmit data complete - 6 - 1 - read-write - - - RDBF - Receive data buffer full - 5 - 1 - read-write - - - IDLEF - IDLE flag - 4 - 1 - read-only - - - ROERR - Receiver overflow error - 3 - 1 - read-only - - - NERR - Noise error - 2 - 1 - read-only - - - FERR - Framing error - 1 - 1 - read-only - - - PERR - Parity error - 0 - 1 - read-only - - - - - DT - DT - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DT - Data value - 0 - 9 - - - - - BAUDR - BAUDR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV - Division - 0 - 16 - - - - - CTRL1 - CTRL1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - DBN1 - high bit for Data bit num - 28 - 1 - - - TSDT - transmit start delay time - 21 - 5 - - - TCDT - transmit complete delay time - 16 - 5 - - - UEN - USART enable - 13 - 1 - - - DBN0 - low bit for Data bit num - 12 - 1 - - - WUM - Wake up mode - 11 - 1 - - - PEN - Parity enable - 10 - 1 - - - PSEL - Parity selection - 9 - 1 - - - PERRIEN - PERR interrupt enable - 8 - 1 - - - TDBEIEN - TDBE interrupt enable - 7 - 1 - - - TDCIEN - TDC interrupt enable - 6 - 1 - - - RDBFIEN - RDBF interrupt enable - 5 - 1 - - - IDLEIEN - IDLE interrupt enable - 4 - 1 - - - TEN - Transmitter enable - 3 - 1 - - - REN - Receiver enable - 2 - 1 - - - RM - Receiver mute - 1 - 1 - - - SBF - Send break frame - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - ID7_4 - bit 7-4 for usart identification - 28 - 4 - - - TRPSWAP - Transmit receive pin swap - 15 - 1 - - - LINEN - LIN mode enable - 14 - 1 - - - STOPBN - STOP bit num - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CLKPOL - Clock polarity - 10 - 1 - - - CLKPHA - Clock phase - 9 - 1 - - - LBCP - Last bit clock pulse - 8 - 1 - - - BFIEN - Break frame interrupt enable - 6 - 1 - - - BFBN - Break frame bit num - 5 - 1 - - - IDBN - Identification bit num - 4 - 1 - - - ID3_0 - bit 3-0 for usart identification - 0 - 4 - - - - - CTRL3 - CTRL3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - DEP - DE polarity selection - 15 - 1 - - - RS485EN - RS485 enable - 14 - 1 - - - CTSCFIEN - CTSCF interrupt enable - 10 - 1 - - - CTSEN - CTS enable - 9 - 1 - - - RTSEN - RTS enable - 8 - 1 - - - DMATEN - DMA transmitter enable - 7 - 1 - - - DMAREN - DMA receiver enable - 6 - 1 - - - SCMEN - Smartcard mode enable - 5 - 1 - - - SCNACKEN - Smartcard NACK enable - 4 - 1 - - - SLBEN - Single line bidirectional half-duplex enable - 3 - 1 - - - IRDALP - IrDA low-power mode - 2 - 1 - - - IRDAEN - IrDA enable - 1 - 1 - - - ERRIEN - Error interrupt enable - 0 - 1 - - - - - GDIV - GDIV - Guard time and division register - 0x18 - 0x20 - read-write - 0x0000 - - - SCGT - Smart card guard time value - 8 - 8 - - - ISDIV - IrDA/smartcard division value - 0 - 8 - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global interrupt - 38 - - - - USART3 - 0x40004800 - - USART3 - USART3 global interrupt - 39 - - - - USART6 - 0x40011400 - - USART6 - USART6 global interrupt - 71 - - - - ADC1 - Analog to digital converter - ADC - 0x40012000 - - 0x0 - 0x100 - registers - - - ADC - ADC1 global interrupt - 18 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - RDY - ADC ready to conversion flag - 6 - 1 - read-only - - - OCCO - Ordinary channel conversion overflow flag - 5 - 1 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - OCCE - Ordinary channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCCOIEN - Ordinary channel conversion overflow interrupt enable - 26 - 1 - - - CRSEL - Conversion resolution select - 24 - 2 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - OCCEIEN - Ordinary channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - OCSWTRG - Ordinary channel software conversion trigger - 30 - 1 - - - OCETE - Ordinary channel external trigger edge select - 28 - 2 - - - OCTESEL - trigger event select for ordinary channels conversion - 24 - 4 - - - PCSWTRG - Preempted channel software conversion trigger - 22 - 1 - - - PCETE - Preempted channel external trigger edge select - 20 - 2 - - - PCTESEL - trigger event select for preempted channels conversion - 16 - 4 - - - DTALIGN - Data alignment - 11 - 1 - - - EOCSFEN - Each ordinary channel conversion set OCCE flag enable - 10 - 1 - - - OCDRCEN - Ordinary channel DMA request continuation enable for independent mode - 9 - 1 - - - OCDMAEN - Ordinary channel DMA transfer enable for independent mode - 8 - 1 - - - ADABRT - ADC conversion abort - 4 - 1 - - - ADCALINIT - Initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT18 - Selection sample time of channel ADC_IN18 - 24 - 3 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - SPT3 - SPT3 - sample time register 3 - 0x50 - 0x20 - read-write - 0x00000000 - - - CSPT27 - Selection sample time of channel ADC_IN27 - 21 - 3 - - - CSPT26 - Selection sample time of channel ADC_IN26 - 18 - 3 - - - CSPT25 - Selection sample time of channel ADC_IN25 - 15 - 3 - - - CSPT24 - Selection sample time of channel ADC_IN24 - 12 - 3 - - - CSPT23 - Selection sample time of channel ADC_IN23 - 9 - 3 - - - CSPT22 - Selection sample time of channel ADC_IN22 - 6 - 3 - - - CSPT21 - Selection sample time of channel ADC_IN21 - 3 - 3 - - - CSPT20 - Selection sample time of channel ADC_IN20 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 16 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 16 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 5 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - OSQ4 - OSQ4 - Ordinary sequence register 4 - 0x54 - 0x20 - read-write - 0x00000000 - - - OSN22 - Number of 22th conversion in ordinary sequence - 25 - 5 - - - OSN21 - Number of 21th conversion in ordinary sequence - 20 - 5 - - - OSN20 - Number of 20th conversion in ordinary sequence - 15 - 5 - - - OSN19 - number of 19rd conversion in ordinary sequence - 10 - 5 - - - OSN18 - Number of 18nd conversion in ordinary sequence - 5 - 5 - - - OSN17 - Number of 17st conversion in ordinary sequence - 0 - 5 - - - - - OSQ5 - OSQ5 - Ordinary sequence register 5 - 0x58 - 0x20 - read-write - 0x00000000 - - - OSN28 - Number of 28th conversion in ordinary sequence - 25 - 5 - - - OSN27 - Number of 27th conversion in ordinary sequence - 20 - 5 - - - OSN26 - Number of 26th conversion in ordinary sequence - 15 - 5 - - - OSN25 - number of 25rd conversion in ordinary sequence - 10 - 5 - - - OSN24 - Number of 24nd conversion in ordinary sequence - 5 - 5 - - - OSN23 - Number of 23st conversion in ordinary sequence - 0 - 5 - - - - - OSQ6 - OSQ6 - Ordinary sequence register 6 - 0x5C - 0x20 - read-write - 0x00000000 - - - OSN32 - Number of 32th conversion in ordinary sequence - 15 - 5 - - - OSN31 - number of 31rd conversion in ordinary sequence - 10 - 5 - - - OSN30 - Number of 30nd conversion in ordinary sequence - 5 - 5 - - - OSN29 - Number of 29st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - OVSP - OVSP - oversampling register - 0x80 - 0x20 - read-write - 0x00000000 - - - OOSRSEL - Ordinary oversampling recovery mode select - 10 - 1 - - - OOSTREN - Ordinary oversampling trigger mode enable - 9 - 1 - - - OSSSEL - Oversampling shift select - 5 - 4 - - - OSRSEL - Oversampling ratio select - 2 - 3 - - - POSEN - Preempted oversampling enable - 1 - 1 - - - OOSEN - Ordinary oversampling enable - 0 - 1 - - - - - CALVAL - CALVAL - Calibration value register - 0xB4 - 0x20 - read-write - 0x00000000 - - - CALVAL - A/D Calibration value - 0 - 7 - - - - - - - ADCCOM - ADC common area - ADC - 0x40012300 - - 0x0 - 0x100 - registers - - - - CSTS - CSTS - Common status register - 0x0 - 0x20 - read-only - 0x00000000 - - - RDY1 - ADC ready to conversion flag of ADC1 - 6 - 1 - - - OCCO1 - Ordinary channel conversion overflow flag of ADC1 - 5 - 1 - - - OCCS1 - Ordinary channel conversion start flag of ADC1 - 4 - 1 - - - PCCS1 - Preempted channel conversion start flag of ADC1 - 3 - 1 - - - PCCE1 - Preempted channels conversion end flag of ADC1 - 2 - 1 - - - OCCE1 - Ordinary channels conversion end flag of ADC1 - 1 - 1 - - - VMOR1 - Voltage monitoring out of range flag of ADC1 - 0 - 1 - - - - - CCTRL - CCTRL - Common control register - 0x4 - 0x20 - read-write - 0x00000000 - - - ITSRVEN - Internal temperature sensor and VINTRV enable - 23 - 1 - - - VBATEN - VBAT enable - 22 - 1 - - - ADCDIV - ADC division - 16 - 4 - - - - - - - CAN1 - Can controller area network - CAN - 0x40006400 - - 0x0 - 0x400 - registers - - - CAN1_TX - CAN1 TX interrupt - 19 - - - CAN1_RX0 - CAN1 RX0 interrupt - 20 - - - CAN_RX1 - CAN1 RX1 interrupt - 21 - - - CAN_SE - CAN1 SE interrupt - 22 - - - - MCTRL - MCTRL - Main control register - 0x0 - 0x20 - read-write - 0x00010002 - - - PTD - Prohibit transmission when debug - 16 - 1 - - - SPRST - Software partial reset - 15 - 1 - - - TTCEN - Time triggered communication mode enable - 7 - 1 - - - AEBOEN - Automatic exit bus-off enable - 6 - 1 - - - AEDEN - Automatic exit doze mode enable - 5 - 1 - - - PRSFEN - Prohibit retransmission when sending fails enable - 4 - 1 - - - MDRSEL - Message discarding rule select when overflow - 3 - 1 - - - MMSSR - Multiple message sending sequence rule - 2 - 1 - - - DZEN - Doze mode enable - 1 - 1 - - - FZEN - Freeze mode enable - 0 - 1 - - - - - MSTS - MSTS - Main status register - 0x4 - 0x20 - 0x00000C02 - - - REALRX - Real time level of RX pin - 11 - 1 - read-only - - - LSAMPRX - Last sample level of RX pin - 10 - 1 - read-only - - - CURS - Currently receiving status - 9 - 1 - read-only - - - CUSS - Currently sending status - 8 - 1 - read-only - - - EDZIF - Enter doze mode interrupt flag - 4 - 1 - read-write - - - QDZIF - Quit doze mode interrupt flag - 3 - 1 - read-write - - - EOIF - Error occur Interrupt flag - 2 - 1 - read-write - - - DZC - Doze mode confirm - 1 - 1 - read-only - - - FZC - Freeze mode confirm - 0 - 1 - read-only - - - - - TSTS - TSTS - Transmit status register - 0x8 - 0x20 - 0x1C000000 - - - TM2LPF - Transmit mailbox 2 lowest priority flag - 31 - 1 - read-only - - - TM1LPF - Transmit mailbox 1 lowest priority flag - 30 - 1 - read-only - - - TM0LPF - Transmit mailbox 0 lowest priority flag - 29 - 1 - read-only - - - TM2EF - Transmit mailbox 2 empty flag - 28 - 1 - read-only - - - TM1EF - Transmit mailbox 1 empty flag - 27 - 1 - read-only - - - TM0EF - Transmit mailbox 0 empty flag - 26 - 1 - read-only - - - TMNR - Transmit Mailbox number record - 24 - 2 - read-only - - - TM2CT - Transmit mailbox 2 cancel transmission - 23 - 1 - read-write - - - TM2TEF - Transmit mailbox 2 transmission error flag - 19 - 1 - read-write - - - TM2ALF - Transmit mailbox 2 arbitration lost flag - 18 - 1 - read-write - - - TM2TSF - Transmit mailbox 2 transmission success flag - 17 - 1 - read-write - - - TM2TCF - transmit mailbox 2 transmission complete flag - 16 - 1 - read-write - - - TM1CT - Transmit mailbox 1 cancel transmission - 15 - 1 - read-write - - - TM1TEF - Transmit mailbox 1 transmission error flag - 11 - 1 - read-write - - - TM1ALF - Transmit mailbox 1 arbitration lost flag - 10 - 1 - read-write - - - TM1TSF - Transmit mailbox 1 transmission success flag - 9 - 1 - read-write - - - TM1TCF - Transmit mailbox 1 transmission complete flag - 8 - 1 - read-write - - - TM0CT - Transmit mailbox 0 cancel transmission - 7 - 1 - read-write - - - TM0TEF - Transmit mailbox 0 transmission error flag - 3 - 1 - read-write - - - TM0ALF - Transmit mailbox 0 arbitration lost flag - 2 - 1 - read-write - - - TM0TSF - Transmit mailbox 0 transmission success flag - 1 - 1 - read-write - - - TM0TCF - Transmit mailbox 0 transmission complete flag - 0 - 1 - read-write - - - - - RF0 - RF0 - Receive FIFO 0 register - 0xC - 0x20 - 0x00000000 - - - RF0R - Receive FIFO 0 release - 5 - 1 - read-write - - - RF0OF - Receive FIFO 0 overflow flag - 4 - 1 - read-write - - - RF0FF - Receive FIFO 0 full flag - 3 - 1 - read-write - - - RF0MN - Receive FIFO 0 message num - 0 - 2 - read-only - - - - - RF1 - RF1 - Receive FIFO 1 register - 0x10 - 0x20 - 0x00000000 - - - RF1R - Receive FIFO 1 release - 5 - 1 - read-write - - - RF1OF - Receive FIFO 1 overflow flag - 4 - 1 - read-write - - - RF1FF - Receive FIFO 1 full flag - 3 - 1 - read-write - - - RF1MN - Receive FIFO 1 message num - 0 - 2 - read-only - - - - - INTEN - INTEN - Interrupt enable register - 0x14 - 0x20 - read-write - 0x00000000 - - - EDZIEN - Enter doze mode interrupt enable - 17 - 1 - - - QDZIEN - Quit doze mode interrupt enable - 16 - 1 - - - EOIEN - Error occur interrupt enable - 15 - 1 - - - ETRIEN - Error type record interrupt enable - 11 - 1 - - - BOIEN - Bus-off interrupt enable - 10 - 1 - - - EPIEN - Error passive interrupt enable - 9 - 1 - - - EAIEN - Error active interrupt enable - 8 - 1 - - - RF1OIEN - Receive FIFO 1 overflow interrupt enable - 6 - 1 - - - RF1FIEN - Receive FIFO 1 full interrupt enable - 5 - 1 - - - RF1MIEN - FIFO 1 receive message interrupt enable - 4 - 1 - - - RF0OIEN - Receive FIFO 0 overflow interrupt enable - 3 - 1 - - - RF0FIEN - Receive FIFO 0 full interrupt enable - 2 - 1 - - - RF0MIEN - FIFO 0 receive message interrupt enable - 1 - 1 - - - TCIEN - Transmission complete interrupt enable - 0 - 1 - - - - - ESTS - ESTS - Error status register - 0x18 - 0x20 - 0x00000000 - - - REC - Receive error counter - 24 - 8 - read-only - - - TEC - Transmit error counter - 16 - 8 - read-only - - - ETR - Error type record - 4 - 3 - read-write - - - BOF - Bus-off flag - 2 - 1 - read-only - - - EPF - Error passive flag - 1 - 1 - read-only - - - EAF - Error active flag - 0 - 1 - read-only - - - - - BTMG - BTMG - Bit timing register - 0x1C - 0x20 - read-write - 0x00000000 - - - LOEN - Listen-Only mode - 31 - 1 - - - LBEN - Loop back mode - 30 - 1 - - - RSAW - Resynchronization adjust width - 24 - 2 - - - BTS2 - Bit time segment 2 - 20 - 3 - - - BTS1 - Bit time segment 1 - 16 - 4 - - - BRDIV - Baud rate division - 0 - 12 - - - - - TMI0 - TMI0 - Transmit mailbox 0 identifier register - 0x180 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC0 - TMC0 - Transmit mailbox 0 data length and time stamp register - 0x184 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL0 - TMDTL0 - Transmit mailbox 0 low byte data register - 0x188 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH0 - TMDTH0 - Transmit mailbox 0 high byte data register - 0x18C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI1 - TMI1 - Transmit mailbox 1 identifier register - 0x190 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC1 - TMC1 - Transmit mailbox 1 data length and time stamp register - 0x194 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL1 - TMDTL1 - Transmit mailbox 1 low byte data register - 0x198 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH1 - TMDTH1 - Transmit mailbox 1 high byte data register - 0x19C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI2 - TMI2 - Transmit mailbox 2 identifier register - 0x1A0 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC2 - TMC2 - Transmit mailbox 2 data length and time stamp register - 0x1A4 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL2 - TMDTL2 - Transmit mailbox 2 low byte data register - 0x1A8 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH2 - TMDTH2 - Transmit mailbox 2 high byte data register - 0x1AC - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - RFI0 - RFI0 - Receive FIFO 0 register - 0x1B0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC0 - RFC0 - Receive FIFO 0 data length and time stamp register - 0x1B4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL0 - RFDTL0 - Receive FIFO 0 low byte data register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH0 - RFDTH0 - Receive FIFO 0 high byte data register - 0x1BC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - RFI1 - RFI1 - Receive FIFO 1 register - 0x1C0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC1 - RFC1 - Receive FIFO 1 data length and time stamp register - 0x1C4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL1 - RFDTL1 - Receive FIFO 1 low byte data register - 0x1C8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH1 - RFDTH1 - Receive FIFO 1 high byte data register - 0x1CC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - FCTRL - FCTRL - Filter control register - 0x200 - 0x20 - read-write - 0x00000000 - - - FCS - Filters configure switch - 0 - 1 - - - - - FMCFG - FMCFG - Filter mode config register - 0x204 - 0x20 - read-write - 0x00000000 - - - FMSEL0 - Filter mode select - 0 - 1 - - - FMSEL1 - Filter mode select - 1 - 1 - - - FMSEL2 - Filter mode select - 2 - 1 - - - FMSEL3 - Filter mode select - 3 - 1 - - - FMSEL4 - Filter mode select - 4 - 1 - - - FMSEL5 - Filter mode select - 5 - 1 - - - FMSEL6 - Filter mode select - 6 - 1 - - - FMSEL7 - Filter mode select - 7 - 1 - - - FMSEL8 - Filter mode select - 8 - 1 - - - FMSEL9 - Filter mode select - 9 - 1 - - - FMSEL10 - Filter mode select - 10 - 1 - - - FMSEL11 - Filter mode select - 11 - 1 - - - FMSEL12 - Filter mode select - 12 - 1 - - - FMSEL13 - Filter mode select - 13 - 1 - - - - - FBWCFG - FBWCFG - Filter bit width config register - 0x20C - 0x20 - read-write - 0x00000000 - - - FBWSEL0 - Filter bit width select - 0 - 1 - - - FBWSEL1 - Filter bit width select - 1 - 1 - - - FBWSEL2 - Filter bit width select - 2 - 1 - - - FBWSEL3 - Filter bit width select - 3 - 1 - - - FBWSEL4 - Filter bit width select - 4 - 1 - - - FBWSEL5 - Filter bit width select - 5 - 1 - - - FBWSEL6 - Filter bit width select - 6 - 1 - - - FBWSEL7 - Filter bit width select - 7 - 1 - - - FBWSEL8 - Filter bit width select - 8 - 1 - - - FBWSEL9 - Filter bit width select - 9 - 1 - - - FBWSEL10 - Filter bit width select - 10 - 1 - - - FBWSEL11 - Filter bit width select - 11 - 1 - - - FBWSEL12 - Filter bit width select - 12 - 1 - - - FBWSEL13 - Filter bit width select - 13 - 1 - - - - - FRF - FRF - Filter related FIFO register - 0x214 - 0x20 - read-write - 0x00000000 - - - FRFSEL0 - Filter relation FIFO select - 0 - 1 - - - FRFSEL1 - Filter relation FIFO select - 1 - 1 - - - FRFSEL2 - Filter relation FIFO select - 2 - 1 - - - FRFSEL3 - Filter relation FIFO select - 3 - 1 - - - FRFSEL4 - Filter relation FIFO select - 4 - 1 - - - FRFSEL5 - Filter relation FIFO select - 5 - 1 - - - FRFSEL6 - Filter relation FIFO select - 6 - 1 - - - FRFSEL7 - Filter relation FIFO select - 7 - 1 - - - FRFSEL8 - Filter relation FIFO select - 8 - 1 - - - FRFSEL9 - Filter relation FIFO select - 9 - 1 - - - FRFSEL10 - Filter relation FIFO select - 10 - 1 - - - FRFSEL11 - Filter relation FIFO select - 11 - 1 - - - FRFSEL12 - Filter relation FIFO select - 12 - 1 - - - FRFSEL13 - Filter relation FIFO select - 13 - 1 - - - - - FACFG - FACFG - Filter activate configuration register - 0x21C - 0x20 - read-write - 0x00000000 - - - FAEN0 - Filter activate enable - 0 - 1 - - - FAEN1 - Filter activate enable - 1 - 1 - - - FAEN2 - Filter activate enable - 2 - 1 - - - FAEN3 - Filter activate enable - 3 - 1 - - - FAEN4 - Filter activate enable - 4 - 1 - - - FAEN5 - Filter activate enable - 5 - 1 - - - FAEN6 - Filter activate enable - 6 - 1 - - - FAEN7 - Filter activate enable - 7 - 1 - - - FAEN8 - Filter activate enable - 8 - 1 - - - FAEN9 - Filter activate enable - 9 - 1 - - - FAEN10 - Filter activate enable - 10 - 1 - - - FAEN11 - Filter activate enable - 11 - 1 - - - FAEN12 - Filter activate enable - 12 - 1 - - - FAEN13 - Filter activate enable - 13 - 1 - - - - - F0FB1 - F0FB1 - Filter bank 0 filtrate bit register 1 - 0x240 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F0FB2 - F0FB2 - Filter bank 0 filtrate bit register 2 - 0x244 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB1 - F1FB1 - Filter bank 1 filtrate bit register 1 - 0x248 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB2 - F1FB2 - Filter bank 1 filtrate bit register 2 - 0x24C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB1 - F2FB1 - Filter bank 2 filtrate bit register 1 - 0x250 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB2 - F2FB2 - Filter bank 2 filtrate bit register 2 - 0x254 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB1 - F3FB1 - Filter bank 3 filtrate bit register 1 - 0x258 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB2 - F3FB2 - Filter bank 3 filtrate bit register 2 - 0x25C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB1 - F4FB1 - Filter bank 4 filtrate bit register 1 - 0x260 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB2 - F4FB2 - Filter bank 4 filtrate bit register 2 - 0x264 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB1 - F5FB1 - Filter bank 5 filtrate bit register 1 - 0x268 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB2 - F5FB2 - Filter bank 5 filtrate bit register 2 - 0x26C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB1 - F6FB1 - Filter bank 6 filtrate bit register 1 - 0x270 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB2 - F6FB2 - Filter bank 6 filtrate bit register 2 - 0x274 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB1 - F7FB1 - Filter bank 7 filtrate bit register 1 - 0x278 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB2 - F7FB2 - Filter bank 7 filtrate bit register 2 - 0x27C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB1 - F8FB1 - Filter bank 8 filtrate bit register 1 - 0x280 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB2 - F8FB2 - Filter bank 8 filtrate bit register 2 - 0x284 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB1 - F9FB1 - Filter bank 9 filtrate bit register 1 - 0x288 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB2 - F9FB2 - Filter bank 9 filtrate bit register 2 - 0x28C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB1 - F10FB1 - Filter bank 10 filtrate bit register 1 - 0x290 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB2 - F10FB2 - Filter bank 10 filtrate bit register 2 - 0x294 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB1 - F11FB1 - Filter bank 11 filtrate bit register 1 - 0x298 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB2 - F11FB2 - Filter bank 11 filtrate bit register 2 - 0x29C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB1 - F12FB1 - Filter bank 12 filtrate bit register 1 - 0x2A0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB2 - F12FB2 - Filter bank 12 filtrate bit register 2 - 0x2A4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB1 - F13FB1 - Filter bank 13 filtrate bit register 1 - 0x2A8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB2 - F13FB2 - Filter bank 13 filtrate bit register 2 - 0x2AC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - - CAN2 - 0x40006800 - - CAN2_TX - CAN2 TX interrupt - 63 - - - CAN2_RX0 - CAN2 RX0 interrupt - 64 - - - CAN2_RX1 - CAN2 RX1 interrupt - 65 - - - CAN2_SE - CAN2 SE interrupt - 66 - - - - DAC - Digital to analog converter - DAC - 0x40007400 - - 0x0 - 0x400 - registers - - - - CTRL - CTRL - Control register (DAC_CTRL) - 0x0 - 0x20 - read-write - 0x00000000 - - - D1EN - DAC1 enable - 0 - 1 - - - D1OBDIS - DAC1 output buffer disable - 1 - 1 - - - D1TRGEN - DAC1 trigger enable - 2 - 1 - - - D1TRGSEL - DAC1 trigger selection - 3 - 3 - - - D1NM - DAC1 noise/triangle wave generation enable - 6 - 2 - - - D1NBSEL - DAC1 mask/amplitude selector - 8 - 4 - - - D1DMAEN - DAC1 DMA enable - 12 - 1 - - - D1DMAUDRIEN - DAC1 DMA underrun interrupt enable - 13 - 1 - - - D2EN - DAC2 enable - 16 - 1 - - - D2OBDIS - DAC2 output buffer disable - 17 - 1 - - - D2TRGEN - DAC2 trigger enable - 18 - 1 - - - D2TRGSEL - DAC2 trigger selection - 19 - 3 - - - D2NM - DAC2 noise/triangle wave generation enable - 22 - 2 - - - D2NBSEL - DAC2 mask/amplitude selector - 24 - 4 - - - D2DMAEN - DAC2 DMA enable - 28 - 1 - - - D2DMAUDRIEN - DAC2 DMA underrun interrupt enable - 29 - 1 - - - - - SWTRG - SWTRG - DAC software trigger register(DAC_SWTRIGR) - 0x4 - 0x20 - write-only - 0x00000000 - - - D1SWTRG - DAC1 software trigger - 0 - 1 - - - D2SWTRG - DAC2 software trigger - 1 - 1 - - - - - D1DTH12R - D1DTH12R - DAC1 12-bit right-aligned data holding register(DAC_D1DTH12R) - 0x8 - 0x20 - read-write - 0x00000000 - - - D1DT12R - DAC1 12-bit right-aligned data - 0 - 12 - - - - - D1DTH12L - D1DTH12L - DAC1 12-bit left aligned data holding register (DAC_D1DTH12L) - 0xC - 0x20 - read-write - 0x00000000 - - - D1DT12L - DAC1 12-bit left-aligned data - 4 - 12 - - - - - D1DTH8R - D1DTH8R - DAC1 8-bit right aligned data holding register (DAC_D1DTH8R) - 0x10 - 0x20 - read-write - 0x00000000 - - - D1DT8R - DAC1 8-bit right-aligned data - 0 - 8 - - - - - D2DTH12R - D2DTH12R - DAC2 12-bit right aligned data holding register (DAC_D2DTH12R) - 0x14 - 0x20 - read-write - 0x00000000 - - - D2DT12R - DAC2 12-bit right-aligned - data - 0 - 12 - - - - - D2DTH12L - D2DTH12L - DAC2 12-bit left aligned data holding register (DAC_D2DTH12L) - 0x18 - 0x20 - read-write - 0x00000000 - - - D2DT12L - DAC2 12-bit left-aligned data - 4 - 12 - - - - - D2DTH8R - D2DTH8R - DAC2 8-bit right-aligned data holding register (DAC_D2DTH8R) - 0x1C - 0x20 - read-write - 0x00000000 - - - D2DT8R - DAC2 8-bit right-aligned - data - 0 - 8 - - - - - DDTH12R - DDTH12R - Dual DAC 12-bit right-aligned data holding register (DAC_DDTH12R), Bits 31:28 Reserved, Bits 15:12 Reserved - 0x20 - 0x20 - read-write - 0x00000000 - - - DD1DT12R - DAC1 12-bit right-aligned data - 0 - 12 - - - DD2DT12R - DAC2 12-bit right-aligned data - 16 - 12 - - - - - DDTH12L - DDTH12L - DUAL DAC 12-bit left aligned data holding register (DAC_DDTH12L), Bits 19:16 Reserved, Bits 3:0 Reserved - 0x24 - 0x20 - read-write - 0x00000000 - - - DD1DT12L - DAC1 12-bit left-aligned data - 4 - 12 - - - DD2DT12L - DAC2 12-bit right-aligned data - 20 - 12 - - - - - DDTH8R - DDTH8R - DUAL DAC 8-bit right aligned data holding register (DAC_DDTH8R), Bits 31:16 Reserved - 0x28 - 0x20 - read-write - 0x00000000 - - - DD1DT8R - DAC1 8-bit right-aligned data - 0 - 8 - - - DD2DT8R - DAC2 8-bit right-aligned data - 8 - 8 - - - - - D1ODT - D1ODT - DAC1 data output register (DAC_D1ODT) - 0x2C - 0x20 - read-only - 0x00000000 - - - D1ODT - DAC1 data output - 0 - 12 - - - - - D2ODT - D2ODT - DAC2 data output register (DAC_D2ODT) - 0x30 - 0x20 - read-only - 0x00000000 - - - D2ODT - DAC2 data output - 0 - 12 - - - - - STS - STS - DAC2 status register - (DAC_STS) - 0x34 - 0x20 - read-write - 0x00000000 - - - D1DMAUDRF - DAC1 DMA underrun flag - 13 - 1 - - - D2DMAUDRF - DAC2 DMA underrun flag - 29 - 1 - - - - - - - DEBUG - Debug support - DEBUG - 0xE0042000 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - DEBUG IDCODE - 0x0 - 0x20 - read-only - 0x0 - - - PID - Product ID - 0 - 32 - - - - - CTRL - CTRL - DEBUG CTRL - 0x4 - 0x20 - read-write - 0x0 - - - SLEEP_DEBUG - SLEEP_DEBUG - 0 - 1 - - - DEEPSLEEP_DEBUG - DEEPSLEEP_DEBUG - 1 - 1 - - - STANDBY_DEBUG - STANDBY_DEBUG - 2 - 1 - - - - - APB1_PAUSE - APB1_PAUSE - DEBUG APB1 PAUSE - 0x8 - 0x20 - read-write - 0x0 - - - TMR2_PAUSE - TMR2_PAUSE - 0 - 1 - - - TMR3_PAUSE - TMR3_PAUSE - 1 - 1 - - - TMR4_PAUSE - TMR4_PAUSE - 2 - 1 - - - TMR6_PAUSE - TMR6_PAUSE - 4 - 1 - - - TMR7_PAUSE - TMR7_PAUSE - 5 - 1 - - - TMR12_PAUSE - TMR12_PAUSE - 6 - 1 - - - TMR13_PAUSE - TMR13_PAUSE - 7 - 1 - - - TMR14_PAUSE - TMR14_PAUSE - 8 - 1 - - - ERTC_PAUSE - ERTC_PAUSE - 10 - 1 - - - WWDT_PAUSE - WWDT_PAUSE - 11 - 1 - - - WDT_PAUSE - WDT_PAUSE - 12 - 1 - - - ERTC512_PAUSE - ERTC512_PAUSE - 15 - 1 - - - I2C1_SMBUS_TIMEOUT - I2C1_SMBUS_TIMEOUT - 24 - 1 - - - CAN1_PAUSE - CAN1_PAUSE - 25 - 1 - - - CAN2_PAUSE - CAN2_PAUSE - 26 - 1 - - - I2C2_SMBUS_TIMEOUT - I2C2_SMBUS_TIMEOUT - 27 - 1 - - - I2C3_SMBUS_TIMEOUT - I2C3_SMBUS_TIMEOUT - 28 - 1 - - - - - APB2_PAUSE - APB2_PAUSE - DEBUG APB2 PAUSE - 0xC - 0x20 - read-write - 0x0 - - - TMR1_PAUSE - TMR1_PAUSE - 0 - 1 - - - TMR8_PAUSE - TMR8_PAUSE - 1 - 1 - - - TMR9_PAUSE - TMR9_PAUSE - 16 - 1 - - - TMR10_PAUSE - TMR10_PAUSE - 17 - 1 - - - TMR11_PAUSE - TMR11_PAUSE - 18 - 1 - - - - - SER_ID - SER_ID - SERIES ID - 0x20 - 0x20 - read-only - 0x0 - - - REV_ID - version ID - 0 - 3 - - - SER_ID - series ID - 8 - 8 - - - - - - - UART4 - Universal asynchronous receiver transmitter - 0x40004C00 - - UART4 - UART4 global interrupt - 52 - - - - UART5 - Universal asynchronous receiver transmitter - 0x40005000 - - UART5 - UART5 global interrupt - 53 - - - - UART7 - Universal asynchronous receiver transmitter - 0x40007800 - - UART7 - UART7 global interrupt - 82 - - - - UART8 - Universal asynchronous receiver transmitter - 0x40007C00 - - UART8 - UART8 global interrupt - 83 - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DT - DT - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DT - Data Register - 0 - 32 - - - - - CDT - CDT - Common data register - 0x4 - 0x20 - read-write - 0x00000000 - - - CDT - Common Data - 0 - 1 - - - - - CTRL - CTRL - Control register - 0x8 - 0x20 - read-write - 0x00000000 - - - RST - Reset bit - 0 - 1 - - - REVID - Reverse input data - 5 - 2 - - - REVOD - Reverse output data - 7 - 1 - - - - - IDT - IDT - Initial data register - 0x10 - 0x20 - read-write - 0xFFFFFFFF - - - IDT - Initial Data - 0 - 32 - - - - - - - FLASH - Flash memory controler - FLASH - 0x40023C00 - - 0x0 - 0x400 - registers - - - FLASH - Flash global interrupt - 4 - - - - PSR - PSR - Performance selection register - 0x0 - 0x20 - 0x00000330 - - - NZW_BST_STS - Flash non-zero wait area boost status - 13 - 1 - read-only - - - NZW_BST - Flash non-zero wait area boost - 12 - 1 - read-write - - - - - UNLOCK - UNLOCK - Unlock register - 0x4 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - USD_UNLOCK - USD_UNLOCK - USD unlock register - 0x8 - 0x20 - write-only - 0x00000000 - - - USD_UKVAL - User system data Unlock key value - 0 - 32 - - - - - STS - STS - Status register - 0xC - 0x20 - 0x00000000 - - - ODF - Operate done flag - 5 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - PRGMERR - program error - 2 - 1 - read-write - - - OBF - Operate busy flag - 0 - 1 - read-only - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - BLKERS - Block erase - 3 - 1 - - - USDPRGM - User system data program - 4 - 1 - - - USDERS - User system data erase - 5 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - USDULKS - User system data unlock success - 9 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR - ADDR - Address register - 0x14 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - USD - USD - User system data register - 0x1C - 0x20 - read-only - 0x03FFFFFC - - - USDERR - User system data error - 0 - 1 - - - FAP - FLASH access protection - 1 - 1 - - - nWDT_ATO_EN - WDT auto enable - 2 - 1 - - - nDEPSLP_RST - Deepsleep reset - 3 - 1 - - - nSTDBY_RST - Standby reset - 4 - 1 - - - BTOPT - boot option - 5 - 1 - - - nWDT_DEPSLP - WDT deep sleep - 7 - 1 - - - nWDT_STDBY - WDT standby - 8 - 1 - - - USER_D0 - User data 0 - 10 - 8 - - - USER_D1 - User data 1 - 18 - 8 - - - - - EPPS0 - EPPS0 - Erase/program protection status register 0 - 0x20 - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - EPPS1 - EPPS1 - Erase/program protection status register 1 - 0x2C - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - UNLOCK2 - UNLOCK2 - Unlock 2 register - 0x44 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - STS2 - STS2 - Status 2 register - 0x4C - 0x20 - 0x00000000 - - - OBF - Operate busy flag - 0 - 1 - read-only - - - PRGMERR - program error - 2 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - ODF - Operate done flag - 5 - 1 - read-write - - - - - CTRL2 - CTRL2 - Control 2 register - 0x50 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - BLKERS - Block erase - 3 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR2 - ADDR2 - Address 2 register - 0x54 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - CONTR - CONTR - Flash continue read register - 0x58 - 0x20 - read-write - 0x00000080 - - - FCONTR_EN - Flash continue read enable - 31 - 1 - - - - - DIVR - DIVR - Flash divider register - 0x60 - 0x20 - 0x00000022 - - - FDIV - Flash divider - 0 - 2 - read-write - - - FDIV_STS - Flash divider status - 4 - 2 - read-only - - - - - SLIB_STS2 - SLIB_STS2 - sLib status 2 register - 0xC8 - 0x20 - 0x0000FFFF - - - SLIB_INST_SS - sLib instruction start sector - 0 - 16 - read-only - - - - - SLIB_STS0 - SLIB_STS0 - sLib status 0 register - 0xCC - 0x20 - 0x00000000 - - - SLIB_ENF - sLib enabled flag - 3 - 1 - read-only - - - - - SLIB_STS1 - SLIB_STS1 - sLib status 1 register - 0xD0 - 0x20 - 0xFFFFFFFF - - - SLIB_SS - sLib start sector - 0 - 16 - read-only - - - SLIB_ES - sLib end sector - 16 - 16 - read-only - - - - - SLIB_PWD_CLR - SLIB_PWD_CLR - SLIB password clear register - 0xD4 - 0x20 - 0x00000000 - write-only - - - SLIB_PCLR_VAL - sLib password clear value - 0 - 32 - - - - - SLIB_MISC_STS - SLIB_MISC_STS - sLib misc status register - 0xD8 - 0x20 - 0x01000000 - - - SLIB_PWD_ERR - sLib password error - 0 - 1 - read-only - - - SLIB_PWD_OK - sLib password ok - 1 - 1 - read-only - - - SLIB_ULKF - sLib unlock flag - 2 - 1 - read-only - - - SLIB_RCNT - sLib remaining count - 16 - 9 - read-only - - - - - SLIB_SET_PWD - SLIB_SET_PWD - sLib password setting register - 0xDC - 0x20 - 0x00000000 - write-only - - - SLIB_PSET_VAL - sLib password setting val - 0 - 32 - - - - - SLIB_SET_RANGE0 - SLIB_SET_RANGE0 - Configure sLib range register 0 - 0xE0 - 0x20 - 0x00000000 - write-only - - - SLIB_SS_SET - sLib start sector setting - 0 - 16 - - - SLIB_ES_SET - sLib end sector setting - 16 - 16 - - - - - SLIB_SET_RANGE1 - SLIB_SET_RANGE1 - Configure sLib range register 1 - 0xE4 - 0x20 - 0x00000000 - write-only - - - SLIB_ISS_SET - sLib instruction start sector setting - 0 - 16 - - - SET_SLIB_STRT - sLib start setting - 31 - 1 - - - - - SLIB_UNLOCK - SLIB_UNLOCK - sLib unlock register - 0xF0 - 0x20 - 0x00000000 - write-only - - - SLIB_UKVAL - sLib unlock key value - 0 - 32 - - - - - CRC_CTRL - CRC_CTRL - CRC controler register - 0xF4 - 0x20 - 0x00000000 - write-only - - - CRC_SS - CRC start sector - 0 - 12 - - - CRC_SN - CRC sector numbler - 12 - 12 - - - CRC_STRT - CRC start - 31 - 1 - - - - - CRC_CHKR - CRC_CHKR - CRC check result register - 0xF8 - 0x20 - 0x00000000 - read-only - - - CRC_CHKR - CRC check result - 0 - 32 - - - - - - - NVIC - Nested Vectored Interrupt - Controller - NVIC - 0xE000E000 - - 0x0 - 0x1001 - registers - - - - ICTR - ICTR - Interrupt Controller Type - Register - 0x4 - 0x20 - read-only - 0x00000000 - - - INTLINESNUM - Total number of interrupt lines in - groups - 0 - 4 - - - - - STIR - STIR - Software Triggered Interrupt - Register - 0xF00 - 0x20 - write-only - 0x00000000 - - - INTID - interrupt to be triggered - 0 - 9 - - - - - ISER0 - ISER0 - Interrupt Set-Enable Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER1 - ISER1 - Interrupt Set-Enable Register - 0x104 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ICER0 - ICER0 - Interrupt Clear-Enable - Register - 0x180 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear-Enable - Register - 0x184 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x200 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x204 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending - Register - 0x280 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending - Register - 0x284 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - IABR0 - IABR0 - Interrupt Active Bit Register - 0x300 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IABR1 - IABR1 - Interrupt Active Bit Register - 0x304 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IPR0 - IPR0 - Interrupt Priority Register - 0x400 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR1 - IPR1 - Interrupt Priority Register - 0x404 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR2 - IPR2 - Interrupt Priority Register - 0x408 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR3 - IPR3 - Interrupt Priority Register - 0x40C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR4 - IPR4 - Interrupt Priority Register - 0x410 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR5 - IPR5 - Interrupt Priority Register - 0x414 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR6 - IPR6 - Interrupt Priority Register - 0x418 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR7 - IPR7 - Interrupt Priority Register - 0x41C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR8 - IPR8 - Interrupt Priority Register - 0x420 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR9 - IPR9 - Interrupt Priority Register - 0x424 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR10 - IPR10 - Interrupt Priority Register - 0x428 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR11 - IPR11 - Interrupt Priority Register - 0x42C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR12 - IPR12 - Interrupt Priority Register - 0x430 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR13 - IPR13 - Interrupt Priority Register - 0x434 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR14 - IPR14 - Interrupt Priority Register - 0x438 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - - - DVP - Digital video parallel interface - DVP - 0x50050000 - - 0x0 - 0x400 - registers - - - DVP - DVP global interrupt - 78 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - 0x0000 - - - LCDS - Line capture/drop selection - 20 - 1 - read-write - - - LCDC - Line capture/drop control - - 19 - 1 - read-write - - - PCDS - Pixel capture/drop selection - - 18 - 1 - read-write - - - PCDC - Basic pixel capture/drop control - - 16 - 2 - read-write - - - ENA - DVP enable - 14 - 1 - read-write - - - PDL - Pixel data length - 10 - 2 - read-write - - - BFRC - Basic frame rate control - 8 - 2 - read-write - - - VSP - Vertical synchronization - polarity - 7 - 1 - read-write - - - HSP - Horizontal synchronization polarity - - 6 - 1 - read-write - - - CKP - Pixel clock polarity - 5 - 1 - read-write - - - SM - synchronization mode - 4 - 1 - read-write - - - JPEG - JPEG format - 3 - 1 - read-write - - - CRP - Cropping function enable - 2 - 1 - read-write - - - CFM - Capture fire mode - 1 - 1 - read-write - - - CAP - Capture function enable - 0 - 1 - read-write - - - - - STS - STS - status register - 0x4 - 0x20 - read-only - 0x0000 - - - OFNE - Output FIFO Non-empty - 2 - 1 - - - VSYN - Vertical synchronization status - 1 - 1 - - - HSYN - Horizontal synchronization status - 0 - 1 - - - - - ESTS - ESTS - Event status register - 0x8 - 0x20 - read-only - 0x0000 - - - HSES - Horizontal synchronization event status - 4 - 1 - - - VSES - Vertical synchronization event status - 3 - 1 - - - ESEES - Embedded synchronization error event status - - 2 - 1 - - - OVRES - Data FIFO overrun event status - - 1 - 1 - - - CFDES - Capture frame done event status - - 0 - 1 - - - - - IENA - IENA - interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - HSIE - Horizontal synchronization interrupt enable - - 4 - 1 - - - VSIE - Vertical synchronization interrupt enablee - - 3 - 1 - - - ESEIE - Embedded synchronization error interrupt - enable - 2 - 1 - - - OVRIE - Data FIFO overrun interrupt enable - - 1 - 1 - - - CFDIE - Capture frame done interrupt enable - - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-only - 0x0000 - - - HSIS - Horizontal synchronization interrupt - status - 4 - 1 - - - VSIS - Vertical synchronization interrupt - status - 3 - 1 - - - ESEIS - Embedded synchronization error - interrupt status - 2 - 1 - - - OVRIS - Data FIFO overrun interrupt - status - 1 - 1 - - - CFDIS - Capture frame done interrupt - status - 0 - 1 - - - - - ICLR - ICLR - Interrupt clear register - 0x14 - 0x20 - write-only - 0x0000 - - - HSIC - Horizontal synchronization - interrupt clear - 4 - 1 - - - VSIC - Vertical synchronization - interrupt clear - 3 - 1 - - - ESEIC - Embedded synchronization - error interrupt clear - 2 - 1 - - - OVRIC - Data FIFO overrun - interrupt clear - 1 - 1 - - - CFDIC - Capture frame done - interrupt clear - 0 - 1 - - - - - SCR - SCR - Synchronization code - register - 0x18 - 0x20 - read-write - 0x0000 - - - FMEC - Frame end code - 24 - 8 - - - LNEC - Line end code - 16 - 8 - - - LNSC - Line start code - 8 - 8 - - - FMSC - Frame start code - 0 - 8 - - - - - SUR - SUR - Synchronization unmask - register - 0x1C - 0x20 - read-write - 0x0000 - - - FMEU - Frame end unmask - 24 - 8 - - - LNEU - Line end unmask - 16 - 8 - - - LNSU - Line start unmask - - 8 - 8 - - - FMSU - Frame start unmask - - 0 - 8 - - - - - CWST - CWST - Crop window start - 0x20 - 0x20 - read-write - 0x0000 - - - CVSTR - Cropping window vertical start line - - 16 - 13 - - - CHSTR - Cropping window horizontal start pixel - - 0 - 14 - - - - - CWSZ - CWSZ - Crop window size - 0x24 - 0x20 - read-write - 0x0000 - - - CVNUM - Cropping window vertical line number - - 16 - 14 - - - CHNUM - Cropping window horizontal pixel number - - 0 - 14 - - - - - DT - DT - Data register - 0x28 - 0x20 - read-only - 0x0000 - - - DT - Data Port - 0 - 32 - - - - - ACTRL - ACTRL - Advanced Control register - - 0x40 - 0x20 - read-write - 0x0000 - - - VSEID - Vertical synchonization event and interrupt - definition - 17 - 1 - - - HSEID - Horizontal synchonization event and interrupt - definition - 16 - 1 - - - DMABT - DMA burst transfer configuration - - 12 - 1 - - - IDUS - Input data un-used setting - - 10 - 1 - - - IDUN - Input data un-used number - - 8 - 2 - - - EFDM - Enhanced function data format management - - 6 - 1 - - - EFDF - Enhanced function data format - - 4 - 2 - - - PCDES - Basic pixel capture/drop extended - selection - 3 - 1 - - - MIBE - Monochrome image binarization - enable - 2 - 1 - - - EFRCE - Enhanced frame rate control - enable - 1 - 1 - - - EISRE - Enhanced image scaling resize - enable - 0 - 1 - - - - - HSCF - HSCF - Horizontal scaling control flow - - 0x48 - 0x20 - read-write - 0x0000 - - - HSRTF - Horizontal scaling resize target factor - - 16 - 13 - - - HSRSF - Horizontal scaling resize source factor - - 0 - 13 - - - - - VSCF - VSCF - Vertical scaling control flow - - 0x4C - 0x20 - read-write - 0x0000 - - - VSRTF - Vertical scaling resize target factor - - 16 - 13 - - - VSRSF - Vertical scaling resize source factor - - 0 - 13 - - - - - FRF - FRF - Frame rate flow - - 0x50 - 0x20 - read-write - 0x0000 - - - EFRCTF - Enhanced frame rate control target factor - - 8 - 5 - - - EFRCSF - Enhanced frame rate contorl source factor - - 0 - 5 - - - - - BTH - BTH - Binarization threshold - - 0x54 - 0x20 - read-write - 0x0000 - - - MIBTHD - Monochrome image binarization threshold - - 0 - 8 - - - - - - - USB_OTGFS_GLOBAL - USB on-the-go full speed - USB_OTGFS - 0x50000000 - - 0x0 - 0x400 - registers - - - OTGFS1 - USB On The Go FS global - interrupt - 67 - - - - GOTGCTL - GOTGCTL - OTGFS control and status register - (OTGFS_GOTGCTL) - 0x0 - 0x20 - 0x00000800 - - - CONIDSTS - Connector ID status - 16 - 1 - read-only - - - CURMOD - Current Mode of Operation - 21 - 1 - read-only - - - - - GOTGINT - GOTGINT - OTGFS interrupt register - (OTGFS_GOTGINT) - 0x4 - 0x20 - 0x00000000 - - - SESENDDET - VBUS is deasserted - 2 - 1 - read-write - - - - - GAHBCFG - GAHBCFG - OTGFS AHB configuration register - (OTGFS_GAHBCFG) - 0x8 - 0x20 - read-write - 0x00000000 - - - GLBINTMSK - Global interrupt mask - 0 - 1 - - - NPTXFEMPLVL - Non-Periodic TxFIFO empty level - 7 - 1 - - - PTXFEMPLVL - Periodic TxFIFO empty - level - 8 - 1 - - - - - GUSBCFG - GUSBCFG - USB configuration register - (OTGFS_GUSBCFG) - 0xC - 0x20 - 0x00000A00 - - - TOUTCAL - FS timeout calibration - 0 - 3 - read-write - - - USBTRDTIM - USB turnaround time - 10 - 4 - read-write - - - FHSTMODE - Force host mode - 29 - 1 - read-write - - - FDEVMODE - Force device mode - 30 - 1 - read-write - - - COTXPKT - Corrupt Tx packet - 31 - 1 - read-write - - - - - GRSTCTL - GRSTCTL - OTGFS reset register - (OTGFS_GRSTCTL) - 0x10 - 0x20 - 0x20000000 - - - CSFTRST - Core soft reset - 0 - 1 - read-write - - - PIUSFTRST - PIU FS Dedicated Controller Soft Reset - 1 - 1 - read-write - - - FRMCNTRST - Host frame counter reset - 2 - 1 - read-write - - - RXFFLSH - RxFIFO flush - 4 - 1 - read-write - - - TXFFLSH - TxFIFO flush - 5 - 1 - read-write - - - TXFNUM - TxFIFO number - 6 - 5 - read-write - - - AHBIDLE - AHB master idle - 31 - 1 - read-only - - - - - GINTSTS - GINTSTS - OTGFS core interrupt register - (OTGFS_GINTSTS) - 0x14 - 0x20 - 0x04000020 - - - CURMOD - Current mode of operation - 0 - 1 - read-only - - - MODEMIS - Mode mismatch interrupt - 1 - 1 - read-write - - - OTGINT - OTG interrupt - 2 - 1 - read-only - - - SOF - Start of frame - 3 - 1 - read-write - - - RXFLVL - RxFIFO non-empty - 4 - 1 - read-only - - - NPTXFEMP - Non-periodic TxFIFO empty - 5 - 1 - read-only - - - GINNAKEFF - Global IN non-periodic NAK - effective - 6 - 1 - read-only - - - GOUTNAKEFF - Global OUT NAK effective - 7 - 1 - read-only - - - ERLYSUSP - Early suspend - 10 - 1 - read-write - - - USBSUSP - USB suspend - 11 - 1 - read-write - - - USBRST - USB reset - 12 - 1 - read-write - - - ENUMDONE - Enumeration done - 13 - 1 - read-write - - - ISOOUTDROP - Isochronous OUT packet dropped - interrupt - 14 - 1 - read-write - - - EOPF - End of periodic frame - interrupt - 15 - 1 - read-write - - - IEPTINT - IN endpoint interrupt - 18 - 1 - read-only - - - OEPTINT - OUT endpoint interrupt - 19 - 1 - read-only - - - INCOMPISOIN - Incomplete isochronous IN - transfer - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUT - Incomplete periodic transfer(Host - mode)/Incomplete isochronous OUT transfer(Device - mode) - 21 - 1 - read-write - - - PRTINT - Host port interrupt - 24 - 1 - read-only - - - HCHINT - Host channels interrupt - 25 - 1 - read-only - - - PTXFEMP - Periodic TxFIFO empty - 26 - 1 - read-only - - - CONIDSCHG - Connector ID status change - 28 - 1 - read-write - - - DISCONINT - Disconnect detected - interrupt - 29 - 1 - read-write - - - WKUPINT - Resume/remote wakeup detected - interrupt - 31 - 1 - read-write - - - - - GINTMSK - GINTMSK - OTG_FS interrupt mask register - (OTG_FS_GINTMSK) - 0x18 - 0x20 - 0x00000000 - - - MODEMISMSK - Mode mismatch interrupt - mask - 1 - 1 - read-write - - - OTGINTMSK - OTG interrupt mask - 2 - 1 - read-write - - - SOFMSK - Start of frame mask - 3 - 1 - read-write - - - RXFLVLMSK - Receive FIFO non-empty - mask - 4 - 1 - read-write - - - NPTXFEMPMSK - Non-periodic TxFIFO empty - mask - 5 - 1 - read-write - - - GINNAKEFFMSK - Global non-periodic IN NAK effective - mask - 6 - 1 - read-write - - - GOUTNAKEFFMSK - Global OUT NAK effective - mask - 7 - 1 - read-write - - - ERLYSUSPMSK - Early suspend mask - 10 - 1 - read-write - - - USBSUSPMSK - USB suspend mask - 11 - 1 - read-write - - - USBRSTMSK - USB reset mask - 12 - 1 - read-write - - - ENUMDONEMSK - Enumeration done mask - 13 - 1 - read-write - - - ISOOUTDROPMSK - Isochronous OUT packet dropped interrupt - mask - 14 - 1 - read-write - - - EOPFMSK - End of periodic frame interrupt - mask - 15 - 1 - read-write - - - IEPTINTMSK - IN endpoints interrupt - mask - 18 - 1 - read-write - - - OEPTINTMSK - OUT endpoints interrupt - mask - 19 - 1 - read-write - - - INCOMISOINMSK - Incomplete isochronous IN transfer - mask - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUTMSK - Incomplete periodic transfer mask(Host - mode)/Incomplete isochronous OUT transfer mask(Device - mode) - 21 - 1 - read-write - - - PRTINTMSK - Host port interrupt mask - 24 - 1 - read-write - - - HCHINTMSK - Host channels interrupt - mask - 25 - 1 - read-write - - - PTXFEMPMSK - Periodic TxFIFO empty mask - 26 - 1 - read-write - - - CONIDSCHGMSK - Connector ID status change - mask - 28 - 1 - read-write - - - DISCONINTMSK - Disconnect detected interrupt - mask - 29 - 1 - read-write - - - WKUPINTMSK - Resume/remote wakeup detected interrupt - mask - 31 - 1 - read-write - - - - - GRXSTSR_Device - GRXSTSR_Device - OTGFS Receive status debug read(Device - mode) - 0x1C - 0x20 - read-only - 0x00000000 - - - EPTNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - FN - Frame number - 21 - 4 - - - - - GRXSTSR_Host - GRXSTSR_Host - OTGFS Receive status debug read(Host - mode) - GRXSTSR_Device - 0x1C - 0x20 - read-only - 0x00000000 - - - CHNUM - Channel number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - - - GRXFSIZ - GRXFSIZ - OTGFS Receive FIFO size register - (OTGFS_GRXFSIZ) - 0x24 - 0x20 - read-write - 0x00000200 - - - RXFDEP - RxFIFO depth - 0 - 16 - - - - - DIEPTXF0 - DIEPTXF0 - IN Endpoint TxFIFO 0 transmit FIFO size - register (Device mode) - 0x28 - 0x20 - read-write - 0x00000200 - - - INEPT0TXSTADDR - Endpoint 0 transmit RAM start - address - 0 - 16 - - - INEPT0TXDEP - Endpoint 0 TxFIFO depth - 16 - 16 - - - - - GNPTXFSIZ - GNPTXFSIZ - OTGFS non-periodic transmit FIFO size - register (Host mode) - DIEPTXF0 - 0x28 - 0x20 - read-write - 0x00000200 - - - NPTXFSTADDR - Non-periodic Transmit RAM Start - address - 0 - 16 - - - NPTXFDEP - Non-periodic TxFIFO depth - 16 - 16 - - - - - GNPTXSTS - GNPTXSTS - OTGFS non-periodic transmit FIFO/queue - status register (OTGFS_GNPTXSTS) - 0x2C - 0x20 - read-only - 0x00080200 - - - NPTXFSPCAVAIL - Non-periodic TxFIFO space - available - 0 - 16 - - - NPTXQSPCAVAIL - Non-periodic transmit request queue - space available - 16 - 8 - - - NPTXQTOP - Top of the non-periodic transmit request - queue - 24 - 7 - - - - - GCCFG - GCCFG - OTGFS general core configuration register - (OTGFS_GCCFG) - 0x38 - 0x20 - read-write - 0x00000000 - - - PWRDOWN - Power down - 16 - 1 - - - LP_MODE - Low power mode - 17 - 1 - - - SOFOUTEN - SOF output enable - 20 - 1 - - - VBUSIG - VBUS Ignored - 21 - 1 - - - - - GUID - GUID - Product ID register - 0x3C - 0x20 - read-write - 0x00001000 - - - USERID - Product ID field - 0 - 32 - - - - - HPTXFSIZ - HPTXFSIZ - OTGFS Host periodic transmit FIFO size - register (OTGFS_HPTXFSIZ) - 0x100 - 0x20 - read-write - 0x02000600 - - - PTXFSTADDR - Host periodic TxFIFO start - address - 0 - 16 - - - PTXFSIZE - Host periodic TxFIFO depth - 16 - 16 - - - - - DIEPTXF1 - DIEPTXF1 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF1) - 0x104 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO1 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF2 - DIEPTXF2 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF2) - 0x108 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO2 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF3 - DIEPTXF3 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF3) - 0x10C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO3 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF4 - DIEPTXF4 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF4) - 0x110 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO4 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF5 - DIEPTXF5 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF5) - 0x114 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO5 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF6 - DIEPTXF6 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF6) - 0x118 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO6 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF7 - DIEPTXF7 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF7) - 0x11C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO7 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - - - USB_OTGFS_HOST - USB on the go full speed - USB_OTGFS - 0x50000400 - - 0x0 - 0x400 - registers - - - - HCFG - HCFG - OTGFS host configuration register - (OTGFS_HCFG) - 0x0 - 0x20 - 0x00000000 - - - FSLSPCLKSEL - FS/LS PHY clock select - 0 - 2 - read-write - - - FSLSSUPP - FS- and LS-only support - 2 - 1 - read-only - - - - - HFIR - HFIR - OTGFS Host frame interval - register - 0x4 - 0x20 - read-write - 0x0000EA60 - - - FRINT - Frame interval - 0 - 16 - - - - - HFNUM - HFNUM - OTGFS host frame number/frame time - remaining register (OTGFS_HFNUM) - 0x8 - 0x20 - read-only - 0x00003FFF - - - FRNUM - Frame number - 0 - 16 - - - FTREM - Frame time remaining - 16 - 16 - - - - - HPTXSTS - HPTXSTS - OTGFS_Host periodic transmit FIFO/queue - status register (OTGFS_HPTXSTS) - 0x10 - 0x20 - 0x00080100 - - - PTXFSPCAVAIL - Periodic transmit data FIFO space - available - 0 - 16 - read-write - - - PTXQSPCAVAIL - Periodic transmit request queue space - available - 16 - 8 - read-only - - - PTXQTOP - Top of the periodic transmit request - queue - 24 - 8 - read-only - - - - - HAINT - HAINT - OTGFS Host all channels interrupt - register - 0x14 - 0x20 - read-only - 0x00000000 - - - HAINT - Channel interrupts - 0 - 16 - - - - - HAINTMSK - HAINTMSK - OTGFS host all channels interrupt mask - register - 0x18 - 0x20 - read-write - 0x00000000 - - - HAINTMSK - Channel interrupt mask - 0 - 16 - - - - - HPRT - HPRT - OTGFS host port control and status register - (OTGFS_HPRT) - 0x40 - 0x20 - 0x00000000 - - - PRTCONSTS - Port connect status - 0 - 1 - read-only - - - PRTCONDET - Port connect detected - 1 - 1 - read-write - - - PRTENA - Port enable - 2 - 1 - read-write - - - PRTENCHNG - Port enable/disable change - 3 - 1 - read-write - - - PRTOVRCACT - Port overcurrent active - 4 - 1 - read-only - - - PRTOVRCCHNG - Port overcurrent change - 5 - 1 - read-write - - - PRTRES - Port resume - 6 - 1 - read-write - - - PRTSUSP - Port suspend - 7 - 1 - read-write - - - PRTRST - Port reset - 8 - 1 - read-write - - - PRTLNSTS - Port line status - 10 - 2 - read-only - - - PRTPWR - Port power - 12 - 1 - read-write - - - PRTTSTCTL - Port test control - 13 - 4 - read-write - - - PRTSPD - Port speed - 17 - 2 - read-only - - - - - HCCHAR0 - HCCHAR0 - OTGFS host channel-0 characteristics - register (OTGFS_HCCHAR0) - 0x100 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR1 - HCCHAR1 - OTGFS host channel-1 characteristics - register (OTGFS_HCCHAR1) - 0x120 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR2 - HCCHAR2 - OTGFS host channel-2 characteristics - register (OTGFS_HCCHAR2) - 0x140 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR3 - HCCHAR3 - OTGFS host channel-3 characteristics - register (OTGFS_HCCHAR3) - 0x160 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR4 - HCCHAR4 - OTGFS host channel-4 characteristics - register (OTGFS_HCCHAR4) - 0x180 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR5 - HCCHAR5 - OTGFS host channel-5 characteristics - register (OTGFS_HCCHAR5) - 0x1A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR6 - HCCHAR6 - OTGFS host channel-6 characteristics - register (OTGFS_HCCHAR6) - 0x1C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR7 - HCCHAR7 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR7) - 0x1E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR8 - HCCHAR8 - OTGFS host channel-8 characteristics - register (OTGFS_HCCHAR8) - 0x200 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR9 - HCCHAR9 - OTGFS host channel-9 characteristics - register (OTGFS_HCCHAR9) - 0x220 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR10 - HCCHAR10 - OTGFS host channel-10 characteristics - register (OTGFS_HCCHAR10) - 0x240 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR11 - HCCHAR11 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR11) - 0x260 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR12 - HCCHAR12 - OTGFS host channel-12 characteristics - register (OTGFS_HCCHAR12) - 0x280 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR13 - HCCHAR13 - OTGFS host channel-13 characteristics - register (OTGFS_HCCHAR13) - 0x2A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR14 - HCCHAR14 - OTGFS host channel-14 characteristics - register (OTGFS_HCCHAR14) - 0x2C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR15 - HCCHAR15 - OTGFS host channel-15 characteristics - register (OTGFS_HCCHAR15) - 0x2E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCINT0 - HCINT0 - OTGFS host channel-0 interrupt register - (OTGFS_HCINT0) - 0x108 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT1 - HCINT1 - OTG_FS host channel-1 interrupt register - (OTG_FS_HCINT1) - 0x128 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT2 - HCINT2 - OTGFS host channel-2 interrupt register - (OTGFS_HCINT2) - 0x148 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT3 - HCINT3 - OTGFS host channel-3 interrupt register - (OTGFS_HCINT3) - 0x168 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT4 - HCINT4 - OTGFS host channel-4 interrupt register - (OTGFS_HCINT4) - 0x188 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT5 - HCINT5 - OTGFS host channel-5 interrupt register - (OTGFS_HCINT5) - 0x1A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT6 - HCINT6 - OTGFS host channel-6 interrupt register - (OTGFS_HCINT6) - 0x1C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT7 - HCINT7 - OTGFS host channel-7 interrupt register - (OTGFS_HCINT7) - 0x1E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT8 - HCINT8 - OTGFS host channel-8 interrupt register - (OTGFS_HCINT8) - 0x208 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT9 - HCINT9 - OTGFS host channel-9 interrupt register - (OTGFS_HCINT9) - 0x228 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT10 - HCINT10 - OTGFS host channel-10 interrupt register - (OTGFS_HCINT10) - 0x248 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT11 - HCINT11 - OTGFS host channel-11 interrupt register - (OTGFS_HCINT11) - 0x268 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT12 - HCINT12 - OTGFS host channel-12 interrupt register - (OTGFS_HCINT12) - 0x288 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT13 - HCINT13 - OTGFS host channel-13 interrupt register - (OTGFS_HCINT13) - 0x2A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT14 - HCINT14 - OTGFS host channel-14 interrupt register - (OTGFS_HCINT14) - 0x2C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT15 - HCINT15 - OTGFS host channel-15 interrupt register - (OTGFS_HCINT15) - 0x2E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINTMSK0 - HCINTMSK0 - OTGFS host channel-0 mask register - (OTGFS_HCINTMSK0) - 0x10C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK1 - HCINTMSK1 - OTGFS host channel-1 mask register - (OTGFS_HCINTMSK1) - 0x12C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK2 - HCINTMSK2 - OTGFS host channel-2 mask register - (OTGFS_HCINTMSK2) - 0x14C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK3 - HCINTMSK3 - OTGFS host channel-3 mask register - (OTGFS_HCINTMSK3) - 0x16C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK4 - HCINTMSK4 - OTGFS host channel-4 mask register - (OTGFS_HCINTMSK4) - 0x18C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK5 - HCINTMSK5 - OTGFS host channel-5 mask register - (OTGFS_HCINTMSK5) - 0x1AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK6 - HCINTMSK6 - OTGFS host channel-6 mask register - (OTGFS_HCINTMSK6) - 0x1CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK7 - HCINTMSK7 - OTGFS host channel-7 mask register - (OTGFS_HCINTMSK7) - 0x1EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK8 - HCINTMSK8 - OTGFS host channel-8 mask register - (OTGFS_HCINTMSK8) - 0x20C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK9 - HCINTMSK9 - OTGFS host channel-9 mask register - (OTGFS_HCINTMSK9) - 0x22C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK10 - HCINTMSK10 - OTGFS host channel-10 mask register - (OTGFS_HCINTMSK10) - 0x24C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK11 - HCINTMSK11 - OTGFS host channel-11 mask register - (OTGFS_HCINTMSK11) - 0x26C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK12 - HCINTMSK12 - OTGFS host channel-12 mask register - (OTGFS_HCINTMSK12) - 0x28C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK13 - HCINTMSK13 - OTGFS host channel-13 mask register - (OTGFS_HCINTMSK13) - 0x2AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK14 - HCINTMSK14 - OTGFS host channel-14 mask register - (OTGFS_HCINTMSK14) - 0x2CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK15 - HCINTMSK15 - OTGFS host channel-15 mask register - (OTGFS_HCINTMSK15) - 0x2EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCTSIZ0 - HCTSIZ0 - OTGFS host channel-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ1 - HCTSIZ1 - OTGFS host channel-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ2 - HCTSIZ2 - OTGFS host channel-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ3 - HCTSIZ3 - OTGFS host channel-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ4 - HCTSIZ4 - OTGFS host channel-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ5 - HCTSIZ5 - OTGFS host channel-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ6 - HCTSIZ6 - OTGFS host channel-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ7 - HCTSIZ7 - OTGFS host channel-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ8 - HCTSIZ8 - OTGFS host channel-8 transfer size - register - 0x210 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ9 - HCTSIZ9 - OTGFS host channel-9 transfer size - register - 0x230 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ10 - HCTSIZ10 - OTGFS host channel-10 transfer size - register - 0x250 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ11 - HCTSIZ11 - OTGFS host channel-11 transfer size - register - 0x270 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ12 - HCTSIZ12 - OTGFS host channel-12 transfer size - register - 0x290 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ13 - HCTSIZ13 - OTGFS host channel-13 transfer size - register - 0x2B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ14 - HCTSIZ14 - OTGFS host channel-14 transfer size - register - 0x2D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ15 - HCTSIZ15 - OTGFS host channel-15 transfer size - register - 0x2F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - - - USB_OTGFS_DEVICE - USB on the go full speed - USB_OTGFS - 0x50000800 - - 0x0 - 0x400 - registers - - - - DCFG - DCFG - OTGFS device configuration register - (OTGFS_DCFG) - 0x0 - 0x20 - read-write - 0x02200000 - - - DEVSPD - Device speed - 0 - 2 - - - NZSTSOUTHSHK - Non-zero-length status OUT - handshake - 2 - 1 - - - DEVADDR - Device address - 4 - 7 - - - PERFRINT - Periodic frame interval - 11 - 2 - - - - - DCTL - DCTL - OTGFS device control register - (OTGFS_DCTL) - 0x4 - 0x20 - 0x00000000 - - - RWKUPSIG - Remote wakeup signaling - 0 - 1 - read-write - - - SFTDISCON - Soft disconnect - 1 - 1 - read-write - - - GNPINNAKSTS - Global IN NAK status - 2 - 1 - read-only - - - GOUTNAKSTS - Global OUT NAK status - 3 - 1 - read-only - - - TSTCTL - Test control - 4 - 3 - read-write - - - SGNPINNAK - Set global IN NAK - 7 - 1 - read-write - - - CGNPINNAK - Clear global IN NAK - 8 - 1 - read-write - - - SGOUTNAK - Set global OUT NAK - 9 - 1 - read-write - - - CGOUTNAK - Clear global OUT NAK - 10 - 1 - read-write - - - PWROPRGDNE - Power-on programming done - 11 - 1 - read-write - - - - - DSTS - DSTS - OTGFS device status register - (OTGFS_DSTS) - 0x8 - 0x20 - read-only - 0x00000010 - - - SUSPSTS - Suspend status - 0 - 1 - - - ENUMSPD - Enumerated speed - 1 - 2 - - - ETICERR - Erratic error - 3 - 1 - - - SOFFN - Frame number of the received - SOF - 8 - 14 - - - - - DIEPMSK - DIEPMSK - OTGFS device IN endpoint common interrupt - mask register (OTGFS_DIEPMSK) - 0x10 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - TIMEOUTMSK - Timeout condition mask (Non-isochronous - endpoints) - 3 - 1 - - - INTKNTXFEMPMSK - IN token received when TxFIFO empty - mask - 4 - 1 - - - INTKNEPTMISMSK - IN token received with EP mismatch - mask - 5 - 1 - - - INEPTNAKMSK - IN endpoint NAK effective - mask - 6 - 1 - - - TXFIFOUDRMSK - FIFO underrun - mask - 8 - 1 - - - BNAINMSK - BNA interrupt - mask - 9 - 1 - - - - - DOEPMSK - DOEPMSK - OTGFS device OUT endpoint common interrupt - mask register (OTGFS_DOEPMSK) - 0x14 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - SETUPMSK - SETUP phase done mask - 3 - 1 - - - OUTTEPDMSK - OUT token received when endpoint - disabled mask - 4 - 1 - - - B2BSETUPMSK - Back-to-back SETUP packets - received mask - 6 - 1 - - - OUTPERRMSK - OUT packet error - mask - 8 - 1 - - - BNAOUTMSK - BNA interrupt - mask - 9 - 1 - - - - - DAINT - DAINT - OTGFS device all endpoints interrupt - register (OTGFS_DAINT) - 0x18 - 0x20 - read-only - 0x00000000 - - - INEPTINT - IN endpoint interrupt bits - 0 - 16 - - - OUTEPTINT - OUT endpoint interrupt - bits - 16 - 16 - - - - - DAINTMSK - DAINTMSK - OTGFS all endpoints interrupt mask register - (OTGFS_DAINTMSK) - 0x1C - 0x20 - read-write - 0x00000000 - - - INEPTMSK - IN EP interrupt mask bits - 0 - 16 - - - OUTEPTMSK - OUT endpoint interrupt - bits - 16 - 16 - - - - - DIEPEMPMSK - DIEPEMPMSK - OTGFS device IN endpoint FIFO empty - interrupt mask register - 0x34 - 0x20 - read-write - 0x00000000 - - - INEPTXFEMSK - IN EP Tx FIFO empty interrupt mask - bits - 0 - 16 - - - - - DIEPCTL0 - DIEPCTL0 - OTGFS device control IN endpoint 0 control - register (OTGFS_DIEPCTL0) - 0x100 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 2 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-only - - - EPTENA - Endpoint enable - 31 - 1 - read-only - - - - - DIEPCTL1 - DIEPCTL1 - OTGFS device IN endpoint-1 control - register - 0x120 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL2 - DIEPCTL2 - OTGFS device IN endpoint-2 control - register - 0x140 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL3 - DIEPCTL3 - OTGFS device IN endpoint-3 control - register - 0x160 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL4 - DIEPCTL4 - OTGFS device IN endpoint-4 control - register - 0x180 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL5 - DIEPCTL5 - OTGFS device IN endpoint-5 control - register - 0x1A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL6 - DIEPCTL6 - OTGFS device IN endpoint-6 control - register - 0x1C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL7 - DIEPCTL7 - OTGFS device IN endpoint-7 control - register - 0x1E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL0 - DOEPCTL0 - OTGFS device OUT endpoint-0 control - register - 0x300 - 0x20 - 0x00008000 - - - MPS - Maximum packet size - 0 - 2 - read-only - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL1 - DOEPCTL1 - OTGFS device OUT endpoint-1 control - register - 0x320 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL2 - DOEPCTL2 - OTGFS device OUT endpoint-2 control - register - 0x340 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL3 - DOEPCTL3 - OTGFS device OUT endpoint-3 control - register - 0x360 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL4 - DOEPCTL4 - OTGFS device OUT endpoint-4 control - register - 0x380 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL5 - DOEPCTL5 - OTGFS device OUT endpoint-5 control - register - 0x3A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL6 - DOEPCTL6 - OTGFS device OUT endpoint-6 control - register - 0x3C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL7 - DOEPCTL7 - OTGFS device OUT endpoint-7 control - register - 0x3E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPINT0 - DIEPINT0 - OTGFS device IN endpoint-0 interrupt - register - 0x108 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT1 - DIEPINT1 - OTGFS device IN endpoint-1 interrupt - register - 0x128 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT2 - DIEPINT2 - OTGFS device IN endpoint-2 interrupt - register - 0x148 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT3 - DIEPINT3 - OTGFS device IN endpoint-3 interrupt - register - 0x168 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT4 - DIEPINT4 - OTGFS device IN endpoint-4 interrupt - register - 0x188 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT5 - DIEPINT5 - OTGFS device IN endpoint-5 interrupt - register - 0x1A8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT6 - DIEPINT6 - OTGFS device IN endpoint-6 interrupt - register - 0x1C8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT7 - DIEPINT7 - OTGFS device IN endpoint-7 interrupt - register - 0x1E8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DOEPINT0 - DOEPINT0 - OTGFS device OUT endpoint-0 interrupt - register - 0x308 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT1 - DOEPINT1 - OTGFS device OUT endpoint-1 interrupt - register - 0x328 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT2 - DOEPINT2 - OTGFS device OUT endpoint-2 interrupt - register - 0x348 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT3 - DOEPINT3 - OTGFS device OUT endpoint-3 interrupt - register - 0x368 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT4 - DOEPINT4 - OTGFS device OUT endpoint-4 interrupt - register - 0x388 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT5 - DOEPINT5 - OTGFS device OUT endpoint-5 interrupt - register - 0x3A8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT6 - DOEPINT6 - OTGFS device OUT endpoint-6 interrupt - register - 0x3C8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT7 - DOEPINT7 - OTGFS device OUT endpoint-7 interrupt - register - 0x3E8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DIEPTSIZ0 - DIEPTSIZ0 - OTGFS device IN endpoint-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 2 - - - - - DOEPTSIZ0 - DOEPTSIZ0 - OTGFS device OUT endpoint-0 transfer size - register - 0x310 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 1 - - - SETUPCNT - SETUP packet count - 29 - 2 - - - - - DIEPTSIZ1 - DIEPTSIZ1 - OTGFS device IN endpoint-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ2 - DIEPTSIZ2 - OTGFS device IN endpoint-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ3 - DIEPTSIZ3 - OTG device IN endpoint-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ4 - DIEPTSIZ4 - OTG device IN endpoint-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ5 - DIEPTSIZ5 - OTG device IN endpoint-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ6 - DIEPTSIZ6 - OTG device IN endpoint-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ7 - DIEPTSIZ7 - OTG device IN endpoint-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DTXFSTS0 - DTXFSTS0 - OTGFS device IN endpoint-0 transmit FIFO - status register - 0x118 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS1 - DTXFSTS1 - OTGFS device IN endpoint-1 transmit FIFO - status register - 0x138 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS2 - DTXFSTS2 - OTGFS device IN endpoint-2 transmit FIFO - status register - 0x158 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS3 - DTXFSTS3 - OTGFS device IN endpoint-3 transmit FIFO - status register - 0x178 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS4 - DTXFSTS4 - OTGFS device IN endpoint-4 transmit FIFO - status register - 0x198 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS5 - DTXFSTS5 - OTGFS device IN endpoint-5 transmit FIFO - status register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS6 - DTXFSTS6 - OTGFS device IN endpoint-6 transmit FIFO - status register - 0x1D8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS7 - DTXFSTS7 - OTGFS device IN endpoint-7 transmit FIFO - status register - 0x1F8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DOEPTSIZ1 - DOEPTSIZ1 - OTGFS device OUT endpoint-1 transfer size - register - 0x330 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ2 - DOEPTSIZ2 - OTGFS device OUT endpoint-2 transfer size - register - 0x350 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ3 - DOEPTSIZ3 - OTGFS device OUT endpoint-3 transfer size - register - 0x370 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ4 - DOEPTSIZ4 - OTGFS device OUT endpoint-4 transfer size - register - 0x390 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ5 - DOEPTSIZ5 - OTGFS device OUT endpoint-5 transfer size - register - 0x3B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ6 - DOEPTSIZ6 - OTGFS device OUT endpoint-6 transfer size - register - 0x3D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ7 - DOEPTSIZ7 - OTGFS device OUT endpoint-7 transfer size - register - 0x3F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - - - USB_OTGFS_PWRCLK - USB on the go full speed - USB_OTGFS - 0x50000E00 - - 0x0 - 0x400 - registers - - - - PCGCCTL - PCGCCTL - OTGFS power and clock gating control - register (OTGFS_PCGCCTL) - 0x0 - 0x20 - 0x00000000 - - - STOPPCLK - Stop PHY clock - 0 - 1 - read-write - - - SUSPENDM - PHY Suspended - 4 - 1 - read-only - - - - - - - SCFG - System configuration controller - SCFG - 0x40013800 - - 0x0 - 0x400 - registers - - - - CFG1 - CFG1 - configuration register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - MEM_MAP_SEL - Memory address mapping selection bits - 0 - 3 - - - IR_POL - IR output polarity selection - 5 - 1 - - - IR_SRC_SEL - IR signal source selection - 6 - 2 - - - - - CFG2 - CFG2 - configuration register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - LOCKUP_LK - CM4 LOCKUP bit enable - 0 - 1 - - - PVM_LK - PVM lock enable - 2 - 1 - - - I2S_FD - I2S full duplex configuration bit - 30 - 2 - - - - - EXINTC1 - EXINTC1 - external interrupt configuration register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - EXINT3 - EXINT 3 configuration bits - 12 - 4 - - - EXINT2 - EXINT 2 configuration bits - 8 - 4 - - - EXINT1 - EXINT 1 configuration bits - 4 - 4 - - - EXINT0 - EXINT 0 configuration bits - 0 - 4 - - - - - EXINTC2 - EXINTC2 - external interrupt configuration register 2 - 0xC - 0x20 - read-write - 0x0000 - - - EXINT7 - EXINT 7 configuration bits - 12 - 4 - - - EXINT6 - EXINT 6 configuration bits - 8 - 4 - - - EXINT5 - EXINT 5 configuration bits - 4 - 4 - - - EXINT4 - EXINT 4 configuration bits - 0 - 4 - - - - - EXINTC3 - EXINTC3 - external interrupt configuration register 3 - 0x10 - 0x20 - read-write - 0x0000 - - - EXINT11 - EXINT 11 configuration bits - 12 - 4 - - - EXINT10 - EXINT 10 configuration bits - 8 - 4 - - - EXINT9 - EXINT 9 configuration bits - 4 - 4 - - - EXINT8 - EXINT 8 configuration bits - 0 - 4 - - - - - EXINTC4 - EXINTC4 - external interrupt configuration register - 4 - 0x14 - 0x20 - read-write - 0x0000 - - - EXINT15 - EXINT 15 configuration bits - 12 - 4 - - - EXINT14 - EXINT 14 configuration bits - 8 - 4 - - - EXINT13 - EXINT 13 configuration bits - 4 - 4 - - - EXINT12 - EXINT 12 configuration bits - 0 - 4 - - - - - UHDRV - UHDRV - Ultra high drive register - 0x2C - 0x20 - read-write - 0x0000 - - - PD13_UH - PD13 ultra high sourcing/sinking strength - 6 - 1 - - - PD12_UH - PD12 ultra high sourcing/sinking strength - 5 - 1 - - - PB8_UH - PB8 ultra high sourcing/sinking strength - 3 - 1 - - - PB9_UH - PB9 ultra high sourcing/sinking strength - 1 - 1 - - - - - - - QSPI1 - Quad SPI Controller - QSPI - 0xA0001000 - - 0x0 - 0x400 - registers - - - QSPI1 - QSPI1 global interrupt - 92 - - - - CMD_W0 - CMD_W0 - Command word 0 - 0x0 - 0x20 - read-write - 0x00000000 - - - SPIADR - SPI flash address - 0 - 32 - - - - - CMD_W1 - CMD_W1 - Command word 1 - 0x4 - 0x20 - read-write - 0x01000003 - - - ADRLEN - SPI address length - 0 - 3 - - - DUM2 - Second dummy state cycle - 16 - 8 - - - INSLEN - Instruction code length - 24 - 2 - - - PEMEN - Perfrmance enhance mode enable - 28 - 1 - - - - - CMD_W2 - CMD_W2 - Command word 2 - 0x8 - 0x20 - read-write - 0x01000003 - - - DCNT - Read write data counter - 0 - 32 - - - - - CMD_W3 - CMD_W3 - Command word 3 - 0xC - 0x20 - read-write - 0x00000000 - - - WEN - Write data enable - 1 - 1 - - - RSTSEN - Read spi status enable - 2 - 1 - - - RSTSC - Read spi status configure - 3 - 1 - - - OPMODE - SPI operate mode - 5 - 3 - - - PEMOPC - Performance enhance mode operate code - 16 - 8 - - - INSC - Instruction code - 24 - 8 - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00000000 - - - CLKDIV - SPI clock divider - 0 - 3 - - - SCKMODE - Sckout mode - 4 - 1 - - - XIPIDLE - XIP port idle status - 7 - 1 - - - ABORT - Abort instruction - 8 - 1 - - - BUSY - Busy bit of spi status - 16 - 3 - - - XIPRCMDF - XIP read command flush - 19 - 1 - - - XIPSEL - XIP port selection - 20 - 1 - - - KEYEN - encryption key enable - 21 - 1 - - - - - ACTR - ACTR - AC timing control register - 0x14 - 0x20 - read-write - 0x0000000F - - - CSDLY - CS delay - 0 - 4 - - - - - FIFOSTS - FIFOSTS - FIFO Status register - 0x18 - 0x20 - read-only - 0x00000001 - - - TXFIFORDY - TxFIFO ready status - 0 - 1 - - - RXFIFORDY - RxFIFO ready status - 1 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x20 - 0x20 - read-write - 0x00000001 - - - DMAEN - DMA handshake enable - 0 - 1 - - - CMDIE - Command complete interrupt enable - 1 - 1 - - - TXFIFOTHOD - TxFIFO thod - 8 - 2 - - - RXFIFOTHOD - RxFIFO thod - 12 - 2 - - - - - CMDSTS - CMDSTS - CMD status register - 0x24 - 0x20 - read-only - 0x00000000 - - - CMDSTS - Command complete status - 0 - 1 - - - - - RSTS - RSTS - SPI read status register - 0x28 - 0x20 - read-only - 0x00000000 - - - SPISTS - SPI read status - 0 - 8 - - - - - FSIZE - FSIZE - SPI flash size - 0x2C - 0x20 - read-write - 0x00000000 - - - SPIFSIZE - SPI flash size - 0 - 32 - - - - - XIP_CMD_W0 - XIP_CMD_W0 - XIP command word 0 - 0x30 - 0x20 - read-write - 0x00000000 - - - XIPR_DUM2 - XIP read second dummy cycle - 0 - 8 - - - XIPR_OPMODE - XIP read operate mode - 8 - 3 - - - XIPR_ADRLEN - XIP read address length - 11 - 1 - - - XIPR_INSC - XIP read instruction code - 12 - 8 - - - - - XIP_CMD_W1 - XIP_CMD_W1 - XIP command word 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - XIPW_DUM2 - XIP write second dummy cycle - 0 - 8 - - - XIPW_OPMODE - XIP write operate mode - 8 - 3 - - - XIPW_ADRLEN - XIP write address length - 11 - 1 - - - XIPW_INSC - XIP write instruction code - 12 - 8 - - - - - XIP_CMD_W2 - XIP_CMD_W2 - XIP command word 2 - 0x38 - 0x20 - read-write - 0x00000000 - - - XIPR_DCNT - XIP read data counter - 0 - 6 - - - XIPR_TCNT - XIP continue read cycle counter - 8 - 7 - - - XIPR_SEL - XIP read continue mode select - 15 - 1 - - - XIPW_DCNT - XIP write data counter - 16 - 6 - - - XIPW_TCNT - XIP continue write cycle counter - 24 - 7 - - - XIPW_SEL - XIP write continue mode select - 31 - 1 - - - - - XIP_CMD_W3 - XIP_CMD_W3 - XIP command word 3 - 0x3C - 0x20 - read-write - 0x00000000 - - - BYPASSC - Bypass cache function - 0 - 1 - - - CSTS - Cache status - 3 - 1 - - - - - REV - REV - Revision - 0x50 - 0x20 - read-write - 0x00010500 - - - REVISION - Revision number - 0 - 31 - - - - - DT - DT - 32/16/8 bit data port register - 0x100 - 0x20 - read-write - 0x00000000 - - - - - QSPI2 - 0xA0002000 - - QSPI2 - QSPI2 global interrupt - 91 - - - - diff --git a/hw/bsp/at32f423/boards/AT_START_F423/board.cmake b/hw/bsp/at32f423/boards/AT_START_F423/board.cmake new file mode 100644 index 000000000..17e665a0b --- /dev/null +++ b/hw/bsp/at32f423/boards/AT_START_F423/board.cmake @@ -0,0 +1,9 @@ +set(MCU_VARIANT AT32F423VCT7) +set(JLINK_DEVICE ${MCU_VARIANT}) + +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/AT32F423xC_FLASH.ld) +set(LD_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/AT32F423xC.icf) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT}) +endfunction() diff --git a/hw/bsp/at32f423/boards/AT_START_F423/board.mk b/hw/bsp/at32f423/boards/AT_START_F423/board.mk index 95ec21d02..4c19c81bb 100644 --- a/hw/bsp/at32f423/boards/AT_START_F423/board.mk +++ b/hw/bsp/at32f423/boards/AT_START_F423/board.mk @@ -1,3 +1,4 @@ +JLINK_DEVICE = AT32F423VCT7 LD_FILE = $(BOARD_PATH)/AT32F423xC_FLASH.ld CFLAGS += \ diff --git a/hw/bsp/at32f423/family.c b/hw/bsp/at32f423/family.c index f63fb8962..afe3758ca 100644 --- a/hw/bsp/at32f423/family.c +++ b/hw/bsp/at32f423/family.c @@ -25,8 +25,8 @@ */ #include "at32f423_clock.h" -#include "bsp/board_api.h" #include "board.h" +#include "bsp/board_api.h" void usb_clock48m_select(usb_clk48_s clk_s); void led_and_button_init(void); @@ -34,17 +34,14 @@ void uart_print_init(uint32_t baudrate); //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void OTGFS1_IRQHandler(void) -{ +void OTGFS1_IRQHandler(void) { tusb_int_handler(0, true); } -void OTGFS1_WKUP_IRQHandler(void) -{ +void OTGFS1_WKUP_IRQHandler(void) { tusb_int_handler(0, true); } -void board_init(void) -{ +void board_init(void) { /* config nvic priority group */ nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); @@ -63,24 +60,24 @@ void board_init(void) /* configure systick */ systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); SysTick_Config(SystemCoreClock / 1000); - #if CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); - #endif - - /* otgfs use vbus pin */ - #ifndef USB_VBUS_IGNORE - gpio_init_type gpio_init_struct; - crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); - gpio_default_para_init(&gpio_init_struct); - gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; - gpio_init_struct.gpio_mode = GPIO_MODE_MUX; - gpio_init_struct.gpio_pins = OTG_PIN_VBUS; - gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); - gpio_init(OTG_PIN_GPIO, &gpio_init_struct); - #endif +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + +/* otgfs use vbus pin */ +#ifndef USB_VBUS_IGNORE + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); +#endif /* config led and key */ led_and_button_init(); @@ -98,10 +95,8 @@ void board_init(void) * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT * @retval none */ -void usb_clock48m_select(usb_clk48_s clk_s) -{ - if(clk_s == USB_CLK_HICK) - { +void usb_clock48m_select(usb_clk48_s clk_s) { + if (clk_s == USB_CLK_HICK) { crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); /* enable the acc calibration ready interrupt */ @@ -114,11 +109,8 @@ void usb_clock48m_select(usb_clk48_s clk_s) /* open acc calibration */ acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); - } - else - { - switch(system_core_clock) - { + } else { + switch (system_core_clock) { /* 48MHz */ case 48000000: crm_usb_clock_div_set(CRM_USB_DIV_2); @@ -138,7 +130,7 @@ void usb_clock48m_select(usb_clk48_s clk_s) case 120000000: crm_usb_clock_div_set(CRM_USB_DIV_5); break; - + /* 144MHz */ case 144000000: crm_usb_clock_div_set(CRM_USB_DIV_6); @@ -149,8 +141,7 @@ void usb_clock48m_select(usb_clk48_s clk_s) } } } -void uart_print_init(uint32_t baudrate) -{ +void uart_print_init(uint32_t baudrate) { gpio_init_type gpio_init_struct; /* enable the uart and gpio clock */ crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); @@ -158,7 +149,7 @@ void uart_print_init(uint32_t baudrate) gpio_default_para_init(&gpio_init_struct); /* configure the uart tx pin */ gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_init_struct.gpio_mode = GPIO_MODE_MUX; gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; gpio_init_struct.gpio_pull = GPIO_PULL_NONE; @@ -170,8 +161,7 @@ void uart_print_init(uint32_t baudrate) usart_enable(PRINT_UART, TRUE); } -void led_and_button_init(void) -{ +void led_and_button_init(void) { /* LED */ gpio_init_type gpio_led_init_struct; /* enable the led clock */ @@ -180,7 +170,7 @@ void led_and_button_init(void) gpio_default_para_init(&gpio_led_init_struct); /* configure the led gpio */ gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; gpio_led_init_struct.gpio_pins = LED_PIN; gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; @@ -200,21 +190,18 @@ void led_and_button_init(void) gpio_init(BUTTON_PORT, &gpio_button_init_struct); } -void board_led_write(bool state) -{ +void board_led_write(bool state) { gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); } -uint32_t board_button_read(void) -{ +uint32_t board_button_read(void) { return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); } -size_t board_get_unique_id(uint8_t id[], size_t max_len) -{ +size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; - volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); - uint32_t* id32 = (uint32_t*) (uintptr_t) id; + volatile uint32_t *at32_uuid = ((volatile uint32_t *) 0x1FFFF7E8); + uint32_t *id32 = (uint32_t *) (uintptr_t) id; uint8_t const len = 12; id32[0] = at32_uuid[0]; @@ -224,68 +211,62 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) return len; } -int board_uart_read(uint8_t *buf, int len) -{ +int board_uart_read(uint8_t *buf, int len) { (void) buf; (void) len; return 0; } -int board_uart_write(void const *buf, int len) -{ - #if CFG_TUSB_OS == OPT_OS_NONE - int txsize = len; - u16 timeout = 0xffff; - while (txsize--) - { - while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) - { - timeout--; - if(timeout == 0) - { - return 0; - } +int board_uart_write(void const *buf, int len) { +#if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) { + while (usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) { + timeout--; + if (timeout == 0) { + return 0; } - PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); - buf++; } - return len; - #else - (void) buf; - (void) len; - return 0; - #endif + PRINT_UART->dt = (*((uint8_t const *) buf) & 0x01FF); + buf++; + } + return len; +#else + (void) buf; + (void) len; + return 0; +#endif } #if CFG_TUSB_OS == OPT_OS_NONE - volatile uint32_t system_ticks = 0; - void SysTick_Handler(void) - { - system_ticks++; - } +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) { + system_ticks++; +} - uint32_t board_millis(void) - { - return system_ticks; - } +uint32_t board_millis(void) { + return system_ticks; +} - void SVC_Handler(void) - { - } +void SVC_Handler(void) { +} - void PendSV_Handler(void) - { - } +void PendSV_Handler(void) { +} #endif -void HardFault_Handler(void) -{ +void HardFault_Handler(void) { __asm("BKPT #0\n"); } -#ifdef USE_FULL_ASSERT -void assert_failed(const char *file, uint32_t line) -{ +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +// void _init(void) { +// } + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) { /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ diff --git a/hw/bsp/at32f423/family.cmake b/hw/bsp/at32f423/family.cmake new file mode 100644 index 000000000..ebc855949 --- /dev/null +++ b/hw/bsp/at32f423/family.cmake @@ -0,0 +1,104 @@ +include_guard() + +set(AT_FAMILY at32f423) +set(AT_SDK_LIB ${TOP}/hw/mcu/artery/${AT_FAMILY}/libraries) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS AT32F423 CACHE INTERNAL "") + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/startup_${AT_FAMILY}.s) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT_FAMILY}.s) + + set(LD_FILE_Clang ${LD_FILE_GNU}) + + add_library(${BOARD_TARGET} STATIC + ${AT_SDK_LIB}/cmsis/cm4/device_support/system_${AT_FAMILY}.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_gpio.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_misc.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_usart.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_acc.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_crm.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${AT_SDK_LIB}/cmsis/cm4/core_support + ${AT_SDK_LIB}/cmsis/cm4/device_support + ${AT_SDK_LIB}/drivers/inc + ) + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT_FAMILY}_clock.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT_FAMILY}_int.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_AT32F423) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c + ) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + + # Flashing + family_add_bin_hex(${TARGET}) + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/at32f423/family.mk b/hw/bsp/at32f423/family.mk index 2653842da..8ee1072be 100644 --- a/hw/bsp/at32f423/family.mk +++ b/hw/bsp/at32f423/family.mk @@ -1,6 +1,6 @@ -# Submodules +JLINK_DEVICE = AT32F423VCT7 + AT32F423_SDK = hw/mcu/artery/at32f423 -DEPS_SUBMODULES += $(AT32F423_SDK) # AT32 SDK path AT32F423_SDK_SRC = $(AT32F423_SDK)/libraries @@ -16,7 +16,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_AT32F423 \ LDFLAGS_GCC += \ - -flto --specs=nosys.specs + -flto --specs=nosys.specs -nostdlib -nostartfiles SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ diff --git a/hw/bsp/at32f423/startup_at32f423.s b/hw/bsp/at32f423/startup_at32f423.s index 764380f0e..3e5404009 100644 --- a/hw/bsp/at32f423/startup_at32f423.s +++ b/hw/bsp/at32f423/startup_at32f423.s @@ -78,7 +78,7 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array diff --git a/hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h index 6cc39f727..f1784902e 100644 --- a/hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h @@ -109,7 +109,7 @@ #define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 #define INCLUDE_uxTaskGetStackHighWaterMark 0 #define INCLUDE_xTaskGetIdleTaskHandle 0 #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 diff --git a/hw/bsp/at32f425/at32f425_clock.h b/hw/bsp/at32f425/at32f425_clock.h index acd442e42..785fcc81a 100644 --- a/hw/bsp/at32f425/at32f425_clock.h +++ b/hw/bsp/at32f425/at32f425_clock.h @@ -41,4 +41,3 @@ void system_clock_config(void); #endif #endif - diff --git a/hw/bsp/at32f425/at32f425_int.c b/hw/bsp/at32f425/at32f425_int.c index eaef6af42..ed774f4f2 100644 --- a/hw/bsp/at32f425/at32f425_int.c +++ b/hw/bsp/at32f425/at32f425_int.c @@ -137,4 +137,3 @@ void DebugMon_Handler(void) /** * @} */ - diff --git a/hw/bsp/at32f425/at32f425_int.h b/hw/bsp/at32f425/at32f425_int.h index b40767ee4..ad9dc308b 100644 --- a/hw/bsp/at32f425/at32f425_int.h +++ b/hw/bsp/at32f425/at32f425_int.h @@ -53,4 +53,3 @@ void SysTick_Handler(void); #endif #endif - diff --git a/hw/bsp/at32f425/boards/AT_START_F425/AT32F425x8_FLASH.ld b/hw/bsp/at32f425/boards/AT_START_F425/AT32F425x8_FLASH.ld index 850d596f9..b1d767b51 100644 --- a/hw/bsp/at32f425/boards/AT_START_F425/AT32F425x8_FLASH.ld +++ b/hw/bsp/at32f425/boards/AT_START_F425/AT32F425x8_FLASH.ld @@ -103,7 +103,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -118,7 +118,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd b/hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd deleted file mode 100644 index d18e75e8e..000000000 --- a/hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd +++ /dev/null @@ -1,30790 +0,0 @@ - - - - - - - - Keil - ArteryTek - AT32F425xx_v2 - AT32F425 - 1.0 - ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 120MHz, etc. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - CM4 - r0p1 - little - false - true - 4 - false - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - - PWC - Power control - PWC - 0x40007000 - - 0x0 - 0x400 - registers - - - PVM - PVM through EXTI line detection interrupt - 1 - - - - CTRL - CTRL - Power control register - (PWC_CTRL) - 0x0 - 0x20 - read-write - 0x00000000 - - - VRSEL - Voltage regulator state select when deepsleep mode - 0 - 1 - read-write - - - LPSEL - Low power mode select when Cortex-M4 sleepdeep - 1 - 1 - read-write - - - CLSWEF - Clear SWEF flag - 2 - 1 - write-only - - - CLSEF - Clear SEF flag - 3 - 1 - write-only - - - PVMEN - Power voltage monitoring enable - 4 - 1 - read-write - - - PVMSEL - Power voltage monitoring boundary select - 5 - 3 - read-write - - - BPWEN - Battery power domain write enable - 8 - 1 - read-write - - - - - CTRLSTS - CTRLSTS - Power control register - (PWC_CTRLSTS) - 0x4 - 0x20 - 0x00000000 - - - SWEF - Standby wake-up event flag - 0 - 1 - read-only - - - SEF - Standby mode entry flag - 1 - 1 - read-only - - - PVMOF - Power voltage monitoring output flag - 2 - 1 - read-only - - - SWPEN1 - Standby wake-up pin1 enable - 8 - 1 - read-write - - - SWPEN2 - Standby wake-up pin2 enable - 9 - 1 - read-write - - - SWPEN4 - Standby wake-up pin4 enable - 11 - 1 - read-write - - - SWPEN5 - Standby wake-up pin5 enable - 12 - 1 - read-write - - - SWPEN6 - Standby wake-up pin6 enable - 13 - 1 - read-write - - - SWPEN7 - Standby wake-up pin7 enable - 14 - 1 - read-write - - - - - CTRL2 - CTRL2 - Power control register 2 - (PWC_CTRL2) - 0x20 - 0x20 - 0x00000000 - - - VREXLPEN - Voltage regulator extra low power mode enable - 5 - 1 - read-write - - - - - - - CRM - Clock and reset management - CRM - 0x40021000 - - 0x0 - 0x400 - registers - - - CRM - CRM global interrupt - 4 - - - - CTRL - CTRL - Clock control register - 0x0 - 0x20 - 0x00000083 - - - HICKEN - High speed internal clock enable - 0 - 1 - read-write - - - HICKSTBL - High speed internal clock ready flag - 1 - 1 - read-only - - - HICKTRIM - High speed internal clock trimming - 2 - 6 - read-write - - - HICKCAL - High speed internal clock calibration - 8 - 8 - read-only - - - HEXTEN - High speed exernal crystal enable - 16 - 1 - read-write - - - HEXTSTBL - High speed exernal crystal ready flag - 17 - 1 - read-only - - - HEXTBYPS - High speed exernal crystal bypass - 18 - 1 - read-write - - - CFDEN - Clock failure detection enable - 19 - 1 - read-write - - - PLLEN - PLL enable - 24 - 1 - read-write - - - PLLSTBL - PLL clock ready flag - 25 - 1 - read-only - - - - - CFG - CFG - Clock configuration register - (CRM_CFG) - 0x4 - 0x20 - 0x00000000 - - - SCLKSEL - System clock select - 0 - 2 - read-write - - - SCLKSTS - System Clock select Status - 2 - 2 - read-only - - - AHBDIV - AHB division - 4 - 4 - read-write - - - APB1DIV - APB1 division - 8 - 3 - read-write - - - APB2DIV - APB2 division - 11 - 3 - read-write - - - ADCDIV1_0 - ADC division bit1 and bit0 - 14 - 2 - read-write - - - PLLRCS - PLL reference clock select - 16 - 1 - read-write - - - PLLHEXTDIV - HEXT division selection for PLL entry clock - 17 - 1 - read-write - - - PLLMULT3_0 - PLL Multiplication Factor bit3 to bit0 - 18 - 4 - read-write - - - USBDIV1_0 - USB division bit1 and bit0 - 22 - 2 - read-write - - - CLKOUT_SEL - Clock output selection bit2 to bit0 - 24 - 3 - read-write - - - USBDIV2 - USB division bit2 - 27 - 1 - read-write - - - ADCDIV2 - ADC division bit2 - 28 - 1 - read-write - - - PLLMULT5_4 - PLL Multiplication Factor bit5 and bit4 - 29 - 2 - read-write - - - - - CLKINT - CLKINT - Clock interrupt register - (CRM_CLKINT) - 0x8 - 0x20 - 0x00000000 - - - LICKSTBLF - LICK ready interrupt flag - 0 - 1 - read-only - - - LEXTSTBLF - LEXT ready interrupt flag - 1 - 1 - read-only - - - HICKSTBLF - HICK ready interrupt flag - 2 - 1 - read-only - - - HEXTSTBLF - HEXT ready interrupt flag - 3 - 1 - read-only - - - PLLSTBLF - PLL ready interrupt flag - 4 - 1 - read-only - - - CFDF - Clock failure detection interrupt flag - 7 - 1 - read-only - - - LICKSTBLIEN - LICK ready interrupt enable - 8 - 1 - read-write - - - LEXTSTBLIEN - LEXT ready interrupt enable - 9 - 1 - read-write - - - HICKSTBLIEN - HICK ready interrupt enable - 10 - 1 - read-write - - - HEXTSTBLIEN - HEXT ready interrupt enable - 11 - 1 - read-write - - - PLLSTBLIEN - PLL ready interrupt enable - 12 - 1 - read-write - - - LICKSTBLFC - LICK ready interrupt clear - 16 - 1 - write-only - - - LEXTSTBLFC - LEXT ready interrupt clear - 17 - 1 - write-only - - - HICKSTBLFC - HICK ready interrupt clear - 18 - 1 - write-only - - - HEXTSTBLFC - HEXT ready interrupt clear - 19 - 1 - write-only - - - PLLSTBLFC - PLL ready interrupt clear - 20 - 1 - write-only - - - CFDFC - Clock failure detection interrupt clear - 23 - 1 - write-only - - - - - APB2RST - APB2RST - APB2 peripheral reset register - (CRM_APB2RST) - 0xC - 0x20 - read-write - 0x000000000 - - - SCFGRST - System config reset - 0 - 1 - - - EXINTRST - External interrupt reset - 1 - 1 - - - ADC1RST - ADC1 reset - 9 - 1 - - - TMR1RST - TMR1 reset - 11 - 1 - - - SPI1RST - SPI1 reset - 12 - 1 - - - USART1RST - USART1 reset - 14 - 1 - - - TMR15RST - Timer15 reset - 16 - 1 - - - TMR16RST - Timer16 reset - 17 - 1 - - - TMR17RST - Timer17 reset - 18 - 1 - - - - - APB1RST - APB1RST - APB1 peripheral reset register - (CRM_APB1RST) - 0x10 - 0x20 - read-write - 0x00000000 - - - TMR2RST - Timer 2 reset - 0 - 1 - - - TMR3RST - Timer 3 reset - 1 - 1 - - - TMR6RST - Timer 6 reset - 4 - 1 - - - TMR7RST - Timer 7 reset - 5 - 1 - - - TMR13RST - Timer 13 reset - 7 - 1 - - - TMR14RST - Timer 14 reset - 8 - 1 - - - WWDTRST - Window watchdog timer reset - 11 - 1 - - - SPI2RST - SPI2 reset - 14 - 1 - - - SPI3RST - SPI3 reset - 15 - 1 - - - USART2RST - USART 2 reset - 17 - 1 - - - USART3RST - USART 3 reset - 18 - 1 - - - USART4RST - USART 4 reset - 19 - 1 - - - I2C1RST - I2C1 reset - 21 - 1 - - - I2C2RST - I2C2 reset - 22 - 1 - - - CAN1RST - CAN1 reset - 25 - 1 - - - ACCRST - ACC reset - 27 - 1 - - - PWCRST - Power controller reset - 28 - 1 - - - - - AHBEN - AHBEN - AHB Peripheral Clock enable register - (CRM_AHBEN) - 0x14 - 0x20 - read-write - 0x00000014 - - - DMA1EN - DMA1 clock enable - 0 - 1 - - - SRAMEN - SRAM interface clock - enable - 2 - 1 - - - FLASHEN - FLASH clock enable - 4 - 1 - - - CRCEN - CRC clock enable - 6 - 1 - - - OTGFS1EN - OTGFS1 clock enable - 12 - 1 - - - GPIOAEN - I/O port A clock enable - 17 - 1 - - - GPIOBEN - I/O port B clock enable - 18 - 1 - - - GPIOCEN - I/O port C clock enable - 19 - 1 - - - GPIODEN - I/O port D clock enable - 20 - 1 - - - GPIOFEN - I/O port F clock enable - 22 - 1 - - - - - APB2EN - APB2EN - APB2 peripheral clock enable register - (CRM_APB2EN) - 0x18 - 0x20 - read-write - 0x00000000 - - - SCFGEN - System config clock enable - 0 - 1 - - - ADC1EN - ADC1 clock enable - 9 - 1 - - - TMR1EN - Timer1 clock enable - 11 - 1 - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - USART1EN - USART1 clock enable - 14 - 1 - - - TMR15EN - Timer15 clock enable - 16 - 1 - - - TMR16EN - Timer16 clock enable - 17 - 1 - - - TMR17EN - Timer17 clock enable - 18 - 1 - - - - - APB1EN - APB1EN - APB1 peripheral clock enable register - (CRM_APB1EN) - 0x1C - 0x20 - read-write - 0x00000000 - - - TMR2EN - Timer2 clock enable - 0 - 1 - - - TMR3EN - Timer3 clock enable - 1 - 1 - - - TMR6EN - Timer6 clock enable - 4 - 1 - - - TMR7EN - Timer7 clock enable - 5 - 1 - - - TMR13EN - Timer13 clock enable - 7 - 1 - - - TMR14EN - Timer14 clock enable - 8 - 1 - - - WWDTEN - Window watchdog timer clock - enable - 11 - 1 - - - SPI2EN - SPI2 clock enable - 14 - 1 - - - SPI3EN - SPI3 clock enable - 15 - 1 - - - USART2EN - USART2 clock enable - 17 - 1 - - - USART3EN - USART3 clock enable - 18 - 1 - - - USART4EN - USART4 clock enable - 19 - 1 - - - I2C1EN - I2C1 clock enable - 21 - 1 - - - I2C2EN - I2C2 clock enable - 22 - 1 - - - CAN1EN - CAN1 clock enable - 25 - 1 - - - ACCEN - ACC clock enable - 27 - 1 - - - PWCEN - Power clock enable - 28 - 1 - - - - - BPDC - BPDC - Battery powered domain control register - (CRM_BPDC) - 0x20 - 0x20 - 0x00000000 - - - LEXTEN - Low speed external crystal enable - 0 - 1 - read-write - - - LEXTSTBL - Low speed external crystal ready - 1 - 1 - read-only - - - LEXTBYPS - Low speed external crystal bypass - 2 - 1 - read-write - - - ERTCSEL - ERTC clock selection - 8 - 2 - read-write - - - ERTCEN - ERTC clock enable - 15 - 1 - read-write - - - BPDRST - Battery powered domain software reset - 16 - 1 - read-write - - - - - CTRLSTS - CTRLSTS - Control/status register - (CRM_CTRLSTS) - 0x24 - 0x20 - 0x0C000000 - - - LICKEN - Low speed internal clock enable - 0 - 1 - read-write - - - LICKSTBL - Low speed internal clock ready - 1 - 1 - read-only - - - RSTFC - Reset flag clear - 24 - 1 - read-write - - - NRSTF - PIN reset flag - 26 - 1 - read-write - - - PORRSTF - POR/LVR reset flag - 27 - 1 - read-write - - - SWRSTF - Software reset flag - 28 - 1 - read-write - - - WDTRSTF - Watchdog timer reset flag - 29 - 1 - read-write - - - WWDTRSTF - Window watchdog timer reset flag - 30 - 1 - read-write - - - LPRSTF - Low-power reset flag - 31 - 1 - read-write - - - - - AHBRST - AHBRST - AHB reset register - - 0x28 - 0x20 - 0x00000000 - - - OTGFS1RST - OTGFS1 reset - 12 - 1 - - - GPIOARST - IO port A reset - 17 - 1 - - - GPIOBRST - IO port B reset - 18 - 1 - - - GPIOCRST - IO port C reset - 19 - 1 - - - GPIODRST - IO port D reset - 20 - 1 - - - GPIOFRST - IO port F reset - 22 - 1 - - - - - PLL - PLL - PLL configuration register - (CRM_PLL) - 0x2C - 0x20 - 0x00001F10 - - - PLL_FR - PLL_FR - 0 - 3 - read-write - - - PLL_MS - PLL_MS - 4 - 4 - read-write - - - PLL_NS - PLL_NS - 8 - 9 - read-write - - - PLL_FREF - PLL entry clock reference frequency - 24 - 3 - read-write - - - PLLCFGEN - PLL config enable - 31 - 1 - read-write - - - - - MISC1 - MISC1 - Miscellaneous register1 - 0x30 - 0x20 - 0x00000000 - - - HICKCAL_KEY - HICKCAL write key value - 0 - 8 - read-write - - - CLKOUT_SEL3 - Clock output bit3 - 16 - 1 - read-write - - - HICKDIV - HICK 6 divider selection - 25 - 1 - read-write - - - CLKOUTDIV - Clock output division - 28 - 4 - read-write - - - - - MISC2 - MISC2 - Miscellaneous register2 - 0x54 - 0x20 - 0x0000000D - - - HICK_TO_USB - HICK_TO_USB - 8 - 1 - read-write - - - HICK_TO_SCLK - HICK to system clock - 9 - 1 - read-write - - - - - - - GPIOA - General purpose I/Os - GPIO - 0x48000000 - - 0x0 - 0x400 - registers - - - - CFGR - CFGR - GPIO configuration register - 0x0 - 0x20 - read-write - 0x00000000 - - - IOMC15 - GPIOx pin 15 mode configurate - 30 - 2 - - - IOMC14 - GPIOx pin 14 mode configurate - 28 - 2 - - - IOMC13 - GPIOx pin 13 mode configurate - 26 - 2 - - - IOMC12 - GPIOx pin 12 mode configurate - 24 - 2 - - - IOMC11 - GPIOx pin 11 mode configurate - 22 - 2 - - - IOMC10 - GPIOx pin 10 mode configurate - 20 - 2 - - - IOMC9 - GPIOx pin 9 mode configurate - 18 - 2 - - - IOMC8 - GPIOx pin 8 mode configurate - 16 - 2 - - - IOMC7 - GPIOx pin 7 mode configurate - 14 - 2 - - - IOMC6 - GPIOx pin 6 mode configurate - 12 - 2 - - - IOMC5 - GPIOx pin 5 mode configurate - 10 - 2 - - - IOMC4 - GPIOx pin 4 mode configurate - 8 - 2 - - - IOMC3 - GPIOx pin 3 mode configurate - 6 - 2 - - - IOMC2 - GPIOx pin 2 mode configurate - 4 - 2 - - - IOMC1 - GPIOx pin 1 mode configurate - 2 - 2 - - - IOMC0 - GPIOx pin 0 mode configurate - 0 - 2 - - - - - OMODE - OMODE - GPIO output mode register - 0x4 - 0x20 - read-write - 0x00000000 - - - OM15 - GPIOx pin 15 outpu mode configurate - 15 - 1 - - - OM14 - GPIOx pin 14 outpu mode configurate - 14 - 1 - - - OM13 - GPIOx pin 13 outpu mode configurate - 13 - 1 - - - OM12 - GPIOx pin 12 outpu mode configurate - 12 - 1 - - - OM11 - GPIOx pin 11 outpu mode configurate - 11 - 1 - - - OM10 - GPIOx pin 10 outpu mode configurate - 10 - 1 - - - OM9 - GPIOx pin 9 outpu mode configurate - 9 - 1 - - - OM8 - GPIOx pin 8 outpu mode configurate - 8 - 1 - - - OM7 - GPIOx pin 7 outpu mode configurate - 7 - 1 - - - OM6 - GPIOx pin 6 outpu mode configurate - 6 - 1 - - - OM5 - GPIOx pin 5 outpu mode configurate - 5 - 1 - - - OM4 - GPIOx pin 4 outpu mode configurate - 4 - 1 - - - OM3 - GPIOx pin 3 outpu mode configurate - 3 - 1 - - - OM2 - GPIOx pin 2 outpu mode configurate - 2 - 1 - - - OM1 - GPIOx pin 1 outpu mode configurate - 1 - 1 - - - OM0 - GPIOx pin 0 outpu mode configurate - 0 - 1 - - - - - ODRVR - ODRVR - GPIO drive capability register - 0x8 - 0x20 - read-write - 0x00000000 - - - ODRV15 - GPIOx pin 15 output drive capability - 30 - 2 - - - ODRV14 - GPIOx pin 14 output drive capability - 28 - 2 - - - ODRV13 - GPIOx pin 13 output drive capability - 26 - 2 - - - ODRV12 - GPIOx pin 12 output drive capability - 24 - 2 - - - ODRV11 - GPIOx pin 11 output drive capability - 22 - 2 - - - ODRV10 - GPIOx pin 10 output drive capability - 20 - 2 - - - ODRV9 - GPIOx pin 9 output drive capability - 18 - 2 - - - ODRV8 - GPIOx pin 8 output drive capability - 16 - 2 - - - ODRV7 - GPIOx pin 7 output drive capability - 14 - 2 - - - ODRV6 - GPIOx pin 6 output drive capability - 12 - 2 - - - ODRV5 - GPIOx pin 5 output drive capability - 10 - 2 - - - ODRV4 - GPIOx pin 4 output drive capability - 8 - 2 - - - ODRV3 - GPIOx pin 3 output drive capability - 6 - 2 - - - ODRV2 - GPIOx pin 2 output drive capability - 4 - 2 - - - ODRV1 - GPIOx pin 1 output drive capability - 2 - 2 - - - ODRV0 - GPIOx pin 0 output drive capability - 0 - 2 - - - - - PULL - PULL - GPIO pull-up/pull-down register - 0xC - 0x20 - read-write - 0x00000000 - - - PULL15 - GPIOx pin 15 pull configuration - 30 - 2 - - - PULL14 - GPIOx pin 14 pull configuration - 28 - 2 - - - PULL13 - GPIOx pin 13 pull configuration - 26 - 2 - - - PULL12 - GPIOx pin 12 pull configuration - 24 - 2 - - - PULL11 - GPIOx pin 11 pull configuration - 22 - 2 - - - PULL10 - GPIOx pin 10 pull configuration - 20 - 2 - - - PULL9 - GPIOx pin 9 pull configuration - 18 - 2 - - - PULL8 - GPIOx pin 8 pull configuration - 16 - 2 - - - PULL7 - GPIOx pin 7 pull configuration - 14 - 2 - - - PULL6 - GPIOx pin 6 pull configuration - 12 - 2 - - - PULL5 - GPIOx pin 5 pull configuration - 10 - 2 - - - PULL4 - GPIOx pin 4 pull configuration - 8 - 2 - - - PULL3 - GPIOx pin 3 pull configuration - 6 - 2 - - - PULL2 - GPIOx pin 2 pull configuration - 4 - 2 - - - PULL1 - GPIOx pin 1 pull configuration - 2 - 2 - - - PULL0 - GPIOx pin 0 pull configuration - 0 - 2 - - - - - IDT - IDT - GPIO input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - IDT0 - Port input data - 0 - 1 - - - IDT1 - Port input data - 1 - 1 - - - IDT2 - Port input data - 2 - 1 - - - IDT3 - Port input data - 3 - 1 - - - IDT4 - Port input data - 4 - 1 - - - IDT5 - Port input data - 5 - 1 - - - IDT6 - Port input data - 6 - 1 - - - IDT7 - Port input data - 7 - 1 - - - IDT8 - Port input data - 8 - 1 - - - IDT9 - Port input data - 9 - 1 - - - IDT10 - Port input data - 10 - 1 - - - IDT11 - Port input data - 11 - 1 - - - IDT12 - Port input data - 12 - 1 - - - IDT13 - Port input data - 13 - 1 - - - IDT14 - Port input data - 14 - 1 - - - IDT15 - Port input data - 15 - 1 - - - - - ODT - ODT - GPIO output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - ODT0 - Port output data - 0 - 1 - - - ODT1 - Port output data - 1 - 1 - - - ODT2 - Port output data - 2 - 1 - - - ODT3 - Port output data - 3 - 1 - - - ODT4 - Port output data - 4 - 1 - - - ODT5 - Port output data - 5 - 1 - - - ODT6 - Port output data - 6 - 1 - - - ODT7 - Port output data - 7 - 1 - - - ODT8 - Port output data - 8 - 1 - - - ODT9 - Port output data - 9 - 1 - - - ODT10 - Port output data - 10 - 1 - - - ODT11 - Port output data - 11 - 1 - - - ODT12 - Port output data - 12 - 1 - - - ODT13 - Port output data - 13 - 1 - - - ODT14 - Port output data - 14 - 1 - - - ODT15 - Port output data - 15 - 1 - - - - - SCR - SCR - Port bit set/clear register - 0x18 - 0x20 - write-only - 0x00000000 - - - IOSB0 - Set bit 0 - 0 - 1 - - - IOSB1 - Set bit 1 - 1 - 1 - - - IOSB2 - Set bit 1 - 2 - 1 - - - IOSB3 - Set bit 3 - 3 - 1 - - - IOSB4 - Set bit 4 - 4 - 1 - - - IOSB5 - Set bit 5 - 5 - 1 - - - IOSB6 - Set bit 6 - 6 - 1 - - - IOSB7 - Set bit 7 - 7 - 1 - - - IOSB8 - Set bit 8 - 8 - 1 - - - IOSB9 - Set bit 9 - 9 - 1 - - - IOSB10 - Set bit 10 - 10 - 1 - - - IOSB11 - Set bit 11 - 11 - 1 - - - IOSB12 - Set bit 12 - 12 - 1 - - - IOSB13 - Set bit 13 - 13 - 1 - - - IOSB14 - Set bit 14 - 14 - 1 - - - IOSB15 - Set bit 15 - 15 - 1 - - - IOCB0 - Clear bit 0 - 16 - 1 - - - IOCB1 - Clear bit 1 - 17 - 1 - - - IOCB2 - Clear bit 2 - 18 - 1 - - - IOCB3 - Clear bit 3 - 19 - 1 - - - IOCB4 - Clear bit 4 - 20 - 1 - - - IOCB5 - Clear bit 5 - 21 - 1 - - - IOCB6 - Clear bit 6 - 22 - 1 - - - IOCB7 - Clear bit 7 - 23 - 1 - - - IOCB8 - Clear bit 8 - 24 - 1 - - - IOCB9 - Clear bit 9 - 25 - 1 - - - IOCB10 - Clear bit 10 - 26 - 1 - - - IOCB11 - Clear bit 11 - 27 - 1 - - - IOCB12 - Clear bit 12 - 28 - 1 - - - IOCB13 - Clear bit 13 - 29 - 1 - - - IOCB14 - Clear bit 14 - 30 - 1 - - - IOCB15 - Clear bit 15 - 31 - 1 - - - - - WPR - WPR - Port write protect - register - 0x1C - 0x20 - read-write - 0x00000000 - - - WPEN0 - Write protect enable 0 - 0 - 1 - - - WPEN1 - Write protect enable 1 - 1 - 1 - - - WPEN2 - Write protect enable 2 - 2 - 1 - - - WPEN3 - Write protect enable 3 - 3 - 1 - - - WPEN4 - Write protect enable 4 - 4 - 1 - - - WPEN5 - Write protect enable 5 - 5 - 1 - - - WPEN6 - Write protect enable 6 - 6 - 1 - - - WPEN7 - Write protect enable 7 - 7 - 1 - - - WPEN8 - Write protect enable 8 - 8 - 1 - - - WPEN9 - Write protect enable 9 - 9 - 1 - - - WPEN10 - Write protect enable 10 - 10 - 1 - - - WPEN11 - Write protect enable 11 - 11 - 1 - - - WPEN12 - Write protect enable 12 - 12 - 1 - - - WPEN13 - Write protect enable 13 - 13 - 1 - - - WPEN14 - Write protect enable 14 - 14 - 1 - - - WPEN15 - Write protect enable 15 - 15 - 1 - - - WPSEQ - Write protect sequence - 16 - 1 - - - - - MUXL - MUXL - GPIO muxing function low register - 0x20 - 0x20 - read-write - 0x00000000 - - - MUXL7 - GPIOx pin 7 muxing - 28 - 4 - - - MUXL6 - GPIOx pin 6 muxing - 24 - 4 - - - MUXL5 - GPIOx pin 5 muxing - 20 - 4 - - - MUXL4 - GPIOx pin 4 muxing - 16 - 4 - - - MUXL3 - GPIOx pin 3 muxing - 12 - 4 - - - MUXL2 - GPIOx pin 2 muxing - 8 - 4 - - - MUXL1 - GPIOx pin 1 muxing - 4 - 4 - - - MUXL0 - GPIOx pin 0 muxing - 0 - 4 - - - - - MUXH - MUXH - GPIO muxing function high register - 0x24 - 0x20 - read-write - 0x00000000 - - - MUXH15 - GPIOx pin 15 muxing - 28 - 4 - - - MUXH14 - GPIOx pin 14 muxing - 24 - 4 - - - MUXH13 - GPIOx pin 13 muxing - 20 - 4 - - - MUXH12 - GPIOx pin 12 muxing - 16 - 4 - - - MUXH11 - GPIOx pin 11 muxing - 12 - 4 - - - MUXH10 - GPIOx pin 10 muxing - 8 - 4 - - - MUXH9 - GPIOx pin 9 muxing - 4 - 4 - - - MUXH8 - GPIOx pin 8 muxing - 0 - 4 - - - - - CLR - CLR - GPIO bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - IOCB0 - Clear bit 0 - 0 - 1 - - - IOCB1 - Clear bit 1 - 1 - 1 - - - IOCB2 - Clear bit 1 - 2 - 1 - - - IOCB3 - Clear bit 3 - 3 - 1 - - - IOCB4 - Clear bit 4 - 4 - 1 - - - IOCB5 - Clear bit 5 - 5 - 1 - - - IOCB6 - Clear bit 6 - 6 - 1 - - - IOCB7 - Clear bit 7 - 7 - 1 - - - IOCB8 - Clear bit 8 - 8 - 1 - - - IOCB9 - Clear bit 9 - 9 - 1 - - - IOCB10 - Clear bit 10 - 10 - 1 - - - IOCB11 - Clear bit 11 - 11 - 1 - - - IOCB12 - Clear bit 12 - 12 - 1 - - - IOCB13 - Clear bit 13 - 13 - 1 - - - IOCB14 - Clear bit 14 - 14 - 1 - - - IOCB15 - Clear bit 15 - 15 - 1 - - - - - HDRV - HDRV - Huge current driver - 0x3C - 0x20 - read-write - 0x00000000 - - - HDRV0 - Port x driver bit y - 0 - 1 - - - HDRV1 - Port x driver bit y - 1 - 1 - - - HDRV2 - Port x driver bit y - 2 - 1 - - - HDRV3 - Port x driver bit y - 3 - 1 - - - HDRV4 - Port x driver bit y - 4 - 1 - - - HDRV5 - Port x driver bit y - 5 - 1 - - - HDRV6 - Port x driver bit y - 6 - 1 - - - HDRV7 - Port x driver bit y - 7 - 1 - - - HDRV8 - Port x driver bit y - 8 - 1 - - - HDRV9 - Port x driver bit y - 9 - 1 - - - HDRV10 - Port x driver bit y - 10 - 1 - - - HDRV11 - Port x driver bit y - 11 - 1 - - - HDRV12 - Port x driver bit y - 12 - 1 - - - HDRV13 - Port x driver bit y - 13 - 1 - - - HDRV14 - Port x driver bit y - 14 - 1 - - - HDRV15 - Port x driver bit y - 15 - 1 - - - - - - - GPIOB - 0x48000400 - - - GPIOC - 0x48000800 - - - GPIOD - 0x48000C00 - - - GPIOF - 0x48001400 - - - EXINT - EXINT - EXINT - 0x40010400 - - 0x0 - 0x400 - registers - - - PVM - PVM interrupt connect to EXTI line16 - 1 - - - ERTC - ERTC interrupt connect to EXTI line17_19_20 - 2 - - - EXTINT1_0 - EXINT Line1_0 interrupt - 5 - - - EXTINT3_2 - EXINT Line3_2 interrupt - 6 - - - EXTINT15_4 - EXINT Line15_4 interrupt - 7 - - - OTGFS - OTGFS interrupt connect to EXTI Line18 - 31 - - - - INTEN - INTEN - Interrupt enable register (EXTINT_INTEN) - 0x0 - 0x20 - read-write - 0x00000000 - - - INTEN0 - Interrupt enable or disable on line 0 - 0 - 1 - - - INTEN1 - Interrupt enable or disable on line 1 - 1 - 1 - - - INTEN2 - Interrupt enable or disable on line 2 - 2 - 1 - - - INTEN3 - Interrupt enable or disable on line 3 - 3 - 1 - - - INTEN4 - Interrupt enable or disable on line 4 - 4 - 1 - - - INTEN5 - Interrupt enable or disable on line 5 - 5 - 1 - - - INTEN6 - Interrupt enable or disable on line 6 - 6 - 1 - - - INTEN7 - Interrupt enable or disable on line 7 - 7 - 1 - - - INTEN8 - Interrupt enable or disable on line 8 - 8 - 1 - - - INTEN9 - Interrupt enable or disable on line 9 - 9 - 1 - - - INTEN10 - Interrupt enable or disable on line 10 - 10 - 1 - - - INTEN11 - Interrupt enable or disable on line 11 - 11 - 1 - - - INTEN12 - Interrupt enable or disable on line 12 - 12 - 1 - - - INTEN13 - Interrupt enable or disable on line 13 - 13 - 1 - - - INTEN14 - Interrupt enable or disable on line 14 - 14 - 1 - - - INTEN15 - Interrupt enable or disable on line 15 - 15 - 1 - - - INTEN16 - Interrupt enable or disable on line 16 - 16 - 1 - - - INTEN17 - Interrupt enable or disable on line 17 - 17 - 1 - - - INTEN18 - Interrupt enable or disable on line 18 - 18 - 1 - - - INTEN19 - Interrupt enable or disable on line 19 - 19 - 1 - - - INTEN20 - Interrupt enable or disable on line 20 - 20 - 1 - - - - - EVTEN - EVTEN - Event enable register (EXTINT_EVTEN) - 0x4 - 0x20 - read-write - 0x00000000 - - - EVTEN0 - Event enable or disable on line 0 - 0 - 1 - - - EVTEN1 - Event enable or disable on line 1 - 1 - 1 - - - EVTEN2 - Event enable or disable on line 2 - 2 - 1 - - - EVTEN3 - Event enable or disable on line 3 - 3 - 1 - - - EVTEN4 - Event enable or disable on line 4 - 4 - 1 - - - EVTEN5 - Event enable or disable on line 5 - 5 - 1 - - - EVTEN6 - Event enable or disable on line 6 - 6 - 1 - - - EVTEN7 - Event enable or disable on line 7 - 7 - 1 - - - EVTEN8 - Event enable or disable on line 8 - 8 - 1 - - - EVTEN9 - Event enable or disable on line 9 - 9 - 1 - - - EVTEN10 - Event enable or disable on line 10 - 10 - 1 - - - EVTEN11 - Event enable or disable on line 11 - 11 - 1 - - - EVTEN12 - Event enable or disable on line 12 - 12 - 1 - - - EVTEN13 - Event enable or disable on line 13 - 13 - 1 - - - EVTEN14 - Event enable or disable on line 14 - 14 - 1 - - - EVTEN15 - Event enable or disable on line 15 - 15 - 1 - - - EVTEN16 - Event enable or disable on line 16 - 16 - 1 - - - EVTEN17 - Event enable or disable on line 17 - 17 - 1 - - - EVTEN18 - Event enable or disable on line 18 - 18 - 1 - - - EVTEN19 - Event enable or disable on line 19 - 19 - 1 - - - EVTEN20 - Event enable or disable on line 20 - 20 - 1 - - - - - POLCFG1 - POLCFG1 - Rising polarity configuration register(EXTINT_POLCFG1) - 0x8 - 0x20 - read-write - 0x00000000 - - - RP0 - Rising polarity configuration bit of line 0 - 0 - 1 - - - RP1 - Rising polarity configuration bit of line 1 - 1 - 1 - - - RP2 - Rising polarity configuration bit of line 2 - 2 - 1 - - - RP3 - Rising polarity configuration bit of line 3 - 3 - 1 - - - RP4 - Rising polarity configuration bit of line 4 - 4 - 1 - - - RP5 - Rising polarity configuration bit of line 5 - 5 - 1 - - - RP6 - Rising polarity configuration bit of linee 6 - 6 - 1 - - - RP7 - Rising polarity configuration bit of line 7 - 7 - 1 - - - RP8 - Rising polarity configuration bit of line 8 - 8 - 1 - - - RP9 - Rising polarity configuration bit of line 9 - 9 - 1 - - - RP10 - Rising polarity configuration bit of line 10 - 10 - 1 - - - RP11 - Rising polarity configuration bit of line 11 - 11 - 1 - - - RP12 - Rising polarity configuration bit of line 12 - 12 - 1 - - - RP13 - Rising polarity configuration bit of line 13 - 13 - 1 - - - RP14 - Rising polarity configuration bit of line 14 - 14 - 1 - - - RP15 - Rising polarity configuration bit of line 15 - 15 - 1 - - - RP16 - Rising polarity configuration bit of line 16 - 16 - 1 - - - RP17 - Rising polarity configuration bit of line 17 - 17 - 1 - - - RP18 - Rising polarity configuration bit of line 18 - 18 - 1 - - - RP19 - Rising polarity configuration bit of line 19 - 19 - 1 - - - RP20 - Rising polarity configuration bit of line 20 - 20 - 1 - - - - - POLCFG2 - POLCFG2 - Falling polarity configuration register(EXTINT_POLCFG2) - 0xC - 0x20 - read-write - 0x00000000 - - - FP0 - Falling polarity event configuration bit of line 0 - 0 - 1 - - - FP1 - Falling polarity event configuration bit of line 1 - 1 - 1 - - - FP2 - Falling polarity event configuration bit of line 2 - 2 - 1 - - - FP3 - Falling polarity event configuration bit of line 3 - 3 - 1 - - - FP4 - Falling polarity event configuration bit of line 4 - 4 - 1 - - - FP5 - Falling polarity event configuration bit of line 5 - 5 - 1 - - - FP6 - Falling polarity event configuration bit of line 6 - 6 - 1 - - - FP7 - Falling polarity event configuration bit of line 7 - 7 - 1 - - - FP8 - Falling polarity event configuration bit of line 8 - 8 - 1 - - - FP9 - Falling polarity event configuration bit of line 9 - 9 - 1 - - - FP10 - Falling polarity event configuration bit of line 10 - 10 - 1 - - - FP11 - Falling polarity event configuration bit of line 11 - 11 - 1 - - - FP12 - Falling polarity event configuration bit of line 12 - 12 - 1 - - - FP13 - Falling polarity event configuration bit of line 13 - 13 - 1 - - - FP14 - Falling polarity event configuration bit of line 14 - 14 - 1 - - - FP15 - Falling polarity event configuration bit of line 15 - 15 - 1 - - - FP16 - Falling polarity event configuration bit of line 16 - 16 - 1 - - - FP17 - Falling polarity event configuration bit of line 17 - 17 - 1 - - - FP18 - Falling polarity event configuration bit of line 18 - 18 - 1 - - - FP19 - Falling polarity event configuration bit of line 19 - 19 - 1 - - - FP20 - Falling polarity event configuration bit of line 20 - 20 - 1 - - - - - SWTRG - SWTRG - Software triggle register - (EXTINT_SWIE) - 0x10 - 0x20 - read-write - 0x00000000 - - - SWT0 - Software triggle on line 0 - 0 - 1 - - - SWT1 - Software triggle on line 1 - 1 - 1 - - - SWT2 - Software triggle on line 2 - 2 - 1 - - - SWT3 - Software triggle on line 3 - 3 - 1 - - - SWT4 - Software triggle on line 4 - 4 - 1 - - - SWT5 - Software triggle on line 5 - 5 - 1 - - - SWT6 - Software triggle on line 6 - 6 - 1 - - - SWT7 - Software triggle on line 7 - 7 - 1 - - - SWT8 - Software triggle on line 8 - 8 - 1 - - - SWT9 - Software triggle on line 9 - 9 - 1 - - - SWT10 - Software triggle on line 10 - 10 - 1 - - - SWT11 - Software triggle on line 11 - 11 - 1 - - - SWT12 - Software triggle on line 12 - 12 - 1 - - - SWT13 - Software triggle on line 13 - 13 - 1 - - - SWT14 - Software triggle on line 14 - 14 - 1 - - - SWT15 - Software triggle on line 15 - 15 - 1 - - - SWT16 - Software triggle on line 16 - 16 - 1 - - - SWT17 - Software triggle on line 17 - 17 - 1 - - - SWT18 - Software triggle on line 18 - 18 - 1 - - - SWT19 - Software triggle on line 19 - 19 - 1 - - - SWT20 - Software triggle on line 20 - 20 - 1 - - - - - INTSTS - INTSTS - Interrupt status register (EXTINT_INTSTS) - 0x14 - 0x20 - read-write - 0x00000000 - - - LINE0 - Line 0 state bit - 0 - 1 - - - LINE1 - Line 1 state bit - 1 - 1 - - - LINE2 - Line 2 state bit - 2 - 1 - - - LINE3 - Line 3 state bit - 3 - 1 - - - LINE4 - Line 4 state bit - 4 - 1 - - - LINE5 - Line 5 state bit - 5 - 1 - - - LINE6 - Line 6 state bit - 6 - 1 - - - LINE7 - Line 7 state bit - 7 - 1 - - - LINE8 - Line 8 state bit - 8 - 1 - - - LINE9 - Line 9 state bit - 9 - 1 - - - LINE10 - Line 10 state bit - 10 - 1 - - - LINE11 - Line 11 state bit - 11 - 1 - - - LINE12 - Line 12 state bit - 12 - 1 - - - LINE13 - Line 13 state bit - 13 - 1 - - - LINE14 - Line 14 state bit - 14 - 1 - - - LINE15 - Line 15 state bit - 15 - 1 - - - LINE16 - Line 16 state bit - 16 - 1 - - - LINE17 - Line 17 state bit - 17 - 1 - - - LINE18 - Line 18 state bit - 18 - 1 - - - LINE19 - Line 19 state bit - 19 - 1 - - - LINE20 - Line 20 state bit - 20 - 1 - - - - - - - DMA1 - DMA controller - DMA - 0x40020000 - - 0x0 - 0x400 - registers - - - DMA1_Channel1 - DMA1 Channel1 global interrupt - 9 - - - DMA1_Channel3_2 - DMA1 Channel3_2 global interrupt - 10 - - - DMA1_Channel7_4 - DMA1 Channel7_4 global interrupt - 11 - - - - STS - STS - DMA interrupt status register (DMA_STS) - 0x0 - 0x20 - read-only - 0x00000000 - - - GF1 - Channel 1 Global event flag - 0 - 1 - - - GF2 - Channel 2 Global event flag - 4 - 1 - - - GF3 - Channel 3 Global event flag - 8 - 1 - - - GF4 - Channel 4 Global event flag - 12 - 1 - - - GF5 - Channel 5 Global event flag - 16 - 1 - - - GF6 - Channel 6 Global event flag - 20 - 1 - - - GF7 - Channel 7 Global event flag - 24 - 1 - - - FDTF1 - Channel 1 full data transfer event flag - 1 - 1 - - - FDTF2 - Channel 2 full data transfer event flag - 5 - 1 - - - FDTF3 - Channel 3 full data transfer event flag - 9 - 1 - - - FDTF4 - Channel 4 full data transfer event flag - 13 - 1 - - - FDTF5 - Channel 5 full data transfer event flag - 17 - 1 - - - FDTF6 - Channel 6 full data transfer event flag - 21 - 1 - - - FDTF7 - Channel 7 full data transfer event flag - 25 - 1 - - - HDTF1 - Channel 1 half data transfer event flag - 2 - 1 - - - HDTF2 - Channel 2 half data transfer event flag - 6 - 1 - - - HDTF3 - Channel 3 half data transfer event flag - 10 - 1 - - - HDTF4 - Channel 4 half data transfer event flag - 14 - 1 - - - HDTF5 - Channel 5 half data transfer event flag - 18 - 1 - - - HDTF6 - Channel 6 half data transfer event flag - 22 - 1 - - - HDTF7 - Channel 7 half data transfer event flag - 26 - 1 - - - DTERRF1 - Channel 1 data transfer error event flag - 3 - 1 - - - DTERRF2 - Channel 2 data transfer error event flag - 7 - 1 - - - DTERRF3 - Channel 3 data transfer error event flag - 11 - 1 - - - DTERRF4 - Channel 4 data transfer error event flag - 15 - 1 - - - DTERRF5 - Channel 5 data transfer error event flag - 19 - 1 - - - DTERRF6 - Channel 6 data transfer error event flag - 23 - 1 - - - DTERRF7 - Channel 7 data transfer error event flag - 27 - 1 - - - - - CLR - CLR - DMA interrupt flag clear register (DMA_CLR) - 0x4 - 0x20 - read-write - 0x00000000 - - - GFC1 - Channel 1 Global flag clear - 0 - 1 - - - GFC2 - Channel 2 Global flag clear - 4 - 1 - - - GFC3 - Channel 3 Global flag clear - 8 - 1 - - - GFC4 - Channel 4 Global flag clear - 12 - 1 - - - GFC5 - Channel 5 Global flag clear - 16 - 1 - - - GFC6 - Channel 6 Global flag clear - 20 - 1 - - - GFC7 - Channel 7 Global flag clear - 24 - 1 - - - FDTFC1 - Channel 1 full data transfer flag clear - 1 - 1 - - - FDTFC2 - Channel 2 full data transfer flag clear - 5 - 1 - - - FDTFC3 - Channel 3 full data transfer flag clear - 9 - 1 - - - FDTFC4 - Channel 4 full data transfer flag clear - 13 - 1 - - - FDTFC5 - Channel 5 full data transfer flag clear - 17 - 1 - - - FDTFC6 - Channel 6 full data transfer flag clear - 21 - 1 - - - FDTFC7 - Channel 7 full data transfer flag clear - 25 - 1 - - - HDTFC1 - Channel 1 half data transfer flag clear - 2 - 1 - - - HDTFC2 - Channel 2 half data transfer flag clear - 6 - 1 - - - HDTFC3 - Channel 3 half data transfer flag clear - 10 - 1 - - - HDTFC4 - Channel 4 half data transfer flag clear - 14 - 1 - - - HDTFC5 - Channel 5 half data transfer flag clear - 18 - 1 - - - HDTFC6 - Channel 6 half data transfer flag clear - 22 - 1 - - - HDTFC7 - Channel 7 half data transfer flag clear - 26 - 1 - - - DTERRFC1 - Channel 1 data transfer error flag clear - 3 - 1 - - - DTERRFC2 - Channel 2 data transfer error flag clear - 7 - 1 - - - DTERRFC3 - Channel 3 data transfer error flag clear - 11 - 1 - - - DTERRFC4 - Channel 4 data transfer error flag clear - 15 - 1 - - - DTERRFC5 - Channel 5 data transfer error flag clear - 19 - 1 - - - DTERRFC6 - Channel 6 data transfer error flag clear - 23 - 1 - - - DTERRFC7 - Channel 7 data transfer error flag clear - 27 - 1 - - - - - C1CTRL - C1CTRL - DMA channel configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C1DTCNT - C1DTCNT - DMA channel 1 number of data to transfer register - 0xC - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C1PADDR - C1PADDR - DMA channel 1 peripheral base address register - 0x10 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C1MADDR - C1MADDR - DMA channel 1 memory base address register - 0x14 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C2CTRL - C2CTRL - DMA channel configuration register - 0x1C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C2DTCNT - C2DTCNT - DMA channel 2 number of data to transferregister - 0x20 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C2PADDR - C2PADDR - DMA channel 2 peripheral base address register - 0x24 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C2MADDR - C2MADDR - DMA channel 2 memory base address register - 0x28 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C3CTRL - C3CTRL - DMA channel configuration register - 0x30 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C3DTCNT - C3DTCNT - DMA channel 3 number of data to transfer register - 0x34 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C3PADDR - C3PADDR - DMA channel 3 peripheral base address register - 0x38 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C3MADDR - C3MADDR - DMA channel 3 memory base address register - 0x3C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C4CTRL - C4CTRL - DMA channel configuration register - 0x44 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C4DTCNT - C4DTCNT - DMA channel 4 number of data to transfer register - 0x48 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C4PADDR - C4PADDR - DMA channel 4 peripheral base address register - 0x4C - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C4MADDR - C4MADDR - DMA channel 4 memory base address register - 0x50 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C5CTRL - C5CTRL - DMA channel configuration register - 0x58 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C5DTCNT - C5DTCNT - DMA channel 5 number of data to transfer register - 0x5C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C5PADDR - C5PADDR - DMA channel 5 peripheral base address register - 0x60 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C5MADDR - C5MADDR - DMA channel 5 memory base address register - 0x64 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C6CTRL - C6CTRL - DMA channel configuration register - 0x6C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C6DTCNT - C6DTCNT - DMA channel 6 number of data to transfer register - 0x70 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C6PADDR - C6PADDR - DMA channel 6 peripheral address base register - 0x74 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C6MADDR - C6MADDR - DMA channel 6 memory address base register - 0x78 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C7CTRL - C7CTRL - DMA channel configuration register - 0x80 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C7DTCNT - C7DTCNT - DMA channel 7 number of data to transfer register - 0x84 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C7PADDR - C7PADDR - DMA channel 7 peripheral base address register - 0x88 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C7MADDR - C7MADDR - DMA channel 7 memory base address register - 0x8C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - DMA_SRC_SEL0 - DMA_SRC_SEL0 - DMA channel source assignment register - 0xA0 - 0x20 - read-write - 0x00000000 - - - CH1_SRC - CH1 SRC select - 0 - 8 - - - CH2_SRC - CH2 SRC select - 8 - 8 - - - CH3_SRC - CH3 SRC select - 16 - 8 - - - CH4_SRC - CH4 SRC select - 24 - 8 - - - - - DMA_SRC_SEL1 - DMA_SRC_SEL1 - DMA channel source assignment register - 0xA4 - 0x20 - read-write - 0x00000000 - - - CH5_SRC - CH5 SRC select - 0 - 8 - - - CH6_SRC - CH6 SRC select - 8 - 8 - - - CH7_SRC - CH7 SRC select - 16 - 8 - - - DMA_FLEX_EN - DMA FLEX Enable - 24 - 1 - - - - - - - ERTC - Real-time clock - ERTC - 0x40002800 - - 0x0 - 0x400 - registers - - - - TIME - TIME - time register - 0x0 - 0x20 - read-write - 0x00000000 - - - AMPM - AM/PM notation - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - DATE - DATE - date register - 0x4 - 0x20 - read-write - 0x00002101 - - - YT - Year tens - 20 - 4 - - - YU - Year units - 16 - 4 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - CTRL - CTRL - control register - 0x8 - 0x20 - read-write - 0x00000000 - - - CALOEN - Calibration output enable - 23 - 1 - - - OUTSEL - Output source selection - 21 - 2 - - - OUTP - Output polarity - 20 - 1 - - - CALOSEL - Calibration output selection - 19 - 1 - - - BPR - Battery power domain data register - 18 - 1 - - - DEC1H - Decrease 1 hour - 17 - 1 - - - ADD1H - Add 1 hour - 16 - 1 - - - TSIEN - Timestamp interrupt enable - 15 - 1 - - - WATIEN - Wakeup timer interrupt enable - 14 - 1 - - - ALAIEN - Alarm A interrupt enable - 12 - 1 - - - TSEN - Timestamp enable - 11 - 1 - - - WATEN - Wakeup timer enable - 10 - 1 - - - ALAEN - Alarm A enable - 8 - 1 - - - HM - Hour mode - 6 - 1 - - - DREN - Date/time register direct read enable - 5 - 1 - - - RCDEN - Reference clock detection enable - 4 - 1 - - - TSEDG - Timestamp trigger edge - 3 - 1 - - - WATCLK - Wakeup timer clock selection - 0 - 3 - - - - - STS - STS - initialization and status - register - 0xC - 0x20 - 0x00000007 - - - ALAWF - Alarm A register allows write flag - 0 - 1 - read-only - - - WATWF - Wakeup timer register allows write flag - 2 - 1 - read-only - - - TADJF - Time adjustment flag - 3 - 1 - read-write - - - INITF - Calendar initialization flag - 4 - 1 - read-only - - - UPDF - Calendar update flag - 5 - 1 - read-write - - - IMF - Enter initialization mode flag - 6 - 1 - read-only - - - IMEN - Initialization mode enable - 7 - 1 - read-write - - - ALAF - Alarm A flag - 8 - 1 - read-write - - - WATF - Wakeup timer flag - 10 - 1 - read-write - - - TSF - Timestamp flag - 11 - 1 - read-write - - - TSOF - Timestamp overflow flag - 12 - 1 - read-write - - - TP1F - Tamper detection 1 flag - 13 - 1 - read-write - - - CALUPDF - Calibration value update completed flag - 16 - 1 - read-only - - - - - DIV - DIV - Diveder register - 0x10 - 0x20 - read-write - 0x007F00FF - - - DIVA - Diveder A - 16 - 7 - - - DIVB - Diveder B - 0 - 15 - - - - - WAT - WAT - Wakeup timer register - 0x14 - 0x20 - read-write - 0x0000FFFF - - - VAL - Wakeup timer reload value - 0 - 16 - - - - - ALA - ALA - Alarm A register - 0x1C - 0x20 - read-write - 0x00000000 - - - MASK4 - Date/week mask - 31 - 1 - - - WKSEL - Date/week mode select - 30 - 1 - - - DT - Date tens - 28 - 2 - - - DU - Date units - 24 - 4 - - - MASK3 - Hours mask - 23 - 1 - - - AMPM - AM/PM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MASK2 - Minutes mask - 15 - 1 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - MASK1 - Seconds mask - 7 - 1 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - WP - WP - write protection register - 0x24 - 0x20 - write-only - 0x00000000 - - - CMD - Command register - 0 - 8 - - - - - SBS - SBS - sub second register - 0x28 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - TADJ - TADJ - time adjust register - 0x2C - 0x20 - write-only - 0x00000000 - - - ADD1S - Add 1 second - 31 - 1 - - - DECSBS - Decrease sub-second value - 0 - 15 - - - - - TSTM - TSTM - time stamp time register - 0x30 - 0x20 - read-only - 0x00000000 - - - AMPM - AMPM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - TSDT - TSDT - timestamp date register - 0x34 - 0x20 - read-only - 0x00000000 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - TSSBS - TSSBS - timestamp sub second register - 0x38 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - SCAL - SCAL - calibration register - 0x3C - 0x20 - read-write - 0x00000000 - - - ADD - Add ERTC clock - 15 - 1 - - - CAL8 - 8-second calibration period - 14 - 1 - - - CAL16 - 16 second calibration period - 13 - 1 - - - DEC - Decrease ERTC clock - 0 - 9 - - - - - TAMP - TAMP - tamper and alternate function configuration - register - 0x40 - 0x20 - read-write - 0x00000000 - - - OUTTYPE - Output type - 18 - 1 - - - TPPU - Tamper detection pull-up - 15 - 1 - - - TPPR - Tamper detection pre-charge time - 13 - 2 - - - TPFLT - Tamper detection filter time - 11 - 2 - - - TPFREQ - Tamper detection frequency - 8 - 3 - - - TPTSEN - Tamper detection timestamp enable - 7 - 1 - - - TPIEN - Tamper detection interrupt enable - 2 - 1 - - - TP1EDG - Tamper detection 1 valid edge - 1 - 1 - - - TP1EN - Tamper detection 1 enable - 0 - 1 - - - - - ALASBS - ALASBS - alarm A sub second register - 0x44 - 0x20 - read-write - 0x00000000 - - - SBSMSK - Sub-second mask - 24 - 4 - - - SBS - Sub-seconds value - 0 - 15 - - - - - BPR1DT - BPR1DT - Battery powered domain register - 0x50 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR2DT - BPR2DT - Battery powered domain register - 0x54 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR3DT - BPR3DT - Battery powered domain register - 0x58 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR4DT - BPR4DT - Battery powered domain register - 0x5C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR5DT - BPR5DT - Battery powered domain register - 0x60 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - - - WDT - Watchdog - WDT - 0x40003000 - - 0x0 - 0x400 - registers - - - - CMD - CMD - Command register - 0x0 - 0x20 - write-only - 0x00000000 - - - CMD - Command register - 0 - 16 - - - - - DIV - DIV - Division register - 0x4 - 0x20 - read-write - 0x00000000 - - - DIV - Division divider - 0 - 3 - - - - - RLD - RLD - Reload register - 0x8 - 0x20 - read-write - 0x00000FFF - - - RLD - Reload value - 0 - 12 - - - - - STS - STS - Status register - 0xC - 0x20 - read-only - 0x00000000 - - - DIVF - Division value update complete flag - 0 - 1 - - - RLDF - Reload value update complete flag - 1 - 1 - - - WINF - Window value update complete flag - 2 - 1 - - - - - WIN - WIN - Window register - 0x10 - 0x20 - read-write - 0x00000FFF - - - WIN - Window value - 0 - 12 - - - - - - - WWDT - Window watchdog - WWDT - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDT - Window Watchdog interrupt - 0 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - read-write - 0x0000007F - - - CNT - Decrement counter - 0 - 7 - - - WWDTEN - Window watchdog enable - 7 - 1 - - - - - CFG - CFG - Configuration register - 0x4 - 0x20 - read-write - 0x0000007F - - - WIN - Window value - 0 - 7 - - - DIV - Clock division value - 7 - 2 - - - RLDIEN - Reload counter interrupt - 9 - 1 - - - - - STS - STS - Status register - 0x8 - 0x20 - read-write - 0x00000000 - - - RLDF - Reload counter interrupt flag - 0 - 1 - - - - - - - TMR1 - Advanced timer - TIMER - 0x40012C00 - - 0x0 - 0x400 - registers - - - TMR1_CH - TMR1 channel interrupt - 14 - - - TMR1_BRK_OVF_TRG_HALL - TMR1 overflow brake trigger hall interrupt - 13 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C4IOS - Channel 4 idle output state - 14 - 1 - - - C3CIOS - Channel 3 complementary idle output state - 13 - 1 - - - C3IOS - Channel 3 idle output state - 12 - 1 - - - C2CIOS - Channel 2 complementary idle output state - 11 - 1 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3CP - Channel 3 complementary polarity - 11 - 1 - - - C3CEN - Channel 3 complementary enable - 10 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR2 - General purpose timer - TIMER - 0x40000000 - - 0x0 - 0x400 - registers - - - TMR2 - TMR2 global interrupt - 15 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR3 - General purpose timer - TIMER - 0x40000400 - - 0x0 - 0x400 - registers - - - TMR3 - TMR3 global interrupt - 16 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR6 - Basic timer - TIMER - 0x40001000 - - 0x0 - 0x400 - registers - - - TMR6 - TMR6 global interrupt - 17 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - PTOS - Primary TMR output selection - 4 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - - - TMR7 - 0x40001400 - - TMR7 - TMR7 global interrupt - 18 - - - - TMR13 - General-purpose-timers - TIMER - 0x40001C00 - - 0x0 - 0x400 - registers - - - TMR13 - TMR13 global interrupt - 35 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - - - TMR14 - General-purpose-timers - TIMER - 0x40002000 - - 0x0 - 0x400 - registers - - - TMR14 - TMR14 global interrupt - 19 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - RMP - RMP - TMR14 channel 1 input remap - 0x50 - 0x20 - read-write - 0x00000000 - - - TMR14_CH1_IRMP - TMR14 channel 1 input remap - 6 - 2 - - - - - - - TMR15 - General-purpose-timers - TIMER - 0x40014000 - - 0x0 - 0x400 - registers - - - TMR15 - TMR15 global interrupt - 20 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR16 - General-purpose-timers - TIMER - 0x40014400 - - 0x0 - 0x400 - registers - - - TMR16 - TMR16 global interrupt - 21 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR17 - 0x40014800 - - TMR17 - TMR17 global interrupt - 22 - - - - I2C1 - Inter-integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1_EVT - I2C1 event interrupt - 23 - - - I2C1_ERR - I2C1 error interrupt - 32 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - 0x00000000 - - - I2CEN - I2C peripheral enable - 0 - 1 - read-write - - - TDIEN - Transmit data interrupt enable - 1 - 1 - read-write - - - RDIEN - Receive data interrupt enable - 2 - 1 - read-write - - - ADDRIEN - Address match interrupt enable - 3 - 1 - read-write - - - ACKFAILIEN - Acknowledge fail interrupt enable - 4 - 1 - read-write - - - STOPIEN - Stop generation complete interrupt enable - 5 - 1 - read-write - - - TDCIEN - Transfer data complete interrupt enable - 6 - 1 - read-write - - - ERRIEN - Error interrupts enable - 7 - 1 - read-write - - - DFLT - Digital filter value - 8 - 4 - read-write - - - DMATEN - DMA Transmit data request enable - 14 - 1 - read-write - - - DMAREN - DMA receive data request enable - 15 - 1 - read-write - - - SCTRL - Slave receiving data control - 16 - 1 - read-write - - - STRETCH - Clock stretching mode - 17 - 1 - read-write - - - GCAEN - General call address enable - 19 - 1 - read-write - - - HADDREN - SMBus host address enable - 20 - 1 - read-write - - - DEVADDREN - SMBus device default address enable - 21 - 1 - read-write - - - SMBALERT - SMBus alert enable / pin set - 22 - 1 - read-write - - - PECEN - PEC calculation enable - 23 - 1 - read-write - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - PECTEN - Request PEC transmission enable - 26 - 1 - - - ASTOPEN - Automatically send stop condition enable - 25 - 1 - - - RLDEN - Send data reload mode enable - 24 - 1 - - - CNT - Transmit data counter - 16 - 8 - - - NACKEN - Not acknowledge enable - 15 - 1 - - - GENSTOP - Generate stop condition - 14 - 1 - - - GENSTART - Generate start condition - 13 - 1 - - - READH10 - 10-bit address header read enable - 12 - 1 - - - ADDR10 - Host send 10-bit address mode enable - 11 - 1 - - - DIR - Master data transmission direction - 10 - 1 - - - SADDR - Slave address - 0 - 10 - - - - - OADDR1 - OADDR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x00000000 - - - ADDR1 - Interface address - 0 - 10 - - - ADDR1MODE - Own Address mode - 10 - 1 - - - ADDR1EN - Own address 1 enable - 15 - 1 - - - - - OADDR2 - OADDR2 - Own address register 2 - 0xC - 0x20 - read-write - 0x00000000 - - - ADDR2 - Own address 2 - 1 - 7 - - - ADDR2MASK - Own address 2-bit mask - 8 - 3 - - - ADDR2EN - Own address 2 enable - 15 - 1 - - - - - CLKCTRL - CLKCTRL - Clock contorl register - 0x10 - 0x20 - read-write - 0x00000000 - - - SCLL - SCL low level - 0 - 8 - - - SCLH - SCL high level - 8 - 8 - - - SDAD - SDA output delay - 16 - 4 - - - SCLD - SCL output delay - 20 - 4 - - - DIVH - High 4 bits of clock divider value - 24 - 4 - - - DIVL - Low 4 bits of clock divider value - 28 - 4 - - - - - TIMEOUT - TIMEOUT - Timeout register - 0x14 - 0x20 - read-write - 0x00000000 - - - TOTIME - Clock timeout detection time - 0 - 12 - - - TOMOED - Clock timeout detection mode - 12 - 1 - - - TOEN - Detect clock low/high timeout enable - 15 - 1 - - - EXTTIME - Cumulative clock low extend timeout value - 16 - 12 - - - EXTEN - Cumulative clock low extend timeout enable - 31 - 1 - - - - - STS - STS - Interrupt and Status register - 0x18 - 0x20 - 0x00000001 - - - ADDR - Slave address matching value - 17 - 7 - read-only - - - SDIR - Slave data transmit direction - 16 - 1 - read-only - - - BUSYF - Bus busy - 15 - 1 - read-only - - - ALERTF - SMBus alert flag - 13 - 1 - read-only - - - TMOUT - SMBus timeout flag - 12 - 1 - read-only - - - PECERR - PEC receive error flag - 11 - 1 - read-only - - - OUF - Overflow or underflow flag - 10 - 1 - read-only - - - ARLOST - Arbitration lost flag - 9 - 1 - read-only - - - BUSERR - Bus error flag - 8 - 1 - read-only - - - TCRLD - Transmission is complete, waiting to load data - 7 - 1 - read-only - - - TDC - Transmit data complete flag - 6 - 1 - read-only - - - STOPF - Stop condition generation complete flag - 5 - 1 - read-only - - - ACKFAIL - Acknowledge failure flag - 4 - 1 - read-only - - - ADDRF - 0~7 bit address match flag - 3 - 1 - read-only - - - RDBF - Receive data buffer full flag - 2 - 1 - read-only - - - TDIS - Send interrupt status - 1 - 1 - read-write - - - TDBE - Transmit data buffer empty flag - 0 - 1 - read-write - - - - - CLR - CLR - Interrupt clear register - 0x1C - 0x20 - write-only - 0x00000000 - - - ALERTC - Clear SMBus alert flag - 13 - 1 - - - TMOUTC - Clear SMBus timeout flag - 12 - 1 - - - PECERRC - Clear PEC receive error flag - 11 - 1 - - - OUFC - Clear overload / underload flag - 10 - 1 - - - ARLOSTC - Clear arbitration lost flag - 9 - 1 - - - BUSERRC - Clear bus error flag - 8 - 1 - - - STOPC - Clear stop condition generation complete flag - 5 - 1 - - - ACKFAILC - Clear acknowledge failure flag - 4 - 1 - - - ADDRC - Clear 0~7 bit address match flag - 3 - 1 - - - - - PEC - PEC - PEC register - 0x20 - 0x20 - read-only - 0x00000000 - - - PECVAL - PEC value - 0 - 8 - - - - - RXDT - RXDT - Receive data register - 0x24 - 0x20 - read-only - 0x00000000 - - - DT - Receive data register - 0 - 8 - - - - - TXDT - TXDT - Transmit data register - 0x28 - 0x20 - read-write - 0x00000000 - - - DT - Transmit data register - 0 - 8 - - - - - - - I2C2 - 0x40005800 - - I2C2_EVT - I2C2 event interrupt - 24 - - - I2C2_ERR - I2C2 error interrupt - 34 - - - - CAN1 - Can controller area network - CAN - 0x40006400 - - 0x0 - 0x400 - registers - - - CAN1 - CAN1 global interrupt - 30 - - - - MCTRL - MCTRL - Main control register - 0x0 - 0x20 - read-write - 0x00010002 - - - PTD - Prohibit transmission when debug - 16 - 1 - - - SPRST - Software partial reset - 15 - 1 - - - TTCEN - Time triggered communication mode enable - 7 - 1 - - - AEBOEN - Automatic exit bus-off enable - 6 - 1 - - - AEDEN - Automatic exit doze mode enable - 5 - 1 - - - PRSFEN - Prohibit retransmission when sending fails enable - 4 - 1 - - - MDRSEL - Message discarding rule select when overflow - 3 - 1 - - - MMSSR - Multiple message sending sequence rule - 2 - 1 - - - DZEN - Doze mode enable - 1 - 1 - - - FZEN - Freeze mode enable - 0 - 1 - - - - - MSTS - MSTS - Main status register - 0x4 - 0x20 - 0x00000C02 - - - REALRX - Real time level of RX pin - 11 - 1 - read-only - - - LSAMPRX - Last sample level of RX pin - 10 - 1 - read-only - - - CURS - Currently receiving status - 9 - 1 - read-only - - - CUSS - Currently sending status - 8 - 1 - read-only - - - EDZIF - Enter doze mode interrupt flag - 4 - 1 - read-write - - - QDZIF - Quit doze mode interrupt flag - 3 - 1 - read-write - - - EOIF - Error occur Interrupt flag - 2 - 1 - read-write - - - DZC - Doze mode confirm - 1 - 1 - read-only - - - FZC - Freeze mode confirm - 0 - 1 - read-only - - - - - TSTS - TSTS - Transmit status register - 0x8 - 0x20 - 0x1C000000 - - - TM2LPF - Transmit mailbox 2 lowest priority flag - 31 - 1 - read-only - - - TM1LPF - Transmit mailbox 1 lowest priority flag - 30 - 1 - read-only - - - TM0LPF - Transmit mailbox 0 lowest priority flag - 29 - 1 - read-only - - - TM2EF - Transmit mailbox 2 empty flag - 28 - 1 - read-only - - - TM1EF - Transmit mailbox 1 empty flag - 27 - 1 - read-only - - - TM0EF - Transmit mailbox 0 empty flag - 26 - 1 - read-only - - - TMNR - Transmit Mailbox number record - 24 - 2 - read-only - - - TM2CT - Transmit mailbox 2 cancel transmission - 23 - 1 - read-write - - - TM2TEF - Transmit mailbox 2 transmission error flag - 19 - 1 - read-write - - - TM2ALF - Transmit mailbox 2 arbitration lost flag - 18 - 1 - read-write - - - TM2TSF - Transmit mailbox 2 transmission success flag - 17 - 1 - read-write - - - TM2TCF - transmit mailbox 2 transmission complete flag - 16 - 1 - read-write - - - TM1CT - Transmit mailbox 1 cancel transmission - 15 - 1 - read-write - - - TM1TEF - Transmit mailbox 1 transmission error flag - 11 - 1 - read-write - - - TM1ALF - Transmit mailbox 1 arbitration lost flag - 10 - 1 - read-write - - - TM1TSF - Transmit mailbox 1 transmission success flag - 9 - 1 - read-write - - - TM1TCF - Transmit mailbox 1 transmission complete flag - 8 - 1 - read-write - - - TM0CT - Transmit mailbox 0 cancel transmission - 7 - 1 - read-write - - - TM0TEF - Transmit mailbox 0 transmission error flag - 3 - 1 - read-write - - - TM0ALF - Transmit mailbox 0 arbitration lost flag - 2 - 1 - read-write - - - TM0TSF - Transmit mailbox 0 transmission success flag - 1 - 1 - read-write - - - TM0TCF - Transmit mailbox 0 transmission complete flag - 0 - 1 - read-write - - - - - RF0 - RF0 - Receive FIFO 0 register - 0xC - 0x20 - 0x00000000 - - - RF0R - Receive FIFO 0 release - 5 - 1 - read-write - - - RF0OF - Receive FIFO 0 overflow flag - 4 - 1 - read-write - - - RF0FF - Receive FIFO 0 full flag - 3 - 1 - read-write - - - RF0MN - Receive FIFO 0 message num - 0 - 2 - read-only - - - - - RF1 - RF1 - Receive FIFO 1 register - 0x10 - 0x20 - 0x00000000 - - - RF1R - Receive FIFO 1 release - 5 - 1 - read-write - - - RF1OF - Receive FIFO 1 overflow flag - 4 - 1 - read-write - - - RF1FF - Receive FIFO 1 full flag - 3 - 1 - read-write - - - RF1MN - Receive FIFO 1 message num - 0 - 2 - read-only - - - - - INTEN - INTEN - Interrupt enable register - 0x14 - 0x20 - read-write - 0x00000000 - - - EDZIEN - Enter doze mode interrupt enable - 17 - 1 - - - QDZIEN - Quit doze mode interrupt enable - 16 - 1 - - - EOIEN - Error occur interrupt enable - 15 - 1 - - - ETRIEN - Error type record interrupt enable - 11 - 1 - - - BOIEN - Bus-off interrupt enable - 10 - 1 - - - EPIEN - Error passive interrupt enable - 9 - 1 - - - EAIEN - Error active interrupt enable - 8 - 1 - - - RF1OIEN - Receive FIFO 1 overflow interrupt enable - 6 - 1 - - - RF1FIEN - Receive FIFO 1 full interrupt enable - 5 - 1 - - - RF1MIEN - FIFO 1 receive message interrupt enable - 4 - 1 - - - RF0OIEN - Receive FIFO 0 overflow interrupt enable - 3 - 1 - - - RF0FIEN - Receive FIFO 0 full interrupt enable - 2 - 1 - - - RF0MIEN - FIFO 0 receive message interrupt enable - 1 - 1 - - - TCIEN - Transmission complete interrupt enable - 0 - 1 - - - - - ESTS - ESTS - Error status register - 0x18 - 0x20 - 0x00000000 - - - REC - Receive error counter - 24 - 8 - read-only - - - TEC - Transmit error counter - 16 - 8 - read-only - - - ETR - Error type record - 4 - 3 - read-write - - - BOF - Bus-off flag - 2 - 1 - read-only - - - EPF - Error passive flag - 1 - 1 - read-only - - - EAF - Error active flag - 0 - 1 - read-only - - - - - BTMG - BTMG - Bit timing register - 0x1C - 0x20 - read-write - 0x00000000 - - - LOEN - Listen-Only mode - 31 - 1 - - - LBEN - Loop back mode - 30 - 1 - - - RSAW - Resynchronization adjust width - 24 - 2 - - - BTS2 - Bit time segment 2 - 20 - 3 - - - BTS1 - Bit time segment 1 - 16 - 4 - - - BRDIV - Baud rate division - 0 - 12 - - - - - TMI0 - TMI0 - Transmit mailbox 0 identifier register - 0x180 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC0 - TMC0 - Transmit mailbox 0 data length and time stamp register - 0x184 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL0 - TMDTL0 - Transmit mailbox 0 low byte data register - 0x188 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH0 - TMDTH0 - Transmit mailbox 0 high byte data register - 0x18C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI1 - TMI1 - Transmit mailbox 1 identifier register - 0x190 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC1 - TMC1 - Transmit mailbox 1 data length and time stamp register - 0x194 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL1 - TMDTL1 - Transmit mailbox 1 low byte data register - 0x198 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH1 - TMDTH1 - Transmit mailbox 1 high byte data register - 0x19C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI2 - TMI2 - Transmit mailbox 2 identifier register - 0x1A0 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC2 - TMC2 - Transmit mailbox 2 data length and time stamp register - 0x1A4 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL2 - TMDTL2 - Transmit mailbox 2 low byte data register - 0x1A8 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH2 - TMDTH2 - Transmit mailbox 2 high byte data register - 0x1AC - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - RFI0 - RFI0 - Receive FIFO 0 register - 0x1B0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC0 - RFC0 - Receive FIFO 0 data length and time stamp register - 0x1B4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL0 - RFDTL0 - Receive FIFO 0 low byte data register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH0 - RFDTH0 - Receive FIFO 0 high byte data register - 0x1BC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - RFI1 - RFI1 - Receive FIFO 1 register - 0x1C0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC1 - RFC1 - Receive FIFO 1 data length and time stamp register - 0x1C4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL1 - RFDTL1 - Receive FIFO 1 low byte data register - 0x1C8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH1 - RFDTH1 - Receive FIFO 1 high byte data register - 0x1CC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - FCTRL - FCTRL - Filter control register - 0x200 - 0x20 - read-write - 0x00000000 - - - FCS - Filters configure switch - 0 - 1 - - - - - FMCFG - FMCFG - Filter mode config register - 0x204 - 0x20 - read-write - 0x00000000 - - - FMSEL0 - Filter mode select - 0 - 1 - - - FMSEL1 - Filter mode select - 1 - 1 - - - FMSEL2 - Filter mode select - 2 - 1 - - - FMSEL3 - Filter mode select - 3 - 1 - - - FMSEL4 - Filter mode select - 4 - 1 - - - FMSEL5 - Filter mode select - 5 - 1 - - - FMSEL6 - Filter mode select - 6 - 1 - - - FMSEL7 - Filter mode select - 7 - 1 - - - FMSEL8 - Filter mode select - 8 - 1 - - - FMSEL9 - Filter mode select - 9 - 1 - - - FMSEL10 - Filter mode select - 10 - 1 - - - FMSEL11 - Filter mode select - 11 - 1 - - - FMSEL12 - Filter mode select - 12 - 1 - - - FMSEL13 - Filter mode select - 13 - 1 - - - - - FBWCFG - FBWCFG - Filter bit width config register - 0x20C - 0x20 - read-write - 0x00000000 - - - FBWSEL0 - Filter bit width select - 0 - 1 - - - FBWSEL1 - Filter bit width select - 1 - 1 - - - FBWSEL2 - Filter bit width select - 2 - 1 - - - FBWSEL3 - Filter bit width select - 3 - 1 - - - FBWSEL4 - Filter bit width select - 4 - 1 - - - FBWSEL5 - Filter bit width select - 5 - 1 - - - FBWSEL6 - Filter bit width select - 6 - 1 - - - FBWSEL7 - Filter bit width select - 7 - 1 - - - FBWSEL8 - Filter bit width select - 8 - 1 - - - FBWSEL9 - Filter bit width select - 9 - 1 - - - FBWSEL10 - Filter bit width select - 10 - 1 - - - FBWSEL11 - Filter bit width select - 11 - 1 - - - FBWSEL12 - Filter bit width select - 12 - 1 - - - FBWSEL13 - Filter bit width select - 13 - 1 - - - - - FRF - FRF - Filter related FIFO register - 0x214 - 0x20 - read-write - 0x00000000 - - - FRFSEL0 - Filter relation FIFO select - 0 - 1 - - - FRFSEL1 - Filter relation FIFO select - 1 - 1 - - - FRFSEL2 - Filter relation FIFO select - 2 - 1 - - - FRFSEL3 - Filter relation FIFO select - 3 - 1 - - - FRFSEL4 - Filter relation FIFO select - 4 - 1 - - - FRFSEL5 - Filter relation FIFO select - 5 - 1 - - - FRFSEL6 - Filter relation FIFO select - 6 - 1 - - - FRFSEL7 - Filter relation FIFO select - 7 - 1 - - - FRFSEL8 - Filter relation FIFO select - 8 - 1 - - - FRFSEL9 - Filter relation FIFO select - 9 - 1 - - - FRFSEL10 - Filter relation FIFO select - 10 - 1 - - - FRFSEL11 - Filter relation FIFO select - 11 - 1 - - - FRFSEL12 - Filter relation FIFO select - 12 - 1 - - - FRFSEL13 - Filter relation FIFO select - 13 - 1 - - - - - FACFG - FACFG - Filter activate configuration register - 0x21C - 0x20 - read-write - 0x00000000 - - - FAEN0 - Filter activate enable - 0 - 1 - - - FAEN1 - Filter activate enable - 1 - 1 - - - FAEN2 - Filter activate enable - 2 - 1 - - - FAEN3 - Filter activate enable - 3 - 1 - - - FAEN4 - Filter activate enable - 4 - 1 - - - FAEN5 - Filter activate enable - 5 - 1 - - - FAEN6 - Filter activate enable - 6 - 1 - - - FAEN7 - Filter activate enable - 7 - 1 - - - FAEN8 - Filter activate enable - 8 - 1 - - - FAEN9 - Filter activate enable - 9 - 1 - - - FAEN10 - Filter activate enable - 10 - 1 - - - FAEN11 - Filter activate enable - 11 - 1 - - - FAEN12 - Filter activate enable - 12 - 1 - - - FAEN13 - Filter activate enable - 13 - 1 - - - - - F0FB1 - F0FB1 - Filter bank 0 filtrate bit register 1 - 0x240 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F0FB2 - F0FB2 - Filter bank 0 filtrate bit register 2 - 0x244 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB1 - F1FB1 - Filter bank 1 filtrate bit register 1 - 0x248 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB2 - F1FB2 - Filter bank 1 filtrate bit register 2 - 0x24C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB1 - F2FB1 - Filter bank 2 filtrate bit register 1 - 0x250 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB2 - F2FB2 - Filter bank 2 filtrate bit register 2 - 0x254 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB1 - F3FB1 - Filter bank 3 filtrate bit register 1 - 0x258 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB2 - F3FB2 - Filter bank 3 filtrate bit register 2 - 0x25C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB1 - F4FB1 - Filter bank 4 filtrate bit register 1 - 0x260 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB2 - F4FB2 - Filter bank 4 filtrate bit register 2 - 0x264 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB1 - F5FB1 - Filter bank 5 filtrate bit register 1 - 0x268 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB2 - F5FB2 - Filter bank 5 filtrate bit register 2 - 0x26C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB1 - F6FB1 - Filter bank 6 filtrate bit register 1 - 0x270 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB2 - F6FB2 - Filter bank 6 filtrate bit register 2 - 0x274 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB1 - F7FB1 - Filter bank 7 filtrate bit register 1 - 0x278 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB2 - F7FB2 - Filter bank 7 filtrate bit register 2 - 0x27C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB1 - F8FB1 - Filter bank 8 filtrate bit filtrate bit register 1 - 0x280 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB2 - F8FB2 - Filter bank 8 filtrate bit filtrate bit register 2 - 0x284 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB1 - F9FB1 - Filter bank 9 filtrate bit filtrate bit filtrate bit filtrate bit filtrate bit register 1 - 0x288 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB2 - F9FB2 - Filter bank 9 filtrate bit filtrate bit filtrate bit filtrate bit filtrate bit register 2 - 0x28C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB1 - F10FB1 - Filter bank 10 filtrate bit register 1 - 0x290 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB2 - F10FB2 - Filter bank 10 filtrate bit register 2 - 0x294 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB1 - F11FB1 - Filter bank 11 filtrate bit register 1 - 0x298 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB2 - F11FB2 - Filter bank 11 filtrate bit register 2 - 0x29C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB1 - F12FB1 - Filter bank 12 filtrate bit filtrate bit register 1 - 0x2A0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB2 - F12FB2 - Filter bank 12 filtrate bit filtrate bit register 2 - 0x2A4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB1 - F13FB1 - Filter bank 13 filtrate bit filtrate bit register 1 - 0x2A8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB2 - F13FB2 - Filter bank 13 filtrate bit filtrate bit register 2 - 0x2AC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - - ACC - HSI Auto Clock Calibration - ACC - 0x40006C00 - - 0x0 - 0x400 - registers - - - ACC - ACC interrupts - 8 - - - - STS - STS - status register - 0x0 - 0x20 - 0x0000 - - - RSLOST - Reference Signal Lost - read-write - 1 - 1 - - - CALRDY - Internal high-speed clock calibration ready - read-write - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x04 - 0x20 - 0x0100 - - - STEP - STEP - read-write - 8 - 4 - - - CALRDYIEN - CALRDY interrupt enable - read-write - 5 - 1 - - - EIEN - RSLOST error interrupt enable - read-write - 4 - 1 - - - ENTRIM - Enable trim - read-write - 1 - 1 - - - CALON - Calibration on - read-write - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x08 - 0x20 - 0x2080 - - - ACC_HSITRIM - Internal high-speed auto clock trimming - read-only - 8 - 6 - - - ACC_HSICAL - Internal high-speed auto clock calibration - read-only - 0 - 8 - - - - - C1 - C1 - compare value 1 - 0x0C - 0x20 - 0x1F2C - - - C1 - Compare 1 - read-write - 0 - 16 - - - - - C2 - C2 - compare value 2 - 0x10 - 0x20 - 0x1F40 - - - C2 - Compare 2 - read-write - 0 - 16 - - - - - C3 - C3 - compare value 3 - 0x14 - 0x20 - 0x1F54 - - - C3 - Compare 3 - read-write - 0 - 16 - - - - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global interrupt - 25 - - - - CTRL1 - CTRL1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SLBEN - Single line bidirectional half-duplex enable - 15 - 1 - - - SLBTD - Single line bidirectional half-duplex transmission direction - 14 - 1 - - - CCEN - CRC calculation enable - 13 - 1 - - - NTC - Next transmission CRC - 12 - 1 - - - FBN - frame bit num - 11 - 1 - - - ORA - Only receive active - 10 - 1 - - - SWCSEN - Software CS enable - 9 - 1 - - - SWCSIL - Software CS internal level - 8 - 1 - - - LTF - LSB transmit first - 7 - 1 - - - SPIEN - SPI enable - 6 - 1 - - - MDIV2_0 - Master clock frequency division bit2-0 - 3 - 3 - - - MSTEN - Master enable - 2 - 1 - - - CLKPOL - Clock polarity - 1 - 1 - - - CLKPHA - Clock phase - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MDIV3EN - Master clock frequency 3 division enable - 9 - 1 - - - MDIV3 - Master clock frequency division bit3 - 8 - 1 - - - TDBEIE - Transmit data buffer empty interrupt enable - 7 - 1 - - - RDBFIE - Receive data buffer full interrupt enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - TIEN - TI mode enable - 4 - 1 - - - HWCSOE - Hardware CS output enable - 2 - 1 - - - DMATEN - DMA transmit enable - 1 - 1 - - - DMAREN - DMA receive enable - 0 - 1 - - - - - STS - STS - status register - 0x8 - 0x20 - 0x0002 - - - CSPAS - CS pulse abnormal setting fiag - 8 - 1 - read-only - - - BF - Busy flag - 7 - 1 - read-only - - - ROERR - Receiver overflow error - 6 - 1 - read-only - - - MMERR - Master mode error - 5 - 1 - read-only - - - CCERR - CRC calculation error - 4 - 1 - read-write - - - TUERR - Transmitter underload error - 3 - 1 - read-only - - - ACS - Audio channel state - 2 - 1 - read-only - - - TDBE - Transmit data buffer empty - 1 - 1 - read-only - - - RDBF - Receive data buffer full - 0 - 1 - read-only - - - - - DT - DT - data register - 0xC - 0x20 - read-write - 0x0000 - - - DT - Data value - 0 - 16 - - - - - CPOLY - CPOLY - CRC polynomial register - 0x10 - 0x20 - read-write - 0x0007 - - - CPOLY - CRC polynomial - 0 - 16 - - - - - RCRC - RCRC - Receive CRC register - 0x14 - 0x20 - read-only - 0x0000 - - - RCRC - Receive CRC - 0 - 16 - - - - - TCRC - TCRC - Transmit CRC register - 0x18 - 0x20 - read-only - 0x0000 - - - TCRC - Transmit CRC - 0 - 16 - - - - - I2SCTRL - I2SCTRL - I2S control register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SMSEL - I2S mode select - 11 - 1 - - - I2SEN - I2S Enable - 10 - 1 - - - OPERSEL - I2S operation select - 8 - 2 - - - PCMFSSEL - PCM frame synchronization select - 7 - 1 - - - STDSEL - I2S standard select - 4 - 2 - - - I2SCLKPOL - I2S clock polarity - 3 - 1 - - - I2SDBN - I2S data bit num - 1 - 2 - - - I2SCBN - I2S channel bit num - 0 - 1 - - - - - I2SCLK - I2SCLK - I2S clock register - 0x20 - 0x20 - read-write - 00000010 - - - I2SDIV9_8 - I2S division bit9 and bit8 - 10 - 2 - - - I2SMCLKOE - I2S master clock output enable - 9 - 1 - - - I2SODD - Odd result for I2S division - 8 - 1 - - - I2SDIV7_0 - I2S division bit7 to bit0 - 0 - 8 - - - - - - - SPI2 - 0x40003800 - - SPI2 - SPI2 global interrupt - 26 - - - - SPI3 - 0x40003C00 - - SPI3 - SPI3 global interrupt - 33 - - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40013800 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global interrupt - 27 - - - - STS - STS - Status register - 0x0 - 0x20 - 0x00C0 - - - CTSCF - CTS change flag - 9 - 1 - read-write - - - BFF - Break frame flag - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - 7 - 1 - read-only - - - TDC - Transmit data complete - 6 - 1 - read-write - - - RDBF - Receive data buffer full - 5 - 1 - read-write - - - IDLEF - IDLE flag - 4 - 1 - read-only - - - ROERR - Receiver overflow error - 3 - 1 - read-only - - - NERR - Noise error - 2 - 1 - read-only - - - FERR - Framing error - 1 - 1 - read-only - - - PERR - Parity error - 0 - 1 - read-only - - - - - DT - DT - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DT - Data value - 0 - 9 - - - - - BAUDR - BAUDR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV - Division - 0 - 16 - - - - - CTRL1 - CTRL1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - DBN1 - high bit for Data bit num - 28 - 1 - - - TSDT - transmit start delay time - 21 - 5 - - - TCDT - transmit complete delay time - 16 - 5 - - - UEN - USART enable - 13 - 1 - - - DBN0 - Data bit num - 12 - 1 - - - WUM - Wake up mode - 11 - 1 - - - PEN - Parity enable - 10 - 1 - - - PSEL - Parity selection - 9 - 1 - - - PERRIEN - PERR interrupt enable - 8 - 1 - - - TDBEIEN - TDBE interrupt enable - 7 - 1 - - - TDCIEN - TDC interrupt enable - 6 - 1 - - - RDBFIEN - RDBF interrupt enable - 5 - 1 - - - IDLEIEN - IDLE interrupt enable - 4 - 1 - - - TEN - Transmitter enable - 3 - 1 - - - REN - Receiver enable - 2 - 1 - - - RM - Receiver mute - 1 - 1 - - - SBF - Send break frame - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - ID7_4 - bit 7-4 for usart identification - 28 - 4 - - - TRPSWAP - Transmit receive pin swap - 15 - 1 - - - LINEN - LIN mode enable - 14 - 1 - - - STOPBN - STOP bit num - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CLKPOL - Clock polarity - 10 - 1 - - - CLKPHA - Clock phase - 9 - 1 - - - LBCP - Last bit clock pulse - 8 - 1 - - - BFIEN - Break frame interrupt enable - 6 - 1 - - - BFBN - Break frame bit num - 5 - 1 - - - ID - USART identification - 0 - 4 - - - - - CTRL3 - CTRL3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - DEP - DE polarity selection - 15 - 1 - - - RS485EN - RS485 enable - 14 - 1 - - - CTSCFIEN - CTSCF interrupt enable - 10 - 1 - - - CTSEN - CTS enable - 9 - 1 - - - RTSEN - RTS enable - 8 - 1 - - - DMATEN - DMA transmitter enable - 7 - 1 - - - DMAREN - DMA receiver enable - 6 - 1 - - - SCMEN - Smartcard mode enable - 5 - 1 - - - SCNACKEN - Smartcard NACK enable - 4 - 1 - - - SLBEN - Single line bidirectional half-duplex enable - 3 - 1 - - - IRDALP - IrDA low-power mode - 2 - 1 - - - IRDAEN - IrDA enable - 1 - 1 - - - ERRIEN - Error interrupt enable - 0 - 1 - - - - - GDIV - GDIV - Guard time and division register - 0x18 - 0x20 - read-write - 0x0000 - - - SCGT - Smart card guard time value - 8 - 8 - - - ISDIV - IrDA/smartcard division value - 0 - 8 - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global interrupt - 28 - - - - USART3 - 0x40004800 - - USART3 - USART4_3 global interrupt - 29 - - - - USART4 - 0x40004C00 - - - ADC - Analog to digital converter - ADC - 0x40012400 - - 0x0 - 0x400 - registers - - - ADC1 - ADC1 global interrupt - 12 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - CCE - Channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - CCEIEN - Channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - ITSRVEN - Internal temperature sensor and VINTRV enable - 23 - 1 - - - OCSWTRG - Conversion trigger by software of ordinary channels - 22 - 1 - - - PCSWTRG - Conversion trigger by software of preempted channels - 21 - 1 - - - OCTEN - Trigger mode enable for ordinary channels conversion - 20 - 1 - - - OCTESEL - Low bit of trigger event select for ordinary channels conversion - 17 - 3 - - - PCTEN - Trigger mode enable for preempted channels conversion - 15 - 1 - - - PCTESEL - Low bit of trigger event select for preempted channels conversion - 12 - 3 - - - DTALIGN - Data alignment - 11 - 1 - - - OCDMAEN - DMA transfer enable of ordinary channels - 8 - 1 - - - ADCALINIT - initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 12 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 12 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 4 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - OVSP - OVSP - oversampling register - 0x80 - 0x20 - read-write - 0x00000000 - - - OOSRSEL - Ordinary oversampling recovery mode select - 10 - 1 - - - OOSTREN - Ordinary oversampling trigger mode enable - 9 - 1 - - - OSSSEL - Oversampling shift select - 5 - 4 - - - OSRSEL - Oversampling ratio select - 2 - 3 - - - POSEN - Preempted oversampling enable - 1 - 1 - - - OOSEN - Ordinary oversampling enable - 0 - 1 - - - - - - - SCFG - System configuration controller - SCFG - 0x40010000 - - 0x0 - 0x400 - registers - - - - CFG1 - CFG1 - configuration register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - MEM_MAP_SEL - Memory mapping selection - bits - 0 - 2 - - - PA11_12_RMP - PA11/PA12 pins remapping bit - 4 - 1 - - - IR_POL - Infrared output polarity selection - 5 - 1 - - - IR_SRC_SEL - Infrared modulation envelope signal source selection - 6 - 2 - - - PB14_UH - PB14 Ultra high sourcing/sinking strength - 16 - 1 - - - PB13_UH - PB13 Ultra high sourcing/sinking strength - 17 - 1 - - - PB9_UH - PB9 Ultra high sourcing/sinking strength - 18 - 1 - - - PB8_UH - PB8 Ultra high sourcing/sinking strength - 19 - 1 - - - - - EXTIC1 - EXTIC1 - external interrupt configuration register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - EXTINT3 - EXTINT 3 configuration bits - 12 - 4 - - - EXTINT2 - EXTINT 2 configuration bits - 8 - 4 - - - EXTINT1 - EXTINT 1 configuration bits - 4 - 4 - - - EXTINT0 - EXTINT 0 configuration bits - 0 - 4 - - - - - EXTIC2 - EXTIC2 - external interrupt configuration register 2 - 0xC - 0x20 - read-write - 0x0000 - - - EXTINT7 - EXTINT 7 configuration bits - 12 - 4 - - - EXTINT6 - EXTINT 6 configuration bits - 8 - 4 - - - EXTINT5 - EXTINT 5 configuration bits - 4 - 4 - - - EXTINT4 - EXTINT 4 configuration bits - 0 - 4 - - - - - EXTIC3 - EXTIC3 - external interrupt configuration register 3 - 0x10 - 0x20 - read-write - 0x0000 - - - EXTINT11 - EXTINT 11 configuration bits - 12 - 4 - - - EXTINT10 - EXTINT 10 configuration bits - 8 - 4 - - - EXTINT9 - EXTINT 9 configuration bits - 4 - 4 - - - EXTINT8 - EXTINT 8 configuration bits - 0 - 4 - - - - - EXTIC4 - EXTIC4 - external interrupt configuration register 4 - 0x14 - 0x20 - read-write - 0x0000 - - - EXTINT15 - EXTINT 15 configuration bits - 12 - 4 - - - EXTINT14 - EXTINT 14 configuration bits - 8 - 4 - - - EXTINT13 - EXTINT 13 configuration bits - 4 - 4 - - - EXTINT12 - EXTINT 12 configuration bits - 0 - 4 - - - - - CFG2 - CFG2 - configuration register 2 - 0x18 - 0x20 - read-write - 0x00000000 - - - PVM_LK - PVM lock enable - 2 - 1 - - - I2S_FD - I2S full duplex - 30 - 2 - - - - - - - DEBUG - Debug support - DEBUG - 0xE0042000 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - DEBUG_IDCODE - 0x0 - 0x20 - read-only - 0x0 - - - PID - PID - 0 - 32 - - - - - CTRL - CTRL - DEBUG_CTRL - 0x4 - 0x20 - read-write - 0x0 - - - SLEEP_DEBUG - SLEEP_DEBUG - 0 - 1 - - - DEEPSLEEP_DEBUG - DEEPSLEEP_DEBUG - 1 - 1 - - - STANDBY_DEBUG - STANDBY_DEBUG - 2 - 1 - - - CAN_PAUSE - CAN_PAUSE - 3 - 1 - - - WDT_PAUSE - WDT_PAUSE - 8 - 1 - - - WWDT_PAUSE - WWDT_PAUSE - 9 - 1 - - - TMR1_PAUSE - TMR1_PAUSE - 10 - 1 - - - TMR2_PAUSE - TMR2_PAUSE - 11 - 1 - - - TMR3_PAUSE - TMR3_PAUSE - 12 - 1 - - - ERTC_PAUSE - ERTC_PAUSE - 14 - 1 - - - I2C1_SMBUS_TIMEOUT - I2C1_SMBUS_TIMEOUT - 15 - 1 - - - I2C2_SMBUS_TIMEOUT - I2C2_SMBUS_TIMEOUT - 16 - 1 - - - TMR6_PAUSE - TMR6_PAUSE - 19 - 1 - - - TMR7_PAUSE - TMR7_PAUSE - 20 - 1 - - - ERTC_512_PAUSE - ERTC_512_PAUSE - 21 - 1 - - - TMR15_PAUSE - TMR15_PAUSE - 22 - 1 - - - TMR16_PAUSE - TMR16_PAUSE - 23 - 1 - - - TMR17_PAUSE - TMR17_PAUSE - 24 - 1 - - - TMR13_PAUSE - TMR13_PAUSE - 26 - 1 - - - TMR14_PAUSE - TMR14_PAUSE - 27 - 1 - - - - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DT - DT - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DT - Data Register - 0 - 32 - - - - - CDT - CDT - Common data register - 0x4 - 0x20 - read-write - 0x00000000 - - - CDT - Common Data - 0 - 1 - - - - - CTRL - CTRL - Control register - 0x8 - 0x20 - read-write - 0x00000000 - - - RST - Reset bit - 0 - 1 - - - REVID - Reverse input data - 5 - 2 - - - REVOD - Reverse output data - 7 - 1 - - - - - IDT - IDT - Initial data register - 0x10 - 0x20 - read-write - 0xFFFFFFFF - - - IDT - Initial Data - 0 - 32 - - - - - - - FLASH - Flash memory controler - FLASH - 0x40022000 - - 0x0 - 0x400 - registers - - - FLASH - Flash global interrupt - 3 - - - - PSR - PSR - Performance selection register - 0x0 - 0x20 - 0x00000030 - - - WTCYC - Wait cycle - 0 - 3 - read-write - - - HFCYC_EN - Half cycle acceleration access enable - 3 - 1 - read-write - - - PFT_EN - Prefetch enable - 4 - 1 - read-write - - - PFT_ENF - Prefetch enabled flag - 5 - 1 - read-only - - - PFT_EN2 - Prefetch enable 2 - 6 - 1 - read-write - - - PFT_ENF2 - Prefetch enabled flag 2 - 7 - 1 - read-only - - - PFT_LAT_DIS - Prefetch latency disable - 8 - 1 - read-write - - - - - UNLOCK - UNLOCK - Unlock register - 0x4 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - USD_UNLOCK - USD_UNLOCK - USD unlock register - 0x8 - 0x20 - write-only - 0x00000000 - - - USD_UKVAL - User system data Unlock key value - 0 - 32 - - - - - STS - STS - Status register - 0xC - 0x20 - 0x00000000 - - - ODF - Operate done flag - 5 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - PRGMERR - program error - 2 - 1 - read-write - - - OBF - Operate busy flag - 0 - 1 - read-only - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00020080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - USDPRGM - User system data program - 4 - 1 - - - USDERS - User system data erase - 5 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - USDULKS - User system data unlock success - 9 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - LPMEN - Low power mode enable - 17 - 1 - - - - - ADDR - ADDR - Address register - 0x14 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - USD - USD - User system data register - 0x1C - 0x20 - read-only - 0x03FFFFFC - - - USDERR - User system data error - 0 - 1 - - - FAP - FLASH access protection - 1 - 1 - - - nWDT_ATO_EN - WDT auto enable - 2 - 1 - - - nDEPSLP_RST - Deepsleep reset - 3 - 1 - - - nSTDBY_RST - Standby reset - 4 - 1 - - - nBOOT1 - boot1 - 6 - 1 - - - nDEPSLP_WDT - Deepsleep wdt stop count - 7 - 1 - - - nSTDBY_WDT - Standby wdt stop count - 8 - 1 - - - USER_D0 - User data 0 - 10 - 8 - - - USER_D1 - User data 1 - 18 - 8 - - - FAP_HL - FAP high level - 26 - 1 - - - - - EPPS - EPPS - Erase/program protection status register - 0x20 - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - SLIB_STS0 - SLIB_STS0 - sLib status 0 register - 0x74 - 0x20 - 0x00000000 - - - BTM_AP_ENF - Boot memory store application code enabled flag - 0 - 1 - - - EM_SLIB_ENF - Extension memory sLib enabled flag - 2 - 1 - - - SLIB_ENF - sLib enabled flag - 3 - 1 - - - EM_SLIB_INST_SS - Extension memory sLib instruction start sector - 16 - 8 - - - - - SLIB_STS1 - SLIB_STS1 - sLib status 1 register - 0x78 - 0x20 - 0x00000000 - - - SLIB_SS - sLib start sector - 0 - 11 - - - SLIB_INST_SS - sLib instruction start sector - 11 - 11 - - - SLIB_ES - sLib end sector - 22 - 10 - - - - - SLIB_PWD_CLR - SLIB_PWD_CLR - SLIB password clear register - 0x7C - 0x20 - 0x00000000 - write-only - - - SLIB_PCLR_VAL - sLib password clear value - 0 - 32 - - - - - SLIB_MISC_STS - SLIB_MISC_STS - sLib misc status register - 0x80 - 0x20 - 0x01000000 - - - SLIB_PWD_ERR - sLib password error - 0 - 1 - read-only - - - SLIB_PWD_OK - sLib password ok - 1 - 1 - read-only - - - SLIB_ULKF - sLib unlock flag - 2 - 1 - read-only - - - - - CRC_ADDR - CRC_ADDR - Flash CRC data start address register - 0x84 - 0x20 - write-only - 0x00000000 - - - CRC_ADDR - CRC address - 0 - 32 - - - - - CRC_CTRL - CRC_CTRL - Flash CRC controll register - 0x88 - 0x20 - 0x00000000 - - - CRC_SN - CRC sector numbler - 0 - 16 - read-write - - - CRC_STRT - CRC start - 16 - 1 - write-only - - - - - CRC_CHKR - CRC_CHKR - FLASH CRC check result register - 0x8C - 0x20 - read-only - 0x00000000 - - - FCRC_OUT - CRC32 verification result of flash user code or SLIB code - 0 - 32 - - - - - SLIB_SET_PWD - SLIB_SET_PWD - sLib password setting register - 0x160 - 0x20 - write-only - 0x00000000 - - - SLIB_PSET_VAL - sLib password setting val - 0 - 32 - - - - - SLIB_SET_RANGE - SLIB_SET_RANGE - Configure sLib range register - 0x164 - 0x20 - write-only - 0x00000000 - - - SLIB_SS_SET - sLib start sector setting - 0 - 11 - - - SLIB_ISS_SET - sLib instruction start sector setting - 11 - 11 - - - SLIB_ES_SET - sLib end sector setting - 22 - 10 - - - - - EM_SLIB_SET - EM_SLIB_SET - Extension momery slib set register - 0x168 - 0x20 - write-only - 0x00000000 - - - EM_SLIB_SET - Extension memory sLib setting - 0 - 16 - - - EM_SLIB_ISS_SET - Extension memory sLib instruction start sector setting - 16 - 8 - - - - - BTM_MODE_SET - BTM_MODE_SET - Boot memory mode setting register - 0x16C - 0x20 - write-only - 0x00000000 - - - BTM_MODE_SET - Boot memory mode setting - 0 - 8 - - - - - SLIB_UNLOCK - SLIB_UNLOCK - sLib unlock register - 0x170 - 0x20 - write-only - 0x00000000 - - - SLIB_UKVAL - sLib unlock key value - 0 - 32 - - - - - - - NVIC - Nested Vectored Interrupt - Controller - NVIC - 0xE000E000 - - 0x0 - 0x1001 - registers - - - - ICTR - ICTR - Interrupt Controller Type - Register - 0x4 - 0x20 - read-only - 0x00000000 - - - INTLINESNUM - Total number of interrupt lines in - groups - 0 - 4 - - - - - STIR - STIR - Software Triggered Interrupt - Register - 0xF00 - 0x20 - write-only - 0x00000000 - - - INTID - interrupt to be triggered - 0 - 9 - - - - - ISER0 - ISER0 - Interrupt Set-Enable Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER1 - ISER1 - Interrupt Set-Enable Register - 0x104 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ICER0 - ICER0 - Interrupt Clear-Enable - Register - 0x180 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear-Enable - Register - 0x184 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x200 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x204 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending - Register - 0x280 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending - Register - 0x284 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - IABR0 - IABR0 - Interrupt Active Bit Register - 0x300 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IABR1 - IABR1 - Interrupt Active Bit Register - 0x304 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IPR0 - IPR0 - Interrupt Priority Register - 0x400 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR1 - IPR1 - Interrupt Priority Register - 0x404 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR2 - IPR2 - Interrupt Priority Register - 0x408 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR3 - IPR3 - Interrupt Priority Register - 0x40C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR4 - IPR4 - Interrupt Priority Register - 0x410 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR5 - IPR5 - Interrupt Priority Register - 0x414 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR6 - IPR6 - Interrupt Priority Register - 0x418 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR7 - IPR7 - Interrupt Priority Register - 0x41C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR8 - IPR8 - Interrupt Priority Register - 0x420 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR9 - IPR9 - Interrupt Priority Register - 0x424 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR10 - IPR10 - Interrupt Priority Register - 0x428 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR11 - IPR11 - Interrupt Priority Register - 0x42C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR12 - IPR12 - Interrupt Priority Register - 0x430 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR13 - IPR13 - Interrupt Priority Register - 0x434 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR14 - IPR14 - Interrupt Priority Register - 0x438 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - - - USB_OTG1_GLOBAL - USB on-the-go full speed - USB_OTG1 - 0x50000000 - - 0x0 - 0x400 - registers - - - OTGFS1 - USB On The Go FS global - interrupt - 67 - - - - GOTGCTL - GOTGCTL - OTGFS control and status register - (OTGFS_GOTGCTL) - 0x0 - 0x20 - 0x00000800 - - - CONIDSTS - Connector ID status - 16 - 1 - read-only - - - CURMOD - Current Mode of Operation - 21 - 1 - read-only - - - - - GOTGINT - GOTGINT - OTGFS interrupt register - (OTGFS_GOTGINT) - 0x4 - 0x20 - 0x00000000 - - - SESENDDET - VBUS is deasserted - 2 - 1 - read-write - - - - - GAHBCFG - GAHBCFG - OTGFS AHB configuration register - (OTGFS_GAHBCFG) - 0x8 - 0x20 - read-write - 0x00000000 - - - GLBINTMSK - Global interrupt mask - 0 - 1 - - - NPTXFEMPLVL - Non-Periodic TxFIFO empty level - 7 - 1 - - - PTXFEMPLVL - Periodic TxFIFO empty - level - 8 - 1 - - - - - GUSBCFG - GUSBCFG - USB configuration register - (OTGFS_GUSBCFG) - 0xC - 0x20 - 0x00000A00 - - - TOUTCAL - FS timeout calibration - 0 - 3 - read-write - - - USBTRDTIM - USB turnaround time - 10 - 4 - read-write - - - FHSTMODE - Force host mode - 29 - 1 - read-write - - - FDEVMODE - Force device mode - 30 - 1 - read-write - - - COTXPKT - Corrupt Tx packet - 31 - 1 - read-write - - - - - GRSTCTL - GRSTCTL - OTGFS reset register - (OTGFS_GRSTCTL) - 0x10 - 0x20 - 0x20000000 - - - CSFTRST - Core soft reset - 0 - 1 - read-write - - - PIUSFTRST - PIU FS Dedicated Controller Soft Reset - 1 - 1 - read-write - - - FRMCNTRST - Host frame counter reset - 2 - 1 - read-write - - - RXFFLSH - RxFIFO flush - 4 - 1 - read-write - - - TXFFLSH - TxFIFO flush - 5 - 1 - read-write - - - TXFNUM - TxFIFO number - 6 - 5 - read-write - - - AHBIDLE - AHB master idle - 31 - 1 - read-only - - - - - GINTSTS - GINTSTS - OTGFS core interrupt register - (OTGFS_GINTSTS) - 0x14 - 0x20 - 0x04000020 - - - CURMOD - Current mode of operation - 0 - 1 - read-only - - - MODEMIS - Mode mismatch interrupt - 1 - 1 - read-write - - - OTGINT - OTG interrupt - 2 - 1 - read-only - - - SOF - Start of frame - 3 - 1 - read-write - - - RXFLVL - RxFIFO non-empty - 4 - 1 - read-only - - - NPTXFEMP - Non-periodic TxFIFO empty - 5 - 1 - read-only - - - GINNAKEFF - Global IN non-periodic NAK - effective - 6 - 1 - read-only - - - GOUTNAKEFF - Global OUT NAK effective - 7 - 1 - read-only - - - ERLYSUSP - Early suspend - 10 - 1 - read-write - - - USBSUSP - USB suspend - 11 - 1 - read-write - - - USBRST - USB reset - 12 - 1 - read-write - - - ENUMDONE - Enumeration done - 13 - 1 - read-write - - - ISOOUTDROP - Isochronous OUT packet dropped - interrupt - 14 - 1 - read-write - - - EOPF - End of periodic frame - interrupt - 15 - 1 - read-write - - - IEPTINT - IN endpoint interrupt - 18 - 1 - read-only - - - OEPTINT - OUT endpoint interrupt - 19 - 1 - read-only - - - INCOMPISOIN - Incomplete isochronous IN - transfer - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUT - Incomplete periodic transfer(Host - mode)/Incomplete isochronous OUT transfer(Device - mode) - 21 - 1 - read-write - - - PRTINT - Host port interrupt - 24 - 1 - read-only - - - HCHINT - Host channels interrupt - 25 - 1 - read-only - - - PTXFEMP - Periodic TxFIFO empty - 26 - 1 - read-only - - - CONIDSCHG - Connector ID status change - 28 - 1 - read-write - - - DISCONINT - Disconnect detected - interrupt - 29 - 1 - read-write - - - WKUPINT - Resume/remote wakeup detected - interrupt - 31 - 1 - read-write - - - - - GINTMSK - GINTMSK - OTG_FS interrupt mask register - (OTG_FS_GINTMSK) - 0x18 - 0x20 - 0x00000000 - - - MODEMISMSK - Mode mismatch interrupt - mask - 1 - 1 - read-write - - - OTGINTMSK - OTG interrupt mask - 2 - 1 - read-write - - - SOFMSK - Start of frame mask - 3 - 1 - read-write - - - RXFLVLMSK - Receive FIFO non-empty - mask - 4 - 1 - read-write - - - NPTXFEMPMSK - Non-periodic TxFIFO empty - mask - 5 - 1 - read-write - - - GINNAKEFFMSK - Global non-periodic IN NAK effective - mask - 6 - 1 - read-write - - - GOUTNAKEFFMSK - Global OUT NAK effective - mask - 7 - 1 - read-write - - - ERLYSUSPMSK - Early suspend mask - 10 - 1 - read-write - - - USBSUSPMSK - USB suspend mask - 11 - 1 - read-write - - - USBRSTMSK - USB reset mask - 12 - 1 - read-write - - - ENUMDONEMSK - Enumeration done mask - 13 - 1 - read-write - - - ISOOUTDROPMSK - Isochronous OUT packet dropped interrupt - mask - 14 - 1 - read-write - - - EOPFMSK - End of periodic frame interrupt - mask - 15 - 1 - read-write - - - IEPTINTMSK - IN endpoints interrupt - mask - 18 - 1 - read-write - - - OEPTINTMSK - OUT endpoints interrupt - mask - 19 - 1 - read-write - - - INCOMISOINMSK - Incomplete isochronous IN transfer - mask - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUTMSK - Incomplete periodic transfer mask(Host - mode)/Incomplete isochronous OUT transfer mask(Device - mode) - 21 - 1 - read-write - - - PRTINTMSK - Host port interrupt mask - 24 - 1 - read-write - - - HCHINTMSK - Host channels interrupt - mask - 25 - 1 - read-write - - - PTXFEMPMSK - Periodic TxFIFO empty mask - 26 - 1 - read-write - - - CONIDSCHGMSK - Connector ID status change - mask - 28 - 1 - read-write - - - DISCONINTMSK - Disconnect detected interrupt - mask - 29 - 1 - read-write - - - WKUPINTMSK - Resume/remote wakeup detected interrupt - mask - 31 - 1 - read-write - - - - - GRXSTSR_Device - GRXSTSR_Device - OTGFS Receive status debug read(Device - mode) - 0x1C - 0x20 - read-only - 0x00000000 - - - EPTNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - FN - Frame number - 21 - 4 - - - - - GRXSTSR_Host - GRXSTSR_Host - OTGFS Receive status debug read(Host - mode) - GRXSTSR_Device - 0x1C - 0x20 - read-only - 0x00000000 - - - CHNUM - Channel number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - - - GRXFSIZ - GRXFSIZ - OTGFS Receive FIFO size register - (OTGFS_GRXFSIZ) - 0x24 - 0x20 - read-write - 0x00000200 - - - RXFDEP - RxFIFO depth - 0 - 16 - - - - - DIEPTXF0 - DIEPTXF0 - IN Endpoint TxFIFO 0 transmit FIFO size - register (Device mode) - 0x28 - 0x20 - read-write - 0x00000200 - - - INEPT0TXSTADDR - Endpoint 0 transmit RAM start - address - 0 - 16 - - - INEPT0TXDEP - Endpoint 0 TxFIFO depth - 16 - 16 - - - - - GNPTXFSIZ - GNPTXFSIZ - OTGFS non-periodic transmit FIFO size - register (Host mode) - DIEPTXF0 - 0x28 - 0x20 - read-write - 0x00000200 - - - NPTXFSTADDR - Non-periodic Transmit RAM Start - address - 0 - 16 - - - NPTXFDEP - Non-periodic TxFIFO depth - 16 - 16 - - - - - GNPTXSTS - GNPTXSTS - OTGFS non-periodic transmit FIFO/queue - status register (OTGFS_GNPTXSTS) - 0x2C - 0x20 - read-only - 0x00080200 - - - NPTXFSPCAVAIL - Non-periodic TxFIFO space - available - 0 - 16 - - - NPTXQSPCAVAIL - Non-periodic transmit request queue - space available - 16 - 8 - - - NPTXQTOP - Top of the non-periodic transmit request - queue - 24 - 7 - - - - - GCCFG - GCCFG - OTGFS general core configuration register - (OTGFS_GCCFG) - 0x38 - 0x20 - read-write - 0x00000000 - - - PWRDOWN - Power down - 16 - 1 - - - LP_MODE - Low power mode - 17 - 1 - - - SOFOUTEN - SOF output enable - 20 - 1 - - - VBUSIG - VBUS Ignored - 21 - 1 - - - - - GUID - GUID - Product ID register - 0x3C - 0x20 - read-write - 0x00001000 - - - USERID - Product ID field - 0 - 32 - - - - - HPTXFSIZ - HPTXFSIZ - OTGFS Host periodic transmit FIFO size - register (OTGFS_HPTXFSIZ) - 0x100 - 0x20 - read-write - 0x02000600 - - - PTXFSTADDR - Host periodic TxFIFO start - address - 0 - 16 - - - PTXFSIZE - Host periodic TxFIFO depth - 16 - 16 - - - - - DIEPTXF1 - DIEPTXF1 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF1) - 0x104 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO1 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF2 - DIEPTXF2 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF2) - 0x108 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO2 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF3 - DIEPTXF3 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF3) - 0x10C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO3 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF4 - DIEPTXF4 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF4) - 0x110 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO4 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF5 - DIEPTXF5 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF5) - 0x114 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO5 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF6 - DIEPTXF6 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF6) - 0x118 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO6 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF7 - DIEPTXF7 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF7) - 0x11C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO7 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - - - USB_OTG1_HOST - USB on the go full speed - USB_OTG1 - 0x50000400 - - 0x0 - 0x400 - registers - - - - HCFG - HCFG - OTGFS host configuration register - (OTGFS_HCFG) - 0x0 - 0x20 - 0x00000000 - - - FSLSPCLKSEL - FS/LS PHY clock select - 0 - 2 - read-write - - - FSLSSUPP - FS- and LS-only support - 2 - 1 - read-only - - - - - HFIR - HFIR - OTGFS Host frame interval - register - 0x4 - 0x20 - read-write - 0x0000EA60 - - - FRINT - Frame interval - 0 - 16 - - - - - HFNUM - HFNUM - OTGFS host frame number/frame time - remaining register (OTGFS_HFNUM) - 0x8 - 0x20 - read-only - 0x00003FFF - - - FRNUM - Frame number - 0 - 16 - - - FTREM - Frame time remaining - 16 - 16 - - - - - HPTXSTS - HPTXSTS - OTGFS_Host periodic transmit FIFO/queue - status register (OTGFS_HPTXSTS) - 0x10 - 0x20 - 0x00080100 - - - PTXFSPCAVAIL - Periodic transmit data FIFO space - available - 0 - 16 - read-write - - - PTXQSPCAVAIL - Periodic transmit request queue space - available - 16 - 8 - read-only - - - PTXQTOP - Top of the periodic transmit request - queue - 24 - 8 - read-only - - - - - HAINT - HAINT - OTGFS Host all channels interrupt - register - 0x14 - 0x20 - read-only - 0x00000000 - - - HAINT - Channel interrupts - 0 - 16 - - - - - HAINTMSK - HAINTMSK - OTGFS host all channels interrupt mask - register - 0x18 - 0x20 - read-write - 0x00000000 - - - HAINTMSK - Channel interrupt mask - 0 - 16 - - - - - HPRT - HPRT - OTGFS host port control and status register - (OTGFS_HPRT) - 0x40 - 0x20 - 0x00000000 - - - PRTCONSTS - Port connect status - 0 - 1 - read-only - - - PRTCONDET - Port connect detected - 1 - 1 - read-write - - - PRTENA - Port enable - 2 - 1 - read-write - - - PRTENCHNG - Port enable/disable change - 3 - 1 - read-write - - - PRTOVRCACT - Port overcurrent active - 4 - 1 - read-only - - - PRTOVRCCHNG - Port overcurrent change - 5 - 1 - read-write - - - PRTRES - Port resume - 6 - 1 - read-write - - - PRTSUSP - Port suspend - 7 - 1 - read-write - - - PRTRST - Port reset - 8 - 1 - read-write - - - PRTLNSTS - Port line status - 10 - 2 - read-only - - - PRTPWR - Port power - 12 - 1 - read-write - - - PRTTSTCTL - Port test control - 13 - 4 - read-write - - - PRTSPD - Port speed - 17 - 2 - read-only - - - - - HCCHAR0 - HCCHAR0 - OTGFS host channel-0 characteristics - register (OTGFS_HCCHAR0) - 0x100 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR1 - HCCHAR1 - OTGFS host channel-1 characteristics - register (OTGFS_HCCHAR1) - 0x120 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR2 - HCCHAR2 - OTGFS host channel-2 characteristics - register (OTGFS_HCCHAR2) - 0x140 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR3 - HCCHAR3 - OTGFS host channel-3 characteristics - register (OTGFS_HCCHAR3) - 0x160 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR4 - HCCHAR4 - OTGFS host channel-4 characteristics - register (OTGFS_HCCHAR4) - 0x180 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR5 - HCCHAR5 - OTGFS host channel-5 characteristics - register (OTGFS_HCCHAR5) - 0x1A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR6 - HCCHAR6 - OTGFS host channel-6 characteristics - register (OTGFS_HCCHAR6) - 0x1C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR7 - HCCHAR7 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR7) - 0x1E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR8 - HCCHAR8 - OTGFS host channel-8 characteristics - register (OTGFS_HCCHAR8) - 0x200 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR9 - HCCHAR9 - OTGFS host channel-9 characteristics - register (OTGFS_HCCHAR9) - 0x220 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR10 - HCCHAR10 - OTGFS host channel-10 characteristics - register (OTGFS_HCCHAR10) - 0x240 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR11 - HCCHAR11 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR11) - 0x260 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR12 - HCCHAR12 - OTGFS host channel-12 characteristics - register (OTGFS_HCCHAR12) - 0x280 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR13 - HCCHAR13 - OTGFS host channel-13 characteristics - register (OTGFS_HCCHAR13) - 0x2A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR14 - HCCHAR14 - OTGFS host channel-14 characteristics - register (OTGFS_HCCHAR14) - 0x2C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR15 - HCCHAR15 - OTGFS host channel-15 characteristics - register (OTGFS_HCCHAR15) - 0x2E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCINT0 - HCINT0 - OTGFS host channel-0 interrupt register - (OTGFS_HCINT0) - 0x108 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT1 - HCINT1 - OTG_FS host channel-1 interrupt register - (OTG_FS_HCINT1) - 0x128 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT2 - HCINT2 - OTGFS host channel-2 interrupt register - (OTGFS_HCINT2) - 0x148 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT3 - HCINT3 - OTGFS host channel-3 interrupt register - (OTGFS_HCINT3) - 0x168 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT4 - HCINT4 - OTGFS host channel-4 interrupt register - (OTGFS_HCINT4) - 0x188 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT5 - HCINT5 - OTGFS host channel-5 interrupt register - (OTGFS_HCINT5) - 0x1A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT6 - HCINT6 - OTGFS host channel-6 interrupt register - (OTGFS_HCINT6) - 0x1C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT7 - HCINT7 - OTGFS host channel-7 interrupt register - (OTGFS_HCINT7) - 0x1E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT8 - HCINT8 - OTGFS host channel-8 interrupt register - (OTGFS_HCINT8) - 0x208 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT9 - HCINT9 - OTGFS host channel-9 interrupt register - (OTGFS_HCINT9) - 0x228 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT10 - HCINT10 - OTGFS host channel-10 interrupt register - (OTGFS_HCINT10) - 0x248 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT11 - HCINT11 - OTGFS host channel-11 interrupt register - (OTGFS_HCINT11) - 0x268 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT12 - HCINT12 - OTGFS host channel-12 interrupt register - (OTGFS_HCINT12) - 0x288 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT13 - HCINT13 - OTGFS host channel-13 interrupt register - (OTGFS_HCINT13) - 0x2A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT14 - HCINT14 - OTGFS host channel-14 interrupt register - (OTGFS_HCINT14) - 0x2C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT15 - HCINT15 - OTGFS host channel-15 interrupt register - (OTGFS_HCINT15) - 0x2E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINTMSK0 - HCINTMSK0 - OTGFS host channel-0 mask register - (OTGFS_HCINTMSK0) - 0x10C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK1 - HCINTMSK1 - OTGFS host channel-1 mask register - (OTGFS_HCINTMSK1) - 0x12C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK2 - HCINTMSK2 - OTGFS host channel-2 mask register - (OTGFS_HCINTMSK2) - 0x14C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK3 - HCINTMSK3 - OTGFS host channel-3 mask register - (OTGFS_HCINTMSK3) - 0x16C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK4 - HCINTMSK4 - OTGFS host channel-4 mask register - (OTGFS_HCINTMSK4) - 0x18C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK5 - HCINTMSK5 - OTGFS host channel-5 mask register - (OTGFS_HCINTMSK5) - 0x1AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK6 - HCINTMSK6 - OTGFS host channel-6 mask register - (OTGFS_HCINTMSK6) - 0x1CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK7 - HCINTMSK7 - OTGFS host channel-7 mask register - (OTGFS_HCINTMSK7) - 0x1EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK8 - HCINTMSK8 - OTGFS host channel-8 mask register - (OTGFS_HCINTMSK8) - 0x20C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK9 - HCINTMSK9 - OTGFS host channel-9 mask register - (OTGFS_HCINTMSK9) - 0x22C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK10 - HCINTMSK10 - OTGFS host channel-10 mask register - (OTGFS_HCINTMSK10) - 0x24C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK11 - HCINTMSK11 - OTGFS host channel-11 mask register - (OTGFS_HCINTMSK11) - 0x26C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK12 - HCINTMSK12 - OTGFS host channel-12 mask register - (OTGFS_HCINTMSK12) - 0x28C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK13 - HCINTMSK13 - OTGFS host channel-13 mask register - (OTGFS_HCINTMSK13) - 0x2AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK14 - HCINTMSK14 - OTGFS host channel-14 mask register - (OTGFS_HCINTMSK14) - 0x2CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK15 - HCINTMSK15 - OTGFS host channel-15 mask register - (OTGFS_HCINTMSK15) - 0x2EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCTSIZ0 - HCTSIZ0 - OTGFS host channel-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ1 - HCTSIZ1 - OTGFS host channel-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ2 - HCTSIZ2 - OTGFS host channel-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ3 - HCTSIZ3 - OTGFS host channel-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ4 - HCTSIZ4 - OTGFS host channel-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ5 - HCTSIZ5 - OTGFS host channel-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ6 - HCTSIZ6 - OTGFS host channel-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ7 - HCTSIZ7 - OTGFS host channel-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ8 - HCTSIZ8 - OTGFS host channel-8 transfer size - register - 0x210 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ9 - HCTSIZ9 - OTGFS host channel-9 transfer size - register - 0x230 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ10 - HCTSIZ10 - OTGFS host channel-10 transfer size - register - 0x250 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ11 - HCTSIZ11 - OTGFS host channel-11 transfer size - register - 0x270 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ12 - HCTSIZ12 - OTGFS host channel-12 transfer size - register - 0x290 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ13 - HCTSIZ13 - OTGFS host channel-13 transfer size - register - 0x2B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ14 - HCTSIZ14 - OTGFS host channel-14 transfer size - register - 0x2D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ15 - HCTSIZ15 - OTGFS host channel-15 transfer size - register - 0x2F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - - - USB_OTG1_DEVICE - USB on the go full speed - USB_OTG1 - 0x50000800 - - 0x0 - 0x400 - registers - - - - DCFG - DCFG - OTGFS device configuration register - (OTGFS_DCFG) - 0x0 - 0x20 - read-write - 0x02200000 - - - DEVSPD - Device speed - 0 - 2 - - - NZSTSOUTHSHK - Non-zero-length status OUT - handshake - 2 - 1 - - - DEVADDR - Device address - 4 - 7 - - - PERFRINT - Periodic frame interval - 11 - 2 - - - - - DCTL - DCTL - OTGFS device control register - (OTGFS_DCTL) - 0x4 - 0x20 - 0x00000000 - - - RWKUPSIG - Remote wakeup signaling - 0 - 1 - read-write - - - SFTDISCON - Soft disconnect - 1 - 1 - read-write - - - GNPINNAKSTS - Global IN NAK status - 2 - 1 - read-only - - - GOUTNAKSTS - Global OUT NAK status - 3 - 1 - read-only - - - TSTCTL - Test control - 4 - 3 - read-write - - - SGNPINNAK - Set global IN NAK - 7 - 1 - read-write - - - CGNPINNAK - Clear global IN NAK - 8 - 1 - read-write - - - SGOUTNAK - Set global OUT NAK - 9 - 1 - read-write - - - CGOUTNAK - Clear global OUT NAK - 10 - 1 - read-write - - - PWROPRGDNE - Power-on programming done - 11 - 1 - read-write - - - - - DSTS - DSTS - OTGFS device status register - (OTGFS_DSTS) - 0x8 - 0x20 - read-only - 0x00000010 - - - SUSPSTS - Suspend status - 0 - 1 - - - ENUMSPD - Enumerated speed - 1 - 2 - - - ETICERR - Erratic error - 3 - 1 - - - SOFFN - Frame number of the received - SOF - 8 - 14 - - - - - DIEPMSK - DIEPMSK - OTGFS device IN endpoint common interrupt - mask register (OTGFS_DIEPMSK) - 0x10 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - TIMEOUTMSK - Timeout condition mask (Non-isochronous - endpoints) - 3 - 1 - - - INTKNTXFEMPMSK - IN token received when TxFIFO empty - mask - 4 - 1 - - - INTKNEPTMISMSK - IN token received with EP mismatch - mask - 5 - 1 - - - INEPTNAKMSK - IN endpoint NAK effective - mask - 6 - 1 - - - TXFIFOUDRMSK - FIFO underrun - mask - 8 - 1 - - - BNAINMSK - BNA interrupt - mask - 9 - 1 - - - - - DOEPMSK - DOEPMSK - OTGFS device OUT endpoint common interrupt - mask register (OTGFS_DOEPMSK) - 0x14 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - SETUPMSK - SETUP phase done mask - 3 - 1 - - - OUTTEPDMSK - OUT token received when endpoint - disabled mask - 4 - 1 - - - B2BSETUPMSK - Back-to-back SETUP packets - received mask - 6 - 1 - - - OUTPERRMSK - OUT packet error - mask - 8 - 1 - - - BNAOUTMSK - BNA interrupt - mask - 9 - 1 - - - - - DAINT - DAINT - OTGFS device all endpoints interrupt - register (OTGFS_DAINT) - 0x18 - 0x20 - read-only - 0x00000000 - - - INEPTINT - IN endpoint interrupt bits - 0 - 16 - - - OUTEPTINT - OUT endpoint interrupt - bits - 16 - 16 - - - - - DAINTMSK - DAINTMSK - OTGFS all endpoints interrupt mask register - (OTGFS_DAINTMSK) - 0x1C - 0x20 - read-write - 0x00000000 - - - INEPTMSK - IN EP interrupt mask bits - 0 - 16 - - - OUTEPTMSK - OUT endpoint interrupt - bits - 16 - 16 - - - - - DIEPEMPMSK - DIEPEMPMSK - OTGFS device IN endpoint FIFO empty - interrupt mask register - 0x34 - 0x20 - read-write - 0x00000000 - - - INEPTXFEMSK - IN EP Tx FIFO empty interrupt mask - bits - 0 - 16 - - - - - DIEPCTL0 - DIEPCTL0 - OTGFS device control IN endpoint 0 control - register (OTGFS_DIEPCTL0) - 0x100 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 2 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-only - - - EPTENA - Endpoint enable - 31 - 1 - read-only - - - - - DIEPCTL1 - DIEPCTL1 - OTGFS device IN endpoint-1 control - register - 0x120 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL2 - DIEPCTL2 - OTGFS device IN endpoint-2 control - register - 0x140 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL3 - DIEPCTL3 - OTGFS device IN endpoint-3 control - register - 0x160 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL4 - DIEPCTL4 - OTGFS device IN endpoint-4 control - register - 0x180 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL5 - DIEPCTL5 - OTGFS device IN endpoint-5 control - register - 0x1A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL6 - DIEPCTL6 - OTGFS device IN endpoint-6 control - register - 0x1C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL7 - DIEPCTL7 - OTGFS device IN endpoint-7 control - register - 0x1E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL0 - DOEPCTL0 - OTGFS device OUT endpoint-0 control - register - 0x300 - 0x20 - 0x00008000 - - - MPS - Maximum packet size - 0 - 2 - read-only - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL1 - DOEPCTL1 - OTGFS device OUT endpoint-1 control - register - 0x320 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL2 - DOEPCTL2 - OTGFS device OUT endpoint-2 control - register - 0x340 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL3 - DOEPCTL3 - OTGFS device OUT endpoint-3 control - register - 0x360 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL4 - DOEPCTL4 - OTGFS device OUT endpoint-4 control - register - 0x380 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL5 - DOEPCTL5 - OTGFS device OUT endpoint-5 control - register - 0x3A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL6 - DOEPCTL6 - OTGFS device OUT endpoint-6 control - register - 0x3C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL7 - DOEPCTL7 - OTGFS device OUT endpoint-7 control - register - 0x3E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPINT0 - DIEPINT0 - OTGFS device IN endpoint-0 interrupt - register - 0x108 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT1 - DIEPINT1 - OTGFS device IN endpoint-1 interrupt - register - 0x128 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT2 - DIEPINT2 - OTGFS device IN endpoint-2 interrupt - register - 0x148 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT3 - DIEPINT3 - OTGFS device IN endpoint-3 interrupt - register - 0x168 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT4 - DIEPINT4 - OTGFS device IN endpoint-4 interrupt - register - 0x188 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT5 - DIEPINT5 - OTGFS device IN endpoint-5 interrupt - register - 0x1A8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT6 - DIEPINT6 - OTGFS device IN endpoint-6 interrupt - register - 0x1C8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT7 - DIEPINT7 - OTGFS device IN endpoint-7 interrupt - register - 0x1E8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DOEPINT0 - DOEPINT0 - OTGFS device OUT endpoint-0 interrupt - register - 0x308 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT1 - DOEPINT1 - OTGFS device OUT endpoint-1 interrupt - register - 0x328 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT2 - DOEPINT2 - OTGFS device OUT endpoint-2 interrupt - register - 0x348 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT3 - DOEPINT3 - OTGFS device OUT endpoint-3 interrupt - register - 0x368 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT4 - DOEPINT4 - OTGFS device OUT endpoint-4 interrupt - register - 0x388 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT5 - DOEPINT5 - OTGFS device OUT endpoint-5 interrupt - register - 0x3A8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT6 - DOEPINT6 - OTGFS device OUT endpoint-6 interrupt - register - 0x3C8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT7 - DOEPINT7 - OTGFS device OUT endpoint-7 interrupt - register - 0x3E8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DIEPTSIZ0 - DIEPTSIZ0 - OTGFS device IN endpoint-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 2 - - - - - DOEPTSIZ0 - DOEPTSIZ0 - OTGFS device OUT endpoint-0 transfer size - register - 0x310 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 1 - - - SETUPCNT - SETUP packet count - 29 - 2 - - - - - DIEPTSIZ1 - DIEPTSIZ1 - OTGFS device IN endpoint-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ2 - DIEPTSIZ2 - OTGFS device IN endpoint-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ3 - DIEPTSIZ3 - OTG device IN endpoint-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ4 - DIEPTSIZ4 - OTG device IN endpoint-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ5 - DIEPTSIZ5 - OTG device IN endpoint-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ6 - DIEPTSIZ6 - OTG device IN endpoint-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ7 - DIEPTSIZ7 - OTG device IN endpoint-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DTXFSTS0 - DTXFSTS0 - OTGFS device IN endpoint-0 transmit FIFO - status register - 0x118 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS1 - DTXFSTS1 - OTGFS device IN endpoint-1 transmit FIFO - status register - 0x138 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS2 - DTXFSTS2 - OTGFS device IN endpoint-2 transmit FIFO - status register - 0x158 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS3 - DTXFSTS3 - OTGFS device IN endpoint-3 transmit FIFO - status register - 0x178 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS4 - DTXFSTS4 - OTGFS device IN endpoint-4 transmit FIFO - status register - 0x198 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS5 - DTXFSTS5 - OTGFS device IN endpoint-5 transmit FIFO - status register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS6 - DTXFSTS6 - OTGFS device IN endpoint-6 transmit FIFO - status register - 0x1D8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS7 - DTXFSTS7 - OTGFS device IN endpoint-7 transmit FIFO - status register - 0x1F8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DOEPTSIZ1 - DOEPTSIZ1 - OTGFS device OUT endpoint-1 transfer size - register - 0x330 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ2 - DOEPTSIZ2 - OTGFS device OUT endpoint-2 transfer size - register - 0x350 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ3 - DOEPTSIZ3 - OTGFS device OUT endpoint-3 transfer size - register - 0x370 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ4 - DOEPTSIZ4 - OTGFS device OUT endpoint-4 transfer size - register - 0x390 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ5 - DOEPTSIZ5 - OTGFS device OUT endpoint-5 transfer size - register - 0x3B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ6 - DOEPTSIZ6 - OTGFS device OUT endpoint-6 transfer size - register - 0x3D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ7 - DOEPTSIZ7 - OTGFS device OUT endpoint-7 transfer size - register - 0x3F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - - - USB_OTG1_PWRCLK - USB on the go full speed - USB_OTG1 - 0x50000E00 - - 0x0 - 0x400 - registers - - - - PCGCCTL - PCGCCTL - OTGFS power and clock gating control - register (OTGFS_PCGCCTL) - 0x0 - 0x20 - 0x00000000 - - - STOPPCLK - Stop PHY clock - 0 - 1 - read-write - - - SUSPENDM - PHY Suspended - 4 - 1 - read-only - - - - - - - diff --git a/hw/bsp/at32f425/family.c b/hw/bsp/at32f425/family.c index e0b66730a..7c2db9258 100644 --- a/hw/bsp/at32f425/family.c +++ b/hw/bsp/at32f425/family.c @@ -35,16 +35,16 @@ void led_and_button_init(void); //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void OTGFS1_IRQHandler(void) +void OTGFS1_IRQHandler(void) { tusb_int_handler(0, true); } -void OTGFS1_WKUP_IRQHandler(void) +void OTGFS1_WKUP_IRQHandler(void) { tusb_int_handler(0, true); } -void board_init(void) +void board_init(void) { /* config nvic priority group */ nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); @@ -85,7 +85,7 @@ void board_init(void) /* config led and key */ led_and_button_init(); - + /* config usart printf */ uart_print_init(115200); printf("usart printf config success!\r\n"); @@ -120,7 +120,7 @@ void usb_clock48m_select(usb_clk48_s clk_s) { /* usb divider reset */ crm_usb_div_reset(); - + switch(system_core_clock) { /* 48MHz */ @@ -144,7 +144,7 @@ void usb_clock48m_select(usb_clk48_s clk_s) } } -void led_and_button_init(void) +void led_and_button_init(void) { /* LED */ gpio_init_type gpio_led_init_struct; @@ -201,7 +201,7 @@ void uart_print_init(uint32_t baudrate) } // Get characters from UART. Return number of read bytes -int board_uart_read(uint8_t *buf, int len) +int board_uart_read(uint8_t *buf, int len) { (void) buf; (void) len; @@ -214,7 +214,7 @@ int board_uart_write(void const *buf, int len) #if CFG_TUSB_OS == OPT_OS_NONE int txsize = len; u16 timeout = 0xffff; - while (txsize--) + while (txsize--) { while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) { @@ -235,17 +235,17 @@ int board_uart_write(void const *buf, int len) #endif } -void board_led_write(bool state) +void board_led_write(bool state) { gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); } -uint32_t board_button_read(void) +uint32_t board_button_read(void) { return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); } -size_t board_get_unique_id(uint8_t id[], size_t max_len) +size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); @@ -263,12 +263,12 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; - void SysTick_Handler(void) + void SysTick_Handler(void) { system_ticks++; } - uint32_t board_millis(void) + uint32_t board_millis(void) { return system_ticks; } @@ -282,7 +282,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) } #endif -void HardFault_Handler(void) +void HardFault_Handler(void) { __asm("BKPT #0\n"); } diff --git a/hw/bsp/at32f425/family.mk b/hw/bsp/at32f425/family.mk index d1bcdfda3..07b383ce9 100644 --- a/hw/bsp/at32f425/family.mk +++ b/hw/bsp/at32f425/family.mk @@ -1,6 +1,5 @@ # Submodules AT32F425_SDK = hw/mcu/artery/at32f425 -DEPS_SUBMODULES += $(AT32F425_SDK) # AT32 SDK path AT32F425_SDK_SRC = $(AT32F425_SDK)/libraries diff --git a/hw/bsp/at32f425/startup_at32f425.s b/hw/bsp/at32f425/startup_at32f425.s index 38127c759..d41fd3f42 100644 --- a/hw/bsp/at32f425/startup_at32f425.s +++ b/hw/bsp/at32f425/startup_at32f425.s @@ -78,7 +78,7 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array diff --git a/hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h index a42e4d414..4e24ead70 100644 --- a/hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h @@ -109,7 +109,7 @@ #define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 #define INCLUDE_uxTaskGetStackHighWaterMark 0 #define INCLUDE_xTaskGetIdleTaskHandle 0 #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 diff --git a/hw/bsp/at32f435_437/at32f435_437_clock.h b/hw/bsp/at32f435_437/at32f435_437_clock.h index 221f67b4a..6d0273f30 100644 --- a/hw/bsp/at32f435_437/at32f435_437_clock.h +++ b/hw/bsp/at32f435_437/at32f435_437_clock.h @@ -41,4 +41,3 @@ void system_clock_config(void); #endif #endif - diff --git a/hw/bsp/at32f435_437/at32f435_437_int.c b/hw/bsp/at32f435_437/at32f435_437_int.c index b2fd3db29..119a0c960 100644 --- a/hw/bsp/at32f435_437/at32f435_437_int.c +++ b/hw/bsp/at32f435_437/at32f435_437_int.c @@ -117,4 +117,3 @@ void DebugMon_Handler(void) /** * @} */ - diff --git a/hw/bsp/at32f435_437/at32f435_437_int.h b/hw/bsp/at32f435_437/at32f435_437_int.h index afd2ad14e..76bfaaae4 100644 --- a/hw/bsp/at32f435_437/at32f435_437_int.h +++ b/hw/bsp/at32f435_437/at32f435_437_int.h @@ -53,4 +53,3 @@ void SysTick_Handler(void); #endif #endif - diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xM_FLASH.ld b/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xM_FLASH.ld index 8b4db93ab..b9d5ba223 100644 --- a/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xM_FLASH.ld +++ b/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xM_FLASH.ld @@ -104,7 +104,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -119,7 +119,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd b/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd deleted file mode 100644 index 4f34af9d3..000000000 --- a/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd +++ /dev/null @@ -1,58291 +0,0 @@ - - - - - - - - Keil - ArteryTek - AT32F437xx_v2 - AT32F437 - 1.0 - ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 288MHz, etc. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - CM4 - r0p1 - little - false - true - 4 - false - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - - XMC - Flexible static memory controller - XMC - 0xA0000000 - - 0x0 - 0x1000 - registers - - - XMC - XMC global interrupt - 48 - - - - BK1CTRL1 - BK1CTRL1 - SRAM/NOR-Flash chip-select control register - 1 - 0x0 - 0x20 - read-write - 0x000030DB - - - MWMC - Memory write mode control - 19 - 1 - - - CRPGS - CRAM page size - 16 - 3 - - - NWASEN - NWAIT in asynchronous transfer enable - 15 - 1 - - - RWTD - Read-write timing different - 14 - 1 - - - NWSEN - NWAIT in synchronous transfer enable - 13 - 1 - - - WEN - Write enable - 12 - 1 - - - NWTCFG - Wait timing configuration - 11 - 1 - - - WRAPEN - Wrapped enable - 10 - 1 - - - NWPOL - NWAIT polarity - 9 - 1 - - - SYNCBEN - Synchronous burst enable - 8 - 1 - - - NOREN - Nor flash access enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 2 - 2 - - - ADMUXEN - Address and data multiplexing enable - 1 - 1 - - - EN - Memory bank enable - 0 - 1 - - - - - BK1TMG1 - BK1TMG1 - SRAM/NOR-Flash chip-select timing register - 1 - 0x4 - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - DTLAT - Data latency - 24 - 4 - - - CLKPSC - Clock prescale - 20 - 4 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1CTRL2 - BK1CTRL2 - SRAM/NOR-Flash chip-select control register - 2 - 0x8 - 0x20 - read-write - 0x000030D2 - - - MWMC - Memory write mode control - 19 - 1 - - - CRPGS - CRAM page size - 16 - 3 - - - NWASEN - NWAIT in asynchronous transfer enable - 15 - 1 - - - RWTD - Read-write timing different - 14 - 1 - - - NWSEN - NWAIT in synchronous transfer enable - 13 - 1 - - - WEN - Write enable - 12 - 1 - - - NWTCFG - Wait timing configuration - 11 - 1 - - - WRAPEN - Wrapped enable - 10 - 1 - - - NWPOL - NWAIT polarity - 9 - 1 - - - SYNCBEN - Synchronous burst enable - 8 - 1 - - - NOREN - Nor flash access enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 2 - 2 - - - ADMUXEN - Address and data multiplexing enable - 1 - 1 - - - EN - Memory bank enable - 0 - 1 - - - - - BK1TMG2 - BK1TMG2 - SRAM/NOR-Flash chip-select timing register - 2 - 0xC - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - DTLAT - Data latency - 24 - 4 - - - CLKPSC - Clock prescale - 20 - 4 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1CTRL3 - BK1CTRL3 - SRAM/NOR-Flash chip-select control register - 3 - 0x10 - 0x20 - read-write - 0x000030D2 - - - MWMC - Memory write mode control - 19 - 1 - - - CRPGS - CRAM page size - 16 - 3 - - - NWASEN - NWAIT in asynchronous transfer enable - 15 - 1 - - - RWTD - Read-write timing different - 14 - 1 - - - NWSEN - NWAIT in synchronous transfer enable - 13 - 1 - - - WEN - Write enable - 12 - 1 - - - NWTCFG - Wait timing configuration - 11 - 1 - - - WRAPEN - Wrapped enable - 10 - 1 - - - NWPOL - NWAIT polarity - 9 - 1 - - - SYNCBEN - Synchronous burst enable - 8 - 1 - - - NOREN - Nor flash access enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 2 - 2 - - - ADMUXEN - Address and data multiplexing enable - 1 - 1 - - - EN - Memory bank enable - 0 - 1 - - - - - BK1TMG3 - BK1TMG3 - SRAM/NOR-Flash chip-select timing register - 3 - 0x14 - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - DTLAT - Data latency - 24 - 4 - - - CLKPSC - Clock prescale - 20 - 4 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1CTRL4 - BK1CTRL4 - SRAM/NOR-Flash chip-select control register - 4 - 0x18 - 0x20 - read-write - 0x000030D2 - - - MWMC - Memory write mode control - 19 - 1 - - - CRPGS - CRAM page size - 16 - 3 - - - NWASEN - NWAIT in asynchronous transfer enable - 15 - 1 - - - RWTD - Read-write timing different - 14 - 1 - - - NWSEN - NWAIT in synchronous transfer enable - 13 - 1 - - - WEN - Write enable - 12 - 1 - - - NWTCFG - Wait timing configuration - 11 - 1 - - - WRAPEN - Wrapped enable - 10 - 1 - - - NWPOL - NWAIT polarity - 9 - 1 - - - SYNCBEN - Synchronous burst enable - 8 - 1 - - - NOREN - Nor flash access enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 2 - 2 - - - ADMUXEN - Address and data multiplexing enable - 1 - 1 - - - EN - Memory bank enable - 0 - 1 - - - - - BK1TMG4 - BK1TMG4 - SRAM/NOR-Flash chip-select timing register - 4 - 0x1C - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - DTLAT - Data latency - 24 - 4 - - - CLKPSC - Clock prescale - 20 - 4 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK2CTRL - BK2CTRL - PC Card/NAND Flash control register - 2 - 0x60 - 0x20 - read-write - 0x00000018 - - - ECCPGS - ECC page size - 17 - 3 - - - TAR - ALE to RE delay - 13 - 4 - - - TCR - CLE to RE delay - 9 - 4 - - - ECCEN - ECC enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 3 - 1 - - - EN - Memory bank enable - 2 - 1 - - - NWEN - Wait feature enable - 1 - 1 - - - - - BK2IS - BK2IS - FIFO status and interrupt register - 2 - 0x64 - 0x20 - 0x00000040 - - - FIFOE - FIFO empty - 6 - 1 - read-only - - - FEIEN - Falling edge interrupt enable - 5 - 1 - read-write - - - HLIEN - High-level interrupt enable - 4 - 1 - read-write - - - REIEN - Rising edge interrupt enable - 3 - 1 - read-write - - - FES - Falling edge status - 2 - 1 - read-write - - - HLS - High-level status - 1 - 1 - read-write - - - RES - Rising edge capture status - 0 - 1 - read-write - - - - - BK2TMGRG - BK2TMGRG - Regular memory space timing register - 2 - 0x68 - 0x20 - read-write - 0xFCFCFCFC - - - RGDHIZT - Regular memory databus High resistance time - 24 - 8 - - - RGHT - Regular memory hold time - 16 - 8 - - - RGWT - Regular memory wait time - 8 - 8 - - - RGST - Regular memory setup time - 0 - 8 - - - - - BK2TMGSP - BK2TMGSP - special memory space timing register - 2 - 0x6C - 0x20 - read-write - 0xFCFCFCFC - - - SPDHIZT - special memory databus High resistance time - 24 - 8 - - - SPHT - special memory hold time - 16 - 8 - - - SPWT - special memory wait time - 8 - 8 - - - SPST - special memory setup time - 0 - 8 - - - - - BK2ECC - BK2ECC - ECC result register 2 - 0x74 - 0x20 - read-write - 0x00000000 - - - ECC - ECC result - 0 - 32 - - - - - BK3CTRL - BK3CTRL - PC Card/NAND Flash control register - 3 - 0x80 - 0x20 - read-write - 0x00000018 - - - ECCPGS - ECC page size - 17 - 3 - - - TAR - ALE to RE delay - 13 - 4 - - - TCR - CLE to RE delay - 9 - 4 - - - ECCEN - ECC enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 3 - 1 - - - EN - Memory bank enable - 2 - 1 - - - NWEN - Wait feature enable - 1 - 1 - - - - - BK3IS - BK3IS - FIFO status and interrupt register - 3 - 0x84 - 0x20 - 0x00000040 - - - FIFOE - FIFO empty - 6 - 1 - read-only - - - FEIEN - Falling edge interrupt enable - 5 - 1 - read-write - - - HLIEN - High-level interrupt enable - 4 - 1 - read-write - - - REIEN - Rising edge interrupt enable - 3 - 1 - read-write - - - FES - Falling edge status - 2 - 1 - read-write - - - HLS - High-level status - 1 - 1 - read-write - - - RES - Rising edge capture status - 0 - 1 - read-write - - - - - BK3TMGRG - BK3TMGRG - Regular memory space timing register - 3 - 0x88 - 0x20 - read-write - 0xFCFCFCFC - - - RGDHIZT - Regular memory databus High resistance time - 24 - 8 - - - RGHT - Regular memory hold time - 16 - 8 - - - RGWT - Regular memory wait time - 8 - 8 - - - RGST - Regular memory setup time - 0 - 8 - - - - - BK3TMGSP - BK3TMGSP - special memory space timing register - 3 - 0x8C - 0x20 - read-write - 0xFCFCFCFC - - - SPDHIZT - special memory databus High resistance time - 24 - 8 - - - SPHT - special memory hold time - 16 - 8 - - - SPWT - special memory wait time - 8 - 8 - - - SPST - special memory setup time - 0 - 8 - - - - - BK3ECC - BK3ECC - ECC result register 3 - 0x94 - 0x20 - read-write - 0x00000000 - - - ECC - ECC result - 0 - 32 - - - - - BK4CTRL - BK4CTRL - PC Card/NAND Flash control register - 4 - 0xA0 - 0x20 - read-write - 0x00000018 - - - EN - Memory bank enable - 2 - 1 - - - NWEN - Wait feature enable - 1 - 1 - - - - - BK4IS - BK4IS - FIFO status and interrupt register - 4 - 0xA4 - 0x20 - 0x00000040 - - - FIFOE - FIFO empty - 6 - 1 - read-only - - - FEIEN - Falling edge interrupt enable - 5 - 1 - read-write - - - HLIEN - High-level interrupt enable - 4 - 1 - read-write - - - REIEN - Rising edge interrupt enable - 3 - 1 - read-write - - - FES - Falling edge status - 2 - 1 - read-write - - - HLS - High-level status - 1 - 1 - read-write - - - RES - Rising edge capture status - 0 - 1 - read-write - - - - - BK4TMGCM - BK4TMGCM - Regular memory space timing register - 4 - 0xA8 - 0x20 - read-write - 0xFCFCFCFC - - - CMDHIZT - Regular memory databus High resistance time - 24 - 8 - - - CMHT - Regular memory hold time - 16 - 8 - - - CMWT - Regular memory wait time - 8 - 8 - - - CMST - Regular memory setup time - 0 - 8 - - - - - BK4TMGAT - BK4TMGAT - special memory space timing register - 4 - 0xAC - 0x20 - read-write - 0xFCFCFCFC - - - ATDHIZT - special memory databus High resistance time - 24 - 8 - - - ATHT - special memory hold time - 16 - 8 - - - ATWT - special memory wait time - 8 - 8 - - - ATST - special memory setup time - 0 - 8 - - - - - BK4TMGIO - BK4TMGIO - I/O space timing register 4 - 0xB0 - 0x20 - read-write - 0xFCFCFCFC - - - IODHIZT - WRSTP - 24 - 8 - - - IOHT - HLD - 16 - 8 - - - IOWT - OP - 8 - 8 - - - IOST - STP - 0 - 8 - - - - - BK1TMGWR1 - BK1TMGWR1 - SRAM/NOR-Flash write timing registers - 1 - 0x104 - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1TMGWR2 - BK1TMGWR2 - SRAM/NOR-Flash write timing registers - 2 - 0x10C - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1TMGWR3 - BK1TMGWR3 - SRAM/NOR-Flash write timing registers - 3 - 0x114 - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1TMGWR4 - BK1TMGWR4 - SRAM/NOR-Flash write timing registers - 4 - 0x11C - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - CTRL1 - CTRL1 - SDRAM Control Register 1 - 0x140 - 0x20 - read-write - 0x000002D0 - - - CA - Number of column address - bits - 0 - 2 - - - RA - Number of row address bits - 2 - 2 - - - DB - Memory data bus width - 4 - 2 - - - INBK - Number of internal banks - 6 - 1 - - - CAS - CAS latency - 7 - 2 - - - WRP - Write protection - 9 - 1 - - - CLKDIV - Clock division configuration - 10 - 2 - - - BSTR - Burst read - 12 - 1 - - - RD - Read delay - 13 - 2 - - - - - CTRL2 - CTRL2 - SDRAM Control Register 2 - 0x144 - 0x20 - read-write - 0x000002D0 - - - CA - Number of column address - bits - 0 - 2 - - - RA - Number of row address bits - 2 - 2 - - - DB - Memory data bus width - 4 - 2 - - - INBK - Number of internal banks - 6 - 1 - - - CAS - CAS latency - 7 - 2 - - - WRP - Write protection - 9 - 1 - - - CLKDIV - Clock division configuration - 10 - 2 - - - BSTR - Burst read - 12 - 1 - - - RD - Read pipe - 13 - 2 - - - - - TM1 - TM1 - SDRAM Timing register 1 - 0x148 - 0x20 - read-write - 0x0FFFFFFF - - - TMRD - Mode register program to active delay - 0 - 4 - - - TXSR - Exit Self-refresh to active delay - 4 - 4 - - - TRAS - Self refresh time - 8 - 4 - - - TRC - Refresh to active delay - 12 - 4 - - - TWR - Write Recovery delay - 16 - 4 - - - TRP - Precharge to active delay - 20 - 4 - - - TRCD - Row active to Read/Write delay - 24 - 4 - - - - - TM2 - TM2 - SDRAM Timing register 2 - 0x14C - 0x20 - read-write - 0x0FFFFFFF - - - TMRD - Mode register program to active delay - 0 - 4 - - - TXSR - Exit Self-refresh to active delay - 4 - 4 - - - TRAS - Self refresh time - 8 - 4 - - - TRC - Refresh to active delay - 12 - 4 - - - TWR - Write Recovery delay - 16 - 4 - - - TRP - Precharge to active delay - 20 - 4 - - - TRCD - Row active to Read/Write delay - 24 - 4 - - - - - CMD - CMD - SDRAM Command Mode register - 0x150 - 0x20 - 0x00000000 - - - CMD - SDRAM Command - 0 - 3 - write-only - - - BK2 - SDRAM Bank 2 - 3 - 1 - write-only - - - BK1 - SDRAM Bank 1 - 4 - 1 - write-only - - - ART - Auto-refresh times - 5 - 4 - read-write - - - MRD - Mode register data - 9 - 13 - read-write - - - - - RCNT - RCNT - SDRAM Refresh Timer register - 0x154 - 0x20 - 0x00000000 - - - ERRC - error flag clear - 0 - 1 - write-only - - - RC - Refresh Count - 1 - 13 - read-write - - - ERIEN - error Interrupt Enable - 14 - 1 - read-write - - - - - STS - STS - SDRAM Status register - 0x158 - 0x20 - read-only - 0x00000000 - - - ERR - error flag - 0 - 1 - - - BK1STS - Bank 1 Status - 1 - 2 - - - BK2STS - Bank 2 Status - 3 - 2 - - - BUSY - Busy status - 5 - 1 - - - - - EXT1 - EXT1 - externl timeing register 1 - 0x220 - 0x20 - read-write - 0x00000808 - - - BUSLATW2W - Bus turnaround phase for consecutive write duration - 0 - 8 - - - BUSLATR2R - Bus turnaround phase for consecutive read duration - 8 - 8 - - - - - EXT2 - EXT2 - externl timeing register 2 - 0x224 - 0x20 - read-write - 0x00000808 - - - BUSLATW2W - Bus turnaround phase for consecutive write duration - 0 - 8 - - - BUSLATR2R - Bus turnaround phase for consecutive read duration - 8 - 8 - - - - - EXT3 - EXT3 - externl timeing register 3 - 0x228 - 0x20 - read-write - 0x00000808 - - - BUSLATW2W - Bus turnaround phase for consecutive write duration - 0 - 8 - - - BUSLATR2R - Bus turnaround phase for consecutive read duration - 8 - 8 - - - - - EXT4 - EXT4 - externl timeing register 4 - 0x22C - 0x20 - read-write - 0x00000808 - - - BUSLATW2W - Bus turnaround phase for consecutive write duration - 0 - 8 - - - BUSLATR2R - Bus turnaround phase for consecutive read duration - 8 - 8 - - - - - - - PWC - Power control - PWC - 0x40007000 - - 0x0 - 0x400 - registers - - - - CTRL - CTRL - Power control register - (PWC_CTRL) - 0x0 - 0x20 - read-write - 0x00000000 - - - VRSEL - Voltage regulator state select when deepsleep mode - 0 - 1 - - - LPSEL - Low power mode select when Cortex-M4F sleepdeep - 1 - 1 - - - CLSWEF - Clear SWEF flag - 2 - 1 - - - CLSEF - Clear SEF flag - 3 - 1 - - - PVMEN - Power voltage monitoring enable - 4 - 1 - - - PVMSEL - Power voltage monitoring boundary select - 5 - 3 - - - BPWEN - Battery powered domain write enable - 8 - 1 - - - - - CTRLSTS - CTRLSTS - Power control and status register - (PWC_CTRLSTS) - 0x4 - 0x20 - 0x00000000 - - - SWEF - Standby wake-up event flag - 0 - 1 - read-only - - - SEF - Standby mode entry flag - 1 - 1 - read-only - - - PVMOF - Power voltage monitoring output flag - 2 - 1 - read-only - - - SWPEN1 - Standby wake-up pin 1 enable - 8 - 1 - read-write - - - SWPEN2 - Standby wake-up pin 2 enable - 9 - 1 - read-write - - - - - LDOOV - LDOOV - LDO output voltage register - 0x10 - 0x20 - 0x00000000 - - - LDOOVSEL - LDO output voltage select - 0 - 3 - read-write - - - - - - - CRM - Clock and reset management - CRM - 0x40023800 - - 0x0 - 0x400 - registers - - - CRM - CRM global interrupt - 5 - - - - CTRL - CTRL - Clock control register - 0x0 - 0x20 - 0x00000083 - - - HICKEN - High speed internal clock enable - 0 - 1 - read-write - - - HICKSTBL - High speed internal clock ready flag - 1 - 1 - read-only - - - HICKTRIM - High speed internal clock trimming - 2 - 6 - read-write - - - HICKCAL - High speed internal clock calibration - 8 - 8 - read-only - - - HEXTEN - High speed exernal crystal enable - 16 - 1 - read-write - - - HEXTSTBL - High speed exernal crystal ready flag - 17 - 1 - read-only - - - HEXTBYPS - High speed exernal crystal bypass - 18 - 1 - read-write - - - CFDEN - Clock failure detection enable - 19 - 1 - read-write - - - PLLEN - PLL enable - 24 - 1 - read-write - - - PLLSTBL - PLL clock ready flag - 25 - 1 - read-only - - - - - PLLCFG - PLLCFG - PLL configuration register - (CRM_PLLCFG) - 0x4 - 0x20 - 0x00033002 - - - PLL_MS - PLL pre-division - 0 - 4 - read-write - - - PLL_NS - PLL frequency multiplication factor - 6 - 9 - read-write - - - PLL_FR - PLL post-division - 16 - 3 - read-write - - - PLLRCS - PLL reference clock select - 22 - 1 - read-write - - - - - CFG - CFG - Clock configuration register(CRM_CFG) - 0x8 - 0x20 - 0x00000000 - - - SCLKSEL - System clock select - 0 - 2 - read-write - - - SCLKSTS - System Clock select Status - 2 - 2 - read-only - - - AHBDIV - AHB division - 4 - 4 - read-write - - - APB1DIV - APB1 division - 10 - 3 - read-write - - - APB2DIV - APB2 division - 13 - 3 - read-write - - - ERTCDIV - HEXT division for ERTC clock - 16 - 5 - read-write - - - CLKOUT1_SEL - Clock output1 selection - 21 - 2 - read-write - - - CLKOUT1DIV1 - Clock output1 division1 - 24 - 3 - read-write - - - CLKOUT2DIV1 - Clock output2 division1 - 27 - 3 - read-write - - - CLKOUT2_SEL1 - Clock output2 selection1 - 30 - 2 - read-write - - - - - CLKINT - CLKINT - Clock interrupt register - (CRM_CLKINT) - 0xC - 0x20 - 0x00000000 - - - LICKSTBLF - LICK ready interrupt flag - 0 - 1 - read-only - - - LEXTSTBLF - LEXT ready interrupt flag - 1 - 1 - read-only - - - HICKSTBLF - HICK ready interrupt flag - 2 - 1 - read-only - - - HEXTSTBLF - HEXT ready interrupt flag - 3 - 1 - read-only - - - PLLSTBLF - PLL ready interrupt flag - 4 - 1 - read-only - - - CFDF - Clock failure detection interrupt flag - 7 - 1 - read-only - - - LICKSTBLIEN - LICK ready interrupt enable - 8 - 1 - read-write - - - LEXTSTBLIEN - LEXT ready interrupt enable - 9 - 1 - read-write - - - HICKSTBLIEN - HICK ready interrupt enable - 10 - 1 - read-write - - - HEXTSTBLIEN - HEXT ready interrupt enable - 11 - 1 - read-write - - - PLLSTBLIEN - PLL ready interrupt enable - 12 - 1 - read-write - - - LICKSTBLFC - LICK ready interrupt clear - 16 - 1 - write-only - - - LEXTSTBLFC - LEXT ready interrupt clear - 17 - 1 - write-only - - - HICKSTBLFC - HICK ready interrupt clear - 18 - 1 - write-only - - - HEXTSTBLFC - HEXT ready interrupt clear - 19 - 1 - write-only - - - PLLSTBLFC - PLL ready interrupt clear - 20 - 1 - write-only - - - CFDFC - Clock failure detection interrupt clear - 23 - 1 - write-only - - - - - AHBRST1 - AHBRST1 - AHB peripheral reset register1 - (CRM_AHBRST1) - 0x10 - 0x20 - read-write - 0x000000000 - - - GPIOARST - IO port A reset - 0 - 1 - - - GPIOBRST - IO port B reset - 1 - 1 - - - GPIOCRST - IO port C reset - 2 - 1 - - - GPIODRST - IO port D reset - 3 - 1 - - - GPIOERST - IO port E reset - 4 - 1 - - - GPIOFRST - IO port F reset - 5 - 1 - - - GPIOGRST - IO port G reset - 6 - 1 - - - GPIOHRST - IO port H reset - 7 - 1 - - - CRCRST - CRC reset - 12 - 1 - - - EDMARST - EDMA reset - 21 - 1 - - - DMA1RST - DMA1 reset - 22 - 1 - - - DMA2RST - DMA2 reset - 24 - 1 - - - EMACRST - EMAC reset - 25 - 1 - - - OTGFS2RST - OTGFS2 interface reset - 29 - 1 - - - - - AHBRST2 - AHBRST2 - AHB peripheral reset register 2 - (CRM_AHBRST2) - 0x14 - 0x20 - read-write - 0x00000000 - - - DVPRST - DVP reset - 0 - 1 - - - OTGFS1RST - OTGFS1 reset - 7 - 1 - - - SDIO1RST - SDIO1 reset - 15 - 1 - - - - - AHBRST3 - AHBRST3 - AHB peripheral reset register 3 - (CRM_AHBRST3) - 0x18 - 0x20 - read-write - 0x00000000 - - - XMCRST - XMC reset - 0 - 1 - - - QSPI1RST - QSPI1 reset - 1 - 1 - - - QSPI2RST - QSPI2 reset - 14 - 1 - - - SDIO2RST - SDIO2 reset - 15 - 1 - - - - - APB1RST - APB1RST - APB1 peripheral reset register - (CRM_APB1RST) - 0x20 - 0x20 - read-write - 0x00000000 - - - TMR2RST - Timer2 reset - 0 - 1 - - - TMR3RST - Timer3 reset - 1 - 1 - - - TMR4RST - Timer4 reset - 2 - 1 - - - TMR5RST - Timer5 reset - 3 - 1 - - - TMR6RST - Timer6 reset - 4 - 1 - - - TMR7RST - Timer7 reset - 5 - 1 - - - TMR12RST - Timer12 reset - 6 - 1 - - - TMR13RST - Timer13 reset - 7 - 1 - - - TMR14RST - Timer14 reset - 8 - 1 - - - WWDTRST - Window watchdog reset - 11 - 1 - - - SPI2RST - SPI2 reset - 14 - 1 - - - SPI3RST - SPI3 reset - 15 - 1 - - - USART2RST - USART2 reset - 17 - 1 - - - USART3RST - USART3 reset - 18 - 1 - - - UART4RST - UART4 reset - 19 - 1 - - - UART5RST - UART5 reset - 20 - 1 - - - I2C1RST - I2C1 reset - 21 - 1 - - - I2C2RST - I2C2 reset - 22 - 1 - - - I2C3RST - I2C3 reset - 23 - 1 - - - CAN1RST - CAN1 reset - 25 - 1 - - - CAN2RST - CAN2 reset - 26 - 1 - - - PWCRST - PWC reset - 28 - 1 - - - DACRST - DAC reset - 29 - 1 - - - UART7RST - UART7 reset - 30 - 1 - - - UART8RST - UART8 reset - 31 - 1 - - - - - APB2RST - APB2RST - APB2 peripheral reset register - (CRM_APB2RST) - 0x24 - 0x20 - read-write - 0x00000000 - - - TMR1RST - Timer1 reset - 0 - 1 - - - TMR8RST - Timer8 reset - 1 - 1 - - - USART1RST - USART1 reset - 4 - 1 - - - USART6RST - USART6 reset - 5 - 1 - - - ADCRST - ADC reset - 8 - 1 - - - SPI1RST - SPI1 reset - 12 - 1 - - - SPI4RST - SPI4 reset - 13 - 1 - - - SCFGRST - SCFG reset - 14 - 1 - - - TMR9RST - Timer9 reset - 16 - 1 - - - TMR10RST - Timer10 reset - 17 - 1 - - - TMR11RST - Timer 11 reset - 18 - 1 - - - TMR20RST - Timer20 reset - 20 - 1 - - - ACCRST - ACC reset - 29 - 1 - - - - - AHBEN1 - AHBEN1 - AHB Peripheral Clock enable register 1 - (CRM_AHBEN1) - 0x30 - 0x20 - read-write - 0x00000000 - - - GPIOAEN - IO A clock enable - 0 - 1 - - - GPIOBEN - IO B clock enable - 1 - 1 - - - GPIOCEN - IO C clock enable - 2 - 1 - - - GPIODEN - IO D clock enable - 3 - 1 - - - GPIOEEN - IO E clock enable - 4 - 1 - - - GPIOFEN - IO F clock enable - 5 - 1 - - - GPIOGEN - IO G clock enable - 6 - 1 - - - GPIOHEN - IO H clock enable - 7 - 1 - - - CRCEN - CRC clock enable - 12 - 1 - - - EDMAEN - DMA1 clock enable - 21 - 1 - - - DMA1EN - DMA1 clock enable - 22 - 1 - - - DMA2EN - DMA2 clock enable - 24 - 1 - - - EMACEN - EMAC clock enable - 25 - 1 - - - EMACTXEN - EMAC Tx clock enable - 26 - 1 - - - EMACRXEN - EMAC Rx clock enable - 27 - 1 - - - EMACPTPEN - EMAC PTP clock enable - 28 - 1 - - - OTGFS2EN - OTGFS2 clock enable - 29 - 1 - - - - - AHBEN2 - AHBEN2 - AHB peripheral clock enable register 2 - (CRM_AHBEN2) - 0x34 - 0x20 - read-write - 0x00000000 - - - DVPEN - DVP clock enable - 0 - 1 - - - OTGFS1EN - OTGFS1 clock enable - 7 - 1 - - - SDIO1EN - SDIO1 clock enable - 15 - 1 - - - - - AHBEN3 - AHBEN3 - AHB peripheral clock enable register 3 - (CRM_AHBEN3) - 0x38 - 0x20 - read-write - 0x00000000 - - - XMCEN - XMC clock enable - 0 - 1 - - - QSPI1EN - QSPI1 clock enable - 1 - 1 - - - QSPI2EN - QSPI2 clock enable - 14 - 1 - - - SDIO2EN - SDIO 2 clock enable - 15 - 1 - - - - - APB1EN - APB1EN - APB1 peripheral clock enable register - (CRM_APB1EN) - 0x40 - 0x20 - read-write - 0x00000000 - - - TMR2EN - Timer2 clock enable - 0 - 1 - - - TMR3EN - Timer3 clock enable - 1 - 1 - - - TMR4EN - Timer4 clock enable - 2 - 1 - - - TMR5EN - Timer5 clock enable - 3 - 1 - - - TMR6EN - Timer6 clock enable - 4 - 1 - - - TMR7EN - Timer7 clock enable - 5 - 1 - - - TMR12EN - Timer12 clock enable - 6 - 1 - - - TMR13EN - Timer13 clock enable - 7 - 1 - - - TMR14EN - Timer14 clock enable - 8 - 1 - - - WWDTEN - WWDT clock enable - 11 - 1 - - - SPI2EN - SPI2 clock enable - 14 - 1 - - - SPI3EN - SPI3 clock enable - 15 - 1 - - - USART2EN - USART2 clock enable - 17 - 1 - - - USART3EN - USART3 clock enable - 18 - 1 - - - UART4EN - UART4 clock enable - 19 - 1 - - - UART5EN - UART5 clock enable - 20 - 1 - - - I2C1EN - I2C1 clock enable - 21 - 1 - - - I2C2EN - I2C2 clock enable - 22 - 1 - - - I2C3EN - I2C3 clock enable - 23 - 1 - - - CAN1EN - CAN1 clock enable - 25 - 1 - - - CAN2EN - CAN2 clock enable - 26 - 1 - - - PWCEN - PWC clock enable - 28 - 1 - - - DACEN - DAC clock enable - 29 - 1 - - - UART7EN - UART7 clock enable - 30 - 1 - - - UART8EN - UART8 clock enable - 31 - 1 - - - - - APB2EN - APB2EN - APB2 peripheral clock enable register - (CRM_APB2EN) - 0x44 - 0x20 - read-write - 0x00000000 - - - TMR1EN - Timer1 clock enable - 0 - 1 - - - TMR8EN - Timer8 clock enable - 1 - 1 - - - USART1EN - USART1 clock enable - 4 - 1 - - - USART6EN - USART6 clock enable - 5 - 1 - - - ADC1EN - ADC1 clock enable - 8 - 1 - - - ADC2EN - ADC2 clock enable - 9 - 1 - - - ADC3EN - ADC3 clock enable - 10 - 1 - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - SPI4EN - SPI4 clock enable - 13 - 1 - - - SCFGEN - SCFG clock enable - 14 - 1 - - - TMR9EN - Timer9 clock enable - 16 - 1 - - - TMR10EN - Timer10 clock enable - 17 - 1 - - - TMR11EN - Timer11 clock enable - 18 - 1 - - - TMR20EN - Timer20 clock enable - 20 - 1 - - - ACCEN - ACC clock enable - 29 - 1 - - - - - AHBLPEN1 - AHBLPEN1 - AHB Low-power Peripheral Clock enable - register 1 (CRM_AHBLPEN1) - 0x50 - 0x20 - read-write - 0x3E6390FF - - - GPIOALPEN - IO A clock enable during sleep mode - 0 - 1 - - - GPIOBLPEN - IO B clock enable during sleep mode - 1 - 1 - - - GPIOCLPEN - IO C clock enable during sleep mode - 2 - 1 - - - GPIODLPEN - IO D clock enable during sleep mode - 3 - 1 - - - GPIOELPEN - IO E clock enable during sleep mode - 4 - 1 - - - GPIOFLPEN - IO F clock enable during sleep mode - 5 - 1 - - - GPIOGLPEN - IO G clock enable during sleep mode - 6 - 1 - - - GPIOHLPEN - IO H clock enable during sleep mode - 7 - 1 - - - CRCLPEN - CRC clock enable during sleep mode - 12 - 1 - - - FLASHLPEN - Flash clock enable during sleep mode - 15 - 1 - - - SRAM1LPEN - SRAM1 clock enable during sleep mode - 16 - 1 - - - SRAM2LPEN - SRAM2 clock enable during sleep mode - 17 - 1 - - - EDMALPEN - EDMA clock enable during sleep mode - 21 - 1 - - - DMA1LPEN - DMA1 clock enable during sleep mode - 22 - 1 - - - DMA2LPEN - DMA2 clock enable during sleep mode - 24 - 1 - - - EMACLPEN - EMAC clock enable during sleep mode - 25 - 1 - - - EMACTXLPEN - EMAC Tx clock enable during sleep mode - 26 - 1 - - - EMACRXLPEN - EMAC Rx clock enable during sleep mode - 27 - 1 - - - EMACPTPLPEN - EMAC PTP clock enable during sleep mode - 28 - 1 - - - OTGFS2LPEN - OTGFS2 clock enable during sleep mode - 29 - 1 - - - - - AHBLPEN2 - AHBLPEN2 - AHB peripheral Low-power clock - enable register 2 (CRM_AHBLPEN2) - 0x54 - 0x20 - read-write - 0x00008081 - - - DVPLPEN - DVP clock enable during sleep mode - 0 - 1 - - - OTGFS1LPEN - OTGFS1 clock enable during sleep mode - 7 - 1 - - - SDIO1LPEN - SDIO1 clock enable during sleep mode - 15 - 1 - - - - - AHBLPEN3 - AHBLPEN3 - AHB peripheral Low-power clock - enable register 3 (CRM_AHBLPEN3) - 0x58 - 0x20 - read-write - 0x0000C003 - - - XMCLPEN - XMC clock enable during sleep mode - 0 - 1 - - - QSPI1LPEN - QSPI1 clock enable during sleep mode - 1 - 1 - - - QSPI2LPEN - QSPI2 clock enable during sleep mode - 14 - 1 - - - SDIO2LPEN - SDIO2 clock enable during sleep mode - 15 - 1 - - - - - APB1LPEN - APB1LPEN - APB1 peripheral Low-power clock - enable register (CRM_APB1LPEN) - 0x60 - 0x20 - read-write - 0xF6FEE9FF - - - TMR2LPEN - Timer2 clock enable during sleep mode - 0 - 1 - - - TMR3LPEN - Timer3 clock enable during sleep mode - 1 - 1 - - - TMR4LPEN - Timer4 clock enable during sleep mode - 2 - 1 - - - TMR5LPEN - Timer5 clock enable during sleep mode - 3 - 1 - - - TMR6LPEN - Timer6 clock enable during sleep mode - 4 - 1 - - - TMR7LPEN - Timer7 clock enable during sleep mode - 5 - 1 - - - TMR12LPEN - Timer12 clock enable during sleep mode - 6 - 1 - - - TMR13LPEN - Timer13 clock enable during sleep mode - 7 - 1 - - - TMR14LPEN - Timer14 clock enable during sleep mode - 8 - 1 - - - WWDTLPEN - WWDT clock enable during sleep mode - 11 - 1 - - - SPI2LPEN - SPI2 clock enable during sleep mode - 14 - 1 - - - SPI3LPEN - SPI3 clock enable during sleep mode - 15 - 1 - - - USART2LPEN - USART2 clock enable during sleep mode - 17 - 1 - - - USART3LPEN - USART3 clock enable during sleep mode - 18 - 1 - - - UART4LPEN - UART4 clock enable during sleep mode - 19 - 1 - - - UART5LPEN - UART5 clock enable during sleep mode - 20 - 1 - - - I2C1CPEN - I2C1 clock enable during sleep mode - 21 - 1 - - - I2C2CPEN - I2C2 clock enable during sleep mode - 22 - 1 - - - I2C3CPEN - I2C3 clock enable during sleep mode - 23 - 1 - - - CAN1LPEN - CAN1 clock enable during sleep mode - 25 - 1 - - - CAN2LPEN - CAN2 clock enable during sleep mode - 26 - 1 - - - PWCLPEN - PWC clock enable during sleep mode - 28 - 1 - - - DACLPEN - DAC clock enable during sleep mode - 29 - 1 - - - UART7LPEN - UART7 clock enable during sleep mode - 30 - 1 - - - UART8LPEN - UART8 clock enable during sleep mode - 31 - 1 - - - - - APB2LPEN - APB2LPEN - APB2 peripheral Low-power clock - enable register (CRM_APB2LPEN) - 0x64 - 0x20 - read-write - 0x20177733 - - - TMR1LPEN - Timer1 clock enable during sleep mode - 0 - 1 - - - TMR8LPEN - Timer8 clock enable during sleep mode - 1 - 1 - - - USART1LPEN - USART1 clock enable during sleep mode - 4 - 1 - - - USART6LPEN - USART6 clock enable during sleep mode - 5 - 1 - - - ADC1CPEN - ADC1 clock enable during sleep mode - 8 - 1 - - - ADC2CPEN - ADC2 clock enable during sleep mode - 9 - 1 - - - ADC3EN - ADC3 clock enable during sleep mode - 10 - 1 - - - SPI1LPEN - SPI1 clock enable during sleep mode - 12 - 1 - - - SPI4LPEN - SPI4 clock enable during sleep mode - 13 - 1 - - - SCFGLPEN - SCFG clock enable during sleep mode - 14 - 1 - - - TMR9LPEN - Timer9 clock enable during sleep mode - 16 - 1 - - - TMR10LPEN - Timer10 clock enable during sleep mode - 17 - 1 - - - TMR11LPEN - Timer11 clock enable during sleep mode - 18 - 1 - - - TMR20LPEN - Timer20 clock enable during sleep mode - 20 - 1 - - - ACCLPEN - ACC clock enable during sleep mode - 29 - 1 - - - - - BPDC - BPDC - Battery powered domain control register - (CRM_BPDC) - 0x70 - 0x20 - 0x00000000 - - - LEXTEN - Low speed external crystal enable - 0 - 1 - read-write - - - LEXTSTBL - Low speed external crystal ready - 1 - 1 - read-only - - - LEXTBYPS - Low speed external crystal bypass - 2 - 1 - read-write - - - ERTCSEL - ERTC clock source selection - 8 - 2 - read-write - - - ERTCEN - ERTC clock enable - 15 - 1 - read-write - - - BPDRST - Battery powered domain software reset - 16 - 1 - read-write - - - - - CTRLSTS - CTRLSTS - Control/status register - (CRM_CTRLSTS) - 0x74 - 0x20 - 0x0C000000 - - - LICKEN - Low speed internal clock enable - 0 - 1 - read-write - - - LICKSTBL - Low speed internal clock ready - 1 - 1 - read-only - - - RSTFC - Reset reset flag - 24 - 1 - read-write - - - NRSTF - PIN reset flag - 26 - 1 - read-write - - - PORRSTF - POR/LVR reset flag - 27 - 1 - read-write - - - SWRSTF - Software reset flag - 28 - 1 - read-write - - - WDTRSTF - Watchdog timer reset flag - 29 - 1 - read-write - - - WWDTRSTF - Window watchdog timer reset flag - 30 - 1 - read-write - - - LPRSTF - Low-power reset flag - 31 - 1 - read-write - - - - - MISC1 - MISC1 - Miscellaneous register1 - 0xA0 - 0x20 - 0x00000000 - - - HICKCAL_KEY - HICKCAL write key value - 0 - 8 - read-write - - - HICKDIV - HICK 6 divider selection - 12 - 1 - read-write - - - HICK_TO_USB - HICK to usb clock - 13 - 1 - read-write - - - HICK_TO_SCLK - HICK to system clock - 14 - 1 - read-write - - - CLKOUT2_SEL2 - Clock output2 select2 - 16 - 4 - read-write - - - CLKOUT1DIV2 - Clock output1 division2 - 24 - 4 - read-write - - - CLKOUT2DIV2 - Clock output2 division2 - 28 - 4 - read-write - - - - - MISC2 - MISC2 - Miscellaneous register2 - 0xA4 - 0x20 - 0x0000000D - - - AUTO_STEP_EN - AUTO_STEP_EN - 4 - 2 - read-write - - - CLK_TO_TMR - Clock output internal connect to timer10 - 8 - 1 - read-write - - - USBDIV - USB division - 12 - 4 - read-write - - - - - - - GPIOA - General purpose I/Os - GPIO - 0x40020000 - - 0x0 - 0x400 - registers - - - - CFGR - CFGR - GPIO configuration register - 0x0 - 0x20 - read-write - 0x00000000 - - - IOMC15 - GPIOx pin 15 mode configurate - 30 - 2 - - - IOMC14 - GPIOx pin 14 mode configurate - 28 - 2 - - - IOMC13 - GPIOx pin 13 mode configurate - 26 - 2 - - - IOMC12 - GPIOx pin 12 mode configurate - 24 - 2 - - - IOMC11 - GPIOx pin 11 mode configurate - 22 - 2 - - - IOMC10 - GPIOx pin 10 mode configurate - 20 - 2 - - - IOMC9 - GPIOx pin 9 mode configurate - 18 - 2 - - - IOMC8 - GPIOx pin 8 mode configurate - 16 - 2 - - - IOMC7 - GPIOx pin 7 mode configurate - 14 - 2 - - - IOMC6 - GPIOx pin 6 mode configurate - 12 - 2 - - - IOMC5 - GPIOx pin 5 mode configurate - 10 - 2 - - - IOMC4 - GPIOx pin 4 mode configurate - 8 - 2 - - - IOMC3 - GPIOx pin 3 mode configurate - 6 - 2 - - - IOMC2 - GPIOx pin 2 mode configurate - 4 - 2 - - - IOMC1 - GPIOx pin 1 mode configurate - 2 - 2 - - - IOMC0 - GPIOx pin 0 mode configurate - 0 - 2 - - - - - OMODE - OMODE - GPIO output mode register - 0x4 - 0x20 - read-write - 0x00000000 - - - OM15 - GPIOx pin 15 outpu mode configurate - 15 - 1 - - - OM14 - GPIOx pin 14 outpu mode configurate - 14 - 1 - - - OM13 - GPIOx pin 13 outpu mode configurate - 13 - 1 - - - OM12 - GPIOx pin 12 outpu mode configurate - 12 - 1 - - - OM11 - GPIOx pin 11 outpu mode configurate - 11 - 1 - - - OM10 - GPIOx pin 10 outpu mode configurate - 10 - 1 - - - OM9 - GPIOx pin 9 outpu mode configurate - 9 - 1 - - - OM8 - GPIOx pin 8 outpu mode configurate - 8 - 1 - - - OM7 - GPIOx pin 7 outpu mode configurate - 7 - 1 - - - OM6 - GPIOx pin 6 outpu mode configurate - 6 - 1 - - - OM5 - GPIOx pin 5 outpu mode configurate - 5 - 1 - - - OM4 - GPIOx pin 4 outpu mode configurate - 4 - 1 - - - OM3 - GPIOx pin 3 outpu mode configurate - 3 - 1 - - - OM2 - GPIOx pin 2 outpu mode configurate - 2 - 1 - - - OM1 - GPIOx pin 1 outpu mode configurate - 1 - 1 - - - OM0 - GPIOx pin 0 outpu mode configurate - 0 - 1 - - - - - ODRVR - ODRVR - GPIO drive capability register - 0x8 - 0x20 - read-write - 0x00000000 - - - ODRV15 - GPIOx pin 15 output drive capability - 30 - 2 - - - ODRV14 - GPIOx pin 14 output drive capability - 28 - 2 - - - ODRV13 - GPIOx pin 13 output drive capability - 26 - 2 - - - ODRV12 - GPIOx pin 12 output drive capability - 24 - 2 - - - ODRV11 - GPIOx pin 11 output drive capability - 22 - 2 - - - ODRV10 - GPIOx pin 10 output drive capability - 20 - 2 - - - ODRV9 - GPIOx pin 9 output drive capability - 18 - 2 - - - ODRV8 - GPIOx pin 8 output drive capability - 16 - 2 - - - ODRV7 - GPIOx pin 7 output drive capability - 14 - 2 - - - ODRV6 - GPIOx pin 6 output drive capability - 12 - 2 - - - ODRV5 - GPIOx pin 5 output drive capability - 10 - 2 - - - ODRV4 - GPIOx pin 4 output drive capability - 8 - 2 - - - ODRV3 - GPIOx pin 3 output drive capability - 6 - 2 - - - ODRV2 - GPIOx pin 2 output drive capability - 4 - 2 - - - ODRV1 - GPIOx pin 1 output drive capability - 2 - 2 - - - ODRV0 - GPIOx pin 0 output drive capability - 0 - 2 - - - - - PULL - PULL - GPIO pull-up/pull-down register - 0xC - 0x20 - read-write - 0x00000000 - - - PULL15 - GPIOx pin 15 pull configuration - 30 - 2 - - - PULL14 - GPIOx pin 14 pull configuration - 28 - 2 - - - PULL13 - GPIOx pin 13 pull configuration - 26 - 2 - - - PULL12 - GPIOx pin 12 pull configuration - 24 - 2 - - - PULL11 - GPIOx pin 11 pull configuration - 22 - 2 - - - PULL10 - GPIOx pin 10 pull configuration - 20 - 2 - - - PULL9 - GPIOx pin 9 pull configuration - 18 - 2 - - - PULL8 - GPIOx pin 8 pull configuration - 16 - 2 - - - PULL7 - GPIOx pin 7 pull configuration - 14 - 2 - - - PULL6 - GPIOx pin 6 pull configuration - 12 - 2 - - - PULL5 - GPIOx pin 5 pull configuration - 10 - 2 - - - PULL4 - GPIOx pin 4 pull configuration - 8 - 2 - - - PULL3 - GPIOx pin 3 pull configuration - 6 - 2 - - - PULL2 - GPIOx pin 2 pull configuration - 4 - 2 - - - PULL1 - GPIOx pin 1 pull configuration - 2 - 2 - - - PULL0 - GPIOx pin 0 pull configuration - 0 - 2 - - - - - IDT - IDT - GPIO input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - IDT0 - Port input data - 0 - 1 - - - IDT1 - Port input data - 1 - 1 - - - IDT2 - Port input data - 2 - 1 - - - IDT3 - Port input data - 3 - 1 - - - IDT4 - Port input data - 4 - 1 - - - IDT5 - Port input data - 5 - 1 - - - IDT6 - Port input data - 6 - 1 - - - IDT7 - Port input data - 7 - 1 - - - IDT8 - Port input data - 8 - 1 - - - IDT9 - Port input data - 9 - 1 - - - IDT10 - Port input data - 10 - 1 - - - IDT11 - Port input data - 11 - 1 - - - IDT12 - Port input data - 12 - 1 - - - IDT13 - Port input data - 13 - 1 - - - IDT14 - Port input data - 14 - 1 - - - IDT15 - Port input data - 15 - 1 - - - - - ODT - ODT - GPIO output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - ODT0 - Port output data - 0 - 1 - - - ODT1 - Port output data - 1 - 1 - - - ODT2 - Port output data - 2 - 1 - - - ODT3 - Port output data - 3 - 1 - - - ODT4 - Port output data - 4 - 1 - - - ODT5 - Port output data - 5 - 1 - - - ODT6 - Port output data - 6 - 1 - - - ODT7 - Port output data - 7 - 1 - - - ODT8 - Port output data - 8 - 1 - - - ODT9 - Port output data - 9 - 1 - - - ODT10 - Port output data - 10 - 1 - - - ODT11 - Port output data - 11 - 1 - - - ODT12 - Port output data - 12 - 1 - - - ODT13 - Port output data - 13 - 1 - - - ODT14 - Port output data - 14 - 1 - - - ODT15 - Port output data - 15 - 1 - - - - - SCR - SCR - Port bit set/clear register - 0x18 - 0x20 - write-only - 0x00000000 - - - IOSB0 - Set bit 0 - 0 - 1 - - - IOSB1 - Set bit 1 - 1 - 1 - - - IOSB2 - Set bit 1 - 2 - 1 - - - IOSB3 - Set bit 3 - 3 - 1 - - - IOSB4 - Set bit 4 - 4 - 1 - - - IOSB5 - Set bit 5 - 5 - 1 - - - IOSB6 - Set bit 6 - 6 - 1 - - - IOSB7 - Set bit 7 - 7 - 1 - - - IOSB8 - Set bit 8 - 8 - 1 - - - IOSB9 - Set bit 9 - 9 - 1 - - - IOSB10 - Set bit 10 - 10 - 1 - - - IOSB11 - Set bit 11 - 11 - 1 - - - IOSB12 - Set bit 12 - 12 - 1 - - - IOSB13 - Set bit 13 - 13 - 1 - - - IOSB14 - Set bit 14 - 14 - 1 - - - IOSB15 - Set bit 15 - 15 - 1 - - - IOCB0 - Clear bit 0 - 16 - 1 - - - IOCB1 - Clear bit 1 - 17 - 1 - - - IOCB2 - Clear bit 2 - 18 - 1 - - - IOCB3 - Clear bit 3 - 19 - 1 - - - IOCB4 - Clear bit 4 - 20 - 1 - - - IOCB5 - Clear bit 5 - 21 - 1 - - - IOCB6 - Clear bit 6 - 22 - 1 - - - IOCB7 - Clear bit 7 - 23 - 1 - - - IOCB8 - Clear bit 8 - 24 - 1 - - - IOCB9 - Clear bit 9 - 25 - 1 - - - IOCB10 - Clear bit 10 - 26 - 1 - - - IOCB11 - Clear bit 11 - 27 - 1 - - - IOCB12 - Clear bit 12 - 28 - 1 - - - IOCB13 - Clear bit 13 - 29 - 1 - - - IOCB14 - Clear bit 14 - 30 - 1 - - - IOCB15 - Clear bit 15 - 31 - 1 - - - - - WPR - WPR - Port write protect - register - 0x1C - 0x20 - read-write - 0x00000000 - - - WPEN0 - Write protect enable 0 - 0 - 1 - - - WPEN1 - Write protect enable 1 - 1 - 1 - - - WPEN2 - Write protect enable 2 - 2 - 1 - - - WPEN3 - Write protect enable 3 - 3 - 1 - - - WPEN4 - Write protect enable 4 - 4 - 1 - - - WPEN5 - Write protect enable 5 - 5 - 1 - - - WPEN6 - Write protect enable 6 - 6 - 1 - - - WPEN7 - Write protect enable 7 - 7 - 1 - - - WPEN8 - Write protect enable 8 - 8 - 1 - - - WPEN9 - Write protect enable 9 - 9 - 1 - - - WPEN10 - Write protect enable 10 - 10 - 1 - - - WPEN11 - Write protect enable 11 - 11 - 1 - - - WPEN12 - Write protect enable 12 - 12 - 1 - - - WPEN13 - Write protect enable 13 - 13 - 1 - - - WPEN14 - Write protect enable 14 - 14 - 1 - - - WPEN15 - Write protect enable 15 - 15 - 1 - - - WPSEQ - Write protect sequence - 16 - 1 - - - - - MUXL - MUXL - GPIO muxing function low register - 0x20 - 0x20 - read-write - 0x00000000 - - - MUXL7 - GPIOx pin 7 muxing - 28 - 4 - - - MUXL6 - GPIOx pin 6 muxing - 24 - 4 - - - MUXL5 - GPIOx pin 5 muxing - 20 - 4 - - - MUXL4 - GPIOx pin 4 muxing - 16 - 4 - - - MUXL3 - GPIOx pin 3 muxing - 12 - 4 - - - MUXL2 - GPIOx pin 2 muxing - 8 - 4 - - - MUXL1 - GPIOx pin 1 muxing - 4 - 4 - - - MUXL0 - GPIOx pin 0 muxing - 0 - 4 - - - - - MUXH - MUXH - GPIO muxing function high register - 0x24 - 0x20 - read-write - 0x00000000 - - - MUXH15 - GPIOx pin 15 muxing - 28 - 4 - - - MUXH14 - GPIOx pin 14 muxing - 24 - 4 - - - MUXH13 - GPIOx pin 13 muxing - 20 - 4 - - - MUXH12 - GPIOx pin 12 muxing - 16 - 4 - - - MUXH11 - GPIOx pin 11 muxing - 12 - 4 - - - MUXH10 - GPIOx pin 10 muxing - 8 - 4 - - - MUXH9 - GPIOx pin 9 muxing - 4 - 4 - - - MUXH8 - GPIOx pin 8 muxing - 0 - 4 - - - - - CLR - CLR - GPIO bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - IOCB0 - Clear bit 0 - 0 - 1 - - - IOCB1 - Clear bit 1 - 1 - 1 - - - IOCB2 - Clear bit 1 - 2 - 1 - - - IOCB3 - Clear bit 3 - 3 - 1 - - - IOCB4 - Clear bit 4 - 4 - 1 - - - IOCB5 - Clear bit 5 - 5 - 1 - - - IOCB6 - Clear bit 6 - 6 - 1 - - - IOCB7 - Clear bit 7 - 7 - 1 - - - IOCB8 - Clear bit 8 - 8 - 1 - - - IOCB9 - Clear bit 9 - 9 - 1 - - - IOCB10 - Clear bit 10 - 10 - 1 - - - IOCB11 - Clear bit 11 - 11 - 1 - - - IOCB12 - Clear bit 12 - 12 - 1 - - - IOCB13 - Clear bit 13 - 13 - 1 - - - IOCB14 - Clear bit 14 - 14 - 1 - - - IOCB15 - Clear bit 15 - 15 - 1 - - - - - HDRV - HDRV - Huge current driver - 0x3C - 0x20 - read-write - 0x00000000 - - - HDRV0 - Port x driver bit y - 0 - 1 - - - HDRV1 - Port x driver bit y - 1 - 1 - - - HDRV2 - Port x driver bit y - 2 - 1 - - - HDRV3 - Port x driver bit y - 3 - 1 - - - HDRV4 - Port x driver bit y - 4 - 1 - - - HDRV5 - Port x driver bit y - 5 - 1 - - - HDRV6 - Port x driver bit y - 6 - 1 - - - HDRV7 - Port x driver bit y - 7 - 1 - - - HDRV8 - Port x driver bit y - 8 - 1 - - - HDRV9 - Port x driver bit y - 9 - 1 - - - HDRV10 - Port x driver bit y - 10 - 1 - - - HDRV11 - Port x driver bit y - 11 - 1 - - - HDRV12 - Port x driver bit y - 12 - 1 - - - HDRV13 - Port x driver bit y - 13 - 1 - - - HDRV14 - Port x driver bit y - 14 - 1 - - - HDRV15 - Port x driver bit y - 15 - 1 - - - - - - - GPIOB - 0x40020400 - - - GPIOC - 0x40020800 - - - GPIOD - 0x40020C00 - - - GPIOE - 0x40021000 - - - GPIOF - 0x40021400 - - - GPIOG - 0x40021800 - - - GPIOH - 0x40021C00 - - - EXINT - EXINT - EXINT - 0x40013C00 - - 0x0 - 0x400 - registers - - - EXINT0 - EXINT Line0 interrupt - 6 - - - EXINT1 - EXINT Line1 interrupt - 7 - - - EXINT2 - EXINT Line2 interrupt - 8 - - - EXINT3 - EXINT Line3 interrupt - 9 - - - EXINT4 - EXINT Line4 interrupt - 10 - - - EXINT9_5 - EXINT Line[9:5] interrupts - 23 - - - EXINT15_10 - EXINT Line[15:10] interrupts - 40 - - - PVM - PVM interrupt connect to EXINT line16 - 1 - - - ERTCALARM - ERTC Alarm interrupt connect to EXINT line17 - 41 - - - OTGFS1_WKUP - OTGFS1_WKUP interrupt connect to EXINT line18 - 42 - - - EMAC_WKUP - EMAC_WKUP interrupt connect to EXINT line19 - 62 - - - OTGFS2_WKUP - OTGFS2_WKUP interrupt connect to EXINT line20 - 76 - - - TAMPER - Tamper interrupt connect to EXINT line21 - 2 - - - ERTC_WKUP - ERTC Global interrupt connect to EXINT line22 - 3 - - - - INTEN - INTEN - Interrupt enable register - 0x0 - 0x20 - read-write - 0x00000000 - - - INTEN0 - Interrupt enable or disable on line 0 - 0 - 1 - - - INTEN1 - Interrupt enable or disable on line 1 - 1 - 1 - - - INTEN2 - Interrupt enable or disable on line 2 - 2 - 1 - - - INTEN3 - Interrupt enable or disable on line 3 - 3 - 1 - - - INTEN4 - Interrupt enable or disable on line 4 - 4 - 1 - - - INTEN5 - Interrupt enable or disable on line 5 - 5 - 1 - - - INTEN6 - Interrupt enable or disable on line 6 - 6 - 1 - - - INTEN7 - Interrupt enable or disable on line 7 - 7 - 1 - - - INTEN8 - Interrupt enable or disable on line 8 - 8 - 1 - - - INTEN9 - Interrupt enable or disable on line 9 - 9 - 1 - - - INTEN10 - Interrupt enable or disable on line 10 - 10 - 1 - - - INTEN11 - Interrupt enable or disable on line 11 - 11 - 1 - - - INTEN12 - Interrupt enable or disable on line 12 - 12 - 1 - - - INTEN13 - Interrupt enable or disable on line 13 - 13 - 1 - - - INTEN14 - Interrupt enable or disable on line 14 - 14 - 1 - - - INTEN15 - Interrupt enable or disable on line 15 - 15 - 1 - - - INTEN16 - Interrupt enable or disable on line 16 - 16 - 1 - - - INTEN17 - Interrupt enable or disable on line 17 - 17 - 1 - - - INTEN18 - Interrupt enable or disable on line 18 - 18 - 1 - - - INTEN19 - Interrupt enable or disable on line 19 - 19 - 1 - - - INTEN20 - Interrupt enable or disable on line 20 - 20 - 1 - - - INTEN21 - Interrupt enable or disable on line 21 - 21 - 1 - - - INTEN22 - Interrupt enable or disable on line 22 - 22 - 1 - - - - - EVTEN - EVTEN - Event enable register - 0x4 - 0x20 - read-write - 0x00000000 - - - EVTEN0 - Event enable or disable on line 0 - 0 - 1 - - - EVTEN1 - Event enable or disable on line 1 - 1 - 1 - - - EVTEN2 - Event enable or disable on line 2 - 2 - 1 - - - EVTEN3 - Event enable or disable on line 3 - 3 - 1 - - - EVTEN4 - Event enable or disable on line 4 - 4 - 1 - - - EVTEN5 - Event enable or disable on line 5 - 5 - 1 - - - EVTEN6 - Event enable or disable on line 6 - 6 - 1 - - - EVTEN7 - Event enable or disable on line 7 - 7 - 1 - - - EVTEN8 - Event enable or disable on line 8 - 8 - 1 - - - EVTEN9 - Event enable or disable on line 9 - 9 - 1 - - - EVTEN10 - Event enable or disable on line 10 - 10 - 1 - - - EVTEN11 - Event enable or disable on line 11 - 11 - 1 - - - EVTEN12 - Event enable or disable on line 12 - 12 - 1 - - - EVTEN13 - Event enable or disable on line 13 - 13 - 1 - - - EVTEN14 - Event enable or disable on line 14 - 14 - 1 - - - EVTEN15 - Event enable or disable on line 15 - 15 - 1 - - - EVTEN16 - Event enable or disable on line 16 - 16 - 1 - - - EVTEN17 - Event enable or disable on line 17 - 17 - 1 - - - EVTEN18 - Event enable or disable on line 18 - 18 - 1 - - - EVTEN19 - Event enable or disable on line 19 - 19 - 1 - - - EVTEN20 - Event enable or disable on line 20 - 20 - 1 - - - EVTEN21 - Event enable or disable on line 21 - 21 - 1 - - - EVTEN22 - Event enable or disable on line 22 - 22 - 1 - - - - - POLCFG1 - POLCFG1 - Rising polarity configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - RP0 - Rising polarity configuration bit of line 0 - 0 - 1 - - - RP1 - Rising polarity configuration bit of line 1 - 1 - 1 - - - RP2 - Rising polarity configuration bit of line 2 - 2 - 1 - - - RP3 - Rising polarity configuration bit of line 3 - 3 - 1 - - - RP4 - Rising polarity configuration bit of line 4 - 4 - 1 - - - RP5 - Rising polarity configuration bit of line 5 - 5 - 1 - - - RP6 - Rising polarity configuration bit of linee 6 - 6 - 1 - - - RP7 - Rising polarity configuration bit of line 7 - 7 - 1 - - - RP8 - Rising polarity configuration bit of line 8 - 8 - 1 - - - RP9 - Rising polarity configuration bit of line 9 - 9 - 1 - - - RP10 - Rising polarity configuration bit of line 10 - 10 - 1 - - - RP11 - Rising polarity configuration bit of line 11 - 11 - 1 - - - RP12 - Rising polarity configuration bit of line 12 - 12 - 1 - - - RP13 - Rising polarity configuration bit of line 13 - 13 - 1 - - - RP14 - Rising polarity configuration bit of line 14 - 14 - 1 - - - RP15 - Rising polarity configuration bit of line 15 - 15 - 1 - - - RP16 - Rising polarity configuration bit of line 16 - 16 - 1 - - - RP17 - Rising polarity configuration bit of line 17 - 17 - 1 - - - RP18 - Rising polarity configuration bit of line 18 - 18 - 1 - - - RP19 - Rising polarity configuration bit of line 19 - 19 - 1 - - - RP20 - Rising polarity configuration bit of line 20 - 20 - 1 - - - RP21 - Rising polarity configuration bit of line 21 - 21 - 1 - - - RP22 - Rising polarity configuration bit of line 22 - 22 - 1 - - - - - POLCFG2 - POLCFG2 - Falling polarity configuration register - 0xC - 0x20 - read-write - 0x00000000 - - - FP0 - Falling polarity event configuration bit of line 0 - 0 - 1 - - - FP1 - Falling polarity event configuration bit of line 1 - 1 - 1 - - - FP2 - Falling polarity event configuration bit of line 2 - 2 - 1 - - - FP3 - Falling polarity event configuration bit of line 3 - 3 - 1 - - - FP4 - Falling polarity event configuration bit of line 4 - 4 - 1 - - - FP5 - Falling polarity event configuration bit of line 5 - 5 - 1 - - - FP6 - Falling polarity event configuration bit of line 6 - 6 - 1 - - - FP7 - Falling polarity event configuration bit of line 7 - 7 - 1 - - - FP8 - Falling polarity event configuration bit of line 8 - 8 - 1 - - - FP9 - Falling polarity event configuration bit of line 9 - 9 - 1 - - - FP10 - Falling polarity event configuration bit of line 10 - 10 - 1 - - - FP11 - Falling polarity event configuration bit of line 11 - 11 - 1 - - - FP12 - Falling polarity event configuration bit of line 12 - 12 - 1 - - - FP13 - Falling polarity event configuration bit of line 13 - 13 - 1 - - - FP14 - Falling polarity event configuration bit of line 14 - 14 - 1 - - - FP15 - Falling polarity event configuration bit of line 15 - 15 - 1 - - - FP16 - Falling polarity event configuration bit of line 16 - 16 - 1 - - - FP17 - Falling polarity event configuration bit of line 17 - 17 - 1 - - - FP18 - Falling polarity event configuration bit of line 18 - 18 - 1 - - - FP19 - Falling polarity event configuration bit of line 19 - 19 - 1 - - - FP20 - Falling polarity event configuration bit of line 20 - 20 - 1 - - - FP21 - Falling polarity event configuration bit of line 21 - 21 - 1 - - - FP22 - Falling polarity event configuration bit of line 22 - 22 - 1 - - - - - SWTRG - SWTRG - Software triggle register - 0x10 - 0x20 - read-write - 0x00000000 - - - SWT0 - Software triggle on line 0 - 0 - 1 - - - SWT1 - Software triggle on line 1 - 1 - 1 - - - SWT2 - Software triggle on line 2 - 2 - 1 - - - SWT3 - Software triggle on line 3 - 3 - 1 - - - SWT4 - Software triggle on line 4 - 4 - 1 - - - SWT5 - Software triggle on line 5 - 5 - 1 - - - SWT6 - Software triggle on line 6 - 6 - 1 - - - SWT7 - Software triggle on line 7 - 7 - 1 - - - SWT8 - Software triggle on line 8 - 8 - 1 - - - SWT9 - Software triggle on line 9 - 9 - 1 - - - SWT10 - Software triggle on line 10 - 10 - 1 - - - SWT11 - Software triggle on line 11 - 11 - 1 - - - SWT12 - Software triggle on line 12 - 12 - 1 - - - SWT13 - Software triggle on line 13 - 13 - 1 - - - SWT14 - Software triggle on line 14 - 14 - 1 - - - SWT15 - Software triggle on line 15 - 15 - 1 - - - SWT16 - Software triggle on line 16 - 16 - 1 - - - SWT17 - Software triggle on line 17 - 17 - 1 - - - SWT18 - Software triggle on line 18 - 18 - 1 - - - SWT19 - Software triggle on line 19 - 19 - 1 - - - SWT20 - Software triggle on line 20 - 20 - 1 - - - SWT21 - Software triggle on line 21 - 21 - 1 - - - SWT22 - Software triggle on line 22 - 22 - 1 - - - - - INTSTS - INTSTS - Interrupt status register - 0x14 - 0x20 - read-write - 0x00000000 - - - LINE0 - Line 0 state bit - 0 - 1 - - - LINE1 - Line 1 state bit - 1 - 1 - - - LINE2 - Line 2 state bit - 2 - 1 - - - LINE3 - Line 3 state bit - 3 - 1 - - - LINE4 - Line 4 state bit - 4 - 1 - - - LINE5 - Line 5 state bit - 5 - 1 - - - LINE6 - Line 6 state bit - 6 - 1 - - - LINE7 - Line 7 state bit - 7 - 1 - - - LINE8 - Line 8 state bit - 8 - 1 - - - LINE9 - Line 9 state bit - 9 - 1 - - - LINE10 - Line 10 state bit - 10 - 1 - - - LINE11 - Line 11 state bit - 11 - 1 - - - LINE12 - Line 12 state bit - 12 - 1 - - - LINE13 - Line 13 state bit - 13 - 1 - - - LINE14 - Line 14 state bit - 14 - 1 - - - LINE15 - Line 15 state bit - 15 - 1 - - - LINE16 - Line 16 state bit - 16 - 1 - - - LINE17 - Line 17 state bit - 17 - 1 - - - LINE18 - Line 18 state bit - 18 - 1 - - - LINE19 - Line 19 state bit - 19 - 1 - - - LINE20 - Line 20 state bit - 20 - 1 - - - LINE21 - Line 21 state bit - 21 - 1 - - - LINE22 - Line 22 state bit - 22 - 1 - - - - - - - EDMA - EDMA controller - EDMA - 0x40026000 - - 0x0 - 0x400 - registers - - - EDMA_Stream1 - EDMA Stream1 global interrupt - 11 - - - EDMA_Stream2 - EDMA Stream2 global interrupt - 12 - - - EDMA_Stream3 - EDMA Stream3 global interrupt - 13 - - - EDMA_Stream4 - EDMA Stream4 global interrupt - 14 - - - EDMA_Stream5 - EDMA Stream5 global interrupt - 15 - - - EDMA_Stream6 - EDMA Stream6 global interrupt - 16 - - - EDMA_Stream7 - EDMA Stream7 global interrupt - 17 - - - EDMA_Stream8 - EDMA Stream8 global interrupt - 47 - - - - STS1 - STS1 - Interrupt status register1 - 0x0 - 0x20 - read-only - 0x00000000 - - - FDTF4 - Stream 4 Full data transfer interrupt flag - - 27 - 1 - - - HDTF4 - Stream 4 half data transfer interrupt flag - - 26 - 1 - - - DTERRF4 - Stream 4 transfer error interrupt flag - - 25 - 1 - - - DMERRF4 - Stream 4 direct mode error interrupt flag - - 24 - 1 - - - FERRF4 - Stream 4 FIFO error interrupt flag - - 22 - 1 - - - FDTF3 - Stream 3 Full data transfer interrupt flag - - 21 - 1 - - - HDTF3 - Stream 3 half data transfer interrupt flag - - 20 - 1 - - - DTERRF3 - Stream 3 transfer error interrupt flag - - 19 - 1 - - - DMERRF3 - Stream 3 direct mode error interrupt flag - - 18 - 1 - - - FERRF3 - Stream 3 FIFO error interrupt flag - - 16 - 1 - - - FDTF2 - Stream 2 Full data transfer interrupt flag - - 11 - 1 - - - HDTF2 - Stream 2 half data transfer interrupt flag - - 10 - 1 - - - DTERRF2 - Stream 2 transfer error interrupt flag - - 9 - 1 - - - DMERRF2 - Stream 2 direct mode error interrupt flag - - 8 - 1 - - - FERRF2 - Stream 2 FIFO error interrupt flag - - 6 - 1 - - - FDTF1 - Stream 1 Full data transfer interrupt flag - - 5 - 1 - - - HDTF1 - Stream 1 half data transfer interrupt flag - - 4 - 1 - - - DTERRF1 - Stream 1 transfer error interrupt flag - - 3 - 1 - - - DMERRF1 - Stream 1 direct mode error interrupt flag - - 2 - 1 - - - FERRF1 - Stream 1 FIFO error interrupt flag - - 0 - 1 - - - - - STS2 - STS2 - Interrupt status register2 - 0x4 - 0x20 - read-only - 0x00000000 - - - FDTF8 - Stream 8 full data transfer interrupt flag - - 27 - 1 - - - HDTF8 - Stream 8 half data transfer interrupt flag - - 26 - 1 - - - DTERRF8 - Stream 8 transfer error interrupt flag - - 25 - 1 - - - DMERRF8 - Stream 8 direct mode error interrupt flag - - 24 - 1 - - - FERRF8 - Stream 8 FIFO error interrupt flag - - 22 - 1 - - - FDTF7 - Stream 7 full data transfer interrupt flag - - 21 - 1 - - - HDTF7 - Stream 7 half data transfer interrupt flag - - 20 - 1 - - - DTERRF7 - Stream 7 transfer error interrupt flag - - 19 - 1 - - - DMERRF7 - Stream 7 direct mode error interrupt flag - - 18 - 1 - - - FERRF7 - Stream 7 FIFO error interrupt flag - - 16 - 1 - - - FDTF6 - Stream 6 full data transfer interrupt flag - - 11 - 1 - - - HDTF6 - Stream 6 half data transfer interrupt flag - - 10 - 1 - - - DTERRF6 - Stream 6 transfer error interrupt flag - - 9 - 1 - - - DMERRF6 - Stream 6 direct mode error interrupt flag - - 8 - 1 - - - FERRF6 - Stream 6 FIFO error interrupt flag - - 6 - 1 - - - FDTF5 - Stream 5 full data transfer interrupt flag - - 5 - 1 - - - HDTF5 - Stream 5 half data transfer interrupt flag - - 4 - 1 - - - DTERRF5 - Stream 5 transfer error interrupt flag - - 3 - 1 - - - DMERRF5 - Stream 5 direct mode error interrupt flag - - 2 - 1 - - - FERRF5 - Stream 5 FIFO error interrupt flag - - 0 - 1 - - - - - CLR1 - CLR1 - Interrupt flag clear register1 - - 0x8 - 0x20 - read-write - 0x00000000 - - - FDTFC4 - Stream 4 clear full data transfer complete interrupt flag - - 27 - 1 - - - HDTFC4 - Stream 4 clear half data transfer interrupt flag - - 26 - 1 - - - DTERRFC4 - Stream 4 clear transfer error interrupt flag - - 25 - 1 - - - DMERRFC4 - Stream 4 clear direct mode error interrupt flag - - 24 - 1 - - - FERRFC4 - Stream 4 clear FIFO error interrupt flag - - 22 - 1 - - - FDTFC3 - Stream 3 clear full data transfer complete interrupt flag - - 21 - 1 - - - HDTFC3 - Stream 3 clear half data transfer interrupt flag - - 20 - 1 - - - DTERRFC3 - Stream 3 clear transfer error interrupt flag - - 19 - 1 - - - DMERRFC3 - Stream 3 clear direct mode error interrupt flag - - 18 - 1 - - - FERRFC3 - Stream 3 clear FIFO error interrupt flag - - 16 - 1 - - - FDTFC2 - Stream 2 clear full data transfer complete interrupt flag - - 11 - 1 - - - HDTFC2 - Stream 2 clear half data transfer interrupt flag - - 10 - 1 - - - DTERRFC2 - Stream 2 clear transfer error interrupt flag - - 9 - 1 - - - DMERRFC2 - Stream 2 clear direct mode error interrupt flag - - 8 - 1 - - - FERRFC2 - Stream 2 clear FIFO error interrupt flag - - 6 - 1 - - - FDTFC1 - Stream 1 clear full data transfer complete interrupt flag - - 5 - 1 - - - HDTFC1 - Stream 1 clear half data transfer interrupt flag - - 4 - 1 - - - DTERRFC1 - Stream 1 clear transfer error interrupt flag - - 3 - 1 - - - DMERRFC1 - Stream 1 clear direct mode error interrupt flag - - 2 - 1 - - - FERRFC1 - Stream 1 clear FIFO error interrupt flag - - 0 - 1 - - - - - CLR2 - CLR2 - Interrupt flag clear register2 - - 0xC - 0x20 - read-write - 0x00000000 - - - FDTFC8 - Stream 8 clear full data transfer complete interrupt flag - - 27 - 1 - - - HDTFC8 - Stream 8 clear half data transfer interrupt flag - - 26 - 1 - - - DTERRFC8 - Stream 8 clear transfer error interrupt flag - - 25 - 1 - - - DMERRFC8 - Stream 8 clear direct mode error interrupt flag - - 24 - 1 - - - FERRFC8 - Stream 8 clear FIFO error interrupt flag - - 22 - 1 - - - FDTFC7 - Stream 7 clear full data transfer complete interrupt flag - - 21 - 1 - - - HDTFC7 - Stream 7 clear half data transfer interrupt flag - - 20 - 1 - - - DTERRFC7 - Stream 7 clear transfer error interrupt flag - - 19 - 1 - - - DMERRFC7 - Stream 7 clear direct mode error interrupt flag - - 18 - 1 - - - FERRFC7 - Stream 7 clear FIFO error interrupt flag - - 16 - 1 - - - FDTFC6 - Stream 6 clear full data transfer complete interrupt flag - - 11 - 1 - - - HDTFC6 - Stream 6 clear half data transfer interrupt flag - - 10 - 1 - - - DTERRFC6 - Stream 6 clear transfer error interrupt flag - - 9 - 1 - - - DMERRFC6 - Stream 6 clear direct mode error interrupt flag - - 8 - 1 - - - FERRFC6 - Stream 6 clear FIFO error interrupt flag - - 6 - 1 - - - FDTFC5 - Stream 5 clear full data transfer complete interrupt flag - - 5 - 1 - - - HDTFC5 - Stream 5 clear half data transfer interrupt flag - - 4 - 1 - - - DTERRFC5 - Stream 5 clear transfer error interrupt flag - - 3 - 1 - - - DMERRFC5 - Stream 5 clear direct mode error interrupt flag - - 2 - 1 - - - FERRFC5 - Stream 5 clear FIFO error interrupt flag - - 0 - 1 - - - - - S1CTRL - S1CTRL - stream 1 control - register - 0x10 - 0x20 - read-write - 0x00000000 - - - MBURST - Memory burst transmission - - 23 - 2 - - - PBURST - Peripheral burst transmission - - 21 - 2 - - - CM - Current memory (only in double buffer - mode) - 19 - 1 - - - DMM - Double memory mode - 18 - 1 - - - SPL - Stream priority level - 16 - 2 - - - PINCOS - Peripheral increment offset - size - 15 - 1 - - - MWIDTH - Memory data width - 13 - 2 - - - PWIDTH - Peripheral data width - 11 - 2 - - - MINCM - Memory increment mode - 10 - 1 - - - PINCM - Peripheral increment mode - 9 - 1 - - - LM - Loop mode - 8 - 1 - - - DTD - Data transfer direction - 6 - 2 - - - PFCTRL - Peripheral flow controller - 5 - 1 - - - FDTIEN - Full data transfer complete interrupt - enable - 4 - 1 - - - HDTIEN - Half data transfer interrupt - enable - 3 - 1 - - - DTERRIEN - Transfer error interrupt - enable - 2 - 1 - - - DMERRIEN - Direct mode error interrupt - enable - 1 - 1 - - - SEN - Stream enable / flag stream ready when - read low - 0 - 1 - - - - - S1DTCNT - S1DTCNT - stream 1 number of data - register - 0x14 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data items to - transfer - 0 - 16 - - - - - S1PADDR - S1PADDR - stream 1 peripheral address - register - 0x18 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - S1M0ADDR - S1M0ADDR - stream 1 memory 0 address - register - 0x1C - 0x20 - read-write - 0x00000000 - - - M0ADDR - Memory 0 address - 0 - 32 - - - - - S1M1ADDR - S1M1ADDR - stream 1 memory 1 address - register - 0x20 - 0x20 - read-write - 0x00000000 - - - M1ADDR - Memory 1 address (used in case of Double - buffer mode) - 0 - 32 - - - - - S1FCTRL - S1FCTRL - stream 1 FIFO control register - 0x24 - 0x20 - 0x00000021 - - - FERRIEN - FIFO error interrupt - enable - 7 - 1 - read-write - - - FSTS - FIFO status - 3 - 3 - read-only - - - FEN - FIFO mode enable - 2 - 1 - read-write - - - FTHSEL - FIFO threshold selection - 0 - 2 - read-write - - - - - S2CTRL - S2CTRL - stream 2 control - register - 0x28 - 0x20 - read-write - 0x00000000 - - - MBURST - Memory burst transmission - - 23 - 2 - - - PBURST - Peripheral burst transmission - - 21 - 2 - - - CM - Current memory (only in double buffer - mode) - 19 - 1 - - - DMM - Double memory mode - 18 - 1 - - - SPL - Stream priority level - 16 - 2 - - - PINCOS - Peripheral increment offset - size - 15 - 1 - - - MWIDTH - Memory data width - 13 - 2 - - - PWIDTH - Peripheral data width - 11 - 2 - - - MINCM - Memory increment mode - 10 - 1 - - - PINCM - Peripheral increment mode - 9 - 1 - - - LM - Loop mode - 8 - 1 - - - DTD - Data transfer direction - 6 - 2 - - - PFCTRL - Peripheral flow controller - 5 - 1 - - - FDTIEN - Full data transfer complete interrupt - enable - 4 - 1 - - - HDTIEN - Half data transfer interrupt - enable - 3 - 1 - - - DTERRIEN - Transfer error interrupt - enable - 2 - 1 - - - DMERRIEN - Direct mode error interrupt - enable - 1 - 1 - - - SEN - Stream enable / flag stream ready when - read low - 0 - 1 - - - - - S2DTCNT - S2DTCNT - stream 2 number of data - register - 0x2C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data items to - transfer - 0 - 16 - - - - - S2PADDR - S2PADDR - stream 2 peripheral address - register - 0x30 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - S2M0ADDR - S2M0ADDR - stream 2 memory 0 address - register - 0x34 - 0x20 - read-write - 0x00000000 - - - M0ADDR - Memory 0 address - 0 - 32 - - - - - S2M1ADDR - S2M1ADDR - stream 2 memory 1 address - register - 0x38 - 0x20 - read-write - 0x00000000 - - - M1ADDR - Memory 1 address (used in case of Double - buffer mode) - 0 - 32 - - - - - S2FCTRL - S2FCTRL - stream 2 FIFO control register - 0x3C - 0x20 - 0x00000021 - - - FERRIEN - FIFO error interrupt - enable - 7 - 1 - read-write - - - FSTS - FIFO status - 3 - 3 - read-only - - - FEN - FIFO mode enable - 2 - 1 - read-write - - - FTHSEL - FIFO threshold selection - 0 - 2 - read-write - - - - - S3CTRL - S3CTRL - stream 3 control - register - 0x40 - 0x20 - read-write - 0x00000000 - - - MBURST - Memory burst transmission - - 23 - 2 - - - PBURST - Peripheral burst transmission - - 21 - 2 - - - CM - Current memory (only in double buffer - mode) - 19 - 1 - - - DMM - Double memory mode - 18 - 1 - - - SPL - Stream priority level - 16 - 2 - - - PINCOS - Peripheral increment offset - size - 15 - 1 - - - MWIDTH - Memory data width - 13 - 2 - - - PWIDTH - Peripheral data width - 11 - 2 - - - MINCM - Memory increment mode - 10 - 1 - - - PINCM - Peripheral increment mode - 9 - 1 - - - LM - Loop mode - 8 - 1 - - - DTD - Data transfer direction - 6 - 2 - - - PFCTRL - Peripheral flow controller - 5 - 1 - - - FDTIEN - Full data transfer complete interrupt - enable - 4 - 1 - - - HDTIEN - Half data transfer interrupt - enable - 3 - 1 - - - DTERRIEN - Transfer error interrupt - enable - 2 - 1 - - - DMERRIEN - Direct mode error interrupt - enable - 1 - 1 - - - SEN - Stream enable / flag stream ready when - read low - 0 - 1 - - - - - S3DTCNT - S3DTCNT - stream 3 number of data - register - 0x44 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data items to - transfer - 0 - 16 - - - - - S3PADDR - S3PADDR - stream 3 peripheral address - register - 0x48 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - S3M0ADDR - S3M0ADDR - stream 3 memory 0 address - register - 0x4C - 0x20 - read-write - 0x00000000 - - - M0ADDR - Memory 0 address - 0 - 32 - - - - - S3M1ADDR - S3M1ADDR - stream 3 memory 1 address - register - 0x50 - 0x20 - read-write - 0x00000000 - - - M1ADDR - Memory 1 address (used in case of Double - buffer mode) - 0 - 32 - - - - - S3FCTRL - S3FCTRL - stream 3 FIFO control register - 0x54 - 0x20 - 0x00000021 - - - FERRIEN - FIFO error interrupt - enable - 7 - 1 - read-write - - - FSTS - FIFO status - 3 - 3 - read-only - - - FEN - FIFO mode enable - 2 - 1 - read-write - - - FTHSEL - FIFO threshold selection - 0 - 2 - read-write - - - - - S4CTRL - S4CTRL - stream 4 control - register - 0x58 - 0x20 - read-write - 0x00000000 - - - MBURST - Memory burst transmission - - 23 - 2 - - - PBURST - Peripheral burst transmission - - 21 - 2 - - - CM - Current memory (only in double buffer - mode) - 19 - 1 - - - DMM - Double memory mode - 18 - 1 - - - SPL - Stream priority level - 16 - 2 - - - PINCOS - Peripheral increment offset - size - 15 - 1 - - - MWIDTH - Memory data width - 13 - 2 - - - PWIDTH - Peripheral data width - 11 - 2 - - - MINCM - Memory increment mode - 10 - 1 - - - PINCM - Peripheral increment mode - 9 - 1 - - - LM - Loop mode - 8 - 1 - - - DTD - Data transfer direction - 6 - 2 - - - PFCTRL - Peripheral flow controller - 5 - 1 - - - FDTIEN - Full data transfer complete interrupt - enable - 4 - 1 - - - HDTIEN - Half data transfer interrupt - enable - 3 - 1 - - - DTERRIEN - Transfer error interrupt - enable - 2 - 1 - - - DMERRIEN - Direct mode error interrupt - enable - 1 - 1 - - - SEN - Stream enable / flag stream ready when - read low - 0 - 1 - - - - - S4DTCNT - S4DTCNT - stream 4 number of data - register - 0x5C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data items to - transfer - 0 - 16 - - - - - S4PADDR - S4PADDR - stream 4 peripheral address - register - 0x60 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - S4M0ADDR - S4M0ADDR - stream 4 memory 0 address - register - 0x64 - 0x20 - read-write - 0x00000000 - - - M0ADDR - Memory 0 address - 0 - 32 - - - - - S4M1ADDR - S4M1ADDR - stream 4 memory 1 address - register - 0x68 - 0x20 - read-write - 0x00000000 - - - M1ADDR - Memory 1 address (used in case of Double - buffer mode) - 0 - 32 - - - - - S4FCTRL - S4FCTRL - stream 4 FIFO control register - 0x6C - 0x20 - 0x00000021 - - - FERRIEN - FIFO error interrupt - enable - 7 - 1 - read-write - - - FSTS - FIFO status - 3 - 3 - read-only - - - FEN - FIFO mode enable - 2 - 1 - read-write - - - FTHSEL - FIFO threshold selection - 0 - 2 - read-write - - - - - S5CTRL - S5CTRL - stream 5 control - register - 0x70 - 0x20 - read-write - 0x00000000 - - - MBURST - Memory burst transmission - - 23 - 2 - - - PBURST - Peripheral burst transmission - - 21 - 2 - - - CM - Current memory (only in double buffer - mode) - 19 - 1 - - - DMM - Double memory mode - 18 - 1 - - - SPL - Stream priority level - 16 - 2 - - - PINCOS - Peripheral increment offset - size - 15 - 1 - - - MWIDTH - Memory data width - 13 - 2 - - - PWIDTH - Peripheral data width - 11 - 2 - - - MINCM - Memory increment mode - 10 - 1 - - - PINCM - Peripheral increment mode - 9 - 1 - - - LM - Loop mode - 8 - 1 - - - DTD - Data transfer direction - 6 - 2 - - - PFCTRL - Peripheral flow controller - 5 - 1 - - - FDTIEN - Full data transfer complete interrupt - enable - 4 - 1 - - - HDTIEN - Half data transfer interrupt - enable - 3 - 1 - - - DTERRIEN - Transfer error interrupt - enable - 2 - 1 - - - DMERRIEN - Direct mode error interrupt - enable - 1 - 1 - - - SEN - Stream enable / flag stream ready when - read low - 0 - 1 - - - - - S5DTCNT - S5DTCNT - stream 5 number of data - register - 0x74 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data items to - transfer - 0 - 16 - - - - - S5PADDR - S5PADDR - stream 5 peripheral address - register - 0x78 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - S5M0ADDR - S5M0ADDR - stream 5 memory 0 address - register - 0x7C - 0x20 - read-write - 0x00000000 - - - M0ADDR - Memory 0 address - 0 - 32 - - - - - S5M1ADDR - S5M1ADDR - stream 5 memory 1 address - register - 0x80 - 0x20 - read-write - 0x00000000 - - - M1ADDR - Memory 1 address (used in case of Double - buffer mode) - 0 - 32 - - - - - S5FCTRL - S5FCTRL - stream 5 FIFO control register - 0x84 - 0x20 - 0x00000021 - - - FERRIEN - FIFO error interrupt - enable - 7 - 1 - read-write - - - FSTS - FIFO status - 3 - 3 - read-only - - - FEN - FIFO mode enable - 2 - 1 - read-write - - - FTHSEL - FIFO threshold selection - 0 - 2 - read-write - - - - - S6CTRL - S6CTRL - stream 6 control - register - 0x88 - 0x20 - read-write - 0x00000000 - - - MBURST - Memory burst transmission - - 23 - 2 - - - PBURST - Peripheral burst transmission - - 21 - 2 - - - CM - Current memory (only in double buffer - mode) - 19 - 1 - - - DMM - Double memory mode - 18 - 1 - - - SPL - Stream priority level - 16 - 2 - - - PINCOS - Peripheral increment offset - size - 15 - 1 - - - MWIDTH - Memory data width - 13 - 2 - - - PWIDTH - Peripheral data width - 11 - 2 - - - MINCM - Memory increment mode - 10 - 1 - - - PINCM - Peripheral increment mode - 9 - 1 - - - LM - Loop mode - 8 - 1 - - - DTD - Data transfer direction - 6 - 2 - - - PFCTRL - Peripheral flow controller - 5 - 1 - - - FDTIEN - Full data transfer complete interrupt - enable - 4 - 1 - - - HDTIEN - Half data transfer interrupt - enable - 3 - 1 - - - DTERRIEN - Transfer error interrupt - enable - 2 - 1 - - - DMERRIEN - Direct mode error interrupt - enable - 1 - 1 - - - SEN - Stream enable / flag stream ready when - read low - 0 - 1 - - - - - S6DTCNT - S6DTCNT - stream 6 number of data - register - 0x8C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data items to - transfer - 0 - 16 - - - - - S6PADDR - S6PADDR - stream 6 peripheral address - register - 0x90 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - S6M0ADDR - S6M0ADDR - stream 6 memory 0 address - register - 0x94 - 0x20 - read-write - 0x00000000 - - - M0ADDR - Memory 0 address - 0 - 32 - - - - - S6M1ADDR - S6M1ADDR - stream 6 memory 1 address - register - 0x98 - 0x20 - read-write - 0x00000000 - - - M1ADDR - Memory 1 address (used in case of Double - buffer mode) - 0 - 32 - - - - - S6FCTRL - S6FCTRL - stream 6 FIFO control register - 0x9C - 0x20 - 0x00000021 - - - FERRIEN - FIFO error interrupt - enable - 7 - 1 - read-write - - - FSTS - FIFO status - 3 - 3 - read-only - - - FEN - FIFO mode enable - 2 - 1 - read-write - - - FTHSEL - FIFO threshold selection - 0 - 2 - read-write - - - - - S7CTRL - S7CTRL - stream 7 control - register - 0xA0 - 0x20 - read-write - 0x00000000 - - - MBURST - Memory burst transmission - - 23 - 2 - - - PBURST - Peripheral burst transmission - - 21 - 2 - - - CM - Current memory (only in double buffer - mode) - 19 - 1 - - - DMM - Double memory mode - 18 - 1 - - - SPL - Stream priority level - 16 - 2 - - - PINCOS - Peripheral increment offset - size - 15 - 1 - - - MWIDTH - Memory data width - 13 - 2 - - - PWIDTH - Peripheral data width - 11 - 2 - - - MINCM - Memory increment mode - 10 - 1 - - - PINCM - Peripheral increment mode - 9 - 1 - - - LM - Loop mode - 8 - 1 - - - DTD - Data transfer direction - 6 - 2 - - - PFCTRL - Peripheral flow controller - 5 - 1 - - - FDTIEN - Full data transfer complete interrupt - enable - 4 - 1 - - - HDTIEN - Half data transfer interrupt - enable - 3 - 1 - - - DTERRIEN - Transfer error interrupt - enable - 2 - 1 - - - DMERRIEN - Direct mode error interrupt - enable - 1 - 1 - - - SEN - Stream enable / flag stream ready when - read low - 0 - 1 - - - - - S7DTCNT - S7DTCNT - stream 7 number of data - register - 0xA4 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data items to - transfer - 0 - 16 - - - - - S7PADDR - S7PADDR - stream 7 peripheral address - register - 0xA8 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - S7M0ADDR - S7M0ADDR - stream 7 memory 0 address - register - 0xAC - 0x20 - read-write - 0x00000000 - - - M0ADDR - Memory 0 address - 0 - 32 - - - - - S7M1ADDR - S7M1ADDR - stream 7 memory 1 address - register - 0xB0 - 0x20 - read-write - 0x00000000 - - - M1ADDR - Memory 1 address (used in case of Double - buffer mode) - 0 - 32 - - - - - S7FCTRL - S7FCTRL - stream 7 FIFO control register - 0xB4 - 0x20 - 0x00000021 - - - FERRIEN - FIFO error interrupt - enable - 7 - 1 - read-write - - - FSTS - FIFO status - 3 - 3 - read-only - - - FEN - FIFO mode enable - 2 - 1 - read-write - - - FTHSEL - FIFO threshold selection - 0 - 2 - read-write - - - - - S8CTRL - S8CTRL - stream 8 control - register - 0xB8 - 0x20 - read-write - 0x00000000 - - - MBURST - Memory burst transmission - - 23 - 2 - - - PBURST - Peripheral burst transmission - - 21 - 2 - - - CM - Current memory (only in double buffer - mode) - 19 - 1 - - - DMM - Double memory mode - 18 - 1 - - - SPL - Stream priority level - 16 - 2 - - - PINCOS - Peripheral increment offset - size - 15 - 1 - - - MWIDTH - Memory data width - 13 - 2 - - - PWIDTH - Peripheral data width - 11 - 2 - - - MINCM - Memory increment mode - 10 - 1 - - - PINCM - Peripheral increment mode - 9 - 1 - - - LM - Loop mode - 8 - 1 - - - DTD - Data transfer direction - 6 - 2 - - - PFCTRL - Peripheral flow controller - 5 - 1 - - - FDTIEN - Full data transfer complete interrupt - enable - 4 - 1 - - - HDTIEN - Half data transfer interrupt - enable - 3 - 1 - - - DTERRIEN - Transfer error interrupt - enable - 2 - 1 - - - DMERRIEN - Direct mode error interrupt - enable - 1 - 1 - - - SEN - Stream enable / flag stream ready when - read low - 0 - 1 - - - - - S8DTCNT - S8DTCNT - stream 8 number of data - register - 0xBC - 0x20 - read-write - 0x00000000 - - - CNT - Number of data items to - transfer - 0 - 16 - - - - - S8PADDR - S8PADDR - stream 8 peripheral address - register - 0xC0 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - S8M0ADDR - S8M0ADDR - stream 8 memory 0 address - register - 0xC4 - 0x20 - read-write - 0x00000000 - - - M0ADDR - Memory 0 address - 0 - 32 - - - - - S8M1ADDR - S8M1ADDR - stream 8 memory 1 address - register - 0xC8 - 0x20 - read-write - 0x00000000 - - - M1ADDR - Memory 1 address (used in case of Double - buffer mode) - 0 - 32 - - - - - S8FCTRL - S8FCTRL - stream 8 FIFO control register - 0xCC - 0x20 - 0x00000021 - - - FERRIEN - FIFO error interrupt - enable - 7 - 1 - read-write - - - FSTS - FIFO status - 3 - 3 - read-only - - - FEN - FIFO mode enable - 2 - 1 - read-write - - - FTHSEL - FIFO threshold selection - 0 - 2 - read-write - - - - - LLCTRL - LLCTRL - DMA Link List Control Register - 0xD0 - 0x20 - 0x00000000 - - - S1LLEN - Stream 1 link list enable - 0 - 1 - read-write - - - S2LLEN - Stream 2 link list enable - 1 - 1 - read-write - - - S3LLEN - Stream 3 link list enable - 2 - 1 - read-write - - - S4LLEN - Stream 4 link list enable - 3 - 1 - read-write - - - S5LLEN - Stream 5 link list enable - 4 - 1 - read-write - - - S6LLEN - Stream 6 link list enable - 5 - 1 - read-write - - - S7LLEN - Stream 7 link list enable - 6 - 1 - read-write - - - S8LLEN - Stream 8 link list enable - 7 - 1 - read-write - - - - - S1LLP - S1LLP - Stream 1 Link List Pointer - 0xD4 - 0x20 - 0x00000000 - - - LLP - Link list pointer - 0 - 32 - read-write - - - - - S2LLP - S2LLP - Stream 2 Link List Pointer - 0xD8 - 0x20 - 0x00000000 - - - LLP - Link list pointer - 0 - 32 - read-write - - - - - S3LLP - S3LLP - Stream 3 Link List Pointer - 0xDC - 0x20 - 0x00000000 - - - LLP - Link list pointer - 0 - 32 - read-write - - - - - S4LLP - S4LLP - Stream 4 Link List Pointer - 0xE0 - 0x20 - 0x00000000 - - - LLP - Link list pointer - 0 - 32 - read-write - - - - - S5LLP - S5LLP - Stream 5 Link List Pointer - 0xE4 - 0x20 - 0x00000000 - - - LLP - Link list pointer - 0 - 32 - read-write - - - - - S6LLP - S6LLP - Stream 6 Link List Pointer - 0xE8 - 0x20 - 0x00000000 - - - LLP - Link list pointer - 0 - 32 - read-write - - - - - S7LLP - S7LLP - Stream 7 Link List Pointer - 0xEC - 0x20 - 0x00000000 - - - LLP - Link list pointer - 0 - 32 - read-write - - - - - S8LLP - S8LLP - Stream 8 Link List Pointer - 0xF0 - 0x20 - 0x00000000 - - - LLP - Link list pointer - 0 - 32 - read-write - - - - - S2DCTRL - S2DCTRL - EDMA 2D Transfer Control Register - 0xF4 - 0x20 - 0x00000000 - - - S1_2DEN - Stream 1 2D transfer enable - 0 - 1 - read-write - - - S2_2DEN - Stream 2 2D transfer enable - 1 - 1 - read-write - - - S3_2DEN - Stream 3 2D transfer enable - 2 - 1 - read-write - - - S4_2DEN - Stream 4 2D transfer enable - 3 - 1 - read-write - - - S5_2DEN - Stream 5 2D transfer enable - 4 - 1 - read-write - - - S6_2DEN - Stream 6 2D transfer enable - 5 - 1 - read-write - - - S7_2DEN - Stream 7 2D transfer enable - 6 - 1 - read-write - - - S8_2DEN - Stream 8 2D transfer enable - 7 - 1 - read-write - - - - - S1_2DCNT - S1_2DCNT - Stream 1 2D Transfer Count - 0xF8 - 0x20 - 0x00000000 - - - XCONUT - X dimension transfer count - 0 - 16 - read-write - - - YCONUT - Y dimension transfer count - 16 - 16 - read-write - - - - - S1_STRIDE - S1_STRIDE - Stream 1 2D Transfer Stride - 0xFC - 0x20 - 0x00000000 - - - SRCSTD - Source stride - 0 - 16 - read-write - - - DSTSTD - Destination stride - 16 - 16 - read-write - - - - - S2_2DCNT - S2_2DCNT - Stream 2 2D Transfer Count - 0x100 - 0x20 - 0x00000000 - - - XCONUT - X dimension transfer count - 0 - 16 - read-write - - - YCONUT - Y dimension transfer count - 16 - 16 - read-write - - - - - S2_STRIDE - S2_STRIDE - Stream 2 2D Transfer Stride - 0x104 - 0x20 - 0x00000000 - - - SRCSTD - Source stride - 0 - 16 - read-write - - - DSTSTD - Destination stride - 16 - 16 - read-write - - - - - S3_2DCNT - S3_2DCNT - Stream 3 2D Transfer Count - 0x108 - 0x20 - 0x00000000 - - - XCONUT - X dimension transfer count - 0 - 16 - read-write - - - YCONUT - Y dimension transfer count - 16 - 16 - read-write - - - - - S3_STRIDE - S3_STRIDE - Stream 3 2D Transfer Stride - 0x10C - 0x20 - 0x00000000 - - - SRCSTD - Source stride - 0 - 16 - read-write - - - DSTSTD - Destination stride - 16 - 16 - read-write - - - - - S4_2DCNT - S4_2DCNT - Stream 4 2D Transfer Count - 0x110 - 0x20 - 0x00000000 - - - XCONUT - X dimension transfer count - 0 - 16 - read-write - - - YCONUT - Y dimension transfer count - 16 - 16 - read-write - - - - - S4_STRIDE - S4_STRIDE - Stream 4 2D Transfer Stride - 0x114 - 0x20 - 0x00000000 - - - SRCSTD - Source stride - 0 - 16 - read-write - - - DSTSTD - Destination stride - 16 - 16 - read-write - - - - - S5_2DCNT - S5_2DCNT - Stream 5 2D Transfer Count - 0x118 - 0x20 - 0x00000000 - - - XCONUT - X dimension transfer count - 0 - 16 - read-write - - - YCONUT - Y dimension transfer count - 16 - 16 - read-write - - - - - S5_STRIDE - S5_STRIDE - Stream 5 2D Transfer Stride - 0x11C - 0x20 - 0x00000000 - - - SRCSTD - Source stride - 0 - 16 - read-write - - - DSTSTD - Destination stride - 16 - 16 - read-write - - - - - S6_2DCNT - S6_2DCNT - Stream 6 2D Transfer Count - 0x120 - 0x20 - 0x00000000 - - - XCONUT - X dimension transfer count - 0 - 16 - read-write - - - YCONUT - Y dimension transfer count - 16 - 16 - read-write - - - - - S6_STRIDE - S6_STRIDE - Stream 6 2D Transfer Stride - 0x124 - 0x20 - 0x00000000 - - - SRCSTD - Source stride - 0 - 16 - read-write - - - DSTSTD - Destination stride - 16 - 16 - read-write - - - - - S7_2DCNT - S7_2DCNT - Stream 7 2D Transfer Count - 0x128 - 0x20 - 0x00000000 - - - XCONUT - X dimension transfer count - 0 - 16 - read-write - - - YCONUT - Y dimension transfer count - 16 - 16 - read-write - - - - - S7_STRIDE - S7_STRIDE - Stream 7 2D Transfer Stride - 0x12C - 0x20 - 0x00000000 - - - SRCSTD - Source stride - 0 - 16 - read-write - - - DSTSTD - Destination stride - 16 - 16 - read-write - - - - - S8_2DCNT - S8_2DCNT - Stream 8 2D Transfer Count - 0x130 - 0x20 - 0x00000000 - - - XCONUT - X dimension transfer count - 0 - 16 - read-write - - - YCONUT - Y dimension transfer count - 16 - 16 - read-write - - - - - S8_STRIDE - S8_STRIDE - Stream 8 2D Transfer Stride - 0x134 - 0x20 - 0x00000000 - - - SRCSTD - Source stride - 0 - 16 - read-write - - - DSTSTD - Destination stride - 16 - 16 - read-write - - - - - SYNCEN - SYNCEN - Sync Enable - 0x138 - 0x20 - 0x00000000 - - - S1SYNC - Stream 1 sync enable - 0 - 1 - read-write - - - S2SYNC - Stream 2 sync enable - 1 - 1 - read-write - - - S3SYNC - Stream 3 sync enable - 2 - 1 - read-write - - - S4SYNC - Stream 4 sync enable - 3 - 1 - read-write - - - S5SYNC - Stream 5 sync enable - 4 - 1 - read-write - - - S6SYNC - Stream 6 sync enable - 5 - 1 - read-write - - - S7SYNC - Stream 7 sync enable - 6 - 1 - read-write - - - S8SYNC - Stream 8 sync enable - 7 - 1 - read-write - - - - - MUXSEL - MUXSEL - EDMA MUX Table Selection - 0x13C - 0x20 - 0x00000000 - - - TBL_SEL - Multiplexer Table Select - 0 - 1 - read-write - - - - - MUXS1CTRL - MUXS1CTRL - Stream 1 Configuration Register - 0x140 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization select - 24 - 5 - read-write - - - - - MUXS2CTRL - MUXS2CTRL - Stream 2 Configuration Register - 0x144 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization select - 24 - 5 - read-write - - - - - MUXS3CTRL - MUXS3CTRL - Stream 3 Configuration Register - 0x148 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization select - 24 - 5 - read-write - - - - - MUXS4CTRL - MUXS4CTRL - Stream 4 Configuration Register - 0x14C - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization select - 24 - 5 - read-write - - - - - MUXS5CTRL - MUXS5CTRL - Stream x Configuration Register - 0x150 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization select - 24 - 5 - read-write - - - - - MUXS6CTRL - MUXS6CTRL - Stream 6 Configuration Register - 0x154 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization select - 24 - 5 - read-write - - - - - MUXS7CTRL - MUXS7CTRL - Stream 7 Configuration Register - 0x158 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization select - 24 - 5 - read-write - - - - - MUXS8CTRL - MUXS8CTRL - Stream 8 Configuration Register - 0x15C - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization select - 24 - 5 - read-write - - - - - MUXG1CTRL - MUXG1CTRL - Generator 1 Configuration Register - 0x160 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG2CTRL - MUXG2CTRL - Generator 2 Configuration Register - 0x164 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG3CTRL - MUXG3CTRL - Generator 3 Configuration Register - 0x168 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG4CTRL - MUXG4CTRL - Generator 4 Configuration Register - 0x16C - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXSYNCSTS - MUXSYNCSTS - Channel Interrupt Status Register - 0x170 - 0x20 - 0x00000000 - - - SYNCOVF1 - Synchronizaton overrun interrupt flag - 0 - 1 - read-only - - - SYNCOVF2 - Synchronizaton overrun interrupt flag - 1 - 1 - read-only - - - SYNCOVF3 - Synchronizaton overrun interrupt flag - 2 - 1 - read-only - - - SYNCOVF4 - Synchronizaton overrun interrupt flag - 3 - 1 - read-only - - - SYNCOVF5 - Synchronizaton overrun interrupt flag - 4 - 1 - read-only - - - SYNCOVF6 - Synchronizaton overrun interrupt flag - 5 - 1 - read-only - - - SYNCOVF7 - Synchronizaton overrun interrupt flag - 6 - 1 - read-only - - - SYNCOVF8 - Synchronizaton overrun interrupt flag - 7 - 1 - read-only - - - - - MUXSYNCCLR - MUXSYNCCLR - Channel Interrupt Clear Flag Register - 0x174 - 0x20 - 0x00000000 - - - SYNCOVFC1 - Clear synchronizaton overrun interrupt flag - 0 - 1 - read-write - - - SYNCOVFC2 - Clear synchronizaton overrun interrupt flag - 1 - 1 - read-write - - - SYNCOVFC3 - Clear synchronizaton overrun interrupt flag - 2 - 1 - read-write - - - SYNCOVFC4 - Clear synchronizaton overrun interrupt flag - 3 - 1 - read-write - - - SYNCOVFC5 - Clear synchronizaton overrun interrupt flag - 4 - 1 - read-write - - - SYNCOVFC6 - Clear synchronizaton overrun interrupt flag - 5 - 1 - read-write - - - SYNCOVFC7 - Clear synchronizaton overrun interrupt flag - 6 - 1 - read-write - - - SYNCOVFC8 - Clear synchronizaton overrun interrupt flag - 7 - 1 - read-write - - - - - MUXGSTS - MUXGSTS - Generator Interrupt Status Register - 0x178 - 0x20 - 0x00000000 - - - TRGOVF1 - Trigger overrun interrupt flag - 0 - 1 - read-write - - - TRGOVF2 - Trigger overrun interrupt flag - 1 - 1 - read-write - - - TRGOVF3 - Trigger overrun interrupt flag - 2 - 1 - read-write - - - TRGOVF4 - Trigger overrun interrupt flag - 3 - 1 - read-write - - - - - MUXGCLR - MUXGCLR - Generator Interrupt Clear Flag Register - 0x17C - 0x20 - 0x00000000 - - - TRGOVFC1 - Clear trigger overrun interrupt flag - 0 - 1 - read-write - - - - TRGOVFC2 - Clear trigger overrun interrupt flag - 1 - 1 - read-write - - - TRGOVFC3 - Clear trigger overrun interrupt flag - 2 - 1 - read-write - - - TRGOVFC4 - Clear trigger overrun interrupt flag - 3 - 1 - read-write - - - - - - - DMA1 - DMA controller - DMA - 0x40026400 - - 0x0 - 0x200 - registers - - - DMA1_Channel1 - DMA1 Channel1 global interrupt - 56 - - - DMA1_Channel2 - DMA1 Channel2 global interrupt - 57 - - - DMA1_Channel3 - DMA1 Channel3 global interrupt - 58 - - - DMA1_Channel4 - DMA1 Channel4 global interrupt - 59 - - - DMA1_Channel5 - DMA1 Channel5 global interrupt - 60 - - - DMA1_Channel6 - DMA1 Channel6 global interrupt - 68 - - - DMA1_Channel7 - DMA1 Channel7 global interrupt - 69 - - - - STS - STS - DMA interrupt status register - (DMA_STS) - 0x0 - 0x20 - read-only - 0x00000000 - - - GF1 - Channel 1 Global event flag - 0 - 1 - - - FDTF1 - Channel 1 full data transfer event flag - 1 - 1 - - - HDTF1 - Channel 1 half data transfer event flag - 2 - 1 - - - DTERRF1 - Channel 1 data transfer error event flag - 3 - 1 - - - GF2 - Channel 2 Global event flag - 4 - 1 - - - FDTF2 - Channel 2 full data transfer event flag - 5 - 1 - - - HDTF2 - Channel 2 half data transfer event flag - 6 - 1 - - - DTERRF2 - Channel 2 data transfer error event flag - 7 - 1 - - - GF3 - Channel 3 Global event flag - 8 - 1 - - - FDTF3 - Channel 3 full data transfer event flag - 9 - 1 - - - HDTF3 - Channel 3 half data transfer event flag - 10 - 1 - - - DTERRF3 - Channel 3 data transfer error event flag - 11 - 1 - - - GF4 - Channel 4 Global event flag - 12 - 1 - - - FDTF4 - Channel 4 full data transfer event flag - 13 - 1 - - - HDTF4 - Channel 4 half data transfer event flag - 14 - 1 - - - DTERRF4 - Channel 4 data transfer error event flag - 15 - 1 - - - GF5 - Channel 5 Global event flag - 16 - 1 - - - FDTF5 - Channel 5 full data transfer event flag - 17 - 1 - - - HDTF5 - Channel 5 half data transfer event flag - 18 - 1 - - - DTERRF5 - Channel 5 data transfer error event flag - 19 - 1 - - - GF6 - Channel 6 Global event flag - 20 - 1 - - - FDTF6 - Channel 6 full data transfer event flag - 21 - 1 - - - HDTF6 - Channel 6 half data transfer event flag - 22 - 1 - - - DTERRF6 - Channel 6 data transfer error event flag - 23 - 1 - - - GF7 - Channel 7 Global event flag - 24 - 1 - - - FDTF7 - Channel 7 full data transfer event flag - 25 - 1 - - - HDTF7 - Channel 7 half data transfer event flag - 26 - 1 - - - DTERRF7 - Channel 7 data transfer error event flag - 27 - 1 - - - - - CLR - CLR - DMA interrupt flag clear register - (DMA_CLR) - 0x4 - 0x20 - read-write - 0x00000000 - - - GFC1 - Channel 1 Global flag clear - 0 - 1 - - - GFC2 - Channel 2 Global flag clear - 4 - 1 - - - GFC3 - Channel 3 Global flag clear - 8 - 1 - - - GFC4 - Channel 4 Global flag clear - 12 - 1 - - - GFC5 - Channel 5 Global flag clear - 16 - 1 - - - GFC6 - Channel 6 Global flag clear - 20 - 1 - - - GFC7 - Channel 7 Global flag clear - 24 - 1 - - - FDTFC1 - Channel 1 full data transfer flag clear - 1 - 1 - - - FDTFC2 - Channel 2 full data transfer flag clear - 5 - 1 - - - FDTFC3 - Channel 3 full data transfer flag clear - 9 - 1 - - - FDTFC4 - Channel 4 full data transfer flag clear - 13 - 1 - - - FDTFC5 - Channel 5 full data transfer flag clear - 17 - 1 - - - FDTFC6 - Channel 6 full data transfer flag clear - 21 - 1 - - - FDTFC7 - Channel 7 full data transfer flag clear - 25 - 1 - - - HDTFC1 - Channel 1 half data transfer flag clear - 2 - 1 - - - HDTFC2 - Channel 2 half data transfer flag clear - 6 - 1 - - - HDTFC3 - Channel 3 half data transfer flag clear - 10 - 1 - - - HDTFC4 - Channel 4 half data transfer flag clear - 14 - 1 - - - HDTFC5 - Channel 5 half data transfer flag clear - 18 - 1 - - - HDTFC6 - Channel 6 half data transfer flag clear - 22 - 1 - - - HDTFC7 - Channel 7 half data transfer flag clear - 26 - 1 - - - DTERRFC1 - Channel 1 data transfer error flag clear - 3 - 1 - - - DTERRFC2 - Channel 2 data transfer error flag clear - 7 - 1 - - - DTERRFC3 - Channel 3 data transfer error flag clear - 11 - 1 - - - DTERRFC4 - Channel 4 data transfer error flag clear - 15 - 1 - - - DTERRFC5 - Channel 5 data transfer error flag clear - 19 - 1 - - - DTERRFC6 - Channel 6 data transfer error flag clear - 23 - 1 - - - DTERRFC7 - Channel 7 data transfer error flag clear - 27 - 1 - - - - - C1CTRL - C1CTRL - DMA channel configuration register(DMA_C1CTRL) - 0x8 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C1DTCNT - C1DTCNT - DMA channel 1 number of data to transfer register - 0xC - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C1PADDR - C1PADDR - DMA channel 1 peripheral base address register - 0x10 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C1MADDR - C1MADDR - DMA channel 1 memory base address register - 0x14 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C2CTRL - C2CTRL - DMA channel configuration register (DMA_C2CTRL) - 0x1C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C2DTCNT - C2DTCNT - DMA channel 2 number of data to transferregister - 0x20 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C2PADDR - C2PADDR - DMA channel 2 peripheral base address register - 0x24 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C2MADDR - C2MADDR - DMA channel 2 memory base address register - 0x28 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C3CTRL - C3CTRL - DMA channel configuration register (DMA_C3CTRL) - 0x30 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C3DTCNT - C3DTCNT - DMA channel 3 number of data to transfer register - 0x34 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C3PADDR - C3PADDR - DMA channel 3 peripheral base address register - 0x38 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C3MADDR - C3MADDR - DMA channel 3 memory base address register - 0x3C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C4CTRL - C4CTRL - DMA channel configuration register (DMA_C4CTRL) - 0x44 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C4DTCNT - C4DTCNT - DMA channel 4 number of data to transfer register - 0x48 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C4PADDR - C4PADDR - DMA channel 4 peripheral base address register - 0x4C - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C4MADDR - C4MADDR - DMA channel 4 memory base address register - 0x50 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C5CTRL - C5CTRL - DMA channel configuration register (DMA_C5CTRL) - 0x58 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C5DTCNT - C5DTCNT - DMA channel 5 number of data to transfer register - 0x5C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C5PADDR - C5PADDR - DMA channel 5 peripheral base address register - 0x60 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C5MADDR - C5MADDR - DMA channel 5 memory base address register - 0x64 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C6CTRL - C6CTRL - DMA channel configuration register(DMA_C6CTRL) - 0x6C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C6DTCNT - C6DTCNT - DMA channel 6 number of data to transfer register - 0x70 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C6PADDR - C6PADDR - DMA channel 6 peripheral address base register - 0x74 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C6MADDR - C6MADDR - DMA channel 6 memory address base register - 0x78 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C7CTRL - C7CTRL - DMA channel configuration register(DMA_C7CTRL) - 0x80 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C7DTCNT - C7DTCNT - DMA channel 7 number of data to transfer register - 0x84 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C7PADDR - C7PADDR - DMA channel 7 peripheral base address register - 0x88 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C7MADDR - C7MADDR - DMA channel 7 memory base address register - 0x8C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - DMA_MUXSEL - DMA_MUXSEL - DMAMUX Table Selection - 0x100 - 0x20 - 0x00000000 - - - TBL_SEL - Multiplexer Table Select - 0 - 1 - read-write - - - - - MUXC1CTRL - MUXC1CTRL - Channel 1 Configuration Register - 0x104 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC2CTRL - MUXC2CTRL - Channel 2 Configuration Register - 0x108 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC3CTRL - MUXC3CTRL - Channel 3 Configuration Register - 0x10C - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC4CTRL - MUXC4CTRL - Channel 4 Configuration Register - 0x110 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC5CTRL - MUXC5CTRL - Channel 5 Configuration Register - 0x114 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC6CTRL - MUXC6CTRL - Channel 6 Configuration Register - 0x118 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC7CTRL - MUXC7CTRL - Channel 7 Configuration Register - 0x11C - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXG1CTRL - MUXG1CTRL - Generator 1 Configuration Register - 0x120 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG2CTRL - MUXG2CTRL - Generator 2 Configuration Register - 0x124 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG3CTRL - MUXG3CTRL - Generator 3 Configuration Register - 0x128 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG4CTRL - MUXG4CTRL - Generator 4 Configuration Register - 0x12C - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXSYNCSTS - MUXSYNCSTS - Channel Interrupt Status Register - 0x130 - 0x20 - 0x00000000 - - - SYNCOVF1 - Synchronizaton overrun interrupt flag - 0 - 1 - read-only - - - SYNCOVF2 - Synchronizaton overrun interrupt flag - 1 - 1 - read-only - - - SYNCOVF3 - Synchronizaton overrun interrupt flag - 2 - 1 - read-only - - - SYNCOVF4 - Synchronizaton overrun interrupt flag - 3 - 1 - read-only - - - SYNCOVF5 - Synchronizaton overrun interrupt flag - 4 - 1 - read-only - - - SYNCOVF6 - Synchronizaton overrun interrupt flag - 5 - 1 - read-only - - - SYNCOVF7 - Synchronizaton overrun interrupt flag - 6 - 1 - read-only - - - - - MUXSYNCCLR - MUXSYNCCLR - Channel Interrupt Clear Flag Register - 0x134 - 0x20 - 0x00000000 - - - SYNCOVFC1 - Clear synchronizaton overrun interrupt flag - 0 - 1 - read-write - - - SYNCOVFC2 - Clear synchronizaton overrun interrupt flag - 1 - 1 - read-write - - - SYNCOVFC3 - Clear synchronizaton overrun interrupt flag - 2 - 1 - read-write - - - SYNCOVFC4 - Clear synchronizaton overrun interrupt flag - 3 - 1 - read-write - - - SYNCOVFC5 - Clear synchronizaton overrun interrupt flag - 4 - 1 - read-write - - - SYNCOVFC6 - Clear synchronizaton overrun interrupt flag - 5 - 1 - read-write - - - SYNCOVFC7 - Clear synchronizaton overrun interrupt flag - 6 - 1 - read-write - - - - - MUXGSTS - MUXGSTS - Generator Interrupt Status Register - 0x138 - 0x20 - 0x00000000 - - - TRGOVF1 - Trigger overrun interrupt flag - 0 - 1 - read-write - - - TRGOVF2 - Trigger overrun interrupt flag - 1 - 1 - read-write - - - TRGOVF3 - Trigger overrun interrupt flag - 2 - 1 - read-write - - - TRGOVF4 - Trigger overrun interrupt flag - 3 - 1 - read-write - - - - - MUXGCLR - MUXGCLR - Generator Interrupt Clear Flag Register - 0x13C - 0x20 - 0x00000000 - - - TRGOVFC1 - Clear trigger overrun interrupt flag - 0 - 1 - read-write - - - TRGOVFC2 - Clear trigger overrun interrupt flag - 1 - 1 - read-write - - - TRGOVFC3 - Clear trigger overrun interrupt flag - 2 - 1 - read-write - - - TRGOVFC4 - Clear trigger overrun interrupt flag - 3 - 1 - read-write - - - - - - - DMA2 - 0x40026600 - - - SDIO1 - Secure digital input/output - interface - SDIO - 0x4002C400 - - 0x0 - 0x400 - registers - - - SDIO1 - SDIO1 global interrupt - 49 - - - - PWRCTRL - PWRCTRL - Bits 1:0 = PWRCTRL: Power supply control - bits - 0x0 - 0x20 - read-write - 0x00000000 - - - PS - Power switch - 0 - 2 - - - - - CLKCTRL - CLKCTRL - SD clock control register - (SDIO_CLKCTRL) - 0x4 - 0x20 - read-write - 0x00000000 - - - CLKDIV - Clock division - 0 - 8 - - - CLKOEN - Clock output enable - 8 - 1 - - - PWRSVEN - Power saving mode enable - 9 - 1 - - - BYPSEN - Clock divider bypass enable - bit - 10 - 1 - - - BUSWS - Bus width selection - 11 - 2 - - - CLKEDS - SDIO_CK edge selection bit - 13 - 1 - - - HFCEN - Hardware flow control enable - 14 - 1 - - - CLKDIV98 - Clock divide factor bit9 and bit8 - 15 - 2 - - - - - ARGU - ARGU - Bits 31:0 = : Command argument - 0x8 - 0x20 - read-write - 0x00000000 - - - ARGU - Command argument - 0 - 32 - - - - - CMDCTRL - CMDCTRL - SDIO command control register - (SDIO_CMDCTRL) - 0xC - 0x20 - read-write - 0x00000000 - - - CMDIDX - CMDIDX - 0 - 6 - - - RSPWT - Wait for response - 6 - 2 - - - INTWT - CCSM wait for interrupt - 8 - 1 - - - PNDWT - CCSM wait for end of transfer - 9 - 1 - - - CCSMEN - Command channel state machine - 10 - 1 - - - IOSUSP - SD I/O suspend command - 11 - 1 - - - - - RSPCMD - RSPCMD - SDIO command register - 0x10 - 0x20 - read-only - 0x00000000 - - - RSPCMD - RSPCMD - 0 - 6 - - - - - RSP1 - RSP1 - Bits 31:0 = CARDSTATUS1 - 0x14 - 0x20 - read-only - 0x00000000 - - - CARDSTS1 - CARDSTATUS1 - 0 - 32 - - - - - RSP2 - RSP2 - Bits 31:0 = CARDSTATUS2 - 0x18 - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS2 - 0 - 32 - - - - - RSP3 - RSP3 - Bits 31:0 = CARDSTATUS3 - 0x1C - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS3 - 0 - 32 - - - - - RSP4 - RSP4 - Bits 31:0 = CARDSTATUS4 - 0x20 - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS4 - 0 - 32 - - - - - DTTMR - DTTMR - Bits 31:0 = TIMEOUT: Data timeout - period - 0x24 - 0x20 - read-write - 0x00000000 - - - TIMEOUT - Data timeout period - 0 - 32 - - - - - DTLEN - DTLEN - Bits 24:0 = DATALENGTH: Data length - value - 0x28 - 0x20 - read-write - 0x00000000 - - - DTLEN - Data length value - 0 - 25 - - - - - DTCTRL - DTCTRL - SDIO data control register - (SDIO_DCTRL) - 0x2C - 0x20 - read-write - 0x00000000 - - - TFREN - DTEN - 0 - 1 - - - TFRDIR - DTDIR - 1 - 1 - - - TFRMODE - DTMODE - 2 - 1 - - - DMAEN - DMAEN - 3 - 1 - - - BLKSIZE - DBLOCKSIZE - 4 - 4 - - - RDWTSTART - PWSTART - 8 - 1 - - - RDWTSTOP - PWSTOP - 9 - 1 - - - RDWTMODE - RWMOD - 10 - 1 - - - IOEN - SD I/O function enable - 11 - 1 - - - - - DTCNT - DTCNT - Bits 24:0 = DATACOUNT: Data count - value - 0x30 - 0x20 - read-only - 0x00000000 - - - CNT - Data count value - 0 - 25 - - - - - STS - STS - SDIO status register - (SDIO_STA) - 0x34 - 0x20 - read-only - 0x00000000 - - - CMDFAIL - Command crc fail - 0 - 1 - - - DTFAIL - Data crc fail - 1 - 1 - - - CMDTIMEOUT - Command timeout - 2 - 1 - - - DTTIMEOUT - Data timeout - 3 - 1 - - - TXERRU - Tx under run error - 4 - 1 - - - RXERRO - Rx over run error - 5 - 1 - - - CMDRSPCMPL - Command response complete - 6 - 1 - - - CMDCMPL - Command sent - 7 - 1 - - - DTCMPL - Data sent - 8 - 1 - - - SBITERR - Start bit error - 9 - 1 - - - DTBLKCMPL - Data block sent - 10 - 1 - - - DOCMD - Command transfer in progress - 11 - 1 - - - DOTX - Data transmit in progress - 12 - 1 - - - DORX - Data receive in progress - 13 - 1 - - - TXBUFH - Tx buffer half empty - 14 - 1 - - - RXBUFH - Rx buffer half empty - 15 - 1 - - - TXBUFF - Tx buffer full - 16 - 1 - - - RXBUFF - Rx buffer full - 17 - 1 - - - TXBUFE - Tx buffer empty - 18 - 1 - - - RXBUFE - Rx buffer empty - 19 - 1 - - - TXBUF - Tx data vaild - 20 - 1 - - - RXBUF - Rx data vaild - 21 - 1 - - - IOIF - SD I/O interrupt - 22 - 1 - - - - - INTCLR - INTCLR - SDIO interrupt clear register - (SDIO_INTCLR) - 0x38 - 0x20 - read-write - 0x00000000 - - - CMDFAIL - Command crc fail flag clear - 0 - 1 - - - DTFAIL - Data crc fail flag clear - 1 - 1 - - - CMDTIMEOUT - Command timeout flag clear - 2 - 1 - - - DTTIMEOUT - Data timeout flag clear - 3 - 1 - - - TXERRU - Tx under run error flag clear - 4 - 1 - - - RXERRU - Rx over run error flag clear - 5 - 1 - - - CMDRSPCMPL - Command response complete flag clear - 6 - 1 - - - CMDCMPL - Command sent flag clear - 7 - 1 - - - DTCMPL - Data sent flag clear - 8 - 1 - - - SBITERR - Start bit error flag clear - 9 - 1 - - - DTBLKCMPL - Data block sent clear - 10 - 1 - - - IOIF - SD I/O interrupt flag clear - 22 - 1 - - - - - INTEN - INTEN - SDIO mask register (SDIO_MASK) - 0x3C - 0x20 - read-write - 0x00000000 - - - CMDFAILIEN - Command crc fail interrupt enable - 0 - 1 - - - DTFAILIEN - Data crc fail interrupt enable - 1 - 1 - - - CMDTIMEOUTIEN - Command timeout interrupt enable - 2 - 1 - - - DTTIMEOUTIEN - Data timeout interrupt enable - 3 - 1 - - - TXERRUIEN - Tx under run interrupt enable - 4 - 1 - - - RXERRUIEN - Rx over run interrupt enable - 5 - 1 - - - CMDRSPCMPLIEN - Command response complete interrupt enable - 6 - 1 - - - CMDCMPLIEN - Command sent complete interrupt enable - 7 - 1 - - - DTCMPLIEN - Data sent complete interrupt enable - 8 - 1 - - - SBITERRIEN - Start bit error interrupt enable - 9 - 1 - - - DTBLKCMPLIEN - Data block sent complete interrupt enable - 10 - 1 - - - DOCMDIEN - Command acting interrupt enable - 11 - 1 - - - DOTXIEN - Data transmit acting interrupt enable - 12 - 1 - - - DORXIEN - Data receive acting interrupt enable - 13 - 1 - - - TXBUFHIEN - Tx buffer half empty interrupt enable - 14 - 1 - - - RXBUFHIEN - Rx buffer half empty interrupt enable - 15 - 1 - - - TXBUFFIEN - Tx buffer full interrupt enable - 16 - 1 - - - RXBUFFIEN - Rx buffer full interrupt enable - 17 - 1 - - - TXBUFEIEN - Tx buffer empty interrupt enable - 18 - 1 - - - RXBUFEIEN - Rx buffer empty interrupt enable - 19 - 1 - - - TXBUFIEN - Tx buffer data vaild interrupt enable - 20 - 1 - - - RXBUFIEN - Rx buffer data vaild interrupt enable - 21 - 1 - - - IOIFIEN - SD I/O interrupt enable - 22 - 1 - - - - - BUFCNT - BUFCNT - Bits 23:0 = BUFCOUNT: Remaining number of - words to be written to or read from the - FIFO - 0x48 - 0x20 - read-only - 0x00000000 - - - CNT - FIF0COUNT - 0 - 24 - - - - - BUF - BUF - bits 31:0 = Buffer Data: Receive and transmit - buffer data - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - Buffer data - 0 - 32 - - - - - - - SDIO2 - 0x50061000 - - SDIO2 - SDIO2 global interrupt - 102 - - - - ERTC - Real-time clock - ERTC - 0x40002800 - - 0x0 - 0x400 - registers - - - - TIME - TIME - time register - 0x0 - 0x20 - read-write - 0x00000000 - - - AMPM - AM/PM notation - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - DATE - DATE - date register - 0x4 - 0x20 - read-write - 0x00002101 - - - YT - Year tens - 20 - 4 - - - YU - Year units - 16 - 4 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - CTRL - CTRL - control register - 0x8 - 0x20 - read-write - 0x00000000 - - - CALOEN - Calibration output enable - 23 - 1 - - - OUTSEL - Output source selection - 21 - 2 - - - OUTP - Output polarity - 20 - 1 - - - CALOSEL - Calibration output selection - 19 - 1 - - - BPR - Battery power domain data register - 18 - 1 - - - DEC1H - Decrease 1 hour - 17 - 1 - - - ADD1H - Add 1 hour - 16 - 1 - - - TSIEN - Timestamp interrupt enable - 15 - 1 - - - WATIEN - Wakeup timer interrupt enable - 14 - 1 - - - ALBIEN - Alarm B interrupt enable - 13 - 1 - - - ALAIEN - Alarm A interrupt enable - 12 - 1 - - - TSEN - Timestamp enable - 11 - 1 - - - WATEN - Wakeup timer enable - 10 - 1 - - - ALBEN - Alarm B enable - 9 - 1 - - - ALAEN - Alarm A enable - 8 - 1 - - - CCALEN - Coarse calibration enable - 7 - 1 - - - HM - Hour mode - 6 - 1 - - - DREN - Date/time register direct read enable - 5 - 1 - - - RCDEN - Reference clock detection enable - 4 - 1 - - - TSEDG - Timestamp trigger edge - 3 - 1 - - - WATCLK - Wakeup timer clock selection - 0 - 3 - - - - - STS - STS - initialization and status - register - 0xC - 0x20 - 0x00000007 - - - ALAWF - Alarm A register allows write flag - 0 - 1 - read-only - - - ALBWF - Alarm B register allows write flag - 1 - 1 - read-only - - - WATWF - Wakeup timer register allows write flag - 2 - 1 - read-only - - - TADJF - Time adjustment flag - 3 - 1 - read-write - - - INITF - Calendar initialization flag - 4 - 1 - read-only - - - UPDF - Calendar update flag - 5 - 1 - read-write - - - IMF - Enter initialization mode flag - 6 - 1 - read-only - - - IMEN - Initialization mode enable - 7 - 1 - read-write - - - ALAF - Alarm A flag - 8 - 1 - read-write - - - ALBF - Alarm B flag - 9 - 1 - read-write - - - WATF - Wakeup timer flag - 10 - 1 - read-write - - - TSF - Timestamp flag - 11 - 1 - read-write - - - TSOF - Timestamp overflow flag - 12 - 1 - read-write - - - TP1F - Tamper detection 1 flag - 13 - 1 - read-write - - - TP2F - Tamper detection 2 flag - 14 - 1 - read-write - - - CALUPDF - Calibration value update completed flag - 16 - 1 - read-only - - - - - DIV - DIV - Diveder register - 0x10 - 0x20 - read-write - 0x007F00FF - - - DIVA - Diveder A - 16 - 7 - - - DIVB - Diveder B - 0 - 15 - - - - - WAT - WAT - Wakeup timer register - 0x14 - 0x20 - read-write - 0x0000FFFF - - - VAL - Wakeup timer reload value - 0 - 16 - - - - - CCAL - CCAL - Calibration register - 0x18 - 0x20 - read-write - 0x00000000 - - - CALDIR - Calibration direction - 7 - 1 - - - CALVAL - Calibration value - 0 - 5 - - - - - ALA - ALA - Alarm A register - 0x1C - 0x20 - read-write - 0x00000000 - - - MASK4 - Date/week mask - 31 - 1 - - - WKSEL - Date/week mode select - 30 - 1 - - - DT - Date tens - 28 - 2 - - - DU - Date units - 24 - 4 - - - MASK3 - Hours mask - 23 - 1 - - - AMPM - AM/PM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MASK2 - Minutes mask - 15 - 1 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - MASK1 - Seconds mask - 7 - 1 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - ALB - ALB - Alarm B register - 0x20 - 0x20 - read-write - 0x00000000 - - - MASK4 - Date/week mask - 31 - 1 - - - WKSEL - Date/week mode select - 30 - 1 - - - DT - Date tens - 28 - 2 - - - DU - Date units - 24 - 4 - - - MASK3 - Hours mask - 23 - 1 - - - AMPM - AM/PM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MASK2 - Minutes mask - 15 - 1 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - MASK1 - Seconds mask - 7 - 1 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - WP - WP - write protection register - 0x24 - 0x20 - write-only - 0x00000000 - - - CMD - Command register - 0 - 8 - - - - - SBS - SBS - sub second register - 0x28 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - TADJ - TADJ - time adjust register - 0x2C - 0x20 - write-only - 0x00000000 - - - ADD1S - Add 1 second - 31 - 1 - - - DECSBS - Decrease sub-second value - 0 - 15 - - - - - TSTM - TSTM - time stamp time register - 0x30 - 0x20 - read-only - 0x00000000 - - - AMPM - AMPM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - TSDT - TSDT - timestamp date register - 0x34 - 0x20 - read-only - 0x00000000 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - TSSBS - TSSBS - timestamp sub second register - 0x38 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - SCAL - SCAL - calibration register - 0x3C - 0x20 - read-write - 0x00000000 - - - ADD - Add ERTC clock - 15 - 1 - - - CAL8 - 8-second calibration period - 14 - 1 - - - CAL16 - 16 second calibration period - 13 - 1 - - - DEC - Decrease ERTC clock - 0 - 9 - - - - - TAMP - TAMP - tamper and alternate function configuration - register - 0x40 - 0x20 - read-write - 0x00000000 - - - OUTTYPE - Output type - 18 - 1 - - - TSPIN - Time stamp detection pin selection - 17 - 1 - - - TP1PIN - Tamper detection pin selection - 16 - 1 - - - TPPU - Tamper detection pull-up - 15 - 1 - - - TPPR - Tamper detection pre-charge time - 13 - 2 - - - TPFLT - Tamper detection filter time - 11 - 2 - - - TPFREQ - Tamper detection frequency - 8 - 3 - - - TPTSEN - Tamper detection timestamp enable - 7 - 1 - - - TP2EDG - Tamper detection 2 valid edge - 4 - 1 - - - TP2EN - Tamper detection 2 enable - 3 - 1 - - - TPIEN - Tamper detection interrupt enable - 2 - 1 - - - TP1EDG - Tamper detection 1 valid edge - 1 - 1 - - - TP1EN - Tamper detection 1 enable - 0 - 1 - - - - - ALASBS - ALASBS - alarm A sub second register - 0x44 - 0x20 - read-write - 0x00000000 - - - SBSMSK - Sub-second mask - 24 - 4 - - - SBS - Sub-seconds value - 0 - 15 - - - - - ALBSBS - ALBSBS - alarm B sub second register - 0x48 - 0x20 - read-write - 0x00000000 - - - SBSMSK - Sub-second mask - 24 - 4 - - - SBS - Sub-seconds value - 0 - 15 - - - - - BPR1DT - BPR1DT - Battery powered domain register - 0x50 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR2DT - BPR2DT - Battery powered domain register - 0x54 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR3DT - BPR3DT - Battery powered domain register - 0x58 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR4DT - BPR4DT - Battery powered domain register - 0x5C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR5DT - BPR5DT - Battery powered domain register - 0x60 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR6DT - BPR6DT - Battery powered domain register - 0x64 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR7DT - BPR7DT - Battery powered domain register - 0x68 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR8DT - BPR8DT - Battery powered domain register - 0x6C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR9DT - BPR9DT - Battery powered domain register - 0x70 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR10DT - BPR10DT - Battery powered domain register - 0x74 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR11DT - BPR11DT - Battery powered domain register - 0x78 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR12DT - BPR12DT - Battery powered domain register - 0x7C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR13DT - BPR13DT - Battery powered domain register - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR14DT - BPR14DT - Battery powered domain register - 0x84 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR15DT - BPR15DT - Battery powered domain register - 0x88 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR16DT - BPR16DT - Battery powered domain register - 0x8C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR17DT - BPR17DT - Battery powered domain register - 0x90 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR18DT - BPR18DT - Battery powered domain register - 0x94 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR19DT - BPR19DT - Battery powered domain register - 0x98 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR20DT - BPR20DT - Battery powered domain register - 0x9C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - - - WDT - Watchdog - WDT - 0x40003000 - - 0x0 - 0x400 - registers - - - - CMD - CMD - Command register - 0x0 - 0x20 - write-only - 0x00000000 - - - CMD - Command register - 0 - 16 - - - - - DIV - DIV - Division register - 0x4 - 0x20 - read-write - 0x00000000 - - - DIV - Division divider - 0 - 3 - - - - - RLD - RLD - Reload register - 0x8 - 0x20 - read-write - 0x00000FFF - - - RLD - Reload value - 0 - 12 - - - - - STS - STS - Status register - 0xC - 0x20 - read-only - 0x00000000 - - - DIVF - Division value update complete flag - 0 - 1 - - - RLDF - Reload value update complete flag - 1 - 1 - - - WINF - Window value update complete flag - 2 - 1 - - - - - WIN - WIN - Window register - 0x10 - 0x20 - read-write - 0x00000FFF - - - WIN - Window value - 0 - 12 - - - - - - - WWDT - Window watchdog - WWDT - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDT - Window Watchdog interrupt - 0 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - read-write - 0x0000007F - - - CNT - Decrement counter - 0 - 7 - - - WWDTEN - Window watchdog enable - 7 - 1 - - - - - CFG - CFG - Configuration register - 0x4 - 0x20 - read-write - 0x0000007F - - - WIN - Window value - 0 - 7 - - - DIV - Clock division value - 7 - 2 - - - RLDIEN - Reload counter interrupt - 9 - 1 - - - - - STS - STS - Status register - 0x8 - 0x20 - read-write - 0x00000000 - - - RLDF - Reload counter interrupt flag - 0 - 1 - - - - - - - TMR1 - Advanced timer - TIMER - 0x40010000 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - TMR1_CH - TMR1 channel interrupt - 27 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - TRGOUT2EN - TRGOUT2 enable - 31 - 1 - - - C4IOS - Channel 4 idle output state - 14 - 1 - - - C3CIOS - Channel 3 complementary idle output state - 13 - 1 - - - C3IOS - Channel 3 idle output state - 12 - 1 - - - C2CIOS - Channel 2 complementary idle output state - 11 - 1 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3CP - Channel 3 complementary polarity - 11 - 1 - - - C3CEN - Channel 3 complementary enable - 10 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - CM3_OUTPUT - CM3_OUTPUT - Channel output mode register - 0x70 - 0x20 - read-write - 0x00000000 - - - C5OSEN - Channel 5 output switch enable - 7 - 1 - - - C5OCTRL - Channel 5 output control - 4 - 3 - - - C5OBEN - Channel 5 output buffer enable - 3 - 1 - - - C5OIEN - Channel 5 output immediately enable - 2 - 1 - - - - - C5DT - C5DT - Channel 5 data register - 0x74 - 0x20 - read-write - 0x00000000 - - - C5DT - Channel 5 data register - 0 - 16 - - - - - - - TMR8 - 0x40010400 - - TMR8_BRK_TMR12 - TMR8 brake interrupt and TMR12 global - interrupt - 43 - - - TMR8_OVF_TMR13 - TMR8 overflow interrupt and TMR13 global - interrupt - 44 - - - TMR8_TRG_HALL_TMR14 - TMR8 trigger and HALL interrupts and - TMR14 global interrupt - 45 - - - TMR8_CH - TMR8 channel interrupt - 46 - - - - TMR20 - 0x40014C00 - - TMR20_BRK - TMR20 brake interrupt - 104 - - - TMR20_OVF - TMR20 overflow interrupt - 105 - - - TMR20_TRG_HALL - TMR20 trigger and HALL interrupts - 106 - - - TMR20_CH - TMR20 channel interrupt - 107 - - - - TMR2 - General purpose timer - TIMER - 0x40000000 - - 0x0 - 0x400 - registers - - - TMR2 - TMR2 global interrupt - 28 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PMEN - Plus Mode Enable - 10 - 1 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 32 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 32 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 32 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 32 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 32 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 32 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - TMR2_RMP - TMR2_RMP - TMR2 channel input remap register - 0x50 - 0x20 - read-write - 0x0000 - - - TMR2_CH1_IRMP - TMR2 channel 1 input remap - 10 - 2 - - - - - - - TMR3 - General purpose timer - TIMER - 0x40000400 - - 0x0 - 0x400 - registers - - - TMR3 - TMR3 global interrupt - 29 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR4 - 0x40000800 - - TMR4 - TMR4 global interrupt - 30 - - - - TMR5 - General purpose timer - TIMER - 0x40000C00 - - 0x0 - 0x400 - registers - - - TMR5 - TMR5 global interrupt - 50 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PMEN - Plus Mode Enable - 10 - 1 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 32 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 32 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 32 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 32 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 32 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 32 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - TMR5_RMP - TMR5_RMP - TMR5 channel input remap register - 0x50 - 0x20 - read-write - 0x0000 - - - TMR5_CH4_IRMP - TMR5 channel 4 input remap - 6 - 2 - - - - - - - TMR9 - General purpose timer - TIMER - 0x40014000 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - - - TMR12 - 0x40001800 - - TMR8_BRK_TMR12 - TMR8 brake interrupt and TMR12 global - interrupt - 43 - - - - TMR10 - General purpose timer - TIMER - 0x40014400 - - 0x0 - 0x400 - registers - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - - - TMR11 - 0x40014800 - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - - TMR13 - 0x40001C00 - - TMR8_OVF_TMR13 - TMR8 overflow interrupt and TMR13 global - interrupt - 44 - - - - TMR14 - 0x40002000 - - TMR8_TRG_HALL_TMR14 - TMR8 trigger and HALL interrupts and - TMR14 global interrupt - 45 - - - - TMR6 - Basic timer - TIMER - 0x40001000 - - 0x0 - 0x400 - registers - - - TMR6 - TMR6 global interrupt - 54 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - PTOS - Primary TMR output selection - 4 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - - - TMR7 - 0x40001400 - - TMR7 - TMR7 global interrupt - 55 - - - - ACC - HSI Auto Clock Calibration - ACC - 0x40017400 - - 0x0 - 0x400 - registers - - - - STS - STS - status register - 0x0 - 0x20 - 0x0000 - - - RSLOST - Reference Signal Lost - read-write - 1 - 1 - - - CALRDY - Internal high-speed clock calibration ready - read-write - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x04 - 0x20 - 0x0100 - - - STEP - STEP - read-write - 8 - 4 - - - CALRDYIEN - CALRDY interrupt enable - read-write - 5 - 1 - - - EIEN - RSLOST error interrupt enable - read-write - 4 - 1 - - - SOFSEL - SOF Select - read-write - 2 - 1 - - - ENTRIM - Enable trim - read-write - 1 - 1 - - - CALON - Calibration on - read-write - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x08 - 0x20 - 0x2080 - - - HICKTWK - Internal high-speed auto clock trimming - read-only - 8 - 6 - - - HICKCAL - Internal high-speed auto clock calibration - read-only - 0 - 8 - - - - - C1 - C1 - compare value 1 - 0x0C - 0x20 - 0x1F2C - - - C1 - Compare 1 - read-write - 0 - 16 - - - - - C2 - C2 - compare value 2 - 0x10 - 0x20 - 0x1F40 - - - C2 - Compare 2 - read-write - 0 - 16 - - - - - C3 - C3 - compare value 3 - 0x14 - 0x20 - 0x1F54 - - - C3 - Compare 3 - read-write - 0 - 16 - - - - - - - I2C1 - Inter-integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1_EVT - I2C1 event interrupt - 31 - - - I2C1_ERR - I2C1 error interrupt - 32 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - 0x00000000 - - - I2CEN - I2C peripheral enable - 0 - 1 - read-write - - - TDIEN - Transmit data interrupt enable - 1 - 1 - read-write - - - RDIEN - Receive data interrupt enable - 2 - 1 - read-write - - - ADDRIEN - Address match interrupt enable - 3 - 1 - read-write - - - ACKFAILIEN - Acknowledge fail interrupt enable - 4 - 1 - read-write - - - STOPIEN - Stop generation complete interrupt enable - 5 - 1 - read-write - - - TDCIEN - Transfer data complete interrupt enable - 6 - 1 - read-write - - - ERRIEN - Error interrupts enable - 7 - 1 - read-write - - - DFLT - Digital filter value - 8 - 4 - read-write - - - DMATEN - DMA Transmit data request enable - 14 - 1 - read-write - - - DMAREN - DMA receive data request enable - 15 - 1 - read-write - - - SCTRL - Slave receiving data control - 16 - 1 - read-write - - - STRETCH - Clock stretching mode - 17 - 1 - read-write - - - GCAEN - General call address enable - 19 - 1 - read-write - - - HADDREN - SMBus host address enable - 20 - 1 - read-write - - - DEVADDREN - SMBus device default address enable - 21 - 1 - read-write - - - SMBALERT - SMBus alert enable / pin set - 22 - 1 - read-write - - - PECEN - PEC calculation enable - 23 - 1 - read-write - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - PECTEN - Request PEC transmission enable - 26 - 1 - - - ASTOPEN - Automatically send stop condition enable - 25 - 1 - - - RLDEN - Send data reload mode enable - 24 - 1 - - - CNT - Transmit data counter - 16 - 8 - - - NACKEN - Not acknowledge enable - 15 - 1 - - - GENSTOP - Generate stop condition - 14 - 1 - - - GENSTART - Generate start condition - 13 - 1 - - - READH10 - 10-bit address header read enable - 12 - 1 - - - ADDR10 - Host send 10-bit address mode enable - 11 - 1 - - - DIR - Master data transmission direction - 10 - 1 - - - SADDR - Slave address - 0 - 10 - - - - - OADDR1 - OADDR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x00000000 - - - ADDR1 - Interface address - 0 - 10 - - - ADDR1MODE - Own Address mode - 10 - 1 - - - ADDR1EN - Own address 1 enable - 15 - 1 - - - - - OADDR2 - OADDR2 - Own address register 2 - 0xC - 0x20 - read-write - 0x00000000 - - - ADDR2 - Own address 2 - 1 - 7 - - - ADDR2MASK - Own address 2-bit mask - 8 - 3 - - - ADDR2EN - Own address 2 enable - 15 - 1 - - - - - CLKCTRL - CLKCTRL - Clock contorl register - 0x10 - 0x20 - read-write - 0x00000000 - - - SCLL - SCL low level - 0 - 8 - - - SCLH - SCL high level - 8 - 8 - - - SDAD - SDA output delay - 16 - 4 - - - SCLD - SCL output delay - 20 - 4 - - - DIVH - High 4 bits of clock divider value - 24 - 4 - - - DIVL - Low 4 bits of clock divider value - 28 - 4 - - - - - TIMEOUT - TIMEOUT - Timeout register - 0x14 - 0x20 - read-write - 0x00000000 - - - TOTIME - Clock timeout detection time - 0 - 12 - - - TOMOED - Clock timeout detection mode - 12 - 1 - - - TOEN - Detect clock low/high timeout enable - 15 - 1 - - - EXTTIME - Cumulative clock low extend timeout value - 16 - 12 - - - EXTEN - Cumulative clock low extend timeout enable - 31 - 1 - - - - - STS - STS - Interrupt and Status register - 0x18 - 0x20 - 0x00000001 - - - ADDR - Slave address matching value - 17 - 7 - read-only - - - SDIR - Slave data transmit direction - 16 - 1 - read-only - - - BUSYF - Bus busy - 15 - 1 - read-only - - - ALERTF - SMBus alert flag - 13 - 1 - read-only - - - TMOUT - SMBus timeout flag - 12 - 1 - read-only - - - PECERR - PEC receive error flag - 11 - 1 - read-only - - - OUF - Overflow or underflow flag - 10 - 1 - read-only - - - ARLOST - Arbitration lost flag - 9 - 1 - read-only - - - BUSERR - Bus error flag - 8 - 1 - read-only - - - TCRLD - Transmission is complete, waiting to load data - 7 - 1 - read-only - - - TDC - Transmit data complete flag - 6 - 1 - read-only - - - STOPF - Stop condition generation complete flag - 5 - 1 - read-only - - - ACKFAIL - Acknowledge failure flag - 4 - 1 - read-only - - - ADDRF - 0~7 bit address match flag - 3 - 1 - read-only - - - RDBF - Receive data buffer full flag - 2 - 1 - read-only - - - TDIS - Send interrupt status - 1 - 1 - read-write - - - TDBE - Transmit data buffer empty flag - 0 - 1 - read-write - - - - - CLR - CLR - Interrupt clear register - 0x1C - 0x20 - write-only - 0x00000000 - - - ALERTC - Clear SMBus alert flag - 13 - 1 - - - TMOUTC - Clear SMBus timeout flag - 12 - 1 - - - PECERRC - Clear PEC receive error flag - 11 - 1 - - - OUFC - Clear overload / underload flag - 10 - 1 - - - ARLOSTC - Clear arbitration lost flag - 9 - 1 - - - BUSERRC - Clear bus error flag - 8 - 1 - - - STOPC - Clear stop condition generation complete flag - 5 - 1 - - - ACKFAILC - Clear acknowledge failure flag - 4 - 1 - - - ADDRC - Clear 0~7 bit address match flag - 3 - 1 - - - - - PEC - PEC - PEC register - 0x20 - 0x20 - read-only - 0x00000000 - - - PECVAL - PEC value - 0 - 8 - - - - - RXDT - RXDT - Receive data register - 0x24 - 0x20 - read-only - 0x00000000 - - - DT - Receive data register - 0 - 8 - - - - - TXDT - TXDT - Transmit data register - 0x28 - 0x20 - read-write - 0x00000000 - - - DT - Transmit data register - 0 - 8 - - - - - - - I2C2 - 0x40005800 - - I2C2_EVT - I2C2 event interrupt - 33 - - - I2C2_ERR - I2C2 error interrupt - 34 - - - - I2C3 - 0x40005C00 - - I2C3_EVT - I2C3 event interrupt - 72 - - - I2C3_ERR - I2C3 error interrupt - 73 - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global interrupt - 35 - - - - CTRL1 - CTRL1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SLBEN - Single line bidirectional half-duplex enable - 15 - 1 - - - SLBTD - Single line bidirectional half-duplex transmission direction - 14 - 1 - - - CCEN - CRC calculation enable - 13 - 1 - - - NTC - Next transmission CRC - 12 - 1 - - - FBN - frame bit num - 11 - 1 - - - ORA - Only receive active - 10 - 1 - - - SWCSEN - Software CS enable - 9 - 1 - - - SWCSIL - Software CS internal level - 8 - 1 - - - LTF - LSB transmit first - 7 - 1 - - - SPIEN - SPI enable - 6 - 1 - - - MDIV2_0 - Master clock frequency division bit2-0 - 3 - 3 - - - MSTEN - Master enable - 2 - 1 - - - CLKPOL - Clock polarity - 1 - 1 - - - CLKPHA - Clock phase - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MDIV3EN - Master clock frequency3 division enable - 9 - 1 - - - MDIV3 - Master clock frequency division bit3 - 8 - 1 - - - TDBEIE - Transmit data buffer empty interrupt enable - 7 - 1 - - - RDBFIE - Receive data buffer full interrupt enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - TIEN - TI mode enable - 4 - 1 - - - HWCSOE - Hardware CS output enable - 2 - 1 - - - DMATEN - DMA transmit enable - 1 - 1 - - - DMAREN - DMA receive enable - 0 - 1 - - - - - STS - STS - status register - 0x8 - 0x20 - 0x0002 - - - CSPAS - CS pulse abnormal setting fiag - 8 - 1 - read-write - - - BF - Busy flag - 7 - 1 - read-only - - - ROERR - Receiver overflow error - 6 - 1 - read-only - - - MMERR - Master mode error - 5 - 1 - read-only - - - CCERR - CRC calculation error - 4 - 1 - read-write - - - TUERR - Transmitter underload error - 3 - 1 - read-only - - - ACS - Audio channel state - 2 - 1 - read-only - - - TDBE - Transmit data buffer empty - 1 - 1 - read-only - - - RDBF - Receive data buffer full - 0 - 1 - read-only - - - - - DT - DT - data register - 0xC - 0x20 - read-write - 0x0000 - - - DT - Data value - 0 - 16 - - - - - CPOLY - CPOLY - CRC polynomial register - 0x10 - 0x20 - read-write - 0x0007 - - - CPOLY - CRC polynomial - 0 - 16 - - - - - RCRC - RCRC - Receive CRC register - 0x14 - 0x20 - read-only - 0x0000 - - - RCRC - Receive CRC - 0 - 16 - - - - - TCRC - TCRC - Transmit CRC register - 0x18 - 0x20 - read-only - 0x0000 - - - TCRC - Transmit CRC - 0 - 16 - - - - - I2SCTRL - I2SCTRL - I2S control register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SMSEL - I2S mode select - 11 - 1 - - - I2SEN - I2S Enable - 10 - 1 - - - OPERSEL - I2S operation select - 8 - 2 - - - PCMFSSEL - PCM frame synchronization select - 7 - 1 - - - STDSEL - I2S standard select - 4 - 2 - - - I2SCLKPOL - I2S clock polarity - 3 - 1 - - - I2SDBN - I2S data bit num - 1 - 2 - - - I2SCBN - I2S channel bit num - 0 - 1 - - - - - I2SCLK - I2SCLK - I2S clock register - 0x20 - 0x20 - read-write - 00000010 - - - I2SDIV9_8 - I2S division bit9 and bit8 - 10 - 2 - - - I2SMCLKOE - I2S master clock output enable - 9 - 1 - - - I2SODD - Odd result for I2S division - 8 - 1 - - - I2SDIV7_0 - I2S division bit7 to bit0 - 0 - 8 - - - - - - - SPI2 - 0x40003800 - - SPI2 - SPI2 global interrupt - 36 - - - - SPI3 - 0x40003C00 - - SPI3 - SPI3 global interrupt - 51 - - - - SPI4 - 0x40013400 - - SPI4 - SPI4 global interrupt - 84 - - - - I2S2_EXT - 0x40017800 - - - I2S3_EXT - 0x40017C00 - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40011000 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global interrupt - 37 - - - - STS - STS - Status register - 0x0 - 0x20 - 0x00C0 - - - CTSCF - CTS change flag - 9 - 1 - read-write - - - BFF - Break frame flag - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - 7 - 1 - read-only - - - TDC - Transmit data complete - 6 - 1 - read-write - - - RDBF - Receive data buffer full - 5 - 1 - read-write - - - IDLEF - IDLE flag - 4 - 1 - read-only - - - ROERR - Receiver overflow error - 3 - 1 - read-only - - - NERR - Noise error - 2 - 1 - read-only - - - FERR - Framing error - 1 - 1 - read-only - - - PERR - Parity error - 0 - 1 - read-only - - - - - DT - DT - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DT - Data value - 0 - 9 - - - - - BAUDR - BAUDR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV - Division - 0 - 16 - - - - - CTRL1 - CTRL1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - DBN1 - high bit for Data bit num - 28 - 1 - - - TSDT - transmit start delay time - 21 - 5 - - - TCDT - transmit complete delay time - 16 - 5 - - - UEN - USART enable - 13 - 1 - - - DBN0 - low bit for Data bit num - 12 - 1 - - - WUM - Wake up mode - 11 - 1 - - - PEN - Parity enable - 10 - 1 - - - PSEL - Parity selection - 9 - 1 - - - PERRIEN - PERR interrupt enable - 8 - 1 - - - TDBEIEN - TDBE interrupt enable - 7 - 1 - - - TDCIEN - TDC interrupt enable - 6 - 1 - - - RDBFIEN - RDBF interrupt enable - 5 - 1 - - - IDLEIEN - IDLE interrupt enable - 4 - 1 - - - TEN - Transmitter enable - 3 - 1 - - - REN - Receiver enable - 2 - 1 - - - RM - Receiver mute - 1 - 1 - - - SBF - Send break frame - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - ID7_4 - bit 7-4 for usart identification - 28 - 4 - - - TRPSWAP - Transmit receive pin swap - 15 - 1 - - - LINEN - LIN mode enable - 14 - 1 - - - STOPBN - STOP bit num - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CLKPOL - Clock polarity - 10 - 1 - - - CLKPHA - Clock phase - 9 - 1 - - - LBCP - Last bit clock pulse - 8 - 1 - - - BFIEN - Break frame interrupt enable - 6 - 1 - - - BFBN - Break frame bit num - 5 - 1 - - - IDBN - Identification bit num - 4 - 1 - - - ID3_0 - bit 3-0 for usart identification - 0 - 4 - - - - - CTRL3 - CTRL3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - DEP - DE polarity selection - 15 - 1 - - - RS485EN - RS485 enable - 14 - 1 - - - CTSCFIEN - CTSCF interrupt enable - 10 - 1 - - - CTSEN - CTS enable - 9 - 1 - - - RTSEN - RTS enable - 8 - 1 - - - DMATEN - DMA transmitter enable - 7 - 1 - - - DMAREN - DMA receiver enable - 6 - 1 - - - SCMEN - Smartcard mode enable - 5 - 1 - - - SCNACKEN - Smartcard NACK enable - 4 - 1 - - - SLBEN - Single line bidirectional half-duplex enable - 3 - 1 - - - IRDALP - IrDA low-power mode - 2 - 1 - - - IRDAEN - IrDA enable - 1 - 1 - - - ERRIEN - Error interrupt enable - 0 - 1 - - - - - GDIV - GDIV - Guard time and division register - 0x18 - 0x20 - read-write - 0x0000 - - - SCGT - Smart card guard time value - 8 - 8 - - - ISDIV - IrDA/smartcard division value - 0 - 8 - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global interrupt - 38 - - - - USART3 - 0x40004800 - - USART3 - USART3 global interrupt - 39 - - - - USART6 - 0x40011400 - - USART6 - USART6 global interrupt - 71 - - - - ADC1 - Analog to digital converter - ADC - 0x40012000 - - 0x0 - 0x100 - registers - - - ADC - ADC1 global interrupt - 18 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - RDY - ADC ready to conversion flag - 6 - 1 - read-only - - - OCCO - Ordinary channel conversion overflow flag - 5 - 1 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - OCCE - Ordinary channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCCOIEN - Ordinary channel conversion overflow interrupt enable - 26 - 1 - - - CRSEL - Conversion resolution select - 24 - 2 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - OCCEIEN - Ordinary channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - OCTESEL_H - High bit of trigger event select for ordinary channels conversion - 31 - 1 - - - OCSWTRG - Ordinary channel software conversion trigger - 30 - 1 - - - OCETE - Ordinary channel external trigger edge select - 28 - 2 - - - OCTESEL_L - Low bit of trigger event select for ordinary channels conversion - 24 - 4 - - - PCTESEL_H - High bit of trigger event select for preempted channels conversion - 23 - 1 - - - PCSWTRG - Preempted channel software conversion trigger - 22 - 1 - - - PCETE - Preempted channel external trigger edge select - 20 - 2 - - - PCTESEL_L - Low bit of trigger event select for preempted channels conversion - 16 - 4 - - - DTALIGN - Data alignment - 11 - 1 - - - EOCSFEN - Each ordinary channel conversion set OCCE flag enable - 10 - 1 - - - OCDRCEN - Ordinary channel DMA request continuation enable for independent mode - 9 - 1 - - - OCDMAEN - Ordinary channel DMA transfer enable for independent mode - 8 - 1 - - - ADABRT - ADC conversion abort - 4 - 1 - - - ADCALINIT - Initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT18 - Selection sample time of channel ADC_IN18 - 24 - 3 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 12 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 12 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 4 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - OVSP - OVSP - oversampling register - 0x80 - 0x20 - read-write - 0x00000000 - - - OOSRSEL - Ordinary oversampling recovery mode select - 10 - 1 - - - OOSTREN - Ordinary oversampling trigger mode enable - 9 - 1 - - - OSSSEL - Oversampling shift select - 5 - 4 - - - OSRSEL - Oversampling ratio select - 2 - 3 - - - POSEN - Preempted oversampling enable - 1 - 1 - - - OOSEN - Ordinary oversampling enable - 0 - 1 - - - - - CALVAL - CALVAL - Calibration value register - 0xB4 - 0x20 - read-write - 0x00000000 - - - CALVAL - A/D Calibration value - 0 - 7 - - - - - - - ADC2 - 0x40012100 - - ADC - ADC2 global interrupts - 18 - - - - ADC3 - 0x40012200 - - ADC - ADC3 global interrupts - 18 - - - - ADCCOM - ADC common area - ADC - 0x40012300 - - 0x0 - 0x100 - registers - - - - CSTS - CSTS - Common status register - 0x0 - 0x20 - read-only - 0x00000000 - - - RDY3 - ADC ready to conversion flag of ADC3 - 22 - 1 - - - OCCO3 - Ordinary channel conversion overflow flag of ADC3 - 21 - 1 - - - OCCS3 - Ordinary channel conversion start flag of ADC3 - 20 - 1 - - - PCCS3 - Preempted channel conversion start flag of ADC3 - 19 - 1 - - - PCCE3 - Preempted channels conversion end flag of ADC3 - 18 - 1 - - - OCCE3 - Ordinary channels conversion end flag of ADC3 - 17 - 1 - - - VMOR3 - Voltage monitoring out of range flag of ADC3 - 16 - 1 - - - RDY2 - ADC ready to conversion flag of ADC2 - 14 - 1 - - - OCCO2 - Ordinary channel conversion overflow flag of ADC2 - 13 - 1 - - - OCCS2 - Ordinary channel conversion start flag of ADC2 - 12 - 1 - - - PCCS2 - Preempted channel conversion start flag of ADC2 - 11 - 1 - - - PCCE2 - Preempted channels conversion end flag of ADC2 - 10 - 1 - - - OCCE2 - Ordinary channels conversion end flag of ADC2 - 9 - 1 - - - VMOR2 - Voltage monitoring out of range flag of ADC2 - 8 - 1 - - - RDY1 - ADC ready to conversion flag of ADC1 - 6 - 1 - - - OCCO1 - Ordinary channel conversion overflow flag of ADC1 - 5 - 1 - - - OCCS1 - Ordinary channel conversion start flag of ADC1 - 4 - 1 - - - PCCS1 - Preempted channel conversion start flag of ADC1 - 3 - 1 - - - PCCE1 - Preempted channels conversion end flag of ADC1 - 2 - 1 - - - OCCE1 - Ordinary channels conversion end flag of ADC1 - 1 - 1 - - - VMOR1 - Voltage monitoring out of range flag of ADC1 - 0 - 1 - - - - - CCTRL - CCTRL - Common control register - 0x4 - 0x20 - read-write - 0x00000000 - - - MSDMASEL_H - High bit of ordinary channel DMA transfer mode select for master slave mode - 28 - 1 - - - ITSRVEN - Internal temperature sensor and VINTRV enable - 23 - 1 - - - VBATEN - VBAT enable - 22 - 1 - - - ADCDIV - ADC division - 16 - 4 - - - MSDMASEL_L - Low bit of ordinary channel DMA transfer mode select for master slave mode - 14 - 2 - - - MSDRCEN - Ordinary channel DMA request continuation enable for master slave mode - 13 - 1 - - - ASISEL - Adjacent ADC sampling interval select for ordinary shifting mode - 8 - 4 - - - MSSEL - Master slave mode select - 0 - 5 - - - - - CODT - CODT - Common Ordinary data register - 0x8 - 0x20 - read-only - 0x00000000 - - - CODTH - Ordinary conversion high halfword data for master slave mode - 16 - 16 - - - CODTL - Ordinary conversion low halfword data for master slave mode - 0 - 16 - - - - - - - CAN1 - Can controller area network - CAN - 0x40006400 - - 0x0 - 0x400 - registers - - - CAN1_TX - CAN1 TX interrupt - 19 - - - CAN1_RX0 - CAN1 RX0 interrupt - 20 - - - CAN_RX1 - CAN1 RX1 interrupt - 21 - - - CAN_SE - CAN1 SE interrupt - 22 - - - - MCTRL - MCTRL - Main control register - 0x0 - 0x20 - read-write - 0x00010002 - - - PTD - Prohibit transmission when debug - 16 - 1 - - - SPRST - Software partial reset - 15 - 1 - - - TTCEN - Time triggered communication mode enable - 7 - 1 - - - AEBOEN - Automatic exit bus-off enable - 6 - 1 - - - AEDEN - Automatic exit doze mode enable - 5 - 1 - - - PRSFEN - Prohibit retransmission when sending fails enable - 4 - 1 - - - MDRSEL - Message discarding rule select when overflow - 3 - 1 - - - MMSSR - Multiple message sending sequence rule - 2 - 1 - - - DZEN - Doze mode enable - 1 - 1 - - - FZEN - Freeze mode enable - 0 - 1 - - - - - MSTS - MSTS - Main status register - 0x4 - 0x20 - 0x00000C02 - - - REALRX - Real time level of RX pin - 11 - 1 - read-only - - - LSAMPRX - Last sample level of RX pin - 10 - 1 - read-only - - - CURS - Currently receiving status - 9 - 1 - read-only - - - CUSS - Currently sending status - 8 - 1 - read-only - - - EDZIF - Enter doze mode interrupt flag - 4 - 1 - read-write - - - QDZIF - Quit doze mode interrupt flag - 3 - 1 - read-write - - - EOIF - Error occur Interrupt flag - 2 - 1 - read-write - - - DZC - Doze mode confirm - 1 - 1 - read-only - - - FZC - Freeze mode confirm - 0 - 1 - read-only - - - - - TSTS - TSTS - Transmit status register - 0x8 - 0x20 - 0x1C000000 - - - TM2LPF - Transmit mailbox 2 lowest priority flag - 31 - 1 - read-only - - - TM1LPF - Transmit mailbox 1 lowest priority flag - 30 - 1 - read-only - - - TM0LPF - Transmit mailbox 0 lowest priority flag - 29 - 1 - read-only - - - TM2EF - Transmit mailbox 2 empty flag - 28 - 1 - read-only - - - TM1EF - Transmit mailbox 1 empty flag - 27 - 1 - read-only - - - TM0EF - Transmit mailbox 0 empty flag - 26 - 1 - read-only - - - TMNR - Transmit Mailbox number record - 24 - 2 - read-only - - - TM2CT - Transmit mailbox 2 cancel transmission - 23 - 1 - read-write - - - TM2TEF - Transmit mailbox 2 transmission error flag - 19 - 1 - read-write - - - TM2ALF - Transmit mailbox 2 arbitration lost flag - 18 - 1 - read-write - - - TM2TSF - Transmit mailbox 2 transmission success flag - 17 - 1 - read-write - - - TM2TCF - transmit mailbox 2 transmission complete flag - 16 - 1 - read-write - - - TM1CT - Transmit mailbox 1 cancel transmission - 15 - 1 - read-write - - - TM1TEF - Transmit mailbox 1 transmission error flag - 11 - 1 - read-write - - - TM1ALF - Transmit mailbox 1 arbitration lost flag - 10 - 1 - read-write - - - TM1TSF - Transmit mailbox 1 transmission success flag - 9 - 1 - read-write - - - TM1TCF - Transmit mailbox 1 transmission complete flag - 8 - 1 - read-write - - - TM0CT - Transmit mailbox 0 cancel transmission - 7 - 1 - read-write - - - TM0TEF - Transmit mailbox 0 transmission error flag - 3 - 1 - read-write - - - TM0ALF - Transmit mailbox 0 arbitration lost flag - 2 - 1 - read-write - - - TM0TSF - Transmit mailbox 0 transmission success flag - 1 - 1 - read-write - - - TM0TCF - Transmit mailbox 0 transmission complete flag - 0 - 1 - read-write - - - - - RF0 - RF0 - Receive FIFO 0 register - 0xC - 0x20 - 0x00000000 - - - RF0R - Receive FIFO 0 release - 5 - 1 - read-write - - - RF0OF - Receive FIFO 0 overflow flag - 4 - 1 - read-write - - - RF0FF - Receive FIFO 0 full flag - 3 - 1 - read-write - - - RF0MN - Receive FIFO 0 message num - 0 - 2 - read-only - - - - - RF1 - RF1 - Receive FIFO 1 register - 0x10 - 0x20 - 0x00000000 - - - RF1R - Receive FIFO 1 release - 5 - 1 - read-write - - - RF1OF - Receive FIFO 1 overflow flag - 4 - 1 - read-write - - - RF1FF - Receive FIFO 1 full flag - 3 - 1 - read-write - - - RF1MN - Receive FIFO 1 message num - 0 - 2 - read-only - - - - - INTEN - INTEN - Interrupt enable register - 0x14 - 0x20 - read-write - 0x00000000 - - - EDZIEN - Enter doze mode interrupt enable - 17 - 1 - - - QDZIEN - Quit doze mode interrupt enable - 16 - 1 - - - EOIEN - Error occur interrupt enable - 15 - 1 - - - ETRIEN - Error type record interrupt enable - 11 - 1 - - - BOIEN - Bus-off interrupt enable - 10 - 1 - - - EPIEN - Error passive interrupt enable - 9 - 1 - - - EAIEN - Error active interrupt enable - 8 - 1 - - - RF1OIEN - Receive FIFO 1 overflow interrupt enable - 6 - 1 - - - RF1FIEN - Receive FIFO 1 full interrupt enable - 5 - 1 - - - RF1MIEN - FIFO 1 receive message interrupt enable - 4 - 1 - - - RF0OIEN - Receive FIFO 0 overflow interrupt enable - 3 - 1 - - - RF0FIEN - Receive FIFO 0 full interrupt enable - 2 - 1 - - - RF0MIEN - FIFO 0 receive message interrupt enable - 1 - 1 - - - TCIEN - Transmission complete interrupt enable - 0 - 1 - - - - - ESTS - ESTS - Error status register - 0x18 - 0x20 - 0x00000000 - - - REC - Receive error counter - 24 - 8 - read-only - - - TEC - Transmit error counter - 16 - 8 - read-only - - - ETR - Error type record - 4 - 3 - read-write - - - BOF - Bus-off flag - 2 - 1 - read-only - - - EPF - Error passive flag - 1 - 1 - read-only - - - EAF - Error active flag - 0 - 1 - read-only - - - - - BTMG - BTMG - Bit timing register - 0x1C - 0x20 - read-write - 0x00000000 - - - LOEN - Listen-Only mode - 31 - 1 - - - LBEN - Loop back mode - 30 - 1 - - - RSAW - Resynchronization adjust width - 24 - 2 - - - BTS2 - Bit time segment 2 - 20 - 3 - - - BTS1 - Bit time segment 1 - 16 - 4 - - - BRDIV - Baud rate division - 0 - 12 - - - - - TMI0 - TMI0 - Transmit mailbox 0 identifier register - 0x180 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC0 - TMC0 - Transmit mailbox 0 data length and time stamp register - 0x184 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL0 - TMDTL0 - Transmit mailbox 0 low byte data register - 0x188 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH0 - TMDTH0 - Transmit mailbox 0 high byte data register - 0x18C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI1 - TMI1 - Transmit mailbox 1 identifier register - 0x190 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC1 - TMC1 - Transmit mailbox 1 data length and time stamp register - 0x194 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL1 - TMDTL1 - Transmit mailbox 1 low byte data register - 0x198 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH1 - TMDTH1 - Transmit mailbox 1 high byte data register - 0x19C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI2 - TMI2 - Transmit mailbox 2 identifier register - 0x1A0 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC2 - TMC2 - Transmit mailbox 2 data length and time stamp register - 0x1A4 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL2 - TMDTL2 - Transmit mailbox 2 low byte data register - 0x1A8 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH2 - TMDTH2 - Transmit mailbox 2 high byte data register - 0x1AC - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - RFI0 - RFI0 - Receive FIFO 0 register - 0x1B0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC0 - RFC0 - Receive FIFO 0 data length and time stamp register - 0x1B4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL0 - RFDTL0 - Receive FIFO 0 low byte data register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH0 - RFDTH0 - Receive FIFO 0 high byte data register - 0x1BC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - RFI1 - RFI1 - Receive FIFO 1 register - 0x1C0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC1 - RFC1 - Receive FIFO 1 data length and time stamp register - 0x1C4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL1 - RFDTL1 - Receive FIFO 1 low byte data register - 0x1C8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH1 - RFDTH1 - Receive FIFO 1 high byte data register - 0x1CC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - FCTRL - FCTRL - Filter control register - 0x200 - 0x20 - read-write - 0x00000000 - - - FCS - Filters configure switch - 0 - 1 - - - - - FMCFG - FMCFG - Filter mode config register - 0x204 - 0x20 - read-write - 0x00000000 - - - FMSEL0 - Filter mode select - 0 - 1 - - - FMSEL1 - Filter mode select - 1 - 1 - - - FMSEL2 - Filter mode select - 2 - 1 - - - FMSEL3 - Filter mode select - 3 - 1 - - - FMSEL4 - Filter mode select - 4 - 1 - - - FMSEL5 - Filter mode select - 5 - 1 - - - FMSEL6 - Filter mode select - 6 - 1 - - - FMSEL7 - Filter mode select - 7 - 1 - - - FMSEL8 - Filter mode select - 8 - 1 - - - FMSEL9 - Filter mode select - 9 - 1 - - - FMSEL10 - Filter mode select - 10 - 1 - - - FMSEL11 - Filter mode select - 11 - 1 - - - FMSEL12 - Filter mode select - 12 - 1 - - - FMSEL13 - Filter mode select - 13 - 1 - - - FMSEL14 - Filter mode select - 14 - 1 - - - FMSEL15 - Filter mode select - 15 - 1 - - - FMSEL16 - Filter mode select - 16 - 1 - - - FMSEL17 - Filter mode select - 17 - 1 - - - FMSEL18 - Filter mode select - 18 - 1 - - - FMSEL19 - Filter mode select - 19 - 1 - - - FMSEL20 - Filter mode select - 20 - 1 - - - FMSEL21 - Filter mode select - 21 - 1 - - - FMSEL22 - Filter mode select - 22 - 1 - - - FMSEL23 - Filter mode select - 23 - 1 - - - FMSEL24 - Filter mode select - 24 - 1 - - - FMSEL25 - Filter mode select - 25 - 1 - - - FMSEL26 - Filter mode select - 26 - 1 - - - FMSEL27 - Filter mode select - 27 - 1 - - - - - FBWCFG - FBWCFG - Filter bit width config register - 0x20C - 0x20 - read-write - 0x00000000 - - - FBWSEL0 - Filter bit width select - 0 - 1 - - - FBWSEL1 - Filter bit width select - 1 - 1 - - - FBWSEL2 - Filter bit width select - 2 - 1 - - - FBWSEL3 - Filter bit width select - 3 - 1 - - - FBWSEL4 - Filter bit width select - 4 - 1 - - - FBWSEL5 - Filter bit width select - 5 - 1 - - - FBWSEL6 - Filter bit width select - 6 - 1 - - - FBWSEL7 - Filter bit width select - 7 - 1 - - - FBWSEL8 - Filter bit width select - 8 - 1 - - - FBWSEL9 - Filter bit width select - 9 - 1 - - - FBWSEL10 - Filter bit width select - 10 - 1 - - - FBWSEL11 - Filter bit width select - 11 - 1 - - - FBWSEL12 - Filter bit width select - 12 - 1 - - - FBWSEL13 - Filter bit width select - 13 - 1 - - - FBWSEL14 - Filter bit width select - 14 - 1 - - - FBWSEL15 - Filter bit width select - 15 - 1 - - - FBWSEL16 - Filter bit width select - 16 - 1 - - - FBWSEL17 - Filter bit width select - 17 - 1 - - - FBWSEL18 - Filter bit width select - 18 - 1 - - - FBWSEL19 - Filter bit width select - 19 - 1 - - - FBWSEL20 - Filter bit width select - 20 - 1 - - - FBWSEL21 - Filter bit width select - 21 - 1 - - - FBWSEL22 - Filter bit width select - 22 - 1 - - - FBWSEL23 - Filter bit width select - 23 - 1 - - - FBWSEL24 - Filter bit width select - 24 - 1 - - - FBWSEL25 - Filter bit width select - 25 - 1 - - - FBWSEL26 - Filter bit width select - 26 - 1 - - - FBWSEL27 - Filter bit width select - 27 - 1 - - - - - FRF - FRF - Filter related FIFO register - 0x214 - 0x20 - read-write - 0x00000000 - - - FRFSEL0 - Filter relation FIFO select - 0 - 1 - - - FRFSEL1 - Filter relation FIFO select - 1 - 1 - - - FRFSEL2 - Filter relation FIFO select - 2 - 1 - - - FRFSEL3 - Filter relation FIFO select - 3 - 1 - - - FRFSEL4 - Filter relation FIFO select - 4 - 1 - - - FRFSEL5 - Filter relation FIFO select - 5 - 1 - - - FRFSEL6 - Filter relation FIFO select - 6 - 1 - - - FRFSEL7 - Filter relation FIFO select - 7 - 1 - - - FRFSEL8 - Filter relation FIFO select - 8 - 1 - - - FRFSEL9 - Filter relation FIFO select - 9 - 1 - - - FRFSEL10 - Filter relation FIFO select - 10 - 1 - - - FRFSEL11 - Filter relation FIFO select - 11 - 1 - - - FRFSEL12 - Filter relation FIFO select - 12 - 1 - - - FRFSEL13 - Filter relation FIFO select - 13 - 1 - - - FRFSEL14 - Filter relation FIFO select - 14 - 1 - - - FRFSEL15 - Filter relation FIFO select - 15 - 1 - - - FRFSEL16 - Filter relation FIFO select - 16 - 1 - - FRFSEL17 - Filter relation FIFO select - 17 - 1 - - - FRFSEL18 - Filter relation FIFO select - 18 - 1 - - - FRFSEL19 - Filter relation FIFO select - 19 - 1 - - - FRFSEL20 - Filter relation FIFO select - 20 - 1 - - - FRFSEL21 - Filter relation FIFO select - 21 - 1 - - - FRFSEL22 - Filter relation FIFO select - 22 - 1 - - - FRFSEL23 - Filter relation FIFO select - 23 - 1 - - - FRFSEL24 - Filter relation FIFO select - 24 - 1 - - - FRFSEL25 - Filter relation FIFO select - 25 - 1 - - - FRFSEL26 - Filter relation FIFO select - 26 - 1 - - - FRFSEL27 - Filter relation FIFO select - 27 - 1 - - - - - FACFG - FACFG - Filter activate configuration register - 0x21C - 0x20 - read-write - 0x00000000 - - - FAEN0 - Filter activate enable - 0 - 1 - - - FAEN1 - Filter activate enable - 1 - 1 - - - FAEN2 - Filter activate enable - 2 - 1 - - - FAEN3 - Filter activate enable - 3 - 1 - - - FAEN4 - Filter activate enable - 4 - 1 - - - FAEN5 - Filter activate enable - 5 - 1 - - - FAEN6 - Filter activate enable - 6 - 1 - - - FAEN7 - Filter activate enable - 7 - 1 - - - FAEN8 - Filter activate enable - 8 - 1 - - - FAEN9 - Filter activate enable - 9 - 1 - - - FAEN10 - Filter activate enable - 10 - 1 - - - FAEN11 - Filter activate enable - 11 - 1 - - - FAEN12 - Filter activate enable - 12 - 1 - - - FAEN13 - Filter activate enable - 13 - 1 - - - FAEN14 - Filter activate enable - 14 - 1 - - FAEN15 - Filter activate enable - 15 - 1 - - - FAEN16 - Filter activate enable - 16 - 1 - - - FAEN17 - Filter activate enable - 17 - 1 - - - FAEN18 - Filter activate enable - 18 - 1 - - - FAEN19 - Filter activate enable - 19 - 1 - - - FAEN20 - Filter activate enable - 20 - 1 - - - FAEN21 - Filter activate enable - 21 - 1 - - - FAEN22 - Filter activate enable - 22 - 1 - - - FAEN23 - Filter activate enable - 23 - 1 - - - FAEN24 - Filter activate enable - 24 - 1 - - - FAEN25 - Filter activate enable - 25 - 1 - - - FAEN26 - Filter activate enable - 26 - 1 - - - FAEN27 - Filter activate enable - 27 - 1 - - - - - F0FB1 - F0FB1 - Filter bank 0 filtrate bit register 1 - 0x240 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F0FB2 - F0FB2 - Filter bank 0 filtrate bit register 2 - 0x244 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB1 - F1FB1 - Filter bank 1 filtrate bit register 1 - 0x248 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB2 - F1FB2 - Filter bank 1 filtrate bit register 2 - 0x24C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB1 - F2FB1 - Filter bank 2 filtrate bit register 1 - 0x250 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB2 - F2FB2 - Filter bank 2 filtrate bit register 2 - 0x254 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB1 - F3FB1 - Filter bank 3 filtrate bit register 1 - 0x258 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB2 - F3FB2 - Filter bank 3 filtrate bit register 2 - 0x25C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB1 - F4FB1 - Filter bank 4 filtrate bit register 1 - 0x260 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB2 - F4FB2 - Filter bank 4 filtrate bit register 2 - 0x264 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB1 - F5FB1 - Filter bank 5 filtrate bit register 1 - 0x268 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB2 - F5FB2 - Filter bank 5 filtrate bit register 2 - 0x26C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB1 - F6FB1 - Filter bank 6 filtrate bit register 1 - 0x270 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB2 - F6FB2 - Filter bank 6 filtrate bit register 2 - 0x274 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - F7FB1 - F7FB1 - Filter bank 7 filtrate bit register 1 - 0x278 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB2 - F7FB2 - Filter bank 7 filtrate bit register 2 - 0x27C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB1 - F8FB1 - Filter bank 8 filtrate bit register 1 - 0x280 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB2 - F8FB2 - Filter bank 8 filtrate bit register 2 - 0x284 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB1 - F9FB1 - Filter bank 9 filtrate bit register 1 - 0x288 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB2 - F9FB2 - Filter bank 9 filtrate bit register 2 - 0x28C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB1 - F10FB1 - Filter bank 10 filtrate bit register 1 - 0x290 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB2 - F10FB2 - Filter bank 10 filtrate bit register 2 - 0x294 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB1 - F11FB1 - Filter bank 11 filtrate bit register 1 - 0x298 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB2 - F11FB2 - Filter bank 11 filtrate bit register 2 - 0x29C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB1 - F12FB1 - Filter bank 12 filtrate bit register 1 - 0x2A0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB2 - F12FB2 - Filter bank 12 filtrate bit register 2 - 0x2A4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB1 - F13FB1 - Filter bank 13 filtrate bit register 1 - 0x2A8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB2 - F13FB2 - Filter bank 13 filtrate bit register 2 - 0x2AC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F14FB1 - F14FB1 - Filter bank 14 filtrate bit register 1 - 0x2B0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F14FB2 - F14FB2 - Filter bank 14 filtrate bit register 2 - 0x2B4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F15FB1 - F15FB1 - Filter bank 15 filtrate bit register 1 - 0x2B8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F15FB2 - F15FB2 - Filter bank 15 filtrate bit register 2 - 0x2BC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F16FB1 - F16FB1 - Filter bank 16 filtrate bit register 1 - 0x2C0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F16FB2 - F16FB2 - Filter bank 16 filtrate bit register 2 - 0x2C4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F17FB1 - F17FB1 - Filter bank 17 filtrate bit register 1 - 0x2C8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F17FB2 - F17FB2 - Filter bank 17 filtrate bit register 2 - 0x2CC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F18FB1 - F18FB1 - Filter bank 18 filtrate bit register 1 - 0x2D0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F18FB2 - F18FB2 - Filter bank 18 filtrate bit register 2 - 0x2D4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F19FB1 - F19FB1 - Filter bank 19 filtrate bit register 1 - 0x2D8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F19FB2 - F19FB2 - Filter bank 19 filtrate bit register 2 - 0x2DC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F20FB1 - F20FB1 - Filter bank 20 filtrate bit register 1 - 0x2E0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F20FB2 - F20FB2 - Filter bank 20 filtrate bit register 2 - 0x2E4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F21FB1 - F21FB1 - Filter bank 21 filtrate bit register 1 - 0x2E8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F21FB2 - F21FB2 - Filter bank 21 filtrate bit register 2 - 0x2EC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F22FB1 - F22FB1 - Filter bank 22 filtrate bit register 1 - 0x2F0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F22FB2 - F22FB2 - Filter bank 22 filtrate bit register 2 - 0x2F4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F23FB1 - F23FB1 - Filter bank 23 filtrate bit register 1 - 0x2F8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F23FB2 - F23FB2 - Filter bank 23 filtrate bit register 2 - 0x2FC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F24FB1 - F24FB1 - Filter bank 24 filtrate bit register 1 - 0x300 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F24FB2 - F24FB2 - Filter bank 24 filtrate bit register 2 - 0x304 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F25FB1 - F25FB1 - Filter bank 25 filtrate bit register 1 - 0x308 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F25FB2 - F25FB2 - Filter bank 25 filtrate bit register 2 - 0x30C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F26FB1 - F26FB1 - Filter bank 26 filtrate bit register 1 - 0x310 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F26FB2 - F26FB2 - Filter bank 26 filtrate bit register 2 - 0x314 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F27FB1 - F27FB1 - Filter bank 27 filtrate bit register 1 - 0x318 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F27FB2 - F27FB2 - Filter bank 27 filtrate bit register 2 - 0x31C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - - CAN2 - 0x40006800 - - CAN2_TX - CAN2 TX interrupt - 63 - - - CAN2_RX0 - CAN2 RX0 interrupt - 64 - - - CAN2_RX1 - CAN2 RX1 interrupt - 65 - - - CAN2_SE - CAN2 SE interrupt - 66 - - - - DAC - Digital to analog converter - DAC - 0x40007400 - - 0x0 - 0x400 - registers - - - - CTRL - CTRL - Control register (DAC_CTRL) - 0x0 - 0x20 - read-write - 0x00000000 - - - D1EN - DAC1 enable - 0 - 1 - - - D1OBDIS - DAC1 output buffer disable - 1 - 1 - - - D1TRGEN - DAC1 trigger enable - 2 - 1 - - - D1TRGSEL - DAC1 trigger selection - 3 - 3 - - - D1NM - DAC1 noise/triangle wave generation enable - 6 - 2 - - - D1NBSEL - DAC1 mask/amplitude selector - 8 - 4 - - - D1DMAEN - DAC1 DMA enable - 12 - 1 - - - D1DMAUDRIEN - DAC1 DMA underrun interrupt enable - 13 - 1 - - - D2EN - DAC2 enable - 16 - 1 - - - D2OBDIS - DAC2 output buffer disable - 17 - 1 - - - D2TRGEN - DAC2 trigger enable - 18 - 1 - - - D2TRGSEL - DAC2 trigger selection - 19 - 3 - - - D2NM - DAC2 noise/triangle wave generation enable - 22 - 2 - - - D2NBSEL - DAC2 mask/amplitude selector - 24 - 4 - - - D2DMAEN - DAC2 DMA enable - 28 - 1 - - - D2DMAUDRIEN - DAC2 DMA underrun interrupt enable - 29 - 1 - - - - - SWTRG - SWTRG - DAC software trigger register(DAC_SWTRIGR) - 0x4 - 0x20 - write-only - 0x00000000 - - - D1SWTRG - DAC1 software trigger - 0 - 1 - - - D2SWTRG - DAC2 software trigger - 1 - 1 - - - - - D1DTH12R - D1DTH12R - DAC1 12-bit right-aligned data holding register(DAC_D1DTH12R) - 0x8 - 0x20 - read-write - 0x00000000 - - - D1DT12R - DAC1 12-bit right-aligned data - 0 - 12 - - - - - D1DTH12L - D1DTH12L - DAC1 12-bit left aligned data holding register (DAC_D1DTH12L) - 0xC - 0x20 - read-write - 0x00000000 - - - D1DT12L - DAC1 12-bit left-aligned data - 4 - 12 - - - - - D1DTH8R - D1DTH8R - DAC1 8-bit right aligned data holding register (DAC_D1DTH8R) - 0x10 - 0x20 - read-write - 0x00000000 - - - D1DT8R - DAC1 8-bit right-aligned data - 0 - 8 - - - - - D2DTH12R - D2DTH12R - DAC2 12-bit right aligned data holding register (DAC_D2DTH12R) - 0x14 - 0x20 - read-write - 0x00000000 - - - D2DT12R - DAC2 12-bit right-aligned - data - 0 - 12 - - - - - D2DTH12L - D2DTH12L - DAC2 12-bit left aligned data holding register (DAC_D2DTH12L) - 0x18 - 0x20 - read-write - 0x00000000 - - - D2DT12L - DAC2 12-bit left-aligned data - 4 - 12 - - - - - D2DTH8R - D2DTH8R - DAC2 8-bit right-aligned data holding register (DAC_D2DTH8R) - 0x1C - 0x20 - read-write - 0x00000000 - - - D2DT8R - DAC2 8-bit right-aligned - data - 0 - 8 - - - - - DDTH12R - DDTH12R - Dual DAC 12-bit right-aligned data holding register (DAC_DDTH12R), Bits 31:28 Reserved, Bits 15:12 Reserved - 0x20 - 0x20 - read-write - 0x00000000 - - - DD1DT12R - DAC1 12-bit right-aligned data - 0 - 12 - - - DD2DT12R - DAC2 12-bit right-aligned data - 16 - 12 - - - - - DDTH12L - DDTH12L - DUAL DAC 12-bit left aligned data holding register (DAC_DDTH12L), Bits 19:16 Reserved, Bits 3:0 Reserved - 0x24 - 0x20 - read-write - 0x00000000 - - - DD1DT12L - DAC1 12-bit left-aligned data - 4 - 12 - - - DD2DT12L - DAC2 12-bit right-aligned data - 20 - 12 - - - - - DDTH8R - DDTH8R - DUAL DAC 8-bit right aligned data holding register (DAC_DDTH8R), Bits 31:16 Reserved - 0x28 - 0x20 - read-write - 0x00000000 - - - DD1DT8R - DAC1 8-bit right-aligned data - 0 - 8 - - - DD2DT8R - DAC2 8-bit right-aligned data - 8 - 8 - - - - - D1ODT - D1ODT - DAC1 data output register (DAC_D1ODT) - 0x2C - 0x20 - read-only - 0x00000000 - - - D1ODT - DAC1 data output - 0 - 12 - - - - - D2ODT - D2ODT - DAC2 data output register (DAC_D2ODT) - 0x30 - 0x20 - read-only - 0x00000000 - - - D2ODT - DAC2 data output - 0 - 12 - - - - - STS - STS - DAC2 status register - (DAC_STS) - 0x34 - 0x20 - read-write - 0x00000000 - - - DMAUDR1 - DAC1 DMA underrun flag - 13 - 1 - - - DMAUDR2 - DAC2 DMA underrun flag - 29 - 1 - - - - - - - DEBUG - Debug support - DEBUG - 0xE0042000 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - DEBUG IDCODE - 0x0 - 0x20 - read-only - 0x0 - - - PID - Product ID - 0 - 32 - - - - - CTRL - CTRL - DEBUG CTRL - 0x4 - 0x20 - read-write - 0x0 - - - SLEEP_DEBUG - SLEEP_DEBUG - 0 - 1 - - - DEEPSLEEP_DEBUG - DEEPSLEEP_DEBUG - 1 - 1 - - - STANDBY_DEBUG - STANDBY_DEBUG - 2 - 1 - - - - - APB1_PAUSE - APB1_PAUSE - DEBUG APB1 PAUSE - 0x8 - 0x20 - read-write - 0x0 - - - TMR2_PAUSE - TMR2_PAUSE - 0 - 1 - - - TMR3_PAUSE - TMR3_PAUSE - 1 - 1 - - - TMR4_PAUSE - TMR4_PAUSE - 2 - 1 - - - TMR5_PAUSE - TMR5_PAUSE - 3 - 1 - - - TMR6_PAUSE - TMR6_PAUSE - 4 - 1 - - - TMR7_PAUSE - TMR7_PAUSE - 5 - 1 - - - TMR12_PAUSE - TMR12_PAUSE - 6 - 1 - - - TMR13_PAUSE - TMR13_PAUSE - 7 - 1 - - - TMR14_PAUSE - TMR14_PAUSE - 8 - 1 - - - ERTC_PAUSE - ERTC_PAUSE - 10 - 1 - - - WWDT_PAUSE - WWDT_PAUSE - 11 - 1 - - - WDT_PAUSE - WDT_PAUSE - 12 - 1 - - - ERTC512_PAUSE - ERTC512_PAUSE - 15 - 1 - - - I2C1_SMBUS_TIMEOUT - I2C1_SMBUS_TIMEOUT - 24 - 1 - - - CAN1_PAUSE - CAN1_PAUSE - 25 - 1 - - - CAN2_PAUSE - CAN2_PAUSE - 26 - 1 - - - I2C2_SMBUS_TIMEOUT - I2C2_SMBUS_TIMEOUT - 27 - 1 - - - I2C3_SMBUS_TIMEOUT - I2C3_SMBUS_TIMEOUT - 28 - 1 - - - - - APB2_PAUSE - APB2_PAUSE - DEBUG APB2 PAUSE - 0xC - 0x20 - read-write - 0x0 - - - TMR1_PAUSE - TMR1_PAUSE - 0 - 1 - - - TMR8_PAUSE - TMR8_PAUSE - 1 - 1 - - - TMR20_PAUSE - TIM20_PAUSE - 6 - 1 - - - TMR9_PAUSE - TMR9_PAUSE - 16 - 1 - - - TMR10_PAUSE - TMR10_PAUSE - 17 - 1 - - - TMR11_PAUSE - TMR11_PAUSE - 18 - 1 - - - - - SER_ID - SER_ID - SERIES ID - 0x20 - 0x20 - read-only - 0x0 - - - REV_ID - version ID - 0 - 3 - - - SER_ID - series ID - 8 - 8 - - - - - - - UART4 - Universal asynchronous receiver transmitter - 0x40004C00 - - UART4 - UART4 global interrupt - 52 - - - - UART5 - Universal asynchronous receiver transmitter - 0x40005000 - - UART5 - UART5 global interrupt - 53 - - - - UART7 - Universal asynchronous receiver transmitter - 0x40007800 - - UART7 - UART7 global interrupt - 82 - - - - UART8 - Universal asynchronous receiver transmitter - 0x40007C00 - - UART8 - UART8 global interrupt - 83 - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DT - DT - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DT - Data Register - 0 - 32 - - - - - CDT - CDT - Common data register - 0x4 - 0x20 - read-write - 0x00000000 - - - CDT - Common Data - 0 - 1 - - - - - CTRL - CTRL - Control register - 0x8 - 0x20 - read-write - 0x00000000 - - - RST - Reset bit - 0 - 1 - - - REVID - Reverse input data - 5 - 2 - - - REVOD - Reverse output data - 7 - 1 - - - - - IDT - IDT - Initial data register - 0x10 - 0x20 - read-write - 0xFFFFFFFF - - - IDT - Initial Data - 0 - 32 - - - - - - - FLASH - Flash memory controler - FLASH - 0x40023C00 - - 0x0 - 0x400 - registers - - - FLASH - Flash global interrupt - 4 - - - - PSR - PSR - Performance selection register - 0x0 - 0x20 - 0x00000330 - - - NZW_BST_STS - Flash non-zero wait area boost status - 13 - 1 - read-only - - - NZW_BST - Flash non-zero wait area boost - 12 - 1 - read-write - - - - - UNLOCK - UNLOCK - Unlock register - 0x4 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - USD_UNLOCK - USD_UNLOCK - USD unlock register - 0x8 - 0x20 - write-only - 0x00000000 - - - USD_UKVAL - User system data Unlock key value - 0 - 32 - - - - - STS - STS - Status register - 0xC - 0x20 - 0x00000000 - - - ODF - Operate done flag - 5 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - PRGMERR - program error - 2 - 1 - read-write - - - OBF - Operate busy flag - 0 - 1 - read-only - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - BLKERS - Block erase - 3 - 1 - - - USDPRGM - User system data program - 4 - 1 - - - USDERS - User system data erase - 5 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - USDULKS - User system data unlock success - 9 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR - ADDR - Address register - 0x14 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - USD - USD - User system data register - 0x1C - 0x20 - read-only - 0x03FFFFFC - - - USDERR - User system data error - 0 - 1 - - - FAP - FLASH access protection - 1 - 1 - - - nWDT_ATO_EN - WDT auto enable - 2 - 1 - - - nDEPSLP_RST - Deepsleep reset - 3 - 1 - - - nSTDBY_RST - Standby reset - 4 - 1 - - - BTOPT - boot option - 5 - 1 - - - nWDT_DEPSLP - WDT deep sleep - 7 - 1 - - - nWDT_STDBY - WDT standby - 8 - 1 - - - USER_D0 - User data 0 - 10 - 8 - - - USER_D1 - User data 1 - 18 - 8 - - - - - EPPS0 - EPPS0 - Erase/program protection status register 0 - 0x20 - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - EPPS1 - EPPS1 - Erase/program protection status register 1 - 0x2C - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - UNLOCK2 - UNLOCK2 - Unlock 2 register - 0x44 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - STS2 - STS2 - Status 2 register - 0x4C - 0x20 - 0x00000000 - - - OBF - Operate busy flag - 0 - 1 - read-only - - - PRGMERR - program error - 2 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - ODF - Operate done flag - 5 - 1 - read-write - - - - - CTRL2 - CTRL2 - Control 2 register - 0x50 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - BLKERS - Block erase - 3 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR2 - ADDR2 - Address 2 register - 0x54 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - CONTR - CONTR - Flash continue read register - 0x58 - 0x20 - read-write - 0x00000080 - - - FCONTR_EN - Flash continue read enable - 31 - 1 - - - - - DIVR - DIVR - Flash divider register - 0x60 - 0x20 - 0x00000022 - - - FDIV - Flash divider - 0 - 2 - read-write - - - FDIV_STS - Flash divider status - 4 - 2 - read-only - - - - - SLIB_STS2 - SLIB_STS2 - sLib status 2 register - 0xC8 - 0x20 - 0x0000FFFF - - - SLIB_INST_SS - sLib instruction start sector - 0 - 16 - read-only - - - - - SLIB_STS0 - SLIB_STS0 - sLib status 0 register - 0xCC - 0x20 - 0x00000000 - - - SLIB_ENF - sLib enabled flag - 3 - 1 - read-only - - - - - SLIB_STS1 - SLIB_STS1 - sLib status 1 register - 0xD0 - 0x20 - 0xFFFFFFFF - - - SLIB_SS - sLib start sector - 0 - 16 - read-only - - - SLIB_ES - sLib end sector - 16 - 16 - read-only - - - - - SLIB_PWD_CLR - SLIB_PWD_CLR - SLIB password clear register - 0xD4 - 0x20 - 0x00000000 - write-only - - - SLIB_PCLR_VAL - sLib password clear value - 0 - 32 - - - - - SLIB_MISC_STS - SLIB_MISC_STS - sLib misc status register - 0xD8 - 0x20 - 0x01000000 - - - SLIB_PWD_ERR - sLib password error - 0 - 1 - read-only - - - SLIB_PWD_OK - sLib password ok - 1 - 1 - read-only - - - SLIB_ULKF - sLib unlock flag - 2 - 1 - read-only - - - SLIB_RCNT - sLib remaining count - 16 - 9 - read-only - - - - - SLIB_SET_PWD - SLIB_SET_PWD - sLib password setting register - 0xDC - 0x20 - 0x00000000 - write-only - - - SLIB_PSET_VAL - sLib password setting val - 0 - 32 - - - - - SLIB_SET_RANGE0 - SLIB_SET_RANGE0 - Configure sLib range register 0 - 0xE0 - 0x20 - 0x00000000 - write-only - - - SLIB_SS_SET - sLib start sector setting - 0 - 16 - - - SLIB_ES_SET - sLib end sector setting - 16 - 16 - - - - - SLIB_SET_RANGE1 - SLIB_SET_RANGE1 - Configure sLib range register 1 - 0xE4 - 0x20 - 0x00000000 - write-only - - - SLIB_ISS_SET - sLib instruction start sector setting - 0 - 16 - - - SET_SLIB_STRT - sLib start setting - 31 - 1 - - - - - SLIB_UNLOCK - SLIB_UNLOCK - sLib unlock register - 0xF0 - 0x20 - 0x00000000 - write-only - - - SLIB_UKVAL - sLib unlock key value - 0 - 32 - - - - - CRC_CTRL - CRC_CTRL - CRC controler register - 0xF4 - 0x20 - 0x00000000 - write-only - - - CRC_SS - CRC start sector - 0 - 12 - - - CRC_SN - CRC sector numbler - 12 - 12 - - - CRC_STRT - CRC start - 31 - 1 - - - - - CRC_CHKR - CRC_CHKR - CRC check result register - 0xF8 - 0x20 - 0x00000000 - read-only - - - CRC_CHKR - CRC check result - 0 - 32 - - - - - - - NVIC - Nested Vectored Interrupt - Controller - NVIC - 0xE000E000 - - 0x0 - 0x1001 - registers - - - - ICTR - ICTR - Interrupt Controller Type - Register - 0x4 - 0x20 - read-only - 0x00000000 - - - INTLINESNUM - Total number of interrupt lines in - groups - 0 - 4 - - - - - STIR - STIR - Software Triggered Interrupt - Register - 0xF00 - 0x20 - write-only - 0x00000000 - - - INTID - interrupt to be triggered - 0 - 9 - - - - - ISER0 - ISER0 - Interrupt Set-Enable Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER1 - ISER1 - Interrupt Set-Enable Register - 0x104 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ICER0 - ICER0 - Interrupt Clear-Enable - Register - 0x180 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear-Enable - Register - 0x184 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x200 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x204 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending - Register - 0x280 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending - Register - 0x284 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - IABR0 - IABR0 - Interrupt Active Bit Register - 0x300 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IABR1 - IABR1 - Interrupt Active Bit Register - 0x304 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IPR0 - IPR0 - Interrupt Priority Register - 0x400 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR1 - IPR1 - Interrupt Priority Register - 0x404 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR2 - IPR2 - Interrupt Priority Register - 0x408 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR3 - IPR3 - Interrupt Priority Register - 0x40C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR4 - IPR4 - Interrupt Priority Register - 0x410 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR5 - IPR5 - Interrupt Priority Register - 0x414 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR6 - IPR6 - Interrupt Priority Register - 0x418 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR7 - IPR7 - Interrupt Priority Register - 0x41C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR8 - IPR8 - Interrupt Priority Register - 0x420 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR9 - IPR9 - Interrupt Priority Register - 0x424 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR10 - IPR10 - Interrupt Priority Register - 0x428 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR11 - IPR11 - Interrupt Priority Register - 0x42C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR12 - IPR12 - Interrupt Priority Register - 0x430 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR13 - IPR13 - Interrupt Priority Register - 0x434 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR14 - IPR14 - Interrupt Priority Register - 0x438 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - - - DVP - Digital video parallel interface - DVP - 0x50050000 - - 0x0 - 0x400 - registers - - - DVP - DVP global interrupt - 78 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - 0x0000 - - - LCDS - Line capture/drop selection - 20 - 1 - read-write - - - LCDC - Line capture/drop control - - 19 - 1 - read-write - - - PCDS - Pixel capture/drop selection - - 18 - 1 - read-write - - - PCDC - Basic pixel capture/drop control - - 16 - 2 - read-write - - - ENA - DVP enable - 14 - 1 - read-write - - - PDL - Pixel data length - 10 - 2 - read-write - - - BFRC - Basic frame rate control - 8 - 2 - read-write - - - VSP - Vertical synchronization - polarity - 7 - 1 - read-write - - - HSP - Horizontal synchronization polarity - - 6 - 1 - read-write - - - CKP - Pixel clock polarity - 5 - 1 - read-write - - - SM - synchronization mode - 4 - 1 - read-write - - - JPEG - JPEG format - 3 - 1 - read-write - - - CRP - Cropping function enable - 2 - 1 - read-write - - - CFM - Capture fire mode - 1 - 1 - read-write - - - CAP - Capture function enable - 0 - 1 - read-write - - - - - STS - STS - status register - 0x4 - 0x20 - read-only - 0x0000 - - - OFNE - Output FIFO Non-empty - 2 - 1 - - - VSYN - Vertical synchronization status - 1 - 1 - - - HSYN - Horizontal synchronization status - 0 - 1 - - - - - ESTS - ESTS - Event status register - 0x8 - 0x20 - read-only - 0x0000 - - - HSES - Horizontal synchronization event status - 4 - 1 - - - VSES - Vertical synchronization event status - 3 - 1 - - - ESEES - Embedded synchronization error event status - - 2 - 1 - - - OVRES - Data FIFO overrun event status - - 1 - 1 - - - CFDES - Capture frame done event status - - 0 - 1 - - - - - IENA - IENA - interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - HSIE - Horizontal synchronization interrupt enable - - 4 - 1 - - - VSIE - Vertical synchronization interrupt enablee - - 3 - 1 - - - ESEIE - Embedded synchronization error interrupt - enable - 2 - 1 - - - OVRIE - Data FIFO overrun interrupt enable - - 1 - 1 - - - CFDIE - Capture frame done interrupt enable - - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-only - 0x0000 - - - HSIS - Horizontal synchronization interrupt - status - 4 - 1 - - - VSIS - Vertical synchronization interrupt - status - 3 - 1 - - - ESEIS - Embedded synchronization error - interrupt status - 2 - 1 - - - OVRIS - Data FIFO overrun interrupt - status - 1 - 1 - - - CFDIS - Capture frame done interrupt - status - 0 - 1 - - - - - ICLR - ICLR - Interrupt clear register - 0x14 - 0x20 - write-only - 0x0000 - - - HSIC - Horizontal synchronization - interrupt clear - 4 - 1 - - - VSIC - Vertical synchronization - interrupt clear - 3 - 1 - - - ESEIC - Embedded synchronization - error interrupt clear - 2 - 1 - - - OVRIC - Data FIFO overrun - interrupt clear - 1 - 1 - - - CFDIC - Capture frame done - interrupt clear - 0 - 1 - - - - - SCR - SCR - Synchronization code - register - 0x18 - 0x20 - read-write - 0x0000 - - - FMEC - Frame end code - 24 - 8 - - - LNEC - Line end code - 16 - 8 - - - LNSC - Line start code - 8 - 8 - - - FMSC - Frame start code - 0 - 8 - - - - - SUR - SUR - Synchronization unmask - register - 0x1C - 0x20 - read-write - 0x0000 - - - FMEU - Frame end unmask - 24 - 8 - - - LNEU - Line end unmask - 16 - 8 - - - LNSU - Line start unmask - - 8 - 8 - - - FMSU - Frame start unmask - - 0 - 8 - - - - - CWST - CWST - Crop window start - 0x20 - 0x20 - read-write - 0x0000 - - - CVSTR - Cropping window vertical start line - - 16 - 13 - - - CHSTR - Cropping window horizontal start pixel - - 0 - 14 - - - - - CWSZ - CWSZ - Crop window size - 0x24 - 0x20 - read-write - 0x0000 - - - CVNUM - Cropping window vertical line number - - 16 - 14 - - - CHNUM - Cropping window horizontal pixel number - - 0 - 14 - - - - - DT - DT - Data register - 0x28 - 0x20 - read-only - 0x0000 - - - DT - Data Port - 0 - 32 - - - - - ACTRL - ACTRL - Advanced Control register - - 0x40 - 0x20 - read-write - 0x0000 - - - VSEID - Vertical synchonization event and interrupt - definition - 17 - 1 - - - HSEID - Horizontal synchonization event and interrupt - definition - 16 - 1 - - - DMABT - DMA burst transfer configuration - - 12 - 1 - - - IDUS - Input data un-used setting - - 10 - 1 - - - IDUN - Input data un-used number - - 8 - 2 - - - EFDM - Enhanced function data format management - - 6 - 1 - - - EFDF - Enhanced function data format - - 4 - 2 - - - PCDES - Basic pixel capture/drop extended - selection - 3 - 1 - - - MIBE - Monochrome image binarization - enable - 2 - 1 - - - EFRCE - Enhanced frame rate control - enable - 1 - 1 - - - EISRE - Enhanced image scaling resize - enable - 0 - 1 - - - - - HSCF - HSCF - Horizontal scaling control flow - - 0x48 - 0x20 - read-write - 0x0000 - - - HSRTF - Horizontal scaling resize target factor - - 16 - 13 - - - HSRSF - Horizontal scaling resize source factor - - 0 - 13 - - - - - VSCF - VSCF - Vertical scaling control flow - - 0x4C - 0x20 - read-write - 0x0000 - - - VSRTF - Vertical scaling resize target factor - - 16 - 13 - - - VSRSF - Vertical scaling resize source factor - - 0 - 13 - - - - - FRF - FRF - Frame rate flow - - 0x50 - 0x20 - read-write - 0x0000 - - - EFRCTF - Enhanced frame rate control target factor - - 8 - 5 - - - EFRCSF - Enhanced frame rate contorl source factor - - 0 - 5 - - - - - BTH - BTH - Binarization threshold - - 0x54 - 0x20 - read-write - 0x0000 - - - MIBTHD - Monochrome image binarization threshold - - 0 - 8 - - - - - - - USB_OTG1_GLOBAL - USB on-the-go full speed - USB_OTG1 - 0x50000000 - - 0x0 - 0x400 - registers - - - OTGFS1 - USB On The Go FS global - interrupt - 67 - - - - GOTGCTL - GOTGCTL - OTGFS control and status register - (OTGFS_GOTGCTL) - 0x0 - 0x20 - 0x00000800 - - - CONIDSTS - Connector ID status - 16 - 1 - read-only - - - CURMOD - Current Mode of Operation - 21 - 1 - read-only - - - - - GOTGINT - GOTGINT - OTGFS interrupt register - (OTGFS_GOTGINT) - 0x4 - 0x20 - 0x00000000 - - - SESENDDET - VBUS is deasserted - 2 - 1 - read-write - - - - - GAHBCFG - GAHBCFG - OTGFS AHB configuration register - (OTGFS_GAHBCFG) - 0x8 - 0x20 - read-write - 0x00000000 - - - GLBINTMSK - Global interrupt mask - 0 - 1 - - - NPTXFEMPLVL - Non-Periodic TxFIFO empty level - 7 - 1 - - - PTXFEMPLVL - Periodic TxFIFO empty - level - 8 - 1 - - - - - GUSBCFG - GUSBCFG - USB configuration register - (OTGFS_GUSBCFG) - 0xC - 0x20 - 0x00000A00 - - - TOUTCAL - FS timeout calibration - 0 - 3 - read-write - - - USBTRDTIM - USB turnaround time - 10 - 4 - read-write - - - FHSTMODE - Force host mode - 29 - 1 - read-write - - - FDEVMODE - Force device mode - 30 - 1 - read-write - - - COTXPKT - Corrupt Tx packet - 31 - 1 - read-write - - - - - GRSTCTL - GRSTCTL - OTGFS reset register - (OTGFS_GRSTCTL) - 0x10 - 0x20 - 0x20000000 - - - CSFTRST - Core soft reset - 0 - 1 - read-write - - - PIUSFTRST - PIU FS Dedicated Controller Soft Reset - 1 - 1 - read-write - - - FRMCNTRST - Host frame counter reset - 2 - 1 - read-write - - - RXFFLSH - RxFIFO flush - 4 - 1 - read-write - - - TXFFLSH - TxFIFO flush - 5 - 1 - read-write - - - TXFNUM - TxFIFO number - 6 - 5 - read-write - - - AHBIDLE - AHB master idle - 31 - 1 - read-only - - - - - GINTSTS - GINTSTS - OTGFS core interrupt register - (OTGFS_GINTSTS) - 0x14 - 0x20 - 0x04000020 - - - CURMOD - Current mode of operation - 0 - 1 - read-only - - - MODEMIS - Mode mismatch interrupt - 1 - 1 - read-write - - - OTGINT - OTG interrupt - 2 - 1 - read-only - - - SOF - Start of frame - 3 - 1 - read-write - - - RXFLVL - RxFIFO non-empty - 4 - 1 - read-only - - - NPTXFEMP - Non-periodic TxFIFO empty - 5 - 1 - read-only - - - GINNAKEFF - Global IN non-periodic NAK - effective - 6 - 1 - read-only - - - GOUTNAKEFF - Global OUT NAK effective - 7 - 1 - read-only - - - ERLYSUSP - Early suspend - 10 - 1 - read-write - - - USBSUSP - USB suspend - 11 - 1 - read-write - - - USBRST - USB reset - 12 - 1 - read-write - - - ENUMDONE - Enumeration done - 13 - 1 - read-write - - - ISOOUTDROP - Isochronous OUT packet dropped - interrupt - 14 - 1 - read-write - - - EOPF - End of periodic frame - interrupt - 15 - 1 - read-write - - - IEPTINT - IN endpoint interrupt - 18 - 1 - read-only - - - OEPTINT - OUT endpoint interrupt - 19 - 1 - read-only - - - INCOMPISOIN - Incomplete isochronous IN - transfer - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUT - Incomplete periodic transfer(Host - mode)/Incomplete isochronous OUT transfer(Device - mode) - 21 - 1 - read-write - - - PRTINT - Host port interrupt - 24 - 1 - read-only - - - HCHINT - Host channels interrupt - 25 - 1 - read-only - - - PTXFEMP - Periodic TxFIFO empty - 26 - 1 - read-only - - - CONIDSCHG - Connector ID status change - 28 - 1 - read-write - - - DISCONINT - Disconnect detected - interrupt - 29 - 1 - read-write - - - WKUPINT - Resume/remote wakeup detected - interrupt - 31 - 1 - read-write - - - - - GINTMSK - GINTMSK - OTG_FS interrupt mask register - (OTG_FS_GINTMSK) - 0x18 - 0x20 - 0x00000000 - - - MODEMISMSK - Mode mismatch interrupt - mask - 1 - 1 - read-write - - - OTGINTMSK - OTG interrupt mask - 2 - 1 - read-write - - - SOFMSK - Start of frame mask - 3 - 1 - read-write - - - RXFLVLMSK - Receive FIFO non-empty - mask - 4 - 1 - read-write - - - NPTXFEMPMSK - Non-periodic TxFIFO empty - mask - 5 - 1 - read-write - - - GINNAKEFFMSK - Global non-periodic IN NAK effective - mask - 6 - 1 - read-write - - - GOUTNAKEFFMSK - Global OUT NAK effective - mask - 7 - 1 - read-write - - - ERLYSUSPMSK - Early suspend mask - 10 - 1 - read-write - - - USBSUSPMSK - USB suspend mask - 11 - 1 - read-write - - - USBRSTMSK - USB reset mask - 12 - 1 - read-write - - - ENUMDONEMSK - Enumeration done mask - 13 - 1 - read-write - - - ISOOUTDROPMSK - Isochronous OUT packet dropped interrupt - mask - 14 - 1 - read-write - - - EOPFMSK - End of periodic frame interrupt - mask - 15 - 1 - read-write - - - IEPTINTMSK - IN endpoints interrupt - mask - 18 - 1 - read-write - - - OEPTINTMSK - OUT endpoints interrupt - mask - 19 - 1 - read-write - - - INCOMISOINMSK - Incomplete isochronous IN transfer - mask - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUTMSK - Incomplete periodic transfer mask(Host - mode)/Incomplete isochronous OUT transfer mask(Device - mode) - 21 - 1 - read-write - - - PRTINTMSK - Host port interrupt mask - 24 - 1 - read-write - - - HCHINTMSK - Host channels interrupt - mask - 25 - 1 - read-write - - - PTXFEMPMSK - Periodic TxFIFO empty mask - 26 - 1 - read-write - - - CONIDSCHGMSK - Connector ID status change - mask - 28 - 1 - read-write - - - DISCONINTMSK - Disconnect detected interrupt - mask - 29 - 1 - read-write - - - WKUPINTMSK - Resume/remote wakeup detected interrupt - mask - 31 - 1 - read-write - - - - - GRXSTSR_Device - GRXSTSR_Device - OTGFS Receive status debug read(Device - mode) - 0x1C - 0x20 - read-only - 0x00000000 - - - EPTNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - FN - Frame number - 21 - 4 - - - - - GRXSTSR_Host - GRXSTSR_Host - OTGFS Receive status debug read(Host - mode) - GRXSTSR_Device - 0x1C - 0x20 - read-only - 0x00000000 - - - CHNUM - Channel number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - - - GRXFSIZ - GRXFSIZ - OTGFS Receive FIFO size register - (OTGFS_GRXFSIZ) - 0x24 - 0x20 - read-write - 0x00000200 - - - RXFDEP - RxFIFO depth - 0 - 16 - - - - - DIEPTXF0 - DIEPTXF0 - IN Endpoint TxFIFO 0 transmit FIFO size - register (Device mode) - 0x28 - 0x20 - read-write - 0x00000200 - - - INEPT0TXSTADDR - Endpoint 0 transmit RAM start - address - 0 - 16 - - - INEPT0TXDEP - Endpoint 0 TxFIFO depth - 16 - 16 - - - - - GNPTXFSIZ - GNPTXFSIZ - OTGFS non-periodic transmit FIFO size - register (Host mode) - DIEPTXF0 - 0x28 - 0x20 - read-write - 0x00000200 - - - NPTXFSTADDR - Non-periodic Transmit RAM Start - address - 0 - 16 - - - NPTXFDEP - Non-periodic TxFIFO depth - 16 - 16 - - - - - GNPTXSTS - GNPTXSTS - OTGFS non-periodic transmit FIFO/queue - status register (OTGFS_GNPTXSTS) - 0x2C - 0x20 - read-only - 0x00080200 - - - NPTXFSPCAVAIL - Non-periodic TxFIFO space - available - 0 - 16 - - - NPTXQSPCAVAIL - Non-periodic transmit request queue - space available - 16 - 8 - - - NPTXQTOP - Top of the non-periodic transmit request - queue - 24 - 7 - - - - - GCCFG - GCCFG - OTGFS general core configuration register - (OTGFS_GCCFG) - 0x38 - 0x20 - read-write - 0x00000000 - - - PWRDOWN - Power down - 16 - 1 - - - LP_MODE - Low power mode - 17 - 1 - - - SOFOUTEN - SOF output enable - 20 - 1 - - - VBUSIG - VBUS Ignored - 21 - 1 - - - - - GUID - GUID - Product ID register - 0x3C - 0x20 - read-write - 0x00001000 - - - USERID - Product ID field - 0 - 32 - - - - - HPTXFSIZ - HPTXFSIZ - OTGFS Host periodic transmit FIFO size - register (OTGFS_HPTXFSIZ) - 0x100 - 0x20 - read-write - 0x02000600 - - - PTXFSTADDR - Host periodic TxFIFO start - address - 0 - 16 - - - PTXFSIZE - Host periodic TxFIFO depth - 16 - 16 - - - - - DIEPTXF1 - DIEPTXF1 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF1) - 0x104 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO1 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF2 - DIEPTXF2 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF2) - 0x108 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO2 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF3 - DIEPTXF3 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF3) - 0x10C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO3 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF4 - DIEPTXF4 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF4) - 0x110 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO4 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF5 - DIEPTXF5 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF5) - 0x114 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO5 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF6 - DIEPTXF6 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF6) - 0x118 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO6 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF7 - DIEPTXF7 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF7) - 0x11C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO7 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - - - USB_OTG1_HOST - USB on the go full speed - USB_OTG1 - 0x50000400 - - 0x0 - 0x400 - registers - - - - HCFG - HCFG - OTGFS host configuration register - (OTGFS_HCFG) - 0x0 - 0x20 - 0x00000000 - - - FSLSPCLKSEL - FS/LS PHY clock select - 0 - 2 - read-write - - - FSLSSUPP - FS- and LS-only support - 2 - 1 - read-only - - - - - HFIR - HFIR - OTGFS Host frame interval - register - 0x4 - 0x20 - read-write - 0x0000EA60 - - - FRINT - Frame interval - 0 - 16 - - - - - HFNUM - HFNUM - OTGFS host frame number/frame time - remaining register (OTGFS_HFNUM) - 0x8 - 0x20 - read-only - 0x00003FFF - - - FRNUM - Frame number - 0 - 16 - - - FTREM - Frame time remaining - 16 - 16 - - - - - HPTXSTS - HPTXSTS - OTGFS_Host periodic transmit FIFO/queue - status register (OTGFS_HPTXSTS) - 0x10 - 0x20 - 0x00080100 - - - PTXFSPCAVAIL - Periodic transmit data FIFO space - available - 0 - 16 - read-write - - - PTXQSPCAVAIL - Periodic transmit request queue space - available - 16 - 8 - read-only - - - PTXQTOP - Top of the periodic transmit request - queue - 24 - 8 - read-only - - - - - HAINT - HAINT - OTGFS Host all channels interrupt - register - 0x14 - 0x20 - read-only - 0x00000000 - - - HAINT - Channel interrupts - 0 - 16 - - - - - HAINTMSK - HAINTMSK - OTGFS host all channels interrupt mask - register - 0x18 - 0x20 - read-write - 0x00000000 - - - HAINTMSK - Channel interrupt mask - 0 - 16 - - - - - HPRT - HPRT - OTGFS host port control and status register - (OTGFS_HPRT) - 0x40 - 0x20 - 0x00000000 - - - PRTCONSTS - Port connect status - 0 - 1 - read-only - - - PRTCONDET - Port connect detected - 1 - 1 - read-write - - - PRTENA - Port enable - 2 - 1 - read-write - - - PRTENCHNG - Port enable/disable change - 3 - 1 - read-write - - - PRTOVRCACT - Port overcurrent active - 4 - 1 - read-only - - - PRTOVRCCHNG - Port overcurrent change - 5 - 1 - read-write - - - PRTRES - Port resume - 6 - 1 - read-write - - - PRTSUSP - Port suspend - 7 - 1 - read-write - - - PRTRST - Port reset - 8 - 1 - read-write - - - PRTLNSTS - Port line status - 10 - 2 - read-only - - - PRTPWR - Port power - 12 - 1 - read-write - - - PRTTSTCTL - Port test control - 13 - 4 - read-write - - - PRTSPD - Port speed - 17 - 2 - read-only - - - - - HCCHAR0 - HCCHAR0 - OTGFS host channel-0 characteristics - register (OTGFS_HCCHAR0) - 0x100 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR1 - HCCHAR1 - OTGFS host channel-1 characteristics - register (OTGFS_HCCHAR1) - 0x120 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR2 - HCCHAR2 - OTGFS host channel-2 characteristics - register (OTGFS_HCCHAR2) - 0x140 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR3 - HCCHAR3 - OTGFS host channel-3 characteristics - register (OTGFS_HCCHAR3) - 0x160 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR4 - HCCHAR4 - OTGFS host channel-4 characteristics - register (OTGFS_HCCHAR4) - 0x180 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR5 - HCCHAR5 - OTGFS host channel-5 characteristics - register (OTGFS_HCCHAR5) - 0x1A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR6 - HCCHAR6 - OTGFS host channel-6 characteristics - register (OTGFS_HCCHAR6) - 0x1C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR7 - HCCHAR7 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR7) - 0x1E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR8 - HCCHAR8 - OTGFS host channel-8 characteristics - register (OTGFS_HCCHAR8) - 0x200 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR9 - HCCHAR9 - OTGFS host channel-9 characteristics - register (OTGFS_HCCHAR9) - 0x220 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR10 - HCCHAR10 - OTGFS host channel-10 characteristics - register (OTGFS_HCCHAR10) - 0x240 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR11 - HCCHAR11 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR11) - 0x260 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR12 - HCCHAR12 - OTGFS host channel-12 characteristics - register (OTGFS_HCCHAR12) - 0x280 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR13 - HCCHAR13 - OTGFS host channel-13 characteristics - register (OTGFS_HCCHAR13) - 0x2A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR14 - HCCHAR14 - OTGFS host channel-14 characteristics - register (OTGFS_HCCHAR14) - 0x2C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR15 - HCCHAR15 - OTGFS host channel-15 characteristics - register (OTGFS_HCCHAR15) - 0x2E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCINT0 - HCINT0 - OTGFS host channel-0 interrupt register - (OTGFS_HCINT0) - 0x108 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT1 - HCINT1 - OTG_FS host channel-1 interrupt register - (OTG_FS_HCINT1) - 0x128 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT2 - HCINT2 - OTGFS host channel-2 interrupt register - (OTGFS_HCINT2) - 0x148 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT3 - HCINT3 - OTGFS host channel-3 interrupt register - (OTGFS_HCINT3) - 0x168 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT4 - HCINT4 - OTGFS host channel-4 interrupt register - (OTGFS_HCINT4) - 0x188 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT5 - HCINT5 - OTGFS host channel-5 interrupt register - (OTGFS_HCINT5) - 0x1A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT6 - HCINT6 - OTGFS host channel-6 interrupt register - (OTGFS_HCINT6) - 0x1C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT7 - HCINT7 - OTGFS host channel-7 interrupt register - (OTGFS_HCINT7) - 0x1E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT8 - HCINT8 - OTGFS host channel-8 interrupt register - (OTGFS_HCINT8) - 0x208 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT9 - HCINT9 - OTGFS host channel-9 interrupt register - (OTGFS_HCINT9) - 0x228 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT10 - HCINT10 - OTGFS host channel-10 interrupt register - (OTGFS_HCINT10) - 0x248 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT11 - HCINT11 - OTGFS host channel-11 interrupt register - (OTGFS_HCINT11) - 0x268 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT12 - HCINT12 - OTGFS host channel-12 interrupt register - (OTGFS_HCINT12) - 0x288 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT13 - HCINT13 - OTGFS host channel-13 interrupt register - (OTGFS_HCINT13) - 0x2A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT14 - HCINT14 - OTGFS host channel-14 interrupt register - (OTGFS_HCINT14) - 0x2C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT15 - HCINT15 - OTGFS host channel-15 interrupt register - (OTGFS_HCINT15) - 0x2E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINTMSK0 - HCINTMSK0 - OTGFS host channel-0 mask register - (OTGFS_HCINTMSK0) - 0x10C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK1 - HCINTMSK1 - OTGFS host channel-1 mask register - (OTGFS_HCINTMSK1) - 0x12C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK2 - HCINTMSK2 - OTGFS host channel-2 mask register - (OTGFS_HCINTMSK2) - 0x14C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK3 - HCINTMSK3 - OTGFS host channel-3 mask register - (OTGFS_HCINTMSK3) - 0x16C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK4 - HCINTMSK4 - OTGFS host channel-4 mask register - (OTGFS_HCINTMSK4) - 0x18C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK5 - HCINTMSK5 - OTGFS host channel-5 mask register - (OTGFS_HCINTMSK5) - 0x1AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK6 - HCINTMSK6 - OTGFS host channel-6 mask register - (OTGFS_HCINTMSK6) - 0x1CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK7 - HCINTMSK7 - OTGFS host channel-7 mask register - (OTGFS_HCINTMSK7) - 0x1EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK8 - HCINTMSK8 - OTGFS host channel-8 mask register - (OTGFS_HCINTMSK8) - 0x20C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK9 - HCINTMSK9 - OTGFS host channel-9 mask register - (OTGFS_HCINTMSK9) - 0x22C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK10 - HCINTMSK10 - OTGFS host channel-10 mask register - (OTGFS_HCINTMSK10) - 0x24C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK11 - HCINTMSK11 - OTGFS host channel-11 mask register - (OTGFS_HCINTMSK11) - 0x26C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK12 - HCINTMSK12 - OTGFS host channel-12 mask register - (OTGFS_HCINTMSK12) - 0x28C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK13 - HCINTMSK13 - OTGFS host channel-13 mask register - (OTGFS_HCINTMSK13) - 0x2AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK14 - HCINTMSK14 - OTGFS host channel-14 mask register - (OTGFS_HCINTMSK14) - 0x2CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK15 - HCINTMSK15 - OTGFS host channel-15 mask register - (OTGFS_HCINTMSK15) - 0x2EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCTSIZ0 - HCTSIZ0 - OTGFS host channel-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ1 - HCTSIZ1 - OTGFS host channel-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ2 - HCTSIZ2 - OTGFS host channel-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ3 - HCTSIZ3 - OTGFS host channel-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ4 - HCTSIZ4 - OTGFS host channel-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ5 - HCTSIZ5 - OTGFS host channel-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ6 - HCTSIZ6 - OTGFS host channel-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ7 - HCTSIZ7 - OTGFS host channel-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ8 - HCTSIZ8 - OTGFS host channel-8 transfer size - register - 0x210 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ9 - HCTSIZ9 - OTGFS host channel-9 transfer size - register - 0x230 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ10 - HCTSIZ10 - OTGFS host channel-10 transfer size - register - 0x250 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ11 - HCTSIZ11 - OTGFS host channel-11 transfer size - register - 0x270 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ12 - HCTSIZ12 - OTGFS host channel-12 transfer size - register - 0x290 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ13 - HCTSIZ13 - OTGFS host channel-13 transfer size - register - 0x2B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ14 - HCTSIZ14 - OTGFS host channel-14 transfer size - register - 0x2D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ15 - HCTSIZ15 - OTGFS host channel-15 transfer size - register - 0x2F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - - - USB_OTG1_DEVICE - USB on the go full speed - USB_OTG1 - 0x50000800 - - 0x0 - 0x400 - registers - - - - DCFG - DCFG - OTGFS device configuration register - (OTGFS_DCFG) - 0x0 - 0x20 - read-write - 0x02200000 - - - DEVSPD - Device speed - 0 - 2 - - - NZSTSOUTHSHK - Non-zero-length status OUT - handshake - 2 - 1 - - - DEVADDR - Device address - 4 - 7 - - - PERFRINT - Periodic frame interval - 11 - 2 - - - - - DCTL - DCTL - OTGFS device control register - (OTGFS_DCTL) - 0x4 - 0x20 - 0x00000000 - - - RWKUPSIG - Remote wakeup signaling - 0 - 1 - read-write - - - SFTDISCON - Soft disconnect - 1 - 1 - read-write - - - GNPINNAKSTS - Global IN NAK status - 2 - 1 - read-only - - - GOUTNAKSTS - Global OUT NAK status - 3 - 1 - read-only - - - TSTCTL - Test control - 4 - 3 - read-write - - - SGNPINNAK - Set global IN NAK - 7 - 1 - read-write - - - CGNPINNAK - Clear global IN NAK - 8 - 1 - read-write - - - SGOUTNAK - Set global OUT NAK - 9 - 1 - read-write - - - CGOUTNAK - Clear global OUT NAK - 10 - 1 - read-write - - - PWROPRGDNE - Power-on programming done - 11 - 1 - read-write - - - - - DSTS - DSTS - OTGFS device status register - (OTGFS_DSTS) - 0x8 - 0x20 - read-only - 0x00000010 - - - SUSPSTS - Suspend status - 0 - 1 - - - ENUMSPD - Enumerated speed - 1 - 2 - - - ETICERR - Erratic error - 3 - 1 - - - SOFFN - Frame number of the received - SOF - 8 - 14 - - - - - DIEPMSK - DIEPMSK - OTGFS device IN endpoint common interrupt - mask register (OTGFS_DIEPMSK) - 0x10 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - TIMEOUTMSK - Timeout condition mask (Non-isochronous - endpoints) - 3 - 1 - - - INTKNTXFEMPMSK - IN token received when TxFIFO empty - mask - 4 - 1 - - - INTKNEPTMISMSK - IN token received with EP mismatch - mask - 5 - 1 - - - INEPTNAKMSK - IN endpoint NAK effective - mask - 6 - 1 - - - TXFIFOUDRMSK - FIFO underrun - mask - 8 - 1 - - - BNAINMSK - BNA interrupt - mask - 9 - 1 - - - - - DOEPMSK - DOEPMSK - OTGFS device OUT endpoint common interrupt - mask register (OTGFS_DOEPMSK) - 0x14 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - SETUPMSK - SETUP phase done mask - 3 - 1 - - - OUTTEPDMSK - OUT token received when endpoint - disabled mask - 4 - 1 - - - B2BSETUPMSK - Back-to-back SETUP packets - received mask - 6 - 1 - - - OUTPERRMSK - OUT packet error - mask - 8 - 1 - - - BNAOUTMSK - BNA interrupt - mask - 9 - 1 - - - - - DAINT - DAINT - OTGFS device all endpoints interrupt - register (OTGFS_DAINT) - 0x18 - 0x20 - read-only - 0x00000000 - - - INEPTINT - IN endpoint interrupt bits - 0 - 16 - - - OUTEPTINT - OUT endpoint interrupt - bits - 16 - 16 - - - - - DAINTMSK - DAINTMSK - OTGFS all endpoints interrupt mask register - (OTGFS_DAINTMSK) - 0x1C - 0x20 - read-write - 0x00000000 - - - INEPTMSK - IN EP interrupt mask bits - 0 - 16 - - - OUTEPTMSK - OUT endpoint interrupt - bits - 16 - 16 - - - - - DIEPEMPMSK - DIEPEMPMSK - OTGFS device IN endpoint FIFO empty - interrupt mask register - 0x34 - 0x20 - read-write - 0x00000000 - - - INEPTXFEMSK - IN EP Tx FIFO empty interrupt mask - bits - 0 - 16 - - - - - DIEPCTL0 - DIEPCTL0 - OTGFS device control IN endpoint 0 control - register (OTGFS_DIEPCTL0) - 0x100 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 2 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-only - - - EPTENA - Endpoint enable - 31 - 1 - read-only - - - - - DIEPCTL1 - DIEPCTL1 - OTGFS device IN endpoint-1 control - register - 0x120 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL2 - DIEPCTL2 - OTGFS device IN endpoint-2 control - register - 0x140 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL3 - DIEPCTL3 - OTGFS device IN endpoint-3 control - register - 0x160 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL4 - DIEPCTL4 - OTGFS device IN endpoint-4 control - register - 0x180 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL5 - DIEPCTL5 - OTGFS device IN endpoint-5 control - register - 0x1A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL6 - DIEPCTL6 - OTGFS device IN endpoint-6 control - register - 0x1C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL7 - DIEPCTL7 - OTGFS device IN endpoint-7 control - register - 0x1E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL0 - DOEPCTL0 - OTGFS device OUT endpoint-0 control - register - 0x300 - 0x20 - 0x00008000 - - - MPS - Maximum packet size - 0 - 2 - read-only - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL1 - DOEPCTL1 - OTGFS device OUT endpoint-1 control - register - 0x320 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL2 - DOEPCTL2 - OTGFS device OUT endpoint-2 control - register - 0x340 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL3 - DOEPCTL3 - OTGFS device OUT endpoint-3 control - register - 0x360 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL4 - DOEPCTL4 - OTGFS device OUT endpoint-4 control - register - 0x380 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL5 - DOEPCTL5 - OTGFS device OUT endpoint-5 control - register - 0x3A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL6 - DOEPCTL6 - OTGFS device OUT endpoint-6 control - register - 0x3C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL7 - DOEPCTL7 - OTGFS device OUT endpoint-7 control - register - 0x3E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPINT0 - DIEPINT0 - OTGFS device IN endpoint-0 interrupt - register - 0x108 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT1 - DIEPINT1 - OTGFS device IN endpoint-1 interrupt - register - 0x128 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT2 - DIEPINT2 - OTGFS device IN endpoint-2 interrupt - register - 0x148 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT3 - DIEPINT3 - OTGFS device IN endpoint-3 interrupt - register - 0x168 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT4 - DIEPINT4 - OTGFS device IN endpoint-4 interrupt - register - 0x188 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT5 - DIEPINT5 - OTGFS device IN endpoint-5 interrupt - register - 0x1A8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT6 - DIEPINT6 - OTGFS device IN endpoint-6 interrupt - register - 0x1C8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT7 - DIEPINT7 - OTGFS device IN endpoint-7 interrupt - register - 0x1E8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DOEPINT0 - DOEPINT0 - OTGFS device OUT endpoint-0 interrupt - register - 0x308 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT1 - DOEPINT1 - OTGFS device OUT endpoint-1 interrupt - register - 0x328 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT2 - DOEPINT2 - OTGFS device OUT endpoint-2 interrupt - register - 0x348 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT3 - DOEPINT3 - OTGFS device OUT endpoint-3 interrupt - register - 0x368 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT4 - DOEPINT4 - OTGFS device OUT endpoint-4 interrupt - register - 0x388 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT5 - DOEPINT5 - OTGFS device OUT endpoint-5 interrupt - register - 0x3A8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT6 - DOEPINT6 - OTGFS device OUT endpoint-6 interrupt - register - 0x3C8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT7 - DOEPINT7 - OTGFS device OUT endpoint-7 interrupt - register - 0x3E8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DIEPTSIZ0 - DIEPTSIZ0 - OTGFS device IN endpoint-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 2 - - - - - DOEPTSIZ0 - DOEPTSIZ0 - OTGFS device OUT endpoint-0 transfer size - register - 0x310 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 1 - - - SETUPCNT - SETUP packet count - 29 - 2 - - - - - DIEPTSIZ1 - DIEPTSIZ1 - OTGFS device IN endpoint-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ2 - DIEPTSIZ2 - OTGFS device IN endpoint-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ3 - DIEPTSIZ3 - OTG device IN endpoint-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ4 - DIEPTSIZ4 - OTG device IN endpoint-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ5 - DIEPTSIZ5 - OTG device IN endpoint-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ6 - DIEPTSIZ6 - OTG device IN endpoint-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ7 - DIEPTSIZ7 - OTG device IN endpoint-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DTXFSTS0 - DTXFSTS0 - OTGFS device IN endpoint-0 transmit FIFO - status register - 0x118 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS1 - DTXFSTS1 - OTGFS device IN endpoint-1 transmit FIFO - status register - 0x138 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS2 - DTXFSTS2 - OTGFS device IN endpoint-2 transmit FIFO - status register - 0x158 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS3 - DTXFSTS3 - OTGFS device IN endpoint-3 transmit FIFO - status register - 0x178 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS4 - DTXFSTS4 - OTGFS device IN endpoint-4 transmit FIFO - status register - 0x198 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS5 - DTXFSTS5 - OTGFS device IN endpoint-5 transmit FIFO - status register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS6 - DTXFSTS6 - OTGFS device IN endpoint-6 transmit FIFO - status register - 0x1D8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS7 - DTXFSTS7 - OTGFS device IN endpoint-7 transmit FIFO - status register - 0x1F8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DOEPTSIZ1 - DOEPTSIZ1 - OTGFS device OUT endpoint-1 transfer size - register - 0x330 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ2 - DOEPTSIZ2 - OTGFS device OUT endpoint-2 transfer size - register - 0x350 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ3 - DOEPTSIZ3 - OTGFS device OUT endpoint-3 transfer size - register - 0x370 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ4 - DOEPTSIZ4 - OTGFS device OUT endpoint-4 transfer size - register - 0x390 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ5 - DOEPTSIZ5 - OTGFS device OUT endpoint-5 transfer size - register - 0x3B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ6 - DOEPTSIZ6 - OTGFS device OUT endpoint-6 transfer size - register - 0x3D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ7 - DOEPTSIZ7 - OTGFS device OUT endpoint-7 transfer size - register - 0x3F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - - - USB_OTG1_PWRCLK - USB on the go full speed - USB_OTG1 - 0x50000E00 - - 0x0 - 0x400 - registers - - - - PCGCCTL - PCGCCTL - OTGFS power and clock gating control - register (OTGFS_PCGCCTL) - 0x0 - 0x20 - 0x00000000 - - - STOPPCLK - Stop PHY clock - 0 - 1 - read-write - - - SUSPENDM - PHY Suspended - 4 - 1 - read-only - - - - - - - USB_OTG2_GLOBAL - USB on the go full speed - USB_OTG2 - 0x40040000 - - 0x0 - 0x400 - registers - - - OTGFS2 - USB On The Go FS2 global - interrupt - 77 - - - - GOTGCTL - GOTGCTL - OTGFS control and status register - (OTGFS_GOTGCTL) - 0x0 - 0x20 - 0x00000800 - - - CONIDSTS - Connector ID status - 16 - 1 - read-only - - - CURMOD - Current Mode of Operation - 21 - 1 - read-only - - - - - GOTGINT - GOTGINT - OTGFS interrupt register - (OTGFS_GOTGINT) - 0x4 - 0x20 - 0x00000000 - - - SESENDDET - VBUS is deasserted - 2 - 1 - read-write - - - - - GAHBCFG - GAHBCFG - OTGFS AHB configuration register - (OTGFS_GAHBCFG) - 0x8 - 0x20 - read-write - 0x00000000 - - - GLBINTMSK - Global interrupt mask - 0 - 1 - - - NPTXFEMPLVL - Non-Periodic TxFIFO empty level - 7 - 1 - - - PTXFEMPLVL - Periodic TxFIFO empty - level - 8 - 1 - - - - - GUSBCFG - GUSBCFG - USB configuration register - (OTGFS_GUSBCFG) - 0xC - 0x20 - 0x00000A00 - - - TOUTCAL - FS timeout calibration - 0 - 3 - read-write - - - USBTRDTIM - USB turnaround time - 10 - 4 - read-write - - - FHSTMODE - Force host mode - 29 - 1 - read-write - - - FDEVMODE - Force device mode - 30 - 1 - read-write - - - COTXPKT - Corrupt Tx packet - 31 - 1 - read-write - - - - - GRSTCTL - GRSTCTL - OTGFS reset register - (OTGFS_GRSTCTL) - 0x10 - 0x20 - 0x20000000 - - - CSFTRST - Core soft reset - 0 - 1 - read-write - - - PIUSFTRST - PIU FS Dedicated Controller Soft Reset - 1 - 1 - read-write - - - FRMCNTRST - Host frame counter reset - 2 - 1 - read-write - - - RXFFLSH - RxFIFO flush - 4 - 1 - read-write - - - TXFFLSH - TxFIFO flush - 5 - 1 - read-write - - - TXFNUM - TxFIFO number - 6 - 5 - read-write - - - AHBIDLE - AHB master idle - 31 - 1 - read-only - - - - - GINTSTS - GINTSTS - OTGFS core interrupt register - (OTGFS_GINTSTS) - 0x14 - 0x20 - 0x04000020 - - - CURMOD - Current mode of operation - 0 - 1 - read-only - - - MODEMIS - Mode mismatch interrupt - 1 - 1 - read-write - - - OTGINT - OTG interrupt - 2 - 1 - read-only - - - SOF - Start of frame - 3 - 1 - read-write - - - RXFLVL - RxFIFO non-empty - 4 - 1 - read-only - - - NPTXFEMP - Non-periodic TxFIFO empty - 5 - 1 - read-only - - - GINNAKEFF - Global IN non-periodic NAK - effective - 6 - 1 - read-only - - - GOUTNAKEFF - Global OUT NAK effective - 7 - 1 - read-only - - - ERLYSUSP - Early suspend - 10 - 1 - read-write - - - USBSUSP - USB suspend - 11 - 1 - read-write - - - USBRST - USB reset - 12 - 1 - read-write - - - ENUMDONE - Enumeration done - 13 - 1 - read-write - - - ISOOUTDROP - Isochronous OUT packet dropped - interrupt - 14 - 1 - read-write - - - EOPF - End of periodic frame - interrupt - 15 - 1 - read-write - - - IEPTINT - IN endpoint interrupt - 18 - 1 - read-only - - - OEPTINT - OUT endpoint interrupt - 19 - 1 - read-only - - - INCOMPISOIN - Incomplete isochronous IN - transfer - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUT - Incomplete periodic transfer(Host - mode)/Incomplete isochronous OUT transfer(Device - mode) - 21 - 1 - read-write - - - PRTINT - Host port interrupt - 24 - 1 - read-only - - - HCHINT - Host channels interrupt - 25 - 1 - read-only - - - PTXFEMP - Periodic TxFIFO empty - 26 - 1 - read-only - - - CONIDSCHG - Connector ID status change - 28 - 1 - read-write - - - DISCONINT - Disconnect detected - interrupt - 29 - 1 - read-write - - - WKUPINT - Resume/remote wakeup detected - interrupt - 31 - 1 - read-write - - - - - GINTMSK - GINTMSK - OTG_FS interrupt mask register - (OTG_FS_GINTMSK) - 0x18 - 0x20 - 0x00000000 - - - MODEMISMSK - Mode mismatch interrupt - mask - 1 - 1 - read-write - - - OTGINTMSK - OTG interrupt mask - 2 - 1 - read-write - - - SOFMSK - Start of frame mask - 3 - 1 - read-write - - - RXFLVLMSK - Receive FIFO non-empty - mask - 4 - 1 - read-write - - - NPTXFEMPMSK - Non-periodic TxFIFO empty - mask - 5 - 1 - read-write - - - GINNAKEFFMSK - Global non-periodic IN NAK effective - mask - 6 - 1 - read-write - - - GOUTNAKEFFMSK - Global OUT NAK effective - mask - 7 - 1 - read-write - - - ERLYSUSPMSK - Early suspend mask - 10 - 1 - read-write - - - USBSUSPMSK - USB suspend mask - 11 - 1 - read-write - - - USBRSTMSK - USB reset mask - 12 - 1 - read-write - - - ENUMDONEMSK - Enumeration done mask - 13 - 1 - read-write - - - ISOOUTDROPMSK - Isochronous OUT packet dropped interrupt - mask - 14 - 1 - read-write - - - EOPFMSK - End of periodic frame interrupt - mask - 15 - 1 - read-write - - - IEPTINTMSK - IN endpoints interrupt - mask - 18 - 1 - read-write - - - OEPTINTMSK - OUT endpoints interrupt - mask - 19 - 1 - read-write - - - INCOMISOINMSK - Incomplete isochronous IN transfer - mask - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUTMSK - Incomplete periodic transfer mask(Host - mode)/Incomplete isochronous OUT transfer mask(Device - mode) - 21 - 1 - read-write - - - PRTINTMSK - Host port interrupt mask - 24 - 1 - read-only - - - HCHINTMSK - Host channels interrupt - mask - 25 - 1 - read-write - - - PTXFEMPMSK - Periodic TxFIFO empty mask - 26 - 1 - read-write - - - CONIDSCHGMSK - Connector ID status change - mask - 28 - 1 - read-write - - - DISCONINTMSK - Disconnect detected interrupt - mask - 29 - 1 - read-write - - - WKUPINTMSK - Resume/remote wakeup detected interrupt - mask - 31 - 1 - read-write - - - - - GRXSTSR_Device - GRXSTSR_Device - OTGFS Receive status debug read(Device - mode) - 0x1C - 0x20 - read-only - 0x00000000 - - - EPTNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - FN - Frame number - 21 - 4 - - - - - GRXSTSR_Host - GRXSTSR_Host - OTGFS Receive status debug read(Host - mode) - GRXSTSR_Device - 0x1C - 0x20 - read-only - 0x00000000 - - - CHNUM - Channel number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - - - GRXFSIZ - GRXFSIZ - OTGFS Receive FIFO size register - (OTGFS_GRXFSIZ) - 0x24 - 0x20 - read-write - 0x00000200 - - - RXFDEP - RxFIFO depth - 0 - 16 - - - - - DIEPTXF0 - DIEPTXF0 - IN Endpoint TxFIFO 0 transmit FIFO size - register (Device mode) - 0x28 - 0x20 - read-write - 0x00000200 - - - INEPT0TXSTADDR - Endpoint 0 transmit RAM start - address - 0 - 16 - - - INEPT0TXDEP - Endpoint 0 TxFIFO depth - 16 - 16 - - - - - GNPTXFSIZ - GNPTXFSIZ - OTGFS non-periodic transmit FIFO size - register (Host mode) - DIEPTXF0 - 0x28 - 0x20 - read-write - 0x00000200 - - - NPTXFSTADDR - Non-periodic Transmit RAM Start - address - 0 - 16 - - - NPTXFDEP - Non-periodic TxFIFO depth - 16 - 16 - - - - - GNPTXSTS - GNPTXSTS - OTGFS non-periodic transmit FIFO/queue - status register (OTGFS_GNPTXSTS) - 0x2C - 0x20 - read-only - 0x00080200 - - - NPTXFSPCAVAIL - Non-periodic TxFIFO space - available - 0 - 16 - - - NPTXQSPCAVAIL - Non-periodic transmit request queue - space available - 16 - 8 - - - NPTXQTOP - Top of the non-periodic transmit request - queue - 24 - 7 - - - - - GCCFG - GCCFG - OTGFS general core configuration register - (OTGFS_GCCFG) - 0x38 - 0x20 - read-write - 0x00000000 - - - PWRDOWN - Power down - 16 - 1 - - - LP_MODE - Low power mode - 17 - 1 - - - SOFOUTEN - SOF output enable - 20 - 1 - - - VBUSIG - VBUS Ignored - 21 - 1 - - - - - GUID - GUID - Product ID register - 0x3C - 0x20 - read-write - 0x00001000 - - - USERID - Product ID field - 0 - 32 - - - - - HPTXFSIZ - HPTXFSIZ - OTGFS Host periodic transmit FIFO size - register (OTGFS_HPTXFSIZ) - 0x100 - 0x20 - read-write - 0x02000600 - - - PTXFSTADDR - Host periodic TxFIFO start - address - 0 - 16 - - - PTXFSIZE - Host periodic TxFIFO depth - 16 - 16 - - - - - DIEPTXF1 - DIEPTXF1 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF1) - 0x104 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO1 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF2 - DIEPTXF2 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF2) - 0x108 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO2 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF3 - DIEPTXF3 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF3) - 0x10C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO3 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF4 - DIEPTXF4 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF4) - 0x110 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO4 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF5 - DIEPTXF5 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF5) - 0x114 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO5 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF6 - DIEPTXF6 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF6) - 0x118 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO6 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF7 - DIEPTXF7 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF7) - 0x11C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO7 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - - - USB_OTG2_HOST - USB on the go full speed - USB_OTG2 - 0x40040400 - - 0x0 - 0x400 - registers - - - - HCFG - HCFG - OTGFS host configuration register - (OTGFS_HCFG) - 0x0 - 0x20 - 0x00000000 - - - FSLSPCLKSEL - FS/LS PHY clock select - 0 - 2 - read-write - - - FSLSSUPP - FS- and LS-only support - 2 - 1 - read-only - - - - - HFIR - HFIR - OTGFS Host frame interval - register - 0x4 - 0x20 - read-write - 0x0000EA60 - - - FRINT - Frame interval - 0 - 16 - - - - - HFNUM - HFNUM - OTGFS host frame number/frame time - remaining register (OTGFS_HFNUM) - 0x8 - 0x20 - read-only - 0x00003FFF - - - FRNUM - Frame number - 0 - 16 - - - FTREM - Frame time remaining - 16 - 16 - - - - - HPTXSTS - HPTXSTS - OTGFS_Host periodic transmit FIFO/queue - status register (OTGFS_HPTXSTS) - 0x10 - 0x20 - 0x00080100 - - - PTXFSPCAVAIL - Periodic transmit data FIFO space - available - 0 - 16 - read-write - - - PTXQSPCAVAIL - Periodic transmit request queue space - available - 16 - 8 - read-only - - - PTXQTOP - Top of the periodic transmit request - queue - 24 - 8 - read-only - - - - - HAINT - HAINT - OTGFS Host all channels interrupt - register - 0x14 - 0x20 - read-only - 0x00000000 - - - HAINT - Channel interrupts - 0 - 16 - - - - - HAINTMSK - HAINTMSK - OTGFS host all channels interrupt mask - register - 0x18 - 0x20 - read-write - 0x00000000 - - - HAINTMSK - Channel interrupt mask - 0 - 16 - - - - - HPRT - HPRT - OTGFS host port control and status register - (OTGFS_HPRT) - 0x40 - 0x20 - 0x00000000 - - - PRTCONSTS - Port connect status - 0 - 1 - read-only - - - PRTCONDET - Port connect detected - 1 - 1 - read-write - - - PRTENA - Port enable - 2 - 1 - read-write - - - PRTENCHNG - Port enable/disable change - 3 - 1 - read-write - - - PRTOVRCACT - Port overcurrent active - 4 - 1 - read-only - - - PRTOVRCCHNG - Port overcurrent change - 5 - 1 - read-write - - - PRTRES - Port resume - 6 - 1 - read-write - - - PRTSUSP - Port suspend - 7 - 1 - read-write - - - PRTRST - Port reset - 8 - 1 - read-write - - - PRTLNSTS - Port line status - 10 - 2 - read-only - - - PRTPWR - Port power - 12 - 1 - read-write - - - PRTTSTCTL - Port test control - 13 - 4 - read-write - - - PRTSPD - Port speed - 17 - 2 - read-only - - - - - HCCHAR0 - HCCHAR0 - OTGFS host channel-0 characteristics - register (OTGFS_HCCHAR0) - 0x100 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR1 - HCCHAR1 - OTGFS host channel-1 characteristics - register (OTGFS_HCCHAR1) - 0x120 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR2 - HCCHAR2 - OTGFS host channel-2 characteristics - register (OTGFS_HCCHAR2) - 0x140 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR3 - HCCHAR3 - OTGFS host channel-3 characteristics - register (OTGFS_HCCHAR3) - 0x160 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR4 - HCCHAR4 - OTGFS host channel-4 characteristics - register (OTGFS_HCCHAR4) - 0x180 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR5 - HCCHAR5 - OTGFS host channel-5 characteristics - register (OTGFS_HCCHAR5) - 0x1A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR6 - HCCHAR6 - OTGFS host channel-6 characteristics - register (OTGFS_HCCHAR6) - 0x1C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR7 - HCCHAR7 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR7) - 0x1E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR8 - HCCHAR8 - OTGFS host channel-8 characteristics - register (OTGFS_HCCHAR8) - 0x200 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR9 - HCCHAR9 - OTGFS host channel-9 characteristics - register (OTGFS_HCCHAR9) - 0x220 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR10 - HCCHAR10 - OTGFS host channel-10 characteristics - register (OTGFS_HCCHAR10) - 0x240 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR11 - HCCHAR11 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR11) - 0x260 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR12 - HCCHAR12 - OTGFS host channel-12 characteristics - register (OTGFS_HCCHAR12) - 0x280 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR13 - HCCHAR13 - OTGFS host channel-13 characteristics - register (OTGFS_HCCHAR13) - 0x2A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR14 - HCCHAR14 - OTGFS host channel-14 characteristics - register (OTGFS_HCCHAR14) - 0x2C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR15 - HCCHAR15 - OTGFS host channel-15 characteristics - register (OTGFS_HCCHAR15) - 0x2E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCINT0 - HCINT0 - OTGFS host channel-0 interrupt register - (OTGFS_HCINT0) - 0x108 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT1 - HCINT1 - OTG_FS host channel-1 interrupt register - (OTG_FS_HCINT1) - 0x128 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT2 - HCINT2 - OTGFS host channel-2 interrupt register - (OTGFS_HCINT2) - 0x148 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT3 - HCINT3 - OTGFS host channel-3 interrupt register - (OTGFS_HCINT3) - 0x168 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT4 - HCINT4 - OTGFS host channel-4 interrupt register - (OTGFS_HCINT4) - 0x188 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT5 - HCINT5 - OTGFS host channel-5 interrupt register - (OTGFS_HCINT5) - 0x1A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT6 - HCINT6 - OTGFS host channel-6 interrupt register - (OTGFS_HCINT6) - 0x1C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT7 - HCINT7 - OTGFS host channel-7 interrupt register - (OTGFS_HCINT7) - 0x1E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT8 - HCINT8 - OTGFS host channel-8 interrupt register - (OTGFS_HCINT8) - 0x208 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT9 - HCINT9 - OTGFS host channel-9 interrupt register - (OTGFS_HCINT9) - 0x228 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT10 - HCINT10 - OTGFS host channel-10 interrupt register - (OTGFS_HCINT10) - 0x248 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT11 - HCINT11 - OTGFS host channel-11 interrupt register - (OTGFS_HCINT11) - 0x268 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT12 - HCINT12 - OTGFS host channel-12 interrupt register - (OTGFS_HCINT12) - 0x288 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT13 - HCINT13 - OTGFS host channel-13 interrupt register - (OTGFS_HCINT13) - 0x2A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT14 - HCINT14 - OTGFS host channel-14 interrupt register - (OTGFS_HCINT14) - 0x2C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT15 - HCINT15 - OTGFS host channel-15 interrupt register - (OTGFS_HCINT15) - 0x2E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINTMSK0 - HCINTMSK0 - OTGFS host channel-0 mask register - (OTGFS_HCINTMSK0) - 0x10C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK1 - HCINTMSK1 - OTGFS host channel-1 mask register - (OTGFS_HCINTMSK1) - 0x12C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK2 - HCINTMSK2 - OTGFS host channel-2 mask register - (OTGFS_HCINTMSK2) - 0x14C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK3 - HCINTMSK3 - OTGFS host channel-3 mask register - (OTGFS_HCINTMSK3) - 0x16C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK4 - HCINTMSK4 - OTGFS host channel-4 mask register - (OTGFS_HCINTMSK4) - 0x18C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK5 - HCINTMSK5 - OTGFS host channel-5 mask register - (OTGFS_HCINTMSK5) - 0x1AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK6 - HCINTMSK6 - OTGFS host channel-6 mask register - (OTGFS_HCINTMSK6) - 0x1CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK7 - HCINTMSK7 - OTGFS host channel-7 mask register - (OTGFS_HCINTMSK7) - 0x1EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK8 - HCINTMSK8 - OTGFS host channel-8 mask register - (OTGFS_HCINTMSK8) - 0x20C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK9 - HCINTMSK9 - OTGFS host channel-9 mask register - (OTGFS_HCINTMSK9) - 0x22C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK10 - HCINTMSK10 - OTGFS host channel-10 mask register - (OTGFS_HCINTMSK10) - 0x24C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK11 - HCINTMSK11 - OTGFS host channel-11 mask register - (OTGFS_HCINTMSK11) - 0x26C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK12 - HCINTMSK12 - OTGFS host channel-12 mask register - (OTGFS_HCINTMSK12) - 0x28C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK13 - HCINTMSK13 - OTGFS host channel-13 mask register - (OTGFS_HCINTMSK13) - 0x2AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK14 - HCINTMSK14 - OTGFS host channel-14 mask register - (OTGFS_HCINTMSK14) - 0x2CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK15 - HCINTMSK15 - OTGFS host channel-15 mask register - (OTGFS_HCINTMSK15) - 0x2EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCTSIZ0 - HCTSIZ0 - OTGFS host channel-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ1 - HCTSIZ1 - OTGFS host channel-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ2 - HCTSIZ2 - OTGFS host channel-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ3 - HCTSIZ3 - OTGFS host channel-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ4 - HCTSIZ4 - OTGFS host channel-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ5 - HCTSIZ5 - OTGFS host channel-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ6 - HCTSIZ6 - OTGFS host channel-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ7 - HCTSIZ7 - OTGFS host channel-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ8 - HCTSIZ8 - OTGFS host channel-8 transfer size - register - 0x210 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ9 - HCTSIZ9 - OTGFS host channel-9 transfer size - register - 0x230 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ10 - HCTSIZ10 - OTGFS host channel-10 transfer size - register - 0x250 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ11 - HCTSIZ11 - OTGFS host channel-11 transfer size - register - 0x270 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ12 - HCTSIZ12 - OTGFS host channel-12 transfer size - register - 0x290 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ13 - HCTSIZ13 - OTGFS host channel-13 transfer size - register - 0x2B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ14 - HCTSIZ14 - OTGFS host channel-14 transfer size - register - 0x2D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ15 - HCTSIZ15 - OTGFS host channel-15 transfer size - register - 0x2F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - - - USB_OTG2_DEVICE - USB on the go full speed - USB_OTG2 - 0x40040800 - - 0x0 - 0x400 - registers - - - - DCFG - DCFG - OTGFS device configuration register - (OTGFS_DCFG) - 0x0 - 0x20 - read-write - 0x02200000 - - - DEVSPD - Device speed - 0 - 2 - - - NZSTSOUTHSHK - Non-zero-length status OUT - handshake - 2 - 1 - - - DEVADDR - Device address - 4 - 7 - - - PERFRINT - Periodic frame interval - 11 - 2 - - - - - DCTL - DCTL - OTGFS device control register - (OTGFS_DCTL) - 0x4 - 0x20 - 0x00000000 - - - RWKUPSIG - Remote wakeup signaling - 0 - 1 - read-write - - - SFTDISCON - Soft disconnect - 1 - 1 - read-write - - - GNPINNAKSTS - Global IN NAK status - 2 - 1 - read-only - - - GOUTNAKSTS - Global OUT NAK status - 3 - 1 - read-only - - - TSTCTL - Test control - 4 - 3 - read-write - - - SGNPINNAK - Set global IN NAK - 7 - 1 - read-write - - - CGNPINNAK - Clear global IN NAK - 8 - 1 - read-write - - - SGOUTNAK - Set global OUT NAK - 9 - 1 - read-write - - - CGOUTNAK - Clear global OUT NAK - 10 - 1 - read-write - - - PWROPRGDNE - Power-on programming done - 11 - 1 - read-write - - - - - DSTS - DSTS - OTGFS device status register - (OTGFS_DSTS) - 0x8 - 0x20 - read-only - 0x00000010 - - - SUSPSTS - Suspend status - 0 - 1 - - - ENUMSPD - Enumerated speed - 1 - 2 - - - ETICERR - Erratic error - 3 - 1 - - - SOFFN - Frame number of the received - SOF - 8 - 14 - - - - - DIEPMSK - DIEPMSK - OTGFS device IN endpoint common interrupt - mask register (OTGFS_DIEPMSK) - 0x10 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - TIMEOUTMSK - Timeout condition mask (Non-isochronous - endpoints) - 3 - 1 - - - INTKNTXFEMPMSK - IN token received when TxFIFO empty - mask - 4 - 1 - - - INTKNEPTMISMSK - IN token received with EP mismatch - mask - 5 - 1 - - - INEPTNAKMSK - IN endpoint NAK effective - mask - 6 - 1 - - - TXFIFOUDRMSK - FIFO underrun - mask - 8 - 1 - - - BNAINMSK - BNA interrupt - mask - 9 - 1 - - - - - DOEPMSK - DOEPMSK - OTGFS device OUT endpoint common interrupt - mask register (OTGFS_DOEPMSK) - 0x14 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - SETUPMSK - SETUP phase done mask - 3 - 1 - - - OUTTEPDMSK - OUT token received when endpoint - disabled mask - 4 - 1 - - - B2BSETUPMSK - Back-to-back SETUP packets - received mask - 6 - 1 - - - OUTPERRMSK - OUT packet error - mask - 8 - 1 - - - BNAOUTMSK - BNA interrupt - mask - 9 - 1 - - - - - DAINT - DAINT - OTGFS device all endpoints interrupt - register (OTGFS_DAINT) - 0x18 - 0x20 - read-only - 0x00000000 - - - INEPTINT - IN endpoint interrupt bits - 0 - 16 - - - OUTEPTINT - OUT endpoint interrupt - bits - 16 - 16 - - - - - DAINTMSK - DAINTMSK - OTGFS all endpoints interrupt mask register - (OTGFS_DAINTMSK) - 0x1C - 0x20 - read-write - 0x00000000 - - - INEPTMSK - IN EP interrupt mask bits - 0 - 16 - - - OUTEPTMSK - OUT endpoint interrupt - bits - 16 - 16 - - - - - DIEPEMPMSK - DIEPEMPMSK - OTGFS device IN endpoint FIFO empty - interrupt mask register - 0x34 - 0x20 - read-write - 0x00000000 - - - INEPTXFEMSK - IN EP Tx FIFO empty interrupt mask - bits - 0 - 16 - - - - - DIEPCTL0 - DIEPCTL0 - OTGFS device control IN endpoint 0 control - register (OTGFS_DIEPCTL0) - 0x100 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 2 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-only - - - EPTENA - Endpoint enable - 31 - 1 - read-only - - - - - DIEPCTL1 - DIEPCTL1 - OTGFS device IN endpoint-1 control - register - 0x120 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL2 - DIEPCTL2 - OTGFS device IN endpoint-2 control - register - 0x140 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL3 - DIEPCTL3 - OTGFS device IN endpoint-3 control - register - 0x160 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL4 - DIEPCTL4 - OTGFS device IN endpoint-4 control - register - 0x180 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL5 - DIEPCTL5 - OTGFS device IN endpoint-5 control - register - 0x1A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL6 - DIEPCTL6 - OTGFS device IN endpoint-6 control - register - 0x1C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL7 - DIEPCTL7 - OTGFS device IN endpoint-7 control - register - 0x1E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL0 - DOEPCTL0 - OTGFS device OUT endpoint-0 control - register - 0x300 - 0x20 - 0x00008000 - - - MPS - Maximum packet size - 0 - 2 - read-only - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL1 - DOEPCTL1 - OTGFS device OUT endpoint-1 control - register - 0x320 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL2 - DOEPCTL2 - OTGFS device OUT endpoint-2 control - register - 0x340 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL3 - DOEPCTL3 - OTGFS device OUT endpoint-3 control - register - 0x360 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL4 - DOEPCTL4 - OTGFS device OUT endpoint-4 control - register - 0x380 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL5 - DOEPCTL5 - OTGFS device OUT endpoint-5 control - register - 0x3A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL6 - DOEPCTL6 - OTGFS device OUT endpoint-6 control - register - 0x3C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL7 - DOEPCTL7 - OTGFS device OUT endpoint-7 control - register - 0x3E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPINT0 - DIEPINT0 - OTGFS device IN endpoint-0 interrupt - register - 0x108 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT1 - DIEPINT1 - OTGFS device IN endpoint-1 interrupt - register - 0x128 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT2 - DIEPINT2 - OTGFS device IN endpoint-2 interrupt - register - 0x148 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT3 - DIEPINT3 - OTGFS device IN endpoint-3 interrupt - register - 0x168 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT4 - DIEPINT4 - OTGFS device IN endpoint-4 interrupt - register - 0x188 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT5 - DIEPINT5 - OTGFS device IN endpoint-5 interrupt - register - 0x1A8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT6 - DIEPINT6 - OTGFS device IN endpoint-6 interrupt - register - 0x1C8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT7 - DIEPINT7 - OTGFS device IN endpoint-7 interrupt - register - 0x1E8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DOEPINT0 - DOEPINT0 - OTGFS device OUT endpoint-0 interrupt - register - 0x308 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT1 - DOEPINT1 - OTGFS device OUT endpoint-1 interrupt - register - 0x328 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT2 - DOEPINT2 - OTGFS device OUT endpoint-2 interrupt - register - 0x348 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT3 - DOEPINT3 - OTGFS device OUT endpoint-3 interrupt - register - 0x368 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT4 - DOEPINT4 - OTGFS device OUT endpoint-4 interrupt - register - 0x388 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT5 - DOEPINT5 - OTGFS device OUT endpoint-5 interrupt - register - 0x3A8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT6 - DOEPINT6 - OTGFS device OUT endpoint-6 interrupt - register - 0x3C8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT7 - DOEPINT7 - OTGFS device OUT endpoint-7 interrupt - register - 0x3E8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DIEPTSIZ0 - DIEPTSIZ0 - OTGFS device IN endpoint-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 2 - - - - - DOEPTSIZ0 - DOEPTSIZ0 - OTGFS device OUT endpoint-0 transfer size - register - 0x310 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 1 - - - SETUPCNT - SETUP packet count - 29 - 2 - - - - - DIEPTSIZ1 - DIEPTSIZ1 - OTGFS device IN endpoint-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ2 - DIEPTSIZ2 - OTGFS device IN endpoint-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ3 - DIEPTSIZ3 - OTG device IN endpoint-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ4 - DIEPTSIZ4 - OTG device IN endpoint-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ5 - DIEPTSIZ5 - OTG device IN endpoint-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ6 - DIEPTSIZ6 - OTG device IN endpoint-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ7 - DIEPTSIZ7 - OTG device IN endpoint-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DTXFSTS0 - DTXFSTS0 - OTGFS device IN endpoint-0 transmit FIFO - status register - 0x118 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS1 - DTXFSTS1 - OTGFS device IN endpoint-1 transmit FIFO - status register - 0x138 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS2 - DTXFSTS2 - OTGFS device IN endpoint-2 transmit FIFO - status register - 0x158 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS3 - DTXFSTS3 - OTGFS device IN endpoint-3 transmit FIFO - status register - 0x178 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS4 - DTXFSTS4 - OTGFS device IN endpoint-4 transmit FIFO - status register - 0x198 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS5 - DTXFSTS5 - OTGFS device IN endpoint-5 transmit FIFO - status register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS6 - DTXFSTS6 - OTGFS device IN endpoint-6 transmit FIFO - status register - 0x1D8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS7 - DTXFSTS7 - OTGFS device IN endpoint-7 transmit FIFO - status register - 0x1F8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DOEPTSIZ1 - DOEPTSIZ1 - OTGFS device OUT endpoint-1 transfer size - register - 0x330 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ2 - DOEPTSIZ2 - OTGFS device OUT endpoint-2 transfer size - register - 0x350 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ3 - DOEPTSIZ3 - OTGFS device OUT endpoint-3 transfer size - register - 0x370 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ4 - DOEPTSIZ4 - OTGFS device OUT endpoint-4 transfer size - register - 0x390 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ5 - DOEPTSIZ5 - OTGFS device OUT endpoint-5 transfer size - register - 0x3B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ6 - DOEPTSIZ6 - OTGFS device OUT endpoint-6 transfer size - register - 0x3D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ7 - DOEPTSIZ7 - OTGFS device OUT endpoint-7 transfer size - register - 0x3F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - - - USB_OTG2_PWRCLK - USB on the go full speed - USB_OTG2 - 0x40040E00 - - 0x0 - 0x400 - registers - - - - PCGCCTL - PCGCCTL - OTGFS power and clock gating control - register (OTGFS_PCGCCTL) - 0x0 - 0x20 - 0x00000000 - - - STOPPCLK - Stop PHY clock - 0 - 1 - read-write - - - SUSPENDM - PHY Suspended - 4 - 1 - read-only - - - - - - - SCFG - System configuration controller - SCFG - 0x40013800 - - 0x0 - 0x400 - registers - - - - CFG1 - CFG1 - configuration register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - MEM_MAP_SEL - Memory address mapping selection bits - 0 - 3 - - - IR_POL - IR output polarity selection - 5 - 1 - - - IR_SRC_SEL - IR signal source selection - 6 - 2 - - - SWAP_XMC - XMC address mapping swap - 10 - 2 - - - - - CFG2 - CFG2 - configuration register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - MII_RMII_SEL - MII or RMII selection - bits - 23 - 1 - - - - - EXINTC1 - EXINTC1 - external interrupt configuration register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - EXINT3 - EXINT 3 configuration bits - 12 - 4 - - - EXINT2 - EXINT 2 configuration bits - 8 - 4 - - - EXINT1 - EXINT 1 configuration bits - 4 - 4 - - - EXINT0 - EXINT 0 configuration bits - 0 - 4 - - - - - EXINTC2 - EXINTC2 - external interrupt configuration register 2 - 0xC - 0x20 - read-write - 0x0000 - - - EXINT7 - EXINT 7 configuration bits - 12 - 4 - - - EXINT6 - EXINT 6 configuration bits - 8 - 4 - - - EXINT5 - EXINT 5 configuration bits - 4 - 4 - - - EXINT4 - EXINT 4 configuration bits - 0 - 4 - - - - - EXINTC3 - EXINTC3 - external interrupt configuration register 3 - 0x10 - 0x20 - read-write - 0x0000 - - - EXINT11 - EXINT 11 configuration bits - 12 - 4 - - - EXINT10 - EXINT 10 configuration bits - 8 - 4 - - - EXINT9 - EXINT 9 configuration bits - 4 - 4 - - - EXINT8 - EXINT 8 configuration bits - 0 - 4 - - - - - EXINTC4 - EXINTC4 - external interrupt configuration register - 4 - 0x14 - 0x20 - read-write - 0x0000 - - - EXINT15 - EXINT 15 configuration bits - 12 - 4 - - - EXINT14 - EXINT 14 configuration bits - 8 - 4 - - - EXINT13 - EXINT 13 configuration bits - 4 - 4 - - - EXINT12 - EXINT 12 configuration bits - 0 - 4 - - - - - UHDRV - UHDRV - Ultra high drive register - 0x2C - 0x20 - read-write - 0x0000 - - - PF15_UH - PF15 ultra high sourcing/sinking strength - 10 - 1 - - - PF14_UH - PF14 ultra high sourcing/sinking strength - 9 - 1 - - - PD15_UH - PD15 ultra high sourcing/sinking strength - 8 - 1 - - - PD14_UH - PD14 ultra high sourcing/sinking strength - 7 - 1 - - - PD13_UH - PD13 ultra high sourcing/sinking strength - 6 - 1 - - - PD12_UH - PD12 ultra high sourcing/sinking strength - 5 - 1 - - - PB10_UH - PB10 ultra high sourcing/sinking strength - 2 - 1 - - - PB9_UH - PB9 ultra high sourcing/sinking strength - 1 - 1 - - - PB3_UH - PB3 ultra high sourcing/sinking strength - 0 - 1 - - - - - - - QSPI1 - Quad SPI Controller - QSPI - 0xA0001000 - - 0x0 - 0x400 - registers - - - QSPI1 - QSPI1 global interrupt - 92 - - - - CMD_W0 - CMD_W0 - Command word 0 - 0x0 - 0x20 - read-write - 0x00000000 - - - SPIADR - SPI flash address - 0 - 32 - - - - - CMD_W1 - CMD_W1 - Command word 1 - 0x4 - 0x20 - read-write - 0x01000003 - - - ADRLEN - SPI address length - 0 - 3 - - - DUM2 - Second dummy state cycle - 16 - 8 - - - INSLEN - Instruction code length - 24 - 2 - - - PEMEN - Perfrmance enhance mode enable - 28 - 1 - - - - - CMD_W2 - CMD_W2 - Command word 2 - 0x8 - 0x20 - read-write - 0x01000003 - - - DCNT - Read write data counter - 0 - 32 - - - - - CMD_W3 - CMD_W3 - Command word 3 - 0xC - 0x20 - read-write - 0x00000000 - - - WEN - Write data enable - 1 - 1 - - - RSTSEN - Read spi status enable - 2 - 1 - - - RSTSC - Read spi status configure - 3 - 1 - - - OPMODE - SPI operate mode - 5 - 3 - - - PEMOPC - Performance enhance mode operate code - 16 - 8 - - - INSC - Instruction code - 24 - 8 - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00000000 - - - CLKDIV - SPI clock divider - 0 - 3 - - - SCKMODE - Sckout mode - 4 - 1 - - - XIPIDLE - XIP port idle status - 7 - 1 - - - ABORT - Abort instruction - 8 - 1 - - - BUSY - Busy bit of spi status - 16 - 3 - - - XIPRCMDF - XIP read command flush - 19 - 1 - - - XIPSEL - XIP port selection - 20 - 1 - - - KEYEN - encryption key enable - 21 - 1 - - - - - ACTR - ACTR - AC timing control register - 0x14 - 0x20 - read-write - 0x0000000F - - - CSDLY - CS delay - 0 - 4 - - - - - FIFOSTS - FIFOSTS - FIFO Status register - 0x18 - 0x20 - read-only - 0x00000001 - - - TXFIFORDY - TxFIFO ready status - 0 - 1 - - - RXFIFORDY - RxFIFO ready status - 1 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x20 - 0x20 - read-write - 0x00000001 - - - DMAEN - DMA handshake enable - 0 - 1 - - - CMDIE - Command complete interrupt enable - 1 - 1 - - - TXFIFOTHOD - TxFIFO thod - 8 - 2 - - - RXFIFOTHOD - RxFIFO thod - 12 - 2 - - - - - CMDSTS - CMDSTS - CMD status register - 0x24 - 0x20 - read-only - 0x00000000 - - - CMDSTS - Command complete status - 0 - 1 - - - - - RSTS - RSTS - SPI read status register - 0x28 - 0x20 - read-only - 0x00000000 - - - SPISTS - SPI read status - 0 - 8 - - - - - FSIZE - FSIZE - SPI flash size - 0x2C - 0x20 - read-write - 0x00000000 - - - SPIFSIZE - SPI flash size - 0 - 32 - - - - - XIP_CMD_W0 - XIP_CMD_W0 - XIP command word 0 - 0x30 - 0x20 - read-write - 0x00000000 - - - XIPR_DUM2 - XIP read second dummy cycle - 0 - 8 - - - XIPR_OPMODE - XIP read operate mode - 8 - 3 - - - XIPR_ADRLEN - XIP read address length - 11 - 1 - - - XIPR_INSC - XIP read instruction code - 12 - 8 - - - - - XIP_CMD_W1 - XIP_CMD_W1 - XIP command word 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - XIPW_DUM2 - XIP write second dummy cycle - 0 - 8 - - - XIPW_OPMODE - XIP write operate mode - 8 - 3 - - - XIPW_ADRLEN - XIP write address length - 11 - 1 - - - XIPW_INSC - XIP write instruction code - 12 - 8 - - - - - XIP_CMD_W2 - XIP_CMD_W2 - XIP command word 2 - 0x38 - 0x20 - read-write - 0x00000000 - - - XIPR_DCNT - XIP read data counter - 0 - 6 - - - XIPR_TCNT - XIP continue read cycle counter - 8 - 7 - - - XIPR_SEL - XIP read continue mode select - 15 - 1 - - - XIPW_DCNT - XIP write data counter - 16 - 6 - - - XIPW_TCNT - XIP continue write cycle counter - 24 - 7 - - - XIPW_SEL - XIP write continue mode select - 31 - 1 - - - - - XIP_CMD_W3 - XIP_CMD_W3 - XIP command word 3 - 0x3C - 0x20 - read-write - 0x00000000 - - - BYPASSC - Bypass cache function - 0 - 1 - - - CSTS - Cache status - 3 - 1 - - - - - REV - REV - Revision - 0x50 - 0x20 - read-write - 0x00010500 - - - REVISION - Revision number - 0 - 31 - - - - - DT - DT - 32/16/8 bit data port register - 0x100 - 0x20 - read-write - 0x00000000 - - - - - QSPI2 - 0xA0002000 - - QSPI2 - QSPI2 global interrupt - 91 - - - - ETHERNET_MAC - Ethernet: media access control - ETHERNET - 0x40028000 - - 0x0 - 0x100 - registers - - - EMAC - Ethernet mac global interrupt - 61 - - - - MACCTRL - MACCTRL - Ethernet MAC configuration register - 0x0 - 0x20 - read-write - 0x00008000 - - - RE - Receiver enable - 2 - 1 - - - TE - Transmitter enable - 3 - 1 - - - DC - Deferral check - 4 - 1 - - - BL - Back-off limit - 5 - 2 - - - ACS - Automatic pad/CRC - stripping - 7 - 1 - - - DR - Disable retry - 9 - 1 - - - IPC - IPv4 checksum offload - 10 - 1 - - - DM - Duplex mode - 11 - 1 - - - LM - Loopback mode - 12 - 1 - - - DRO - Disable receive own - 13 - 1 - - - FES - Fast EMAC speed - 14 - 1 - - - DCS - Disable carrier sense - 16 - 1 - - - IFG - Interframe gap - 17 - 3 - - - JD - Jabber disable - 22 - 1 - - - WD - Watchdog disable - 23 - 1 - - - - - MACFRMF - MACFRMF - Ethernet MAC frame filter register - 0x4 - 0x20 - read-write - 0x00000000 - - - PR - Promiscuous mode - 0 - 1 - - - HUC - Hash unicast - 1 - 1 - - - HMC - Hash multicast - 2 - 1 - - - DAIF - Destination address inverse - filtering - 3 - 1 - - - PMC - Pass multicast - 4 - 1 - - - DBF - Disable broadcast frames - 5 - 1 - - - PCF - Pass control frames - 6 - 2 - - - SAIF - Source address inverse - filtering - 8 - 1 - - - SAF - Source address filter - 9 - 1 - - - HPF - Hash or perfect filter - 10 - 1 - - - RA - Receive all - 31 - 1 - - - - - MACHTH - MACHTH - Ethernet MAC hash table high register - 0x8 - 0x20 - read-write - 0x00000000 - - - HTH - Hash table high - 0 - 32 - - - - - MACHTL - MACHTL - Ethernet MAC hash table low register - 0xC - 0x20 - read-write - 0x00000000 - - - HTL - Hash table low - 0 - 32 - - - - - MACMIIADDR - MACMIIADDR - Ethernet MAC MII address register - 0x10 - 0x20 - read-write - 0x00000000 - - - MB - MII busy - 0 - 1 - - - MW - MII write - 1 - 1 - - - CR - Clock range - 2 - 3 - - - MII - MII register - 6 - 5 - - - PA - PHY address - 11 - 5 - - - - - MACMIIDT - MACMIIDT - Ethernet MAC MII data register - 0x14 - 0x20 - read-write - 0x00000000 - - - MD - MII data - 0 - 16 - - - - - MACFCTRL - MACFCTRL - Ethernet MAC flow control register - 0x18 - 0x20 - read-write - 0x00000000 - - - FCB_BPA - Flow control busy/back pressure - activate - 0 - 1 - - - ETF - Enable transmit flow control - - 1 - 1 - - - ERF - Enable receive flow control - - 2 - 1 - - - DUP - Detect unicast pause frame - 3 - 1 - - - PLT - Pause low threshold - 4 - 2 - - - DZQP - Disable zero-quanta pause - 7 - 1 - - - PT - Pass time - 16 - 16 - - - - - MACVLT - MACVLT - Ethernet MAC VLAN tag register - 0x1C - 0x20 - read-write - 0x00000000 - - - VTI - VLAN tag identifier (for receive - frames) - 0 - 16 - - - ETV - Enable 12-bit VLAN tag comparison - 16 - 1 - - - - - MACRWFF - MACRWFF - Ethernet MAC remote wakeup frame filter register - 0x28 - 0x20 - read-write - 0x00000000 - - - MACPMTCTRLSTS - MACPMTCTRLSTS - Ethernet MAC PMT control and status register - 0x2C - 0x20 - read-write - 0x00000000 - - - PD - Power down - 0 - 1 - - - EMP - Enable magic packet - 1 - 1 - - - ERWF - Enable remote wakeup frame - 2 - 1 - - - RMP - Received magic packet - 5 - 1 - - - RRWF - Recevied remote wakeup frame - 6 - 1 - - - GUC - Global unicast - 9 - 1 - - - RWFFPR - Remote wakeup frame filter register pointer - reset - 31 - 1 - - - - - MACISTS - MACISTS - Ethernet MAC interrupt status register - 0x38 - 0x20 - read-write - 0x00000000 - - - PIS - PMT interrupt status - 3 - 1 - - - MIS - MMC interrupt status - 4 - 1 - - - MRIS - MMC receive interrupt status - 5 - 1 - - - MTIS - MMC transmit interrupt status - 6 - 1 - - - TIS - Timestamp interrupt status - 9 - 1 - - - - - MACIMR - MACIMR - Ethernet MAC interrupt mask register - 0x3C - 0x20 - read-write - 0x00000000 - - - PIM - PMT interrupt mask - 3 - 1 - - - TIM - Timestamp interrupt mask - 9 - 1 - - - - - MACA0H - MACA0H - Ethernet MAC address 0 high register - 0x40 - 0x20 - 0x0010FFFF - - - MA0H - MAC address0 high - 0 - 16 - read-write - - - AE - Address enable - 31 - 1 - read-only - - - - - MACA0L - MACA0L - Ethernet MAC address 0 low register - 0x44 - 0x20 - read-write - 0xFFFFFFFF - - - MA0L - MAC address0 low - 0 - 32 - - - - - MACA1H - MACA1H - Ethernet MAC address 1 high register - 0x48 - 0x20 - read-write - 0x0000FFFF - - - MA1H - MAC address1 high - 0 - 16 - - - MBC - Mask byte control - 24 - 6 - - - SA - Source address - 30 - 1 - - - AE - Address enable - 31 - 1 - - - - - MACA1L - MACA1L - Ethernet MAC address1 low register - 0x4C - 0x20 - read-write - 0xFFFFFFFF - - - MA1L - MAC address1 low - 0 - 32 - - - - - MACA2H - MACA2H - Ethernet MAC address 2 high register - 0x50 - 0x20 - read-write - 0x0050 - - - MA2H - MAC address 2 high - 0 - 16 - - - MBC - Mask byte control - 24 - 6 - - - SA - Source address - 30 - 1 - - - AE - Address enable - 31 - 1 - - - - - MACA2L - MACA2L - Ethernet MAC address 2 low register - 0x54 - 0x20 - read-write - 0xFFFFFFFF - - - MA2L - MAC address2 low - 0 - 31 - - - - - MACA3H - MACA3H - Ethernet MAC address 3 high register - 0x58 - 0x20 - read-write - 0x0000FFFF - - - MA3H - MAC address3 high - 0 - 16 - - - MBC - Mask byte control - 24 - 6 - - - SA - Source address - 30 - 1 - - - AE - Address enable - 31 - 1 - - - - - MACA3L - MACA3L - Ethernet MAC address 3 low register - 0x5C - 0x20 - read-write - 0xFFFFFFFF - - - MA3L - MAC address3 low - 0 - 32 - - - - - - - ETHERNET_MMC - Ethernet: MAC management counters - ETHERNET - 0x40028100 - - 0x0 - 0x100 - registers - - - - MMCCTRL - MMCCTRL - Ethernet MMC control register - 0x0 - 0x20 - read-write - 0x00000000 - - - RC - Reset counter - 0 - 1 - - - SCR - Stop counter rollover - 1 - 1 - - - RR - Reset on read - 2 - 1 - - - FMC - Freeze MMC counter - 31 - 1 - - - - - MMCRI - MMCRI - Ethernet MMC receive interrupt register - 0x4 - 0x20 - read-write - 0x00000000 - - - RFCE - Received frames CRC error - 5 - 1 - - - RFAE - Received frames alignment error - 6 - 1 - - - RGUF - Received good unicast frames - 17 - 1 - - - - - MMCTI - MMCTI - Ethernet MMC transmit interrupt register - 0x8 - 0x20 - read-write - 0x00000000 - - - TSCGFCI - Transmit single collision good frame - counter interrupt - 14 - 1 - - - TGFMSC - Transmit good frames more single - collision - 15 - 1 - - - TGF - Transmitted good frames - 21 - 1 - - - - - MMCRIM - MMCRIM - Ethernet MMC receive interrupt mask register - 0xC - 0x20 - read-write - 0x00000000 - - - RCEFCIM - Received CRC error frame counter interrupt - mask - 5 - 1 - - - RAEFACIM - Received alignment error frame alignment - counter interrupt mask - 6 - 1 - - - RUGFCIM - Received unicast good frame counter - interrupt mask - 17 - 1 - - - - - MMCTIM - MMCTIM - Ethernet MMC transmit interrupt mask register - 0x10 - 0x20 - read-write - 0x00000000 - - - TSCGFCIM - Transmit single collision good frame - counter interrupt mask - 14 - 1 - - - TMCGFCIM - Transmit multiple collision good frame - counter interrupt mask - 15 - 1 - - - TGFCIM - Transmitted good frame counter interrupt - mask - 21 - 1 - - - - - MMCTFSCC - MMCTFSCC - Ethernet MMC transmitted good frames after a single collision counter - 0x4C - 0x20 - read-only - 0x00000000 - - - TGFSCC - Transmitted good frames single - collision counter - 0 - 32 - - - - - MMCTFMSCC - MMCTFMSCC - Ethernet MMC transmitted good frames after more than a single collision - 0x50 - 0x20 - read-only - 0x00000000 - - - TGFMSCC - Transmitted good frame more single - collision counter - 0 - 32 - - - - - MMCTFCNT - MMCTFCNT - Ethernet MMC transmitted good frames counter register - 0x68 - 0x20 - read-only - 0x00000000 - - - TGFC - Transmitted good frames - counter - 0 - 32 - - - - - MMCRFCECNT - MMCRFCECNT - Ethernet MMC received frames with CRC error counter register - 0x94 - 0x20 - read-only - 0x00000000 - - - RFCEC - Received frames CRC error counter - 0 - 32 - - - - - MMCRFAECNT - MMCRFAECNT - Ethernet MMC received frames with alignment error counter register - 0x98 - 0x20 - read-only - 0x00000000 - - - RFAEC - Received frames alignment error counter - 0 - 32 - - - - - MMCRGUFCNT - MMCRGUFCNT - MMC received good unicast frames counter register - 0xC4 - 0x20 - read-only - 0x00000000 - - - RGUFC - Received good unicast frames - counter - 0 - 32 - - - - - - - ETHERNET_PTP - Ethernet: Precision time protocol - ETHERNET - 0x40028700 - - 0x0 - 0x100 - registers - - - - PTPTSCTRL - PTPTSCTRL - Ethernet PTP time stamp control register - 0x0 - 0x20 - read-write - 0x2000 - - - TE - Timestamp enable - 0 - 1 - - - TFCU - Timestamp fine or coarse - update - 1 - 1 - - - TI - Timestamp initialize - 2 - 1 - - - TU - Timestamp update - 3 - 1 - - - TITE - Timestamp interrupt trigger - enable - 4 - 1 - - - ARU - Addend register update - 5 - 1 - - - ETAF - Enable timestamp for all frames - 8 - 1 - - - TDBRC - Timestamp digital or binary - rollover control - 9 - 1 - - - EPPV2F - Enable PTP packet processing for - version2 format - 10 - 1 - - - EPPEF - Enable processing of PTP - over EMAC frames - 11 - 1 - - - EPPFSIP6U - Enable processing of PTP frames - sent over IPv6-UDP - 12 - 1 - - - EPPFSIP4U - Enable processing of PTP frames - sent over IPv4-UDP - 13 - 1 - - - ETSFEM - Enable timestamp snapshot for - event message - 14 - 1 - - - ESFMRTM - Enable snapshot for message - relevant to master - 15 - 1 - - - SPPFTS - Select PTP packet for taking snapshot - 16 - 2 - - - EMAFPFF - Enable MAC address for PTP frame filtering - 18 - 1 - - - - - PTPSSINC - PTPSSINC - Ethernet PTP subsecond increment register - 0x4 - 0x20 - read-write - 0x00000000 - - - SSIV - Sub-second increment value - 0 - 8 - - - - - PTPTSH - PTPTSH - Ethernet PTP time stamp high register - 0x8 - 0x20 - read-only - 0x00000000 - - - TS - Timestamp second - 0 - 32 - - - - - PTPTSL - PTPTSL - Ethernet PTP time stamp low register - 0xC - 0x20 - read-only - 0x00000000 - - - TSS - Timestamp subseconds - 0 - 31 - - - AST - Add or subtract time - 31 - 1 - - - - - PTPTSHUD - PTPTSHUD - Ethernet PTP time stamp high update register - 0x10 - 0x20 - read-write - 0x00000000 - - - TS - Timestamp second - 0 - 32 - - - - - PTPTSLUD - PTPTSLUD - Ethernet PTP time stamp low update register - 0x14 - 0x20 - read-write - 0x00000000 - - - TSS - Timestamp subseconds - 0 - 31 - - - AST - Add or subtract time - 31 - 1 - - - - - PTPTSAD - PTPTSAD - Ethernet PTP time stamp addend register - 0x18 - 0x20 - read-write - 0x00000000 - - - TAR - Timestamp addend register - 0 - 32 - - - - - PTPTTH - PTPTTH - Ethernet PTP target time high register - 0x1C - 0x20 - read-write - 0x00000000 - - - TTSR - Target time seconds register - 0 - 32 - - - - - PTPTTL - PTPTTL - Ethernet PTP target time low register - 0x20 - 0x20 - read-write - 0x00000000 - - - TTLR - Target timestamp low register - 0 - 32 - - - - - PTPTSSR - PTPTSSR - Ethernet PTP time stamp status register - 0x28 - 0x20 - read-only - 0x00000000 - - - TSO - Timestamp second overflow - 0 - 1 - - - TTTR - Timestamp target time reached - 1 - 1 - - - - - PTPPPSCR - PTPPPSCR - Ethernet PTP PPS control register - 0x2C - 0x20 - read-only - 0x00000000 - - - POFC - PPS Output frequency control - 0 - 4 - - - - - - - ETHERNET_DMA - Ethernet: DMA controller operation - ETHERNET - 0x40029000 - - 0x0 - 0x100 - registers - - - - DMABM - DMABM - Ethernet DMA bus mode register - 0x0 - 0x20 - read-write - 0x20101 - - - SWR - Software reset - 0 - 1 - - - DA - DMA Arbitration - 1 - 1 - - - DSL - Descriptor skip length - 2 - 5 - - - PBL - Programmable burst length - 8 - 6 - - - PR - Priority ratio - 14 - 2 - - - FB - Fixed burst - 16 - 1 - - - RDP - Rx DMA PBL - 17 - 6 - - - USP - Use separate PBL - 23 - 1 - - - PBLx8 - PNLx8 mode - 24 - 1 - - - AAB - Address-aligned beats - 25 - 1 - - - - - DMATPD - DMATPD - Ethernet DMA transmit poll demand register - 0x4 - 0x20 - read-write - 0x00000000 - - - TPD - Transmit poll demand - 0 - 32 - - - - - DMARPD - DMARPD - EHERNET DMA receive poll demand register - 0x8 - 0x20 - read-write - 0x00000000 - - - RPD - Receive poll demand - 0 - 32 - - - - - DMARDLADDR - DMARDLADDR - Ethernet DMA receive descriptor list address register - 0xC - 0x20 - read-write - 0x00000000 - - - SRL - Start of receive list - 0 - 32 - - - - - DMATDLADDR - DMATDLADDR - Ethernet DMA transmit descriptor list address register - 0x10 - 0x20 - read-write - 0x00000000 - - - STL - Start of transmit list - 0 - 32 - - - - - DMASTS - DMASTS - Ethernet DMA status register - 0x14 - 0x20 - 0x00000000 - - - TI - Transmit interrupt - 0 - 1 - read-write - - - TPS - Transmit process stopped - 1 - 1 - read-write - - - TBU - Transmit buffer unavailable - 2 - 1 - read-write - - - TJT - Transmit jabber timeout - 3 - 1 - read-write - - - OVF - Receive overflow - 4 - 1 - read-write - - - UNF - Transmit underflow - 5 - 1 - read-write - - - RI - Receive interrupt - 6 - 1 - read-write - - - RBU - Receive buffer unavailable - 7 - 1 - read-write - - - RPS - Receive process stopped - 8 - 1 - read-write - - - RWT - Receive watchdog timeout - 9 - 1 - read-write - - - ETI - Early transmit interrupt - 10 - 1 - read-write - - - FBEI - Fatal bus error interrupt - 13 - 1 - read-write - - - ERI - Early receive interrupt - 14 - 1 - read-write - - - AIS - Abnormal interrupt summary - 15 - 1 - read-write - - - NIS - Normal interrupt summary - 16 - 1 - read-write - - - RS - Receive process state - 17 - 3 - read-only - - - TS - Transmit process state - 20 - 3 - read-only - - - EB - Error bits - 23 - 3 - read-only - - - MMI - MAC MMC interrupt - 27 - 1 - read-only - - - MPI - MAC PMT interrupt - 28 - 1 - read-only - - - TTI - Timestamp trigger interrupt - 29 - 1 - read-only - - - - - DMAOPM - DMAOPM - Ethernet DMA operation mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - SSR - Start or stop receive - 1 - 1 - - - OSF - Operate on second frame - 2 - 1 - - - RTC - Receive threshold control - 3 - 2 - - - FUGF - Forward undersized good frames - 6 - 1 - - - FEF - Forward error frames - 7 - 1 - - - SSTC - Start of stop transmission command - 13 - 1 - - - TTC - Transmit threshold control - 14 - 3 - - - FTF - Flush transmit FIFO - 20 - 1 - - - TSF - Transmit store and forward - 21 - 1 - - - DFRF - Disable flushing of received - frames - 24 - 1 - - - RSF - Receive store and forward - 25 - 1 - - - DT - Disable dropping of TCP/IP - checksum error frames - 26 - 1 - - - - - DMAIE - DMAIE - Ethernet DMA interrupt enable register - 0x1C - 0x20 - read-write - 0x00000000 - - - TIE - Transmit interrupt enable - 0 - 1 - - - TSE - Transmit stopped enable - 1 - 1 - - - TUE - Transmit buffer unavailable enable - 2 - 1 - - - TJE - Transmit jabber timeout enable - 3 - 1 - - - OVE - Overflow interrupt enable - 4 - 1 - - - UNE - Underflow interrupt enable - 5 - 1 - - - RIE - Receive interrupt enable - 6 - 1 - - - RBUE - Receive buffer unavailable enable - 7 - 1 - - - RSE - Receive stopped enable - 8 - 1 - - - RWTE - receive watchdog timeout enable - 9 - 1 - - - EIE - Early transmit interrupt enable - 10 - 1 - - - FBEE - Fatal bus error enable - 13 - 1 - - - ERE - Early receive interrupt - enable - 14 - 1 - - - AIE - Abnormal interrupt enable - 15 - 1 - - - NIE - Normal interrupt enable - 16 - 1 - - - - - DMAMFBOCNT - DMAMFBOCNT - Ethernet DMA missed frame and buffer overflow counter register - 0x20 - 0x20 - read-only - 0x00000000 - - - MFC - Missed frames control - 0 - 16 - - - OBMFC - Overflow bit for missed frame - counter - 16 - 1 - - - OFC - Overflow frame counter - 17 - 11 - - - OBFOC - Overflow bit for FIFO overflow - counter - 28 - 1 - - - - - DMACTD - DMACTD - Ethernet DMA current host transmit descriptor register - 0x48 - 0x20 - read-only - 0x00000000 - - - HTDAP - Host transmit descriptor address pointer - 0 - 32 - - - - - DMACRD - DMACRD - Ethernet DMA current host receive descriptor register - 0x4C - 0x20 - read-only - 0x00000000 - - - HRDAP - Host receive descriptor address pointer - 0 - 32 - - - - - DMACTBADDR - DMACTBADDR - Ethernet DMA current host transmit buffer address register - 0x50 - 0x20 - read-only - 0x00000000 - - - HTBAP - Host transmit buffer address pointer - 0 - 32 - - - - - DMACRBADDR - DMACRBADDR - Ethernet DMA current host receive buffer address register - 0x54 - 0x20 - read-only - 0x00000000 - - - HRBAP - Host receive buffer address pointer - 0 - 32 - - - - - - - diff --git a/hw/bsp/at32f435_437/family.c b/hw/bsp/at32f435_437/family.c index c238fff32..03bb5674b 100644 --- a/hw/bsp/at32f435_437/family.c +++ b/hw/bsp/at32f435_437/family.c @@ -36,11 +36,11 @@ int inHandlerMode(void); //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void OTGFS1_IRQHandler(void) +void OTGFS1_IRQHandler(void) { tusb_int_handler(0, true); } -void OTGFS2_IRQHandler(void) +void OTGFS2_IRQHandler(void) { tusb_int_handler(1, true); } @@ -53,7 +53,7 @@ void OTGFS2_WKUP_IRQHandler(void) tusb_int_handler(1, true); } -void board_init(void) +void board_init(void) { /* config nvic priority group */ nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); @@ -185,7 +185,7 @@ void usb_clock48m_select(usb_clk48_s clk_s) } } -void led_and_botton_init(void) +void led_and_botton_init(void) { /* LED */ gpio_init_type gpio_led_init_struct; @@ -245,7 +245,7 @@ void uart_print_init(uint32_t baudrate) } // Get characters from UART. Return number of read bytes -int board_uart_read(uint8_t *buf, int len) +int board_uart_read(uint8_t *buf, int len) { (void) buf; (void) len; @@ -257,7 +257,7 @@ int board_uart_write(void const *buf, int len) #if CFG_TUSB_OS == OPT_OS_NONE int txsize = len; u16 timeout = 0xffff; - while (txsize--) + while (txsize--) { while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) { @@ -280,7 +280,7 @@ int board_uart_write(void const *buf, int len) int inHandlerMode(void) { - return __get_IPSR(); + return __get_IPSR(); } void usb_gpio_config(void) @@ -312,17 +312,17 @@ void usb_gpio_config(void) #endif } -void board_led_write(bool state) +void board_led_write(bool state) { gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); } -uint32_t board_button_read(void) +uint32_t board_button_read(void) { return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); } -size_t board_get_unique_id(uint8_t id[], size_t max_len) +size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); @@ -338,11 +338,11 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; - void SysTick_Handler(void) + void SysTick_Handler(void) { system_ticks++; } - uint32_t board_millis(void) + uint32_t board_millis(void) { return system_ticks; } @@ -354,7 +354,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) } #endif -void HardFault_Handler(void) +void HardFault_Handler(void) { __asm("BKPT #0\n"); } diff --git a/hw/bsp/at32f435_437/family.mk b/hw/bsp/at32f435_437/family.mk index 47731b621..f712a573d 100644 --- a/hw/bsp/at32f435_437/family.mk +++ b/hw/bsp/at32f435_437/family.mk @@ -1,6 +1,5 @@ # Submodules AT32F435_437_SDK = hw/mcu/artery/at32f435_437 -DEPS_SUBMODULES += $(AT32F435_437_SDK) # AT32 SDK path AT32F435_437_SDK_SRC = $(AT32F435_437_SDK)/libraries diff --git a/hw/bsp/at32f435_437/startup_at32f435_437.s b/hw/bsp/at32f435_437/startup_at32f435_437.s index aa1aa3f4a..70bc4ec89 100644 --- a/hw/bsp/at32f435_437/startup_at32f435_437.s +++ b/hw/bsp/at32f435_437/startup_at32f435_437.s @@ -78,7 +78,7 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array diff --git a/src/portable/synopsys/dwc2/dwc2_at32.h b/src/portable/synopsys/dwc2/dwc2_at32.h index 10832a702..1150d825b 100644 --- a/src/portable/synopsys/dwc2/dwc2_at32.h +++ b/src/portable/synopsys/dwc2/dwc2_at32.h @@ -109,13 +109,13 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) { (void) dwc2; // Enable on-chip HS PHY - if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) + if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) { - + } else if(hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) { - + } } -- cgit v1.3.1 From b531f43434779c5946973d141bf6dd942c5d946c Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 28 Jul 2025 22:58:32 +0700 Subject: add ci build for at32: f402_405, f403a_407, f423 --- .github/workflows/ci_set_matrix.py | 1 + .../boards/AT_START_F402_405/board.cmake | 6 + .../at32f402_405/boards/AT_START_F402_405/board.mk | 1 + hw/bsp/at32f402_405/family.c | 8 +- hw/bsp/at32f402_405/family.cmake | 122 +++++++++++++++++++++ hw/bsp/at32f402_405/family.mk | 2 +- .../boards/AT_START_F403A_407/board.cmake | 3 - hw/bsp/at32f403a_407/family.cmake | 18 ++- hw/bsp/at32f413/family.mk | 2 +- hw/bsp/at32f415/family.c | 8 +- hw/bsp/at32f415/family.mk | 2 +- hw/bsp/at32f423/boards/AT_START_F423/board.cmake | 3 - hw/bsp/at32f423/family.c | 4 +- hw/bsp/at32f423/family.cmake | 18 ++- hw/bsp/at32f425/family.c | 8 +- hw/bsp/at32f425/family.mk | 2 +- hw/bsp/at32f435_437/family.c | 8 +- hw/bsp/at32f435_437/family.mk | 2 +- 18 files changed, 193 insertions(+), 25 deletions(-) create mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/board.cmake create mode 100644 hw/bsp/at32f402_405/family.cmake diff --git a/.github/workflows/ci_set_matrix.py b/.github/workflows/ci_set_matrix.py index ddb3ee1fb..5fe805c82 100755 --- a/.github/workflows/ci_set_matrix.py +++ b/.github/workflows/ci_set_matrix.py @@ -15,6 +15,7 @@ toolchain_list = [ # family: [supported toolchain] family_list = { + "at32f403a_407 at32f423": ["arm-gcc"], "broadcom_32bit": ["arm-gcc"], "broadcom_64bit": ["aarch64-gcc"], "ch32v10x ch32v20x ch32v307 fomu gd32vf103": ["riscv-gcc"], diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.cmake b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.cmake new file mode 100644 index 000000000..f27d73d7b --- /dev/null +++ b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.cmake @@ -0,0 +1,6 @@ +set(MCU_VARIANT AT32F405RCT7) +set(JLINK_DEVICE ${MCU_VARIANT}) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT}) +endfunction() diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk index 527d3706b..e09211794 100644 --- a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk +++ b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk @@ -1,3 +1,4 @@ +JLINK_DEVICE = AT32F405RCT7 LD_FILE = $(BOARD_PATH)/AT32F405xC_FLASH.ld CFLAGS += \ diff --git a/hw/bsp/at32f402_405/family.c b/hw/bsp/at32f402_405/family.c index e6a3bce22..2dbc538b8 100644 --- a/hw/bsp/at32f402_405/family.c +++ b/hw/bsp/at32f402_405/family.c @@ -280,11 +280,15 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) } #endif -void HardFault_Handler(void) -{ +void HardFault_Handler(void) { __asm("BKPT #0\n"); } +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} + #ifdef USE_FULL_ASSERT void assert_failed(const char *file, uint32_t line) { diff --git a/hw/bsp/at32f402_405/family.cmake b/hw/bsp/at32f402_405/family.cmake new file mode 100644 index 000000000..2d2cdc026 --- /dev/null +++ b/hw/bsp/at32f402_405/family.cmake @@ -0,0 +1,122 @@ +include_guard() + +set(AT_FAMILY at32f402_405) +set(AT_SDK_LIB ${TOP}/hw/mcu/artery/${AT_FAMILY}/libraries) + +string(TOUPPER ${AT_FAMILY} AT_FAMILY_UPPER) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS ${AT_FAMILY_UPPER} CACHE INTERNAL "") + +# extract variant linker name +string(LENGTH ${MCU_VARIANT} MCU_VARIANT_LEN) +math(EXPR MCU_FLASH_CODE_INDEX "${MCU_VARIANT_LEN} - 3") +math(EXPR MCU_VARIANT_PREFIX_LEN "${MCU_FLASH_CODE_INDEX} - 1") +string(SUBSTRING ${MCU_VARIANT} ${MCU_FLASH_CODE_INDEX} 1 MCU_FLASH_CODE) +string(SUBSTRING ${MCU_VARIANT} 0 ${MCU_VARIANT_PREFIX_LEN} MCU_VARIANT_PREFIX) +set(MCU_LINKER_NAME ${MCU_VARIANT_PREFIX}x${MCU_FLASH_CODE}) + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/startup_${AT_FAMILY}.s) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT_FAMILY}.s) + + if (NOT DEFINED LD_FILE_GNU) + set(LD_FILE_GNU ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld) + endif () + set(LD_FILE_Clang ${LD_FILE_GNU}) + set(LD_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf) + + add_library(${BOARD_TARGET} STATIC + ${AT_SDK_LIB}/cmsis/cm4/device_support/system_${AT_FAMILY}.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_gpio.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_misc.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_usart.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_acc.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_crm.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${AT_SDK_LIB}/cmsis/cm4/core_support + ${AT_SDK_LIB}/cmsis/cm4/device_support + ${AT_SDK_LIB}/drivers/inc + ) + target_compile_definitions(${BOARD_TARGET} PUBLIC + BOARD_TUD_RHPORT=0 + BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + ) + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT_FAMILY}_clock.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT_FAMILY}_int.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_${AT_FAMILY_UPPER}) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c + ) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + + # Flashing + family_add_bin_hex(${TARGET}) + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/at32f402_405/family.mk b/hw/bsp/at32f402_405/family.mk index 461264561..91b5baffb 100644 --- a/hw/bsp/at32f402_405/family.mk +++ b/hw/bsp/at32f402_405/family.mk @@ -16,7 +16,7 @@ CFLAGS += \ -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED LDFLAGS_GCC += \ - -flto --specs=nosys.specs + -flto --specs=nosys.specs -nostdlib -nostartfiles SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake index fb45caf23..72ace807a 100644 --- a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake +++ b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake @@ -1,9 +1,6 @@ set(MCU_VARIANT AT32F403ACGU7) set(JLINK_DEVICE ${MCU_VARIANT}) -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/AT32F403AxG_FLASH.ld) -set(LD_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxG.icf) - function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT}) endfunction() diff --git a/hw/bsp/at32f403a_407/family.cmake b/hw/bsp/at32f403a_407/family.cmake index c121b166b..19b392015 100644 --- a/hw/bsp/at32f403a_407/family.cmake +++ b/hw/bsp/at32f403a_407/family.cmake @@ -3,6 +3,8 @@ include_guard() set(AT_FAMILY at32f403a_407) set(AT_SDK_LIB ${TOP}/hw/mcu/artery/${AT_FAMILY}/libraries) +string(TOUPPER ${AT_FAMILY} AT_FAMILY_UPPER) + # include board specific include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) @@ -10,7 +12,15 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(FAMILY_MCUS AT32F403A_407 CACHE INTERNAL "") +set(FAMILY_MCUS ${AT_FAMILY_UPPER} CACHE INTERNAL "") + +# extract variant linker name +string(LENGTH ${MCU_VARIANT} MCU_VARIANT_LEN) +math(EXPR MCU_FLASH_CODE_INDEX "${MCU_VARIANT_LEN} - 3") +math(EXPR MCU_VARIANT_PREFIX_LEN "${MCU_FLASH_CODE_INDEX} - 1") +string(SUBSTRING ${MCU_VARIANT} ${MCU_FLASH_CODE_INDEX} 1 MCU_FLASH_CODE) +string(SUBSTRING ${MCU_VARIANT} 0 ${MCU_VARIANT_PREFIX_LEN} MCU_VARIANT_PREFIX) +set(MCU_LINKER_NAME ${MCU_VARIANT_PREFIX}x${MCU_FLASH_CODE}) #------------------------------------ # BOARD_TARGET @@ -26,7 +36,11 @@ function(add_board_target BOARD_TARGET) set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) set(STARTUP_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT_FAMILY}.s) + if (NOT DEFINED LD_FILE_GNU) + set(LD_FILE_GNU ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld) + endif () set(LD_FILE_Clang ${LD_FILE_GNU}) + set(LD_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf) add_library(${BOARD_TARGET} STATIC ${AT_SDK_LIB}/cmsis/cm4/device_support/system_${AT_FAMILY}.c @@ -90,7 +104,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_AT32F403A_407) + family_add_tinyusb(${TARGET} OPT_MCU_${AT_FAMILY_UPPER}) target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) diff --git a/hw/bsp/at32f413/family.mk b/hw/bsp/at32f413/family.mk index a88c248dd..cf02445c0 100644 --- a/hw/bsp/at32f413/family.mk +++ b/hw/bsp/at32f413/family.mk @@ -15,7 +15,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_AT32F413 LDFLAGS_GCC += \ - -flto --specs=nosys.specs + -flto --specs=nosys.specs -nostdlib -nostartfiles SRC_C += \ src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ diff --git a/hw/bsp/at32f415/family.c b/hw/bsp/at32f415/family.c index 53897243a..516095dfb 100644 --- a/hw/bsp/at32f415/family.c +++ b/hw/bsp/at32f415/family.c @@ -271,11 +271,15 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) } #endif -void HardFault_Handler(void) -{ +void HardFault_Handler(void) { __asm("BKPT #0\n"); } +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} + #ifdef USE_FULL_ASSERT void assert_failed(const char *file, uint32_t line) { diff --git a/hw/bsp/at32f415/family.mk b/hw/bsp/at32f415/family.mk index 7af6a8cb8..1edf6be4e 100644 --- a/hw/bsp/at32f415/family.mk +++ b/hw/bsp/at32f415/family.mk @@ -15,7 +15,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_AT32F415 \ LDFLAGS_GCC += \ - -flto --specs=nosys.specs + -flto --specs=nosys.specs -nostdlib -nostartfiles SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ diff --git a/hw/bsp/at32f423/boards/AT_START_F423/board.cmake b/hw/bsp/at32f423/boards/AT_START_F423/board.cmake index 17e665a0b..45aa39900 100644 --- a/hw/bsp/at32f423/boards/AT_START_F423/board.cmake +++ b/hw/bsp/at32f423/boards/AT_START_F423/board.cmake @@ -1,9 +1,6 @@ set(MCU_VARIANT AT32F423VCT7) set(JLINK_DEVICE ${MCU_VARIANT}) -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/AT32F423xC_FLASH.ld) -set(LD_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/AT32F423xC.icf) - function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT}) endfunction() diff --git a/hw/bsp/at32f423/family.c b/hw/bsp/at32f423/family.c index afe3758ca..5e9e70dd8 100644 --- a/hw/bsp/at32f423/family.c +++ b/hw/bsp/at32f423/family.c @@ -262,8 +262,8 @@ void HardFault_Handler(void) { // Required by __libc_init_array in startup code if we are compiling using // -nostdlib/-nostartfiles. -// void _init(void) { -// } +void _init(void) { +} #ifdef USE_FULL_ASSERT void assert_failed(const char *file, uint32_t line) { diff --git a/hw/bsp/at32f423/family.cmake b/hw/bsp/at32f423/family.cmake index ebc855949..3845f13ad 100644 --- a/hw/bsp/at32f423/family.cmake +++ b/hw/bsp/at32f423/family.cmake @@ -3,6 +3,8 @@ include_guard() set(AT_FAMILY at32f423) set(AT_SDK_LIB ${TOP}/hw/mcu/artery/${AT_FAMILY}/libraries) +string(TOUPPER ${AT_FAMILY} AT_FAMILY_UPPER) + # include board specific include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) @@ -10,7 +12,15 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(FAMILY_MCUS AT32F423 CACHE INTERNAL "") +set(FAMILY_MCUS ${AT_FAMILY_UPPER} CACHE INTERNAL "") + +# extract variant linker name +string(LENGTH ${MCU_VARIANT} MCU_VARIANT_LEN) +math(EXPR MCU_FLASH_CODE_INDEX "${MCU_VARIANT_LEN} - 3") +math(EXPR MCU_VARIANT_PREFIX_LEN "${MCU_FLASH_CODE_INDEX} - 1") +string(SUBSTRING ${MCU_VARIANT} ${MCU_FLASH_CODE_INDEX} 1 MCU_FLASH_CODE) +string(SUBSTRING ${MCU_VARIANT} 0 ${MCU_VARIANT_PREFIX_LEN} MCU_VARIANT_PREFIX) +set(MCU_LINKER_NAME ${MCU_VARIANT_PREFIX}x${MCU_FLASH_CODE}) #------------------------------------ # BOARD_TARGET @@ -26,7 +36,11 @@ function(add_board_target BOARD_TARGET) set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) set(STARTUP_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT_FAMILY}.s) + if (NOT DEFINED LD_FILE_GNU) + set(LD_FILE_GNU ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld) + endif () set(LD_FILE_Clang ${LD_FILE_GNU}) + set(LD_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf) add_library(${BOARD_TARGET} STATIC ${AT_SDK_LIB}/cmsis/cm4/device_support/system_${AT_FAMILY}.c @@ -90,7 +104,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_AT32F423) + family_add_tinyusb(${TARGET} OPT_MCU_${AT_FAMILY_UPPER}) target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c diff --git a/hw/bsp/at32f425/family.c b/hw/bsp/at32f425/family.c index 7c2db9258..59a485210 100644 --- a/hw/bsp/at32f425/family.c +++ b/hw/bsp/at32f425/family.c @@ -282,11 +282,15 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) } #endif -void HardFault_Handler(void) -{ +void HardFault_Handler(void) { __asm("BKPT #0\n"); } +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} + #ifdef USE_FULL_ASSERT void assert_failed(const char *file, uint32_t line) { diff --git a/hw/bsp/at32f425/family.mk b/hw/bsp/at32f425/family.mk index 07b383ce9..81d5ffc97 100644 --- a/hw/bsp/at32f425/family.mk +++ b/hw/bsp/at32f425/family.mk @@ -15,7 +15,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_AT32F425 \ LDFLAGS_GCC += \ - -flto --specs=nosys.specs + -flto --specs=nosys.specs -nostdlib -nostartfiles SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ diff --git a/hw/bsp/at32f435_437/family.c b/hw/bsp/at32f435_437/family.c index 03bb5674b..af1fb30e0 100644 --- a/hw/bsp/at32f435_437/family.c +++ b/hw/bsp/at32f435_437/family.c @@ -354,11 +354,15 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) } #endif -void HardFault_Handler(void) -{ +void HardFault_Handler(void) { __asm("BKPT #0\n"); } +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} + #ifdef USE_FULL_ASSERT void assert_failed(const char *file, uint32_t line) { diff --git a/hw/bsp/at32f435_437/family.mk b/hw/bsp/at32f435_437/family.mk index f712a573d..891c7501c 100644 --- a/hw/bsp/at32f435_437/family.mk +++ b/hw/bsp/at32f435_437/family.mk @@ -15,7 +15,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_AT32F435_437 \ LDFLAGS_GCC += \ - -flto --specs=nosys.specs + -flto --specs=nosys.specs -nostdlib -nostartfiles SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ -- cgit v1.3.1 From b67e00892c726f27051b407486d9f0c04ff687f9 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 31 Jul 2025 21:52:59 +0700 Subject: add ci build for all at32, use linker and startup from mcu cmsis instead of local files --- .github/workflows/ci_set_matrix.py | 2 +- .../build_system/cmake/cpu/cortex-m4-nofpu.cmake | 30 ++ examples/build_system/make/cpu/cortex-m4-nofpu.mk | 20 + examples/device/net_lwip_webserver/skip.txt | 1 + .../boards/AT_START_F402_405/AT32F405xC_FLASH.ld | 154 ------ .../boards/AT_START_F402_405/board.cmake | 2 + .../at32f402_405/boards/AT_START_F402_405/board.mk | 8 +- hw/bsp/at32f402_405/family.cmake | 48 +- hw/bsp/at32f402_405/family.mk | 35 +- hw/bsp/at32f402_405/startup_at32f402_405.s | 486 ------------------ .../boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld | 154 ------ .../boards/AT_START_F403A_407/board.cmake | 2 + .../boards/AT_START_F403A_407/board.mk | 8 +- hw/bsp/at32f403a_407/family.cmake | 48 +- hw/bsp/at32f403a_407/family.mk | 32 +- hw/bsp/at32f403a_407/startup_at32f403a_407.s | 478 ----------------- .../boards/AT_START_F413/AT32F413xC_FLASH.ld | 168 ------ hw/bsp/at32f413/boards/AT_START_F413/board.cmake | 8 + hw/bsp/at32f413/boards/AT_START_F413/board.mk | 8 +- hw/bsp/at32f413/family.c | 105 ++-- hw/bsp/at32f413/family.cmake | 108 ++++ hw/bsp/at32f413/family.mk | 32 +- hw/bsp/at32f413/startup_at32f413.s | 431 ---------------- .../boards/AT_START_F415/AT32F415xC_FLASH.ld | 154 ------ hw/bsp/at32f415/boards/AT_START_F415/board.cmake | 11 + hw/bsp/at32f415/boards/AT_START_F415/board.mk | 8 +- hw/bsp/at32f415/family.c | 208 ++++---- hw/bsp/at32f415/family.cmake | 108 ++++ hw/bsp/at32f415/family.mk | 33 +- hw/bsp/at32f415/startup_at32f415.s | 407 --------------- .../boards/AT_START_F423/AT32F423xC_FLASH.ld | 154 ------ hw/bsp/at32f423/boards/AT_START_F423/board.cmake | 2 + hw/bsp/at32f423/boards/AT_START_F423/board.mk | 8 +- hw/bsp/at32f423/family.cmake | 48 +- hw/bsp/at32f423/family.mk | 34 +- hw/bsp/at32f423/startup_at32f423.s | 483 ----------------- .../boards/AT_START_F425/AT32F425x8_FLASH.ld | 153 ------ hw/bsp/at32f425/boards/AT_START_F425/board.cmake | 12 + hw/bsp/at32f425/boards/AT_START_F425/board.mk | 9 +- hw/bsp/at32f425/family.c | 159 +++--- hw/bsp/at32f425/family.cmake | 108 ++++ hw/bsp/at32f425/family.mk | 33 +- hw/bsp/at32f425/startup_at32f425.s | 309 ----------- .../boards/AT_START_F435_437/AT32F437xM_FLASH.ld | 154 ------ .../boards/AT_START_F435_437/board.cmake | 8 + .../at32f435_437/boards/AT_START_F435_437/board.mk | 7 +- hw/bsp/at32f435_437/family.c | 177 +++---- hw/bsp/at32f435_437/family.cmake | 114 +++++ hw/bsp/at32f435_437/family.mk | 36 +- hw/bsp/at32f435_437/startup_at32f435_437.s | 569 --------------------- 50 files changed, 1030 insertions(+), 4844 deletions(-) create mode 100644 examples/build_system/cmake/cpu/cortex-m4-nofpu.cmake create mode 100644 examples/build_system/make/cpu/cortex-m4-nofpu.mk delete mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xC_FLASH.ld delete mode 100644 hw/bsp/at32f402_405/startup_at32f402_405.s delete mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld delete mode 100644 hw/bsp/at32f403a_407/startup_at32f403a_407.s delete mode 100644 hw/bsp/at32f413/boards/AT_START_F413/AT32F413xC_FLASH.ld create mode 100644 hw/bsp/at32f413/boards/AT_START_F413/board.cmake create mode 100644 hw/bsp/at32f413/family.cmake delete mode 100644 hw/bsp/at32f413/startup_at32f413.s delete mode 100644 hw/bsp/at32f415/boards/AT_START_F415/AT32F415xC_FLASH.ld create mode 100644 hw/bsp/at32f415/boards/AT_START_F415/board.cmake create mode 100644 hw/bsp/at32f415/family.cmake delete mode 100644 hw/bsp/at32f415/startup_at32f415.s delete mode 100644 hw/bsp/at32f423/boards/AT_START_F423/AT32F423xC_FLASH.ld delete mode 100644 hw/bsp/at32f423/startup_at32f423.s delete mode 100644 hw/bsp/at32f425/boards/AT_START_F425/AT32F425x8_FLASH.ld create mode 100644 hw/bsp/at32f425/boards/AT_START_F425/board.cmake create mode 100644 hw/bsp/at32f425/family.cmake delete mode 100644 hw/bsp/at32f425/startup_at32f425.s delete mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xM_FLASH.ld create mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/board.cmake create mode 100644 hw/bsp/at32f435_437/family.cmake delete mode 100644 hw/bsp/at32f435_437/startup_at32f435_437.s diff --git a/.github/workflows/ci_set_matrix.py b/.github/workflows/ci_set_matrix.py index 5fe805c82..4870ec28e 100755 --- a/.github/workflows/ci_set_matrix.py +++ b/.github/workflows/ci_set_matrix.py @@ -15,7 +15,7 @@ toolchain_list = [ # family: [supported toolchain] family_list = { - "at32f403a_407 at32f423": ["arm-gcc"], + "at32f402_405 at32f403a_407 at32f413 at32f415 at32f423 at32f425 at32f435_437": ["arm-gcc"], "broadcom_32bit": ["arm-gcc"], "broadcom_64bit": ["aarch64-gcc"], "ch32v10x ch32v20x ch32v307 fomu gd32vf103": ["riscv-gcc"], diff --git a/examples/build_system/cmake/cpu/cortex-m4-nofpu.cmake b/examples/build_system/cmake/cpu/cortex-m4-nofpu.cmake new file mode 100644 index 000000000..eec924986 --- /dev/null +++ b/examples/build_system/cmake/cpu/cortex-m4-nofpu.cmake @@ -0,0 +1,30 @@ +if (TOOLCHAIN STREQUAL "gcc") + set(TOOLCHAIN_COMMON_FLAGS + -mthumb + -mcpu=cortex-m4 + -mfloat-abi=soft + ) + if (NOT DEFINED FREERTOS_PORT) + set(FREERTOS_PORT GCC_ARM_CM3 CACHE INTERNAL "") + endif () + +elseif (TOOLCHAIN STREQUAL "clang") + set(TOOLCHAIN_COMMON_FLAGS + --target=arm-none-eabi + -mcpu=cortex-m4 + ) + if (NOT DEFINED FREERTOS_PORT) + set(FREERTOS_PORT GCC_ARM_CM3 CACHE INTERNAL "") + endif () + +elseif (TOOLCHAIN STREQUAL "iar") + set(TOOLCHAIN_COMMON_FLAGS + --cpu cortex-m4 + --fpu none + ) + + if (NOT DEFINED FREERTOS_PORT) + set(FREERTOS_PORT IAR_ARM_CM3 CACHE INTERNAL "") + endif () + +endif () diff --git a/examples/build_system/make/cpu/cortex-m4-nofpu.mk b/examples/build_system/make/cpu/cortex-m4-nofpu.mk new file mode 100644 index 000000000..ac2916005 --- /dev/null +++ b/examples/build_system/make/cpu/cortex-m4-nofpu.mk @@ -0,0 +1,20 @@ +ifeq ($(TOOLCHAIN),gcc) + CFLAGS += \ + -mthumb \ + -mcpu=cortex-m4 \ + -mfloat-abi=soft + +else ifeq ($(TOOLCHAIN),clang) + CFLAGS += \ + --target=arm-none-eabi \ + -mcpu=cortex-m4 + +else ifeq ($(TOOLCHAIN),iar) + CFLAGS += --cpu cortex-m4 --fpu none + ASFLAGS += --cpu cortex-m4 --fpu none + +else + $(error "TOOLCHAIN is not supported") +endif + +FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM3 diff --git a/examples/device/net_lwip_webserver/skip.txt b/examples/device/net_lwip_webserver/skip.txt index 20a264387..6f66efb53 100644 --- a/examples/device/net_lwip_webserver/skip.txt +++ b/examples/device/net_lwip_webserver/skip.txt @@ -15,6 +15,7 @@ mcu:STM32N6 family:broadcom_64bit family:broadcom_32bit family:espressif +board:AT_START_F425 board:curiosity_nano board:frdm_kl25z # lpc55 has weird error 'ncm_interface' causes a section type conflict with 'ntb_parameters' diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xC_FLASH.ld b/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xC_FLASH.ld deleted file mode 100644 index 0b3550ddb..000000000 --- a/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xC_FLASH.ld +++ /dev/null @@ -1,154 +0,0 @@ -/* -***************************************************************************** -** -** File : AT32F405xC_FLASH.ld -** -** Abstract : Linker script for AT32F405xC Device with -** 256KByte FLASH, 102KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : Artery Tek AT32 -** -** Environment : Arm gcc toolchain -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20019800; /* end of RAM */ - -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x2000; /* required amount of heap */ -_Min_Stack_Size = 0x4000; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 102K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.cmake b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.cmake index f27d73d7b..0d09680a1 100644 --- a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.cmake +++ b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.cmake @@ -1,4 +1,6 @@ set(MCU_VARIANT AT32F405RCT7) +set(MCU_LINKER_NAME AT32F405xC) + set(JLINK_DEVICE ${MCU_VARIANT}) function(update_board TARGET) diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk index e09211794..25a719ccf 100644 --- a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk +++ b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk @@ -1,5 +1,7 @@ -JLINK_DEVICE = AT32F405RCT7 -LD_FILE = $(BOARD_PATH)/AT32F405xC_FLASH.ld +MCU_VARIANT = AT32F405RCT7 +MCU_LINKER_NAME = AT32F405xC + +JLINK_DEVICE = ${MCU_VARIANT} CFLAGS += \ - -DAT32F405RCT7 + -D${MCU_VARIANT} diff --git a/hw/bsp/at32f402_405/family.cmake b/hw/bsp/at32f402_405/family.cmake index 2d2cdc026..010e36b88 100644 --- a/hw/bsp/at32f402_405/family.cmake +++ b/hw/bsp/at32f402_405/family.cmake @@ -1,9 +1,9 @@ include_guard() -set(AT_FAMILY at32f402_405) -set(AT_SDK_LIB ${TOP}/hw/mcu/artery/${AT_FAMILY}/libraries) +set(AT32_FAMILY at32f402_405) +set(AT32_SDK_LIB ${TOP}/hw/mcu/artery/${AT32_FAMILY}/libraries) -string(TOUPPER ${AT_FAMILY} AT_FAMILY_UPPER) +string(TOUPPER ${AT32_FAMILY} AT32_FAMILY_UPPER) # include board specific include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) @@ -12,15 +12,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(FAMILY_MCUS ${AT_FAMILY_UPPER} CACHE INTERNAL "") - -# extract variant linker name -string(LENGTH ${MCU_VARIANT} MCU_VARIANT_LEN) -math(EXPR MCU_FLASH_CODE_INDEX "${MCU_VARIANT_LEN} - 3") -math(EXPR MCU_VARIANT_PREFIX_LEN "${MCU_FLASH_CODE_INDEX} - 1") -string(SUBSTRING ${MCU_VARIANT} ${MCU_FLASH_CODE_INDEX} 1 MCU_FLASH_CODE) -string(SUBSTRING ${MCU_VARIANT} 0 ${MCU_VARIANT_PREFIX_LEN} MCU_VARIANT_PREFIX) -set(MCU_LINKER_NAME ${MCU_VARIANT_PREFIX}x${MCU_FLASH_CODE}) +set(FAMILY_MCUS ${AT32_FAMILY_UPPER} CACHE INTERNAL "") #------------------------------------ # BOARD_TARGET @@ -32,30 +24,30 @@ function(add_board_target BOARD_TARGET) endif () # Startup & Linker script - set(STARTUP_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/startup_${AT_FAMILY}.s) + set(STARTUP_FILE_GNU ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/startup_${AT32_FAMILY}.s) set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) - set(STARTUP_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT_FAMILY}.s) + set(STARTUP_FILE_IAR ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT32_FAMILY}.s) if (NOT DEFINED LD_FILE_GNU) - set(LD_FILE_GNU ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld) + set(LD_FILE_GNU ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld) endif () set(LD_FILE_Clang ${LD_FILE_GNU}) - set(LD_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf) + set(LD_FILE_IAR ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf) add_library(${BOARD_TARGET} STATIC - ${AT_SDK_LIB}/cmsis/cm4/device_support/system_${AT_FAMILY}.c - ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_gpio.c - ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_misc.c - ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_usart.c - ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_acc.c - ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_crm.c + ${AT32_SDK_LIB}/cmsis/cm4/device_support/system_${AT32_FAMILY}.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_gpio.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_misc.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_usart.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_acc.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_crm.c ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${AT_SDK_LIB}/cmsis/cm4/core_support - ${AT_SDK_LIB}/cmsis/cm4/device_support - ${AT_SDK_LIB}/drivers/inc + ${AT32_SDK_LIB}/cmsis/cm4/core_support + ${AT32_SDK_LIB}/cmsis/cm4/device_support + ${AT32_SDK_LIB}/drivers/inc ) target_compile_definitions(${BOARD_TARGET} PUBLIC BOARD_TUD_RHPORT=0 @@ -97,8 +89,8 @@ function(family_configure_example TARGET RTOS) # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT_FAMILY}_clock.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT_FAMILY}_int.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT32_FAMILY}_clock.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT32_FAMILY}_int.c ) target_include_directories(${TARGET} PUBLIC # family, hw, board @@ -108,7 +100,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_${AT_FAMILY_UPPER}) + family_add_tinyusb(${TARGET} OPT_MCU_${AT32_FAMILY_UPPER}) target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c diff --git a/hw/bsp/at32f402_405/family.mk b/hw/bsp/at32f402_405/family.mk index 91b5baffb..60a0f93e9 100644 --- a/hw/bsp/at32f402_405/family.mk +++ b/hw/bsp/at32f402_405/family.mk @@ -1,8 +1,5 @@ -# Submodules -AT32F402_405_SDK = hw/mcu/artery/at32f402_405 - -# AT32 SDK path -AT32F402_405_SDK_SRC = $(AT32F402_405_SDK)/libraries +AT32_FAMILY = at32f402_405 +AT32_SDK_LIB = hw/mcu/artery/${AT32_FAMILY}/libraries include $(TOP)/$(BOARD_PATH)/board.mk @@ -13,6 +10,7 @@ CFLAGS_GCC += \ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_AT32F402_405 \ + -DBOARD_TUD_RHPORT=0 \ -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED LDFLAGS_GCC += \ @@ -22,23 +20,26 @@ SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ src/portable/synopsys/dwc2/hcd_dwc2.c \ src/portable/synopsys/dwc2/dwc2_common.c \ - $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_gpio.c \ - $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_misc.c \ - $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_usart.c \ - $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_crm.c \ - $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_acc.c \ - $(AT32F402_405_SDK_SRC)/cmsis/cm4/device_support/system_at32f402_405.c + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_gpio.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_misc.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_usart.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_crm.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_acc.c \ + $(AT32_SDK_LIB)/cmsis/cm4/device_support/system_${AT32_FAMILY}.c INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(AT32F402_405_SDK_SRC)/drivers/inc \ - $(TOP)/$(AT32F402_405_SDK_SRC)/cmsis/cm4/core_support \ - $(TOP)/$(AT32F402_405_SDK_SRC)/cmsis/cm4/device_support + $(TOP)/$(AT32_SDK_LIB)/drivers/inc \ + $(TOP)/$(AT32_SDK_LIB)/cmsis/cm4/core_support \ + $(TOP)/$(AT32_SDK_LIB)/cmsis/cm4/device_support + +SRC_S_GCC += ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/startup_${AT32_FAMILY}.s +SRC_S_IAR += ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT32_FAMILY}.s -SRC_S += \ - $(FAMILY_PATH)/startup_at32f402_405.s +LD_FILE_GCC ?= ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld +LD_FILE_IAR ?= ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf # For freeRTOS port source -#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4 +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F flash: flash-atlink diff --git a/hw/bsp/at32f402_405/startup_at32f402_405.s b/hw/bsp/at32f402_405/startup_at32f402_405.s deleted file mode 100644 index 9b0dad9ef..000000000 --- a/hw/bsp/at32f402_405/startup_at32f402_405.s +++ /dev/null @@ -1,486 +0,0 @@ -/** - ****************************************************************************** - * @file startup_at32f402_405.s - * @brief at32f402_405 devices vector table for gcc toolchain. - * this module performs: - * - set the initial sp - * - set the initial pc == reset_handler, - * - set the vector table entries with the exceptions isr address - * - configure the clock system and the external sram to - * be used as data memory (optional, to be enabled by user) - * - branches to main in the c library (which eventually - * calls main()). - * after reset the cortex-m4 processor is in thread mode, - * priority is privileged, and the stack is set to main. - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system initialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDT_IRQHandler /* Window Watchdog Timer */ - .word PVM_IRQHandler /* PVM through EXINT Line detect */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */ - .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */ - .word FLASH_IRQHandler /* Flash */ - .word CRM_IRQHandler /* CRM */ - .word EXINT0_IRQHandler /* EXINT Line 0 */ - .word EXINT1_IRQHandler /* EXINT Line 1 */ - .word EXINT2_IRQHandler /* EXINT Line 2 */ - .word EXINT3_IRQHandler /* EXINT Line 3 */ - .word EXINT4_IRQHandler /* EXINT Line 4 */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ - .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ - .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ - .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ - .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ - .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ - .word ADC1_IRQHandler /* ADC1 */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SE_IRQHandler /* CAN1 SE */ - .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ - .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ - .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ - .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ - .word TMR1_CH_IRQHandler /* TMR1 Channel */ - .word TMR2_GLOBAL_IRQHandler /* TMR2 */ - .word TMR3_GLOBAL_IRQHandler /* TMR3 */ - .word TMR4_GLOBAL_IRQHandler /* TMR4 */ - .word I2C1_EVT_IRQHandler /* I2C1 Event */ - .word I2C1_ERR_IRQHandler /* I2C1 Error */ - .word I2C2_EVT_IRQHandler /* I2C2 Event */ - .word I2C2_ERR_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ - .word ERTCAlarm_IRQHandler /* ERTC Alarm through EXINT Line */ - .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */ - .word 0 /* Reserved */ - .word TMR13_GLOBAL_IRQHandler /* TMR13 */ - .word TMR14_GLOBAL_IRQHandler /* TMR14 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word SPI3_IRQHandler /* SPI3 */ - .word USART4_IRQHandler /* USART4 */ - .word USART5_IRQHandler /* USART5 */ - .word TMR6_GLOBAL_IRQHandler /* TMR6 */ - .word TMR7_GLOBAL_IRQHandler /* TMR7 */ - .word DMA2_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA2_Channel2_IRQHandler /* DMA1 Channel 2 */ - .word DMA2_Channel3_IRQHandler /* DMA1 Channel 3 */ - .word DMA2_Channel4_IRQHandler /* DMA1 Channel 4 */ - .word DMA2_Channel5_IRQHandler /* DMA1 Channel 5 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word OTGFS1_IRQHandler /* OTGFS1 */ - .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ - .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ - .word 0 /* Reserved */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EVT_IRQHandler /* I2C3 Event */ - .word I2C3_ERR_IRQHandler /* I2C3 Error */ - .word OTGHS_EP1_OUT_IRQHandler /* OTGHS endpoint1 out */ - .word OTGHS_EP1_IN_IRQHandler /* OTGHS endpoint1 in */ - .word OTGHS_WKUP_IRQHandler /* OTGHS Wakeup from suspend */ - .word OTGHS_IRQHandler /* OTGHS */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word FPU_IRQHandler /* FPU */ - .word UART7_IRQHandler /* UART7 */ - .word UART8_IRQHandler /* UART8 */ - .word 0 /* Reserved */ - .word I2SF5_IRQHandler /* I2SF5 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word QSPI1_IRQHandler /* QSPI1 */ - .word 0 /* Reserved */ - .word DMAMUX_IRQHandler /* DMAMUX */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word ACC_IRQHandler /* ACC */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDT_IRQHandler - .thumb_set WWDT_IRQHandler,Default_Handler - - .weak PVM_IRQHandler - .thumb_set PVM_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak ERTC_WKUP_IRQHandler - .thumb_set ERTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak CRM_IRQHandler - .thumb_set CRM_IRQHandler,Default_Handler - - .weak EXINT0_IRQHandler - .thumb_set EXINT0_IRQHandler,Default_Handler - - .weak EXINT1_IRQHandler - .thumb_set EXINT1_IRQHandler,Default_Handler - - .weak EXINT2_IRQHandler - .thumb_set EXINT2_IRQHandler,Default_Handler - - .weak EXINT3_IRQHandler - .thumb_set EXINT3_IRQHandler,Default_Handler - - .weak EXINT4_IRQHandler - .thumb_set EXINT4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SE_IRQHandler - .thumb_set CAN1_SE_IRQHandler,Default_Handler - - .weak EXINT9_5_IRQHandler - .thumb_set EXINT9_5_IRQHandler,Default_Handler - - .weak TMR1_BRK_TMR9_IRQHandler - .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler - - .weak TMR1_OVF_TMR10_IRQHandler - .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler - - .weak TMR1_TRG_HALL_TMR11_IRQHandler - .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler - - .weak TMR1_CH_IRQHandler - .thumb_set TMR1_CH_IRQHandler,Default_Handler - - .weak TMR2_GLOBAL_IRQHandler - .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler - - .weak TMR3_GLOBAL_IRQHandler - .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler - - .weak TMR4_GLOBAL_IRQHandler - .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler - - .weak I2C1_EVT_IRQHandler - .thumb_set I2C1_EVT_IRQHandler,Default_Handler - - .weak I2C1_ERR_IRQHandler - .thumb_set I2C1_ERR_IRQHandler,Default_Handler - - .weak I2C2_EVT_IRQHandler - .thumb_set I2C2_EVT_IRQHandler,Default_Handler - - .weak I2C2_ERR_IRQHandler - .thumb_set I2C2_ERR_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXINT15_10_IRQHandler - .thumb_set EXINT15_10_IRQHandler,Default_Handler - - .weak ERTCAlarm_IRQHandler - .thumb_set ERTCAlarm_IRQHandler,Default_Handler - - .weak OTGFS1_WKUP_IRQHandler - .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler - - .weak TMR13_GLOBAL_IRQHandler - .thumb_set TMR13_GLOBAL_IRQHandler,Default_Handler - - .weak TMR14_GLOBAL_IRQHandler - .thumb_set TMR14_GLOBAL_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak USART4_IRQHandler - .thumb_set USART4_IRQHandler,Default_Handler - - .weak USART5_IRQHandler - .thumb_set USART5_IRQHandler,Default_Handler - - .weak TMR6_GLOBAL_IRQHandler - .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler - - .weak TMR7_GLOBAL_IRQHandler - .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_IRQHandler - .thumb_set DMA2_Channel4_IRQHandler,Default_Handler - - .weak DMA2_Channel5_IRQHandler - .thumb_set DMA2_Channel5_IRQHandler,Default_Handler - - .weak OTGFS1_IRQHandler - .thumb_set OTGFS1_IRQHandler,Default_Handler - - .weak DMA2_Channel6_IRQHandler - .thumb_set DMA2_Channel6_IRQHandler,Default_Handler - - .weak DMA2_Channel7_IRQHandler - .thumb_set DMA2_Channel7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EVT_IRQHandler - .thumb_set I2C3_EVT_IRQHandler,Default_Handler - - .weak I2C3_ERR_IRQHandler - .thumb_set I2C3_ERR_IRQHandler,Default_Handler - - .weak OTGHS_EP1_OUT_IRQHandler - .thumb_set OTGHS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTGHS_EP1_IN_IRQHandler - .thumb_set OTGHS_EP1_IN_IRQHandler,Default_Handler - - .weak OTGHS_WKUP_IRQHandler - .thumb_set OTGHS_WKUP_IRQHandler,Default_Handler - - .weak OTGHS_IRQHandler - .thumb_set OTGHS_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak UART7_IRQHandler - .thumb_set UART7_IRQHandler,Default_Handler - - .weak UART8_IRQHandler - .thumb_set UART8_IRQHandler,Default_Handler - - .weak I2SF5_IRQHandler - .thumb_set I2SF5_IRQHandler,Default_Handler - - .weak QSPI1_IRQHandler - .thumb_set QSPI1_IRQHandler,Default_Handler - - .weak DMAMUX_IRQHandler - .thumb_set DMAMUX_IRQHandler ,Default_Handler - - .weak ACC_IRQHandler - .thumb_set ACC_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld deleted file mode 100644 index c3d8aca80..000000000 --- a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld +++ /dev/null @@ -1,154 +0,0 @@ -/* -***************************************************************************** -** -** File : AT32F403AxG_FLASH.ld -** -** Abstract : Linker script for AT32F403AxG Device with -** 1000KByte FLASH, 96KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : Artery Tek AT32 -** -** Environment : Arm gcc toolchain -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20018000; /* end of RAM */ - -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake index 72ace807a..25c9558f9 100644 --- a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake +++ b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake @@ -1,4 +1,6 @@ set(MCU_VARIANT AT32F403ACGU7) +set(MCU_LINKER_NAME AT32F403AxG) + set(JLINK_DEVICE ${MCU_VARIANT}) function(update_board TARGET) diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk index e309c86bb..9bb6843aa 100644 --- a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk +++ b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk @@ -1,5 +1,7 @@ -JLINK_DEVICE = at32f403acgu7 -LD_FILE = $(BOARD_PATH)/AT32F403AxG_FLASH.ld +MCU_VARIANT = AT32F403ACGU7 +MCU_LINKER_NAME = AT32F403AxG + +JLINK_DEVICE = ${MCU_VARIANT} CFLAGS += \ - -DAT32F403ACGU7 + -D${MCU_VARIANT} diff --git a/hw/bsp/at32f403a_407/family.cmake b/hw/bsp/at32f403a_407/family.cmake index 19b392015..ae4037088 100644 --- a/hw/bsp/at32f403a_407/family.cmake +++ b/hw/bsp/at32f403a_407/family.cmake @@ -1,9 +1,9 @@ include_guard() -set(AT_FAMILY at32f403a_407) -set(AT_SDK_LIB ${TOP}/hw/mcu/artery/${AT_FAMILY}/libraries) +set(AT32_FAMILY at32f403a_407) +set(AT32_SDK_LIB ${TOP}/hw/mcu/artery/${AT32_FAMILY}/libraries) -string(TOUPPER ${AT_FAMILY} AT_FAMILY_UPPER) +string(TOUPPER ${AT32_FAMILY} AT32_FAMILY_UPPER) # include board specific include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) @@ -12,15 +12,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(FAMILY_MCUS ${AT_FAMILY_UPPER} CACHE INTERNAL "") - -# extract variant linker name -string(LENGTH ${MCU_VARIANT} MCU_VARIANT_LEN) -math(EXPR MCU_FLASH_CODE_INDEX "${MCU_VARIANT_LEN} - 3") -math(EXPR MCU_VARIANT_PREFIX_LEN "${MCU_FLASH_CODE_INDEX} - 1") -string(SUBSTRING ${MCU_VARIANT} ${MCU_FLASH_CODE_INDEX} 1 MCU_FLASH_CODE) -string(SUBSTRING ${MCU_VARIANT} 0 ${MCU_VARIANT_PREFIX_LEN} MCU_VARIANT_PREFIX) -set(MCU_LINKER_NAME ${MCU_VARIANT_PREFIX}x${MCU_FLASH_CODE}) +set(FAMILY_MCUS ${AT32_FAMILY_UPPER} CACHE INTERNAL "") #------------------------------------ # BOARD_TARGET @@ -32,30 +24,30 @@ function(add_board_target BOARD_TARGET) endif () # Startup & Linker script - set(STARTUP_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/startup_${AT_FAMILY}.s) + set(STARTUP_FILE_GNU ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/startup_${AT32_FAMILY}.s) set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) - set(STARTUP_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT_FAMILY}.s) + set(STARTUP_FILE_IAR ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT32_FAMILY}.s) if (NOT DEFINED LD_FILE_GNU) - set(LD_FILE_GNU ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld) + set(LD_FILE_GNU ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld) endif () set(LD_FILE_Clang ${LD_FILE_GNU}) - set(LD_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf) + set(LD_FILE_IAR ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf) add_library(${BOARD_TARGET} STATIC - ${AT_SDK_LIB}/cmsis/cm4/device_support/system_${AT_FAMILY}.c - ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_gpio.c - ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_misc.c - ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_usart.c - ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_acc.c - ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_crm.c + ${AT32_SDK_LIB}/cmsis/cm4/device_support/system_${AT32_FAMILY}.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_gpio.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_misc.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_usart.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_acc.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_crm.c ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${AT_SDK_LIB}/cmsis/cm4/core_support - ${AT_SDK_LIB}/cmsis/cm4/device_support - ${AT_SDK_LIB}/drivers/inc + ${AT32_SDK_LIB}/cmsis/cm4/core_support + ${AT32_SDK_LIB}/cmsis/cm4/device_support + ${AT32_SDK_LIB}/drivers/inc ) update_board(${BOARD_TARGET}) @@ -93,8 +85,8 @@ function(family_configure_example TARGET RTOS) # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT_FAMILY}_clock.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT_FAMILY}_int.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT32_FAMILY}_clock.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT32_FAMILY}_int.c ) target_include_directories(${TARGET} PUBLIC # family, hw, board @@ -104,7 +96,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_${AT_FAMILY_UPPER}) + family_add_tinyusb(${TARGET} OPT_MCU_${AT32_FAMILY_UPPER}) target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) diff --git a/hw/bsp/at32f403a_407/family.mk b/hw/bsp/at32f403a_407/family.mk index b3210a6d4..c82d402ca 100644 --- a/hw/bsp/at32f403a_407/family.mk +++ b/hw/bsp/at32f403a_407/family.mk @@ -1,8 +1,5 @@ -# Submodules -AT32F403A_407_SDK = hw/mcu/artery/at32f403a_407 - -# AT32 SDK path -AT32F403A_407_SDK_SRC = $(AT32F403A_407_SDK)/libraries +AT32_FAMILY = at32f403a_407 +AT32_SDK_LIB = hw/mcu/artery/${AT32_FAMILY}/libraries include $(TOP)/$(BOARD_PATH)/board.mk @@ -19,21 +16,24 @@ LDFLAGS_GCC += \ SRC_C += \ src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ - $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_gpio.c \ - $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_misc.c \ - $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_usart.c \ - $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_acc.c \ - $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_crm.c \ - $(AT32F403A_407_SDK_SRC)/cmsis/cm4/device_support/system_at32f403a_407.c + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_gpio.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_misc.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_usart.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_acc.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_crm.c \ + $(AT32_SDK_LIB)/cmsis/cm4/device_support/system_${AT32_FAMILY}.c INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(AT32F403A_407_SDK_SRC)/drivers/inc \ - $(TOP)/$(AT32F403A_407_SDK_SRC)/cmsis/cm4/core_support \ - $(TOP)/$(AT32F403A_407_SDK_SRC)/cmsis/cm4/device_support + $(TOP)/$(AT32_SDK_LIB)/drivers/inc \ + $(TOP)/$(AT32_SDK_LIB)/cmsis/cm4/core_support \ + $(TOP)/$(AT32_SDK_LIB)/cmsis/cm4/device_support + +SRC_S_GCC += ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/startup_${AT32_FAMILY}.s +SRC_S_IAR += ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT32_FAMILY}.s -SRC_S += \ - $(FAMILY_PATH)/startup_at32f403a_407.s +LD_FILE_GCC ?= ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld +LD_FILE_IAR ?= ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf # For freeRTOS port source FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F diff --git a/hw/bsp/at32f403a_407/startup_at32f403a_407.s b/hw/bsp/at32f403a_407/startup_at32f403a_407.s deleted file mode 100644 index 3b81f2043..000000000 --- a/hw/bsp/at32f403a_407/startup_at32f403a_407.s +++ /dev/null @@ -1,478 +0,0 @@ -/** - ****************************************************************************** - * @file startup_at32f403a_407.s - * @brief at32f403a_407xx devices vector table for gcc toolchain. - * this module performs: - * - set the initial sp - * - set the initial pc == reset_handler, - * - set the vector table entries with the exceptions isr address - * - configure the clock system and the external sram to - * be used as data memory (optional, to be enabled by user) - * - branches to main in the c library (which eventually - * calls main()). - * after reset the cortex-m4 processor is in thread mode, - * priority is privileged, and the stack is set to main. - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system initialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDT_IRQHandler /* Window Watchdog Timer */ - .word PVM_IRQHandler /* PVM through EXINT Line detect */ - .word TAMPER_IRQHandler /* Tamper */ - .word RTC_IRQHandler /* RTC */ - .word FLASH_IRQHandler /* Flash */ - .word CRM_IRQHandler /* CRM */ - .word EXINT0_IRQHandler /* EXINT Line 0 */ - .word EXINT1_IRQHandler /* EXINT Line 1 */ - .word EXINT2_IRQHandler /* EXINT Line 2 */ - .word EXINT3_IRQHandler /* EXINT Line 3 */ - .word EXINT4_IRQHandler /* EXINT Line 4 */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ - .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ - .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ - .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ - .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ - .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ - .word ADC1_2_IRQHandler /* ADC1 & ADC2 */ - .word USBFS_H_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */ - .word USBFS_L_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SE_IRQHandler /* CAN1 SE */ - .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ - .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ - .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ - .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ - .word TMR1_CH_IRQHandler /* TMR1 Channel */ - .word TMR2_GLOBAL_IRQHandler /* TMR2 */ - .word TMR3_GLOBAL_IRQHandler /* TMR3 */ - .word TMR4_GLOBAL_IRQHandler /* TMR4 */ - .word I2C1_EVT_IRQHandler /* I2C1 Event */ - .word I2C1_ERR_IRQHandler /* I2C1 Error */ - .word I2C2_EVT_IRQHandler /* I2C2 Event */ - .word I2C2_ERR_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_I2S2EXT_IRQHandler /* SPI2 & I2S2EXT */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ - .word RTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */ - .word USBFSWakeUp_IRQHandler /* USB Wakeup from suspend */ - .word TMR8_BRK_TMR12_IRQHandler /* TMR8 Brake and TMR12 */ - .word TMR8_OVF_TMR13_IRQHandler /* TMR8 Overflow and TMR13 */ - .word TMR8_TRG_HALL_TMR14_IRQHandler /* TMR8 Trigger and hall and TMR14 */ - .word TMR8_CH_IRQHandler /* TMR8 Channel */ - .word ADC3_IRQHandler /* ADC3 */ - .word XMC_IRQHandler /* XMC */ - .word SDIO1_IRQHandler /* SDIO1 */ - .word TMR5_GLOBAL_IRQHandler /* TMR5 */ - .word SPI3_I2S3EXT_IRQHandler /* SPI3 & I2S3EXT */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TMR6_GLOBAL_IRQHandler /* TMR6 */ - .word TMR7_GLOBAL_IRQHandler /* TMR7 */ - .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */ - .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */ - .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */ - .word DMA2_Channel4_5_IRQHandler /* DMA2 Channel4 & Channel5 */ - .word SDIO2_IRQHandler /* SDIO2 */ - .word I2C3_EVT_IRQHandler /* I2C3 Event */ - .word I2C3_ERR_IRQHandler /* I2C3 Error */ - .word SPI4_IRQHandler /* SPI4 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SE_IRQHandler /* CAN2 SE */ - .word ACC_IRQHandler /* ACC */ - .word USBFS_MAPH_IRQHandler /* USB Map HP */ - .word USBFS_MAPL_IRQHandler /* USB Map LP */ - .word DMA2_Channel6_7_IRQHandler /* DMA2 Channel6 & Channel7 */ - .word USART6_IRQHandler /* USART6 */ - .word UART7_IRQHandler /* UART7 */ - .word UART8_IRQHandler /* UART8 */ - .word EMAC_IRQHandler /* EMAC */ - .word EMAC_WKUP_IRQHandler /* EMAC Wakeup */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDT_IRQHandler - .thumb_set WWDT_IRQHandler,Default_Handler - - .weak PVM_IRQHandler - .thumb_set PVM_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak CRM_IRQHandler - .thumb_set CRM_IRQHandler,Default_Handler - - .weak EXINT0_IRQHandler - .thumb_set EXINT0_IRQHandler,Default_Handler - - .weak EXINT1_IRQHandler - .thumb_set EXINT1_IRQHandler,Default_Handler - - .weak EXINT2_IRQHandler - .thumb_set EXINT2_IRQHandler,Default_Handler - - .weak EXINT3_IRQHandler - .thumb_set EXINT3_IRQHandler,Default_Handler - - .weak EXINT4_IRQHandler - .thumb_set EXINT4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak USBFS_H_CAN1_TX_IRQHandler - .thumb_set USBFS_H_CAN1_TX_IRQHandler,Default_Handler - - .weak USBFS_L_CAN1_RX0_IRQHandler - .thumb_set USBFS_L_CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SE_IRQHandler - .thumb_set CAN1_SE_IRQHandler,Default_Handler - - .weak EXINT9_5_IRQHandler - .thumb_set EXINT9_5_IRQHandler,Default_Handler - - .weak TMR1_BRK_TMR9_IRQHandler - .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler - - .weak TMR1_OVF_TMR10_IRQHandler - .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler - - .weak TMR1_TRG_HALL_TMR11_IRQHandler - .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler - - .weak TMR1_CH_IRQHandler - .thumb_set TMR1_CH_IRQHandler,Default_Handler - - .weak TMR2_GLOBAL_IRQHandler - .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler - - .weak TMR3_GLOBAL_IRQHandler - .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler - - .weak TMR4_GLOBAL_IRQHandler - .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler - - .weak I2C1_EVT_IRQHandler - .thumb_set I2C1_EVT_IRQHandler,Default_Handler - - .weak I2C1_ERR_IRQHandler - .thumb_set I2C1_ERR_IRQHandler,Default_Handler - - .weak I2C2_EVT_IRQHandler - .thumb_set I2C2_EVT_IRQHandler,Default_Handler - - .weak I2C2_ERR_IRQHandler - .thumb_set I2C2_ERR_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_I2S2EXT_IRQHandler - .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXINT15_10_IRQHandler - .thumb_set EXINT15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak USBFSWakeUp_IRQHandler - .thumb_set USBFSWakeUp_IRQHandler,Default_Handler - - .weak TMR8_BRK_TMR12_IRQHandler - .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler - - .weak TMR8_OVF_TMR13_IRQHandler - .thumb_set TMR8_OVF_TMR13_IRQHandler,Default_Handler - - .weak TMR8_TRG_HALL_TMR14_IRQHandler - .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler - - .weak TMR8_CH_IRQHandler - .thumb_set TMR8_CH_IRQHandler,Default_Handler - - .weak ADC3_IRQHandler - .thumb_set ADC3_IRQHandler,Default_Handler - - .weak XMC_IRQHandler - .thumb_set XMC_IRQHandler,Default_Handler - - .weak SDIO1_IRQHandler - .thumb_set SDIO1_IRQHandler,Default_Handler - - .weak TMR5_GLOBAL_IRQHandler - .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler - - .weak SPI3_I2S3EXT_IRQHandler - .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TMR6_GLOBAL_IRQHandler - .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler - - .weak TMR7_GLOBAL_IRQHandler - .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_5_IRQHandler - .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler - - .weak SDIO2_IRQHandler - .thumb_set SDIO2_IRQHandler,Default_Handler - - .weak I2C3_EVT_IRQHandler - .thumb_set I2C3_EVT_IRQHandler,Default_Handler - - .weak I2C3_ERR_IRQHandler - .thumb_set I2C3_ERR_IRQHandler,Default_Handler - - .weak SPI4_IRQHandler - .thumb_set SPI4_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler ,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler ,Default_Handler - - .weak CAN2_SE_IRQHandler - .thumb_set CAN2_SE_IRQHandler,Default_Handler - - .weak ACC_IRQHandler - .thumb_set ACC_IRQHandler,Default_Handler - - .weak USBFS_MAPH_IRQHandler - .thumb_set USBFS_MAPH_IRQHandler,Default_Handler - - .weak USBFS_MAPL_IRQHandler - .thumb_set USBFS_MAPL_IRQHandler,Default_Handler - - .weak DMA2_Channel6_7_IRQHandler - .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak UART7_IRQHandler - .thumb_set UART7_IRQHandler,Default_Handler - - .weak UART8_IRQHandler - .thumb_set UART8_IRQHandler,Default_Handler - - .weak EMAC_IRQHandler - .thumb_set EMAC_IRQHandler,Default_Handler - - .weak EMAC_WKUP_IRQHandler - .thumb_set EMAC_WKUP_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xC_FLASH.ld b/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xC_FLASH.ld deleted file mode 100644 index 9d95a7d3d..000000000 --- a/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xC_FLASH.ld +++ /dev/null @@ -1,168 +0,0 @@ -/* -***************************************************************************** -** -** File : AT32F413xC_FLASH.ld -** -** Abstract : Linker script for AT32F413xC Device with -** 256KByte FLASH, 32KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : Artery Tek AT32 -** -** Environment : Arm gcc toolchain -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20008000; /* end of RAM */ - -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K -SPIM (rx) : ORIGIN = 0x08400000, LENGTH = 16384K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - _spim_init_base = LOADADDR(.spim); - _spim_init_length = SIZEOF(.spim); - - .spim : - { - . = ALIGN(4); - _spim_start = .; /* create a global symbol at spim start */ - *(.spim) /* .spim sections */ - *(.spim*) /* .spim* sections */ - . = ALIGN(4); - _spim_end = .; /* define a global symbols at end of spim */ - } >SPIM - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/hw/bsp/at32f413/boards/AT_START_F413/board.cmake b/hw/bsp/at32f413/boards/AT_START_F413/board.cmake new file mode 100644 index 000000000..0a9cc4bbd --- /dev/null +++ b/hw/bsp/at32f413/boards/AT_START_F413/board.cmake @@ -0,0 +1,8 @@ +set(MCU_VARIANT AT32F413RCT7) +set(MCU_LINKER_NAME AT32F413xC) + +set(JLINK_DEVICE ${MCU_VARIANT}) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT}) +endfunction() diff --git a/hw/bsp/at32f413/boards/AT_START_F413/board.mk b/hw/bsp/at32f413/boards/AT_START_F413/board.mk index 28351265d..30fc6b9af 100644 --- a/hw/bsp/at32f413/boards/AT_START_F413/board.mk +++ b/hw/bsp/at32f413/boards/AT_START_F413/board.mk @@ -1,4 +1,8 @@ -LD_FILE = $(BOARD_PATH)/AT32F413xC_FLASH.ld +MCU_VARIANT = AT32F413RCT7 +MCU_LINKER_NAME = AT32F413xC + +JLINK_DEVICE = ${MCU_VARIANT} CFLAGS += \ - -DAT32F413RCT7 + -D${MCU_VARIANT} \ + -DCFG_EXAMPLE_VIDEO_READONLY diff --git a/hw/bsp/at32f413/family.c b/hw/bsp/at32f413/family.c index ffaf892e7..6e12c6015 100644 --- a/hw/bsp/at32f413/family.c +++ b/hw/bsp/at32f413/family.c @@ -25,8 +25,8 @@ */ #include "at32f413_clock.h" -#include "bsp/board_api.h" #include "board.h" +#include "bsp/board_api.h" void usb_clock48m_select(usb_clk48_s clk_s); void uart_print_init(uint32_t baudrate); @@ -50,8 +50,7 @@ void USBFSWakeUp_IRQHandler(void) { tud_int_handler(0); } -void board_init(void) -{ +void board_init(void) { system_clock_config(); /* config nvic priority group */ @@ -82,7 +81,7 @@ void board_init(void) gpio_default_para_init(&gpio_led_init_struct); /* configure the led gpio */ gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; gpio_led_init_struct.gpio_pins = LED_PIN; gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; @@ -114,10 +113,8 @@ void board_init(void) * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT * @retval none */ -void usb_clock48m_select(usb_clk48_s clk_s) -{ - if(clk_s == USB_CLK_HICK) - { +void usb_clock48m_select(usb_clk48_s clk_s) { + if (clk_s == USB_CLK_HICK) { crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); /* enable the acc calibration ready interrupt */ @@ -130,11 +127,8 @@ void usb_clock48m_select(usb_clk48_s clk_s) /* open acc calibration */ acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); - } - else - { - switch(system_core_clock) - { + } else { + switch (system_core_clock) { /* 48MHz */ case 48000000: crm_usb_clock_div_set(CRM_USB_DIV_1); @@ -176,8 +170,7 @@ void usb_clock48m_select(usb_clk48_s clk_s) } } -void uart_print_init(uint32_t baudrate) -{ +void uart_print_init(uint32_t baudrate) { gpio_init_type gpio_init_struct; /* enable the uart and gpio clock */ crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); @@ -185,7 +178,7 @@ void uart_print_init(uint32_t baudrate) gpio_default_para_init(&gpio_init_struct); /* configure the uart tx pin */ gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_init_struct.gpio_mode = GPIO_MODE_MUX; gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; gpio_init_struct.gpio_pull = GPIO_PULL_NONE; @@ -206,8 +199,8 @@ uint32_t board_button_read(void) { size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; - volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); - uint32_t* id32 = (uint32_t*) (uintptr_t) id; + volatile uint32_t *at32_uuid = ((volatile uint32_t *) 0x1FFFF7E8); + uint32_t *id32 = (uint32_t *) (uintptr_t) id; uint8_t const len = 12; id32[0] = at32_uuid[0]; @@ -223,61 +216,57 @@ int board_uart_read(uint8_t *buf, int len) { return 0; } -int board_uart_write(void const *buf, int len) -{ - #if CFG_TUSB_OS == OPT_OS_NONE - int txsize = len; - u16 timeout = 0xffff; - while (txsize--) - { - while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) - { - timeout--; - if(timeout == 0) - { - return 0; - } +int board_uart_write(void const *buf, int len) { +#if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) { + while (usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) { + timeout--; + if (timeout == 0) { + return 0; } - PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); - buf++; } - return len; - #else - (void) buf; - (void) len; - return 0; - #endif + PRINT_UART->dt = (*((uint8_t const *) buf) & 0x01FF); + buf++; + } + return len; +#else + (void) buf; + (void) len; + return 0; +#endif } #if CFG_TUSB_OS == OPT_OS_NONE - volatile uint32_t system_ticks = 0; - void SysTick_Handler(void) - { - system_ticks++; - } +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) { + system_ticks++; +} - uint32_t board_millis(void) - { - return system_ticks; - } +uint32_t board_millis(void) { + return system_ticks; +} - void SVC_Handler(void) - { - } +void SVC_Handler(void) { +} - void PendSV_Handler(void) - { - } +void PendSV_Handler(void) { +} #endif void HardFault_Handler(void) { __asm("BKPT #0\n"); } -#ifdef USE_FULL_ASSERT -void assert_failed(const char *file, uint32_t line) -{ +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) { /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ diff --git a/hw/bsp/at32f413/family.cmake b/hw/bsp/at32f413/family.cmake new file mode 100644 index 000000000..b534bcbbc --- /dev/null +++ b/hw/bsp/at32f413/family.cmake @@ -0,0 +1,108 @@ +include_guard() + +set(AT32_FAMILY at32f413) +set(AT32_SDK_LIB ${TOP}/hw/mcu/artery/${AT32_FAMILY}/libraries) + +string(TOUPPER ${AT32_FAMILY} AT32_FAMILY_UPPER) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS ${AT32_FAMILY_UPPER} CACHE INTERNAL "") + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/startup_${AT32_FAMILY}.s) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT32_FAMILY}.s) + + if (NOT DEFINED LD_FILE_GNU) + set(LD_FILE_GNU ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld) + endif () + set(LD_FILE_Clang ${LD_FILE_GNU}) + set(LD_FILE_IAR ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf) + + add_library(${BOARD_TARGET} STATIC + ${AT32_SDK_LIB}/cmsis/cm4/device_support/system_${AT32_FAMILY}.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_gpio.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_misc.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_usart.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_acc.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_crm.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${AT32_SDK_LIB}/cmsis/cm4/core_support + ${AT32_SDK_LIB}/cmsis/cm4/device_support + ${AT32_SDK_LIB}/drivers/inc + ) + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT32_FAMILY}_clock.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT32_FAMILY}_int.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_${AT32_FAMILY_UPPER}) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + ) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + + # Flashing + family_add_bin_hex(${TARGET}) + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/at32f413/family.mk b/hw/bsp/at32f413/family.mk index cf02445c0..9c5d867de 100644 --- a/hw/bsp/at32f413/family.mk +++ b/hw/bsp/at32f413/family.mk @@ -1,8 +1,5 @@ -# Submodules -AT32F413_SDK = hw/mcu/artery/at32f413 - -# AT32 SDK path -AT32F413_SDK_SRC = $(AT32F413_SDK)/libraries +AT32_FAMILY = at32f413 +AT32_SDK_LIB = hw/mcu/artery/${AT32_FAMILY}/libraries include $(TOP)/$(BOARD_PATH)/board.mk @@ -19,21 +16,24 @@ LDFLAGS_GCC += \ SRC_C += \ src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ - $(AT32F413_SDK_SRC)/drivers/src/at32f413_gpio.c \ - $(AT32F413_SDK_SRC)/drivers/src/at32f413_misc.c \ - $(AT32F413_SDK_SRC)/drivers/src/at32f413_usart.c \ - $(AT32F413_SDK_SRC)/drivers/src/at32f413_acc.c \ - $(AT32F413_SDK_SRC)/drivers/src/at32f413_crm.c \ - $(AT32F413_SDK_SRC)/cmsis/cm4/device_support/system_at32f413.c + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_gpio.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_misc.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_usart.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_acc.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_crm.c \ + $(AT32_SDK_LIB)/cmsis/cm4/device_support/system_${AT32_FAMILY}.c INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(AT32F413_SDK_SRC)/drivers/inc \ - $(TOP)/$(AT32F413_SDK_SRC)/cmsis/cm4/core_support \ - $(TOP)/$(AT32F413_SDK_SRC)/cmsis/cm4/device_support + $(TOP)/$(AT32_SDK_LIB)/drivers/inc \ + $(TOP)/$(AT32_SDK_LIB)/cmsis/cm4/core_support \ + $(TOP)/$(AT32_SDK_LIB)/cmsis/cm4/device_support + +SRC_S_GCC += ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/startup_${AT32_FAMILY}.s +SRC_S_IAR += ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT32_FAMILY}.s -SRC_S += \ - $(FAMILY_PATH)/startup_at32f413.s +LD_FILE_GCC ?= ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld +LD_FILE_IAR ?= ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf # For freeRTOS port source FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F diff --git a/hw/bsp/at32f413/startup_at32f413.s b/hw/bsp/at32f413/startup_at32f413.s deleted file mode 100644 index 42631da93..000000000 --- a/hw/bsp/at32f413/startup_at32f413.s +++ /dev/null @@ -1,431 +0,0 @@ -/** - ****************************************************************************** - * @file startup_at32f413.s - * @brief at32f413xx devices vector table for gcc toolchain. - * this module performs: - * - set the initial sp - * - set the initial pc == reset_handler, - * - set the vector table entries with the exceptions isr address - * - configure the clock system and the external sram to - * be used as data memory (optional, to be enabled by user) - * - branches to main in the c library (which eventually - * calls main()). - * after reset the cortex-m4 processor is in thread mode, - * priority is privileged, and the stack is set to main. - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system initialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDT_IRQHandler /* Window Watchdog Timer */ - .word PVM_IRQHandler /* PVM through EXINT Line detect */ - .word TAMPER_IRQHandler /* Tamper */ - .word RTC_IRQHandler /* RTC */ - .word FLASH_IRQHandler /* Flash */ - .word CRM_IRQHandler /* CRM */ - .word EXINT0_IRQHandler /* EXINT Line 0 */ - .word EXINT1_IRQHandler /* EXINT Line 1 */ - .word EXINT2_IRQHandler /* EXINT Line 2 */ - .word EXINT3_IRQHandler /* EXINT Line 3 */ - .word EXINT4_IRQHandler /* EXINT Line 4 */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ - .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ - .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ - .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ - .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ - .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ - .word ADC1_2_IRQHandler /* ADC1 & ADC2 */ - .word USBFS_H_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */ - .word USBFS_L_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SE_IRQHandler /* CAN1 SE */ - .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ - .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ - .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ - .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ - .word TMR1_CH_IRQHandler /* TMR1 Channel */ - .word TMR2_GLOBAL_IRQHandler /* TMR2 */ - .word TMR3_GLOBAL_IRQHandler /* TMR3 */ - .word TMR4_GLOBAL_IRQHandler /* TMR4 */ - .word I2C1_EVT_IRQHandler /* I2C1 Event */ - .word I2C1_ERR_IRQHandler /* I2C1 Error */ - .word I2C2_EVT_IRQHandler /* I2C2 Event */ - .word I2C2_ERR_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* Reserved */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ - .word RTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */ - .word USBFSWakeUp_IRQHandler /* USB Wakeup from suspend */ - .word TMR8_BRK_IRQHandler /* TMR8 Brake */ - .word TMR8_OVF_IRQHandler /* TMR8 Overflow */ - .word TMR8_TRG_HALL_IRQHandler /* TMR8 Trigger and hall */ - .word TMR8_CH_IRQHandler /* TMR8 Channel */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word SDIO1_IRQHandler /* SDIO1 */ - .word TMR5_GLOBAL_IRQHandler /* TMR5 */ - .word 0 /* Reserved */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */ - .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */ - .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */ - .word DMA2_Channel4_5_IRQHandler /* DMA2 Channel4 & Channel5 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SE_IRQHandler /* CAN2 SE */ - .word ACC_IRQHandler /* ACC */ - .word USBFS_MAPH_IRQHandler /* USB Map HP */ - .word USBFS_MAPL_IRQHandler /* USB Map LP */ - .word DMA2_Channel6_7_IRQHandler /* DMA2 Channel6 & Channel7 */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDT_IRQHandler - .thumb_set WWDT_IRQHandler,Default_Handler - - .weak PVM_IRQHandler - .thumb_set PVM_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak CRM_IRQHandler - .thumb_set CRM_IRQHandler,Default_Handler - - .weak EXINT0_IRQHandler - .thumb_set EXINT0_IRQHandler,Default_Handler - - .weak EXINT1_IRQHandler - .thumb_set EXINT1_IRQHandler,Default_Handler - - .weak EXINT2_IRQHandler - .thumb_set EXINT2_IRQHandler,Default_Handler - - .weak EXINT3_IRQHandler - .thumb_set EXINT3_IRQHandler,Default_Handler - - .weak EXINT4_IRQHandler - .thumb_set EXINT4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak USBFS_H_CAN1_TX_IRQHandler - .thumb_set USBFS_H_CAN1_TX_IRQHandler,Default_Handler - - .weak USBFS_L_CAN1_RX0_IRQHandler - .thumb_set USBFS_L_CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SE_IRQHandler - .thumb_set CAN1_SE_IRQHandler,Default_Handler - - .weak EXINT9_5_IRQHandler - .thumb_set EXINT9_5_IRQHandler,Default_Handler - - .weak TMR1_BRK_TMR9_IRQHandler - .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler - - .weak TMR1_OVF_TMR10_IRQHandler - .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler - - .weak TMR1_TRG_HALL_TMR11_IRQHandler - .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler - - .weak TMR1_CH_IRQHandler - .thumb_set TMR1_CH_IRQHandler,Default_Handler - - .weak TMR2_GLOBAL_IRQHandler - .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler - - .weak TMR3_GLOBAL_IRQHandler - .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler - - .weak TMR4_GLOBAL_IRQHandler - .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler - - .weak I2C1_EVT_IRQHandler - .thumb_set I2C1_EVT_IRQHandler,Default_Handler - - .weak I2C1_ERR_IRQHandler - .thumb_set I2C1_ERR_IRQHandler,Default_Handler - - .weak I2C2_EVT_IRQHandler - .thumb_set I2C2_EVT_IRQHandler,Default_Handler - - .weak I2C2_ERR_IRQHandler - .thumb_set I2C2_ERR_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXINT15_10_IRQHandler - .thumb_set EXINT15_10_IRQHandler,Default_Handler - - .weak RTCAlarm_IRQHandler - .thumb_set RTCAlarm_IRQHandler,Default_Handler - - .weak USBFSWakeUp_IRQHandler - .thumb_set USBFSWakeUp_IRQHandler,Default_Handler - - .weak TMR8_BRK_IRQHandler - .thumb_set TMR8_BRK_IRQHandler,Default_Handler - - .weak TMR8_OVF_IRQHandler - .thumb_set TMR8_OVF_IRQHandler,Default_Handler - - .weak TMR8_TRG_HALL_IRQHandler - .thumb_set TMR8_TRG_HALL_IRQHandler,Default_Handler - - .weak TMR8_CH_IRQHandler - .thumb_set TMR8_CH_IRQHandler,Default_Handler - - .weak SDIO1_IRQHandler - .thumb_set SDIO1_IRQHandler,Default_Handler - - .weak TMR5_GLOBAL_IRQHandler - .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_5_IRQHandler - .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler ,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler ,Default_Handler - - .weak CAN2_SE_IRQHandler - .thumb_set CAN2_SE_IRQHandler,Default_Handler - - .weak ACC_IRQHandler - .thumb_set ACC_IRQHandler,Default_Handler - - .weak USBFS_MAPH_IRQHandler - .thumb_set USBFS_MAPH_IRQHandler,Default_Handler - - .weak USBFS_MAPL_IRQHandler - .thumb_set USBFS_MAPL_IRQHandler,Default_Handler - - .weak DMA2_Channel6_7_IRQHandler - .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xC_FLASH.ld b/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xC_FLASH.ld deleted file mode 100644 index 6da817705..000000000 --- a/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xC_FLASH.ld +++ /dev/null @@ -1,154 +0,0 @@ -/* -***************************************************************************** -** -** File : AT32F415xC_FLASH.ld -** -** Abstract : Linker script for AT32F415xC Device with -** 256KByte FLASH, 32KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : Artery Tek AT32 -** -** Environment : Arm gcc toolchain -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20008000; /* end of RAM */ - -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/hw/bsp/at32f415/boards/AT_START_F415/board.cmake b/hw/bsp/at32f415/boards/AT_START_F415/board.cmake new file mode 100644 index 000000000..43fc43a70 --- /dev/null +++ b/hw/bsp/at32f415/boards/AT_START_F415/board.cmake @@ -0,0 +1,11 @@ +set(MCU_VARIANT AT32F415RCT7) +set(MCU_LINKER_NAME AT32F415xC) + +set(JLINK_DEVICE ${MCU_VARIANT}) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + ${MCU_VARIANT} + CFG_EXAMPLE_VIDEO_READONLY + ) +endfunction() diff --git a/hw/bsp/at32f415/boards/AT_START_F415/board.mk b/hw/bsp/at32f415/boards/AT_START_F415/board.mk index 6c877ec71..7ea7dc593 100644 --- a/hw/bsp/at32f415/boards/AT_START_F415/board.mk +++ b/hw/bsp/at32f415/boards/AT_START_F415/board.mk @@ -1,4 +1,8 @@ -LD_FILE = $(BOARD_PATH)/AT32F415xC_FLASH.ld +MCU_VARIANT = AT32F415RCT7 +MCU_LINKER_NAME = AT32F415xC + +JLINK_DEVICE = ${MCU_VARIANT} CFLAGS += \ - -DAT32F415RCT7 + -D${MCU_VARIANT} \ + -DCFG_EXAMPLE_VIDEO_READONLY diff --git a/hw/bsp/at32f415/family.c b/hw/bsp/at32f415/family.c index 516095dfb..b8ccae97d 100644 --- a/hw/bsp/at32f415/family.c +++ b/hw/bsp/at32f415/family.c @@ -25,8 +25,8 @@ */ #include "at32f415_clock.h" -#include "bsp/board_api.h" #include "board.h" +#include "bsp/board_api.h" void uart_print_init(uint32_t baudrate); void usb_clock48m_select(usb_clk48_s clk_s); @@ -35,17 +35,14 @@ void led_and_button_init(void); //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void OTGFS1_IRQHandler(void) -{ +void OTGFS1_IRQHandler(void) { tusb_int_handler(0, true); } -void OTGFS1_WKUP_IRQHandler(void) -{ +void OTGFS1_WKUP_IRQHandler(void) { tusb_int_handler(0, true); } -void board_init(void) -{ +void board_init(void) { /* config nvic priority group */ nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); @@ -64,24 +61,24 @@ void board_init(void) /* configure systick */ systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); SysTick_Config(SystemCoreClock / 1000); - #if CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); - #endif - - /* otgfs use vbus pin */ - #ifndef USB_VBUS_IGNORE - gpio_init_type gpio_init_struct; - crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); - gpio_default_para_init(&gpio_init_struct); - gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; - gpio_init_struct.gpio_mode = GPIO_MODE_MUX; - gpio_init_struct.gpio_pins = OTG_PIN_VBUS; - gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); - gpio_init(OTG_PIN_GPIO, &gpio_init_struct); - #endif +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + +/* otgfs use vbus pin */ +#ifndef USB_VBUS_IGNORE + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); +#endif /* config led and key */ led_and_button_init(); @@ -99,43 +96,40 @@ void board_init(void) * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT * @retval none */ -void usb_clock48m_select(usb_clk48_s clk_s) -{ - (void) clk_s; - switch(system_core_clock) - { - /* 48MHz */ - case 48000000: - crm_usb_clock_div_set(CRM_USB_DIV_1); - break; - - /* 72MHz */ - case 72000000: - crm_usb_clock_div_set(CRM_USB_DIV_1_5); - break; - - /* 96MHz */ - case 96000000: - crm_usb_clock_div_set(CRM_USB_DIV_2); - break; - - /* 120MHz */ - case 120000000: - crm_usb_clock_div_set(CRM_USB_DIV_2_5); - break; - - /* 144MHz */ - case 144000000: - crm_usb_clock_div_set(CRM_USB_DIV_3); - break; - - default: - break; - } +void usb_clock48m_select(usb_clk48_s clk_s) { + (void) clk_s; + switch (system_core_clock) { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_1); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_1_5); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + /* 120MHz */ + case 120000000: + crm_usb_clock_div_set(CRM_USB_DIV_2_5); + break; + + /* 144MHz */ + case 144000000: + crm_usb_clock_div_set(CRM_USB_DIV_3); + break; + + default: + break; + } } -void led_and_button_init(void) -{ +void led_and_button_init(void) { /* LED */ gpio_init_type gpio_led_init_struct; /* enable the led clock */ @@ -144,7 +138,7 @@ void led_and_button_init(void) gpio_default_para_init(&gpio_led_init_struct); /* configure the led gpio */ gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; gpio_led_init_struct.gpio_pins = LED_PIN; gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; @@ -169,8 +163,7 @@ void led_and_button_init(void) * @param baudrate: uart baudrate * @retval none */ -void uart_print_init(uint32_t baudrate) -{ +void uart_print_init(uint32_t baudrate) { gpio_init_type gpio_init_struct; /* enable the uart and gpio clock */ crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); @@ -178,7 +171,7 @@ void uart_print_init(uint32_t baudrate) gpio_default_para_init(&gpio_init_struct); /* configure the uart tx pin */ gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_init_struct.gpio_mode = GPIO_MODE_MUX; gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; gpio_init_struct.gpio_pull = GPIO_PULL_NONE; @@ -190,55 +183,47 @@ void uart_print_init(uint32_t baudrate) } // Get characters from UART. Return number of read bytes -int board_uart_read(uint8_t *buf, int len) -{ +int board_uart_read(uint8_t *buf, int len) { (void) buf; (void) len; return 0; } // Send characters to UART. Return number of sent bytes -int board_uart_write(void const *buf, int len) -{ - #if CFG_TUSB_OS == OPT_OS_NONE - int txsize = len; - u16 timeout = 0xffff; - while (txsize--) - { - while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) - { - timeout--; - if(timeout == 0) - { - return 0; - } +int board_uart_write(void const *buf, int len) { +#if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) { + while (usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) { + timeout--; + if (timeout == 0) { + return 0; } - PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); - buf++; } - return len; - #else - (void) buf; - (void) len; - return 0; - #endif + PRINT_UART->dt = (*((uint8_t const *) buf) & 0x01FF); + buf++; + } + return len; +#else + (void) buf; + (void) len; + return 0; +#endif } -void board_led_write(bool state) -{ +void board_led_write(bool state) { gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); } -uint32_t board_button_read(void) -{ +uint32_t board_button_read(void) { return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); } -size_t board_get_unique_id(uint8_t id[], size_t max_len) -{ +size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; - volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); - uint32_t* id32 = (uint32_t*) (uintptr_t) id; + volatile uint32_t *at32_uuid = ((volatile uint32_t *) 0x1FFFF7E8); + uint32_t *id32 = (uint32_t *) (uintptr_t) id; uint8_t const len = 12; id32[0] = at32_uuid[0]; @@ -251,24 +236,20 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) #if CFG_TUSB_OS == OPT_OS_NONE - volatile uint32_t system_ticks = 0; - void SysTick_Handler(void) - { - system_ticks++; - } +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) { + system_ticks++; +} - uint32_t board_millis(void) - { - return system_ticks; - } +uint32_t board_millis(void) { + return system_ticks; +} - void SVC_Handler(void) - { - } +void SVC_Handler(void) { +} - void PendSV_Handler(void) - { - } +void PendSV_Handler(void) { +} #endif void HardFault_Handler(void) { @@ -280,9 +261,8 @@ void HardFault_Handler(void) { void _init(void) { } -#ifdef USE_FULL_ASSERT -void assert_failed(const char *file, uint32_t line) -{ +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) { /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ diff --git a/hw/bsp/at32f415/family.cmake b/hw/bsp/at32f415/family.cmake new file mode 100644 index 000000000..8ac946265 --- /dev/null +++ b/hw/bsp/at32f415/family.cmake @@ -0,0 +1,108 @@ +include_guard() + +set(AT32_FAMILY at32f415) +set(AT32_SDK_LIB ${TOP}/hw/mcu/artery/${AT32_FAMILY}/libraries) + +string(TOUPPER ${AT32_FAMILY} AT32_FAMILY_UPPER) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_CPU cortex-m4-nofpu CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS ${AT32_FAMILY_UPPER} CACHE INTERNAL "") + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/startup_${AT32_FAMILY}.s) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT32_FAMILY}.s) + + if (NOT DEFINED LD_FILE_GNU) + set(LD_FILE_GNU ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld) + endif () + set(LD_FILE_Clang ${LD_FILE_GNU}) + set(LD_FILE_IAR ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf) + + add_library(${BOARD_TARGET} STATIC + ${AT32_SDK_LIB}/cmsis/cm4/device_support/system_${AT32_FAMILY}.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_gpio.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_misc.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_usart.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_crm.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${AT32_SDK_LIB}/cmsis/cm4/core_support + ${AT32_SDK_LIB}/cmsis/cm4/device_support + ${AT32_SDK_LIB}/drivers/inc + ) + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT32_FAMILY}_clock.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT32_FAMILY}_int.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_${AT32_FAMILY_UPPER}) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c + ) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + + # Flashing + family_add_bin_hex(${TARGET}) + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/at32f415/family.mk b/hw/bsp/at32f415/family.mk index 1edf6be4e..73a89c543 100644 --- a/hw/bsp/at32f415/family.mk +++ b/hw/bsp/at32f415/family.mk @@ -1,12 +1,9 @@ -# Submodules -AT32F415_SDK = hw/mcu/artery/at32f415 - -# AT32 SDK path -AT32F415_SDK_SRC = $(AT32F415_SDK)/libraries +AT32_FAMILY = at32f415 +AT32_SDK_LIB = hw/mcu/artery/${AT32_FAMILY}/libraries include $(TOP)/$(BOARD_PATH)/board.mk -CPU_CORE ?= cortex-m3 +CPU_CORE ?= cortex-m4-nofpu CFLAGS_GCC += \ -flto @@ -21,22 +18,22 @@ SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ src/portable/synopsys/dwc2/hcd_dwc2.c \ src/portable/synopsys/dwc2/dwc2_common.c \ - $(AT32F415_SDK_SRC)/drivers/src/at32f415_gpio.c \ - $(AT32F415_SDK_SRC)/drivers/src/at32f415_misc.c \ - $(AT32F415_SDK_SRC)/drivers/src/at32f415_usart.c \ - $(AT32F415_SDK_SRC)/drivers/src/at32f415_crm.c \ - $(AT32F415_SDK_SRC)/cmsis/cm4/device_support/system_at32f415.c + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_gpio.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_misc.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_usart.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_crm.c \ + $(AT32_SDK_LIB)/cmsis/cm4/device_support/system_${AT32_FAMILY}.c INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(AT32F415_SDK_SRC)/drivers/inc \ - $(TOP)/$(AT32F415_SDK_SRC)/cmsis/cm4/core_support \ - $(TOP)/$(AT32F415_SDK_SRC)/cmsis/cm4/device_support + $(TOP)/$(AT32_SDK_LIB)/drivers/inc \ + $(TOP)/$(AT32_SDK_LIB)/cmsis/cm4/core_support \ + $(TOP)/$(AT32_SDK_LIB)/cmsis/cm4/device_support -SRC_S += \ - $(FAMILY_PATH)/startup_at32f415.s +SRC_S_GCC += ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/startup_${AT32_FAMILY}.s +SRC_S_IAR += ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT32_FAMILY}.s -# For freeRTOS port source -#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4 +LD_FILE_GCC ?= ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld +LD_FILE_IAR ?= ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf flash: flash-atlink diff --git a/hw/bsp/at32f415/startup_at32f415.s b/hw/bsp/at32f415/startup_at32f415.s deleted file mode 100644 index 2c4dbc9ef..000000000 --- a/hw/bsp/at32f415/startup_at32f415.s +++ /dev/null @@ -1,407 +0,0 @@ -/** - ****************************************************************************** - * @file startup_at32f415.s - * @brief at32f415xx devices vector table for gcc toolchain. - * this module performs: - * - set the initial sp - * - set the initial pc == reset_handler, - * - set the vector table entries with the exceptions isr address - * - configure the clock system and the external sram to - * be used as data memory (optional, to be enabled by user) - * - branches to main in the c library (which eventually - * calls main()). - * after reset the cortex-m4 processor is in thread mode, - * priority is privileged, and the stack is set to main. - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system initialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDT_IRQHandler /* Window Watchdog Timer */ - .word PVM_IRQHandler /* PVM through EXINT Line detect */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */ - .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */ - .word FLASH_IRQHandler /* Flash */ - .word CRM_IRQHandler /* CRM */ - .word EXINT0_IRQHandler /* EXINT Line 0 */ - .word EXINT1_IRQHandler /* EXINT Line 1 */ - .word EXINT2_IRQHandler /* EXINT Line 2 */ - .word EXINT3_IRQHandler /* EXINT Line 3 */ - .word EXINT4_IRQHandler /* EXINT Line 4 */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ - .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ - .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ - .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ - .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ - .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ - .word ADC1_IRQHandler /* ADC1 */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SE_IRQHandler /* CAN1 SE */ - .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ - .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ - .word TMR1_OVF_TMR10_IRQHandler /* TMR1 overflow and TMR10 */ - .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ - .word TMR1_CH_IRQHandler /* TMR1 channel */ - .word TMR2_GLOBAL_IRQHandler /* TMR2 */ - .word TMR3_GLOBAL_IRQHandler /* TMR3 */ - .word TMR4_GLOBAL_IRQHandler /* TMR4 */ - .word I2C1_EVT_IRQHandler /* I2C1 Event */ - .word I2C1_ERR_IRQHandler /* I2C1 Error */ - .word I2C2_EVT_IRQHandler /* I2C2 Event */ - .word I2C2_ERR_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ - .word ERTCAlarm_IRQHandler /* ERTC Alarm through EXINT Line */ - .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word SDIO1_IRQHandler /* SDIO1 */ - .word TMR5_GLOBAL_IRQHandler /* TMR5 */ - .word 0 /* Reserved */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */ - .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */ - .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */ - .word DMA2_Channel4_5_IRQHandler /* DMA2 Channel4 & Channel5 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word OTGFS1_IRQHandler /* OTGFS1 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word CMP1_IRQHandler /* CMP1 */ - .word CMP2_IRQHandler /* CMP2 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word DMA2_Channel6_7_IRQHandler /* DMA2 Channel6 & Channel7 */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDT_IRQHandler - .thumb_set WWDT_IRQHandler,Default_Handler - - .weak PVM_IRQHandler - .thumb_set PVM_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak ERTC_WKUP_IRQHandler - .thumb_set ERTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak CRM_IRQHandler - .thumb_set CRM_IRQHandler,Default_Handler - - .weak EXINT0_IRQHandler - .thumb_set EXINT0_IRQHandler,Default_Handler - - .weak EXINT1_IRQHandler - .thumb_set EXINT1_IRQHandler,Default_Handler - - .weak EXINT2_IRQHandler - .thumb_set EXINT2_IRQHandler,Default_Handler - - .weak EXINT3_IRQHandler - .thumb_set EXINT3_IRQHandler,Default_Handler - - .weak EXINT4_IRQHandler - .thumb_set EXINT4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SE_IRQHandler - .thumb_set CAN1_SE_IRQHandler,Default_Handler - - .weak EXINT9_5_IRQHandler - .thumb_set EXINT9_5_IRQHandler,Default_Handler - - .weak TMR1_BRK_TMR9_IRQHandler - .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler - - .weak TMR1_OVF_TMR10_IRQHandler - .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler - - .weak TMR1_TRG_HALL_TMR11_IRQHandler - .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler - - .weak TMR1_CH_IRQHandler - .thumb_set TMR1_CH_IRQHandler,Default_Handler - - .weak TMR2_GLOBAL_IRQHandler - .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler - - .weak TMR3_GLOBAL_IRQHandler - .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler - - .weak TMR4_GLOBAL_IRQHandler - .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler - - .weak I2C1_EVT_IRQHandler - .thumb_set I2C1_EVT_IRQHandler,Default_Handler - - .weak I2C1_ERR_IRQHandler - .thumb_set I2C1_ERR_IRQHandler,Default_Handler - - .weak I2C2_EVT_IRQHandler - .thumb_set I2C2_EVT_IRQHandler,Default_Handler - - .weak I2C2_ERR_IRQHandler - .thumb_set I2C2_ERR_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXINT15_10_IRQHandler - .thumb_set EXINT15_10_IRQHandler,Default_Handler - - .weak ERTCAlarm_IRQHandler - .thumb_set ERTCAlarm_IRQHandler,Default_Handler - - .weak OTGFS1_WKUP_IRQHandler - .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler - - .weak SDIO1_IRQHandler - .thumb_set SDIO1_IRQHandler,Default_Handler - - .weak TMR5_GLOBAL_IRQHandler - .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_5_IRQHandler - .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler - - .weak OTGFS1_IRQHandler - .thumb_set OTGFS1_IRQHandler,Default_Handler - - .weak CMP1_IRQHandler - .thumb_set CMP1_IRQHandler,Default_Handler - - .weak CMP2_IRQHandler - .thumb_set CMP2_IRQHandler,Default_Handler - - .weak DMA2_Channel6_7_IRQHandler - .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xC_FLASH.ld b/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xC_FLASH.ld deleted file mode 100644 index ee08e979a..000000000 --- a/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xC_FLASH.ld +++ /dev/null @@ -1,154 +0,0 @@ -/* -***************************************************************************** -** -** File : AT32F423xC_FLASH.ld -** -** Abstract : Linker script for AT32F423xC Device with -** 256KByte FLASH, 48KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : Artery Tek AT32 -** -** Environment : Arm gcc toolchain -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x2000C000; /* end of RAM */ - -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 48K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/hw/bsp/at32f423/boards/AT_START_F423/board.cmake b/hw/bsp/at32f423/boards/AT_START_F423/board.cmake index 45aa39900..f97a12194 100644 --- a/hw/bsp/at32f423/boards/AT_START_F423/board.cmake +++ b/hw/bsp/at32f423/boards/AT_START_F423/board.cmake @@ -1,4 +1,6 @@ set(MCU_VARIANT AT32F423VCT7) +set(MCU_LINKER_NAME AT32F423xC) + set(JLINK_DEVICE ${MCU_VARIANT}) function(update_board TARGET) diff --git a/hw/bsp/at32f423/boards/AT_START_F423/board.mk b/hw/bsp/at32f423/boards/AT_START_F423/board.mk index 4c19c81bb..f7ef2117d 100644 --- a/hw/bsp/at32f423/boards/AT_START_F423/board.mk +++ b/hw/bsp/at32f423/boards/AT_START_F423/board.mk @@ -1,5 +1,7 @@ -JLINK_DEVICE = AT32F423VCT7 -LD_FILE = $(BOARD_PATH)/AT32F423xC_FLASH.ld +MCU_VARIANT = AT32F423VCT7 +MCU_LINKER_NAME = AT32F423xC + +JLINK_DEVICE = ${MCU_VARIANT} CFLAGS += \ - -DAT32F423VCT7 + -D${MCU_VARIANT} diff --git a/hw/bsp/at32f423/family.cmake b/hw/bsp/at32f423/family.cmake index 3845f13ad..17c3f37a2 100644 --- a/hw/bsp/at32f423/family.cmake +++ b/hw/bsp/at32f423/family.cmake @@ -1,9 +1,9 @@ include_guard() -set(AT_FAMILY at32f423) -set(AT_SDK_LIB ${TOP}/hw/mcu/artery/${AT_FAMILY}/libraries) +set(AT32_FAMILY at32f423) +set(AT32_SDK_LIB ${TOP}/hw/mcu/artery/${AT32_FAMILY}/libraries) -string(TOUPPER ${AT_FAMILY} AT_FAMILY_UPPER) +string(TOUPPER ${AT32_FAMILY} AT32_FAMILY_UPPER) # include board specific include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) @@ -12,15 +12,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) -set(FAMILY_MCUS ${AT_FAMILY_UPPER} CACHE INTERNAL "") - -# extract variant linker name -string(LENGTH ${MCU_VARIANT} MCU_VARIANT_LEN) -math(EXPR MCU_FLASH_CODE_INDEX "${MCU_VARIANT_LEN} - 3") -math(EXPR MCU_VARIANT_PREFIX_LEN "${MCU_FLASH_CODE_INDEX} - 1") -string(SUBSTRING ${MCU_VARIANT} ${MCU_FLASH_CODE_INDEX} 1 MCU_FLASH_CODE) -string(SUBSTRING ${MCU_VARIANT} 0 ${MCU_VARIANT_PREFIX_LEN} MCU_VARIANT_PREFIX) -set(MCU_LINKER_NAME ${MCU_VARIANT_PREFIX}x${MCU_FLASH_CODE}) +set(FAMILY_MCUS ${AT32_FAMILY_UPPER} CACHE INTERNAL "") #------------------------------------ # BOARD_TARGET @@ -32,30 +24,30 @@ function(add_board_target BOARD_TARGET) endif () # Startup & Linker script - set(STARTUP_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/startup_${AT_FAMILY}.s) + set(STARTUP_FILE_GNU ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/startup_${AT32_FAMILY}.s) set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) - set(STARTUP_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT_FAMILY}.s) + set(STARTUP_FILE_IAR ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT32_FAMILY}.s) if (NOT DEFINED LD_FILE_GNU) - set(LD_FILE_GNU ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld) + set(LD_FILE_GNU ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld) endif () set(LD_FILE_Clang ${LD_FILE_GNU}) - set(LD_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf) + set(LD_FILE_IAR ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf) add_library(${BOARD_TARGET} STATIC - ${AT_SDK_LIB}/cmsis/cm4/device_support/system_${AT_FAMILY}.c - ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_gpio.c - ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_misc.c - ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_usart.c - ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_acc.c - ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_crm.c + ${AT32_SDK_LIB}/cmsis/cm4/device_support/system_${AT32_FAMILY}.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_gpio.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_misc.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_usart.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_acc.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_crm.c ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${AT_SDK_LIB}/cmsis/cm4/core_support - ${AT_SDK_LIB}/cmsis/cm4/device_support - ${AT_SDK_LIB}/drivers/inc + ${AT32_SDK_LIB}/cmsis/cm4/core_support + ${AT32_SDK_LIB}/cmsis/cm4/device_support + ${AT32_SDK_LIB}/drivers/inc ) update_board(${BOARD_TARGET}) @@ -93,8 +85,8 @@ function(family_configure_example TARGET RTOS) # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT_FAMILY}_clock.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT_FAMILY}_int.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT32_FAMILY}_clock.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT32_FAMILY}_int.c ) target_include_directories(${TARGET} PUBLIC # family, hw, board @@ -104,7 +96,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_${AT_FAMILY_UPPER}) + family_add_tinyusb(${TARGET} OPT_MCU_${AT32_FAMILY_UPPER}) target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c diff --git a/hw/bsp/at32f423/family.mk b/hw/bsp/at32f423/family.mk index 8ee1072be..960f4a9a1 100644 --- a/hw/bsp/at32f423/family.mk +++ b/hw/bsp/at32f423/family.mk @@ -1,9 +1,5 @@ -JLINK_DEVICE = AT32F423VCT7 - -AT32F423_SDK = hw/mcu/artery/at32f423 - -# AT32 SDK path -AT32F423_SDK_SRC = $(AT32F423_SDK)/libraries +AT32_FAMILY = at32f423 +AT32_SDK_LIB = hw/mcu/artery/${AT32_FAMILY}/libraries include $(TOP)/$(BOARD_PATH)/board.mk @@ -22,23 +18,23 @@ SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ src/portable/synopsys/dwc2/hcd_dwc2.c \ src/portable/synopsys/dwc2/dwc2_common.c \ - $(AT32F423_SDK_SRC)/drivers/src/at32f423_gpio.c \ - $(AT32F423_SDK_SRC)/drivers/src/at32f423_misc.c \ - $(AT32F423_SDK_SRC)/drivers/src/at32f423_usart.c \ - $(AT32F423_SDK_SRC)/drivers/src/at32f423_crm.c \ - $(AT32F423_SDK_SRC)/drivers/src/at32f423_acc.c \ - $(AT32F423_SDK_SRC)/cmsis/cm4/device_support/system_at32f423.c + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_gpio.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_misc.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_usart.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_crm.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_acc.c \ + $(AT32_SDK_LIB)/cmsis/cm4/device_support/system_${AT32_FAMILY}.c INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(AT32F423_SDK_SRC)/drivers/inc \ - $(TOP)/$(AT32F423_SDK_SRC)/cmsis/cm4/core_support \ - $(TOP)/$(AT32F423_SDK_SRC)/cmsis/cm4/device_support + $(TOP)/$(AT32_SDK_LIB)/drivers/inc \ + $(TOP)/$(AT32_SDK_LIB)/cmsis/cm4/core_support \ + $(TOP)/$(AT32_SDK_LIB)/cmsis/cm4/device_support -SRC_S += \ - $(FAMILY_PATH)/startup_at32f423.s +SRC_S_GCC += ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/startup_${AT32_FAMILY}.s +SRC_S_IAR += ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT32_FAMILY}.s -# For freeRTOS port source -#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4 +LD_FILE_GCC ?= ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld +LD_FILE_IAR ?= ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf flash: flash-atlink diff --git a/hw/bsp/at32f423/startup_at32f423.s b/hw/bsp/at32f423/startup_at32f423.s deleted file mode 100644 index 3e5404009..000000000 --- a/hw/bsp/at32f423/startup_at32f423.s +++ /dev/null @@ -1,483 +0,0 @@ -/** - ****************************************************************************** - * @file startup_at32f423.s - * @brief at32f423 devices vector table for gcc toolchain. - * this module performs: - * - set the initial sp - * - set the initial pc == reset_handler, - * - set the vector table entries with the exceptions isr address - * - configure the clock system and the external sram to - * be used as data memory (optional, to be enabled by user) - * - branches to main in the c library (which eventually - * calls main()). - * after reset the cortex-m4 processor is in thread mode, - * priority is privileged, and the stack is set to main. - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system initialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDT_IRQHandler /* Window Watchdog Timer */ - .word PVM_IRQHandler /* PVM through EXINT Line detect */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */ - .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */ - .word FLASH_IRQHandler /* Flash */ - .word CRM_IRQHandler /* CRM */ - .word EXINT0_IRQHandler /* EXINT Line 0 */ - .word EXINT1_IRQHandler /* EXINT Line 1 */ - .word EXINT2_IRQHandler /* EXINT Line 2 */ - .word EXINT3_IRQHandler /* EXINT Line 3 */ - .word EXINT4_IRQHandler /* EXINT Line 4 */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ - .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ - .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ - .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ - .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ - .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ - .word ADC1_IRQHandler /* ADC1 */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SE_IRQHandler /* CAN1 SE */ - .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ - .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ - .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ - .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ - .word TMR1_CH_IRQHandler /* TMR1 Channel */ - .word TMR2_GLOBAL_IRQHandler /* TMR2 */ - .word TMR3_GLOBAL_IRQHandler /* TMR3 */ - .word TMR4_GLOBAL_IRQHandler /* TMR4 */ - .word I2C1_EVT_IRQHandler /* I2C1 Event */ - .word I2C1_ERR_IRQHandler /* I2C1 Error */ - .word I2C2_EVT_IRQHandler /* I2C2 Event */ - .word I2C2_ERR_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ - .word ERTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */ - .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */ - .word TMR12_GLOBAL_IRQHandler /* TMR12 */ - .word TMR13_GLOBAL_IRQHandler /* TMR13 */ - .word TMR14_GLOBAL_IRQHandler /* TMR14 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word SPI3_IRQHandler /* SPI3 */ - .word USART4_IRQHandler /* USART4 */ - .word USART5_IRQHandler /* USART5 */ - .word TMR6_DAC_GLOBAL_IRQHandler /* TMR6 & DAC */ - .word TMR7_GLOBAL_IRQHandler /* TMR7 */ - .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ - .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ - .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ - .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ - .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SE_IRQHandler /* CAN2 SE */ - .word OTGFS1_IRQHandler /* OTGFS1 */ - .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ - .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ - .word 0 /* Reserved */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EVT_IRQHandler /* I2C3 Event */ - .word I2C3_ERR_IRQHandler /* I2C3 Error */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word FPU_IRQHandler /* FPU */ - .word USART7_IRQHandler /* USART7 */ - .word USART8_IRQHandler /* USART8 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word DMAMUX_IRQHandler /* DMAMUX */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word ACC_IRQHandler /* ACC */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDT_IRQHandler - .thumb_set WWDT_IRQHandler,Default_Handler - - .weak PVM_IRQHandler - .thumb_set PVM_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak ERTC_WKUP_IRQHandler - .thumb_set ERTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak CRM_IRQHandler - .thumb_set CRM_IRQHandler,Default_Handler - - .weak EXINT0_IRQHandler - .thumb_set EXINT0_IRQHandler,Default_Handler - - .weak EXINT1_IRQHandler - .thumb_set EXINT1_IRQHandler,Default_Handler - - .weak EXINT2_IRQHandler - .thumb_set EXINT2_IRQHandler,Default_Handler - - .weak EXINT3_IRQHandler - .thumb_set EXINT3_IRQHandler,Default_Handler - - .weak EXINT4_IRQHandler - .thumb_set EXINT4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SE_IRQHandler - .thumb_set CAN1_SE_IRQHandler,Default_Handler - - .weak EXINT9_5_IRQHandler - .thumb_set EXINT9_5_IRQHandler,Default_Handler - - .weak TMR1_BRK_TMR9_IRQHandler - .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler - - .weak TMR1_OVF_TMR10_IRQHandler - .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler - - .weak TMR1_TRG_HALL_TMR11_IRQHandler - .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler - - .weak TMR1_CH_IRQHandler - .thumb_set TMR1_CH_IRQHandler,Default_Handler - - .weak TMR2_GLOBAL_IRQHandler - .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler - - .weak TMR3_GLOBAL_IRQHandler - .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler - - .weak TMR4_GLOBAL_IRQHandler - .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler - - .weak I2C1_EVT_IRQHandler - .thumb_set I2C1_EVT_IRQHandler,Default_Handler - - .weak I2C1_ERR_IRQHandler - .thumb_set I2C1_ERR_IRQHandler,Default_Handler - - .weak I2C2_EVT_IRQHandler - .thumb_set I2C2_EVT_IRQHandler,Default_Handler - - .weak I2C2_ERR_IRQHandler - .thumb_set I2C2_ERR_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXINT15_10_IRQHandler - .thumb_set EXINT15_10_IRQHandler,Default_Handler - - .weak ERTCAlarm_IRQHandler - .thumb_set ERTCAlarm_IRQHandler,Default_Handler - - .weak OTGFS1_WKUP_IRQHandler - .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler - - .weak TMR12_GLOBAL_IRQHandler - .thumb_set TMR12_GLOBAL_IRQHandler,Default_Handler - - .weak TMR13_GLOBAL_IRQHandler - .thumb_set TMR13_GLOBAL_IRQHandler,Default_Handler - - .weak TMR14_GLOBAL_IRQHandler - .thumb_set TMR14_GLOBAL_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak USART4_IRQHandler - .thumb_set USART4_IRQHandler,Default_Handler - - .weak USART5_IRQHandler - .thumb_set USART5_IRQHandler,Default_Handler - - .weak TMR6_DAC_GLOBAL_IRQHandler - .thumb_set TMR6_DAC_GLOBAL_IRQHandler,Default_Handler - - .weak TMR7_GLOBAL_IRQHandler - .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_IRQHandler - .thumb_set DMA2_Channel4_IRQHandler,Default_Handler - - .weak DMA2_Channel5_IRQHandler - .thumb_set DMA2_Channel5_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler ,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler ,Default_Handler - - .weak CAN2_SE_IRQHandler - .thumb_set CAN2_SE_IRQHandler,Default_Handler - - .weak OTGFS1_IRQHandler - .thumb_set OTGFS1_IRQHandler,Default_Handler - - .weak DMA2_Channel6_IRQHandler - .thumb_set DMA2_Channel6_IRQHandler,Default_Handler - - .weak DMA2_Channel7_IRQHandler - .thumb_set DMA2_Channel7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EVT_IRQHandler - .thumb_set I2C3_EVT_IRQHandler,Default_Handler - - .weak I2C3_ERR_IRQHandler - .thumb_set I2C3_ERR_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak USART7_IRQHandler - .thumb_set USART7_IRQHandler,Default_Handler - - .weak USART8_IRQHandler - .thumb_set USART8_IRQHandler,Default_Handler - - .weak DMAMUX_IRQHandler - .thumb_set DMAMUX_IRQHandler ,Default_Handler - - .weak ACC_IRQHandler - .thumb_set ACC_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f425/boards/AT_START_F425/AT32F425x8_FLASH.ld b/hw/bsp/at32f425/boards/AT_START_F425/AT32F425x8_FLASH.ld deleted file mode 100644 index b1d767b51..000000000 --- a/hw/bsp/at32f425/boards/AT_START_F425/AT32F425x8_FLASH.ld +++ /dev/null @@ -1,153 +0,0 @@ -/* -***************************************************************************** -** -** File : AT32F425x8_FLASH.ld -** -** Abstract : Linker script for AT32F425x8 Device with -** 64KByte FLASH, 16KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** -** Environment : Arm gcc toolchain -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20005000; /* end of RAM */ - -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64K -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/hw/bsp/at32f425/boards/AT_START_F425/board.cmake b/hw/bsp/at32f425/boards/AT_START_F425/board.cmake new file mode 100644 index 000000000..535bb3cb4 --- /dev/null +++ b/hw/bsp/at32f425/boards/AT_START_F425/board.cmake @@ -0,0 +1,12 @@ +set(MCU_VARIANT AT32F425R8T7) +set(MCU_LINKER_NAME AT32F425x8) + +set(JLINK_DEVICE ${MCU_VARIANT}) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + ${MCU_VARIANT} + CFG_EXAMPLE_VIDEO_READONLY + CFG_EXAMPLE_MSC_READONLY + ) +endfunction() diff --git a/hw/bsp/at32f425/boards/AT_START_F425/board.mk b/hw/bsp/at32f425/boards/AT_START_F425/board.mk index 3fa74d95a..f7aeba1db 100644 --- a/hw/bsp/at32f425/boards/AT_START_F425/board.mk +++ b/hw/bsp/at32f425/boards/AT_START_F425/board.mk @@ -1,4 +1,9 @@ -LD_FILE = $(BOARD_PATH)/AT32F425x8_FLASH.ld +MCU_VARIANT = AT32F425R8T7 +MCU_LINKER_NAME = AT32F425x8 + +JLINK_DEVICE = ${MCU_VARIANT} CFLAGS += \ - -DAT32F425R8T7 + -D${MCU_VARIANT} \ + -DCFG_EXAMPLE_VIDEO_READONLY \ + -DCFG_EXAMPLE_MSC_READONLY diff --git a/hw/bsp/at32f425/family.c b/hw/bsp/at32f425/family.c index 59a485210..26e69bf31 100644 --- a/hw/bsp/at32f425/family.c +++ b/hw/bsp/at32f425/family.c @@ -25,8 +25,8 @@ */ #include "at32f425_clock.h" -#include "bsp/board_api.h" #include "board.h" +#include "bsp/board_api.h" void uart_print_init(uint32_t baudrate); void usb_clock48m_select(usb_clk48_s clk_s); @@ -35,17 +35,14 @@ void led_and_button_init(void); //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void OTGFS1_IRQHandler(void) -{ +void OTGFS1_IRQHandler(void) { tusb_int_handler(0, true); } -void OTGFS1_WKUP_IRQHandler(void) -{ +void OTGFS1_WKUP_IRQHandler(void) { tusb_int_handler(0, true); } -void board_init(void) -{ +void board_init(void) { /* config nvic priority group */ nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); @@ -64,24 +61,24 @@ void board_init(void) /* configure systick */ systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); SysTick_Config(SystemCoreClock / 1000); - #if CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); - #endif - - /* otgfs use vbus pin */ - #ifndef USB_VBUS_IGNORE - gpio_init_type gpio_init_struct; - crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); - gpio_default_para_init(&gpio_init_struct); - gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; - gpio_init_struct.gpio_mode = GPIO_MODE_MUX; - gpio_init_struct.gpio_pins = OTG_PIN_VBUS; - gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); - gpio_init(OTG_PIN_GPIO, &gpio_init_struct); - #endif +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + +/* otgfs use vbus pin */ +#ifndef USB_VBUS_IGNORE + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); +#endif /* config led and key */ led_and_button_init(); @@ -99,10 +96,8 @@ void board_init(void) * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT * @retval none */ -void usb_clock48m_select(usb_clk48_s clk_s) -{ - if(clk_s == USB_CLK_HICK) - { +void usb_clock48m_select(usb_clk48_s clk_s) { + if (clk_s == USB_CLK_HICK) { crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); /* enable the acc calibration ready interrupt */ @@ -115,14 +110,11 @@ void usb_clock48m_select(usb_clk48_s clk_s) /* open acc calibration */ acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); - } - else - { - /* usb divider reset */ + } else { + /* usb divider reset */ crm_usb_div_reset(); - switch(system_core_clock) - { + switch (system_core_clock) { /* 48MHz */ case 48000000: crm_usb_clock_div_set(CRM_USB_DIV_1); @@ -144,8 +136,7 @@ void usb_clock48m_select(usb_clk48_s clk_s) } } -void led_and_button_init(void) -{ +void led_and_button_init(void) { /* LED */ gpio_init_type gpio_led_init_struct; /* enable the led clock */ @@ -154,7 +145,7 @@ void led_and_button_init(void) gpio_default_para_init(&gpio_led_init_struct); /* configure the led gpio */ gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; gpio_led_init_struct.gpio_pins = LED_PIN; gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; @@ -179,8 +170,7 @@ void led_and_button_init(void) * @param baudrate: uart baudrate * @retval none */ -void uart_print_init(uint32_t baudrate) -{ +void uart_print_init(uint32_t baudrate) { gpio_init_type gpio_init_struct; /* enable the uart and gpio clock */ crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); @@ -188,7 +178,7 @@ void uart_print_init(uint32_t baudrate) gpio_default_para_init(&gpio_init_struct); /* configure the uart tx pin */ gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_init_struct.gpio_mode = GPIO_MODE_MUX; gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; gpio_init_struct.gpio_pull = GPIO_PULL_NONE; @@ -201,55 +191,47 @@ void uart_print_init(uint32_t baudrate) } // Get characters from UART. Return number of read bytes -int board_uart_read(uint8_t *buf, int len) -{ +int board_uart_read(uint8_t *buf, int len) { (void) buf; (void) len; return 0; } // Send characters to UART. Return number of sent bytes -int board_uart_write(void const *buf, int len) -{ - #if CFG_TUSB_OS == OPT_OS_NONE - int txsize = len; - u16 timeout = 0xffff; - while (txsize--) - { - while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) - { - timeout--; - if(timeout == 0) - { - return 0; - } +int board_uart_write(void const *buf, int len) { +#if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) { + while (usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) { + timeout--; + if (timeout == 0) { + return 0; } - PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); - buf++; } - return len; - #else - (void) buf; - (void) len; - return 0; - #endif + PRINT_UART->dt = (*((uint8_t const *) buf) & 0x01FF); + buf++; + } + return len; +#else + (void) buf; + (void) len; + return 0; +#endif } -void board_led_write(bool state) -{ +void board_led_write(bool state) { gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); } -uint32_t board_button_read(void) -{ +uint32_t board_button_read(void) { return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); } -size_t board_get_unique_id(uint8_t id[], size_t max_len) -{ +size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; - volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); - uint32_t* id32 = (uint32_t*) (uintptr_t) id; + volatile uint32_t *at32_uuid = ((volatile uint32_t *) 0x1FFFF7E8); + uint32_t *id32 = (uint32_t *) (uintptr_t) id; uint8_t const len = 12; id32[0] = at32_uuid[0]; @@ -262,24 +244,20 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) #if CFG_TUSB_OS == OPT_OS_NONE - volatile uint32_t system_ticks = 0; - void SysTick_Handler(void) - { - system_ticks++; - } +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) { + system_ticks++; +} - uint32_t board_millis(void) - { - return system_ticks; - } +uint32_t board_millis(void) { + return system_ticks; +} - void SVC_Handler(void) - { - } +void SVC_Handler(void) { +} - void PendSV_Handler(void) - { - } +void PendSV_Handler(void) { +} #endif void HardFault_Handler(void) { @@ -291,9 +269,8 @@ void HardFault_Handler(void) { void _init(void) { } -#ifdef USE_FULL_ASSERT -void assert_failed(const char *file, uint32_t line) -{ +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) { /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ diff --git a/hw/bsp/at32f425/family.cmake b/hw/bsp/at32f425/family.cmake new file mode 100644 index 000000000..3f6b36a6b --- /dev/null +++ b/hw/bsp/at32f425/family.cmake @@ -0,0 +1,108 @@ +include_guard() + +set(AT32_FAMILY at32f425) +set(AT32_SDK_LIB ${TOP}/hw/mcu/artery/${AT32_FAMILY}/libraries) + +string(TOUPPER ${AT32_FAMILY} AT32_FAMILY_UPPER) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_CPU cortex-m4-nofpu CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS ${AT32_FAMILY_UPPER} CACHE INTERNAL "") + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/startup_${AT32_FAMILY}.s) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT32_FAMILY}.s) + + if (NOT DEFINED LD_FILE_GNU) + set(LD_FILE_GNU ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld) + endif () + set(LD_FILE_Clang ${LD_FILE_GNU}) + set(LD_FILE_IAR ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf) + + add_library(${BOARD_TARGET} STATIC + ${AT32_SDK_LIB}/cmsis/cm4/device_support/system_${AT32_FAMILY}.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_gpio.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_misc.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_usart.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_crm.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${AT32_SDK_LIB}/cmsis/cm4/core_support + ${AT32_SDK_LIB}/cmsis/cm4/device_support + ${AT32_SDK_LIB}/drivers/inc + ) + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT32_FAMILY}_clock.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT32_FAMILY}_int.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_${AT32_FAMILY_UPPER}) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c + ) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + + # Flashing + family_add_bin_hex(${TARGET}) + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/at32f425/family.mk b/hw/bsp/at32f425/family.mk index 81d5ffc97..0a0a74414 100644 --- a/hw/bsp/at32f425/family.mk +++ b/hw/bsp/at32f425/family.mk @@ -1,12 +1,9 @@ -# Submodules -AT32F425_SDK = hw/mcu/artery/at32f425 - -# AT32 SDK path -AT32F425_SDK_SRC = $(AT32F425_SDK)/libraries +AT32_FAMILY = at32f425 +AT32_SDK_LIB = hw/mcu/artery/${AT32_FAMILY}/libraries include $(TOP)/$(BOARD_PATH)/board.mk -CPU_CORE ?= cortex-m3 +CPU_CORE ?= cortex-m4-nofpu CFLAGS_GCC += \ -flto @@ -21,22 +18,22 @@ SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ src/portable/synopsys/dwc2/hcd_dwc2.c \ src/portable/synopsys/dwc2/dwc2_common.c \ - $(AT32F425_SDK_SRC)/drivers/src/at32f425_gpio.c \ - $(AT32F425_SDK_SRC)/drivers/src/at32f425_misc.c \ - $(AT32F425_SDK_SRC)/drivers/src/at32f425_usart.c \ - $(AT32F425_SDK_SRC)/drivers/src/at32f425_crm.c \ - $(AT32F425_SDK_SRC)/cmsis/cm4/device_support/system_at32f425.c + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_gpio.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_misc.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_usart.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_crm.c \ + $(AT32_SDK_LIB)/cmsis/cm4/device_support/system_${AT32_FAMILY}.c INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(AT32F425_SDK_SRC)/drivers/inc \ - $(TOP)/$(AT32F425_SDK_SRC)/cmsis/cm4/core_support \ - $(TOP)/$(AT32F425_SDK_SRC)/cmsis/cm4/device_support + $(TOP)/$(AT32_SDK_LIB)/drivers/inc \ + $(TOP)/$(AT32_SDK_LIB)/cmsis/cm4/core_support \ + $(TOP)/$(AT32_SDK_LIB)/cmsis/cm4/device_support -SRC_S += \ - $(FAMILY_PATH)/startup_at32f425.s +SRC_S_GCC += ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/startup_${AT32_FAMILY}.s +SRC_S_IAR += ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT32_FAMILY}.s -# For freeRTOS port source -#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4 +LD_FILE_GCC ?= ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld +LD_FILE_IAR ?= ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf flash: flash-atlink diff --git a/hw/bsp/at32f425/startup_at32f425.s b/hw/bsp/at32f425/startup_at32f425.s deleted file mode 100644 index d41fd3f42..000000000 --- a/hw/bsp/at32f425/startup_at32f425.s +++ /dev/null @@ -1,309 +0,0 @@ -/** - ****************************************************************************** - * @file startup_at32f425.s - * @brief at32f425xx devices vector table for gcc toolchain. - * this module performs: - * - set the initial sp - * - set the initial pc == reset_handler, - * - set the vector table entries with the exceptions isr address - * - configure the clock system and the external sram to - * be used as data memory (optional, to be enabled by user) - * - branches to main in the c library (which eventually - * calls main()). - * after reset the cortex-m4 processor is in thread mode, - * priority is privileged, and the stack is set to main. - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system initialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDT_IRQHandler /* Window Watchdog Timer */ - .word PVM_IRQHandler /* PVM through EXINT Line detect */ - .word ERTC_IRQHandler /* ERTC */ - .word FLASH_IRQHandler /* Flash */ - .word CRM_IRQHandler /* CRM */ - .word EXINT1_0_IRQHandler /* EXINT Line 1 & 0 */ - .word EXINT3_2_IRQHandler /* EXINT Line 3 & 2 */ - .word EXINT15_4_IRQHandler /* EXINT Line 15 ~ 4 */ - .word ACC_IRQHandler /* ACC */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel3_2_IRQHandler /* DMA1 Channel 3 & 2 */ - .word DMA1_Channel7_4_IRQHandler /* DMA1 Channel 7 & 4 */ - .word ADC1_IRQHandler /* ADC1 */ - .word TMR1_BRK_OVF_TRG_HALL_IRQHandler /* TMR1 brake overflow trigger and hall */ - .word TMR1_CH_IRQHandler /* TMR1 channel */ - .word TMR2_GLOBAL_IRQHandler /* TMR2 */ - .word TMR3_GLOBAL_IRQHandler /* TMR3 */ - .word TMR6_GLOBAL_IRQHandler /* TMR6 */ - .word TMR7_GLOBAL_IRQHandler /* TMR7 */ - .word TMR14_GLOBAL_IRQHandler /* TMR14 */ - .word TMR15_GLOBAL_IRQHandler /* TMR15 */ - .word TMR16_GLOBAL_IRQHandler /* TMR16 */ - .word TMR17_GLOBAL_IRQHandler /* TMR17 */ - .word I2C1_EVT_IRQHandler /* I2C1 Event */ - .word I2C2_EVT_IRQHandler /* I2C2 Event */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART4_3_IRQHandler /* USART3 & USART4 */ - .word CAN1_IRQHandler /* CAN1 */ - .word OTGFS1_IRQHandler /* OTGFS1 */ - .word I2C1_ERR_IRQHandler /* I2C1 Error */ - .word SPI3_IRQHandler /* SPI3 */ - .word I2C2_ERR_IRQHandler /* I2C2 Error */ - .word TMR13_GLOBAL_IRQHandler /* TMR13 */ -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDT_IRQHandler - .thumb_set WWDT_IRQHandler,Default_Handler - - .weak PVM_IRQHandler - .thumb_set PVM_IRQHandler,Default_Handler - - .weak ERTC_IRQHandler - .thumb_set ERTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak CRM_IRQHandler - .thumb_set CRM_IRQHandler,Default_Handler - - .weak EXINT1_0_IRQHandler - .thumb_set EXINT1_0_IRQHandler,Default_Handler - - .weak EXINT3_2_IRQHandler - .thumb_set EXINT3_2_IRQHandler,Default_Handler - - .weak EXINT15_4_IRQHandler - .thumb_set EXINT15_4_IRQHandler,Default_Handler - - .weak ACC_IRQHandler - .thumb_set ACC_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel3_2_IRQHandler - .thumb_set DMA1_Channel3_2_IRQHandler,Default_Handler - - .weak DMA1_Channel7_4_IRQHandler - .thumb_set DMA1_Channel7_4_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak TMR1_BRK_OVF_TRG_HALL_IRQHandler - .thumb_set TMR1_BRK_OVF_TRG_HALL_IRQHandler,Default_Handler - - .weak TMR1_CH_IRQHandler - .thumb_set TMR1_CH_IRQHandler,Default_Handler - - .weak TMR2_GLOBAL_IRQHandler - .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler - - .weak TMR3_GLOBAL_IRQHandler - .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler - - .weak TMR6_GLOBAL_IRQHandler - .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler - - .weak TMR7_GLOBAL_IRQHandler - .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler - - .weak TMR14_GLOBAL_IRQHandler - .thumb_set TMR14_GLOBAL_IRQHandler,Default_Handler - - .weak TMR15_GLOBAL_IRQHandler - .thumb_set TMR15_GLOBAL_IRQHandler,Default_Handler - - .weak TMR16_GLOBAL_IRQHandler - .thumb_set TMR16_GLOBAL_IRQHandler,Default_Handler - - .weak TMR17_GLOBAL_IRQHandler - .thumb_set TMR17_GLOBAL_IRQHandler,Default_Handler - - .weak I2C1_EVT_IRQHandler - .thumb_set I2C1_EVT_IRQHandler,Default_Handler - - .weak I2C2_EVT_IRQHandler - .thumb_set I2C2_EVT_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART4_3_IRQHandler - .thumb_set USART4_3_IRQHandler,Default_Handler - - .weak CAN1_IRQHandler - .thumb_set CAN1_IRQHandler,Default_Handler - - .weak OTGFS1_IRQHandler - .thumb_set OTGFS1_IRQHandler,Default_Handler - - .weak I2C1_ERR_IRQHandler - .thumb_set I2C1_ERR_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak I2C2_ERR_IRQHandler - .thumb_set I2C2_ERR_IRQHandler,Default_Handler - - .weak TMR13_GLOBAL_IRQHandler - .thumb_set TMR13_GLOBAL_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xM_FLASH.ld b/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xM_FLASH.ld deleted file mode 100644 index b9d5ba223..000000000 --- a/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xM_FLASH.ld +++ /dev/null @@ -1,154 +0,0 @@ -/* -***************************************************************************** -** -** File : AT32F437xM_FLASH.ld -** -** Abstract : Linker script for AT32F437xM Device with -** 4096KByte FLASH, 384KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : Artery Tek AT32 -** -** Environment : Arm gcc toolchain -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20060000; /* end of RAM */ - -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ -FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 4032K -RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 384K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.cmake b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.cmake new file mode 100644 index 000000000..fc54dbcab --- /dev/null +++ b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.cmake @@ -0,0 +1,8 @@ +set(MCU_VARIANT AT32F437ZMT7) +set(MCU_LINKER_NAME AT32F437xM) + +set(JLINK_DEVICE ${MCU_VARIANT}) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT}) +endfunction() diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk index 823ae677d..e663d59f0 100644 --- a/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk +++ b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk @@ -1,4 +1,7 @@ -LD_FILE = $(BOARD_PATH)/AT32F437xM_FLASH.ld +MCU_VARIANT = AT32F437ZMT7 +MCU_LINKER_NAME = AT32F437xM + +JLINK_DEVICE = ${MCU_VARIANT} CFLAGS += \ - -DAT32F437ZMT7 + -D${MCU_VARIANT} diff --git a/hw/bsp/at32f435_437/family.c b/hw/bsp/at32f435_437/family.c index af1fb30e0..c93beeb5a 100644 --- a/hw/bsp/at32f435_437/family.c +++ b/hw/bsp/at32f435_437/family.c @@ -25,8 +25,8 @@ */ #include "at32f435_437_clock.h" -#include "bsp/board_api.h" #include "board.h" +#include "bsp/board_api.h" void usb_gpio_config(void); void uart_print_init(uint32_t baudrate); @@ -36,25 +36,20 @@ int inHandlerMode(void); //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void OTGFS1_IRQHandler(void) -{ +void OTGFS1_IRQHandler(void) { tusb_int_handler(0, true); } -void OTGFS2_IRQHandler(void) -{ +void OTGFS2_IRQHandler(void) { tusb_int_handler(1, true); } -void OTGFS1_WKUP_IRQHandler(void) -{ +void OTGFS1_WKUP_IRQHandler(void) { tusb_int_handler(0, true); } -void OTGFS2_WKUP_IRQHandler(void) -{ +void OTGFS2_WKUP_IRQHandler(void) { tusb_int_handler(1, true); } -void board_init(void) -{ +void board_init(void) { /* config nvic priority group */ nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); @@ -97,10 +92,8 @@ void board_init(void) * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT * @retval none */ -void usb_clock48m_select(usb_clk48_s clk_s) -{ - if(clk_s == USB_CLK_HICK) - { +void usb_clock48m_select(usb_clk48_s clk_s) { + if (clk_s == USB_CLK_HICK) { crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); /* enable the acc calibration ready interrupt */ @@ -110,20 +103,17 @@ void usb_clock48m_select(usb_clk48_s clk_s) acc_write_c1(7980); acc_write_c2(8000); acc_write_c3(8020); - #ifdef BOARD_TUD_RHPORT - #if BOARD_TUD_RHPORT == 0 - acc_sof_select(ACC_SOF_OTG1); - #else - acc_sof_select(ACC_SOF_OTG2); - #endif - #endif +#ifdef BOARD_TUD_RHPORT + #if BOARD_TUD_RHPORT == 0 + acc_sof_select(ACC_SOF_OTG1); + #else + acc_sof_select(ACC_SOF_OTG2); + #endif +#endif /* open acc calibration */ acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); - } - else - { - switch(system_core_clock) - { + } else { + switch (system_core_clock) { /* 48MHz */ case 48000000: crm_usb_clock_div_set(CRM_USB_DIV_1); @@ -185,8 +175,7 @@ void usb_clock48m_select(usb_clk48_s clk_s) } } -void led_and_botton_init(void) -{ +void led_and_botton_init(void) { /* LED */ gpio_init_type gpio_led_init_struct; /* enable the led clock */ @@ -195,7 +184,7 @@ void led_and_botton_init(void) gpio_default_para_init(&gpio_led_init_struct); /* configure the led gpio */ gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; gpio_led_init_struct.gpio_pins = LED_PIN; gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; @@ -223,8 +212,7 @@ void led_and_botton_init(void) * @param baudrate: uart baudrate * @retval none */ -void uart_print_init(uint32_t baudrate) -{ +void uart_print_init(uint32_t baudrate) { gpio_init_type gpio_init_struct; /* enable the uart and gpio clock */ crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); @@ -232,7 +220,7 @@ void uart_print_init(uint32_t baudrate) gpio_default_para_init(&gpio_init_struct); /* configure the uart tx pin */ gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_init_struct.gpio_mode = GPIO_MODE_MUX; gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; gpio_init_struct.gpio_pull = GPIO_PULL_NONE; @@ -245,51 +233,44 @@ void uart_print_init(uint32_t baudrate) } // Get characters from UART. Return number of read bytes -int board_uart_read(uint8_t *buf, int len) -{ +int board_uart_read(uint8_t *buf, int len) { (void) buf; (void) len; return 0; } // Send characters to UART. Return number of sent bytes -int board_uart_write(void const *buf, int len) -{ - #if CFG_TUSB_OS == OPT_OS_NONE - int txsize = len; - u16 timeout = 0xffff; - while (txsize--) - { - while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) - { - timeout--; - if(timeout == 0) - { - return 0; - } +int board_uart_write(void const *buf, int len) { +#if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) { + while (usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) { + timeout--; + if (timeout == 0) { + return 0; } - PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); - buf++; } - return len; - #else - (void) buf; - (void) len; - return 0; - #endif + PRINT_UART->dt = (*((uint8_t const *) buf) & 0x01FF); + buf++; + } + return len; +#else + (void) buf; + (void) len; + return 0; +#endif } -int inHandlerMode(void) -{ - return __get_IPSR(); +int inHandlerMode(void) { + return __get_IPSR(); } -void usb_gpio_config(void) -{ +void usb_gpio_config(void) { gpio_init_type gpio_init_struct; crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); gpio_default_para_init(&gpio_init_struct); gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_init_struct.gpio_mode = GPIO_MODE_MUX; gpio_init_struct.gpio_pull = GPIO_PULL_NONE; /* dp and dm */ @@ -297,36 +278,33 @@ void usb_gpio_config(void) gpio_init(OTG_PIN_GPIO, &gpio_init_struct); gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_DP_SOURCE, OTG_PIN_MUX); gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_DM_SOURCE, OTG_PIN_MUX); - #ifdef USB_SOF_OUTPUT_ENABLE - crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); - gpio_init_struct.gpio_pins = OTG_PIN_SOF; - gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); - gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); - #endif - /* otgfs use vbus pin */ - #ifndef USB_VBUS_IGNORE - gpio_init_struct.gpio_pins = OTG_PIN_VBUS; - gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); - gpio_init(OTG_PIN_GPIO, &gpio_init_struct); - #endif +#ifdef USB_SOF_OUTPUT_ENABLE + crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); + gpio_init_struct.gpio_pins = OTG_PIN_SOF; + gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); +#endif + /* otgfs use vbus pin */ +#ifndef USB_VBUS_IGNORE + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); +#endif } -void board_led_write(bool state) -{ +void board_led_write(bool state) { gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); } -uint32_t board_button_read(void) -{ +uint32_t board_button_read(void) { return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); } -size_t board_get_unique_id(uint8_t id[], size_t max_len) -{ +size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; - volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); - uint32_t* id32 = (uint32_t*) (uintptr_t) id; + volatile uint32_t *at32_uuid = ((volatile uint32_t *) 0x1FFFF7E8); + uint32_t *id32 = (uint32_t *) (uintptr_t) id; uint8_t const len = 12; id32[0] = at32_uuid[0]; @@ -337,21 +315,17 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) } #if CFG_TUSB_OS == OPT_OS_NONE - volatile uint32_t system_ticks = 0; - void SysTick_Handler(void) - { - system_ticks++; - } - uint32_t board_millis(void) - { - return system_ticks; - } - void SVC_Handler(void) - { - } - void PendSV_Handler(void) - { - } +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) { + system_ticks++; +} +uint32_t board_millis(void) { + return system_ticks; +} +void SVC_Handler(void) { +} +void PendSV_Handler(void) { +} #endif void HardFault_Handler(void) { @@ -363,9 +337,8 @@ void HardFault_Handler(void) { void _init(void) { } -#ifdef USE_FULL_ASSERT -void assert_failed(const char *file, uint32_t line) -{ +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) { /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ diff --git a/hw/bsp/at32f435_437/family.cmake b/hw/bsp/at32f435_437/family.cmake new file mode 100644 index 000000000..c85b58ae4 --- /dev/null +++ b/hw/bsp/at32f435_437/family.cmake @@ -0,0 +1,114 @@ +include_guard() + +set(AT32_FAMILY at32f435_437) +set(AT32_SDK_LIB ${TOP}/hw/mcu/artery/${AT32_FAMILY}/libraries) + +string(TOUPPER ${AT32_FAMILY} AT32_FAMILY_UPPER) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS ${AT32_FAMILY_UPPER} CACHE INTERNAL "") + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/startup_${AT32_FAMILY}.s) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT32_FAMILY}.s) + + if (NOT DEFINED LD_FILE_GNU) + set(LD_FILE_GNU ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld) + endif () + set(LD_FILE_Clang ${LD_FILE_GNU}) + set(LD_FILE_IAR ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf) + + add_library(${BOARD_TARGET} STATIC + ${AT32_SDK_LIB}/cmsis/cm4/device_support/system_${AT32_FAMILY}.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_gpio.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_misc.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_usart.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_acc.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_crm.c + ${AT32_SDK_LIB}/drivers/src/${AT32_FAMILY}_exint.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${AT32_SDK_LIB}/cmsis/cm4/core_support + ${AT32_SDK_LIB}/cmsis/cm4/device_support + ${AT32_SDK_LIB}/drivers/inc + ) + target_compile_definitions(${BOARD_TARGET} PUBLIC + BOARD_TUD_RHPORT=0 + ) + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT32_FAMILY}_clock.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT32_FAMILY}_int.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_${AT32_FAMILY_UPPER}) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c + ) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + + # Flashing + family_add_bin_hex(${TARGET}) + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/at32f435_437/family.mk b/hw/bsp/at32f435_437/family.mk index 891c7501c..b33be1180 100644 --- a/hw/bsp/at32f435_437/family.mk +++ b/hw/bsp/at32f435_437/family.mk @@ -1,8 +1,5 @@ -# Submodules -AT32F435_437_SDK = hw/mcu/artery/at32f435_437 - -# AT32 SDK path -AT32F435_437_SDK_SRC = $(AT32F435_437_SDK)/libraries +AT32_FAMILY = at32f435_437 +AT32_SDK_LIB = hw/mcu/artery/${AT32_FAMILY}/libraries include $(TOP)/$(BOARD_PATH)/board.mk @@ -13,6 +10,7 @@ CFLAGS_GCC += \ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_AT32F435_437 \ + -DBOARD_TUD_RHPORT=0 LDFLAGS_GCC += \ -flto --specs=nosys.specs -nostdlib -nostartfiles @@ -21,24 +19,24 @@ SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ src/portable/synopsys/dwc2/hcd_dwc2.c \ src/portable/synopsys/dwc2/dwc2_common.c \ - $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_gpio.c \ - $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_misc.c \ - $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_usart.c \ - $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_crm.c \ - $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_acc.c \ - $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_exint.c \ - $(AT32F435_437_SDK_SRC)/cmsis/cm4/device_support/system_at32f435_437.c + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_gpio.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_misc.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_usart.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_crm.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_acc.c \ + $(AT32_SDK_LIB)/drivers/src/${AT32_FAMILY}_exint.c \ + $(AT32_SDK_LIB)/cmsis/cm4/device_support/system_${AT32_FAMILY}.c INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(AT32F435_437_SDK_SRC)/drivers/inc \ - $(TOP)/$(AT32F435_437_SDK_SRC)/cmsis/cm4/core_support \ - $(TOP)/$(AT32F435_437_SDK_SRC)/cmsis/cm4/device_support \ + $(TOP)/$(AT32_SDK_LIB)/drivers/inc \ + $(TOP)/$(AT32_SDK_LIB)/cmsis/cm4/core_support \ + $(TOP)/$(AT32_SDK_LIB)/cmsis/cm4/device_support -SRC_S += \ - $(FAMILY_PATH)/startup_at32f435_437.s +SRC_S_GCC += ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/startup_${AT32_FAMILY}.s +SRC_S_IAR += ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT32_FAMILY}.s -# For freeRTOS port source -#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F +LD_FILE_GCC ?= ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/gcc/linker/${MCU_LINKER_NAME}_FLASH.ld +LD_FILE_IAR ?= ${AT32_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/${MCU_LINKER_NAME}.icf flash: flash-atlink diff --git a/hw/bsp/at32f435_437/startup_at32f435_437.s b/hw/bsp/at32f435_437/startup_at32f435_437.s deleted file mode 100644 index 70bc4ec89..000000000 --- a/hw/bsp/at32f435_437/startup_at32f435_437.s +++ /dev/null @@ -1,569 +0,0 @@ -/** - ****************************************************************************** - * @file startup_at32f435_437.s - * @brief at32f435_437 devices vector table for gcc toolchain. - * this module performs: - * - set the initial sp - * - set the initial pc == reset_handler, - * - set the vector table entries with the exceptions isr address - * - configure the clock system and the external sram to - * be used as data memory (optional, to be enabled by user) - * - branches to main in the c library (which eventually - * calls main()). - * after reset the cortex-m4 processor is in thread mode, - * priority is privileged, and the stack is set to main. - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system initialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDT_IRQHandler /* Window Watchdog Timer */ - .word PVM_IRQHandler /* PVM through EXINT Line detect */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */ - .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */ - .word FLASH_IRQHandler /* Flash */ - .word CRM_IRQHandler /* CRM */ - .word EXINT0_IRQHandler /* EXINT Line 0 */ - .word EXINT1_IRQHandler /* EXINT Line 1 */ - .word EXINT2_IRQHandler /* EXINT Line 2 */ - .word EXINT3_IRQHandler /* EXINT Line 3 */ - .word EXINT4_IRQHandler /* EXINT Line 4 */ - .word EDMA_Stream1_IRQHandler /* EDMA Stream 1 */ - .word EDMA_Stream2_IRQHandler /* EDMA Stream 2 */ - .word EDMA_Stream3_IRQHandler /* EDMA Stream 3 */ - .word EDMA_Stream4_IRQHandler /* EDMA Stream 4 */ - .word EDMA_Stream5_IRQHandler /* EDMA Stream 5 */ - .word EDMA_Stream6_IRQHandler /* EDMA Stream 6 */ - .word EDMA_Stream7_IRQHandler /* EDMA Stream 7 */ - .word ADC1_2_3_IRQHandler /* ADC1 & ADC2 & ADC3 */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SE_IRQHandler /* CAN1 SE */ - .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ - .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ - .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ - .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ - .word TMR1_CH_IRQHandler /* TMR1 Channel */ - .word TMR2_GLOBAL_IRQHandler /* TMR2 */ - .word TMR3_GLOBAL_IRQHandler /* TMR3 */ - .word TMR4_GLOBAL_IRQHandler /* TMR4 */ - .word I2C1_EVT_IRQHandler /* I2C1 Event */ - .word I2C1_ERR_IRQHandler /* I2C1 Error */ - .word I2C2_EVT_IRQHandler /* I2C2 Event */ - .word I2C2_ERR_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_I2S2EXT_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ - .word ERTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */ - .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */ - .word TMR8_BRK_TMR12_IRQHandler /* TMR8 Brake and TMR12 */ - .word TMR8_OVF_TMR13_IRQHandler /* TMR8 Overflow and TMR13 */ - .word TMR8_TRG_HALL_TMR14_IRQHandler /* TMR8 Trigger and hall and TMR14 */ - .word TMR8_CH_IRQHandler /* TMR8 Channel */ - .word EDMA_Stream8_IRQHandler /* EDMA Stream 8 */ - .word XMC_IRQHandler /* XMC */ - .word SDIO1_IRQHandler /* SDIO1 */ - .word TMR5_GLOBAL_IRQHandler /* TMR5 */ - .word SPI3_I2S3EXT_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TMR6_DAC_GLOBAL_IRQHandler /* TMR6 & DAC */ - .word TMR7_GLOBAL_IRQHandler /* TMR7 */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ - .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ - .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ - .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ - .word EMAC_IRQHandler /* EMAC */ - .word EMAC_WKUP_IRQHandler /* EMAC Wakeup */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SE_IRQHandler /* CAN2 SE */ - .word OTGFS1_IRQHandler /* OTGFS1 */ - .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ - .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ - .word 0 /* Reserved */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EVT_IRQHandler /* I2C3 Event */ - .word I2C3_ERR_IRQHandler /* I2C3 Error */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word OTGFS2_WKUP_IRQHandler /* OTGFS2 Wakeup from suspend */ - .word OTGFS2_IRQHandler /* OTGFS2 */ - .word DVP_IRQHandler /* DVP */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word FPU_IRQHandler /* FPU */ - .word UART7_IRQHandler /* UART7 */ - .word UART8_IRQHandler /* UART8 */ - .word SPI4_IRQHandler /* SPI4 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word QSPI2_IRQHandler /* QSPI2 */ - .word QSPI1_IRQHandler /* QSPI1 */ - .word 0 /* Reserved */ - .word DMAMUX_IRQHandler /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word SDIO2_IRQHandler /* SDIO2 */ - .word ACC_IRQHandler /* ACC */ - .word TMR20_BRK_IRQHandler /* TMR20 Brake */ - .word TMR20_OVF_IRQHandler /* TMR20 Overflow */ - .word TMR20_TRG_HALL_IRQHandler /* TMR20 Trigger and hall */ - .word TMR20_CH_IRQHandler /* TMR20 Channel */ - .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ - .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ - .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ - .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ - .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ - .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ - .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDT_IRQHandler - .thumb_set WWDT_IRQHandler,Default_Handler - - .weak PVM_IRQHandler - .thumb_set PVM_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak ERTC_WKUP_IRQHandler - .thumb_set ERTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak CRM_IRQHandler - .thumb_set CRM_IRQHandler,Default_Handler - - .weak EXINT0_IRQHandler - .thumb_set EXINT0_IRQHandler,Default_Handler - - .weak EXINT1_IRQHandler - .thumb_set EXINT1_IRQHandler,Default_Handler - - .weak EXINT2_IRQHandler - .thumb_set EXINT2_IRQHandler,Default_Handler - - .weak EXINT3_IRQHandler - .thumb_set EXINT3_IRQHandler,Default_Handler - - .weak EXINT4_IRQHandler - .thumb_set EXINT4_IRQHandler,Default_Handler - - .weak EDMA_Stream1_IRQHandler - .thumb_set EDMA_Stream1_IRQHandler,Default_Handler - - .weak EDMA_Stream2_IRQHandler - .thumb_set EDMA_Stream2_IRQHandler,Default_Handler - - .weak EDMA_Stream3_IRQHandler - .thumb_set EDMA_Stream3_IRQHandler,Default_Handler - - .weak EDMA_Stream4_IRQHandler - .thumb_set EDMA_Stream4_IRQHandler,Default_Handler - - .weak EDMA_Stream5_IRQHandler - .thumb_set EDMA_Stream5_IRQHandler,Default_Handler - - .weak EDMA_Stream6_IRQHandler - .thumb_set EDMA_Stream6_IRQHandler,Default_Handler - - .weak EDMA_Stream7_IRQHandler - .thumb_set EDMA_Stream7_IRQHandler,Default_Handler - - .weak ADC1_2_3_IRQHandler - .thumb_set ADC1_2_3_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SE_IRQHandler - .thumb_set CAN1_SE_IRQHandler,Default_Handler - - .weak EXINT9_5_IRQHandler - .thumb_set EXINT9_5_IRQHandler,Default_Handler - - .weak TMR1_BRK_TMR9_IRQHandler - .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler - - .weak TMR1_OVF_TMR10_IRQHandler - .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler - - .weak TMR1_TRG_HALL_TMR11_IRQHandler - .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler - - .weak TMR1_CH_IRQHandler - .thumb_set TMR1_CH_IRQHandler,Default_Handler - - .weak TMR2_GLOBAL_IRQHandler - .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler - - .weak TMR3_GLOBAL_IRQHandler - .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler - - .weak TMR4_GLOBAL_IRQHandler - .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler - - .weak I2C1_EVT_IRQHandler - .thumb_set I2C1_EVT_IRQHandler,Default_Handler - - .weak I2C1_ERR_IRQHandler - .thumb_set I2C1_ERR_IRQHandler,Default_Handler - - .weak I2C2_EVT_IRQHandler - .thumb_set I2C2_EVT_IRQHandler,Default_Handler - - .weak I2C2_ERR_IRQHandler - .thumb_set I2C2_ERR_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_I2S2EXT_IRQHandler - .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXINT15_10_IRQHandler - .thumb_set EXINT15_10_IRQHandler,Default_Handler - - .weak ERTCAlarm_IRQHandler - .thumb_set ERTCAlarm_IRQHandler,Default_Handler - - .weak OTGFS1_WKUP_IRQHandler - .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler - - .weak TMR8_BRK_TMR12_IRQHandler - .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler - - .weak TMR8_OVF_TMR13_IRQHandler - .thumb_set TMR8_OVF_TMR13_IRQHandler,Default_Handler - - .weak TMR8_TRG_HALL_TMR14_IRQHandler - .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler - - .weak TMR8_CH_IRQHandler - .thumb_set TMR8_CH_IRQHandler,Default_Handler - - .weak EDMA_Stream8_IRQHandler - .thumb_set EDMA_Stream8_IRQHandler,Default_Handler - - .weak XMC_IRQHandler - .thumb_set XMC_IRQHandler,Default_Handler - - .weak SDIO1_IRQHandler - .thumb_set SDIO1_IRQHandler,Default_Handler - - .weak TMR5_GLOBAL_IRQHandler - .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler - - .weak SPI3_I2S3EXT_IRQHandler - .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TMR6_DAC_GLOBAL_IRQHandler - .thumb_set TMR6_DAC_GLOBAL_IRQHandler,Default_Handler - - .weak TMR7_GLOBAL_IRQHandler - .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak EMAC_IRQHandler - .thumb_set EMAC_IRQHandler,Default_Handler - - .weak EMAC_WKUP_IRQHandler - .thumb_set EMAC_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler ,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler ,Default_Handler - - .weak CAN2_SE_IRQHandler - .thumb_set CAN2_SE_IRQHandler,Default_Handler - - .weak OTGFS1_IRQHandler - .thumb_set OTGFS1_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EVT_IRQHandler - .thumb_set I2C3_EVT_IRQHandler,Default_Handler - - .weak I2C3_ERR_IRQHandler - .thumb_set I2C3_ERR_IRQHandler,Default_Handler - - .weak OTGFS2_WKUP_IRQHandler - .thumb_set OTGFS2_WKUP_IRQHandler,Default_Handler - - .weak OTGFS2_IRQHandler - .thumb_set OTGFS2_IRQHandler,Default_Handler - - .weak DVP_IRQHandler - .thumb_set DVP_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak UART7_IRQHandler - .thumb_set UART7_IRQHandler,Default_Handler - - .weak UART8_IRQHandler - .thumb_set UART8_IRQHandler,Default_Handler - - .weak SPI4_IRQHandler - .thumb_set SPI4_IRQHandler,Default_Handler - - .weak QSPI2_IRQHandler - .thumb_set QSPI2_IRQHandler,Default_Handler - - .weak QSPI1_IRQHandler - .thumb_set QSPI1_IRQHandler,Default_Handler - - .weak DMAMUX_IRQHandler - .thumb_set DMAMUX_IRQHandler ,Default_Handler - - .weak SDIO2_IRQHandler - .thumb_set SDIO2_IRQHandler ,Default_Handler - - .weak ACC_IRQHandler - .thumb_set ACC_IRQHandler,Default_Handler - - .weak TMR20_BRK_IRQHandler - .thumb_set TMR20_BRK_IRQHandler,Default_Handler - - .weak TMR20_OVF_IRQHandler - .thumb_set TMR20_OVF_IRQHandler,Default_Handler - - .weak TMR20_TRG_HALL_IRQHandler - .thumb_set TMR20_TRG_HALL_IRQHandler,Default_Handler - - .weak TMR20_CH_IRQHandler - .thumb_set TMR20_CH_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_IRQHandler - .thumb_set DMA2_Channel4_IRQHandler,Default_Handler - - .weak DMA2_Channel5_IRQHandler - .thumb_set DMA2_Channel5_IRQHandler,Default_Handler - - .weak DMA2_Channel6_IRQHandler - .thumb_set DMA2_Channel6_IRQHandler,Default_Handler - - .weak DMA2_Channel7_IRQHandler - .thumb_set DMA2_Channel7_IRQHandler,Default_Handler -- cgit v1.3.1 From e0f2343954c71743358f2b2362bef64bbc68e4a3 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 31 Jul 2025 23:26:27 +0700 Subject: clean up --- src/portable/st/stm32_fsdev/fsdev_at32.h | 148 +++++++++++++++---------------- src/portable/synopsys/dwc2/dwc2_at32.h | 106 ++++++++++------------ src/portable/synopsys/dwc2/dwc2_common.c | 16 ++-- 3 files changed, 124 insertions(+), 146 deletions(-) diff --git a/src/portable/st/stm32_fsdev/fsdev_at32.h b/src/portable/st/stm32_fsdev/fsdev_at32.h index 5f2ce4ba2..3a785bbbd 100644 --- a/src/portable/st/stm32_fsdev/fsdev_at32.h +++ b/src/portable/st/stm32_fsdev/fsdev_at32.h @@ -35,82 +35,6 @@ #endif -//#include "fsdev_common.h" - -//--------------------------------------------------------------------+ -// -//--------------------------------------------------------------------+ - -#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) -static const IRQn_Type fsdev_irq[] = { - USBFS_H_CAN1_TX_IRQn, - USBFS_L_CAN1_RX0_IRQn, - USBFSWakeUp_IRQn -}; -enum { FSDEV_IRQ_NUM = TU_ARRAY_SIZE(fsdev_irq) }; - -#else - #error "Unsupported MCU" -#endif - -void dcd_int_enable(uint8_t rhport) { - (void)rhport; - #if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) - // AT32F403A/407 devices allow to remap the USB interrupt vectors from - // shared USB/CAN IRQs to separate CAN and USB IRQs. - // This dynamically checks if this remap is active to enable the right IRQs. - if (CRM->intmap_bit.usbintmap) { - NVIC_DisableIRQ(USBFS_MAPH_IRQn); - NVIC_DisableIRQ(USBFS_MAPL_IRQn); - NVIC_DisableIRQ(USBFSWakeUp_IRQn); - } else - #endif - { - for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) { - NVIC_EnableIRQ(fsdev_irq[i]); - } - } -} - -void dcd_int_disable(uint8_t rhport) { - (void)rhport; - #if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) - // AT32F403A/407 devices allow to remap the USB interrupt vectors from - // shared USB/CAN IRQs to separate CAN and USB IRQs. - // This dynamically checks if this remap is active to enable the right IRQs. - if (CRM->intmap_bit.usbintmap) { - NVIC_DisableIRQ(USBFS_MAPH_IRQn); - NVIC_DisableIRQ(USBFS_MAPL_IRQn); - NVIC_DisableIRQ(USBFSWakeUp_IRQn); - } else - #endif - { - for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) { - NVIC_DisableIRQ(fsdev_irq[i]); - } - } -} - -void dcd_disconnect(uint8_t rhport) { - (void) rhport; - /* disable usb phy */ - //USB->ctrl_bit.disusb = TRUE; - *(int *)(0x40000000+0x5C00+0x40) |= (1<<1); - *(int *)(0x40000000+0x5C00+0x60) |= (1<<1); - /* D+ 1.5k pull-up disable */ - //USB->cfg_bit.puo = TRUE; -} - -void dcd_connect(uint8_t rhport) { - (void) rhport; - /* enable usb phy */ - //USB->ctrl_bit.disusb = 0; - *(int *)(0x40000000+0x5C00+0x40) &= ~(1<<1); - *(int *)(0x40000000+0x5C00+0x60) &= ~(1<<1); - /* Dp 1.5k pull-up enable */ - //USB->cfg_bit.puo = 0; -} - #define FSDEV_PMA_SIZE (512u) #define FSDEV_REG_BASE (APB1PERIPH_BASE + 0x00005C00UL) #define FSDEV_PMA_BASE (APB1PERIPH_BASE + 0x00006000UL) @@ -221,4 +145,76 @@ void dcd_connect(uint8_t rhport) { #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */ #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) +#include "fsdev_type.h" + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) +static const IRQn_Type fsdev_irq[] = { + USBFS_H_CAN1_TX_IRQn, + USBFS_L_CAN1_RX0_IRQn, + USBFSWakeUp_IRQn +}; +enum { FSDEV_IRQ_NUM = TU_ARRAY_SIZE(fsdev_irq) }; + +#else + #error "Unsupported MCU" +#endif + +void dcd_int_enable(uint8_t rhport) { + (void)rhport; + #if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) + // AT32F403A/407 devices allow to remap the USB interrupt vectors from + // shared USB/CAN IRQs to separate CAN and USB IRQs. + // This dynamically checks if this remap is active to enable the right IRQs. + if (CRM->intmap_bit.usbintmap) { + NVIC_DisableIRQ(USBFS_MAPH_IRQn); + NVIC_DisableIRQ(USBFS_MAPL_IRQn); + NVIC_DisableIRQ(USBFSWakeUp_IRQn); + } else + #endif + { + for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) { + NVIC_EnableIRQ(fsdev_irq[i]); + } + } +} + +void dcd_int_disable(uint8_t rhport) { + (void)rhport; + #if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) + // AT32F403A/407 devices allow to remap the USB interrupt vectors from + // shared USB/CAN IRQs to separate CAN and USB IRQs. + // This dynamically checks if this remap is active to enable the right IRQs. + if (CRM->intmap_bit.usbintmap) { + NVIC_DisableIRQ(USBFS_MAPH_IRQn); + NVIC_DisableIRQ(USBFS_MAPL_IRQn); + NVIC_DisableIRQ(USBFSWakeUp_IRQn); + } else + #endif + { + for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) { + NVIC_DisableIRQ(fsdev_irq[i]); + } + } +} + +void dcd_disconnect(uint8_t rhport) { + (void) rhport; + /* disable usb phy */ + FSDEV_REG->CNTR |= USB_CNTR_PDWN; + /* D+ 1.5k pull-up disable, USB->cfg_bit.puo = TRUE; */ + *(uint32_t *)(FSDEV_REG_BASE+0x60) |= (1u<<1); +} + +void dcd_connect(uint8_t rhport) { + (void) rhport; + /* enable usb phy */ + FSDEV_REG->CNTR &= ~USB_CNTR_PDWN; + /* Dp 1.5k pull-up enable, USB->cfg_bit.puo = 0; */ + *(uint32_t *)(FSDEV_REG_BASE+0x60) &= ~(1u<<1); +} + #endif diff --git a/src/portable/synopsys/dwc2/dwc2_at32.h b/src/portable/synopsys/dwc2/dwc2_at32.h index 1150d825b..37b6592c4 100644 --- a/src/portable/synopsys/dwc2/dwc2_at32.h +++ b/src/portable/synopsys/dwc2/dwc2_at32.h @@ -67,66 +67,52 @@ extern "C" { #endif -static const dwc2_controller_t _dwc2_controller[] = -{ - { .reg_base = DWC2_OTG1_REG_BASE, .irqnum = OTG1_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG1_FIFO_SIZE }, - #if defined DWC2_OTG2_REG_BASE - { .reg_base = DWC2_OTG2_REG_BASE, .irqnum = OTG2_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG2_FIFO_SIZE } - #endif -}; - -TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) { - (void) role; - const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum; - if (enabled) { - NVIC_EnableIRQ(irqn); - } else { - NVIC_DisableIRQ(irqn); - } -} - -TU_ATTR_ALWAYS_INLINE -static inline void dwc2_dcd_int_enable(uint8_t rhport) -{ - NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum); -} - -TU_ATTR_ALWAYS_INLINE -static inline void dwc2_dcd_int_disable (uint8_t rhport) -{ - NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum); -} - -static inline void dwc2_remote_wakeup_delay(void) -{ - // try to delay for 1 ms - uint32_t count = system_core_clock / 1000; - while ( count-- ) __asm volatile ("nop"); -} - -// MCU specific PHY init, called BEFORE core reset -static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) -{ - (void) dwc2; - // Enable on-chip HS PHY - if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) - { - - } - else if(hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) - { - - } -} - -// MCU specific PHY update, it is called AFTER init() and core reset -static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) -{ - (void) dwc2; - (void) hs_phy_type; - - dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN; -} + static const dwc2_controller_t _dwc2_controller[] = { +{.reg_base = DWC2_OTG1_REG_BASE, .irqnum = OTG1_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG1_FIFO_SIZE}, +#if defined DWC2_OTG2_REG_BASE + {.reg_base = DWC2_OTG2_REG_BASE, .irqnum = OTG2_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG2_FIFO_SIZE} +#endif + }; + + TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) { + (void) role; + const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum; + if (enabled) { + NVIC_EnableIRQ(irqn); + } else { + NVIC_DisableIRQ(irqn); + } + } + + TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) { NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum); + } + + TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) { + NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum); + } + + TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) { + // try to delay for 1 ms + uint32_t count = system_core_clock / 1000; + while (count--) __asm volatile("nop"); + } + + // MCU specific PHY init, called BEFORE core reset + TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t *dwc2, uint8_t hs_phy_type) { + (void) dwc2; + // Enable on-chip HS PHY + if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) { + } else if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) { + } + } + + // MCU specific PHY update, it is called AFTER init() and core reset + TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t *dwc2, uint8_t hs_phy_type) { + (void) dwc2; + (void) hs_phy_type; + + dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN; + } #ifdef __cplusplus } diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index 56326d5a7..b001f343d 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -120,13 +120,9 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // Set 16-bit interface if supported if (ghwcfg4.phy_data_width) { + #if CFG_TUSB_MCU != OPT_MCU_AT32F402_405 // at32f402_405 does not actually support 16-bit gusbcfg |= GUSBCFG_PHYIF16; // 16 bit - - /* at32f402_405 does not actually support 16-bit */ - #if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 - gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit #endif - } else { gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit } @@ -145,12 +141,12 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // - 9 if using 8-bit PHY interface // - 5 if using 16-bit PHY interface gusbcfg &= ~GUSBCFG_TRDT_Msk; - gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; - /* at32f402_405 does not actually support 16-bit */ - #if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 - gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 9u : 9u) << GUSBCFG_TRDT_Pos; - #endif +#if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 // at32f402_405 does not actually support 16-bit + gusbcfg |= 9u << GUSBCFG_TRDT_Pos; +#else + gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; +#endif dwc2->gusbcfg = gusbcfg; -- cgit v1.3.1