From e7d59fba3506d2ae0d60f4c019153e1d9d349262 Mon Sep 17 00:00:00 2001
From: UMRnInside <30196401+UMRnInside@users.noreply.github.com>
Date: Sun, 24 May 2026 10:21:41 +0800
Subject: Fix missing prototype in ch32v10x bsp

---
 hw/bsp/ch32v10x/family.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/bsp/ch32v10x/family.c b/hw/bsp/ch32v10x/family.c
index 6d52227d5..8eec9f4a1 100644
--- a/hw/bsp/ch32v10x/family.c
+++ b/hw/bsp/ch32v10x/family.c
@@ -69,13 +69,13 @@ uint32_t tusb_time_millis_api(void) {
 // 0x800 CSR register is writable in U-mode
 // according to manual: https://www.wch-ic.com/downloads/QingKeV3_Processor_Manual_PDF.html
 __attribute__((always_inline)) RV_STATIC_INLINE
-void __wch_vendor_enable_irq()
+void __wch_vendor_enable_irq(void)
 {
   __asm volatile ("csrs 0x800, %0" : : "r" (0x88) );
 }
 
 __attribute__((always_inline)) RV_STATIC_INLINE
-void __wch_vendor_disable_irq()
+void __wch_vendor_disable_irq(void)
 {
   __asm volatile ("csrc 0x800, %0" : : "r" (0x88) );
   __asm volatile ("fence.i");
@@ -84,7 +84,7 @@ void __wch_vendor_disable_irq()
 void board_init(void) {
   /* __disable_irq() in CH32V103 EVT attempts to call
    * `csrc mstatus, 0x88` in U-mode, which is allowed ONLY in M-mode.
-   * Disable this to avoid hard-fault. */
+   * Replace this with CSR 0x800 to avoid hard-fault. */
   __wch_vendor_disable_irq();
 
 #if CFG_TUSB_OS == OPT_OS_NONE
-- 
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