From 4579b4f8255a5ed06e276978474fab7c7567445a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 2 Jul 2025 14:41:16 +0700
Subject: add doc for building examples with cmake build system change ci
 matrix build: - github build make/cmake one per family on push only -
 circicle do full cmake build for all toolchain (missing rx-gcc)

---
 docs/reference/getting_started.rst | 72 ++++++++++++++++++++++++++------------
 1 file changed, 49 insertions(+), 23 deletions(-)

(limited to 'docs/reference')

diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst
index 37745d6a1..ee68f6386 100644
--- a/docs/reference/getting_started.rst
+++ b/docs/reference/getting_started.rst
@@ -5,12 +5,12 @@ Getting Started
 Add TinyUSB to your project
 ---------------------------
 
-It is relatively simple to incorporate tinyusb to your project
+To incorporate tinyusb to your project
 
 * Copy or ``git submodule`` this repo into your project in a subfolder. Let's say it is ``your_project/tinyusb``
 * Add all the ``.c`` in the ``tinyusb/src`` folder to your project
 * Add ``your_project/tinyusb/src`` to your include path. Also make sure your current include path also contains the configuration file ``tusb_config.h``.
-* Make sure all required macros are all defined properly in ``tusb_config.h`` (configure file in demo application is sufficient, but you need to add a few more such as ``CFG_TUSB_MCU``, ``CFG_TUSB_OS`` since they are passed by IDE/compiler to maintain a unique configure for all boards).
+* Make sure all required macros are all defined properly in ``tusb_config.h`` (configure file in demo application is sufficient, but you need to add a few more such as ``CFG_TUSB_MCU``, ``CFG_TUSB_OS`` since they are passed by make/cmake to maintain a unique configure for all boards).
 * If you use the device stack, make sure you have created/modified usb descriptors for your own need. Ultimately you need to implement all **tud descriptor** callbacks for the stack to work.
 * Add ``tusb_init(rhport, role)`` call to your reset initialization code.
 * Call ``tusb_int_handler(rhport, in_isr)`` in your USB IRQ Handler
@@ -75,24 +75,36 @@ The hardware code is located in ``hw/bsp`` folder, and is organized by family/bo
 .. code-block:: bash
 
    $ cd examples/device/cdc_msc
-   $ make BOARD=raspberry_pi_pico get-deps
+   $ make BOARD=feather_nrf52840_express get-deps
 
 You only need to do this once per family. Check out `complete list of dependencies and their designated path here <dependencies.rst>`_
 
-Build
-^^^^^
+Build Examples
+^^^^^^^^^^^^^^
 
-To build example, first change directory to an example folder.
+Examples support make and cmake build system, though some MCU family such as espressif/rp2040 only support cmake. First change directory to an example folder.
 
 .. code-block:: bash
 
    $ cd examples/device/cdc_msc
 
-Then compile with ``make BOARD={board_name} all`` , for example
+Then compile with make or cmake
+
+.. code-block:: bash
+
+   $ # make
+   $ make BOARD=feather_nrf52840_express all
+
+   $ # cmake
+   $ mkdir build && cd build
+   $ cmake -DBOARD=raspberry_pi_pico ..
+   $ make
+
+To list all available targets with cmake
 
 .. code-block:: bash
 
-   $ make BOARD=raspberry_pi_pico all
+   $ cmake --build . --target help
 
 Note: some examples especially those that uses Vendor class (e.g webUSB) may requires udev permission on Linux (and/or macOS) to access usb device. It depends on your OS distro, typically copy ``99-tinyusb.rules`` and reload your udev is good to go
 
@@ -104,20 +116,24 @@ Note: some examples especially those that uses Vendor class (e.g webUSB) may req
 RootHub Port Selection
 ~~~~~~~~~~~~~~~~~~~~~~
 
-If a board has several ports, one port is chosen by default in the individual board.mk file. Use option ``PORT=x`` To choose another port. For example to select the HS port of a STM32F746Disco board, use:
+If a board has several ports, one port is chosen by default in the individual board.mk file. Use option ``RHPORT_DEVICE=x`` or ``RHPORT_HOST=x`` To choose another port. For example to select the HS port of a STM32F746Disco board, use:
 
 .. code-block:: bash
 
-   $ make BOARD=stm32f746disco PORT=1 all
+   $ make BOARD=stm32f746disco RHPORT_DEVICE=1 all
+
+   $ cmake -DBOARD=stm32f746disco -DRHPORT_DEVICE=1 ..
 
 Port Speed
 ~~~~~~~~~~
 
-A MCU can support multiple operational speed. By default, the example build system will use the fastest supported on the board. Use option ``SPEED=full/high`` e.g To force F723 operate at full instead of default high speed
+A MCU can support multiple operational speed. By default, the example build system will use the fastest supported on the board. Use option ``RHPORT_DEVICE_SPEED=OPT_MODE_FULL/HIGH_SPEED/`` or ``RHPORT_HOST_SPEED=OPT_MODE_FULL/HIGH_SPEED/`` e.g To force F723 operate at full instead of default high speed
 
 .. code-block:: bash
 
-   $ make BOARD=stm32f746disco SPEED=full all
+   $ make BOARD=stm32f746disco RHPORT_DEVICE_SPEED=OPT_MODE_FULL_SPEED all
+
+   $ cmake -DBOARD=stm32f746disco -DRHPORT_DEVICE_SPEED=OPT_MODE_FULL_SPEED ..
 
 Size Analysis
 ~~~~~~~~~~~~~
@@ -137,6 +153,8 @@ To compile for debugging add ``DEBUG=1``\ , for example
 
    $ make BOARD=feather_nrf52840_express DEBUG=1 all
 
+   $ cmake -DBOARD=feather_nrf52840_express -DCMAKE_BUILD_TYPE=Debug ..
+
 Log
 ~~~
 
@@ -146,6 +164,8 @@ Should you have an issue running example and/or submitting an bug report. You co
 
    $ make BOARD=feather_nrf52840_express LOG=2 all
 
+   $ cmake -DBOARD=feather_nrf52840_express -DLOG=2 ..
+
 Logger
 ~~~~~~
 
@@ -169,6 +189,9 @@ By default log message is printed via on-board UART which is slow and take lots
    $ make BOARD=feather_nrf52840_express LOG=2 LOGGER=rtt all
    $ make BOARD=feather_nrf52840_express LOG=2 LOGGER=swo all
 
+   $ cmake -DBOARD=feather_nrf52840_express -DLOG=2 -DLOGGER=rtt ..
+   $ cmake -DBOARD=feather_nrf52840_express -DLOG=2 -DLOGGER=swo ..
+
 Flash
 ^^^^^
 
@@ -179,11 +202,15 @@ Flash
    $ make BOARD=feather_nrf52840_express flash
    $ make SERIAL=/dev/ttyACM0 BOARD=feather_nrf52840_express flash
 
-Since jlink can be used with most of the boards, there is also ``flash-jlink`` target for your convenience.
+Since jlink/openocd can be used with most of the boards, there is also ``flash-jlink/openocd`` (make) and ``EXAMPLE-jlink/openocd`` target for your convenience. Note for stm32 board with stlink, you can use ``flash-stlink`` target as well.
 
 .. code-block:: bash
 
    $ make BOARD=feather_nrf52840_express flash-jlink
+   $ make BOARD=feather_nrf52840_express flash-openocd
+
+   $ cmake --build . --target cdc_msc-jlink
+   $ cmake --build . --target cdc_msc-openocd
 
 Some board use uf2 bootloader for drag & drop in to mass storage device, uf2 can be generated with ``uf2`` target
 
@@ -191,17 +218,18 @@ Some board use uf2 bootloader for drag & drop in to mass storage device, uf2 can
 
    $ make BOARD=feather_nrf52840_express all uf2
 
+   $ cmake --build . --target cdc_msc-uf2
+
 IAR Support
------------
+^^^^^^^^^^^
 
 Use project connection
-^^^^^^^^^^^^^^^^^^^^^^
+~~~~~~~~~~~~~~~~~~~~~~
 
 IAR Project Connection files are provided to import TinyUSB stack into your project.
 
 * A buildable project of your MCU need to be created in advance.
 
-
   * Take example of STM32F0:
 
     -  You need ``stm32l0xx.h``, ``startup_stm32f0xx.s``, ``system_stm32f0xx.c``.
@@ -212,15 +240,13 @@ IAR Project Connection files are provided to import TinyUSB stack into your proj
    Click ``New Group ...``, name it to ``TUSB``, Click ``Add Variable ...``, name it to ``TUSB_DIR``, change it's value to the path of your TinyUSB stack,
    for example ``C:\\tinyusb``
 
-Import stack only
-~~~~~~~~~~~~~~~~~
+**Import stack only**
 
-1. Open ``Project -> Add project Connection ...``, click ``OK``, choose ``tinyusb\\tools\\iar_template.ipcf``.
+Open ``Project -> Add project Connection ...``, click ``OK``, choose ``tinyusb\\tools\\iar_template.ipcf``.
 
-Run examples
-~~~~~~~~~~~~
+**Run examples**
 
-1. (Python3 is needed) Run ``iar_gen.py`` to generate .ipcf files of examples:
+1. Run ``iar_gen.py`` to generate .ipcf files of examples:
 
    .. code-block::
 
@@ -231,7 +257,7 @@ Run examples
    For example ``C:\\tinyusb\\examples\\device\\cdc_msc\\iar_cdc_msc.ipcf``
 
 Native CMake support (9.50.1+)
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 With 9.50.1 release, IAR added experimental native CMake support (strangely not mentioned in public release note). Now it's possible to import CMakeLists.txt then build and debug as a normal project.
 
-- 
cgit v1.3.1


From 52f0427096a9e20b62dc3055a153a60e50317297 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 2 Jul 2025 16:34:17 +0700
Subject: remove make wrapper for rp2040/espressif

---
 docs/reference/getting_started.rst |  2 +-
 hw/bsp/rp2040/family.mk            | 16 ----------------
 tools/build.py                     | 21 +++++++++++++--------
 3 files changed, 14 insertions(+), 25 deletions(-)
 delete mode 100644 hw/bsp/rp2040/family.mk

(limited to 'docs/reference')

diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst
index ee68f6386..5b009f21e 100644
--- a/docs/reference/getting_started.rst
+++ b/docs/reference/getting_started.rst
@@ -82,7 +82,7 @@ You only need to do this once per family. Check out `complete list of dependenci
 Build Examples
 ^^^^^^^^^^^^^^
 
-Examples support make and cmake build system, though some MCU family such as espressif/rp2040 only support cmake. First change directory to an example folder.
+Examples support make and cmake build system for most MCUs, however some MCU families such as espressif or rp2040 only support cmake. First change directory to an example folder.
 
 .. code-block:: bash
 
diff --git a/hw/bsp/rp2040/family.mk b/hw/bsp/rp2040/family.mk
deleted file mode 100644
index 813683c54..000000000
--- a/hw/bsp/rp2040/family.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-JLINK_DEVICE = rp2040_m0_0
-PYOCD_TARGET = rp2040
-
-ifeq ($(DEBUG), 1)
-CMAKE_DEFSYM += -DCMAKE_BUILD_TYPE=Debug
-endif
-
-$(BUILD):
-	cmake -S . -B $(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) -DPICO_BUILD_DOCS=0 $(CMAKE_DEFSYM)
-
-all: $(BUILD)
-	$(MAKE) -C $(BUILD)
-
-flash: flash-pyocd
-flash-uf2:
-	@$(CP) $(BUILD)/$(PROJECT).uf2 /media/$(USER)/RPI-RP2
diff --git a/tools/build.py b/tools/build.py
index eaa383d73..f639fba81 100755
--- a/tools/build.py
+++ b/tools/build.py
@@ -154,16 +154,21 @@ def make_one_example(example, board, make_option):
 
 def make_board(board, toolchain):
     print(build_separator)
-    all_examples = get_examples(find_family(board))
+    family = find_family(board);
+    all_examples = get_examples(family)
     start_time = time.monotonic()
     ret = [0, 0, 0]
-    with Pool(processes=os.cpu_count()) as pool:
-        pool_args = list((map(lambda e, b=board, o=f"TOOLCHAIN={toolchain}": [e, b, o], all_examples)))
-        r = pool.starmap(make_one_example, pool_args)
-        # sum all element of same index (column sum)
-        ret = list(map(sum, list(zip(*r))))
-    example = 'all'
-    print_build_result(board, example, 0 if ret[1] == 0 else 1, time.monotonic() - start_time)
+    if family == 'espressif' or family == 'rp2040':
+        # espressif and rp2040 do not support make, use cmake instead
+        final_status = 2
+    else:
+        with Pool(processes=os.cpu_count()) as pool:
+            pool_args = list((map(lambda e, b=board, o=f"TOOLCHAIN={toolchain}": [e, b, o], all_examples)))
+            r = pool.starmap(make_one_example, pool_args)
+            # sum all element of same index (column sum)
+            ret = list(map(sum, list(zip(*r))))
+        final_status = 0 if ret[1] == 0 else 1
+    print_build_result(board, 'all', final_status, time.monotonic() - start_time)
     return ret
 
 
-- 
cgit v1.3.1


From a64e3eb0aa661db14eb647e2f75059815741112f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 2 Jul 2025 17:27:03 +0700
Subject: update board_test always output to uart regardless of LOGGER option

---
 docs/reference/getting_started.rst    |  4 ++--
 examples/build_system/make/make.mk    | 19 ++++++++-----------
 examples/device/board_test/src/main.c |  6 ++++++
 hw/bsp/board.c                        |  1 -
 hw/bsp/family_support.cmake           |  2 ++
 test/fuzz/make.mk                     |  6 ------
 6 files changed, 18 insertions(+), 20 deletions(-)

(limited to 'docs/reference')

diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst
index 5b009f21e..bb9ff1cb4 100644
--- a/docs/reference/getting_started.rst
+++ b/docs/reference/getting_started.rst
@@ -256,8 +256,8 @@ Open ``Project -> Add project Connection ...``, click ``OK``, choose ``tinyusb\\
 2. Open ``Project -> Add project Connection ...``, click ``OK``, choose ``tinyusb\\examples\\(.ipcf of example)``.
    For example ``C:\\tinyusb\\examples\\device\\cdc_msc\\iar_cdc_msc.ipcf``
 
-Native CMake support (9.50.1+)
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Native CMake support
+~~~~~~~~~~~~~~~~~~~~
 
 With 9.50.1 release, IAR added experimental native CMake support (strangely not mentioned in public release note). Now it's possible to import CMakeLists.txt then build and debug as a normal project.
 
diff --git a/examples/build_system/make/make.mk b/examples/build_system/make/make.mk
index dbc73903e..f70748d34 100644
--- a/examples/build_system/make/make.mk
+++ b/examples/build_system/make/make.mk
@@ -123,27 +123,24 @@ endif
 ifeq (${MAX3421_HOST},1)
   SRC_C += src/portable/analog/max3421/hcd_max3421.c
   CFLAGS += -DCFG_TUH_MAX3421=1
-  CMAKE_DEFSYM +=	-DMAX3421_HOST=1
 endif
 
 # Log level is mapped to TUSB DEBUG option
 ifneq ($(LOG),)
-  CMAKE_DEFSYM +=	-DLOG=$(LOG)
   CFLAGS += -DCFG_TUSB_DEBUG=$(LOG)
 endif
 
 # Logger: default is uart, can be set to rtt or swo
-ifneq ($(LOGGER),)
-  CMAKE_DEFSYM +=	-DLOGGER=$(LOGGER)
-endif
-
 ifeq ($(LOGGER),rtt)
-  CFLAGS += -DLOGGER_RTT -DSEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL
-  RTT_SRC = lib/SEGGER_RTT
-  INC   += $(TOP)/$(RTT_SRC)/RTT
-  SRC_C += $(RTT_SRC)/RTT/SEGGER_RTT.c
-else ifeq ($(LOGGER),swo)
+  CFLAGS += -DLOGGER_RTT
+  #CFLAGS += -DSEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL
+  INC   += $(TOP)/$(lib/SEGGER_RTT)/RTT
+  SRC_C += $(lib/SEGGER_RTT)/RTT/SEGGER_RTT.c
+endif
+ifeq ($(LOGGER),swo)
   CFLAGS += -DLOGGER_SWO
+else
+  CFLAGS += -DLOGGER_UART
 endif
 
 # CPU specific flags
diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c
index 2c6ab6288..d91a8760e 100644
--- a/examples/device/board_test/src/main.c
+++ b/examples/device/board_test/src/main.c
@@ -52,6 +52,9 @@ int main(void) {
     int ch = board_getchar();
     if (ch > 0) {
       board_putchar(ch);
+      #ifndef LOGGER_UART
+      board_uart_write(&ch, 1);
+      #endif
     }
 
     // Blink and print every interval ms
@@ -61,7 +64,10 @@ int main(void) {
       if (ch < 0) {
         // skip if echoing
         printf(HELLO_STR);
+
+        #ifndef LOGGER_UART
         board_uart_write(HELLO_STR, strlen(HELLO_STR));
+        #endif
       }
 
       board_led_write(led_state);
diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 8f2f93306..1ba5a1b9d 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -60,7 +60,6 @@ int sys_read(int fhdl, char *buf, size_t count) {
   int rd = (int) SEGGER_RTT_Read(0, buf, count);
   return (rd > 0) ? rd : -1;
 }
-
 #endif
 
 #elif defined(LOGGER_SWO)
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 0509fdc28..9ec80df91 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -221,6 +221,8 @@ function(family_configure_common TARGET RTOS)
       target_include_directories(${TARGET}  PUBLIC ${TOP}/lib/SEGGER_RTT/RTT)
 #      target_compile_definitions(${TARGET}  PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL)
     endif ()
+  else ()
+    target_compile_definitions(${TARGET} PUBLIC LOGGER_UART)
   endif ()
 
   if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang")
diff --git a/test/fuzz/make.mk b/test/fuzz/make.mk
index b7b6d6a75..e9aa80bf1 100644
--- a/test/fuzz/make.mk
+++ b/test/fuzz/make.mk
@@ -124,11 +124,5 @@ endif
 
 # Log level is mapped to TUSB DEBUG option
 ifneq ($(LOG),)
-  CMAKE_DEFSYM +=	-DLOG=$(LOG)
   CFLAGS += -DCFG_TUSB_DEBUG=$(LOG)
 endif
-
-# Logger: default is uart, can be set to rtt or swo
-ifneq ($(LOGGER),)
-	CMAKE_DEFSYM +=	-DLOGGER=$(LOGGER)
-endif
-- 
cgit v1.3.1


From aacd73ba42dfe58706fe83f8521ebe0ff957a79c Mon Sep 17 00:00:00 2001
From: Jie Feng <hjf3108@gmail.com>
Date: Thu, 24 Jul 2025 22:30:10 +0800
Subject: Add nanoch32v305

---
 docs/reference/boards.rst                          |   3 +-
 .../ch32v307/boards/ch32v307v_r1_1v0/board.cmake   |   4 -
 hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h    |  55 --
 hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.mk   |   1 -
 hw/bsp/ch32v307/ch32v307.ld                        | 167 -----
 hw/bsp/ch32v307/ch32v30x_conf.h                    |  38 -
 hw/bsp/ch32v307/ch32v30x_it.c                      |  47 --
 hw/bsp/ch32v307/ch32v30x_it.h                      |  16 -
 hw/bsp/ch32v307/debug_uart.c                       | 119 ----
 hw/bsp/ch32v307/debug_uart.h                       |  31 -
 hw/bsp/ch32v307/family.c                           | 195 ------
 hw/bsp/ch32v307/family.cmake                       | 128 ----
 hw/bsp/ch32v307/family.mk                          |  64 --
 hw/bsp/ch32v307/system_ch32v30x.c                  | 776 ---------------------
 hw/bsp/ch32v307/system_ch32v30x.h                  |  27 -
 hw/bsp/ch32v307/wch-riscv.cfg                      |  17 -
 .../ch32v30x/boards/ch32v307v_r1_1v0/board.cmake   |   4 +
 hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.h    |  55 ++
 hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.mk   |   1 +
 hw/bsp/ch32v30x/boards/nanoch32v305/board.cmake    |   4 +
 hw/bsp/ch32v30x/boards/nanoch32v305/board.h        |  48 ++
 hw/bsp/ch32v30x/boards/nanoch32v305/board.mk       |   1 +
 hw/bsp/ch32v30x/ch32v307.ld                        | 167 +++++
 hw/bsp/ch32v30x/ch32v30x_conf.h                    |  38 +
 hw/bsp/ch32v30x/ch32v30x_it.c                      |  47 ++
 hw/bsp/ch32v30x/ch32v30x_it.h                      |  16 +
 hw/bsp/ch32v30x/debug_uart.c                       | 119 ++++
 hw/bsp/ch32v30x/debug_uart.h                       |  31 +
 hw/bsp/ch32v30x/family.c                           | 200 ++++++
 hw/bsp/ch32v30x/family.cmake                       | 128 ++++
 hw/bsp/ch32v30x/family.mk                          |  64 ++
 hw/bsp/ch32v30x/system_ch32v30x.c                  | 776 +++++++++++++++++++++
 hw/bsp/ch32v30x/system_ch32v30x.h                  |  27 +
 hw/bsp/ch32v30x/wch-riscv.cfg                      |  17 +
 tools/get_deps.py                                  |   2 +-
 35 files changed, 1746 insertions(+), 1687 deletions(-)
 delete mode 100644 hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.cmake
 delete mode 100644 hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h
 delete mode 100644 hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.mk
 delete mode 100644 hw/bsp/ch32v307/ch32v307.ld
 delete mode 100644 hw/bsp/ch32v307/ch32v30x_conf.h
 delete mode 100644 hw/bsp/ch32v307/ch32v30x_it.c
 delete mode 100644 hw/bsp/ch32v307/ch32v30x_it.h
 delete mode 100644 hw/bsp/ch32v307/debug_uart.c
 delete mode 100644 hw/bsp/ch32v307/debug_uart.h
 delete mode 100644 hw/bsp/ch32v307/family.c
 delete mode 100644 hw/bsp/ch32v307/family.cmake
 delete mode 100644 hw/bsp/ch32v307/family.mk
 delete mode 100644 hw/bsp/ch32v307/system_ch32v30x.c
 delete mode 100644 hw/bsp/ch32v307/system_ch32v30x.h
 delete mode 100644 hw/bsp/ch32v307/wch-riscv.cfg
 create mode 100644 hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.cmake
 create mode 100644 hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.h
 create mode 100644 hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.mk
 create mode 100644 hw/bsp/ch32v30x/boards/nanoch32v305/board.cmake
 create mode 100644 hw/bsp/ch32v30x/boards/nanoch32v305/board.h
 create mode 100644 hw/bsp/ch32v30x/boards/nanoch32v305/board.mk
 create mode 100644 hw/bsp/ch32v30x/ch32v307.ld
 create mode 100644 hw/bsp/ch32v30x/ch32v30x_conf.h
 create mode 100644 hw/bsp/ch32v30x/ch32v30x_it.c
 create mode 100644 hw/bsp/ch32v30x/ch32v30x_it.h
 create mode 100644 hw/bsp/ch32v30x/debug_uart.c
 create mode 100644 hw/bsp/ch32v30x/debug_uart.h
 create mode 100644 hw/bsp/ch32v30x/family.c
 create mode 100644 hw/bsp/ch32v30x/family.cmake
 create mode 100644 hw/bsp/ch32v30x/family.mk
 create mode 100644 hw/bsp/ch32v30x/system_ch32v30x.c
 create mode 100644 hw/bsp/ch32v30x/system_ch32v30x.h
 create mode 100644 hw/bsp/ch32v30x/wch-riscv.cfg

(limited to 'docs/reference')

diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst
index 41e765683..824b1214b 100644
--- a/docs/reference/boards.rst
+++ b/docs/reference/boards.rst
@@ -326,5 +326,6 @@ ch32v103r_r1_1v0  CH32V103R-R1-1v1  ch32v10x  https://github.com/openwch/ch32v10
 ch32v203c_r0_1v0  CH32V203C-R0-1v0  ch32v20x  https://github.com/openwch/ch32v20x/tree/main/SCHPCB/CH32V203C-R0
 ch32v203g_r0_1v0  CH32V203G-R0-1v0  ch32v20x  https://github.com/openwch/ch32v20x/tree/main/SCHPCB/CH32V203C-R0
 nanoch32v203      nanoCH32V203      ch32v20x  https://github.com/wuxx/nanoCH32V203
-ch32v307v_r1_1v0  CH32V307V-R1-1v0  ch32v307  https://github.com/openwch/ch32v307/tree/main/SCHPCB/CH32V307V-R1-1v0
+nanoch32v305      nanoCH32V305      ch32v30x  https://github.com/wuxx/nanoCH32V305
+ch32v307v_r1_1v0  CH32V307V-R1-1v0  ch32v30x  https://github.com/openwch/ch32v307/tree/main/SCHPCB/CH32V307V-R1-1v0
 ================  ================  ========  =====================================================================  ======
diff --git a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.cmake b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.cmake
deleted file mode 100644
index 9f5682042..000000000
--- a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.cmake
+++ /dev/null
@@ -1,4 +0,0 @@
-function(update_board TARGET)
-#  target_compile_definitions(${TARGET} PUBLIC
-#    )
-endfunction()
diff --git a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h
deleted file mode 100644
index 491347034..000000000
--- a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2023 Ha Thach (tinyusb.org) for Adafruit Industries
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-/* metadata:
-   name: CH32V307V-R1-1v0
-   url: https://github.com/openwch/ch32v307/tree/main/SCHPCB/CH32V307V-R1-1v0
-*/
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED: need to wire pin LED1 to PC0 in the J3 header
-#define LED_PORT              GPIOC
-#define LED_PIN               GPIO_Pin_0
-#define LED_STATE_ON          0
-#define LED_CLOCK_EN()        RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE)
-
-// Button: need to wire pin KEY to PC1 in the J3 header
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_Pin_1
-#define BUTTON_STATE_ACTIVE   0
-#define BUTTON_CLOCK_EN()     do { } while(0) // same as LED clock, no need to do anything
-
-// TODO UART port
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif
diff --git a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.mk b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.mk
deleted file mode 100644
index 4e91d8938..000000000
--- a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.mk
+++ /dev/null
@@ -1 +0,0 @@
-LD_FILE = $(FAMILY_PATH)/ch32v307.ld
diff --git a/hw/bsp/ch32v307/ch32v307.ld b/hw/bsp/ch32v307/ch32v307.ld
deleted file mode 100644
index 55bd10cd0..000000000
--- a/hw/bsp/ch32v307/ch32v307.ld
+++ /dev/null
@@ -1,167 +0,0 @@
-ENTRY( _start )
-
-__stack_size = 4096;
-
-PROVIDE( _stack_size = __stack_size );
-
-
-MEMORY
-{
-	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 288K
-	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
-}
-
-
-SECTIONS
-{
-
-	.init :
-	{
-		_sinit = .;
-		. = ALIGN(4);
-		KEEP(*(SORT_NONE(.init)))
-		. = ALIGN(4);
-		_einit = .;
-	} >FLASH AT>FLASH
-
-  .vector :
-  {
-      *(.vector);
-	  . = ALIGN(64);
-  } >FLASH AT>FLASH
-
-	.text :
-	{
-		. = ALIGN(4);
-		*(.text)
-		*(.text.*)
-		*(.rodata)
-		*(.rodata*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.gnu.linkonce.t.*)
-		. = ALIGN(4);
-	} >FLASH AT>FLASH
-
-	.fini :
-	{
-		KEEP(*(SORT_NONE(.fini)))
-		. = ALIGN(4);
-	} >FLASH AT>FLASH
-
-	PROVIDE( _etext = . );
-	PROVIDE( _eitcm = . );
-
-	.preinit_array  :
-	{
-	  PROVIDE_HIDDEN (__preinit_array_start = .);
-	  KEEP (*(.preinit_array))
-	  PROVIDE_HIDDEN (__preinit_array_end = .);
-	} >FLASH AT>FLASH
-
-	.init_array     :
-	{
-	  PROVIDE_HIDDEN (__init_array_start = .);
-	  KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
-	  KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
-	  PROVIDE_HIDDEN (__init_array_end = .);
-	} >FLASH AT>FLASH
-
-	.fini_array     :
-	{
-	  PROVIDE_HIDDEN (__fini_array_start = .);
-	  KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
-	  KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
-	  PROVIDE_HIDDEN (__fini_array_end = .);
-	} >FLASH AT>FLASH
-
-	.ctors          :
-	{
-	  /* gcc uses crtbegin.o to find the start of
-	     the constructors, so we make sure it is
-	     first.  Because this is a wildcard, it
-	     doesn't matter if the user does not
-	     actually link against crtbegin.o; the
-	     linker won't look for a file to match a
-	     wildcard.  The wildcard also means that it
-	     doesn't matter which directory crtbegin.o
-	     is in.  */
-	  KEEP (*crtbegin.o(.ctors))
-	  KEEP (*crtbegin?.o(.ctors))
-	  /* We don't want to include the .ctor section from
-	     the crtend.o file until after the sorted ctors.
-	     The .ctor section from the crtend file contains the
-	     end of ctors marker and it must be last */
-	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
-	  KEEP (*(SORT(.ctors.*)))
-	  KEEP (*(.ctors))
-	} >FLASH AT>FLASH
-
-	.dtors          :
-	{
-	  KEEP (*crtbegin.o(.dtors))
-	  KEEP (*crtbegin?.o(.dtors))
-	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
-	  KEEP (*(SORT(.dtors.*)))
-	  KEEP (*(.dtors))
-	} >FLASH AT>FLASH
-
-	.dalign :
-	{
-		. = ALIGN(4);
-		PROVIDE(_data_vma = .);
-	} >RAM AT>FLASH
-
-	.dlalign :
-	{
-		. = ALIGN(4);
-		PROVIDE(_data_lma = .);
-	} >FLASH AT>FLASH
-
-	.data :
-	{
-    	*(.gnu.linkonce.r.*)
-    	*(.data .data.*)
-    	*(.gnu.linkonce.d.*)
-		. = ALIGN(8);
-    	PROVIDE( __global_pointer$ = . + 0x800 );
-    	*(.sdata .sdata.*)
-		*(.sdata2.*)
-    	*(.gnu.linkonce.s.*)
-    	. = ALIGN(8);
-    	*(.srodata.cst16)
-    	*(.srodata.cst8)
-    	*(.srodata.cst4)
-    	*(.srodata.cst2)
-    	*(.srodata .srodata.*)
-    	. = ALIGN(4);
-		PROVIDE( _edata = .);
-	} >RAM AT>FLASH
-
-	.bss :
-	{
-		. = ALIGN(4);
-		PROVIDE( _sbss = .);
-  	    *(.sbss*)
-        *(.gnu.linkonce.sb.*)
-		*(.bss*)
-     	*(.gnu.linkonce.b.*)
-		*(COMMON*)
-		. = ALIGN(4);
-		PROVIDE( _ebss = .);
-	} >RAM AT>FLASH
-
-	PROVIDE( _end = _ebss);
-	PROVIDE( end = . );
-
-    .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
-    {
-        PROVIDE( _heap_end = . );
-        . = ALIGN(4);
-        PROVIDE(_susrstack = . );
-        . = . + __stack_size;
-        PROVIDE( _eusrstack = .);
-        __freertos_irq_stack_top = .;
-    } >RAM
-
-}
diff --git a/hw/bsp/ch32v307/ch32v30x_conf.h b/hw/bsp/ch32v307/ch32v30x_conf.h
deleted file mode 100644
index 0b86ad390..000000000
--- a/hw/bsp/ch32v307/ch32v30x_conf.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/********************************** (C) COPYRIGHT *******************************
-* File Name          : ch32v30x_conf.h
-* Author             : WCH
-* Version            : V1.0.0
-* Date               : 2021/06/06
-* Description        : Library configuration file.
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* SPDX-License-Identifier: Apache-2.0
-*******************************************************************************/
-#ifndef __CH32V30x_CONF_H
-#define __CH32V30x_CONF_H
-
-#include "ch32v30x_adc.h"
-#include "ch32v30x_bkp.h"
-#include "ch32v30x_can.h"
-#include "ch32v30x_crc.h"
-#include "ch32v30x_dac.h"
-#include "ch32v30x_dbgmcu.h"
-#include "ch32v30x_dma.h"
-#include "ch32v30x_exti.h"
-#include "ch32v30x_flash.h"
-#include "ch32v30x_fsmc.h"
-#include "ch32v30x_gpio.h"
-#include "ch32v30x_i2c.h"
-#include "ch32v30x_iwdg.h"
-#include "ch32v30x_pwr.h"
-#include "ch32v30x_rcc.h"
-#include "ch32v30x_rtc.h"
-#include "ch32v30x_sdio.h"
-#include "ch32v30x_spi.h"
-#include "ch32v30x_tim.h"
-#include "ch32v30x_usart.h"
-#include "ch32v30x_wwdg.h"
-#include "ch32v30x_it.h"
-#include "ch32v30x_misc.h"
-
-
-#endif /* __CH32V30x_CONF_H */
diff --git a/hw/bsp/ch32v307/ch32v30x_it.c b/hw/bsp/ch32v307/ch32v30x_it.c
deleted file mode 100644
index c329c5613..000000000
--- a/hw/bsp/ch32v307/ch32v30x_it.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/********************************** (C) COPYRIGHT *******************************
-* File Name          : ch32v30x_it.c
-* Author             : WCH
-* Version            : V1.0.0
-* Date               : 2021/06/06
-* Description        : Main Interrupt Service Routines.
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* SPDX-License-Identifier: Apache-2.0
-*******************************************************************************/
-#include "ch32v30x_it.h"
-
-void NMI_Handler(void) __attribute__((naked));
-void HardFault_Handler(void) __attribute__((naked));
-
-/*********************************************************************
- * @fn      NMI_Handler
- *
- * @brief   This function handles NMI exception.
- *
- * @return  none
- */
-void NMI_Handle(void){
-      __asm volatile ("call NMI_Handler_impl; mret");
-}
-
-__attribute__((used)) void NMI_Handler_impl(void)
-{
-
-}
-
-/*********************************************************************
- * @fn      HardFault_Handler
- *
- * @brief   This function handles Hard Fault exception.
- *
- * @return  none
- */
-void HardFault_Handler(void){
-      __asm volatile ("call HardFault_Handler_impl; mret");
-}
-
-__attribute__((used)) void HardFault_Handler_impl(void)
-{
-  while (1)
-  {
-  }
-}
diff --git a/hw/bsp/ch32v307/ch32v30x_it.h b/hw/bsp/ch32v307/ch32v30x_it.h
deleted file mode 100644
index f3977a8be..000000000
--- a/hw/bsp/ch32v307/ch32v30x_it.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/********************************** (C) COPYRIGHT *******************************
-* File Name          : ch32v30x_it.h
-* Author             : WCH
-* Version            : V1.0.0
-* Date               : 2021/06/06
-* Description        : This file contains the headers of the interrupt handlers.
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* SPDX-License-Identifier: Apache-2.0
-*******************************************************************************/
-#ifndef __CH32V30x_IT_H
-#define __CH32V30x_IT_H
-
-// #include "debug.h"
-
-
-#endif /* __CH32V30x_IT_H */
diff --git a/hw/bsp/ch32v307/debug_uart.c b/hw/bsp/ch32v307/debug_uart.c
deleted file mode 100644
index 2fd3a9d64..000000000
--- a/hw/bsp/ch32v307/debug_uart.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2022 Greg Davill
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "debug_uart.h"
-
-#ifdef __GNUC__
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wstrict-prototypes"
-#endif
-
-#include <ch32v30x.h>
-
-#ifdef __GNUC__
-#pragma GCC diagnostic pop
-#endif
-
-#define UART_RINGBUFFER_SIZE_TX 128
-#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1)
-
-static char tx_buf[UART_RINGBUFFER_SIZE_TX];
-static unsigned int tx_produce;
-static volatile unsigned int tx_consume;
-
-void USART1_IRQHandler(void) __attribute__((naked));
-void USART1_IRQHandler(void) {
-      __asm volatile ("call USART1_IRQHandler_impl; mret");
-}
-
-__attribute__((used)) void USART1_IRQHandler_impl(void)
-{
-	if(USART_GetITStatus(USART1, USART_IT_TC) != RESET)
-    {
-        USART_ClearITPendingBit(USART1, USART_IT_TC);
-
-		if(tx_consume != tx_produce) {
-			USART_SendData(USART1, tx_buf[tx_consume]);
-			tx_consume = (tx_consume + 1) & UART_RINGBUFFER_MASK_TX;
-		}
-    }
-
-}
-
-void uart_write(char c)
-{
-	unsigned int tx_produce_next = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX;
-
-    NVIC_DisableIRQ(USART1_IRQn);
-    if((tx_consume != tx_produce) || (USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET)) {
-		tx_buf[tx_produce] = c;
-		tx_produce = tx_produce_next;
-	} else {
-		USART_SendData(USART1, c);
-	}
-    NVIC_EnableIRQ(USART1_IRQn);
-}
-
-
-void uart_sync(void)
-{
-	while(tx_consume != tx_produce);
-}
-
-
-void usart_printf_init(uint32_t baudrate)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-  USART_InitTypeDef USART_InitStructure;
-
-  tx_produce = 0;
-  tx_consume = 0;
-
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
-
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-  USART_InitStructure.USART_BaudRate = baudrate;
-  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-  USART_InitStructure.USART_StopBits = USART_StopBits_1;
-  USART_InitStructure.USART_Parity = USART_Parity_No;
-  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-  USART_InitStructure.USART_Mode = USART_Mode_Tx;
-
-  USART_Init(USART1, &USART_InitStructure);
-  USART_ITConfig(USART1, USART_IT_TC, ENABLE);
-  USART_Cmd(USART1, ENABLE);
-
-  NVIC_InitTypeDef NVIC_InitStructure = { 0 };
-  NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
-  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
-  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
-  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-  NVIC_Init(&NVIC_InitStructure);
-}
diff --git a/hw/bsp/ch32v307/debug_uart.h b/hw/bsp/ch32v307/debug_uart.h
deleted file mode 100644
index a7e070585..000000000
--- a/hw/bsp/ch32v307/debug_uart.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2022 Greg Davill
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include <stdint.h>
-
-void uart_write(char c);
-void uart_sync(void);
-void usart_printf_init(uint32_t baudrate);
diff --git a/hw/bsp/ch32v307/family.c b/hw/bsp/ch32v307/family.c
deleted file mode 100644
index 48eb8a38c..000000000
--- a/hw/bsp/ch32v307/family.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2022 Greg Davill
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/* metadata:
-   manufacturer: WCH
-*/
-
-#include "stdio.h"
-
-// https://github.com/openwch/ch32v307/pull/90
-// https://github.com/openwch/ch32v20x/pull/12
-
-#ifdef __GNUC__
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wstrict-prototypes"
-#endif
-
-#include "debug_uart.h"
-#include "ch32v30x.h"
-
-#ifdef __GNUC__
-#pragma GCC diagnostic pop
-#endif
-
-#include "bsp/board_api.h"
-#include "board.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-
-// TODO maybe having FS as port0, HS as port1
-
-__attribute__((interrupt)) void USBHS_IRQHandler(void) {
-  #if CFG_TUD_WCH_USBIP_USBHS
-  tud_int_handler(0);
-  #endif
-}
-
-__attribute__((interrupt)) void OTG_FS_IRQHandler(void) {
-  #if CFG_TUD_WCH_USBIP_USBFS
-  tud_int_handler(0);
-  #endif
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-uint32_t SysTick_Config(uint32_t ticks) {
-  NVIC_EnableIRQ(SysTicK_IRQn);
-  SysTick->CTLR = 0;
-  SysTick->SR = 0;
-  SysTick->CNT = 0;
-  SysTick->CMP = ticks - 1;
-  SysTick->CTLR = 0xF;
-  return 0;
-}
-
-void board_init(void) {
-
-  /* Disable interrupts during init */
-  __disable_irq();
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  SysTick_Config(SystemCoreClock / 1000);
-#endif
-
-  usart_printf_init(CFG_BOARD_UART_BAUDRATE);
-
-#ifdef CH32V30x_D8C
-  // v305/v307: Highspeed USB
-  RCC_USBCLK48MConfig(RCC_USBCLK48MCLKSource_USBPHY);
-  RCC_USBHSPLLCLKConfig(RCC_HSBHSPLLCLKSource_HSE);
-  RCC_USBHSConfig(RCC_USBPLL_Div2);
-  RCC_USBHSPLLCKREFCLKConfig(RCC_USBHSPLLCKREFCLK_4M);
-  RCC_USBHSPHYPLLALIVEcmd(ENABLE);
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBHS, ENABLE);
-#endif
-
-  // Fullspeed USB
-  uint8_t otg_div;
-  switch (SystemCoreClock) {
-    case 48000000:  otg_div = RCC_OTGFSCLKSource_PLLCLK_Div1; break;
-    case 96000000:  otg_div = RCC_OTGFSCLKSource_PLLCLK_Div2; break;
-    case 144000000: otg_div = RCC_OTGFSCLKSource_PLLCLK_Div3; break;
-    default: TU_ASSERT(0,); break;
-  }
-  RCC_OTGFSCLKConfig(otg_div);
-  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_OTG_FS, ENABLE);
-
-  GPIO_InitTypeDef GPIO_InitStructure = {0};
-
-  // LED
-  LED_CLOCK_EN();
-  GPIO_InitStructure.GPIO_Pin = LED_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(LED_PORT, &GPIO_InitStructure);
-
-  // Button
-  BUTTON_CLOCK_EN();
-  GPIO_InitStructure.GPIO_Pin = BUTTON_PIN;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(BUTTON_PORT, &GPIO_InitStructure);
-
-  /* Enable interrupts globally */
-  __enable_irq();
-
-  board_delay(2);
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-__attribute__((interrupt)) void SysTick_Handler(void) {
-  SysTick->SR = 0;
-  system_ticks++;
-}
-
-uint32_t board_millis(void) {
-  return system_ticks;
-}
-
-#endif
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state) {
-  GPIO_WriteBit(LED_PORT, LED_PIN, state);
-}
-
-uint32_t board_button_read(void) {
-  return BUTTON_STATE_ACTIVE == GPIO_ReadInputDataBit(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len) {
-  (void) buf;
-  (void) len;
-  return 0;
-}
-
-int board_uart_write(void const* buf, int len) {
-  int txsize = len;
-  const char* bufc = (const char*) buf;
-  while (txsize--) {
-    uart_write(*bufc++);
-  }
-  uart_sync();
-  return len;
-}
-
-#ifdef USE_FULL_ASSERT
-/**
- * @brief  Reports the name of the source file and the source line number
- *         where the assert_param error has occurred.
- * @param  file: pointer to the source file name
- * @param  line: assert_param error line source number
- * @retval None
- */
-void assert_failed(char* file, uint32_t line) {
-  /* USER CODE BEGIN 6 */
-  /* User can add his own implementation to report the file name and line
-     number,
-     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line)
-   */
-  /* USER CODE END 6 */
-}
-#endif /* USE_FULL_ASSERT */
diff --git a/hw/bsp/ch32v307/family.cmake b/hw/bsp/ch32v307/family.cmake
deleted file mode 100644
index 446e850c5..000000000
--- a/hw/bsp/ch32v307/family.cmake
+++ /dev/null
@@ -1,128 +0,0 @@
-include_guard()
-
-set(CH32_FAMILY ch32v30x)
-set(SDK_DIR ${TOP}/hw/mcu/wch/ch32v307)
-set(SDK_SRC_DIR ${SDK_DIR}/EVT/EXAM/SRC)
-
-# include board specific
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
-
-# toolchain set up
-set(CMAKE_SYSTEM_CPU rv32imac-ilp32 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake)
-
-set(FAMILY_MCUS CH32V307 CACHE INTERNAL "")
-set(OPENOCD_OPTION "-f ${CMAKE_CURRENT_LIST_DIR}/wch-riscv.cfg")
-
-# default to highspeed, used to select USBFS / USBHS driver
-if (NOT DEFINED SPEED)
-  set(SPEED high)
-endif()
-
-#------------------------------------
-# BOARD_TARGET
-#------------------------------------
-# only need to be built ONCE for all examples
-function(add_board_target BOARD_TARGET)
-  if (TARGET ${BOARD_TARGET})
-    return()
-  endif()
-
-  if (NOT DEFINED LD_FILE_GNU)
-    set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/ch32v307.ld)
-  endif ()
-  set(LD_FILE_Clang ${LD_FILE_GNU})
-
-  if (NOT DEFINED STARTUP_FILE_GNU)
-    set(STARTUP_FILE_GNU ${SDK_SRC_DIR}/Startup/startup_${CH32_FAMILY}_D8C.S)
-  endif ()
-  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
-
-  add_library(${BOARD_TARGET} STATIC
-    ${SDK_SRC_DIR}/Core/core_riscv.c
-    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_gpio.c
-    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_misc.c
-    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_rcc.c
-    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_usart.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${CH32_FAMILY}_it.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/system_${CH32_FAMILY}.c
-    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
-    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    ${SDK_SRC_DIR}/Core
-    ${SDK_SRC_DIR}/Peripheral/inc
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    )
-  if (SPEED STREQUAL high)
-    target_compile_definitions(${BOARD_TARGET} PUBLIC
-      CFG_TUD_WCH_USBIP_USBHS=1
-#      BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-      )
-  else ()
-    target_compile_definitions(${BOARD_TARGET} PUBLIC
-      CFG_TUD_WCH_USBIP_USBFS=1
-      )
-  endif ()
-
-  update_board(${BOARD_TARGET})
-
-  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-    target_compile_options(${BOARD_TARGET} PUBLIC
-      -msmall-data-limit=8
-      -mno-save-restore
-      -fmessage-length=0
-      -fsigned-char
-      )
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_GNU}"
-      -nostartfiles
-      --specs=nosys.specs --specs=nano.specs
-      )
-  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
-    message(FATAL_ERROR "Clang is not supported for MSP432E4")
-  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--config=${LD_FILE_IAR}"
-      )
-  endif ()
-endfunction()
-
-
-#------------------------------------
-# Functions
-#------------------------------------
-function(family_configure_example TARGET RTOS)
-  family_configure_common(${TARGET} ${RTOS})
-
-  # Board target
-  add_board_target(board_${BOARD})
-
-  #---------- Port Specific ----------
-  # These files are built for each example since it depends on example's tusb_config.h
-  target_sources(${TARGET} PUBLIC
-    # BSP
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/debug_uart.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
-    )
-  target_include_directories(${TARGET} PUBLIC
-    # family, hw, board
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
-    )
-
-  # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_CH32V307)
-  target_sources(${TARGET} PUBLIC
-    ${TOP}/src/portable/wch/dcd_ch32_usbhs.c
-    ${TOP}/src/portable/wch/dcd_ch32_usbfs.c
-    )
-  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
-
-
-
-  # Flashing
-  family_add_bin_hex(${TARGET})
-  family_flash_openocd_wch(${TARGET})
-endfunction()
diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk
deleted file mode 100644
index bf2732106..000000000
--- a/hw/bsp/ch32v307/family.mk
+++ /dev/null
@@ -1,64 +0,0 @@
-# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable
-#CROSS_COMPILE ?= riscv32-unknown-elf-
-
-# Toolchain from https://nucleisys.com/download.php
-#CROSS_COMPILE ?= riscv-nuclei-elf-
-
-# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
-CROSS_COMPILE ?= riscv-none-elf-
-
-CH32_FAMILY = ch32v30x
-SDK_DIR = hw/mcu/wch/ch32v307
-SDK_SRC_DIR = $(SDK_DIR)/EVT/EXAM/SRC
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-CPU_CORE ?= rv32imac-ilp32
-
-# default to use high speed port, unless specified in board.mk or command line
-SPEED ?= high
-
-CFLAGS += \
-	-flto \
-	-msmall-data-limit=8 \
-	-mno-save-restore \
-	-fmessage-length=0 \
-	-fsigned-char \
-	-DCFG_TUSB_MCU=OPT_MCU_CH32V307 \
-
-# https://github.com/openwch/ch32v307/pull/90
-CFLAGS += -Wno-error=strict-prototypes
-
-ifeq ($(SPEED),high)
-  $(info "Using USBHS driver for HighSpeed mode")
-  CFLAGS += -DCFG_TUD_WCH_USBIP_USBHS=1
-else
-  $(info "Using USBFS driver for FullSpeed mode")
-  CFLAGS += -DCFG_TUD_WCH_USBIP_USBFS=1
-endif
-
-LDFLAGS_GCC += \
-	-nostdlib -nostartfiles \
-  --specs=nosys.specs --specs=nano.specs \
-
-SRC_C += \
-	src/portable/wch/dcd_ch32_usbhs.c \
-	src/portable/wch/dcd_ch32_usbfs.c \
-	$(SDK_SRC_DIR)/Core/core_riscv.c \
-	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_gpio.c \
-	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_misc.c \
-	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_rcc.c \
-	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_usart.c
-
-SRC_S += \
-	$(SDK_SRC_DIR)/Startup/startup_${CH32_FAMILY}_D8C.S
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(SDK_SRC_DIR)/Core \
-	$(TOP)/$(SDK_SRC_DIR)/Peripheral/inc
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
-
-OPENOCD_WCH_OPTION=-f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg
-flash: flash-openocd-wch
diff --git a/hw/bsp/ch32v307/system_ch32v30x.c b/hw/bsp/ch32v307/system_ch32v30x.c
deleted file mode 100644
index 23f783df4..000000000
--- a/hw/bsp/ch32v307/system_ch32v30x.c
+++ /dev/null
@@ -1,776 +0,0 @@
-/********************************** (C) COPYRIGHT *******************************
-* File Name          : system_ch32v30x.c
-* Author             : WCH
-* Version            : V1.0.0
-* Date               : 2021/06/06
-* Description        : CH32V30x Device Peripheral Access Layer System Source File.
-*                      For HSE = 8Mhz
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* SPDX-License-Identifier: Apache-2.0
-*********************************************************************************/
-#include "ch32v30x.h"
-
-/*
-* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
-* reset the HSI is used as SYSCLK source).
-* If none of the define below is enabled, the HSI is used as System clock source.
-*/
-// #define SYSCLK_FREQ_HSE    HSE_VALUE
-/* #define SYSCLK_FREQ_24MHz  24000000  */
-//#define SYSCLK_FREQ_48MHz  48000000
-/* #define SYSCLK_FREQ_56MHz  56000000  */
-//#define SYSCLK_FREQ_72MHz  72000000
-//#define SYSCLK_FREQ_96MHz  96000000
-//#define SYSCLK_FREQ_120MHz  120000000
-#define SYSCLK_FREQ_144MHz  144000000
-
-/* Clock Definitions */
-#ifdef SYSCLK_FREQ_HSE
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;          /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_24MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_48MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_56MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_72MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /* System Clock Frequency (Core Clock) */
-
-#elif defined SYSCLK_FREQ_96MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz;        /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_120MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz;        /* System Clock Frequency (Core Clock) */
-#elif defined SYSCLK_FREQ_144MHz
-  uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz;        /* System Clock Frequency (Core Clock) */
-
-#else /* HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = HSI_VALUE;                /* System Clock Frequency (Core Clock) */
-#endif
-
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
-
-/* system_private_function_proto_types */
-static void SetSysClock(void);
-
-#ifdef SYSCLK_FREQ_HSE
-  static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-  static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_48MHz
-  static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);
-#elif defined SYSCLK_FREQ_72MHz
-  static void SetSysClockTo72(void);
-
-#elif defined SYSCLK_FREQ_96MHz
-  static void SetSysClockTo96(void);
-#elif defined SYSCLK_FREQ_120MHz
-  static void SetSysClockTo120(void);
-#elif defined SYSCLK_FREQ_144MHz
-  static void SetSysClockTo144(void);
-
-#endif
-
-
-/*********************************************************************
- * @fn      SystemInit
- *
- * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
- *        the PLL and update the SystemCoreClock variable.
- *
- * @return  none
- */
-void SystemInit (void)
-{
-  RCC->CTLR |= (uint32_t)0x00000001;
-
-#ifdef CH32V30x_D8C
-  RCC->CFGR0 &= (uint32_t)0xF8FF0000;
-#else
-  RCC->CFGR0 &= (uint32_t)0xF0FF0000;
-#endif
-
-  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
-  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
-  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
-
-#ifdef CH32V30x_D8C
-  RCC->CTLR &= (uint32_t)0xEBFFFFFF;
-  RCC->INTR = 0x00FF0000;
-  RCC->CFGR2 = 0x00000000;
-#else
-  RCC->INTR = 0x009F0000;
-#endif
-  SetSysClock();
-}
-
-/*********************************************************************
- * @fn      SystemCoreClockUpdate
- *
- * @brief   Update SystemCoreClock variable according to Clock Register Values.
- *
- * @return  none
- */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
-
-  tmp = RCC->CFGR0 & RCC_SWS;
-
-  switch (tmp)
-  {
-    case 0x00:
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:
-      pllmull = RCC->CFGR0 & RCC_PLLMULL;
-      pllsource = RCC->CFGR0 & RCC_PLLSRC;
-      pllmull = ( pllmull >> 18) + 2;
-
-#ifdef CH32V30x_D8
-          if(pllmull == 17) pllmull = 18;
-#else
-          if(pllmull == 2) pllmull = 18;
-          if(pllmull == 15){
-              pllmull = 13;  /* *6.5 */
-              Pll_6_5 = 1;
-          }
-          if(pllmull == 16) pllmull = 15;
-          if(pllmull == 17) pllmull = 16;
-#endif
-
-      if (pllsource == 0x00)
-      {
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
-        if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
-        {
-          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
-      }
-
-      if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
-
-      break;
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-
-  tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
-  SystemCoreClock >>= tmp;
-}
-
-/*********************************************************************
- * @fn      SetSysClock
- *
- * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClock(void)
-{
-#ifdef SYSCLK_FREQ_HSE
-  SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-  SetSysClockTo24();
-#elif defined SYSCLK_FREQ_48MHz
-  SetSysClockTo48();
-#elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();
-#elif defined SYSCLK_FREQ_72MHz
-  SetSysClockTo72();
-#elif defined SYSCLK_FREQ_96MHz
-  SetSysClockTo96();
-#elif defined SYSCLK_FREQ_120MHz
-  SetSysClockTo120();
-#elif defined SYSCLK_FREQ_144MHz
-  SetSysClockTo144();
-
-#endif
-
- /* If none of the define above is enabled, the HSI is used as System clock
-  * source (default after reset)
-    */
-}
-
-
-#ifdef SYSCLK_FREQ_HSE
-
-/*********************************************************************
- * @fn      SetSysClockToHSE
- *
- * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockToHSE(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
-  RCC->CTLR |= ((uint32_t)RCC_HSEON);
-
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CTLR & RCC_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
-
-    /* Select HSE as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
-
-    /* Wait till HSE is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
-    {
-    }
-  }
-  else
-  {
-        /* If HSE fails to start-up, the application will have wrong clock
-     * configuration. User can add here some code to deal with this error
-         */
-  }
-}
-
-#elif defined SYSCLK_FREQ_24MHz
-
-/*********************************************************************
- * @fn      SetSysClockTo24
- *
- * @brief   Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo24(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
-  RCC->CTLR |= ((uint32_t)RCC_HSEON);
-
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CTLR & RCC_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
-
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
-
-#ifdef CH32V30x_D8
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3);
-#else
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3_EXTEN);
-#endif
-    /* Enable PLL */
-    RCC->CTLR |= RCC_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CTLR & RCC_PLLRDY) == 0)
-    {
-    }
-    /* Select PLL as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  {
-        /* If HSE fails to start-up, the application will have wrong clock
-     * configuration. User can add here some code to deal with this error
-         */
-  }
-}
-
-#elif defined SYSCLK_FREQ_48MHz
-
-/*********************************************************************
- * @fn      SetSysClockTo48
- *
- * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo48(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
-
-  RCC->CTLR |= ((uint32_t)RCC_HSEON);
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CTLR & RCC_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
-
-#ifdef CH32V30x_D8
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
-#else
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN);
-#endif
-
-    /* Enable PLL */
-    RCC->CTLR |= RCC_PLLON;
-    /* Wait till PLL is ready */
-    while((RCC->CTLR & RCC_PLLRDY) == 0)
-    {
-    }
-    /* Select PLL as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  {
-        /*
-         * If HSE fails to start-up, the application will have wrong clock
-     * configuration. User can add here some code to deal with this error
-         */
-  }
-}
-
-#elif defined SYSCLK_FREQ_56MHz
-
-/*********************************************************************
- * @fn      SetSysClockTo56
- *
- * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo56(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
-  RCC->CTLR |= ((uint32_t)RCC_HSEON);
-
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CTLR & RCC_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
-
-#ifdef CH32V30x_D8
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
-#else
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN);
-#endif
-
-    /* Enable PLL */
-    RCC->CTLR |= RCC_PLLON;
-    /* Wait till PLL is ready */
-    while((RCC->CTLR & RCC_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  {
-        /*
-         * If HSE fails to start-up, the application will have wrong clock
-     * configuration. User can add here some code to deal with this error
-         */
-  }
-}
-
-#elif defined SYSCLK_FREQ_72MHz
-
-/*********************************************************************
- * @fn      SetSysClockTo72
- *
- * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo72(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
-  RCC->CTLR |= ((uint32_t)RCC_HSEON);
-
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CTLR & RCC_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-    /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
-                                        RCC_PLLMULL));
-
-#ifdef CH32V30x_D8
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
-#else
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN);
-#endif
-
-    /* Enable PLL */
-    RCC->CTLR |= RCC_PLLON;
-    /* Wait till PLL is ready */
-    while((RCC->CTLR & RCC_PLLRDY) == 0)
-    {
-    }
-    /* Select PLL as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  {
-        /*
-         * If HSE fails to start-up, the application will have wrong clock
-     * configuration. User can add here some code to deal with this error
-         */
-  }
-}
-
-
-#elif defined SYSCLK_FREQ_96MHz
-
-/*********************************************************************
- * @fn      SetSysClockTo96
- *
- * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo96(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
-  RCC->CTLR |= ((uint32_t)RCC_HSEON);
-
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CTLR & RCC_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-    /*  PLL configuration: PLLCLK = HSE * 12 = 96 MHz */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
-                                        RCC_PLLMULL));
-
-#ifdef CH32V30x_D8
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
-#else
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN);
-#endif
-
-    /* Enable PLL */
-    RCC->CTLR |= RCC_PLLON;
-    /* Wait till PLL is ready */
-    while((RCC->CTLR & RCC_PLLRDY) == 0)
-    {
-    }
-    /* Select PLL as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  {
-        /*
-         * If HSE fails to start-up, the application will have wrong clock
-     * configuration. User can add here some code to deal with this error
-         */
-  }
-}
-
-
-#elif defined SYSCLK_FREQ_120MHz
-
-/*********************************************************************
- * @fn      SetSysClockTo120
- *
- * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo120(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
-  RCC->CTLR |= ((uint32_t)RCC_HSEON);
-
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CTLR & RCC_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-    /*  PLL configuration: PLLCLK = HSE * 15 = 120 MHz */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
-                                        RCC_PLLMULL));
-
-#ifdef CH32V30x_D8
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
-#else
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN);
-#endif
-
-    /* Enable PLL */
-    RCC->CTLR |= RCC_PLLON;
-    /* Wait till PLL is ready */
-    while((RCC->CTLR & RCC_PLLRDY) == 0)
-    {
-    }
-    /* Select PLL as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  {
-        /*
-         * If HSE fails to start-up, the application will have wrong clock
-     * configuration. User can add here some code to deal with this error
-         */
-  }
-}
-
-
-#elif defined SYSCLK_FREQ_144MHz
-
-/*********************************************************************
- * @fn      SetSysClockTo144
- *
- * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
- *
- * @return  none
- */
-static void SetSysClockTo144(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
-  RCC->CTLR |= ((uint32_t)RCC_HSEON);
-
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CTLR & RCC_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
-    /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
-    /* PCLK1 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-
-    /*  PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
-                                        RCC_PLLMULL));
-
-#ifdef CH32V30x_D8
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
-#else
-        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN);
-#endif
-
-    /* Enable PLL */
-    RCC->CTLR |= RCC_PLLON;
-    /* Wait till PLL is ready */
-    while((RCC->CTLR & RCC_PLLRDY) == 0)
-    {
-    }
-    /* Select PLL as system clock source */
-    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
-    {
-    }
-  }
-  else
-  {
-        /*
-         * If HSE fails to start-up, the application will have wrong clock
-     * configuration. User can add here some code to deal with this error
-         */
-  }
-}
-
-
-#endif
diff --git a/hw/bsp/ch32v307/system_ch32v30x.h b/hw/bsp/ch32v307/system_ch32v30x.h
deleted file mode 100644
index ad81058c7..000000000
--- a/hw/bsp/ch32v307/system_ch32v30x.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/********************************** (C) COPYRIGHT *******************************
-* File Name          : system_ch32v30x.h
-* Author             : WCH
-* Version            : V1.0.0
-* Date               : 2021/06/06
-* Description        : CH32V30x Device Peripheral Access Layer System Header File.
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* SPDX-License-Identifier: Apache-2.0
-*******************************************************************************/
-#ifndef __SYSTEM_CH32V30x_H
-#define __SYSTEM_CH32V30x_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-extern uint32_t SystemCoreClock;          /* System Clock Frequency (Core Clock) */
-
-/* System_Exported_Functions */
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__CH32V30x_SYSTEM_H */
diff --git a/hw/bsp/ch32v307/wch-riscv.cfg b/hw/bsp/ch32v307/wch-riscv.cfg
deleted file mode 100644
index aa35aa9c5..000000000
--- a/hw/bsp/ch32v307/wch-riscv.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-adapter driver wlinke
-adapter speed 6000
-transport select sdi
-
-wlink_set_address 0x00000000
-set _CHIPNAME wch_riscv
-sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure  -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1
-set _FLASHNAME $_CHIPNAME.flash
-
-flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
-
-echo "Ready for Remote Connections"
diff --git a/hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.cmake b/hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.cmake
new file mode 100644
index 000000000..9f5682042
--- /dev/null
+++ b/hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.cmake
@@ -0,0 +1,4 @@
+function(update_board TARGET)
+#  target_compile_definitions(${TARGET} PUBLIC
+#    )
+endfunction()
diff --git a/hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.h b/hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.h
new file mode 100644
index 000000000..491347034
--- /dev/null
+++ b/hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.h
@@ -0,0 +1,55 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/* metadata:
+   name: CH32V307V-R1-1v0
+   url: https://github.com/openwch/ch32v307/tree/main/SCHPCB/CH32V307V-R1-1v0
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED: need to wire pin LED1 to PC0 in the J3 header
+#define LED_PORT              GPIOC
+#define LED_PIN               GPIO_Pin_0
+#define LED_STATE_ON          0
+#define LED_CLOCK_EN()        RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE)
+
+// Button: need to wire pin KEY to PC1 in the J3 header
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_Pin_1
+#define BUTTON_STATE_ACTIVE   0
+#define BUTTON_CLOCK_EN()     do { } while(0) // same as LED clock, no need to do anything
+
+// TODO UART port
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.mk b/hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.mk
new file mode 100644
index 000000000..4e91d8938
--- /dev/null
+++ b/hw/bsp/ch32v30x/boards/ch32v307v_r1_1v0/board.mk
@@ -0,0 +1 @@
+LD_FILE = $(FAMILY_PATH)/ch32v307.ld
diff --git a/hw/bsp/ch32v30x/boards/nanoch32v305/board.cmake b/hw/bsp/ch32v30x/boards/nanoch32v305/board.cmake
new file mode 100644
index 000000000..9f5682042
--- /dev/null
+++ b/hw/bsp/ch32v30x/boards/nanoch32v305/board.cmake
@@ -0,0 +1,4 @@
+function(update_board TARGET)
+#  target_compile_definitions(${TARGET} PUBLIC
+#    )
+endfunction()
diff --git a/hw/bsp/ch32v30x/boards/nanoch32v305/board.h b/hw/bsp/ch32v30x/boards/nanoch32v305/board.h
new file mode 100644
index 000000000..62bbef94c
--- /dev/null
+++ b/hw/bsp/ch32v30x/boards/nanoch32v305/board.h
@@ -0,0 +1,48 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/* metadata:
+   name: nanoCH32V305
+   url: https://github.com/wuxx/nanoCH32V305
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define LED_PORT              GPIOA
+#define LED_PIN               GPIO_Pin_3
+#define LED_STATE_ON          0
+#define LED_CLOCK_EN()        RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE)
+
+// TODO UART port
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/ch32v30x/boards/nanoch32v305/board.mk b/hw/bsp/ch32v30x/boards/nanoch32v305/board.mk
new file mode 100644
index 000000000..4e91d8938
--- /dev/null
+++ b/hw/bsp/ch32v30x/boards/nanoch32v305/board.mk
@@ -0,0 +1 @@
+LD_FILE = $(FAMILY_PATH)/ch32v307.ld
diff --git a/hw/bsp/ch32v30x/ch32v307.ld b/hw/bsp/ch32v30x/ch32v307.ld
new file mode 100644
index 000000000..55bd10cd0
--- /dev/null
+++ b/hw/bsp/ch32v30x/ch32v307.ld
@@ -0,0 +1,167 @@
+ENTRY( _start )
+
+__stack_size = 4096;
+
+PROVIDE( _stack_size = __stack_size );
+
+
+MEMORY
+{
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 288K
+	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+
+SECTIONS
+{
+
+	.init :
+	{
+		_sinit = .;
+		. = ALIGN(4);
+		KEEP(*(SORT_NONE(.init)))
+		. = ALIGN(4);
+		_einit = .;
+	} >FLASH AT>FLASH
+
+  .vector :
+  {
+      *(.vector);
+	  . = ALIGN(64);
+  } >FLASH AT>FLASH
+
+	.text :
+	{
+		. = ALIGN(4);
+		*(.text)
+		*(.text.*)
+		*(.rodata)
+		*(.rodata*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.gnu.linkonce.t.*)
+		. = ALIGN(4);
+	} >FLASH AT>FLASH
+
+	.fini :
+	{
+		KEEP(*(SORT_NONE(.fini)))
+		. = ALIGN(4);
+	} >FLASH AT>FLASH
+
+	PROVIDE( _etext = . );
+	PROVIDE( _eitcm = . );
+
+	.preinit_array  :
+	{
+	  PROVIDE_HIDDEN (__preinit_array_start = .);
+	  KEEP (*(.preinit_array))
+	  PROVIDE_HIDDEN (__preinit_array_end = .);
+	} >FLASH AT>FLASH
+
+	.init_array     :
+	{
+	  PROVIDE_HIDDEN (__init_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+	  KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+	  PROVIDE_HIDDEN (__init_array_end = .);
+	} >FLASH AT>FLASH
+
+	.fini_array     :
+	{
+	  PROVIDE_HIDDEN (__fini_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+	  KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+	  PROVIDE_HIDDEN (__fini_array_end = .);
+	} >FLASH AT>FLASH
+
+	.ctors          :
+	{
+	  /* gcc uses crtbegin.o to find the start of
+	     the constructors, so we make sure it is
+	     first.  Because this is a wildcard, it
+	     doesn't matter if the user does not
+	     actually link against crtbegin.o; the
+	     linker won't look for a file to match a
+	     wildcard.  The wildcard also means that it
+	     doesn't matter which directory crtbegin.o
+	     is in.  */
+	  KEEP (*crtbegin.o(.ctors))
+	  KEEP (*crtbegin?.o(.ctors))
+	  /* We don't want to include the .ctor section from
+	     the crtend.o file until after the sorted ctors.
+	     The .ctor section from the crtend file contains the
+	     end of ctors marker and it must be last */
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+	  KEEP (*(SORT(.ctors.*)))
+	  KEEP (*(.ctors))
+	} >FLASH AT>FLASH
+
+	.dtors          :
+	{
+	  KEEP (*crtbegin.o(.dtors))
+	  KEEP (*crtbegin?.o(.dtors))
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+	  KEEP (*(SORT(.dtors.*)))
+	  KEEP (*(.dtors))
+	} >FLASH AT>FLASH
+
+	.dalign :
+	{
+		. = ALIGN(4);
+		PROVIDE(_data_vma = .);
+	} >RAM AT>FLASH
+
+	.dlalign :
+	{
+		. = ALIGN(4);
+		PROVIDE(_data_lma = .);
+	} >FLASH AT>FLASH
+
+	.data :
+	{
+    	*(.gnu.linkonce.r.*)
+    	*(.data .data.*)
+    	*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+    	PROVIDE( __global_pointer$ = . + 0x800 );
+    	*(.sdata .sdata.*)
+		*(.sdata2.*)
+    	*(.gnu.linkonce.s.*)
+    	. = ALIGN(8);
+    	*(.srodata.cst16)
+    	*(.srodata.cst8)
+    	*(.srodata.cst4)
+    	*(.srodata.cst2)
+    	*(.srodata .srodata.*)
+    	. = ALIGN(4);
+		PROVIDE( _edata = .);
+	} >RAM AT>FLASH
+
+	.bss :
+	{
+		. = ALIGN(4);
+		PROVIDE( _sbss = .);
+  	    *(.sbss*)
+        *(.gnu.linkonce.sb.*)
+		*(.bss*)
+     	*(.gnu.linkonce.b.*)
+		*(COMMON*)
+		. = ALIGN(4);
+		PROVIDE( _ebss = .);
+	} >RAM AT>FLASH
+
+	PROVIDE( _end = _ebss);
+	PROVIDE( end = . );
+
+    .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
+    {
+        PROVIDE( _heap_end = . );
+        . = ALIGN(4);
+        PROVIDE(_susrstack = . );
+        . = . + __stack_size;
+        PROVIDE( _eusrstack = .);
+        __freertos_irq_stack_top = .;
+    } >RAM
+
+}
diff --git a/hw/bsp/ch32v30x/ch32v30x_conf.h b/hw/bsp/ch32v30x/ch32v30x_conf.h
new file mode 100644
index 000000000..0b86ad390
--- /dev/null
+++ b/hw/bsp/ch32v30x/ch32v30x_conf.h
@@ -0,0 +1,38 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_conf.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : Library configuration file.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CH32V30x_CONF_H
+#define __CH32V30x_CONF_H
+
+#include "ch32v30x_adc.h"
+#include "ch32v30x_bkp.h"
+#include "ch32v30x_can.h"
+#include "ch32v30x_crc.h"
+#include "ch32v30x_dac.h"
+#include "ch32v30x_dbgmcu.h"
+#include "ch32v30x_dma.h"
+#include "ch32v30x_exti.h"
+#include "ch32v30x_flash.h"
+#include "ch32v30x_fsmc.h"
+#include "ch32v30x_gpio.h"
+#include "ch32v30x_i2c.h"
+#include "ch32v30x_iwdg.h"
+#include "ch32v30x_pwr.h"
+#include "ch32v30x_rcc.h"
+#include "ch32v30x_rtc.h"
+#include "ch32v30x_sdio.h"
+#include "ch32v30x_spi.h"
+#include "ch32v30x_tim.h"
+#include "ch32v30x_usart.h"
+#include "ch32v30x_wwdg.h"
+#include "ch32v30x_it.h"
+#include "ch32v30x_misc.h"
+
+
+#endif /* __CH32V30x_CONF_H */
diff --git a/hw/bsp/ch32v30x/ch32v30x_it.c b/hw/bsp/ch32v30x/ch32v30x_it.c
new file mode 100644
index 000000000..c329c5613
--- /dev/null
+++ b/hw/bsp/ch32v30x/ch32v30x_it.c
@@ -0,0 +1,47 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_it.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : Main Interrupt Service Routines.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_it.h"
+
+void NMI_Handler(void) __attribute__((naked));
+void HardFault_Handler(void) __attribute__((naked));
+
+/*********************************************************************
+ * @fn      NMI_Handler
+ *
+ * @brief   This function handles NMI exception.
+ *
+ * @return  none
+ */
+void NMI_Handle(void){
+      __asm volatile ("call NMI_Handler_impl; mret");
+}
+
+__attribute__((used)) void NMI_Handler_impl(void)
+{
+
+}
+
+/*********************************************************************
+ * @fn      HardFault_Handler
+ *
+ * @brief   This function handles Hard Fault exception.
+ *
+ * @return  none
+ */
+void HardFault_Handler(void){
+      __asm volatile ("call HardFault_Handler_impl; mret");
+}
+
+__attribute__((used)) void HardFault_Handler_impl(void)
+{
+  while (1)
+  {
+  }
+}
diff --git a/hw/bsp/ch32v30x/ch32v30x_it.h b/hw/bsp/ch32v30x/ch32v30x_it.h
new file mode 100644
index 000000000..f3977a8be
--- /dev/null
+++ b/hw/bsp/ch32v30x/ch32v30x_it.h
@@ -0,0 +1,16 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_it.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains the headers of the interrupt handlers.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CH32V30x_IT_H
+#define __CH32V30x_IT_H
+
+// #include "debug.h"
+
+
+#endif /* __CH32V30x_IT_H */
diff --git a/hw/bsp/ch32v30x/debug_uart.c b/hw/bsp/ch32v30x/debug_uart.c
new file mode 100644
index 000000000..2fd3a9d64
--- /dev/null
+++ b/hw/bsp/ch32v30x/debug_uart.c
@@ -0,0 +1,119 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Greg Davill
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "debug_uart.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
+#include <ch32v30x.h>
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#define UART_RINGBUFFER_SIZE_TX 128
+#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1)
+
+static char tx_buf[UART_RINGBUFFER_SIZE_TX];
+static unsigned int tx_produce;
+static volatile unsigned int tx_consume;
+
+void USART1_IRQHandler(void) __attribute__((naked));
+void USART1_IRQHandler(void) {
+      __asm volatile ("call USART1_IRQHandler_impl; mret");
+}
+
+__attribute__((used)) void USART1_IRQHandler_impl(void)
+{
+	if(USART_GetITStatus(USART1, USART_IT_TC) != RESET)
+    {
+        USART_ClearITPendingBit(USART1, USART_IT_TC);
+
+		if(tx_consume != tx_produce) {
+			USART_SendData(USART1, tx_buf[tx_consume]);
+			tx_consume = (tx_consume + 1) & UART_RINGBUFFER_MASK_TX;
+		}
+    }
+
+}
+
+void uart_write(char c)
+{
+	unsigned int tx_produce_next = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX;
+
+    NVIC_DisableIRQ(USART1_IRQn);
+    if((tx_consume != tx_produce) || (USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET)) {
+		tx_buf[tx_produce] = c;
+		tx_produce = tx_produce_next;
+	} else {
+		USART_SendData(USART1, c);
+	}
+    NVIC_EnableIRQ(USART1_IRQn);
+}
+
+
+void uart_sync(void)
+{
+	while(tx_consume != tx_produce);
+}
+
+
+void usart_printf_init(uint32_t baudrate)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  USART_InitTypeDef USART_InitStructure;
+
+  tx_produce = 0;
+  tx_consume = 0;
+
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+  USART_InitStructure.USART_BaudRate = baudrate;
+  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+  USART_InitStructure.USART_StopBits = USART_StopBits_1;
+  USART_InitStructure.USART_Parity = USART_Parity_No;
+  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+  USART_InitStructure.USART_Mode = USART_Mode_Tx;
+
+  USART_Init(USART1, &USART_InitStructure);
+  USART_ITConfig(USART1, USART_IT_TC, ENABLE);
+  USART_Cmd(USART1, ENABLE);
+
+  NVIC_InitTypeDef NVIC_InitStructure = { 0 };
+  NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
+}
diff --git a/hw/bsp/ch32v30x/debug_uart.h b/hw/bsp/ch32v30x/debug_uart.h
new file mode 100644
index 000000000..a7e070585
--- /dev/null
+++ b/hw/bsp/ch32v30x/debug_uart.h
@@ -0,0 +1,31 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Greg Davill
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include <stdint.h>
+
+void uart_write(char c);
+void uart_sync(void);
+void usart_printf_init(uint32_t baudrate);
diff --git a/hw/bsp/ch32v30x/family.c b/hw/bsp/ch32v30x/family.c
new file mode 100644
index 000000000..bd01f4f46
--- /dev/null
+++ b/hw/bsp/ch32v30x/family.c
@@ -0,0 +1,200 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Greg Davill
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   manufacturer: WCH
+*/
+
+#include "stdio.h"
+
+// https://github.com/openwch/ch32v307/pull/90
+// https://github.com/openwch/ch32v20x/pull/12
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#endif
+
+#include "debug_uart.h"
+#include "ch32v30x.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+
+// TODO maybe having FS as port0, HS as port1
+
+__attribute__((interrupt)) void USBHS_IRQHandler(void) {
+  #if CFG_TUD_WCH_USBIP_USBHS
+  tud_int_handler(0);
+  #endif
+}
+
+__attribute__((interrupt)) void OTG_FS_IRQHandler(void) {
+  #if CFG_TUD_WCH_USBIP_USBFS
+  tud_int_handler(0);
+  #endif
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+uint32_t SysTick_Config(uint32_t ticks) {
+  NVIC_EnableIRQ(SysTicK_IRQn);
+  SysTick->CTLR = 0;
+  SysTick->SR = 0;
+  SysTick->CNT = 0;
+  SysTick->CMP = ticks - 1;
+  SysTick->CTLR = 0xF;
+  return 0;
+}
+
+void board_init(void) {
+
+  /* Disable interrupts during init */
+  __disable_irq();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  SysTick_Config(SystemCoreClock / 1000);
+#endif
+
+  usart_printf_init(CFG_BOARD_UART_BAUDRATE);
+
+#ifdef CH32V30x_D8C
+  // v305/v307: Highspeed USB
+  RCC_USBCLK48MConfig(RCC_USBCLK48MCLKSource_USBPHY);
+  RCC_USBHSPLLCLKConfig(RCC_HSBHSPLLCLKSource_HSE);
+  RCC_USBHSConfig(RCC_USBPLL_Div2);
+  RCC_USBHSPLLCKREFCLKConfig(RCC_USBHSPLLCKREFCLK_4M);
+  RCC_USBHSPHYPLLALIVEcmd(ENABLE);
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBHS, ENABLE);
+#endif
+
+  // Fullspeed USB
+  uint8_t otg_div;
+  switch (SystemCoreClock) {
+    case 48000000:  otg_div = RCC_OTGFSCLKSource_PLLCLK_Div1; break;
+    case 96000000:  otg_div = RCC_OTGFSCLKSource_PLLCLK_Div2; break;
+    case 144000000: otg_div = RCC_OTGFSCLKSource_PLLCLK_Div3; break;
+    default: TU_ASSERT(0,); break;
+  }
+  RCC_OTGFSCLKConfig(otg_div);
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_OTG_FS, ENABLE);
+
+  GPIO_InitTypeDef GPIO_InitStructure = {0};
+
+  // LED
+  LED_CLOCK_EN();
+  GPIO_InitStructure.GPIO_Pin = LED_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(LED_PORT, &GPIO_InitStructure);
+
+  // Button
+#ifdef BUTTON_PORT
+  BUTTON_CLOCK_EN();
+  GPIO_InitStructure.GPIO_Pin = BUTTON_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(BUTTON_PORT, &GPIO_InitStructure);
+#endif
+  /* Enable interrupts globally */
+  __enable_irq();
+
+  board_delay(2);
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+__attribute__((interrupt)) void SysTick_Handler(void) {
+  SysTick->SR = 0;
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+
+#endif
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+  GPIO_WriteBit(LED_PORT, LED_PIN, state);
+}
+
+uint32_t board_button_read(void) {
+#ifdef BUTTON_PORT
+  return BUTTON_STATE_ACTIVE == GPIO_ReadInputDataBit(BUTTON_PORT, BUTTON_PIN);
+#else
+  return false;
+#endif
+}
+
+int board_uart_read(uint8_t* buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const* buf, int len) {
+  int txsize = len;
+  const char* bufc = (const char*) buf;
+  while (txsize--) {
+    uart_write(*bufc++);
+  }
+  uart_sync();
+  return len;
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief  Reports the name of the source file and the source line number
+ *         where the assert_param error has occurred.
+ * @param  file: pointer to the source file name
+ * @param  line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(char* file, uint32_t line) {
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line
+     number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line)
+   */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/hw/bsp/ch32v30x/family.cmake b/hw/bsp/ch32v30x/family.cmake
new file mode 100644
index 000000000..446e850c5
--- /dev/null
+++ b/hw/bsp/ch32v30x/family.cmake
@@ -0,0 +1,128 @@
+include_guard()
+
+set(CH32_FAMILY ch32v30x)
+set(SDK_DIR ${TOP}/hw/mcu/wch/ch32v307)
+set(SDK_SRC_DIR ${SDK_DIR}/EVT/EXAM/SRC)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_CPU rv32imac-ilp32 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS CH32V307 CACHE INTERNAL "")
+set(OPENOCD_OPTION "-f ${CMAKE_CURRENT_LIST_DIR}/wch-riscv.cfg")
+
+# default to highspeed, used to select USBFS / USBHS driver
+if (NOT DEFINED SPEED)
+  set(SPEED high)
+endif()
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/ch32v307.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_GNU)
+    set(STARTUP_FILE_GNU ${SDK_SRC_DIR}/Startup/startup_${CH32_FAMILY}_D8C.S)
+  endif ()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_SRC_DIR}/Core/core_riscv.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_gpio.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_misc.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_rcc.c
+    ${SDK_SRC_DIR}/Peripheral/src/${CH32_FAMILY}_usart.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${CH32_FAMILY}_it.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/system_${CH32_FAMILY}.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_SRC_DIR}/Core
+    ${SDK_SRC_DIR}/Peripheral/inc
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    )
+  if (SPEED STREQUAL high)
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      CFG_TUD_WCH_USBIP_USBHS=1
+#      BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+      )
+  else ()
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      CFG_TUD_WCH_USBIP_USBFS=1
+      )
+  endif ()
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      -msmall-data-limit=8
+      -mno-save-restore
+      -fmessage-length=0
+      -fsigned-char
+      )
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    message(FATAL_ERROR "Clang is not supported for MSP432E4")
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/debug_uart.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_CH32V307)
+  target_sources(${TARGET} PUBLIC
+    ${TOP}/src/portable/wch/dcd_ch32_usbhs.c
+    ${TOP}/src/portable/wch/dcd_ch32_usbfs.c
+    )
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD})
+
+
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_openocd_wch(${TARGET})
+endfunction()
diff --git a/hw/bsp/ch32v30x/family.mk b/hw/bsp/ch32v30x/family.mk
new file mode 100644
index 000000000..bf2732106
--- /dev/null
+++ b/hw/bsp/ch32v30x/family.mk
@@ -0,0 +1,64 @@
+# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable
+#CROSS_COMPILE ?= riscv32-unknown-elf-
+
+# Toolchain from https://nucleisys.com/download.php
+#CROSS_COMPILE ?= riscv-nuclei-elf-
+
+# Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
+CROSS_COMPILE ?= riscv-none-elf-
+
+CH32_FAMILY = ch32v30x
+SDK_DIR = hw/mcu/wch/ch32v307
+SDK_SRC_DIR = $(SDK_DIR)/EVT/EXAM/SRC
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= rv32imac-ilp32
+
+# default to use high speed port, unless specified in board.mk or command line
+SPEED ?= high
+
+CFLAGS += \
+	-flto \
+	-msmall-data-limit=8 \
+	-mno-save-restore \
+	-fmessage-length=0 \
+	-fsigned-char \
+	-DCFG_TUSB_MCU=OPT_MCU_CH32V307 \
+
+# https://github.com/openwch/ch32v307/pull/90
+CFLAGS += -Wno-error=strict-prototypes
+
+ifeq ($(SPEED),high)
+  $(info "Using USBHS driver for HighSpeed mode")
+  CFLAGS += -DCFG_TUD_WCH_USBIP_USBHS=1
+else
+  $(info "Using USBFS driver for FullSpeed mode")
+  CFLAGS += -DCFG_TUD_WCH_USBIP_USBFS=1
+endif
+
+LDFLAGS_GCC += \
+	-nostdlib -nostartfiles \
+  --specs=nosys.specs --specs=nano.specs \
+
+SRC_C += \
+	src/portable/wch/dcd_ch32_usbhs.c \
+	src/portable/wch/dcd_ch32_usbfs.c \
+	$(SDK_SRC_DIR)/Core/core_riscv.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_gpio.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_misc.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_rcc.c \
+	$(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_usart.c
+
+SRC_S += \
+	$(SDK_SRC_DIR)/Startup/startup_${CH32_FAMILY}_D8C.S
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(SDK_SRC_DIR)/Core \
+	$(TOP)/$(SDK_SRC_DIR)/Peripheral/inc
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
+
+OPENOCD_WCH_OPTION=-f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg
+flash: flash-openocd-wch
diff --git a/hw/bsp/ch32v30x/system_ch32v30x.c b/hw/bsp/ch32v30x/system_ch32v30x.c
new file mode 100644
index 000000000..23f783df4
--- /dev/null
+++ b/hw/bsp/ch32v30x/system_ch32v30x.c
@@ -0,0 +1,776 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : system_ch32v30x.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : CH32V30x Device Peripheral Access Layer System Source File.
+*                      For HSE = 8Mhz
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*********************************************************************************/
+#include "ch32v30x.h"
+
+/*
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source.
+*/
+// #define SYSCLK_FREQ_HSE    HSE_VALUE
+/* #define SYSCLK_FREQ_24MHz  24000000  */
+//#define SYSCLK_FREQ_48MHz  48000000
+/* #define SYSCLK_FREQ_56MHz  56000000  */
+//#define SYSCLK_FREQ_72MHz  72000000
+//#define SYSCLK_FREQ_96MHz  96000000
+//#define SYSCLK_FREQ_120MHz  120000000
+#define SYSCLK_FREQ_144MHz  144000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;          /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /* System Clock Frequency (Core Clock) */
+
+#elif defined SYSCLK_FREQ_96MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz;        /* System Clock Frequency (Core Clock) */
+
+#else /* HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;                /* System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+
+/* system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+
+#elif defined SYSCLK_FREQ_96MHz
+  static void SetSysClockTo96(void);
+#elif defined SYSCLK_FREQ_120MHz
+  static void SetSysClockTo120(void);
+#elif defined SYSCLK_FREQ_144MHz
+  static void SetSysClockTo144(void);
+
+#endif
+
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit (void)
+{
+  RCC->CTLR |= (uint32_t)0x00000001;
+
+#ifdef CH32V30x_D8C
+  RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR0 &= (uint32_t)0xF0FF0000;
+#endif
+
+  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+
+#ifdef CH32V30x_D8C
+  RCC->CTLR &= (uint32_t)0xEBFFFFFF;
+  RCC->INTR = 0x00FF0000;
+  RCC->CFGR2 = 0x00000000;
+#else
+  RCC->INTR = 0x009F0000;
+#endif
+  SetSysClock();
+}
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
+
+  tmp = RCC->CFGR0 & RCC_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:
+      pllmull = RCC->CFGR0 & RCC_PLLMULL;
+      pllsource = RCC->CFGR0 & RCC_PLLSRC;
+      pllmull = ( pllmull >> 18) + 2;
+
+#ifdef CH32V30x_D8
+          if(pllmull == 17) pllmull = 18;
+#else
+          if(pllmull == 2) pllmull = 18;
+          if(pllmull == 15){
+              pllmull = 13;  /* *6.5 */
+              Pll_6_5 = 1;
+          }
+          if(pllmull == 16) pllmull = 15;
+          if(pllmull == 17) pllmull = 16;
+#endif
+
+      if (pllsource == 0x00)
+      {
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {
+        if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+        {
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+      }
+
+      if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
+
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+
+  tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+  SystemCoreClock >>= tmp;
+}
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#elif defined SYSCLK_FREQ_96MHz
+  SetSysClockTo96();
+#elif defined SYSCLK_FREQ_120MHz
+  SetSysClockTo120();
+#elif defined SYSCLK_FREQ_144MHz
+  SetSysClockTo144();
+
+#endif
+
+ /* If none of the define above is enabled, the HSI is used as System clock
+  * source (default after reset)
+    */
+}
+
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+
+    /* Select HSE as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  {
+        /* If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+#elif defined SYSCLK_FREQ_24MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo24
+ *
+ * @brief   Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3_EXTEN);
+#endif
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /* If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+#elif defined SYSCLK_FREQ_48MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo48
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo56
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo72
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo96
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 12 = 96 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo120
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 15 = 120 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_144MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo144
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#endif
diff --git a/hw/bsp/ch32v30x/system_ch32v30x.h b/hw/bsp/ch32v30x/system_ch32v30x.h
new file mode 100644
index 000000000..ad81058c7
--- /dev/null
+++ b/hw/bsp/ch32v30x/system_ch32v30x.h
@@ -0,0 +1,27 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : system_ch32v30x.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : CH32V30x Device Peripheral Access Layer System Header File.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __SYSTEM_CH32V30x_H
+#define __SYSTEM_CH32V30x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;          /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V30x_SYSTEM_H */
diff --git a/hw/bsp/ch32v30x/wch-riscv.cfg b/hw/bsp/ch32v30x/wch-riscv.cfg
new file mode 100644
index 000000000..aa35aa9c5
--- /dev/null
+++ b/hw/bsp/ch32v30x/wch-riscv.cfg
@@ -0,0 +1,17 @@
+adapter driver wlinke
+adapter speed 6000
+transport select sdi
+
+wlink_set_address 0x00000000
+set _CHIPNAME wch_riscv
+sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure  -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+
+flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
+
+echo "Ready for Remote Connections"
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 4a980b255..539ab52a9 100755
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -204,7 +204,7 @@ deps_optional = {
                             'ch32v20x'],
     'hw/mcu/wch/ch32v307': ['https://github.com/openwch/ch32v307.git',
                             '184f21b852cb95eed58e86e901837bc9fff68775',
-                            'ch32v307'],
+                            'ch32v30x'],
     'hw/mcu/wch/ch32f20x': ['https://github.com/openwch/ch32f20x.git',
                             '77c4095087e5ed2c548ec9058e655d0b8757663b',
                             'ch32f20x'],
-- 
cgit v1.3.1


From 9290788a2376277740742cc07873143a034193cf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 1 Aug 2025 11:26:04 +0700
Subject: add at32 to README.rst, rename at32 board to lower case, correct name
 to match mcu, add meta data

---
 .circleci/config.yml                               |   2 +-
 .idea/cmake.xml                                    |   3 +
 README.rst                                         |   6 +
 docs/reference/boards.rst                          |  17 +-
 docs/reference/dependencies.rst                    |  10 +-
 examples/device/net_lwip_webserver/skip.txt        |   2 +-
 .../boards/AT_START_F402_405/board.cmake           |   8 -
 .../at32f402_405/boards/AT_START_F402_405/board.h  | 169 -------------------
 .../at32f402_405/boards/AT_START_F402_405/board.mk |   7 -
 .../at32f402_405/boards/at_start_f405/board.cmake  |   8 +
 hw/bsp/at32f402_405/boards/at_start_f405/board.h   | 174 +++++++++++++++++++
 hw/bsp/at32f402_405/boards/at_start_f405/board.mk  |   7 +
 hw/bsp/at32f402_405/family.c                       |   4 +
 .../boards/AT_START_F403A_407/board.cmake          |   8 -
 .../boards/AT_START_F403A_407/board.h              |  61 -------
 .../boards/AT_START_F403A_407/board.mk             |   7 -
 .../boards/at_start_f403a/board.cmake              |   8 +
 hw/bsp/at32f403a_407/boards/at_start_f403a/board.h |  71 ++++++++
 .../at32f403a_407/boards/at_start_f403a/board.mk   |   7 +
 hw/bsp/at32f403a_407/family.c                      |   4 +
 hw/bsp/at32f413/boards/AT_START_F413/board.cmake   |   8 -
 hw/bsp/at32f413/boards/AT_START_F413/board.h       |  62 -------
 hw/bsp/at32f413/boards/AT_START_F413/board.mk      |   8 -
 hw/bsp/at32f413/boards/at_start_f413/board.cmake   |   8 +
 hw/bsp/at32f413/boards/at_start_f413/board.h       |  67 ++++++++
 hw/bsp/at32f413/boards/at_start_f413/board.mk      |   8 +
 hw/bsp/at32f413/family.c                           |   4 +
 hw/bsp/at32f415/boards/AT_START_F415/board.cmake   |  11 --
 hw/bsp/at32f415/boards/AT_START_F415/board.h       |  80 ---------
 hw/bsp/at32f415/boards/AT_START_F415/board.mk      |   8 -
 hw/bsp/at32f415/boards/at_start_f415/board.cmake   |  11 ++
 hw/bsp/at32f415/boards/at_start_f415/board.h       |  85 ++++++++++
 hw/bsp/at32f415/boards/at_start_f415/board.mk      |   8 +
 hw/bsp/at32f415/family.c                           |   4 +
 hw/bsp/at32f423/boards/AT_START_F423/board.cmake   |   8 -
 hw/bsp/at32f423/boards/AT_START_F423/board.h       |  91 ----------
 hw/bsp/at32f423/boards/AT_START_F423/board.mk      |   7 -
 hw/bsp/at32f423/boards/at_start_f423/board.cmake   |   8 +
 hw/bsp/at32f423/boards/at_start_f423/board.h       |  96 +++++++++++
 hw/bsp/at32f423/boards/at_start_f423/board.mk      |   7 +
 hw/bsp/at32f423/family.c                           |   4 +
 hw/bsp/at32f425/boards/AT_START_F425/board.cmake   |  12 --
 hw/bsp/at32f425/boards/AT_START_F425/board.h       |  90 ----------
 hw/bsp/at32f425/boards/AT_START_F425/board.mk      |   9 -
 hw/bsp/at32f425/boards/at_start_f425/board.cmake   |  12 ++
 hw/bsp/at32f425/boards/at_start_f425/board.h       |  95 +++++++++++
 hw/bsp/at32f425/boards/at_start_f425/board.mk      |   9 +
 hw/bsp/at32f425/family.c                           |   4 +
 .../boards/AT_START_F435_437/board.cmake           |   8 -
 .../at32f435_437/boards/AT_START_F435_437/board.h  | 182 --------------------
 .../at32f435_437/boards/AT_START_F435_437/board.mk |   7 -
 .../at32f435_437/boards/at_start_f437/board.cmake  |   8 +
 hw/bsp/at32f435_437/boards/at_start_f437/board.h   | 187 +++++++++++++++++++++
 hw/bsp/at32f435_437/boards/at_start_f437/board.mk  |   7 +
 hw/bsp/at32f435_437/family.c                       |   4 +
 55 files changed, 955 insertions(+), 855 deletions(-)
 delete mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/board.cmake
 delete mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h
 delete mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk
 create mode 100644 hw/bsp/at32f402_405/boards/at_start_f405/board.cmake
 create mode 100644 hw/bsp/at32f402_405/boards/at_start_f405/board.h
 create mode 100644 hw/bsp/at32f402_405/boards/at_start_f405/board.mk
 delete mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake
 delete mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.h
 delete mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk
 create mode 100644 hw/bsp/at32f403a_407/boards/at_start_f403a/board.cmake
 create mode 100644 hw/bsp/at32f403a_407/boards/at_start_f403a/board.h
 create mode 100644 hw/bsp/at32f403a_407/boards/at_start_f403a/board.mk
 delete mode 100644 hw/bsp/at32f413/boards/AT_START_F413/board.cmake
 delete mode 100644 hw/bsp/at32f413/boards/AT_START_F413/board.h
 delete mode 100644 hw/bsp/at32f413/boards/AT_START_F413/board.mk
 create mode 100644 hw/bsp/at32f413/boards/at_start_f413/board.cmake
 create mode 100644 hw/bsp/at32f413/boards/at_start_f413/board.h
 create mode 100644 hw/bsp/at32f413/boards/at_start_f413/board.mk
 delete mode 100644 hw/bsp/at32f415/boards/AT_START_F415/board.cmake
 delete mode 100644 hw/bsp/at32f415/boards/AT_START_F415/board.h
 delete mode 100644 hw/bsp/at32f415/boards/AT_START_F415/board.mk
 create mode 100644 hw/bsp/at32f415/boards/at_start_f415/board.cmake
 create mode 100644 hw/bsp/at32f415/boards/at_start_f415/board.h
 create mode 100644 hw/bsp/at32f415/boards/at_start_f415/board.mk
 delete mode 100644 hw/bsp/at32f423/boards/AT_START_F423/board.cmake
 delete mode 100644 hw/bsp/at32f423/boards/AT_START_F423/board.h
 delete mode 100644 hw/bsp/at32f423/boards/AT_START_F423/board.mk
 create mode 100644 hw/bsp/at32f423/boards/at_start_f423/board.cmake
 create mode 100644 hw/bsp/at32f423/boards/at_start_f423/board.h
 create mode 100644 hw/bsp/at32f423/boards/at_start_f423/board.mk
 delete mode 100644 hw/bsp/at32f425/boards/AT_START_F425/board.cmake
 delete mode 100644 hw/bsp/at32f425/boards/AT_START_F425/board.h
 delete mode 100644 hw/bsp/at32f425/boards/AT_START_F425/board.mk
 create mode 100644 hw/bsp/at32f425/boards/at_start_f425/board.cmake
 create mode 100644 hw/bsp/at32f425/boards/at_start_f425/board.h
 create mode 100644 hw/bsp/at32f425/boards/at_start_f425/board.mk
 delete mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/board.cmake
 delete mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/board.h
 delete mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk
 create mode 100644 hw/bsp/at32f435_437/boards/at_start_f437/board.cmake
 create mode 100644 hw/bsp/at32f435_437/boards/at_start_f437/board.h
 create mode 100644 hw/bsp/at32f435_437/boards/at_start_f437/board.mk

(limited to 'docs/reference')

diff --git a/.circleci/config.yml b/.circleci/config.yml
index c2f6c4356..3342cbc65 100644
--- a/.circleci/config.yml
+++ b/.circleci/config.yml
@@ -32,7 +32,7 @@ jobs:
               BUILDSYSTEM_TOOLCHAIN+=("cmake arm-iar")
             fi
 
-            RESOURCE_LARGE='["nrf", "imxrt", "stm32f4", "stm32h7"]'
+            RESOURCE_LARGE='["nrf", "imxrt", "stm32f4", "stm32h7 stm32h7rs"]'
 
             gen_build_entry() {
               local build_system="$1"
diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 7e0a9be92..f5e5d1f0e 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -163,12 +163,15 @@
       <configuration PROFILE_NAME="ch32v203c_r0_1v0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ch32v203c_r0_1v0 -DLOG=0" />
       <configuration PROFILE_NAME="ch32v203c_r0_1v0 USBFS" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ch32v203c_r0_1v0 -DPORT=1" />
       <configuration PROFILE_NAME="ch32v203g_r0_1v0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ch32v203g_r0_1v0" />
+      <configuration PROFILE_NAME="nanoch32v305" ENABLED="false" GENERATION_OPTIONS="-DBOARD=nanoch32v305 -DLOG=1" />
       <configuration PROFILE_NAME="ch32v307v_r1_1v0" ENABLED="false" GENERATION_OPTIONS="-DBOARD=ch32v307v_r1_1v0 -DLOG=1" />
       <configuration PROFILE_NAME="ch32v307v_r1_1v0 USBFS" ENABLED="false" GENERATION_OPTIONS="-DBOARD=ch32v307v_r1_1v0 -DSPEED=full" />
       <configuration PROFILE_NAME="da14695_dk_usb" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=da14695_dk_usb" />
       <configuration PROFILE_NAME="max32650fthr" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=max32650fthr -DLOG=0 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="max32666fthr" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=max32666fthr -DLOG=0 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="max32690evkit" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=max32690evkit -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="at_start_f403a" ENABLED="false" GENERATION_OPTIONS="-DBOARD=at_start_f403a -DLOG=1" />
+      <configuration PROFILE_NAME="at_start_f423" ENABLED="false" GENERATION_OPTIONS="-DBOARD=at_start_f423 -DLOG=1" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/README.rst b/README.rst
index 2a756a97f..d6830e707 100644
--- a/README.rst
+++ b/README.rst
@@ -109,6 +109,12 @@ Supported CPUs
 |              | MAX32 650, 666, 690,        | ✔      |      | ✔         | musb                   | 1-dir ep          |
 |              | MAX78002                    |        |      |           |                        |                   |
 +--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
+| Artery AT32  | F403a_407, F413             | ✔      |      |           | fsdev                  |                   |
+|              +-----------------------------+--------+------+-----------+------------------------+-------------------+
+|              | F415, F435_437, F423, F425  | ✔      | ✔    |           | dwc2                   |                   |
+|              +-----------------------------+--------+------+-----------+------------------------+-------------------+
+|              | F402_F405                   | ✔      | ✔    | ✔         | dwc2                   | F405 is HS        |
++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
 | Brigetek     | FT90x                       | ✔      |      | ✔         | ft9xx                  | 1-dir ep          |
 +--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+
 | Broadcom     | BCM2711, BCM2837            | ✔      |      | ✔         | dwc2                   |                   |
diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst
index 824b1214b..289ec543a 100644
--- a/docs/reference/boards.rst
+++ b/docs/reference/boards.rst
@@ -27,6 +27,21 @@ max32690evkit  MAX32690 EVKIT    maxim     https://www.analog.com/en/resources/e
 max78002evkit  MAX78002 EVKIT    maxim     https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html
 =============  ================  ========  =================================================================================================================  ======
 
+Artery
+-----
+
+==============  ==============  =============  ==================================================  ======
+Board           Name            Family         URL                                                 Note
+==============  ==============  =============  ==================================================  ======
+at_start_f405   AT-START-F405   at32f402_405   https://www.arterychip.com/en/product/AT32F405.jsp
+at_start_f403a  AT-START-F403a  at32f403a_407  https://www.arterychip.com/en/product/AT32F403.jsp
+at_start_f413   AT-START-F413   at32f413       https://www.arterychip.com/en/product/AT32F413.jsp
+at_start_f415   AT-START-F415   at32f415       https://www.arterychip.com/en/product/AT32F415.jsp
+at_start_f423   AT-START-F423   at32f423       https://www.arterychip.com/en/product/AT32F423.jsp
+at_start_f425   AT-START-F425   at32f425       https://www.arterychip.com/en/product/AT32F425.jsp
+at_start_f437   AT-START-F437   at32f435_437   https://www.arterychip.com/en/product/AT32F437.jsp
+==============  ==============  =============  ==================================================  ======
+
 Bridgetek
 ---------
 
@@ -326,6 +341,6 @@ ch32v103r_r1_1v0  CH32V103R-R1-1v1  ch32v10x  https://github.com/openwch/ch32v10
 ch32v203c_r0_1v0  CH32V203C-R0-1v0  ch32v20x  https://github.com/openwch/ch32v20x/tree/main/SCHPCB/CH32V203C-R0
 ch32v203g_r0_1v0  CH32V203G-R0-1v0  ch32v20x  https://github.com/openwch/ch32v20x/tree/main/SCHPCB/CH32V203C-R0
 nanoch32v203      nanoCH32V203      ch32v20x  https://github.com/wuxx/nanoCH32V203
-nanoch32v305      nanoCH32V305      ch32v30x  https://github.com/wuxx/nanoCH32V305
 ch32v307v_r1_1v0  CH32V307V-R1-1v0  ch32v30x  https://github.com/openwch/ch32v307/tree/main/SCHPCB/CH32V307V-R1-1v0
+nanoch32v305      nanoCH32V305      ch32v30x  https://github.com/wuxx/nanoCH32V305
 ================  ================  ========  =====================================================================  ======
diff --git a/docs/reference/dependencies.rst b/docs/reference/dependencies.rst
index 5104c6456..d75139aae 100644
--- a/docs/reference/dependencies.rst
+++ b/docs/reference/dependencies.rst
@@ -9,6 +9,13 @@ Local Path                                Repo
 ========================================  ================================================================  ========================================  ======================================================================================================================================================================================================================================================================================================================================================
 hw/mcu/allwinner                          https://github.com/hathach/allwinner_driver.git                   8e5e89e8e132c0fd90e72d5422e5d3d68232b756  fc100s
 hw/mcu/analog/msdk                        https://github.com/analogdevicesinc/msdk.git                      b20b398d3e5e2007594e54a74ba3d2a2e50ddd75  maxim
+hw/mcu/artery/at32f402_405                https://github.com/ArteryTek/AT32F402_405_Firmware_Library.git    4424515c2663e82438654e0947695295df2abdfe  at32f402_405
+hw/mcu/artery/at32f403a_407               https://github.com/ArteryTek/AT32F403A_407_Firmware_Library.git   f2cb360c3d28fada76b374308b8c4c61d37a090b  at32f403a_407
+hw/mcu/artery/at32f413                    https://github.com/ArteryTek/AT32F413_Firmware_Library.git        f6fe62dfec9fd40c5b63d92fc5ef2c2b5e77a450  at32f413
+hw/mcu/artery/at32f415                    https://github.com/ArteryTek/AT32F415_Firmware_Library.git        716f545aa1290ff144ccf023a8e797b951e1bc8e  at32f415
+hw/mcu/artery/at32f423                    https://github.com/ArteryTek/AT32F423_Firmware_Library.git        2afa7f12852e57a9e8aab3a892c641e1a8635a18  at32f423
+hw/mcu/artery/at32f425                    https://github.com/ArteryTek/AT32F425_Firmware_Library.git        620233e1357d5c1b7e2bde6b9dd5196822b91817  at32f425
+hw/mcu/artery/at32f435_437                https://github.com/ArteryTek/AT32F435_437_Firmware_Library.git    25439cc6650a8ae0345934e8707a5f38c7ae41f8  at32f435_437
 hw/mcu/bridgetek/ft9xx/ft90x-sdk          https://github.com/BRTSG-FOSS/ft90x-sdk.git                       91060164afe239fcb394122e8bf9eb24d3194eb1  brtmm90x
 hw/mcu/broadcom                           https://github.com/adafruit/broadcom-peripherals.git              08370086080759ed54ac1136d62d2ad24c6fa267  broadcom_32bit broadcom_64bit
 hw/mcu/gd/nuclei-sdk                      https://github.com/Nuclei-Software/nuclei-sdk.git                 7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7  gd32vf103
@@ -44,6 +51,7 @@ hw/mcu/st/cmsis_device_n6                 https://github.com/STMicroelectronics/
 hw/mcu/st/cmsis_device_u5                 https://github.com/STMicroelectronics/cmsis_device_u5.git         5ad9797c54ec3e55eff770fc9b3cd4a1aefc1309  stm32u5
 hw/mcu/st/cmsis_device_wb                 https://github.com/STMicroelectronics/cmsis_device_wb.git         d6a7fa2e7de084f5e5e47f2ab88b022fe9b50e5a  stm32wb
 hw/mcu/st/stm32-mfxstm32l152              https://github.com/STMicroelectronics/stm32-mfxstm32l152.git      7f4389efee9c6a655b55e5df3fceef5586b35f9b  stm32h7
+hw/mcu/st/stm32-tcpp0203                  https://github.com/STMicroelectronics/stm32-tcpp0203.git          9918655bff176ac3046ccf378b5c7bbbc6a38d15  stm32h7rs stm32n6
 hw/mcu/st/stm32c0xx_hal_driver            https://github.com/STMicroelectronics/stm32c0xx_hal_driver.git    41253e2f1d7ae4a4d0c379cf63f5bcf71fcf8eb3  stm32c0
 hw/mcu/st/stm32f0xx_hal_driver            https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git    0e95cd88657030f640a11e690a8a5186c7712ea5  stm32f0
 hw/mcu/st/stm32f1xx_hal_driver            https://github.com/STMicroelectronics/stm32f1xx_hal_driver.git    1dd9d3662fb7eb2a7f7d3bc0a4c1dc7537915a29  stm32f1
@@ -67,7 +75,7 @@ hw/mcu/ti                                 https://github.com/hathach/ti_driver.g
 hw/mcu/wch/ch32f20x                       https://github.com/openwch/ch32f20x.git                           77c4095087e5ed2c548ec9058e655d0b8757663b  ch32f20x
 hw/mcu/wch/ch32v103                       https://github.com/openwch/ch32v103.git                           7578cae0b21f86dd053a1f781b2fc6ab99d0ec17  ch32v10x
 hw/mcu/wch/ch32v20x                       https://github.com/openwch/ch32v20x.git                           c4c38f507e258a4e69b059ccc2dc27dde33cea1b  ch32v20x
-hw/mcu/wch/ch32v307                       https://github.com/openwch/ch32v307.git                           184f21b852cb95eed58e86e901837bc9fff68775  ch32v307
+hw/mcu/wch/ch32v307                       https://github.com/openwch/ch32v307.git                           184f21b852cb95eed58e86e901837bc9fff68775  ch32v30x
 lib/CMSIS_5                               https://github.com/ARM-software/CMSIS_5.git                       2b7495b8535bdcb306dac29b9ded4cfb679d7e5c  imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf saml2x lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 stm32h7 stm32h7rs stm32l0 stm32l1 stm32l4 stm32l5 stm32n6 stm32u5 stm32wb sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg tm4c
 lib/CMSIS_6                               https://github.com/ARM-software/CMSIS_6.git                       b0bbb0423b278ca632cfe1474eb227961d835fd2  ra
 lib/FreeRTOS-Kernel                       https://github.com/FreeRTOS/FreeRTOS-Kernel.git                   cc0e0707c0c748713485b870bb980852b210877f  all
diff --git a/examples/device/net_lwip_webserver/skip.txt b/examples/device/net_lwip_webserver/skip.txt
index 6f66efb53..6121f1f9d 100644
--- a/examples/device/net_lwip_webserver/skip.txt
+++ b/examples/device/net_lwip_webserver/skip.txt
@@ -15,7 +15,7 @@ mcu:STM32N6
 family:broadcom_64bit
 family:broadcom_32bit
 family:espressif
-board:AT_START_F425
+board:at_start_f425
 board:curiosity_nano
 board:frdm_kl25z
 # lpc55 has weird error 'ncm_interface' causes a section type conflict with 'ntb_parameters'
diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.cmake b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.cmake
deleted file mode 100644
index 0d09680a1..000000000
--- a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.cmake
+++ /dev/null
@@ -1,8 +0,0 @@
-set(MCU_VARIANT AT32F405RCT7)
-set(MCU_LINKER_NAME AT32F405xC)
-
-set(JLINK_DEVICE ${MCU_VARIANT})
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT})
-endfunction()
diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h
deleted file mode 100644
index 0061fd242..000000000
--- a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define USB_VBUS_IGNORE
-//#define USB_SOF_OUTPUT_ENABLE
-
-// LED
-#define LED_PORT              GPIOF
-#define LED_PIN               GPIO_PINS_4
-#define LED_STATE_ON          0 // Active Low
-#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOF_PERIPH_CLOCK, TRUE)
-
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PINS_0
-#define BUTTON_STATE_ACTIVE   0
-#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
-
-//USART
-#define PRINT_UART                       USART1
-#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
-#define PRINT_UART_TX_PIN                GPIO_PINS_9
-#define PRINT_UART_TX_GPIO               GPIOA
-#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
-#define PRINT_UART_TX_PIN_SOURCE         GPIO_PINS_SOURCE9
-#define PRINT_UART_TX_PIN_MUX_NUM        GPIO_MUX_7
-
-//USB
-#ifdef BOARD_TUD_RHPORT
-    #if BOARD_TUD_RHPORT == 0
-        #define USB_ID                           USB_OTG1_ID
-        #define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
-        #define OTG_IRQ                          OTGFS1_IRQn
-        #define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
-        #define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
-        #define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
-        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
-        #define OTG_PIN_GPIO                     GPIOA
-        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_VBUS                     GPIO_PINS_9
-        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
-        #define OTG_PIN_ID                       GPIO_PINS_10
-        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
-        #define OTG_PIN_SOF_GPIO                 GPIOA
-        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_SOF                      GPIO_PINS_8
-        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
-        #define OTG_PIN_MUX                      GPIO_MUX_10
-        #define USB_SPEED_CORE_ID                USB_FULL_SPEED_CORE_ID
-    #elif BOARD_TUD_RHPORT == 1
-        #define USB_ID                           USB_OTG2_ID
-        #define OTG_CLOCK                        CRM_OTGHS_PERIPH_CLOCK
-        #define OTG_IRQ                          OTGHS_IRQn
-        #define OTG_IRQ_HANDLER                  OTGHS_IRQHandler
-        #define OTG_WKUP_IRQ                     OTGHS_WKUP_IRQn
-        #define OTG_WKUP_HANDLER                 OTGHS_WKUP_IRQHandler
-        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_20
-        #define OTG_PIN_GPIO                     GPIOB
-        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOB_PERIPH_CLOCK
-        #define OTG_PIN_VBUS                     GPIO_PINS_13
-        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE13
-        #define OTG_PIN_ID                       GPIO_PINS_12
-        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE12
-        #define OTG_PIN_SOF_GPIO                 GPIOA
-        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_SOF                      GPIO_PINS_4
-        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE4
-        #define OTG_PIN_MUX                      GPIO_MUX_10
-        #define USB_SPEED_CORE_ID                USB_HIGH_SPEED_CORE_ID
-    #endif
-#endif
-#ifdef BOARD_TUH_RHPORT
-    #if BOARD_TUH_RHPORT == 0
-        #define USB_ID                           USB_OTG1_ID
-        #define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
-        #define OTG_IRQ                          OTGFS1_IRQn
-        #define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
-        #define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
-        #define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
-        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
-        #define OTG_PIN_GPIO                     GPIOA
-        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_VBUS                     GPIO_PINS_9
-        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
-        #define OTG_PIN_ID                       GPIO_PINS_10
-        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
-        #define OTG_PIN_SOF_GPIO                 GPIOA
-        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_SOF                      GPIO_PINS_8
-        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
-        #define OTG_PIN_MUX                      GPIO_MUX_10
-        #define USB_SPEED_CORE_ID                USB_FULL_SPEED_CORE_ID
-    #elif BOARD_TUH_RHPORT == 1
-        #define USB_ID                           USB_OTG2_ID
-        #define OTG_CLOCK                        CRM_OTGHS_PERIPH_CLOCK
-        #define OTG_IRQ                          OTGHS_IRQn
-        #define OTG_IRQ_HANDLER                  OTGHS_IRQHandler
-        #define OTG_WKUP_IRQ                     OTGHS_WKUP_IRQn
-        #define OTG_WKUP_HANDLER                 OTGHS_WKUP_IRQHandler
-        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_20
-        #define OTG_PIN_GPIO                     GPIOB
-        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOB_PERIPH_CLOCK
-        #define OTG_PIN_VBUS                     GPIO_PINS_13
-        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE13
-        #define OTG_PIN_ID                       GPIO_PINS_12
-        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE12
-        #define OTG_PIN_SOF_GPIO                 GPIOA
-        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_SOF                      GPIO_PINS_4
-        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE4
-        #define OTG_PIN_MUX                      GPIO_MUX_10
-        #define USB_SPEED_CORE_ID                USB_HIGH_SPEED_CORE_ID
-    #endif
-#endif
-
-//Vbus
-static inline void board_vbus_sense_init(void)
-{
-    #ifdef BOARD_TUD_RHPORT
-        #if BOARD_TUD_RHPORT == 0
-            *(int*)(0x50000038) |= (1<<21);
-        #elif BOARD_TUD_RHPORT == 1
-            *(int*)(0x40040038) |= (1<<21);
-        #endif
-    #endif
-    #ifdef BOARD_TUH_RHPORT
-        #if BOARD_TUH_RHPORT == 0
-            *(int*)(0x50000038) |= (1<<21);
-        #elif BOARD_TUH_RHPORT == 1
-            *(int*)(0x40040038) |= (1<<21);
-        #endif
-    #endif
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk
deleted file mode 100644
index 25a719ccf..000000000
--- a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-MCU_VARIANT = AT32F405RCT7
-MCU_LINKER_NAME = AT32F405xC
-
-JLINK_DEVICE = ${MCU_VARIANT}
-
-CFLAGS += \
-  -D${MCU_VARIANT}
diff --git a/hw/bsp/at32f402_405/boards/at_start_f405/board.cmake b/hw/bsp/at32f402_405/boards/at_start_f405/board.cmake
new file mode 100644
index 000000000..0d09680a1
--- /dev/null
+++ b/hw/bsp/at32f402_405/boards/at_start_f405/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT AT32F405RCT7)
+set(MCU_LINKER_NAME AT32F405xC)
+
+set(JLINK_DEVICE ${MCU_VARIANT})
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT})
+endfunction()
diff --git a/hw/bsp/at32f402_405/boards/at_start_f405/board.h b/hw/bsp/at32f402_405/boards/at_start_f405/board.h
new file mode 100644
index 000000000..2d6cc3e57
--- /dev/null
+++ b/hw/bsp/at32f402_405/boards/at_start_f405/board.h
@@ -0,0 +1,174 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: AT-START-F405
+   url: https://www.arterychip.com/en/product/AT32F405.jsp
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define USB_VBUS_IGNORE
+//#define USB_SOF_OUTPUT_ENABLE
+
+// LED
+#define LED_PORT              GPIOF
+#define LED_PIN               GPIO_PINS_4
+#define LED_STATE_ON          0 // Active Low
+#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOF_PERIPH_CLOCK, TRUE)
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PINS_0
+#define BUTTON_STATE_ACTIVE   0
+#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
+
+//USART
+#define PRINT_UART                       USART1
+#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN                GPIO_PINS_9
+#define PRINT_UART_TX_GPIO               GPIOA
+#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN_SOURCE         GPIO_PINS_SOURCE9
+#define PRINT_UART_TX_PIN_MUX_NUM        GPIO_MUX_7
+
+//USB
+#ifdef BOARD_TUD_RHPORT
+    #if BOARD_TUD_RHPORT == 0
+        #define USB_ID                           USB_OTG1_ID
+        #define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
+        #define OTG_IRQ                          OTGFS1_IRQn
+        #define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
+        #define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
+        #define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
+        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
+        #define OTG_PIN_GPIO                     GPIOA
+        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
+        #define OTG_PIN_VBUS                     GPIO_PINS_9
+        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
+        #define OTG_PIN_ID                       GPIO_PINS_10
+        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
+        #define OTG_PIN_SOF_GPIO                 GPIOA
+        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
+        #define OTG_PIN_SOF                      GPIO_PINS_8
+        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
+        #define OTG_PIN_MUX                      GPIO_MUX_10
+        #define USB_SPEED_CORE_ID                USB_FULL_SPEED_CORE_ID
+    #elif BOARD_TUD_RHPORT == 1
+        #define USB_ID                           USB_OTG2_ID
+        #define OTG_CLOCK                        CRM_OTGHS_PERIPH_CLOCK
+        #define OTG_IRQ                          OTGHS_IRQn
+        #define OTG_IRQ_HANDLER                  OTGHS_IRQHandler
+        #define OTG_WKUP_IRQ                     OTGHS_WKUP_IRQn
+        #define OTG_WKUP_HANDLER                 OTGHS_WKUP_IRQHandler
+        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_20
+        #define OTG_PIN_GPIO                     GPIOB
+        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOB_PERIPH_CLOCK
+        #define OTG_PIN_VBUS                     GPIO_PINS_13
+        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE13
+        #define OTG_PIN_ID                       GPIO_PINS_12
+        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE12
+        #define OTG_PIN_SOF_GPIO                 GPIOA
+        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
+        #define OTG_PIN_SOF                      GPIO_PINS_4
+        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE4
+        #define OTG_PIN_MUX                      GPIO_MUX_10
+        #define USB_SPEED_CORE_ID                USB_HIGH_SPEED_CORE_ID
+    #endif
+#endif
+#ifdef BOARD_TUH_RHPORT
+    #if BOARD_TUH_RHPORT == 0
+        #define USB_ID                           USB_OTG1_ID
+        #define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
+        #define OTG_IRQ                          OTGFS1_IRQn
+        #define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
+        #define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
+        #define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
+        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
+        #define OTG_PIN_GPIO                     GPIOA
+        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
+        #define OTG_PIN_VBUS                     GPIO_PINS_9
+        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
+        #define OTG_PIN_ID                       GPIO_PINS_10
+        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
+        #define OTG_PIN_SOF_GPIO                 GPIOA
+        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
+        #define OTG_PIN_SOF                      GPIO_PINS_8
+        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
+        #define OTG_PIN_MUX                      GPIO_MUX_10
+        #define USB_SPEED_CORE_ID                USB_FULL_SPEED_CORE_ID
+    #elif BOARD_TUH_RHPORT == 1
+        #define USB_ID                           USB_OTG2_ID
+        #define OTG_CLOCK                        CRM_OTGHS_PERIPH_CLOCK
+        #define OTG_IRQ                          OTGHS_IRQn
+        #define OTG_IRQ_HANDLER                  OTGHS_IRQHandler
+        #define OTG_WKUP_IRQ                     OTGHS_WKUP_IRQn
+        #define OTG_WKUP_HANDLER                 OTGHS_WKUP_IRQHandler
+        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_20
+        #define OTG_PIN_GPIO                     GPIOB
+        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOB_PERIPH_CLOCK
+        #define OTG_PIN_VBUS                     GPIO_PINS_13
+        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE13
+        #define OTG_PIN_ID                       GPIO_PINS_12
+        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE12
+        #define OTG_PIN_SOF_GPIO                 GPIOA
+        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
+        #define OTG_PIN_SOF                      GPIO_PINS_4
+        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE4
+        #define OTG_PIN_MUX                      GPIO_MUX_10
+        #define USB_SPEED_CORE_ID                USB_HIGH_SPEED_CORE_ID
+    #endif
+#endif
+
+//Vbus
+static inline void board_vbus_sense_init(void)
+{
+    #ifdef BOARD_TUD_RHPORT
+        #if BOARD_TUD_RHPORT == 0
+            *(int*)(0x50000038) |= (1<<21);
+        #elif BOARD_TUD_RHPORT == 1
+            *(int*)(0x40040038) |= (1<<21);
+        #endif
+    #endif
+    #ifdef BOARD_TUH_RHPORT
+        #if BOARD_TUH_RHPORT == 0
+            *(int*)(0x50000038) |= (1<<21);
+        #elif BOARD_TUH_RHPORT == 1
+            *(int*)(0x40040038) |= (1<<21);
+        #endif
+    #endif
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f402_405/boards/at_start_f405/board.mk b/hw/bsp/at32f402_405/boards/at_start_f405/board.mk
new file mode 100644
index 000000000..25a719ccf
--- /dev/null
+++ b/hw/bsp/at32f402_405/boards/at_start_f405/board.mk
@@ -0,0 +1,7 @@
+MCU_VARIANT = AT32F405RCT7
+MCU_LINKER_NAME = AT32F405xC
+
+JLINK_DEVICE = ${MCU_VARIANT}
+
+CFLAGS += \
+  -D${MCU_VARIANT}
diff --git a/hw/bsp/at32f402_405/family.c b/hw/bsp/at32f402_405/family.c
index 2dbc538b8..7d94f2564 100644
--- a/hw/bsp/at32f402_405/family.c
+++ b/hw/bsp/at32f402_405/family.c
@@ -24,6 +24,10 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: Artery
+*/
+
 #include "at32f402_405_clock.h"
 #include "bsp/board_api.h"
 #include "board.h"
diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake
deleted file mode 100644
index 25c9558f9..000000000
--- a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake
+++ /dev/null
@@ -1,8 +0,0 @@
-set(MCU_VARIANT AT32F403ACGU7)
-set(MCU_LINKER_NAME AT32F403AxG)
-
-set(JLINK_DEVICE ${MCU_VARIANT})
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT})
-endfunction()
diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.h b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.h
deleted file mode 100644
index 55d9d05dc..000000000
--- a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PORT              GPIOD
-#define LED_PIN               GPIO_PINS_13
-#define LED_STATE_ON          0 // Active Low
-#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE)
-
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PINS_0
-#define BUTTON_STATE_ACTIVE   0
-#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
-
-// UART
-#define PRINT_UART                       USART1
-#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
-#define PRINT_UART_TX_PIN                GPIO_PINS_9
-#define PRINT_UART_TX_GPIO               GPIOA
-#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
-
-static inline void board_vbus_sense_init(void)
-{
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk
deleted file mode 100644
index 9bb6843aa..000000000
--- a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-MCU_VARIANT = AT32F403ACGU7
-MCU_LINKER_NAME = AT32F403AxG
-
-JLINK_DEVICE = ${MCU_VARIANT}
-
-CFLAGS += \
-  -D${MCU_VARIANT}
diff --git a/hw/bsp/at32f403a_407/boards/at_start_f403a/board.cmake b/hw/bsp/at32f403a_407/boards/at_start_f403a/board.cmake
new file mode 100644
index 000000000..25c9558f9
--- /dev/null
+++ b/hw/bsp/at32f403a_407/boards/at_start_f403a/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT AT32F403ACGU7)
+set(MCU_LINKER_NAME AT32F403AxG)
+
+set(JLINK_DEVICE ${MCU_VARIANT})
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT})
+endfunction()
diff --git a/hw/bsp/at32f403a_407/boards/at_start_f403a/board.h b/hw/bsp/at32f403a_407/boards/at_start_f403a/board.h
new file mode 100644
index 000000000..472901cfe
--- /dev/null
+++ b/hw/bsp/at32f403a_407/boards/at_start_f403a/board.h
@@ -0,0 +1,71 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: AT-START-F403a
+   url: https://www.arterychip.com/en/product/AT32F403.jsp
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOD
+#define LED_PIN               GPIO_PINS_13
+#define LED_STATE_ON          0 // Active Low
+#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE)
+
+// #define LED_PORT              GPIOA
+// #define LED_PIN               GPIO_PINS_1
+// #define LED_STATE_ON          0 // Active Low
+// #define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PINS_0
+#define BUTTON_STATE_ACTIVE   0
+#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
+
+// UART
+#define PRINT_UART                       USART1
+#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN                GPIO_PINS_9
+#define PRINT_UART_TX_GPIO               GPIOA
+#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
+
+static inline void board_vbus_sense_init(void)
+{
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f403a_407/boards/at_start_f403a/board.mk b/hw/bsp/at32f403a_407/boards/at_start_f403a/board.mk
new file mode 100644
index 000000000..9bb6843aa
--- /dev/null
+++ b/hw/bsp/at32f403a_407/boards/at_start_f403a/board.mk
@@ -0,0 +1,7 @@
+MCU_VARIANT = AT32F403ACGU7
+MCU_LINKER_NAME = AT32F403AxG
+
+JLINK_DEVICE = ${MCU_VARIANT}
+
+CFLAGS += \
+  -D${MCU_VARIANT}
diff --git a/hw/bsp/at32f403a_407/family.c b/hw/bsp/at32f403a_407/family.c
index f9a6dd70d..b05a0435f 100644
--- a/hw/bsp/at32f403a_407/family.c
+++ b/hw/bsp/at32f403a_407/family.c
@@ -24,6 +24,10 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: Artery
+*/
+
 #include "at32f403a_407_clock.h"
 #include "board.h"
 #include "bsp/board_api.h"
diff --git a/hw/bsp/at32f413/boards/AT_START_F413/board.cmake b/hw/bsp/at32f413/boards/AT_START_F413/board.cmake
deleted file mode 100644
index 0a9cc4bbd..000000000
--- a/hw/bsp/at32f413/boards/AT_START_F413/board.cmake
+++ /dev/null
@@ -1,8 +0,0 @@
-set(MCU_VARIANT AT32F413RCT7)
-set(MCU_LINKER_NAME AT32F413xC)
-
-set(JLINK_DEVICE ${MCU_VARIANT})
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT})
-endfunction()
diff --git a/hw/bsp/at32f413/boards/AT_START_F413/board.h b/hw/bsp/at32f413/boards/AT_START_F413/board.h
deleted file mode 100644
index 13ec7a207..000000000
--- a/hw/bsp/at32f413/boards/AT_START_F413/board.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// LED
-#define LED_PORT              GPIOC
-#define LED_PIN               GPIO_PINS_2
-#define LED_STATE_ON          0 // Active Low
-#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE)
-
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PINS_0
-#define BUTTON_STATE_ACTIVE   0
-#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
-
-// UART
-#define PRINT_UART                       USART1
-#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
-#define PRINT_UART_TX_PIN                GPIO_PINS_9
-#define PRINT_UART_TX_GPIO               GPIOA
-#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
-
-static inline void board_vbus_sense_init(void)
-{
-
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f413/boards/AT_START_F413/board.mk b/hw/bsp/at32f413/boards/AT_START_F413/board.mk
deleted file mode 100644
index 30fc6b9af..000000000
--- a/hw/bsp/at32f413/boards/AT_START_F413/board.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-MCU_VARIANT = AT32F413RCT7
-MCU_LINKER_NAME = AT32F413xC
-
-JLINK_DEVICE = ${MCU_VARIANT}
-
-CFLAGS += \
-  -D${MCU_VARIANT} \
-  -DCFG_EXAMPLE_VIDEO_READONLY
diff --git a/hw/bsp/at32f413/boards/at_start_f413/board.cmake b/hw/bsp/at32f413/boards/at_start_f413/board.cmake
new file mode 100644
index 000000000..0a9cc4bbd
--- /dev/null
+++ b/hw/bsp/at32f413/boards/at_start_f413/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT AT32F413RCT7)
+set(MCU_LINKER_NAME AT32F413xC)
+
+set(JLINK_DEVICE ${MCU_VARIANT})
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT})
+endfunction()
diff --git a/hw/bsp/at32f413/boards/at_start_f413/board.h b/hw/bsp/at32f413/boards/at_start_f413/board.h
new file mode 100644
index 000000000..4b386a2f4
--- /dev/null
+++ b/hw/bsp/at32f413/boards/at_start_f413/board.h
@@ -0,0 +1,67 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: AT-START-F413
+   url: https://www.arterychip.com/en/product/AT32F413.jsp
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOC
+#define LED_PIN               GPIO_PINS_2
+#define LED_STATE_ON          0 // Active Low
+#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE)
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PINS_0
+#define BUTTON_STATE_ACTIVE   0
+#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
+
+// UART
+#define PRINT_UART                       USART1
+#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN                GPIO_PINS_9
+#define PRINT_UART_TX_GPIO               GPIOA
+#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
+
+static inline void board_vbus_sense_init(void)
+{
+
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f413/boards/at_start_f413/board.mk b/hw/bsp/at32f413/boards/at_start_f413/board.mk
new file mode 100644
index 000000000..30fc6b9af
--- /dev/null
+++ b/hw/bsp/at32f413/boards/at_start_f413/board.mk
@@ -0,0 +1,8 @@
+MCU_VARIANT = AT32F413RCT7
+MCU_LINKER_NAME = AT32F413xC
+
+JLINK_DEVICE = ${MCU_VARIANT}
+
+CFLAGS += \
+  -D${MCU_VARIANT} \
+  -DCFG_EXAMPLE_VIDEO_READONLY
diff --git a/hw/bsp/at32f413/family.c b/hw/bsp/at32f413/family.c
index 6e12c6015..bb16d4d5b 100644
--- a/hw/bsp/at32f413/family.c
+++ b/hw/bsp/at32f413/family.c
@@ -24,6 +24,10 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: Artery
+*/
+
 #include "at32f413_clock.h"
 #include "board.h"
 #include "bsp/board_api.h"
diff --git a/hw/bsp/at32f415/boards/AT_START_F415/board.cmake b/hw/bsp/at32f415/boards/AT_START_F415/board.cmake
deleted file mode 100644
index 43fc43a70..000000000
--- a/hw/bsp/at32f415/boards/AT_START_F415/board.cmake
+++ /dev/null
@@ -1,11 +0,0 @@
-set(MCU_VARIANT AT32F415RCT7)
-set(MCU_LINKER_NAME AT32F415xC)
-
-set(JLINK_DEVICE ${MCU_VARIANT})
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    ${MCU_VARIANT}
-    CFG_EXAMPLE_VIDEO_READONLY
-    )
-endfunction()
diff --git a/hw/bsp/at32f415/boards/AT_START_F415/board.h b/hw/bsp/at32f415/boards/AT_START_F415/board.h
deleted file mode 100644
index 8b933f9e9..000000000
--- a/hw/bsp/at32f415/boards/AT_START_F415/board.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define USB_VBUS_IGNORE
-
-// LED
-#define LED_PORT              GPIOC
-#define LED_PIN               GPIO_PINS_2
-#define LED_STATE_ON          0 // Active Low
-#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE)
-
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PINS_0
-#define BUTTON_STATE_ACTIVE   0
-#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
-
-// Usart
-#define PRINT_UART                       USART1
-#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
-#define PRINT_UART_TX_PIN                GPIO_PINS_9
-#define PRINT_UART_TX_GPIO               GPIOA
-#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
-
-//USB
-#define USB_ID                           0
-#define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
-#define OTG_IRQ                          OTGFS1_IRQn
-#define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
-#define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
-#define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
-#define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
-#define OTG_PIN_GPIO                     GPIOA
-#define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
-#define OTG_PIN_VBUS                     GPIO_PINS_9
-#define OTG_PIN_ID                       GPIO_PINS_10
-#define OTG_PIN_SOF_GPIO                 GPIOA
-#define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-#define OTG_PIN_SOF                      GPIO_PINS_8
-
-static inline void board_vbus_sense_init(void)
-{
-    *(int*)(0x50000038) |= (1<<21);
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f415/boards/AT_START_F415/board.mk b/hw/bsp/at32f415/boards/AT_START_F415/board.mk
deleted file mode 100644
index 7ea7dc593..000000000
--- a/hw/bsp/at32f415/boards/AT_START_F415/board.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-MCU_VARIANT = AT32F415RCT7
-MCU_LINKER_NAME = AT32F415xC
-
-JLINK_DEVICE = ${MCU_VARIANT}
-
-CFLAGS += \
-  -D${MCU_VARIANT} \
-  -DCFG_EXAMPLE_VIDEO_READONLY
diff --git a/hw/bsp/at32f415/boards/at_start_f415/board.cmake b/hw/bsp/at32f415/boards/at_start_f415/board.cmake
new file mode 100644
index 000000000..43fc43a70
--- /dev/null
+++ b/hw/bsp/at32f415/boards/at_start_f415/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT AT32F415RCT7)
+set(MCU_LINKER_NAME AT32F415xC)
+
+set(JLINK_DEVICE ${MCU_VARIANT})
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    ${MCU_VARIANT}
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/at32f415/boards/at_start_f415/board.h b/hw/bsp/at32f415/boards/at_start_f415/board.h
new file mode 100644
index 000000000..0464d383e
--- /dev/null
+++ b/hw/bsp/at32f415/boards/at_start_f415/board.h
@@ -0,0 +1,85 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: AT-START-F415
+   url: https://www.arterychip.com/en/product/AT32F415.jsp
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define USB_VBUS_IGNORE
+
+// LED
+#define LED_PORT              GPIOC
+#define LED_PIN               GPIO_PINS_2
+#define LED_STATE_ON          0 // Active Low
+#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE)
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PINS_0
+#define BUTTON_STATE_ACTIVE   0
+#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
+
+// Usart
+#define PRINT_UART                       USART1
+#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN                GPIO_PINS_9
+#define PRINT_UART_TX_GPIO               GPIOA
+#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
+
+//USB
+#define USB_ID                           0
+#define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
+#define OTG_IRQ                          OTGFS1_IRQn
+#define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
+#define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
+#define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
+#define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
+#define OTG_PIN_GPIO                     GPIOA
+#define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
+#define OTG_PIN_VBUS                     GPIO_PINS_9
+#define OTG_PIN_ID                       GPIO_PINS_10
+#define OTG_PIN_SOF_GPIO                 GPIOA
+#define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
+#define OTG_PIN_SOF                      GPIO_PINS_8
+
+static inline void board_vbus_sense_init(void)
+{
+    *(int*)(0x50000038) |= (1<<21);
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f415/boards/at_start_f415/board.mk b/hw/bsp/at32f415/boards/at_start_f415/board.mk
new file mode 100644
index 000000000..7ea7dc593
--- /dev/null
+++ b/hw/bsp/at32f415/boards/at_start_f415/board.mk
@@ -0,0 +1,8 @@
+MCU_VARIANT = AT32F415RCT7
+MCU_LINKER_NAME = AT32F415xC
+
+JLINK_DEVICE = ${MCU_VARIANT}
+
+CFLAGS += \
+  -D${MCU_VARIANT} \
+  -DCFG_EXAMPLE_VIDEO_READONLY
diff --git a/hw/bsp/at32f415/family.c b/hw/bsp/at32f415/family.c
index b8ccae97d..381b79eeb 100644
--- a/hw/bsp/at32f415/family.c
+++ b/hw/bsp/at32f415/family.c
@@ -24,6 +24,10 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: Artery
+*/
+
 #include "at32f415_clock.h"
 #include "board.h"
 #include "bsp/board_api.h"
diff --git a/hw/bsp/at32f423/boards/AT_START_F423/board.cmake b/hw/bsp/at32f423/boards/AT_START_F423/board.cmake
deleted file mode 100644
index f97a12194..000000000
--- a/hw/bsp/at32f423/boards/AT_START_F423/board.cmake
+++ /dev/null
@@ -1,8 +0,0 @@
-set(MCU_VARIANT AT32F423VCT7)
-set(MCU_LINKER_NAME AT32F423xC)
-
-set(JLINK_DEVICE ${MCU_VARIANT})
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT})
-endfunction()
diff --git a/hw/bsp/at32f423/boards/AT_START_F423/board.h b/hw/bsp/at32f423/boards/AT_START_F423/board.h
deleted file mode 100644
index fc8e2d8a5..000000000
--- a/hw/bsp/at32f423/boards/AT_START_F423/board.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define USB_VBUS_IGNORE
-
-// LED
-#define LED_PORT              GPIOD
-#define LED_PIN               GPIO_PINS_13
-#define LED_STATE_ON          0 // Active Low
-#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE)
-
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PINS_0
-#define BUTTON_STATE_ACTIVE   0
-#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
-
-// UART
-#define PRINT_UART                       USART1
-#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
-#define PRINT_UART_TX_PIN                GPIO_PINS_9
-#define PRINT_UART_TX_GPIO               GPIOA
-#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
-#define PRINT_UART_TX_PIN_SOURCE         GPIO_PINS_SOURCE9
-#define PRINT_UART_TX_PIN_MUX_NUM        GPIO_MUX_7
-
-//USB
-#define USB_ID                           0
-#define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
-#define OTG_IRQ                          OTGFS1_IRQn
-#define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
-#define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
-#define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
-#define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
-#define OTG_PIN_GPIO                     GPIOA
-#define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
-#define OTG_PIN_DP                       GPIO_PINS_12
-#define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE12
-#define OTG_PIN_DM                       GPIO_PINS_11
-#define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE11
-#define OTG_PIN_VBUS                     GPIO_PINS_9
-#define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
-#define OTG_PIN_ID                       GPIO_PINS_10
-#define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
-#define OTG_PIN_SOF_GPIO                 GPIOA
-#define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-#define OTG_PIN_SOF                      GPIO_PINS_8
-#define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
-#define OTG_PIN_MUX                      GPIO_MUX_10
-
-//Vbus
-static inline void board_vbus_sense_init(void)
-{
-    *(int*)(0x50000038) |= (1<<21);
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f423/boards/AT_START_F423/board.mk b/hw/bsp/at32f423/boards/AT_START_F423/board.mk
deleted file mode 100644
index f7ef2117d..000000000
--- a/hw/bsp/at32f423/boards/AT_START_F423/board.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-MCU_VARIANT = AT32F423VCT7
-MCU_LINKER_NAME = AT32F423xC
-
-JLINK_DEVICE = ${MCU_VARIANT}
-
-CFLAGS += \
-  -D${MCU_VARIANT}
diff --git a/hw/bsp/at32f423/boards/at_start_f423/board.cmake b/hw/bsp/at32f423/boards/at_start_f423/board.cmake
new file mode 100644
index 000000000..f97a12194
--- /dev/null
+++ b/hw/bsp/at32f423/boards/at_start_f423/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT AT32F423VCT7)
+set(MCU_LINKER_NAME AT32F423xC)
+
+set(JLINK_DEVICE ${MCU_VARIANT})
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT})
+endfunction()
diff --git a/hw/bsp/at32f423/boards/at_start_f423/board.h b/hw/bsp/at32f423/boards/at_start_f423/board.h
new file mode 100644
index 000000000..ef85b4977
--- /dev/null
+++ b/hw/bsp/at32f423/boards/at_start_f423/board.h
@@ -0,0 +1,96 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: AT-START-F423
+   url: https://www.arterychip.com/en/product/AT32F423.jsp
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define USB_VBUS_IGNORE
+
+// LED
+#define LED_PORT              GPIOD
+#define LED_PIN               GPIO_PINS_13
+#define LED_STATE_ON          0 // Active Low
+#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE)
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PINS_0
+#define BUTTON_STATE_ACTIVE   0
+#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
+
+// UART
+#define PRINT_UART                       USART1
+#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN                GPIO_PINS_9
+#define PRINT_UART_TX_GPIO               GPIOA
+#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN_SOURCE         GPIO_PINS_SOURCE9
+#define PRINT_UART_TX_PIN_MUX_NUM        GPIO_MUX_7
+
+//USB
+#define USB_ID                           0
+#define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
+#define OTG_IRQ                          OTGFS1_IRQn
+#define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
+#define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
+#define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
+#define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
+#define OTG_PIN_GPIO                     GPIOA
+#define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
+#define OTG_PIN_DP                       GPIO_PINS_12
+#define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE12
+#define OTG_PIN_DM                       GPIO_PINS_11
+#define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE11
+#define OTG_PIN_VBUS                     GPIO_PINS_9
+#define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
+#define OTG_PIN_ID                       GPIO_PINS_10
+#define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
+#define OTG_PIN_SOF_GPIO                 GPIOA
+#define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
+#define OTG_PIN_SOF                      GPIO_PINS_8
+#define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
+#define OTG_PIN_MUX                      GPIO_MUX_10
+
+//Vbus
+static inline void board_vbus_sense_init(void)
+{
+    *(int*)(0x50000038) |= (1<<21);
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f423/boards/at_start_f423/board.mk b/hw/bsp/at32f423/boards/at_start_f423/board.mk
new file mode 100644
index 000000000..f7ef2117d
--- /dev/null
+++ b/hw/bsp/at32f423/boards/at_start_f423/board.mk
@@ -0,0 +1,7 @@
+MCU_VARIANT = AT32F423VCT7
+MCU_LINKER_NAME = AT32F423xC
+
+JLINK_DEVICE = ${MCU_VARIANT}
+
+CFLAGS += \
+  -D${MCU_VARIANT}
diff --git a/hw/bsp/at32f423/family.c b/hw/bsp/at32f423/family.c
index 5e9e70dd8..723a8a2c9 100644
--- a/hw/bsp/at32f423/family.c
+++ b/hw/bsp/at32f423/family.c
@@ -24,6 +24,10 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: Artery
+*/
+
 #include "at32f423_clock.h"
 #include "board.h"
 #include "bsp/board_api.h"
diff --git a/hw/bsp/at32f425/boards/AT_START_F425/board.cmake b/hw/bsp/at32f425/boards/AT_START_F425/board.cmake
deleted file mode 100644
index 535bb3cb4..000000000
--- a/hw/bsp/at32f425/boards/AT_START_F425/board.cmake
+++ /dev/null
@@ -1,12 +0,0 @@
-set(MCU_VARIANT AT32F425R8T7)
-set(MCU_LINKER_NAME AT32F425x8)
-
-set(JLINK_DEVICE ${MCU_VARIANT})
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    ${MCU_VARIANT}
-    CFG_EXAMPLE_VIDEO_READONLY
-    CFG_EXAMPLE_MSC_READONLY
-    )
-endfunction()
diff --git a/hw/bsp/at32f425/boards/AT_START_F425/board.h b/hw/bsp/at32f425/boards/AT_START_F425/board.h
deleted file mode 100644
index ddfe1f71b..000000000
--- a/hw/bsp/at32f425/boards/AT_START_F425/board.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define USB_VBUS_IGNORE
-
-// LED
-#define LED_PORT              GPIOC
-#define LED_PIN               GPIO_PINS_2
-#define LED_STATE_ON          0 // Active Low
-#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE)
-
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PINS_0
-#define BUTTON_STATE_ACTIVE   0
-#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
-
-// Usart
-#define PRINT_UART                       USART1
-#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
-#define PRINT_UART_TX_PIN                GPIO_PINS_9
-#define PRINT_UART_TX_GPIO               GPIOA
-#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
-#define PRINT_UART_TX_PIN_SOURCE         GPIO_PINS_SOURCE9
-#define PRINT_UART_TX_PIN_MUX_NUM        GPIO_MUX_1
-
-//USB
-#define USB_ID                           0
-#define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
-#define OTG_IRQ                          OTGFS1_IRQn
-#define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
-#define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
-#define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
-#define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
-#define OTG_PIN_GPIO                     GPIOA
-#define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
-#define OTG_PIN_DP                       GPIO_PINS_12
-#define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE12
-#define OTG_PIN_DM                       GPIO_PINS_11
-#define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE11
-#define OTG_PIN_VBUS                     GPIO_PINS_9
-#define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
-#define OTG_PIN_ID                       GPIO_PINS_10
-#define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
-#define OTG_PIN_SOF_GPIO                 GPIOA
-#define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-#define OTG_PIN_SOF                      GPIO_PINS_8
-#define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
-#define OTG_PIN_MUX                      GPIO_MUX_3
-
-static inline void board_vbus_sense_init(void)
-{
-    *(int*)(0x50000038) |= (1<<21);
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f425/boards/AT_START_F425/board.mk b/hw/bsp/at32f425/boards/AT_START_F425/board.mk
deleted file mode 100644
index f7aeba1db..000000000
--- a/hw/bsp/at32f425/boards/AT_START_F425/board.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-MCU_VARIANT = AT32F425R8T7
-MCU_LINKER_NAME = AT32F425x8
-
-JLINK_DEVICE = ${MCU_VARIANT}
-
-CFLAGS += \
-  -D${MCU_VARIANT} \
-  -DCFG_EXAMPLE_VIDEO_READONLY \
-  -DCFG_EXAMPLE_MSC_READONLY
diff --git a/hw/bsp/at32f425/boards/at_start_f425/board.cmake b/hw/bsp/at32f425/boards/at_start_f425/board.cmake
new file mode 100644
index 000000000..535bb3cb4
--- /dev/null
+++ b/hw/bsp/at32f425/boards/at_start_f425/board.cmake
@@ -0,0 +1,12 @@
+set(MCU_VARIANT AT32F425R8T7)
+set(MCU_LINKER_NAME AT32F425x8)
+
+set(JLINK_DEVICE ${MCU_VARIANT})
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    ${MCU_VARIANT}
+    CFG_EXAMPLE_VIDEO_READONLY
+    CFG_EXAMPLE_MSC_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/at32f425/boards/at_start_f425/board.h b/hw/bsp/at32f425/boards/at_start_f425/board.h
new file mode 100644
index 000000000..145eab3b9
--- /dev/null
+++ b/hw/bsp/at32f425/boards/at_start_f425/board.h
@@ -0,0 +1,95 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: AT-START-F425
+   url: https://www.arterychip.com/en/product/AT32F425.jsp
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define USB_VBUS_IGNORE
+
+// LED
+#define LED_PORT              GPIOC
+#define LED_PIN               GPIO_PINS_2
+#define LED_STATE_ON          0 // Active Low
+#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE)
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PINS_0
+#define BUTTON_STATE_ACTIVE   0
+#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
+
+// Usart
+#define PRINT_UART                       USART1
+#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN                GPIO_PINS_9
+#define PRINT_UART_TX_GPIO               GPIOA
+#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN_SOURCE         GPIO_PINS_SOURCE9
+#define PRINT_UART_TX_PIN_MUX_NUM        GPIO_MUX_1
+
+//USB
+#define USB_ID                           0
+#define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
+#define OTG_IRQ                          OTGFS1_IRQn
+#define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
+#define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
+#define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
+#define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
+#define OTG_PIN_GPIO                     GPIOA
+#define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
+#define OTG_PIN_DP                       GPIO_PINS_12
+#define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE12
+#define OTG_PIN_DM                       GPIO_PINS_11
+#define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE11
+#define OTG_PIN_VBUS                     GPIO_PINS_9
+#define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
+#define OTG_PIN_ID                       GPIO_PINS_10
+#define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
+#define OTG_PIN_SOF_GPIO                 GPIOA
+#define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
+#define OTG_PIN_SOF                      GPIO_PINS_8
+#define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
+#define OTG_PIN_MUX                      GPIO_MUX_3
+
+static inline void board_vbus_sense_init(void)
+{
+    *(int*)(0x50000038) |= (1<<21);
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f425/boards/at_start_f425/board.mk b/hw/bsp/at32f425/boards/at_start_f425/board.mk
new file mode 100644
index 000000000..f7aeba1db
--- /dev/null
+++ b/hw/bsp/at32f425/boards/at_start_f425/board.mk
@@ -0,0 +1,9 @@
+MCU_VARIANT = AT32F425R8T7
+MCU_LINKER_NAME = AT32F425x8
+
+JLINK_DEVICE = ${MCU_VARIANT}
+
+CFLAGS += \
+  -D${MCU_VARIANT} \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
+  -DCFG_EXAMPLE_MSC_READONLY
diff --git a/hw/bsp/at32f425/family.c b/hw/bsp/at32f425/family.c
index 26e69bf31..963e1485f 100644
--- a/hw/bsp/at32f425/family.c
+++ b/hw/bsp/at32f425/family.c
@@ -24,6 +24,10 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: Artery
+*/
+
 #include "at32f425_clock.h"
 #include "board.h"
 #include "bsp/board_api.h"
diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.cmake b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.cmake
deleted file mode 100644
index fc54dbcab..000000000
--- a/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.cmake
+++ /dev/null
@@ -1,8 +0,0 @@
-set(MCU_VARIANT AT32F437ZMT7)
-set(MCU_LINKER_NAME AT32F437xM)
-
-set(JLINK_DEVICE ${MCU_VARIANT})
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT})
-endfunction()
diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.h b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.h
deleted file mode 100644
index ef4ec6dcf..000000000
--- a/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-//#define USB_VBUS_IGNORE
-//#define USB_SOF_OUTPUT_ENABLE
-
-// LED
-#define LED_PORT              GPIOD
-#define LED_PIN               GPIO_PINS_13
-#define LED_STATE_ON          0 // Active Low
-#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE)
-
-// Button
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PINS_0
-#define BUTTON_STATE_ACTIVE   1
-#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
-
-// USART
-#define PRINT_UART                       USART1
-#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
-#define PRINT_UART_TX_PIN                GPIO_PINS_9
-#define PRINT_UART_TX_GPIO               GPIOA
-#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
-#define PRINT_UART_TX_PIN_SOURCE         GPIO_PINS_SOURCE9
-#define PRINT_UART_TX_PIN_MUX_NUM        GPIO_MUX_7
-
-// USB
-#ifdef BOARD_TUD_RHPORT
-    #if BOARD_TUD_RHPORT == 0
-        #define USB_ID                           0
-        #define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
-        #define OTG_IRQ                          OTGFS1_IRQn
-        #define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
-        #define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
-        #define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
-        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
-        #define OTG_PIN_GPIO                     GPIOA
-        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_DP                       GPIO_PINS_12
-        #define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE12
-        #define OTG_PIN_DM                       GPIO_PINS_11
-        #define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE11
-        #define OTG_PIN_VBUS                     GPIO_PINS_9
-        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
-        #define OTG_PIN_ID                       GPIO_PINS_10
-        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE12
-        #define OTG_PIN_SOF_GPIO                 GPIOA
-        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_SOF                      GPIO_PINS_8
-        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
-        #define OTG_PIN_MUX                      GPIO_MUX_10
-    #elif BOARD_TUD_RHPORT == 1
-        #define USB_ID                           1
-        #define OTG_CLOCK                        CRM_OTGFS2_PERIPH_CLOCK
-        #define OTG_IRQ                          OTGFS2_IRQn
-        #define OTG_IRQ_HANDLER                  OTGFS2_IRQHandler
-        #define OTG_WKUP_IRQ                     OTGFS2_WKUP_IRQn
-        #define OTG_WKUP_HANDLER                 OTGFS2_WKUP_IRQHandler
-        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_20
-        #define OTG_PIN_GPIO                     GPIOB
-        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOB_PERIPH_CLOCK
-        #define OTG_PIN_DP                       GPIO_PINS_15
-        #define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE15
-        #define OTG_PIN_DM                       GPIO_PINS_14
-        #define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE14
-        #define OTG_PIN_VBUS                     GPIO_PINS_13
-        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE13
-        #define OTG_PIN_ID                       GPIO_PINS_12
-        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
-        #define OTG_PIN_SOF_GPIO                 GPIOA
-        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_SOF                      GPIO_PINS_4
-        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE4
-        #define OTG_PIN_MUX                      GPIO_MUX_12
-    #endif
-#endif
-
-#ifdef BOARD_TUH_RHPORT
-    #if BOARD_TUH_RHPORT == 0
-        #define USB_ID                           0
-        #define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
-        #define OTG_IRQ                          OTGFS1_IRQn
-        #define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
-        #define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
-        #define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
-        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
-        #define OTG_PIN_GPIO                     GPIOA
-        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_DP                       GPIO_PINS_12
-        #define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE12
-        #define OTG_PIN_DM                       GPIO_PINS_11
-        #define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE11
-        #define OTG_PIN_VBUS                     GPIO_PINS_9
-        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
-        #define OTG_PIN_ID                       GPIO_PINS_10
-        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE12
-        #define OTG_PIN_SOF_GPIO                 GPIOA
-        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_SOF                      GPIO_PINS_8
-        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
-        #define OTG_PIN_MUX                      GPIO_MUX_10
-    #elif BOARD_TUH_RHPORT == 1
-        #define USB_ID                           1
-        #define OTG_CLOCK                        CRM_OTGFS2_PERIPH_CLOCK
-        #define OTG_IRQ                          OTGFS2_IRQn
-        #define OTG_IRQ_HANDLER                  OTGFS2_IRQHandler
-        #define OTG_WKUP_IRQ                     OTGFS2_WKUP_IRQn
-        #define OTG_WKUP_HANDLER                 OTGFS2_WKUP_IRQHandler
-        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_20
-        #define OTG_PIN_GPIO                     GPIOB
-        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOB_PERIPH_CLOCK
-        #define OTG_PIN_DP                       GPIO_PINS_15
-        #define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE15
-        #define OTG_PIN_DM                       GPIO_PINS_14
-        #define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE14
-        #define OTG_PIN_VBUS                     GPIO_PINS_13
-        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE13
-        #define OTG_PIN_ID                       GPIO_PINS_12
-        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
-        #define OTG_PIN_SOF_GPIO                 GPIOA
-        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_SOF                      GPIO_PINS_4
-        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE4
-        #define OTG_PIN_MUX                      GPIO_MUX_12
-    #endif
-#endif
-
-// VBUS
-static inline void board_vbus_sense_init(void)
-{
-    #ifdef BOARD_TUD_RHPORT
-        #if BOARD_TUD_RHPORT == 0
-            *(int*)(0x50000038) |= (1<<21);
-        #elif BOARD_TUD_RHPORT == 1
-            *(int*)(0x40040038) |= (1<<21);
-        #endif
-    #endif
-    #ifdef BOARD_TUH_RHPORT
-        #if BOARD_TUH_RHPORT == 0
-            *(int*)(0x50000038) |= (1<<21);
-        #elif BOARD_TUH_RHPORT == 1
-            *(int*)(0x40040038) |= (1<<21);
-        #endif
-    #endif
-}
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk
deleted file mode 100644
index e663d59f0..000000000
--- a/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-MCU_VARIANT = AT32F437ZMT7
-MCU_LINKER_NAME = AT32F437xM
-
-JLINK_DEVICE = ${MCU_VARIANT}
-
-CFLAGS += \
-  -D${MCU_VARIANT}
diff --git a/hw/bsp/at32f435_437/boards/at_start_f437/board.cmake b/hw/bsp/at32f435_437/boards/at_start_f437/board.cmake
new file mode 100644
index 000000000..fc54dbcab
--- /dev/null
+++ b/hw/bsp/at32f435_437/boards/at_start_f437/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT AT32F437ZMT7)
+set(MCU_LINKER_NAME AT32F437xM)
+
+set(JLINK_DEVICE ${MCU_VARIANT})
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT})
+endfunction()
diff --git a/hw/bsp/at32f435_437/boards/at_start_f437/board.h b/hw/bsp/at32f435_437/boards/at_start_f437/board.h
new file mode 100644
index 000000000..b6de119bc
--- /dev/null
+++ b/hw/bsp/at32f435_437/boards/at_start_f437/board.h
@@ -0,0 +1,187 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: AT-START-F437
+   url: https://www.arterychip.com/en/product/AT32F437.jsp
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//#define USB_VBUS_IGNORE
+//#define USB_SOF_OUTPUT_ENABLE
+
+// LED
+#define LED_PORT              GPIOD
+#define LED_PIN               GPIO_PINS_13
+#define LED_STATE_ON          0 // Active Low
+#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE)
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PINS_0
+#define BUTTON_STATE_ACTIVE   1
+#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
+
+// USART
+#define PRINT_UART                       USART1
+#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN                GPIO_PINS_9
+#define PRINT_UART_TX_GPIO               GPIOA
+#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN_SOURCE         GPIO_PINS_SOURCE9
+#define PRINT_UART_TX_PIN_MUX_NUM        GPIO_MUX_7
+
+// USB
+#ifdef BOARD_TUD_RHPORT
+    #if BOARD_TUD_RHPORT == 0
+        #define USB_ID                           0
+        #define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
+        #define OTG_IRQ                          OTGFS1_IRQn
+        #define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
+        #define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
+        #define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
+        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
+        #define OTG_PIN_GPIO                     GPIOA
+        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
+        #define OTG_PIN_DP                       GPIO_PINS_12
+        #define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE12
+        #define OTG_PIN_DM                       GPIO_PINS_11
+        #define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE11
+        #define OTG_PIN_VBUS                     GPIO_PINS_9
+        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
+        #define OTG_PIN_ID                       GPIO_PINS_10
+        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE12
+        #define OTG_PIN_SOF_GPIO                 GPIOA
+        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
+        #define OTG_PIN_SOF                      GPIO_PINS_8
+        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
+        #define OTG_PIN_MUX                      GPIO_MUX_10
+    #elif BOARD_TUD_RHPORT == 1
+        #define USB_ID                           1
+        #define OTG_CLOCK                        CRM_OTGFS2_PERIPH_CLOCK
+        #define OTG_IRQ                          OTGFS2_IRQn
+        #define OTG_IRQ_HANDLER                  OTGFS2_IRQHandler
+        #define OTG_WKUP_IRQ                     OTGFS2_WKUP_IRQn
+        #define OTG_WKUP_HANDLER                 OTGFS2_WKUP_IRQHandler
+        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_20
+        #define OTG_PIN_GPIO                     GPIOB
+        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOB_PERIPH_CLOCK
+        #define OTG_PIN_DP                       GPIO_PINS_15
+        #define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE15
+        #define OTG_PIN_DM                       GPIO_PINS_14
+        #define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE14
+        #define OTG_PIN_VBUS                     GPIO_PINS_13
+        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE13
+        #define OTG_PIN_ID                       GPIO_PINS_12
+        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
+        #define OTG_PIN_SOF_GPIO                 GPIOA
+        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
+        #define OTG_PIN_SOF                      GPIO_PINS_4
+        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE4
+        #define OTG_PIN_MUX                      GPIO_MUX_12
+    #endif
+#endif
+
+#ifdef BOARD_TUH_RHPORT
+    #if BOARD_TUH_RHPORT == 0
+        #define USB_ID                           0
+        #define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
+        #define OTG_IRQ                          OTGFS1_IRQn
+        #define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
+        #define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
+        #define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
+        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
+        #define OTG_PIN_GPIO                     GPIOA
+        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
+        #define OTG_PIN_DP                       GPIO_PINS_12
+        #define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE12
+        #define OTG_PIN_DM                       GPIO_PINS_11
+        #define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE11
+        #define OTG_PIN_VBUS                     GPIO_PINS_9
+        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
+        #define OTG_PIN_ID                       GPIO_PINS_10
+        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE12
+        #define OTG_PIN_SOF_GPIO                 GPIOA
+        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
+        #define OTG_PIN_SOF                      GPIO_PINS_8
+        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
+        #define OTG_PIN_MUX                      GPIO_MUX_10
+    #elif BOARD_TUH_RHPORT == 1
+        #define USB_ID                           1
+        #define OTG_CLOCK                        CRM_OTGFS2_PERIPH_CLOCK
+        #define OTG_IRQ                          OTGFS2_IRQn
+        #define OTG_IRQ_HANDLER                  OTGFS2_IRQHandler
+        #define OTG_WKUP_IRQ                     OTGFS2_WKUP_IRQn
+        #define OTG_WKUP_HANDLER                 OTGFS2_WKUP_IRQHandler
+        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_20
+        #define OTG_PIN_GPIO                     GPIOB
+        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOB_PERIPH_CLOCK
+        #define OTG_PIN_DP                       GPIO_PINS_15
+        #define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE15
+        #define OTG_PIN_DM                       GPIO_PINS_14
+        #define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE14
+        #define OTG_PIN_VBUS                     GPIO_PINS_13
+        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE13
+        #define OTG_PIN_ID                       GPIO_PINS_12
+        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
+        #define OTG_PIN_SOF_GPIO                 GPIOA
+        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
+        #define OTG_PIN_SOF                      GPIO_PINS_4
+        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE4
+        #define OTG_PIN_MUX                      GPIO_MUX_12
+    #endif
+#endif
+
+// VBUS
+static inline void board_vbus_sense_init(void)
+{
+    #ifdef BOARD_TUD_RHPORT
+        #if BOARD_TUD_RHPORT == 0
+            *(int*)(0x50000038) |= (1<<21);
+        #elif BOARD_TUD_RHPORT == 1
+            *(int*)(0x40040038) |= (1<<21);
+        #endif
+    #endif
+    #ifdef BOARD_TUH_RHPORT
+        #if BOARD_TUH_RHPORT == 0
+            *(int*)(0x50000038) |= (1<<21);
+        #elif BOARD_TUH_RHPORT == 1
+            *(int*)(0x40040038) |= (1<<21);
+        #endif
+    #endif
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f435_437/boards/at_start_f437/board.mk b/hw/bsp/at32f435_437/boards/at_start_f437/board.mk
new file mode 100644
index 000000000..e663d59f0
--- /dev/null
+++ b/hw/bsp/at32f435_437/boards/at_start_f437/board.mk
@@ -0,0 +1,7 @@
+MCU_VARIANT = AT32F437ZMT7
+MCU_LINKER_NAME = AT32F437xM
+
+JLINK_DEVICE = ${MCU_VARIANT}
+
+CFLAGS += \
+  -D${MCU_VARIANT}
diff --git a/hw/bsp/at32f435_437/family.c b/hw/bsp/at32f435_437/family.c
index c93beeb5a..702fdd2a8 100644
--- a/hw/bsp/at32f435_437/family.c
+++ b/hw/bsp/at32f435_437/family.c
@@ -24,6 +24,10 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* metadata:
+   manufacturer: Artery
+*/
+
 #include "at32f435_437_clock.h"
 #include "board.h"
 #include "bsp/board_api.h"
-- 
cgit v1.3.1


From 4a78e4c86193c562c684a7e445276982ae9a7cd5 Mon Sep 17 00:00:00 2001
From: Jie Feng <hjf3108@gmail.com>
Date: Sun, 10 Aug 2025 13:29:41 +0800
Subject: Add to boards.rst file

---
 docs/reference/boards.rst                          | 23 +++++++++++-----------
 .../boards/at32f403a_weact_blackpill/board.h       |  2 +-
 2 files changed, 13 insertions(+), 12 deletions(-)

(limited to 'docs/reference')

diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst
index 289ec543a..d35cf7b06 100644
--- a/docs/reference/boards.rst
+++ b/docs/reference/boards.rst
@@ -30,17 +30,18 @@ max78002evkit  MAX78002 EVKIT    maxim     https://www.analog.com/en/resources/e
 Artery
 -----
 
-==============  ==============  =============  ==================================================  ======
-Board           Name            Family         URL                                                 Note
-==============  ==============  =============  ==================================================  ======
-at_start_f405   AT-START-F405   at32f402_405   https://www.arterychip.com/en/product/AT32F405.jsp
-at_start_f403a  AT-START-F403a  at32f403a_407  https://www.arterychip.com/en/product/AT32F403.jsp
-at_start_f413   AT-START-F413   at32f413       https://www.arterychip.com/en/product/AT32F413.jsp
-at_start_f415   AT-START-F415   at32f415       https://www.arterychip.com/en/product/AT32F415.jsp
-at_start_f423   AT-START-F423   at32f423       https://www.arterychip.com/en/product/AT32F423.jsp
-at_start_f425   AT-START-F425   at32f425       https://www.arterychip.com/en/product/AT32F425.jsp
-at_start_f437   AT-START-F437   at32f435_437   https://www.arterychip.com/en/product/AT32F437.jsp
-==============  ==============  =============  ==================================================  ======
+==============             ==============                        =============  ==================================================   ======
+Board                      Name                                  Family         URL                                                  Note
+==============             ==============                        =============  ==================================================   ======
+at_start_f405              AT-START-F405                         at32f402_405   https://www.arterychip.com/en/product/AT32F405.jsp
+at_start_f403a             AT-START-F403a                        at32f403a_407  https://www.arterychip.com/en/product/AT32F403.jsp
+at32f403a_weact_blackpill  WeAct Studio BlackPill AT32F403ACGU7  at32f403a_407  https://github.com/WeActStudio/WeActStudio.BlackPill
+at_start_f413              AT-START-F413                         at32f413       https://www.arterychip.com/en/product/AT32F413.jsp
+at_start_f415              AT-START-F415                         at32f415       https://www.arterychip.com/en/product/AT32F415.jsp
+at_start_f423              AT-START-F423                         at32f423       https://www.arterychip.com/en/product/AT32F423.jsp
+at_start_f425              AT-START-F425                         at32f425       https://www.arterychip.com/en/product/AT32F425.jsp
+at_start_f437              AT-START-F437                         at32f435_437   https://www.arterychip.com/en/product/AT32F437.jsp
+==============             ==============                        =============  ==================================================   ======
 
 Bridgetek
 ---------
diff --git a/hw/bsp/at32f403a_407/boards/at32f403a_weact_blackpill/board.h b/hw/bsp/at32f403a_407/boards/at32f403a_weact_blackpill/board.h
index 73b6f91c1..005c5aed6 100644
--- a/hw/bsp/at32f403a_407/boards/at32f403a_weact_blackpill/board.h
+++ b/hw/bsp/at32f403a_407/boards/at32f403a_weact_blackpill/board.h
@@ -25,7 +25,7 @@
  */
 
 /* metadata:
-   name: WeAct Studio BlackPill AT32F403ACGx
+   name: WeAct Studio BlackPill AT32F403ACGU7
    url: https://github.com/WeActStudio/WeActStudio.BlackPill
 */
 
-- 
cgit v1.3.1


From 24e596b977f8e17e2c672cbbf8c337ced38a4788 Mon Sep 17 00:00:00 2001
From: Jie Feng <hjf3108@gmail.com>
Date: Sun, 10 Aug 2025 13:33:51 +0800
Subject: Fix file

---
 docs/reference/boards.rst | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'docs/reference')

diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst
index d35cf7b06..f4f2f6d1f 100644
--- a/docs/reference/boards.rst
+++ b/docs/reference/boards.rst
@@ -30,9 +30,9 @@ max78002evkit  MAX78002 EVKIT    maxim     https://www.analog.com/en/resources/e
 Artery
 -----
 
-==============             ==============                        =============  ==================================================   ======
-Board                      Name                                  Family         URL                                                  Note
-==============             ==============                        =============  ==================================================   ======
+=========================  ====================================  =============  ====================================================  ======
+Board                      Name                                  Family         URL                                                   Note
+=========================  ====================================  =============  ====================================================  ======
 at_start_f405              AT-START-F405                         at32f402_405   https://www.arterychip.com/en/product/AT32F405.jsp
 at_start_f403a             AT-START-F403a                        at32f403a_407  https://www.arterychip.com/en/product/AT32F403.jsp
 at32f403a_weact_blackpill  WeAct Studio BlackPill AT32F403ACGU7  at32f403a_407  https://github.com/WeActStudio/WeActStudio.BlackPill
@@ -41,7 +41,7 @@ at_start_f415              AT-START-F415                         at32f415
 at_start_f423              AT-START-F423                         at32f423       https://www.arterychip.com/en/product/AT32F423.jsp
 at_start_f425              AT-START-F425                         at32f425       https://www.arterychip.com/en/product/AT32F425.jsp
 at_start_f437              AT-START-F437                         at32f435_437   https://www.arterychip.com/en/product/AT32F437.jsp
-==============             ==============                        =============  ==================================================   ======
+=========================  ====================================  =============  ====================================================  ======
 
 Bridgetek
 ---------
-- 
cgit v1.3.1


From eda5c3a5d1f7c4d402acbd739d025ee84eb39828 Mon Sep 17 00:00:00 2001
From: Aleksei Musin <aleksei.musin@alango.com>
Date: Sun, 24 Aug 2025 17:21:20 +0400
Subject: STM32N6570-DK gets listed in boards.rst

---
 docs/reference/boards.rst | 1 +
 1 file changed, 1 insertion(+)

(limited to 'docs/reference')

diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst
index 289ec543a..2368dd9e5 100644
--- a/docs/reference/boards.rst
+++ b/docs/reference/boards.rst
@@ -292,6 +292,7 @@ stm32l412nucleo      STM32 L412 Nucleo                  stm32l4    https://www.s
 stm32l476disco       STM32 L476 Disco                   stm32l4    https://www.st.com/en/evaluation-tools/32l476gdiscovery.html
 stm32l4p5nucleo      STM32 L4P5 Nucleo                  stm32l4    https://www.st.com/en/evaluation-tools/nucleo-l4p5zg.html
 stm32l4r5nucleo      STM32 L4R5 Nucleo                  stm32l4    https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html
+stm32n6570dk         STM32 N6570-DK                     stm32n6    https://www.st.com/en/evaluation-tools/stm32n6570-dk.html
 stm32n657nucleo      STM32 N657X0-Q Nucleo              stm32n6    https://www.st.com/en/evaluation-tools/nucleo-n657x0-q.html
 b_u585i_iot2a        STM32 B-U585i IOT2A Discovery kit  stm32u5    https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html
 stm32u545nucleo      STM32 U545 Nucleo                  stm32u5    https://www.st.com/en/evaluation-tools/nucleo-u545re-q.html
-- 
cgit v1.3.1


From f6ca80ab13997d8fdee084d218c22ae15d734e2a Mon Sep 17 00:00:00 2001
From: zhiqiang <zhiqiangyou@arterytek.com>
Date: Thu, 4 Sep 2025 14:38:27 +0800
Subject: modified the bsp files of at32 to make them work better

---
 docs/reference/boards.rst                          |  26 ++---
 .../at32f402_405/boards/at_start_f402/board.cmake  |   8 ++
 hw/bsp/at32f402_405/boards/at_start_f402/board.h   |  74 +++++++++++++
 hw/bsp/at32f402_405/boards/at_start_f402/board.mk  |   7 ++
 .../at32f402_405/boards/at_start_f405/board.cmake  |   9 ++
 hw/bsp/at32f402_405/boards/at_start_f405/board.h   | 106 +------------------
 hw/bsp/at32f402_405/boards/at_start_f405/board.mk  |   4 +
 hw/bsp/at32f402_405/family.c                       |  32 ++----
 hw/bsp/at32f402_405/family.cmake                   |  23 +++-
 hw/bsp/at32f402_405/family.mk                      |  28 ++++-
 .../boards/at_start_f403a/board.cmake              |   2 +-
 .../at32f403a_407/boards/at_start_f403a/board.mk   |   2 +-
 .../at32f403a_407/boards/at_start_f407/board.cmake |   8 ++
 hw/bsp/at32f403a_407/boards/at_start_f407/board.h  |  71 +++++++++++++
 hw/bsp/at32f403a_407/boards/at_start_f407/board.mk |   7 ++
 hw/bsp/at32f403a_407/family.c                      |   4 +-
 hw/bsp/at32f413/boards/at_start_f413/board.h       |   2 +-
 hw/bsp/at32f415/boards/at_start_f415/board.h       |   2 +-
 hw/bsp/at32f423/boards/at_start_f423/board.h       |   2 +-
 hw/bsp/at32f425/boards/at_start_f425/board.h       |   2 +-
 .../at32f435_437/boards/at_start_f435/board.cmake  |   8 ++
 hw/bsp/at32f435_437/boards/at_start_f435/board.h   |  74 +++++++++++++
 hw/bsp/at32f435_437/boards/at_start_f435/board.mk  |   7 ++
 hw/bsp/at32f435_437/boards/at_start_f437/board.h   | 117 +--------------------
 hw/bsp/at32f435_437/family.c                       |  40 +++----
 hw/bsp/at32f435_437/family.cmake                   |   7 +-
 hw/bsp/at32f435_437/family.mk                      |   5 +-
 27 files changed, 384 insertions(+), 293 deletions(-)
 create mode 100644 hw/bsp/at32f402_405/boards/at_start_f402/board.cmake
 create mode 100644 hw/bsp/at32f402_405/boards/at_start_f402/board.h
 create mode 100644 hw/bsp/at32f402_405/boards/at_start_f402/board.mk
 create mode 100644 hw/bsp/at32f403a_407/boards/at_start_f407/board.cmake
 create mode 100644 hw/bsp/at32f403a_407/boards/at_start_f407/board.h
 create mode 100644 hw/bsp/at32f403a_407/boards/at_start_f407/board.mk
 create mode 100644 hw/bsp/at32f435_437/boards/at_start_f435/board.cmake
 create mode 100644 hw/bsp/at32f435_437/boards/at_start_f435/board.h
 create mode 100644 hw/bsp/at32f435_437/boards/at_start_f435/board.mk

(limited to 'docs/reference')

diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst
index f4f2f6d1f..d984b3529 100644
--- a/docs/reference/boards.rst
+++ b/docs/reference/boards.rst
@@ -30,18 +30,20 @@ max78002evkit  MAX78002 EVKIT    maxim     https://www.analog.com/en/resources/e
 Artery
 -----
 
-=========================  ====================================  =============  ====================================================  ======
-Board                      Name                                  Family         URL                                                   Note
-=========================  ====================================  =============  ====================================================  ======
-at_start_f405              AT-START-F405                         at32f402_405   https://www.arterychip.com/en/product/AT32F405.jsp
-at_start_f403a             AT-START-F403a                        at32f403a_407  https://www.arterychip.com/en/product/AT32F403.jsp
-at32f403a_weact_blackpill  WeAct Studio BlackPill AT32F403ACGU7  at32f403a_407  https://github.com/WeActStudio/WeActStudio.BlackPill
-at_start_f413              AT-START-F413                         at32f413       https://www.arterychip.com/en/product/AT32F413.jsp
-at_start_f415              AT-START-F415                         at32f415       https://www.arterychip.com/en/product/AT32F415.jsp
-at_start_f423              AT-START-F423                         at32f423       https://www.arterychip.com/en/product/AT32F423.jsp
-at_start_f425              AT-START-F425                         at32f425       https://www.arterychip.com/en/product/AT32F425.jsp
-at_start_f437              AT-START-F437                         at32f435_437   https://www.arterychip.com/en/product/AT32F437.jsp
-=========================  ====================================  =============  ====================================================  ======
+==============  ==============  =============  ==================================================  ======
+Board           Name            Family         URL                                                 Note
+==============  ==============  =============  ==================================================  ======
+at_start_f402   AT-START-F402   at32f402_405   https://www.arterychip.com/en/product/AT32F402.jsp
+at_start_f405   AT-START-F405   at32f402_405   https://www.arterychip.com/en/product/AT32F405.jsp
+at_start_f403a  AT-START-F403a  at32f403a_407  https://www.arterychip.com/en/product/AT32F403A.jsp
+at_start_f407   AT-START-F407   at32f403a_407  https://www.arterychip.com/en/product/AT32F407.jsp
+at_start_f413   AT-START-F413   at32f413       https://www.arterychip.com/en/product/AT32F413.jsp
+at_start_f415   AT-START-F415   at32f415       https://www.arterychip.com/en/product/AT32F415.jsp
+at_start_f423   AT-START-F423   at32f423       https://www.arterychip.com/en/product/AT32F423.jsp
+at_start_f425   AT-START-F425   at32f425       https://www.arterychip.com/en/product/AT32F425.jsp
+at_start_f435   AT-START-F435   at32f435_435   https://www.arterychip.com/en/product/AT32F435.jsp
+at_start_f437   AT-START-F437   at32f435_437   https://www.arterychip.com/en/product/AT32F437.jsp
+==============  ==============  =============  ==================================================  ======
 
 Bridgetek
 ---------
diff --git a/hw/bsp/at32f402_405/boards/at_start_f402/board.cmake b/hw/bsp/at32f402_405/boards/at_start_f402/board.cmake
new file mode 100644
index 000000000..4e7755c0f
--- /dev/null
+++ b/hw/bsp/at32f402_405/boards/at_start_f402/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT AT32F402RCT7)
+set(MCU_LINKER_NAME AT32F402xC)
+
+set(JLINK_DEVICE ${MCU_VARIANT})
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT})
+endfunction()
diff --git a/hw/bsp/at32f402_405/boards/at_start_f402/board.h b/hw/bsp/at32f402_405/boards/at_start_f402/board.h
new file mode 100644
index 000000000..b11b7a80f
--- /dev/null
+++ b/hw/bsp/at32f402_405/boards/at_start_f402/board.h
@@ -0,0 +1,74 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: AT-START-F405
+   url: https://www.arterychip.com/en/product/AT32F405.jsp
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define USB_VBUS_IGNORE
+//#define USB_SOF_OUTPUT_ENABLE
+
+// LED
+#define LED_PORT              GPIOF
+#define LED_PIN               GPIO_PINS_4
+#define LED_STATE_ON          0 // Active Low
+#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOF_PERIPH_CLOCK, TRUE)
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PINS_0
+#define BUTTON_STATE_ACTIVE   1
+#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
+
+//USART
+#define PRINT_UART                       USART1
+#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN                GPIO_PINS_9
+#define PRINT_UART_TX_GPIO               GPIOA
+#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN_SOURCE         GPIO_PINS_SOURCE9
+#define PRINT_UART_TX_PIN_MUX_NUM        GPIO_MUX_7
+
+//Vbus
+static inline void board_vbus_sense_init(void)
+{
+    *(int*)(0x50000038) |= (1<<21);
+    *(int*)(0x40040038) |= (1<<21);
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f402_405/boards/at_start_f402/board.mk b/hw/bsp/at32f402_405/boards/at_start_f402/board.mk
new file mode 100644
index 000000000..f1082247b
--- /dev/null
+++ b/hw/bsp/at32f402_405/boards/at_start_f402/board.mk
@@ -0,0 +1,7 @@
+MCU_VARIANT = AT32F402RCT7
+MCU_LINKER_NAME = AT32F402xC
+
+JLINK_DEVICE = ${MCU_VARIANT}
+
+CFLAGS += \
+  -D${MCU_VARIANT}
diff --git a/hw/bsp/at32f402_405/boards/at_start_f405/board.cmake b/hw/bsp/at32f402_405/boards/at_start_f405/board.cmake
index 0d09680a1..39c5cd905 100644
--- a/hw/bsp/at32f402_405/boards/at_start_f405/board.cmake
+++ b/hw/bsp/at32f402_405/boards/at_start_f405/board.cmake
@@ -3,6 +3,15 @@ set(MCU_LINKER_NAME AT32F405xC)
 
 set(JLINK_DEVICE ${MCU_VARIANT})
 
+set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED)
+
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 1)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif()
+
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT})
 endfunction()
diff --git a/hw/bsp/at32f402_405/boards/at_start_f405/board.h b/hw/bsp/at32f402_405/boards/at_start_f405/board.h
index 2d6cc3e57..b11b7a80f 100644
--- a/hw/bsp/at32f402_405/boards/at_start_f405/board.h
+++ b/hw/bsp/at32f402_405/boards/at_start_f405/board.h
@@ -48,7 +48,7 @@
 // Button
 #define BUTTON_PORT           GPIOA
 #define BUTTON_PIN            GPIO_PINS_0
-#define BUTTON_STATE_ACTIVE   0
+#define BUTTON_STATE_ACTIVE   1
 #define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
 
 //USART
@@ -60,111 +60,11 @@
 #define PRINT_UART_TX_PIN_SOURCE         GPIO_PINS_SOURCE9
 #define PRINT_UART_TX_PIN_MUX_NUM        GPIO_MUX_7
 
-//USB
-#ifdef BOARD_TUD_RHPORT
-    #if BOARD_TUD_RHPORT == 0
-        #define USB_ID                           USB_OTG1_ID
-        #define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
-        #define OTG_IRQ                          OTGFS1_IRQn
-        #define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
-        #define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
-        #define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
-        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
-        #define OTG_PIN_GPIO                     GPIOA
-        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_VBUS                     GPIO_PINS_9
-        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
-        #define OTG_PIN_ID                       GPIO_PINS_10
-        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
-        #define OTG_PIN_SOF_GPIO                 GPIOA
-        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_SOF                      GPIO_PINS_8
-        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
-        #define OTG_PIN_MUX                      GPIO_MUX_10
-        #define USB_SPEED_CORE_ID                USB_FULL_SPEED_CORE_ID
-    #elif BOARD_TUD_RHPORT == 1
-        #define USB_ID                           USB_OTG2_ID
-        #define OTG_CLOCK                        CRM_OTGHS_PERIPH_CLOCK
-        #define OTG_IRQ                          OTGHS_IRQn
-        #define OTG_IRQ_HANDLER                  OTGHS_IRQHandler
-        #define OTG_WKUP_IRQ                     OTGHS_WKUP_IRQn
-        #define OTG_WKUP_HANDLER                 OTGHS_WKUP_IRQHandler
-        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_20
-        #define OTG_PIN_GPIO                     GPIOB
-        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOB_PERIPH_CLOCK
-        #define OTG_PIN_VBUS                     GPIO_PINS_13
-        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE13
-        #define OTG_PIN_ID                       GPIO_PINS_12
-        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE12
-        #define OTG_PIN_SOF_GPIO                 GPIOA
-        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_SOF                      GPIO_PINS_4
-        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE4
-        #define OTG_PIN_MUX                      GPIO_MUX_10
-        #define USB_SPEED_CORE_ID                USB_HIGH_SPEED_CORE_ID
-    #endif
-#endif
-#ifdef BOARD_TUH_RHPORT
-    #if BOARD_TUH_RHPORT == 0
-        #define USB_ID                           USB_OTG1_ID
-        #define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
-        #define OTG_IRQ                          OTGFS1_IRQn
-        #define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
-        #define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
-        #define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
-        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
-        #define OTG_PIN_GPIO                     GPIOA
-        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_VBUS                     GPIO_PINS_9
-        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
-        #define OTG_PIN_ID                       GPIO_PINS_10
-        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
-        #define OTG_PIN_SOF_GPIO                 GPIOA
-        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_SOF                      GPIO_PINS_8
-        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
-        #define OTG_PIN_MUX                      GPIO_MUX_10
-        #define USB_SPEED_CORE_ID                USB_FULL_SPEED_CORE_ID
-    #elif BOARD_TUH_RHPORT == 1
-        #define USB_ID                           USB_OTG2_ID
-        #define OTG_CLOCK                        CRM_OTGHS_PERIPH_CLOCK
-        #define OTG_IRQ                          OTGHS_IRQn
-        #define OTG_IRQ_HANDLER                  OTGHS_IRQHandler
-        #define OTG_WKUP_IRQ                     OTGHS_WKUP_IRQn
-        #define OTG_WKUP_HANDLER                 OTGHS_WKUP_IRQHandler
-        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_20
-        #define OTG_PIN_GPIO                     GPIOB
-        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOB_PERIPH_CLOCK
-        #define OTG_PIN_VBUS                     GPIO_PINS_13
-        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE13
-        #define OTG_PIN_ID                       GPIO_PINS_12
-        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE12
-        #define OTG_PIN_SOF_GPIO                 GPIOA
-        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_SOF                      GPIO_PINS_4
-        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE4
-        #define OTG_PIN_MUX                      GPIO_MUX_10
-        #define USB_SPEED_CORE_ID                USB_HIGH_SPEED_CORE_ID
-    #endif
-#endif
-
 //Vbus
 static inline void board_vbus_sense_init(void)
 {
-    #ifdef BOARD_TUD_RHPORT
-        #if BOARD_TUD_RHPORT == 0
-            *(int*)(0x50000038) |= (1<<21);
-        #elif BOARD_TUD_RHPORT == 1
-            *(int*)(0x40040038) |= (1<<21);
-        #endif
-    #endif
-    #ifdef BOARD_TUH_RHPORT
-        #if BOARD_TUH_RHPORT == 0
-            *(int*)(0x50000038) |= (1<<21);
-        #elif BOARD_TUH_RHPORT == 1
-            *(int*)(0x40040038) |= (1<<21);
-        #endif
-    #endif
+    *(int*)(0x50000038) |= (1<<21);
+    *(int*)(0x40040038) |= (1<<21);
 }
 
 #ifdef __cplusplus
diff --git a/hw/bsp/at32f402_405/boards/at_start_f405/board.mk b/hw/bsp/at32f402_405/boards/at_start_f405/board.mk
index 25a719ccf..b4d55ca8f 100644
--- a/hw/bsp/at32f402_405/boards/at_start_f405/board.mk
+++ b/hw/bsp/at32f402_405/boards/at_start_f405/board.mk
@@ -3,5 +3,9 @@ MCU_LINKER_NAME = AT32F405xC
 
 JLINK_DEVICE = ${MCU_VARIANT}
 
+RHPORT_SPEED = OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED
+RHPORT_DEVICE ?= 1
+RHPORT_HOST ?= 0
+
 CFLAGS += \
   -D${MCU_VARIANT}
diff --git a/hw/bsp/at32f402_405/family.c b/hw/bsp/at32f402_405/family.c
index 7d94f2564..6b69c0157 100644
--- a/hw/bsp/at32f402_405/family.c
+++ b/hw/bsp/at32f402_405/family.c
@@ -66,10 +66,11 @@ void board_init(void)
   system_clock_config();
 
   /* config usb io*/
-  usb_gpio_config();
+  //usb_gpio_config();
 
   /* enable usb clock */
-  crm_periph_clock_enable(OTG_CLOCK, TRUE);
+  crm_periph_clock_enable(CRM_OTGFS1_PERIPH_CLOCK, TRUE);
+  crm_periph_clock_enable(CRM_OTGHS_PERIPH_CLOCK, TRUE);
 
   /* select usb 48m clcok source */
   usb_clock48m_select(USB_CLK_HEXT);
@@ -82,9 +83,11 @@ void board_init(void)
 
   #if CFG_TUSB_OS == OPT_OS_FREERTOS
     // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-    NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+    NVIC_SetPriority(OTGHS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+    NVIC_SetPriority(OTGFS1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
   #else
-    NVIC_SetPriority(OTG_IRQ, 0);
+    NVIC_SetPriority(OTGHS_IRQn, 0);
+    NVIC_SetPriority(OTGFS1_IRQn, 0);
   #endif
 
   /* config led and key */
@@ -160,26 +163,7 @@ void usb_clock48m_select(usb_clk48_s clk_s)
 
 void usb_gpio_config(void)
 {
-  gpio_init_type gpio_init_struct;
-  crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE);
-  gpio_default_para_init(&gpio_init_struct);
-  gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
-  gpio_init_struct.gpio_out_type  = GPIO_OUTPUT_PUSH_PULL;
-  gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
-  gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
-  #ifdef USB_SOF_OUTPUT_ENABLE
-    crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE);
-    gpio_init_struct.gpio_pins = OTG_PIN_SOF;
-    gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct);
-    gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX);
-  #endif
-  /* otgfs use vbus pin */
-  #ifndef USB_VBUS_IGNORE
-    gpio_init_struct.gpio_pins = OTG_PIN_VBUS;
-    gpio_init_struct.gpio_pull = GPIO_PULL_DOWN;
-    gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX);
-    gpio_init(OTG_PIN_GPIO, &gpio_init_struct);
-  #endif
+  /*if needed*/
 }
 
 /**
diff --git a/hw/bsp/at32f402_405/family.cmake b/hw/bsp/at32f402_405/family.cmake
index 010e36b88..b10760cef 100644
--- a/hw/bsp/at32f402_405/family.cmake
+++ b/hw/bsp/at32f402_405/family.cmake
@@ -14,6 +14,23 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL
 
 set(FAMILY_MCUS ${AT32_FAMILY_UPPER} CACHE INTERNAL "")
 
+if (NOT DEFINED RHPORT_DEVICE)
+  set(RHPORT_DEVICE 0)
+endif ()
+if (NOT DEFINED RHPORT_HOST)
+  set(RHPORT_HOST 0)
+endif ()
+
+if (NOT DEFINED RHPORT_SPEED)
+  set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_FULL_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_DEVICE_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_HOST_SPEED)
+  list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED)
+endif ()
+
 #------------------------------------
 # BOARD_TARGET
 #------------------------------------
@@ -50,8 +67,10 @@ function(add_board_target BOARD_TARGET)
     ${AT32_SDK_LIB}/drivers/inc
     )
   target_compile_definitions(${BOARD_TARGET} PUBLIC
-    BOARD_TUD_RHPORT=0
-    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+    BOARD_TUD_RHPORT=${RHPORT_DEVICE}
+    BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
+    BOARD_TUH_RHPORT=${RHPORT_HOST}
+    BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
     )
 
   update_board(${BOARD_TARGET})
diff --git a/hw/bsp/at32f402_405/family.mk b/hw/bsp/at32f402_405/family.mk
index 60a0f93e9..09b2f1139 100644
--- a/hw/bsp/at32f402_405/family.mk
+++ b/hw/bsp/at32f402_405/family.mk
@@ -8,10 +8,32 @@ CPU_CORE ?= cortex-m4
 CFLAGS_GCC += \
   -flto
 
+RHPORT_SPEED ?= OPT_MODE_FULL_SPEED OPT_MODE_FULL_SPEED
+RHPORT_DEVICE ?= 0
+RHPORT_HOST ?= 0
+
+ifndef RHPORT_DEVICE_SPEED
+ifeq ($(RHPORT_DEVICE), 0)
+  RHPORT_DEVICE_SPEED = $(firstword $(RHPORT_SPEED))
+else
+  RHPORT_DEVICE_SPEED = $(lastword $(RHPORT_SPEED))
+endif
+endif
+
+ifndef RHPORT_HOST_SPEED
+ifeq ($(RHPORT_HOST), 0)
+  RHPORT_HOST_SPEED = $(firstword $(RHPORT_SPEED))
+else
+  RHPORT_HOST_SPEED = $(lastword $(RHPORT_SPEED))
+endif
+endif
+
 CFLAGS += \
-	-DCFG_TUSB_MCU=OPT_MCU_AT32F402_405 \
-	-DBOARD_TUD_RHPORT=0 \
-	-DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+    -DCFG_TUSB_MCU=OPT_MCU_AT32F402_405 \
+	-DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \
+	-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
+	-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
+	-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
 
 LDFLAGS_GCC += \
 	-flto --specs=nosys.specs -nostdlib -nostartfiles
diff --git a/hw/bsp/at32f403a_407/boards/at_start_f403a/board.cmake b/hw/bsp/at32f403a_407/boards/at_start_f403a/board.cmake
index 25c9558f9..ce26fd244 100644
--- a/hw/bsp/at32f403a_407/boards/at_start_f403a/board.cmake
+++ b/hw/bsp/at32f403a_407/boards/at_start_f403a/board.cmake
@@ -1,4 +1,4 @@
-set(MCU_VARIANT AT32F403ACGU7)
+set(MCU_VARIANT AT32F403AVGT7)
 set(MCU_LINKER_NAME AT32F403AxG)
 
 set(JLINK_DEVICE ${MCU_VARIANT})
diff --git a/hw/bsp/at32f403a_407/boards/at_start_f403a/board.mk b/hw/bsp/at32f403a_407/boards/at_start_f403a/board.mk
index 9bb6843aa..d9f360360 100644
--- a/hw/bsp/at32f403a_407/boards/at_start_f403a/board.mk
+++ b/hw/bsp/at32f403a_407/boards/at_start_f403a/board.mk
@@ -1,4 +1,4 @@
-MCU_VARIANT = AT32F403ACGU7
+MCU_VARIANT = AT32F403AVGT7
 MCU_LINKER_NAME = AT32F403AxG
 
 JLINK_DEVICE = ${MCU_VARIANT}
diff --git a/hw/bsp/at32f403a_407/boards/at_start_f407/board.cmake b/hw/bsp/at32f403a_407/boards/at_start_f407/board.cmake
new file mode 100644
index 000000000..f76c46f21
--- /dev/null
+++ b/hw/bsp/at32f403a_407/boards/at_start_f407/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT AT32F407VGT7)
+set(MCU_LINKER_NAME AT32F407xG)
+
+set(JLINK_DEVICE ${MCU_VARIANT})
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT})
+endfunction()
diff --git a/hw/bsp/at32f403a_407/boards/at_start_f407/board.h b/hw/bsp/at32f403a_407/boards/at_start_f407/board.h
new file mode 100644
index 000000000..753fece10
--- /dev/null
+++ b/hw/bsp/at32f403a_407/boards/at_start_f407/board.h
@@ -0,0 +1,71 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: AT-START-F403a
+   url: https://www.arterychip.com/en/product/AT32F403.jsp
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOD
+#define LED_PIN               GPIO_PINS_13
+#define LED_STATE_ON          0 // Active Low
+#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE)
+
+// #define LED_PORT              GPIOA
+// #define LED_PIN               GPIO_PINS_1
+// #define LED_STATE_ON          0 // Active Low
+// #define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PINS_0
+#define BUTTON_STATE_ACTIVE   1
+#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
+
+// UART
+#define PRINT_UART                       USART1
+#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN                GPIO_PINS_9
+#define PRINT_UART_TX_GPIO               GPIOA
+#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
+
+static inline void board_vbus_sense_init(void)
+{
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f403a_407/boards/at_start_f407/board.mk b/hw/bsp/at32f403a_407/boards/at_start_f407/board.mk
new file mode 100644
index 000000000..714cbaec2
--- /dev/null
+++ b/hw/bsp/at32f403a_407/boards/at_start_f407/board.mk
@@ -0,0 +1,7 @@
+MCU_VARIANT = AT32F407VGT7
+MCU_LINKER_NAME = AT32F407xG
+
+JLINK_DEVICE = ${MCU_VARIANT}
+
+CFLAGS += \
+  -D${MCU_VARIANT}
diff --git a/hw/bsp/at32f403a_407/family.c b/hw/bsp/at32f403a_407/family.c
index afd3a24d1..8c8329323 100644
--- a/hw/bsp/at32f403a_407/family.c
+++ b/hw/bsp/at32f403a_407/family.c
@@ -29,8 +29,8 @@
 */
 
 #include "at32f403a_407_clock.h"
-#include "board.h"
 #include "bsp/board_api.h"
+#include "board.h"
 
 void usb_clock48m_select(usb_clk48_s clk_s);
 void uart_print_init(uint32_t baudrate);
@@ -102,7 +102,7 @@ void board_init(void) {
   gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
   gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT;
   gpio_button_init_struct.gpio_pins = BUTTON_PIN;
-  gpio_button_init_struct.gpio_pull = BUTTON_PULL;
+  gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN;
   gpio_init(BUTTON_PORT, &gpio_button_init_struct);
 
   uart_print_init(115200);
diff --git a/hw/bsp/at32f413/boards/at_start_f413/board.h b/hw/bsp/at32f413/boards/at_start_f413/board.h
index 4b386a2f4..290400658 100644
--- a/hw/bsp/at32f413/boards/at_start_f413/board.h
+++ b/hw/bsp/at32f413/boards/at_start_f413/board.h
@@ -45,7 +45,7 @@
 // Button
 #define BUTTON_PORT           GPIOA
 #define BUTTON_PIN            GPIO_PINS_0
-#define BUTTON_STATE_ACTIVE   0
+#define BUTTON_STATE_ACTIVE   1
 #define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
 
 // UART
diff --git a/hw/bsp/at32f415/boards/at_start_f415/board.h b/hw/bsp/at32f415/boards/at_start_f415/board.h
index 0464d383e..b3c2c1aea 100644
--- a/hw/bsp/at32f415/boards/at_start_f415/board.h
+++ b/hw/bsp/at32f415/boards/at_start_f415/board.h
@@ -47,7 +47,7 @@
 // Button
 #define BUTTON_PORT           GPIOA
 #define BUTTON_PIN            GPIO_PINS_0
-#define BUTTON_STATE_ACTIVE   0
+#define BUTTON_STATE_ACTIVE   1
 #define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
 
 // Usart
diff --git a/hw/bsp/at32f423/boards/at_start_f423/board.h b/hw/bsp/at32f423/boards/at_start_f423/board.h
index ef85b4977..24def1ee7 100644
--- a/hw/bsp/at32f423/boards/at_start_f423/board.h
+++ b/hw/bsp/at32f423/boards/at_start_f423/board.h
@@ -47,7 +47,7 @@
 // Button
 #define BUTTON_PORT           GPIOA
 #define BUTTON_PIN            GPIO_PINS_0
-#define BUTTON_STATE_ACTIVE   0
+#define BUTTON_STATE_ACTIVE   1
 #define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
 
 // UART
diff --git a/hw/bsp/at32f425/boards/at_start_f425/board.h b/hw/bsp/at32f425/boards/at_start_f425/board.h
index 145eab3b9..2a4d98237 100644
--- a/hw/bsp/at32f425/boards/at_start_f425/board.h
+++ b/hw/bsp/at32f425/boards/at_start_f425/board.h
@@ -47,7 +47,7 @@
 // Button
 #define BUTTON_PORT           GPIOA
 #define BUTTON_PIN            GPIO_PINS_0
-#define BUTTON_STATE_ACTIVE   0
+#define BUTTON_STATE_ACTIVE   1
 #define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
 
 // Usart
diff --git a/hw/bsp/at32f435_437/boards/at_start_f435/board.cmake b/hw/bsp/at32f435_437/boards/at_start_f435/board.cmake
new file mode 100644
index 000000000..6d9024f4f
--- /dev/null
+++ b/hw/bsp/at32f435_437/boards/at_start_f435/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT AT32F435ZMT7)
+set(MCU_LINKER_NAME AT32F435xM)
+
+set(JLINK_DEVICE ${MCU_VARIANT})
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT})
+endfunction()
diff --git a/hw/bsp/at32f435_437/boards/at_start_f435/board.h b/hw/bsp/at32f435_437/boards/at_start_f435/board.h
new file mode 100644
index 000000000..3522e759a
--- /dev/null
+++ b/hw/bsp/at32f435_437/boards/at_start_f435/board.h
@@ -0,0 +1,74 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* metadata:
+   name: AT-START-F437
+   url: https://www.arterychip.com/en/product/AT32F437.jsp
+*/
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//#define USB_VBUS_IGNORE
+//#define USB_SOF_OUTPUT_ENABLE
+
+// LED
+#define LED_PORT              GPIOD
+#define LED_PIN               GPIO_PINS_13
+#define LED_STATE_ON          0 // Active Low
+#define LED_GPIO_CLK_EN()     crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE)
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PINS_0
+#define BUTTON_STATE_ACTIVE   1
+#define BUTTON_GPIO_CLK_EN()  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE)
+
+// USART
+#define PRINT_UART                       USART1
+#define PRINT_UART_CRM_CLK               CRM_USART1_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN                GPIO_PINS_9
+#define PRINT_UART_TX_GPIO               GPIOA
+#define PRINT_UART_TX_GPIO_CRM_CLK       CRM_GPIOA_PERIPH_CLOCK
+#define PRINT_UART_TX_PIN_SOURCE         GPIO_PINS_SOURCE9
+#define PRINT_UART_TX_PIN_MUX_NUM        GPIO_MUX_7
+
+// VBUS
+static inline void board_vbus_sense_init(void)
+{
+    *(int*)(0x50000038) |= (1<<21);
+    *(int*)(0x40040038) |= (1<<21);
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/at32f435_437/boards/at_start_f435/board.mk b/hw/bsp/at32f435_437/boards/at_start_f435/board.mk
new file mode 100644
index 000000000..5fe56ce77
--- /dev/null
+++ b/hw/bsp/at32f435_437/boards/at_start_f435/board.mk
@@ -0,0 +1,7 @@
+MCU_VARIANT = AT32F435ZMT7
+MCU_LINKER_NAME = AT32F435xM
+
+JLINK_DEVICE = ${MCU_VARIANT}
+
+CFLAGS += \
+  -D${MCU_VARIANT}
diff --git a/hw/bsp/at32f435_437/boards/at_start_f437/board.h b/hw/bsp/at32f435_437/boards/at_start_f437/board.h
index b6de119bc..3522e759a 100644
--- a/hw/bsp/at32f435_437/boards/at_start_f437/board.h
+++ b/hw/bsp/at32f435_437/boards/at_start_f437/board.h
@@ -60,124 +60,11 @@
 #define PRINT_UART_TX_PIN_SOURCE         GPIO_PINS_SOURCE9
 #define PRINT_UART_TX_PIN_MUX_NUM        GPIO_MUX_7
 
-// USB
-#ifdef BOARD_TUD_RHPORT
-    #if BOARD_TUD_RHPORT == 0
-        #define USB_ID                           0
-        #define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
-        #define OTG_IRQ                          OTGFS1_IRQn
-        #define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
-        #define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
-        #define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
-        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
-        #define OTG_PIN_GPIO                     GPIOA
-        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_DP                       GPIO_PINS_12
-        #define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE12
-        #define OTG_PIN_DM                       GPIO_PINS_11
-        #define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE11
-        #define OTG_PIN_VBUS                     GPIO_PINS_9
-        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
-        #define OTG_PIN_ID                       GPIO_PINS_10
-        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE12
-        #define OTG_PIN_SOF_GPIO                 GPIOA
-        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_SOF                      GPIO_PINS_8
-        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
-        #define OTG_PIN_MUX                      GPIO_MUX_10
-    #elif BOARD_TUD_RHPORT == 1
-        #define USB_ID                           1
-        #define OTG_CLOCK                        CRM_OTGFS2_PERIPH_CLOCK
-        #define OTG_IRQ                          OTGFS2_IRQn
-        #define OTG_IRQ_HANDLER                  OTGFS2_IRQHandler
-        #define OTG_WKUP_IRQ                     OTGFS2_WKUP_IRQn
-        #define OTG_WKUP_HANDLER                 OTGFS2_WKUP_IRQHandler
-        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_20
-        #define OTG_PIN_GPIO                     GPIOB
-        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOB_PERIPH_CLOCK
-        #define OTG_PIN_DP                       GPIO_PINS_15
-        #define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE15
-        #define OTG_PIN_DM                       GPIO_PINS_14
-        #define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE14
-        #define OTG_PIN_VBUS                     GPIO_PINS_13
-        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE13
-        #define OTG_PIN_ID                       GPIO_PINS_12
-        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
-        #define OTG_PIN_SOF_GPIO                 GPIOA
-        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_SOF                      GPIO_PINS_4
-        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE4
-        #define OTG_PIN_MUX                      GPIO_MUX_12
-    #endif
-#endif
-
-#ifdef BOARD_TUH_RHPORT
-    #if BOARD_TUH_RHPORT == 0
-        #define USB_ID                           0
-        #define OTG_CLOCK                        CRM_OTGFS1_PERIPH_CLOCK
-        #define OTG_IRQ                          OTGFS1_IRQn
-        #define OTG_IRQ_HANDLER                  OTGFS1_IRQHandler
-        #define OTG_WKUP_IRQ                     OTGFS1_WKUP_IRQn
-        #define OTG_WKUP_HANDLER                 OTGFS1_WKUP_IRQHandler
-        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_18
-        #define OTG_PIN_GPIO                     GPIOA
-        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_DP                       GPIO_PINS_12
-        #define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE12
-        #define OTG_PIN_DM                       GPIO_PINS_11
-        #define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE11
-        #define OTG_PIN_VBUS                     GPIO_PINS_9
-        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE9
-        #define OTG_PIN_ID                       GPIO_PINS_10
-        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE12
-        #define OTG_PIN_SOF_GPIO                 GPIOA
-        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_SOF                      GPIO_PINS_8
-        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE8
-        #define OTG_PIN_MUX                      GPIO_MUX_10
-    #elif BOARD_TUH_RHPORT == 1
-        #define USB_ID                           1
-        #define OTG_CLOCK                        CRM_OTGFS2_PERIPH_CLOCK
-        #define OTG_IRQ                          OTGFS2_IRQn
-        #define OTG_IRQ_HANDLER                  OTGFS2_IRQHandler
-        #define OTG_WKUP_IRQ                     OTGFS2_WKUP_IRQn
-        #define OTG_WKUP_HANDLER                 OTGFS2_WKUP_IRQHandler
-        #define OTG_WKUP_EXINT_LINE              EXINT_LINE_20
-        #define OTG_PIN_GPIO                     GPIOB
-        #define OTG_PIN_GPIO_CLOCK               CRM_GPIOB_PERIPH_CLOCK
-        #define OTG_PIN_DP                       GPIO_PINS_15
-        #define OTG_PIN_DP_SOURCE                GPIO_PINS_SOURCE15
-        #define OTG_PIN_DM                       GPIO_PINS_14
-        #define OTG_PIN_DM_SOURCE                GPIO_PINS_SOURCE14
-        #define OTG_PIN_VBUS                     GPIO_PINS_13
-        #define OTG_PIN_VBUS_SOURCE              GPIO_PINS_SOURCE13
-        #define OTG_PIN_ID                       GPIO_PINS_12
-        #define OTG_PIN_ID_SOURCE                GPIO_PINS_SOURCE10
-        #define OTG_PIN_SOF_GPIO                 GPIOA
-        #define OTG_PIN_SOF_GPIO_CLOCK           CRM_GPIOA_PERIPH_CLOCK
-        #define OTG_PIN_SOF                      GPIO_PINS_4
-        #define OTG_PIN_SOF_SOURCE               GPIO_PINS_SOURCE4
-        #define OTG_PIN_MUX                      GPIO_MUX_12
-    #endif
-#endif
-
 // VBUS
 static inline void board_vbus_sense_init(void)
 {
-    #ifdef BOARD_TUD_RHPORT
-        #if BOARD_TUD_RHPORT == 0
-            *(int*)(0x50000038) |= (1<<21);
-        #elif BOARD_TUD_RHPORT == 1
-            *(int*)(0x40040038) |= (1<<21);
-        #endif
-    #endif
-    #ifdef BOARD_TUH_RHPORT
-        #if BOARD_TUH_RHPORT == 0
-            *(int*)(0x50000038) |= (1<<21);
-        #elif BOARD_TUH_RHPORT == 1
-            *(int*)(0x40040038) |= (1<<21);
-        #endif
-    #endif
+    *(int*)(0x50000038) |= (1<<21);
+    *(int*)(0x40040038) |= (1<<21);
 }
 
 #ifdef __cplusplus
diff --git a/hw/bsp/at32f435_437/family.c b/hw/bsp/at32f435_437/family.c
index 702fdd2a8..a65116729 100644
--- a/hw/bsp/at32f435_437/family.c
+++ b/hw/bsp/at32f435_437/family.c
@@ -64,21 +64,23 @@ void board_init(void) {
   usb_gpio_config();
 
   /* enable usb clock */
-  crm_periph_clock_enable(OTG_CLOCK, TRUE);
+  crm_periph_clock_enable(CRM_OTGFS1_PERIPH_CLOCK, TRUE);
+  crm_periph_clock_enable(CRM_OTGFS2_PERIPH_CLOCK, TRUE);
 
   /* select usb 48m clcok source */
   usb_clock48m_select(USB_CLK_HEXT);
 
-  /* enable otgfs irq */
-  //nvic_irq_enable(OTG_IRQ, 0, 0);
-
   /* vbus ignore */
   board_vbus_sense_init();
 
   SysTick_Config(SystemCoreClock / 1000);
 #if CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(OTGFS1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(OTGFS2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#else
+  NVIC_SetPriority(OTGFS1_IRQn, 0);
+  NVIC_SetPriority(OTGFS2_IRQn, 0);
 #endif
 
   /* config led and key */
@@ -271,30 +273,22 @@ int inHandlerMode(void) {
 
 void usb_gpio_config(void) {
   gpio_init_type gpio_init_struct;
-  crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE);
+  crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
+  crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
   gpio_default_para_init(&gpio_init_struct);
   gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
   gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
   gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
   gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
   /* dp and dm */
-  gpio_init_struct.gpio_pins = OTG_PIN_DP | OTG_PIN_DM;
-  gpio_init(OTG_PIN_GPIO, &gpio_init_struct);
-  gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_DP_SOURCE, OTG_PIN_MUX);
-  gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_DM_SOURCE, OTG_PIN_MUX);
-#ifdef USB_SOF_OUTPUT_ENABLE
-  crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE);
-  gpio_init_struct.gpio_pins = OTG_PIN_SOF;
-  gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct);
-  gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX);
-#endif
-  /* otgfs use vbus pin */
-#ifndef USB_VBUS_IGNORE
-  gpio_init_struct.gpio_pins = OTG_PIN_VBUS;
-  gpio_init_struct.gpio_pull = GPIO_PULL_DOWN;
-  gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX);
-  gpio_init(OTG_PIN_GPIO, &gpio_init_struct);
-#endif
+  gpio_init_struct.gpio_pins = GPIO_PINS_11 | GPIO_PINS_12;
+  gpio_init(GPIOA, &gpio_init_struct);
+  gpio_init_struct.gpio_pins = GPIO_PINS_14 | GPIO_PINS_15;
+  gpio_init(GPIOB, &gpio_init_struct);
+  gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE11, GPIO_MUX_10);
+  gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE12, GPIO_MUX_10);
+  gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE14, GPIO_MUX_12);
+  gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE15, GPIO_MUX_12);
 }
 
 void board_led_write(bool state) {
diff --git a/hw/bsp/at32f435_437/family.cmake b/hw/bsp/at32f435_437/family.cmake
index c85b58ae4..7bb38eb2f 100644
--- a/hw/bsp/at32f435_437/family.cmake
+++ b/hw/bsp/at32f435_437/family.cmake
@@ -51,9 +51,12 @@ function(add_board_target BOARD_TARGET)
     ${AT32_SDK_LIB}/drivers/inc
     )
   target_compile_definitions(${BOARD_TARGET} PUBLIC
-    BOARD_TUD_RHPORT=0
+    BOARD_TUD_RHPORT=1
+    BOARD_TUH_RHPORT=0
+    BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+    BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED
     )
-
+    
   update_board(${BOARD_TARGET})
 
   if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
diff --git a/hw/bsp/at32f435_437/family.mk b/hw/bsp/at32f435_437/family.mk
index b33be1180..ba22f5420 100644
--- a/hw/bsp/at32f435_437/family.mk
+++ b/hw/bsp/at32f435_437/family.mk
@@ -10,7 +10,10 @@ CFLAGS_GCC += \
 
 CFLAGS += \
 	-DCFG_TUSB_MCU=OPT_MCU_AT32F435_437 \
-	-DBOARD_TUD_RHPORT=0
+	-DBOARD_TUD_RHPORT=1 \
+	-DBOARD_TUH_RHPORT=0 \
+	-DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED \
+	-DBOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED \
 
 LDFLAGS_GCC += \
 	-flto --specs=nosys.specs -nostdlib -nostartfiles
-- 
cgit v1.3.1


From 3b983cb3e97e55c38959b7cf92c8fd65ca118095 Mon Sep 17 00:00:00 2001
From: zhiqiang <zhiqiangyou@arterytek.com>
Date: Fri, 5 Sep 2025 09:57:38 +0800
Subject: the family name error of at32 has been corrected

---
 docs/reference/boards.rst    | 2 +-
 hw/bsp/at32f402_405/family.c | 6 +++++-
 2 files changed, 6 insertions(+), 2 deletions(-)

(limited to 'docs/reference')

diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst
index d984b3529..a8d73de5f 100644
--- a/docs/reference/boards.rst
+++ b/docs/reference/boards.rst
@@ -41,7 +41,7 @@ at_start_f413   AT-START-F413   at32f413       https://www.arterychip.com/en/pro
 at_start_f415   AT-START-F415   at32f415       https://www.arterychip.com/en/product/AT32F415.jsp
 at_start_f423   AT-START-F423   at32f423       https://www.arterychip.com/en/product/AT32F423.jsp
 at_start_f425   AT-START-F425   at32f425       https://www.arterychip.com/en/product/AT32F425.jsp
-at_start_f435   AT-START-F435   at32f435_435   https://www.arterychip.com/en/product/AT32F435.jsp
+at_start_f435   AT-START-F435   at32f435_437   https://www.arterychip.com/en/product/AT32F435.jsp
 at_start_f437   AT-START-F437   at32f435_437   https://www.arterychip.com/en/product/AT32F437.jsp
 ==============  ==============  =============  ==================================================  ======
 
diff --git a/hw/bsp/at32f402_405/family.c b/hw/bsp/at32f402_405/family.c
index 6b69c0157..cb5987cd4 100644
--- a/hw/bsp/at32f402_405/family.c
+++ b/hw/bsp/at32f402_405/family.c
@@ -163,7 +163,11 @@ void usb_clock48m_select(usb_clk48_s clk_s)
 
 void usb_gpio_config(void)
 {
-  /*if needed*/
+  /* When the USB clock is enabled, the hardware will automatically
+  configure the pins; but other special pins that need to be used,
+  such as the pins used to detect VBUS or the pins that output the
+  SOF signal, still need to be configured separately, and these pins
+  are usually not required */
 }
 
 /**
-- 
cgit v1.3.1


From 19f67ffc22bcf9a59125b0f992bf6e8ee9819eec Mon Sep 17 00:00:00 2001
From: Dalton Caron <dcaron@anduril.com>
Date: Tue, 9 Sep 2025 14:09:26 -0700
Subject: Initial STM32WBARI eval support

Clean up includes definitions

Remove wait that is not required

Remove redundant settings

Clean up clock configuration to look like other modules

Remove MSP_Init that is not required

Clean up driver code

dhcp: Fix DHCP_OFFER/DHCP_ACK destinaton.

In RFC 2131, the destination of DHCP OFFER/ACK is defined in Section 4.1.
Fix the destination error by following the rule of RFC 2131.
TODO: We implement all rule but the last one. ARP table is required to associate client's macaddr.
Currently, fallback to broadcast.

Signed-off-by: Elwin Huang <s09289728096@gmail.com>

Fix compile error.

Fix goto indentation

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>

Fix osal_spin_unlock for mynewt

Mynewt version for osal_spin_unlock() called
OS_ENTER_CRITICAL instead of OS_EXIT_CRITICAL.

Signed-off-by: Jerzy Kasenberg <jerzy@apache.org>

Add ESP32-C5 and ESP32-C61 definitions

fix(dcd/dwc2): Fix reset procedure for versions >=4.20a

Fix STM32L4 GPIOD clock enable for variants without GPIOD

Add weact blackpill support

Add to boards.rst file

Fix file

Small cleanups.

Insert small delay for LowSpeed device

Improve retry operation at NAK response.

Remove dynamic memory allocation

use tusb_time_millis_api() instead of board_millis()
make loopdelay() always inline

update at32f405 dwc2 info and phy width selection

add at32f415 dwc2 info

add some consumer page configs

remove duplicated enum

Initial plan

Fix obsolete cnt assignment in _tu_fifo_peek() overflow check

Co-authored-by: hathach <249515+hathach@users.noreply.github.com>

Initial plan

Update STM32 CMSIS dependencies to fix HSITRIM register bug

Co-authored-by: hathach <249515+hathach@users.noreply.github.com>

Remove accidentally committed dependency directories

Co-authored-by: hathach <249515+hathach@users.noreply.github.com>

Update all STM32 HAL driver dependencies to latest versions

Co-authored-by: hathach <249515+hathach@users.noreply.github.com>

fix linker h745 issue with clang

fix linker h745 issue with clang

Update all STM32 CMSIS device dependencies to latest versions

Co-authored-by: hathach <249515+hathach@users.noreply.github.com>

update pio-usb

Create comprehensive GitHub Copilot instructions and fix pre-commit configuration for TinyUSB (#3234)

* Initial plan

* Create comprehensive GitHub Copilot instructions for TinyUSB

Co-authored-by: hathach <249515+hathach@users.noreply.github.com>

* Remove accidentally committed dependencies, use tools/get_deps.py instead

Co-authored-by: hathach <249515+hathach@users.noreply.github.com>

* Fix .gitignore: ignore vendor/ directory not ceedling script

Co-authored-by: hathach <249515+hathach@users.noreply.github.com>

* Revert .gitignore changes and add README_processed.rst

Co-authored-by: hathach <249515+hathach@users.noreply.github.com>

* Remove README_processed.rst and revert ceedling file permissions

Co-authored-by: hathach <249515+hathach@users.noreply.github.com>

* Changes before error encountered

Co-authored-by: hathach <249515+hathach@users.noreply.github.com>

* Remove redundant manual validation step, keep only pre-commit and build validation

Co-authored-by: hathach <249515+hathach@users.noreply.github.com>

* fix pre-commit

---------

Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com>
Co-authored-by: hathach <249515+hathach@users.noreply.github.com>

modified the bsp files of at32 to make them work better

the family name error of at32 has been corrected

fix pre-commit

STM32N6570-DK board is added. Build with DEBUG=1 (make BOARD=stm32n6570dk DEBUG=1 all), otherwise it does not work for now. Tested with examples/device/cdc_dual_ports
---
 docs/reference/boards.rst                          |   1 +
 docs/reference/dependencies.rst                    |   1 +
 hw/bsp/stm32wba/FreeRTOSConfig/FreeRTOSConfig.h    | 153 +++++++++
 hw/bsp/stm32wba/boards/stm32wba_eval/board.cmake   |  10 +
 hw/bsp/stm32wba/boards/stm32wba_eval/board.h       | 136 ++++++++
 hw/bsp/stm32wba/boards/stm32wba_eval/board.mk      |   6 +
 .../stm32wba_eval/include/stm32wbaxx_hal_conf.h    | 368 +++++++++++++++++++++
 hw/bsp/stm32wba/family.c                           | 233 +++++++++++++
 hw/bsp/stm32wba/family.mk                          |  59 ++++
 hw/bsp/stm32wba/stm32wbaxx_hal_conf.h              | 367 ++++++++++++++++++++
 src/common/tusb_mcu.h                              |   6 +
 src/portable/st/stm32_fsdev/fsdev_stm32.h          |   8 +
 src/portable/synopsys/dwc2/dwc2_common.c           |   5 +
 src/portable/synopsys/dwc2/dwc2_stm32.h            |  23 +-
 src/tusb_option.h                                  |   1 +
 tools/get_deps.py                                  |   6 +
 16 files changed, 1381 insertions(+), 2 deletions(-)
 create mode 100644 hw/bsp/stm32wba/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/stm32wba/boards/stm32wba_eval/board.cmake
 create mode 100644 hw/bsp/stm32wba/boards/stm32wba_eval/board.h
 create mode 100644 hw/bsp/stm32wba/boards/stm32wba_eval/board.mk
 create mode 100644 hw/bsp/stm32wba/boards/stm32wba_eval/include/stm32wbaxx_hal_conf.h
 create mode 100644 hw/bsp/stm32wba/family.c
 create mode 100644 hw/bsp/stm32wba/family.mk
 create mode 100644 hw/bsp/stm32wba/stm32wbaxx_hal_conf.h

(limited to 'docs/reference')

diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst
index 71dca8e94..a930f485b 100644
--- a/docs/reference/boards.rst
+++ b/docs/reference/boards.rst
@@ -303,6 +303,7 @@ stm32u575eval        STM32 U575 Eval                    stm32u5    https://www.s
 stm32u575nucleo      STM32 U575 Nucleo                  stm32u5    https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html
 stm32u5a5nucleo      STM32 U5a5 Nucleo                  stm32u5    https://www.st.com/en/evaluation-tools/nucleo-u5a5zj-q.html
 stm32wb55nucleo      STM32 P-NUCLEO-WB55                stm32wb    https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html
+stm32wba65nucleo     STM32 NUCLEO-WBA65RI               stm32wba   https://www.st.com/en/evaluation-tools/nucleo-wba65ri.html
 ===================  =================================  =========  =================================================================  ======
 
 Sunxi
diff --git a/docs/reference/dependencies.rst b/docs/reference/dependencies.rst
index d75139aae..8a65eee86 100644
--- a/docs/reference/dependencies.rst
+++ b/docs/reference/dependencies.rst
@@ -71,6 +71,7 @@ hw/mcu/st/stm32l5xx_hal_driver            https://github.com/STMicroelectronics/
 hw/mcu/st/stm32n6xx_hal_driver            https://github.com/STMicroelectronics/stm32n6xx-hal-driver.git    49f9989d10cf6817d4b07ac01848956b46bd0fd6  stm32n6
 hw/mcu/st/stm32u5xx_hal_driver            https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git    4d93097a67928e9377e655ddd14622adc31b9770  stm32u5
 hw/mcu/st/stm32wbxx_hal_driver            https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git    2c5f06638be516c1b772f768456ba637f077bac8  stm32wb
+hw/mcu/st/stm32wbaxx_hal_driver           https://github.com/STMicroelectronics/stm32wbaxx-hal-driver.git   9442fbb71f855ff2e64fbf662b7726beba511a24  stm32wba
 hw/mcu/ti                                 https://github.com/hathach/ti_driver.git                          143ed6cc20a7615d042b03b21e070197d473e6e5  msp430 msp432e4 tm4c
 hw/mcu/wch/ch32f20x                       https://github.com/openwch/ch32f20x.git                           77c4095087e5ed2c548ec9058e655d0b8757663b  ch32f20x
 hw/mcu/wch/ch32v103                       https://github.com/openwch/ch32v103.git                           7578cae0b21f86dd053a1f781b2fc6ab99d0ec17  ch32v10x
diff --git a/hw/bsp/stm32wba/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32wba/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..471d56aec
--- /dev/null
+++ b/hw/bsp/stm32wba/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,153 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32wbaxx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#if defined(__ARM_FP) && __ARM_FP >= 4
+  #define configENABLE_FPU                      1
+#else
+  #define configENABLE_FPU                      0
+#endif
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+#define configCHECK_HANDLER_INSTALLATION       0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32wba/boards/stm32wba_eval/board.cmake b/hw/bsp/stm32wba/boards/stm32wba_eval/board.cmake
new file mode 100644
index 000000000..c0d1cbbcc
--- /dev/null
+++ b/hw/bsp/stm32wba/boards/stm32wba_eval/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32wba65xx)
+set(JLINK_DEVICE STM32WB65RI)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/stm32wb65RIVX_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32WB65xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32wba/boards/stm32wba_eval/board.h b/hw/bsp/stm32wba/boards/stm32wba_eval/board.h
new file mode 100644
index 000000000..eb0622399
--- /dev/null
+++ b/hw/bsp/stm32wba/boards/stm32wba_eval/board.h
@@ -0,0 +1,136 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2025, Dalton Caron
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+ /* metadata:
+    name: STM32 NUCLEO-WBA65RI
+    url: https://www.st.com/en/evaluation-tools/nucleo-wba65ri.html
+ */
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+    // LED (user LED 1)
+#define LED_CLK_EN            __HAL_RCC_GPIOD_CLK_ENABLE
+#define LED_PORT              GPIOD
+#define LED_PIN               GPIO_PIN_8
+#define LED_STATE_ON          1
+
+// Button (user button 1)
+#define BUTTON_CLK_EN         __HAL_RCC_GPIOC_CLK_ENABLE
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   0
+
+// USART (on STM link USB connector)
+#define USART_GPIO_CLK_EN     __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE
+#define USART_DEV             USART3
+#define USART_CLK_EN          __HAL_RCC_USART3_CLK_ENABLE
+#define USART_TX_GPIO_PORT    GPIOA
+#define USART_RX_GPIO_PORT    GPIOA
+#define USART_GPIO_AF         GPIO_AF8_USART3
+#define USART_TX_PIN          GPIO_PIN_7
+#define USART_RX_PIN          GPIO_PIN_5
+
+// USB Pins
+// These pints are only used for USB and must be in analog mode when not used.
+// They are by default configured for USB operation after reset.
+#define USB_DP_PORT           GPIOD
+#define USB_DP_PIN            GPIO_PIN_6
+
+#define USB_DM_PORT           GPIOD
+#define USB_DM_PIN            GPIO_PIN_7
+
+//--------------------------------------------------------------------+
+//    The system clock is configured as follows:
+//        System Clock source       = PLL (HSE, crystal)
+//        SYSCLK (CPU Clock)        = 64 MHz
+//        HCLK (AXI and AHB Clocks) = 64 MHz
+//        AHB Prescaler             = 1
+//        APB1 Prescaler            = 1 (APB3 Clock = 64MHz)
+//        APB2 Prescaler            = 1 (APB1 Clock = 64MHz)
+//        APB7 Prescaler            = 1 (APB2 Clock = 64MHz)
+//        HPRE5 Prescaler           = 2 (AHB5 Clock = 32MHz)
+//        HSE Frequency (Hz)        = 32 MHz
+//        PLL_M                     = 2
+//        PLL_N                     = 8
+//        PLL_P                     = 2
+//        PLL_Q                     = 2
+//        PLL_R                     = 2
+//        VDD (V)                   = 3.3 V
+//        Flash Latency             = 1  Wait States
+//--------------------------------------------------------------------+
+static void board_system_clock_config( void )
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+
+    __HAL_RCC_SYSCFG_CLK_ENABLE();
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    ( void ) HAL_PWREx_ConfigSupply( PWR_LDO_SUPPLY );
+
+    // Must be in voltage scaling mode 1 for the OTG USB HS peripheral to function
+    ( void ) HAL_PWREx_ControlVoltageScaling( PWR_REGULATOR_VOLTAGE_SCALE1 );
+
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+    RCC_OscInitStruct.HSEDiv = RCC_HSE_DIV1;
+    RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL1.PLLM = 2;
+    RCC_OscInitStruct.PLL1.PLLN = 8;
+    RCC_OscInitStruct.PLL1.PLLP = 2;
+    RCC_OscInitStruct.PLL1.PLLQ = 2;
+    RCC_OscInitStruct.PLL1.PLLR = 2;
+    RCC_OscInitStruct.PLL1.PLLFractional = 0;
+    ( void ) HAL_RCC_OscConfig( &RCC_OscInitStruct );
+
+    RCC_ClkInitStruct.ClockType = ( RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+        | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+        | RCC_CLOCKTYPE_PCLK7 | RCC_CLOCKTYPE_HCLK5 );
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+    RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+    RCC_ClkInitStruct.APB7CLKDivider = RCC_HCLK_DIV1;
+    RCC_ClkInitStruct.AHB5_PLL1_CLKDivider = RCC_SYSCLK_PLL1_DIV2;
+    RCC_ClkInitStruct.AHB5_HSEHSI_CLKDivider = RCC_SYSCLK_HSEHSI_DIV1;
+
+    ( void ) HAL_RCC_ClockConfig( &RCC_ClkInitStruct, FLASH_LATENCY_1 );
+
+    ( void ) SystemCoreClockUpdate();
+
+    ( void ) HAL_ICACHE_Enable();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32wba/boards/stm32wba_eval/board.mk b/hw/bsp/stm32wba/boards/stm32wba_eval/board.mk
new file mode 100644
index 000000000..dc8463ca0
--- /dev/null
+++ b/hw/bsp/stm32wba/boards/stm32wba_eval/board.mk
@@ -0,0 +1,6 @@
+MCU_VARIANT = stm32wba65xx
+
+CFLAGS += -DSTM32WBA65xx
+
+# For flash-jlink target
+JLINK_DEVICE = STM32WBA65RI
diff --git a/hw/bsp/stm32wba/boards/stm32wba_eval/include/stm32wbaxx_hal_conf.h b/hw/bsp/stm32wba/boards/stm32wba_eval/include/stm32wbaxx_hal_conf.h
new file mode 100644
index 000000000..419865492
--- /dev/null
+++ b/hw/bsp/stm32wba/boards/stm32wba_eval/include/stm32wbaxx_hal_conf.h
@@ -0,0 +1,368 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbaxx_hal_conf_template.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32wbaxx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32WBAxx_HAL_CONF_H
+#define STM32WBAxx_HAL_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_GTZC_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_ICACHE_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LPTIM_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_PKA_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RAMCFG_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_TSC_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+/* #define HAL_XSPI_MODULE_ENABLED */
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE              32000000UL /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT    100UL   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined (HSI_VALUE)
+#define HSI_VALUE              16000000UL /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined (LSI_VALUE)
+#define LSI_VALUE               32000UL    /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
+                                                The real value may vary depending on the variations in voltage
+                                                and temperature.*/
+
+#if defined (RCC_LSI2_SUPPORT)
+#if !defined (LSI2_VALUE)
+#define LSI2_VALUE              32000UL    /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */
+#endif
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined (LSE_VALUE)
+#define LSE_VALUE              32768UL   /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000UL     /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+#define EXTERNAL_SAI1_CLOCK_VALUE  48000UL /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    3300UL /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((1UL<<__NVIC_PRIO_BITS) - 1UL)  /*!< tick interrupt priority (lowest by default) */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U               /*!< Enable prefetch */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Register callback feature configuration ############### */
+/**
+  * @brief Set below the peripheral configuration  to "1U" to add the support
+  *        of HAL callback registration/unregistration feature for the HAL
+  *        driver(s). This allows user application to provide specific callback
+  *        functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
+  *        the default weak callback functions (see each stm32wbaxx_hal_ppp.h file
+  *        for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
+  *        for each PPP peripheral).
+  */
+#define  USE_HAL_ADC_REGISTER_CALLBACKS        0U /* ADC register callback disabled       */
+#define  USE_HAL_COMP_REGISTER_CALLBACKS       0U /* COMP register callback disabled      */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS       0U /* CRYP register callback disabled      */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS       0U /* HASH register callback disabled      */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS        0U /* HCD register callback disabled       */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS        0U /* I2C register callback disabled       */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS       0U /* IRDA register callback disabled      */
+#define  USE_HAL_IWDG_REGISTER_CALLBACKS       0U /* IWDG register callback disabled      */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS      0U /* LPTIM register callback disabled     */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS        0U /* PCD register callback disabled       */
+#define  USE_HAL_PKA_REGISTER_CALLBACKS        0U /* PKA register callback disabled       */
+#define  USE_HAL_RAMCFG_REGISTER_CALLBACKS     0U /* RAMCFG register callback disabled    */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS        0U /* RNG register callback disabled       */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS        0U /* RTC register callback disabled       */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS        0U /* SAI register callback disabled       */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS      0U /* SMBUS register callback disabled     */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS        0U /* SPI register callback disabled       */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS        0U /* TIM register callback disabled       */
+#define  USE_HAL_TSC_REGISTER_CALLBACKS        0U /* TSC register callback disabled       */
+#define  USE_HAL_UART_REGISTER_CALLBACKS       0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS      0U /* USART register callback disabled     */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS       0U /* WWDG register callback disabled      */
+#define  USE_HAL_XSPI_REGISTER_CALLBACKS       0U /* XSPI register callback disabled      */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+#define USE_SPI_CRC                   1U
+
+/* ################## CRYP peripheral configuration ########################## */
+
+#define USE_HAL_CRYP_SUSPEND_RESUME   0U
+
+/* ################## HASH peripheral configuration ########################## */
+
+#define USE_HAL_HASH_SUSPEND_RESUME   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32wbaxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32wbaxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32wbaxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+#include "stm32wbaxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32wbaxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32wbaxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32wbaxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32wbaxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32wbaxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32wbaxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_GTZC_MODULE_ENABLED
+#include "stm32wbaxx_hal_gtzc.h"
+#endif /* HAL_GTZC_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+#include "stm32wbaxx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+#include "stm32wbaxx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+#include "stm32wbaxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32wbaxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_ICACHE_MODULE_ENABLED
+#include "stm32wbaxx_hal_icache.h"
+#endif /* HAL_ICACHE_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32wbaxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32wbaxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32wbaxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32wbaxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+#include "stm32wbaxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32wbaxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RAMCFG_MODULE_ENABLED
+#include "stm32wbaxx_hal_ramcfg.h"
+#endif /* HAL_RAMCFG_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32wbaxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32wbaxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+#include "stm32wbaxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32wbaxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32wbaxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32wbaxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32wbaxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+#include "stm32wbaxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32wbaxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32wbaxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32wbaxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_XSPI_MODULE_ENABLED
+/* #include "stm32wbaxx_hal_xspi.h" */
+#endif /* HAL_XSPI_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32WBAxx_HAL_CONF_H */
+
diff --git a/hw/bsp/stm32wba/family.c b/hw/bsp/stm32wba/family.c
new file mode 100644
index 000000000..bacac2fdc
--- /dev/null
+++ b/hw/bsp/stm32wba/family.c
@@ -0,0 +1,233 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2025 Dalton Caron
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+#include <stdbool.h>
+
+#include "stm32wbaxx_hal.h"
+#include "bsp/board_api.h"
+#include "board.h"
+
+ //--------------------------------------------------------------------+
+ // MACRO TYPEDEF CONSTANT ENUM
+ //--------------------------------------------------------------------+
+#ifndef CFG_BOARD_UART_BAUDRATE
+#define CFG_BOARD_UART_BAUDRATE 115200
+#endif
+
+#ifndef USART_TIMEOUT_TICKS
+#define USART_TIMEOUT_TICKS 1000
+#endif
+
+static UART_HandleTypeDef uart_handle;
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_OTG_HS_IRQHandler( void )
+{
+    tud_int_handler( 0 );
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+static void board_gpio_configuration( void )
+{
+    GPIO_InitTypeDef gpio_init = { 0 };
+
+    USART_GPIO_CLK_EN();
+    USART_CLK_EN();
+
+    // Configure USART TX pin
+    gpio_init.Pin = USART_TX_PIN;
+    gpio_init.Mode = GPIO_MODE_AF_PP;
+    gpio_init.Pull = GPIO_NOPULL;
+    gpio_init.Speed = GPIO_SPEED_FREQ_HIGH;
+    gpio_init.Alternate = USART_GPIO_AF;
+    HAL_GPIO_Init( USART_TX_GPIO_PORT, &gpio_init );
+
+    // Configure USART RX pin
+    gpio_init.Pin = USART_RX_PIN;
+    gpio_init.Mode = GPIO_MODE_AF_PP;
+    gpio_init.Pull = GPIO_PULLUP;
+    gpio_init.Speed = GPIO_SPEED_FREQ_HIGH;
+    gpio_init.Alternate = USART_GPIO_AF;
+    HAL_GPIO_Init( USART_RX_GPIO_PORT, &gpio_init );
+
+    // Configure the LED
+    LED_CLK_EN();
+    gpio_init.Pin = LED_PIN;
+    gpio_init.Mode = GPIO_MODE_OUTPUT_PP;
+    gpio_init.Pull = GPIO_PULLUP;
+    gpio_init.Speed = GPIO_SPEED_FREQ_LOW;
+    gpio_init.Alternate = 0;
+    HAL_GPIO_Init( LED_PORT, &gpio_init );
+
+    // Default LED state is off
+    board_led_write( false );
+
+    // Configure the button
+    BUTTON_CLK_EN();
+    gpio_init.Pin = BUTTON_PIN;
+    gpio_init.Mode = GPIO_MODE_INPUT;
+    gpio_init.Pull = GPIO_PULLUP;
+    gpio_init.Speed = GPIO_SPEED_FREQ_LOW;
+    gpio_init.Alternate = 0;
+    HAL_GPIO_Init( BUTTON_PORT, &gpio_init );
+
+    // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
+    gpio_init.Pin = (GPIO_PIN_7 | GPIO_PIN_6);
+    gpio_init.Mode = GPIO_MODE_INPUT;
+    gpio_init.Pull = GPIO_NOPULL;
+    gpio_init.Speed = GPIO_SPEED_FREQ_HIGH;
+    HAL_GPIO_Init( GPIOD, &gpio_init );
+}
+
+static void board_uart_configuration( void )
+{
+    uart_handle = ( UART_HandleTypeDef ) {
+      .Instance        = USART_DEV,
+      .Init.BaudRate   = CFG_BOARD_UART_BAUDRATE,
+      .Init.WordLength = UART_WORDLENGTH_8B,
+      .Init.StopBits   = UART_STOPBITS_1,
+      .Init.Parity     = UART_PARITY_NONE,
+      .Init.HwFlowCtl  = UART_HWCONTROL_NONE,
+      .Init.Mode       = UART_MODE_TX_RX,
+      .Init.OverSampling = UART_OVERSAMPLING_16
+    };
+    HAL_UART_Init( &uart_handle );
+}
+
+void board_init( void )
+{
+    board_system_clock_config();
+    board_gpio_configuration();
+    board_uart_configuration();
+
+#ifdef USB_OTG_HS
+    // STM32WBA65/64/62 only has 1 USB HS port
+
+    #if CFG_TUSB_OS == OPT_OS_NONE
+        // 1ms tick timer
+        SysTick_Config( SystemCoreClock / 1000 );
+    #elif CFG_TUSB_OS == OPT_OS_FREERTOS
+        // Explicitly disable systick to prevent its ISR runs before scheduler start
+        SysTick->CTRL &= ~1U;
+
+        // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+        NVIC_SetPriority( OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+    #endif
+
+    // USB clock enable
+    __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
+    __HAL_RCC_USB_OTG_HS_PHY_CLK_ENABLE();
+
+    // See the reference manual section 11.4.7 for the USB OTG powering sequence
+
+    // Remove the VDDUSB power isolation
+    PWR->SVMCR |= PWR_SVMCR_USV;
+
+    // Enable VDD11USB supply by clearing VDD11USBDIS to 0
+    PWR->VOSR &= ~PWR_VOSR_VDD11USBDIS;
+
+    // Enable USB OTG internal power by setting USBPWREN to 1
+    PWR->VOSR |= PWR_VOSR_USBPWREN;
+
+    // Wait for VDD11USB supply to be ready in VDD11USBRDY = 1
+    while ((PWR->VOSR & PWR_VOSR_VDD11USBRDY) == 0) {}
+
+    // Enable USB OTG booster by setting USBBOOSTEN to 1
+    PWR->VOSR |= PWR_VOSR_USBBOOSTEN;
+
+    // Wait for USB OTG booster to be ready in USBBOOSTRDY = 1
+    while ((PWR->VOSR & PWR_VOSR_USBBOOSTRDY) == 0) {}
+
+    // Enable USB power on Pwrctrl CR2 register
+    PWR->SVMCR |= PWR_SVMCR_USV;
+
+    // Set the reference clock selection (must match the clock source)
+    SYSCFG->OTGHSPHYCR &= ~SYSCFG_OTGHSPHYCR_CLKSEL;
+    SYSCFG->OTGHSPHYCR |= SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 |
+        SYSCFG_OTGHSPHYCR_CLKSEL_3;  // 32MHz clock
+
+    // Configuring the SYSCFG registers OTG_HS PHY
+    SYSCFG->OTGHSPHYCR |= SYSCFG_OTGHSPHYCR_EN;
+
+    // Disable VBUS sense (B device)
+    USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+    // B-peripheral session valid override enable
+    USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
+    USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
+#endif // USB_OTG_FS
+}
+
+void board_led_write( bool state )
+{
+    HAL_GPIO_WritePin( LED_PORT, LED_PIN, state ? LED_STATE_ON : ( 1 - LED_STATE_ON ) );
+}
+
+uint32_t board_button_read( void )
+{
+    return HAL_GPIO_ReadPin( BUTTON_PORT, BUTTON_PIN ) == BUTTON_STATE_ACTIVE;
+}
+
+int board_uart_read( uint8_t *buf, int len )
+{
+    ( void ) buf;
+    ( void ) len;
+    return 0;
+}
+
+int board_uart_write( void const *buf, int len )
+{
+    ( void ) HAL_UART_Transmit( &uart_handle, ( const uint8_t * ) buf, len, USART_TIMEOUT_TICKS );
+    return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler( void )
+{
+    HAL_IncTick();
+    system_ticks++;
+}
+
+uint32_t board_millis( void )
+{
+    return system_ticks;
+}
+#endif
+
+void HardFault_Handler( void )
+{
+    asm( "bkpt 1" );
+}
+
+// Required by __libc_init_array in startup code if we are compiling using -nostdlib/-nostartfiles.
+void _init( void );
+void _init( void )
+{ }
diff --git a/hw/bsp/stm32wba/family.mk b/hw/bsp/stm32wba/family.mk
new file mode 100644
index 000000000..ca6459ab2
--- /dev/null
+++ b/hw/bsp/stm32wba/family.mk
@@ -0,0 +1,59 @@
+UF2_FAMILY_ID = 0x70d16657
+ST_FAMILY = wba
+
+ST_PREFIX = stm32${ST_FAMILY}xx
+ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
+ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m33
+
+CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32WBA
+
+CFLAGS_GCC += \
+  -flto \
+  -nostdlib -nostartfiles \
+  -Wno-error=cast-align -Wno-unused-parameter
+
+LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs -Wl,--gc-sections
+
+SRC_C += \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
+	src/portable/synopsys/dwc2/hcd_dwc2.c \
+	src/portable/synopsys/dwc2/dwc2_common.c \
+	$(ST_CMSIS)/Source/Templates/system_${ST_PREFIX}.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_icache.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr_ex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_gpio.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pcd.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pcd_ex.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_ll_usb.c \
+	$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(BOARD_PATH)/include \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(ST_CMSIS)/Include \
+	$(TOP)/$(ST_HAL_DRIVER)/Inc
+
+# STM32WBA HAL uses uppercase MCU_VARIANT (excluding the x's) for linking and lowercase MCU_VARIANT for startup.
+UPPERCASE_MCU_VARIANT = $(shell echo $(MCU_VARIANT) | sed 's/\([^x]\)/\U\1/g')
+
+# Startup - Manually specify lowercase version for startup file
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
+
+# Linker
+LD_FILE_GCC ?= ${ST_CMSIS}/Source/Templates/gcc/linker/${UPPERCASE_MCU_VARIANT}_FLASH_ns.ld
+LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash_cm33.icf
+
+# flash target using on-board stlink
+flash: flash-stlink
\ No newline at end of file
diff --git a/hw/bsp/stm32wba/stm32wbaxx_hal_conf.h b/hw/bsp/stm32wba/stm32wbaxx_hal_conf.h
new file mode 100644
index 000000000..f4e49f341
--- /dev/null
+++ b/hw/bsp/stm32wba/stm32wbaxx_hal_conf.h
@@ -0,0 +1,367 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbaxx_hal_conf_template.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32wbaxx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32WBAxx_HAL_CONF_H
+#define STM32WBAxx_HAL_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+// #define HAL_ADC_MODULE_ENABLED
+// #define HAL_COMP_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+// #define HAL_CRC_MODULE_ENABLED
+// #define HAL_CRYP_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_GTZC_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+// #define HAL_I2C_MODULE_ENABLED
+#define HAL_ICACHE_MODULE_ENABLED
+// #define HAL_IRDA_MODULE_ENABLED
+// #define HAL_IWDG_MODULE_ENABLED
+// #define HAL_LPTIM_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+// #define HAL_PKA_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RAMCFG_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+// #define HAL_RNG_MODULE_ENABLED
+// #define HAL_RTC_MODULE_ENABLED
+// #define HAL_SAI_MODULE_ENABLED
+// #define HAL_SMARTCARD_MODULE_ENABLED
+// #define HAL_SMBUS_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+// #define HAL_TSC_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+// #define HAL_WWDG_MODULE_ENABLED
+// #define HAL_XSPI_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE              32000000UL /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT    100UL   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined (HSI_VALUE)
+#define HSI_VALUE              16000000UL /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined (LSI_VALUE)
+#define LSI_VALUE               32000UL    /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
+                                                The real value may vary depending on the variations in voltage
+                                                and temperature.*/
+
+#if defined (RCC_LSI2_SUPPORT)
+#if !defined (LSI2_VALUE)
+#define LSI2_VALUE              32000UL    /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */
+#endif
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined (LSE_VALUE)
+#define LSE_VALUE              32768UL   /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000UL     /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+#define EXTERNAL_SAI1_CLOCK_VALUE  48000UL /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    3300UL /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((1UL<<__NVIC_PRIO_BITS) - 1UL)  /*!< tick interrupt priority (lowest by default) */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U               /*!< Enable prefetch */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Register callback feature configuration ############### */
+/**
+  * @brief Set below the peripheral configuration  to "1U" to add the support
+  *        of HAL callback registration/unregistration feature for the HAL
+  *        driver(s). This allows user application to provide specific callback
+  *        functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
+  *        the default weak callback functions (see each stm32wbaxx_hal_ppp.h file
+  *        for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
+  *        for each PPP peripheral).
+  */
+#define  USE_HAL_ADC_REGISTER_CALLBACKS        0U /* ADC register callback disabled       */
+#define  USE_HAL_COMP_REGISTER_CALLBACKS       0U /* COMP register callback disabled      */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS       0U /* CRYP register callback disabled      */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS       0U /* HASH register callback disabled      */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS        0U /* HCD register callback disabled       */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS        0U /* I2C register callback disabled       */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS       0U /* IRDA register callback disabled      */
+#define  USE_HAL_IWDG_REGISTER_CALLBACKS       0U /* IWDG register callback disabled      */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS      0U /* LPTIM register callback disabled     */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS        0U /* PCD register callback disabled       */
+#define  USE_HAL_PKA_REGISTER_CALLBACKS        0U /* PKA register callback disabled       */
+#define  USE_HAL_RAMCFG_REGISTER_CALLBACKS     0U /* RAMCFG register callback disabled    */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS        0U /* RNG register callback disabled       */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS        0U /* RTC register callback disabled       */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS        0U /* SAI register callback disabled       */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS      0U /* SMBUS register callback disabled     */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS        0U /* SPI register callback disabled       */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS        0U /* TIM register callback disabled       */
+#define  USE_HAL_TSC_REGISTER_CALLBACKS        0U /* TSC register callback disabled       */
+#define  USE_HAL_UART_REGISTER_CALLBACKS       0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS      0U /* USART register callback disabled     */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS       0U /* WWDG register callback disabled      */
+#define  USE_HAL_XSPI_REGISTER_CALLBACKS       0U /* XSPI register callback disabled      */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+#define USE_SPI_CRC                   1U
+
+/* ################## CRYP peripheral configuration ########################## */
+
+#define USE_HAL_CRYP_SUSPEND_RESUME   0U
+
+/* ################## HASH peripheral configuration ########################## */
+
+#define USE_HAL_HASH_SUSPEND_RESUME   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32wbaxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32wbaxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32wbaxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+#include "stm32wbaxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32wbaxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32wbaxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32wbaxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32wbaxx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32wbaxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32wbaxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_GTZC_MODULE_ENABLED
+#include "stm32wbaxx_hal_gtzc.h"
+#endif /* HAL_GTZC_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+#include "stm32wbaxx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+#include "stm32wbaxx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+#include "stm32wbaxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32wbaxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_ICACHE_MODULE_ENABLED
+#include "stm32wbaxx_hal_icache.h"
+#endif /* HAL_ICACHE_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32wbaxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32wbaxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32wbaxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32wbaxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+#include "stm32wbaxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32wbaxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RAMCFG_MODULE_ENABLED
+#include "stm32wbaxx_hal_ramcfg.h"
+#endif /* HAL_RAMCFG_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32wbaxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32wbaxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+#include "stm32wbaxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32wbaxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32wbaxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32wbaxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32wbaxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+#include "stm32wbaxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32wbaxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32wbaxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32wbaxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_XSPI_MODULE_ENABLED
+#include "stm32wbaxx_hal_xspi.h"
+#endif /* HAL_XSPI_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32WBAxx_HAL_CONF_H */
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 3ffc2d1a4..7722ca1e6 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -295,6 +295,12 @@
   #define TUP_USBIP_FSDEV_STM32
   #define TUP_DCD_ENDPOINT_MAX    8
 
+#elif TU_CHECK_MCU(OPT_MCU_STM32WBA)
+  #define TUP_USBIP_DWC2
+  #define TUP_USBIP_DWC2_STM32
+  #define TUP_DCD_ENDPOINT_MAX    9
+  #define TUP_RHPORT_HIGHSPEED    1
+
 #elif TU_CHECK_MCU(OPT_MCU_STM32U5)
   #if defined (STM32U535xx) || defined (STM32U545xx)
     #define TUP_USBIP_FSDEV
diff --git a/src/portable/st/stm32_fsdev/fsdev_stm32.h b/src/portable/st/stm32_fsdev/fsdev_stm32.h
index ccf31e035..01baf50ae 100644
--- a/src/portable/st/stm32_fsdev/fsdev_stm32.h
+++ b/src/portable/st/stm32_fsdev/fsdev_stm32.h
@@ -148,6 +148,12 @@
   /* ST provided header has incorrect value of USB_PMAADDR */
   #define FSDEV_PMA_BASE USB1_PMAADDR
 
+#elif defined(STM32WBA62xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx)
+  // Available only on STM32WBA62/64/65xx devices
+  #include "stm32wbaxx.h"
+  #define FSDEV_PMA_SIZE (2048u)
+  #define USB USB_DRD_FS
+
 #elif CFG_TUSB_MCU == OPT_MCU_STM32L4
   #include "stm32l4xx.h"
   #define FSDEV_PMA_SIZE (1024u)
@@ -289,6 +295,8 @@ static const IRQn_Type fsdev_irq[] = {
     USB_LP_IRQn,
   #elif CFG_TUSB_MCU == OPT_MCU_STM32U5
     USB_IRQn,
+  #elif CFG_TUSB_MCU == OPT_MCU_STM32WBA
+    USB_OTG_HS_IRQn,
   #elif CFG_TUSB_MCU == OPT_MCU_STM32U0
     USB_DRD_FS_IRQn,
   #else
diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c
index d7d157149..f81cfceda 100644
--- a/src/portable/synopsys/dwc2/dwc2_common.c
+++ b/src/portable/synopsys/dwc2/dwc2_common.c
@@ -49,6 +49,11 @@ static void reset_core(dwc2_regs_t* dwc2) {
   uint32_t gsnpsid = dwc2->gsnpsid;
 
   // reset core
+
+  // On the STM32WBA peripheral, the device seems to get stuck in reset unless
+  // this shadow register is utilized.
+  uint32_t gsnpsid = dwc2->gsnpsid;
+
   dwc2->grstctl |= GRSTCTL_CSRST;
 
   if ((gsnpsid & DWC2_CORE_REV_MASK) < (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 672891561..ca5ce5a7c 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -113,6 +113,22 @@ extern "C" {
     #define EP_MAX_HS                 9
     #define EP_FIFO_SIZE_HS           4096
   #endif
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32WBA
+  #if defined(STM32WBA62xx)
+    #include "stm32wba62xx.h"
+  #elif defined(STM32WBA64xx)
+    #include "stm32wba64xx.h"
+  #elif defined(STM32WBA65xx)
+    #include "stm32wba65xx.h"
+  #else
+    #error "The selected STM32WBA series chip does not support OTG USB HS"
+  #endif
+
+  #define USB_OTG_HS_PERIPH_BASE    USB_OTG_HS_BASE_NS
+  #define OTG_HS_IRQn               USB_OTG_HS_IRQn
+  #define EP_MAX_HS                 9
+  #define EP_FIFO_SIZE_HS           4096
 #else
   #error "Unsupported MCUs"
 #endif
@@ -166,6 +182,7 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
 // MCU specific PHY init, called BEFORE core reset
 // - dwc2 3.30a (H5) use USB_HS_PHYC
 // - dwc2 4.11a (U5) use femtoPHY
+// - dwc2 x.xxx (WBA) use USB_OTG_HS
 static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
     // Enable on-chip FS PHY
@@ -194,11 +211,10 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
     #endif
 
   } else {
-#if CFG_TUSB_MCU != OPT_MCU_STM32U5
+#if CFG_TUSB_MCU != OPT_MCU_STM32U5 && CFG_TUSB_MCU != OPT_MCU_STM32WBA
     // Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable'
     dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
 #endif
-
     // Enable on-chip HS PHY
     if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) {
       #ifdef USB_HS_PHYC
@@ -233,11 +249,14 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
 
       // Enable PLL internal PHY
       USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
+<<<<<<< HEAD
 
       // Wait ~2ms until the PLL is ready (there's no RDY bit to query)
       tusb_time_delay_ms_api(2);
       #else
 
+=======
+>>>>>>> 246a92c65 (It worksgit status!)
       #endif
     }
   }
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 1533bb209..b2dd5fcb2 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -95,6 +95,7 @@
 #define OPT_MCU_STM32H7RS         317 ///< ST F7RS
 #define OPT_MCU_STM32C0           318 ///< ST C0
 #define OPT_MCU_STM32N6           319 ///< ST N6
+#define OPT_MCU_STM32WBA          320 ///< ST WBA
 
 // Sony
 #define OPT_MCU_CXD56             400 ///< SONY CXD56
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 36b4d2d59..37d541785 100755
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -130,6 +130,9 @@ deps_optional = {
     'hw/mcu/st/cmsis_device_wb': ['https://github.com/STMicroelectronics/cmsis_device_wb.git',
                                   'cda2cb9fc4a5232ab18efece0bb06b0b60910083',
                                   'stm32wb'],
+    'hw/mcu/st/cmsis_device_wba': ['https://github.com/STMicroelectronics/cmsis-device-wba',
+                                   '647d8522e5fd15049e9a1cc30ed19d85e5911eaf',
+                                   'stm32wba'],
     'hw/mcu/st/stm32-mfxstm32l152': ['https://github.com/STMicroelectronics/stm32-mfxstm32l152.git',
                                      '7f4389efee9c6a655b55e5df3fceef5586b35f9b',
                                      'stm32h7'],
@@ -193,6 +196,9 @@ deps_optional = {
     'hw/mcu/st/stm32wbxx_hal_driver': ['https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git',
                                        'd60dd46996876506f1d2e9abd6b1cc110c8004cd',
                                        'stm32wb'],
+    'hw/mcu/st/stm32wbaxx_hal_driver': ['https://github.com/STMicroelectronics/stm32wbaxx_hal_driver.git',
+                                       '9442fbb71f855ff2e64fbf662b7726beba511a24',
+                                       'stm32wba'],
     'hw/mcu/ti': ['https://github.com/hathach/ti_driver.git',
                   '143ed6cc20a7615d042b03b21e070197d473e6e5',
                   'msp430 msp432e4 tm4c'],
-- 
cgit v1.3.1


From 913597707493ed7ac075d420795574bc7faa3075 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 12 Sep 2025 11:26:16 +0700
Subject: rename stm32wba eval to nucleo use local linker to fix READONLY
 keyword with clang add wba to ci build

---
 .github/workflows/ci_set_matrix.py                 |   1 +
 docs/reference/dependencies.rst                    |  81 +++---
 hw/bsp/stm32wba/boards/stm32wba_eval/board.cmake   |   8 -
 hw/bsp/stm32wba/boards/stm32wba_eval/board.h       | 136 ----------
 hw/bsp/stm32wba/boards/stm32wba_eval/board.mk      |   6 -
 hw/bsp/stm32wba/boards/stm32wba_nucleo/board.cmake |   8 +
 hw/bsp/stm32wba/boards/stm32wba_nucleo/board.h     | 136 ++++++++++
 hw/bsp/stm32wba/boards/stm32wba_nucleo/board.mk    |   6 +
 hw/bsp/stm32wba/family.c                           | 281 ++++++++++-----------
 hw/bsp/stm32wba/family.cmake                       |  47 ++--
 hw/bsp/stm32wba/family.mk                          |   9 +-
 hw/bsp/stm32wba/linker/STM32WBA65xx_FLASH_ns.ld    | 188 ++++++++++++++
 12 files changed, 534 insertions(+), 373 deletions(-)
 delete mode 100644 hw/bsp/stm32wba/boards/stm32wba_eval/board.cmake
 delete mode 100644 hw/bsp/stm32wba/boards/stm32wba_eval/board.h
 delete mode 100644 hw/bsp/stm32wba/boards/stm32wba_eval/board.mk
 create mode 100644 hw/bsp/stm32wba/boards/stm32wba_nucleo/board.cmake
 create mode 100644 hw/bsp/stm32wba/boards/stm32wba_nucleo/board.h
 create mode 100644 hw/bsp/stm32wba/boards/stm32wba_nucleo/board.mk
 create mode 100644 hw/bsp/stm32wba/linker/STM32WBA65xx_FLASH_ns.ld

(limited to 'docs/reference')

diff --git a/.github/workflows/ci_set_matrix.py b/.github/workflows/ci_set_matrix.py
index 40d51a7a2..3559909ba 100755
--- a/.github/workflows/ci_set_matrix.py
+++ b/.github/workflows/ci_set_matrix.py
@@ -45,6 +45,7 @@ family_list = {
     "stm32l0 stm32l4": ["arm-gcc", "arm-clang", "arm-iar"],
     "stm32n6": ["arm-gcc"],
     "stm32u5 stm32wb": ["arm-gcc", "arm-clang", "arm-iar"],
+    "stm32wba": ["arm-gcc", "arm-clang"],
     "xmc4000": ["arm-gcc"],
     "-bespressif_s2_devkitc": ["esp-idf"],
     # S3, P4 will be built by hil test
diff --git a/docs/reference/dependencies.rst b/docs/reference/dependencies.rst
index 8a65eee86..ca5c84151 100644
--- a/docs/reference/dependencies.rst
+++ b/docs/reference/dependencies.rst
@@ -26,52 +26,53 @@ hw/mcu/nordic/nrfx                        https://github.com/NordicSemiconductor
 hw/mcu/nuvoton                            https://github.com/majbthrd/nuc_driver.git                        2204191ec76283371419fbcec207da02e1bc22fa  nuc
 hw/mcu/nxp/lpcopen                        https://github.com/hathach/nxp_lpcopen.git                        b41cf930e65c734d8ec6de04f1d57d46787c76ae  lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43
 hw/mcu/nxp/mcux-sdk                       https://github.com/nxp-mcuxpresso/mcux-sdk                        a1bdae309a14ec95a4f64a96d3315a4f89c397c6  kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt
-hw/mcu/raspberry_pi/Pico-PIO-USB          https://github.com/sekigon-gonnoc/Pico-PIO-USB.git                3c1eec341a5232640e4c00628b889b641af34b28  rp2040
+hw/mcu/raspberry_pi/Pico-PIO-USB          https://github.com/sekigon-gonnoc/Pico-PIO-USB.git                675543bcc9baa8170f868ab7ba316d418dbcf41f  rp2040
 hw/mcu/renesas/fsp                        https://github.com/renesas/fsp.git                                edcc97d684b6f716728a60d7a6fea049d9870bd6  ra
 hw/mcu/renesas/rx                         https://github.com/kkitayam/rx_device.git                         706b4e0cf485605c32351e2f90f5698267996023  rx
 hw/mcu/silabs/cmsis-dfp-efm32gg12b        https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b.git           f1c31b7887669cb230b3ea63f9b56769078960bc  efm32
 hw/mcu/sony/cxd56/spresense-exported-sdk  https://github.com/sonydevworld/spresense-exported-sdk.git        2ec2a1538362696118dc3fdf56f33dacaf8f4067  spresense
-hw/mcu/st/cmsis_device_c0                 https://github.com/STMicroelectronics/cmsis_device_c0.git         fb56b1b70c73b74eacda2a4bcc36886444364ab3  stm32c0
-hw/mcu/st/cmsis_device_f0                 https://github.com/STMicroelectronics/cmsis_device_f0.git         2fc25ee22264bc27034358be0bd400b893ef837e  stm32f0
-hw/mcu/st/cmsis_device_f1                 https://github.com/STMicroelectronics/cmsis_device_f1.git         6601104a6397299b7304fd5bcd9a491f56cb23a6  stm32f1
-hw/mcu/st/cmsis_device_f2                 https://github.com/STMicroelectronics/cmsis_device_f2.git         182fcb3681ce116816feb41b7764f1b019ce796f  stm32f2
-hw/mcu/st/cmsis_device_f3                 https://github.com/STMicroelectronics/cmsis_device_f3.git         5e4ee5ed7a7b6c85176bb70a9fd3c72d6eb99f1b  stm32f3
-hw/mcu/st/cmsis_device_f4                 https://github.com/STMicroelectronics/cmsis_device_f4.git         2615e866fa48fe1ff1af9e31c348813f2b19e7ec  stm32f4
-hw/mcu/st/cmsis_device_f7                 https://github.com/STMicroelectronics/cmsis_device_f7.git         25b0463439303b7a38f0d27b161f7d2f3c096e79  stm32f7
-hw/mcu/st/cmsis_device_g0                 https://github.com/STMicroelectronics/cmsis_device_g0.git         3a23e1224417f3f2d00300ecd620495e363f2094  stm32g0
-hw/mcu/st/cmsis_device_g4                 https://github.com/STMicroelectronics/cmsis_device_g4.git         ce822adb1dc552b3aedd13621edbc7fdae124878  stm32g4
-hw/mcu/st/cmsis_device_h5                 https://github.com/STMicroelectronics/cmsis_device_h5.git         cd2d1d579743de57b88ccaf61a968b9c05848ffc  stm32h5
-hw/mcu/st/cmsis_device_h7                 https://github.com/STMicroelectronics/cmsis_device_h7.git         60dc2c913203dc8629dc233d4384dcc41c91e77f  stm32h7
-hw/mcu/st/cmsis_device_h7rs               https://github.com/STMicroelectronics/cmsis_device_h7rs.git       832649d1fd09bd901e9f68e979522e5c209ebf20  stm32h7rs
-hw/mcu/st/cmsis_device_l0                 https://github.com/STMicroelectronics/cmsis_device_l0.git         69cd5999fd40ae6e546d4905b21635c6ca1bcb92  stm32l0
-hw/mcu/st/cmsis_device_l1                 https://github.com/STMicroelectronics/cmsis_device_l1.git         7f16ec0a1c4c063f84160b4cc6bf88ad554a823e  stm32l1
-hw/mcu/st/cmsis_device_l4                 https://github.com/STMicroelectronics/cmsis_device_l4.git         6ca7312fa6a5a460b5a5a63d66da527fdd8359a6  stm32l4
-hw/mcu/st/cmsis_device_l5                 https://github.com/STMicroelectronics/cmsis_device_l5.git         d922865fc0326a102c26211c44b8e42f52c1e53d  stm32l5
-hw/mcu/st/cmsis_device_n6                 https://github.com/STMicroelectronics/cmsis-device-n6.git         f818b00f775444e8d19ef6cad822534c345e054f  stm32n6
-hw/mcu/st/cmsis_device_u5                 https://github.com/STMicroelectronics/cmsis_device_u5.git         5ad9797c54ec3e55eff770fc9b3cd4a1aefc1309  stm32u5
-hw/mcu/st/cmsis_device_wb                 https://github.com/STMicroelectronics/cmsis_device_wb.git         d6a7fa2e7de084f5e5e47f2ab88b022fe9b50e5a  stm32wb
+hw/mcu/st/cmsis-device-wba                https://github.com/STMicroelectronics/cmsis-device-wba.git        647d8522e5fd15049e9a1cc30ed19d85e5911eaf  stm32wba
+hw/mcu/st/cmsis_device_c0                 https://github.com/STMicroelectronics/cmsis_device_c0.git         517611273f835ffe95318947647bc1408f69120d  stm32c0
+hw/mcu/st/cmsis_device_f0                 https://github.com/STMicroelectronics/cmsis_device_f0.git         cbb5da5d48b4b5f2efacdc2f033be30f9d29889f  stm32f0
+hw/mcu/st/cmsis_device_f1                 https://github.com/STMicroelectronics/cmsis_device_f1.git         c8e9a4a4f16b6d2cb2a2083cbe5161025280fb22  stm32f1
+hw/mcu/st/cmsis_device_f2                 https://github.com/STMicroelectronics/cmsis_device_f2.git         49321f1e4d2bd3e65687b37f2652a28ea7983674  stm32f2
+hw/mcu/st/cmsis_device_f3                 https://github.com/STMicroelectronics/cmsis_device_f3.git         5558e64e3675a1e1fcb1c71f468c7c407c1b1134  stm32f3
+hw/mcu/st/cmsis_device_f4                 https://github.com/STMicroelectronics/cmsis_device_f4.git         3c77349ce04c8af401454cc51f85ea9a50e34fc1  stm32f4
+hw/mcu/st/cmsis_device_f7                 https://github.com/STMicroelectronics/cmsis_device_f7.git         2352e888e821aa0f4fe549bd5ea81d29c67a3222  stm32f7
+hw/mcu/st/cmsis_device_g0                 https://github.com/STMicroelectronics/cmsis_device_g0.git         f484fe852535f913a02ee79787eafa74dd7f9488  stm32g0
+hw/mcu/st/cmsis_device_g4                 https://github.com/STMicroelectronics/cmsis_device_g4.git         7c39c32593b03764aaa57531588b8bf7cdd443a5  stm32g4
+hw/mcu/st/cmsis_device_h5                 https://github.com/STMicroelectronics/cmsis_device_h5.git         5273b8f134ba65f5b8174c4141b711b5c0d295b2  stm32h5
+hw/mcu/st/cmsis_device_h7                 https://github.com/STMicroelectronics/cmsis_device_h7.git         45b818cab6ee2806e3a27c80e330957223424392  stm32h7
+hw/mcu/st/cmsis_device_h7rs               https://github.com/STMicroelectronics/cmsis_device_h7rs.git       57ea11f70ebf1850e1048989d665c9070f0bb863  stm32h7rs
+hw/mcu/st/cmsis_device_l0                 https://github.com/STMicroelectronics/cmsis_device_l0.git         7b7ae8cd71437331e1d7824f157d00c7bb4a5044  stm32l0
+hw/mcu/st/cmsis_device_l1                 https://github.com/STMicroelectronics/cmsis_device_l1.git         a23ade4ccf14012085fedf862e33a536ab7ed8be  stm32l1
+hw/mcu/st/cmsis_device_l4                 https://github.com/STMicroelectronics/cmsis_device_l4.git         a2530753e86dd326a75467d28feb92e2ba7d0df2  stm32l4
+hw/mcu/st/cmsis_device_l5                 https://github.com/STMicroelectronics/cmsis_device_l5.git         7d9a51481f0e6c376e62c3c849e6caf652c66482  stm32l5
+hw/mcu/st/cmsis_device_n6                 https://github.com/STMicroelectronics/cmsis-device-n6.git         7bcdc944fbf7cf5928d3c1d14054ca13261d33ec  stm32n6
+hw/mcu/st/cmsis_device_u5                 https://github.com/STMicroelectronics/cmsis_device_u5.git         6e67187dec98035893692ab2923914cb5f4e0117  stm32u5
+hw/mcu/st/cmsis_device_wb                 https://github.com/STMicroelectronics/cmsis_device_wb.git         cda2cb9fc4a5232ab18efece0bb06b0b60910083  stm32wb
 hw/mcu/st/stm32-mfxstm32l152              https://github.com/STMicroelectronics/stm32-mfxstm32l152.git      7f4389efee9c6a655b55e5df3fceef5586b35f9b  stm32h7
 hw/mcu/st/stm32-tcpp0203                  https://github.com/STMicroelectronics/stm32-tcpp0203.git          9918655bff176ac3046ccf378b5c7bbbc6a38d15  stm32h7rs stm32n6
-hw/mcu/st/stm32c0xx_hal_driver            https://github.com/STMicroelectronics/stm32c0xx_hal_driver.git    41253e2f1d7ae4a4d0c379cf63f5bcf71fcf8eb3  stm32c0
-hw/mcu/st/stm32f0xx_hal_driver            https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git    0e95cd88657030f640a11e690a8a5186c7712ea5  stm32f0
-hw/mcu/st/stm32f1xx_hal_driver            https://github.com/STMicroelectronics/stm32f1xx_hal_driver.git    1dd9d3662fb7eb2a7f7d3bc0a4c1dc7537915a29  stm32f1
-hw/mcu/st/stm32f2xx_hal_driver            https://github.com/STMicroelectronics/stm32f2xx_hal_driver.git    c75ace9b908a9aca631193ebf2466963b8ea33d0  stm32f2
-hw/mcu/st/stm32f3xx_hal_driver            https://github.com/STMicroelectronics/stm32f3xx_hal_driver.git    1761b6207318ede021706e75aae78f452d72b6fa  stm32f3
-hw/mcu/st/stm32f4xx_hal_driver            https://github.com/STMicroelectronics/stm32f4xx_hal_driver.git    04e99fbdabd00ab8f370f377c66b0a4570365b58  stm32f4
-hw/mcu/st/stm32f7xx_hal_driver            https://github.com/STMicroelectronics/stm32f7xx_hal_driver.git    f7ffdf6bf72110e58b42c632b0a051df5997e4ee  stm32f7
-hw/mcu/st/stm32g0xx_hal_driver            https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git    e911b12c7f67084d7f6b76157a4c0d4e2ec3779c  stm32g0
-hw/mcu/st/stm32g4xx_hal_driver            https://github.com/STMicroelectronics/stm32g4xx_hal_driver.git    8b4518417706d42eef5c14e56a650005abf478a8  stm32g4
-hw/mcu/st/stm32h5xx_hal_driver            https://github.com/STMicroelectronics/stm32h5xx_hal_driver.git    2cf77de584196d619cec1b4586c3b9e2820a254e  stm32h5
-hw/mcu/st/stm32h7rsxx_hal_driver          https://github.com/STMicroelectronics/stm32h7rsxx-hal-driver.git  7ca2e07ca21bc66b53654e845b4c85c884343b60  stm32h7rs
-hw/mcu/st/stm32h7xx_hal_driver            https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git    d8461b980b59b1625207d8c4f2ce0a9c2a7a3b04  stm32h7
-hw/mcu/st/stm32l0xx_hal_driver            https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git    fbdacaf6f8c82a4e1eb9bd74ba650b491e97e17b  stm32l0
-hw/mcu/st/stm32l1xx_hal_driver            https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git    44efc446fa69ed8344e7fd966e68ed11043b35d9  stm32l1
-hw/mcu/st/stm32l4xx_hal_driver            https://github.com/STMicroelectronics/stm32l4xx_hal_driver.git    aee3d5bf283ae5df87532b781bdd01b7caf256fc  stm32l4
-hw/mcu/st/stm32l5xx_hal_driver            https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git    675c32a75df37f39d50d61f51cb0dcf53f07e1cb  stm32l5
-hw/mcu/st/stm32n6xx_hal_driver            https://github.com/STMicroelectronics/stm32n6xx-hal-driver.git    49f9989d10cf6817d4b07ac01848956b46bd0fd6  stm32n6
-hw/mcu/st/stm32u5xx_hal_driver            https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git    4d93097a67928e9377e655ddd14622adc31b9770  stm32u5
-hw/mcu/st/stm32wbxx_hal_driver            https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git    2c5f06638be516c1b772f768456ba637f077bac8  stm32wb
-hw/mcu/st/stm32wbaxx_hal_driver           https://github.com/STMicroelectronics/stm32wbaxx-hal-driver.git   9442fbb71f855ff2e64fbf662b7726beba511a24  stm32wba
+hw/mcu/st/stm32c0xx_hal_driver            https://github.com/STMicroelectronics/stm32c0xx_hal_driver.git    c283b143bef6bdaacf64240ee6f15eb61dad6125  stm32c0
+hw/mcu/st/stm32f0xx_hal_driver            https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git    94399697cb5eeaf8511b81b7f50dc62f0a5a3f6c  stm32f0
+hw/mcu/st/stm32f1xx_hal_driver            https://github.com/STMicroelectronics/stm32f1xx_hal_driver.git    18074e3e5ecad0b380a5cf5a9131fe4b5ed1b2b7  stm32f1
+hw/mcu/st/stm32f2xx_hal_driver            https://github.com/STMicroelectronics/stm32f2xx_hal_driver.git    ae7b47fe41cf75ccaf65cbf8ee8749b18ba0e0f3  stm32f2
+hw/mcu/st/stm32f3xx_hal_driver            https://github.com/STMicroelectronics/stm32f3xx_hal_driver.git    e098c8c8ce6f426bcee7db3a37c0932ea881eb0b  stm32f3
+hw/mcu/st/stm32f4xx_hal_driver            https://github.com/STMicroelectronics/stm32f4xx_hal_driver.git    b6f0ed3829f3829eb358a2e7417d80bba1a42db7  stm32f4
+hw/mcu/st/stm32f7xx_hal_driver            https://github.com/STMicroelectronics/stm32f7xx_hal_driver.git    e1446fa12ffda80ea1016faf349e45b2047fff12  stm32f7
+hw/mcu/st/stm32g0xx_hal_driver            https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git    a248a9e484d58943b46c68f6c49b4b276778bd59  stm32g0
+hw/mcu/st/stm32g4xx_hal_driver            https://github.com/STMicroelectronics/stm32g4xx_hal_driver.git    10138a41749ea62d53ecab65b2bc2a950acc04d2  stm32g4
+hw/mcu/st/stm32h5xx_hal_driver            https://github.com/STMicroelectronics/stm32h5xx_hal_driver.git    3c84eaa6000ab620be01afbcfba2735389afe09b  stm32h5
+hw/mcu/st/stm32h7rsxx_hal_driver          https://github.com/STMicroelectronics/stm32h7rsxx-hal-driver.git  9e83b95ae0f70faa067eddce2da617d180937f9b  stm32h7rs
+hw/mcu/st/stm32h7xx_hal_driver            https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git    dbfb749f229e1aa89e50b54229ca87766e180d2d  stm32h7
+hw/mcu/st/stm32l0xx_hal_driver            https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git    65da4cd8a10ad859ec8d9cd71f3f6c50735bd473  stm32l0
+hw/mcu/st/stm32l1xx_hal_driver            https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git    54f0b7568ce2acb33d090c70c897ee32229c1d32  stm32l1
+hw/mcu/st/stm32l4xx_hal_driver            https://github.com/STMicroelectronics/stm32l4xx_hal_driver.git    3e039bbf62f54bbd834d578185521cff80596efe  stm32l4
+hw/mcu/st/stm32l5xx_hal_driver            https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git    3340b9a597bcf75cc173345a90a74aa2a4a37510  stm32l5
+hw/mcu/st/stm32n6xx_hal_driver            https://github.com/STMicroelectronics/stm32n6xx-hal-driver.git    bc6c41f8f67d61b47af26695d0bf67762a000666  stm32n6
+hw/mcu/st/stm32u5xx_hal_driver            https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git    2c5e2568fbdb1900a13ca3b2901fdd302cac3444  stm32u5
+hw/mcu/st/stm32wbaxx_hal_driver           https://github.com/STMicroelectronics/stm32wbaxx_hal_driver.git   9442fbb71f855ff2e64fbf662b7726beba511a24  stm32wba
+hw/mcu/st/stm32wbxx_hal_driver            https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git    d60dd46996876506f1d2e9abd6b1cc110c8004cd  stm32wb
 hw/mcu/ti                                 https://github.com/hathach/ti_driver.git                          143ed6cc20a7615d042b03b21e070197d473e6e5  msp430 msp432e4 tm4c
 hw/mcu/wch/ch32f20x                       https://github.com/openwch/ch32f20x.git                           77c4095087e5ed2c548ec9058e655d0b8757663b  ch32f20x
 hw/mcu/wch/ch32v103                       https://github.com/openwch/ch32v103.git                           7578cae0b21f86dd053a1f781b2fc6ab99d0ec17  ch32v10x
diff --git a/hw/bsp/stm32wba/boards/stm32wba_eval/board.cmake b/hw/bsp/stm32wba/boards/stm32wba_eval/board.cmake
deleted file mode 100644
index 57bd920d3..000000000
--- a/hw/bsp/stm32wba/boards/stm32wba_eval/board.cmake
+++ /dev/null
@@ -1,8 +0,0 @@
-set(MCU_VARIANT stm32wba65xx)
-set(JLINK_DEVICE STM32WBA65RI)
-
-function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    STM32WBA65xx
-    )
-endfunction()
diff --git a/hw/bsp/stm32wba/boards/stm32wba_eval/board.h b/hw/bsp/stm32wba/boards/stm32wba_eval/board.h
deleted file mode 100644
index eb0622399..000000000
--- a/hw/bsp/stm32wba/boards/stm32wba_eval/board.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2025, Dalton Caron
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
- /* metadata:
-    name: STM32 NUCLEO-WBA65RI
-    url: https://www.st.com/en/evaluation-tools/nucleo-wba65ri.html
- */
-#ifndef BOARD_H_
-#define BOARD_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-    // LED (user LED 1)
-#define LED_CLK_EN            __HAL_RCC_GPIOD_CLK_ENABLE
-#define LED_PORT              GPIOD
-#define LED_PIN               GPIO_PIN_8
-#define LED_STATE_ON          1
-
-// Button (user button 1)
-#define BUTTON_CLK_EN         __HAL_RCC_GPIOC_CLK_ENABLE
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   0
-
-// USART (on STM link USB connector)
-#define USART_GPIO_CLK_EN     __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE
-#define USART_DEV             USART3
-#define USART_CLK_EN          __HAL_RCC_USART3_CLK_ENABLE
-#define USART_TX_GPIO_PORT    GPIOA
-#define USART_RX_GPIO_PORT    GPIOA
-#define USART_GPIO_AF         GPIO_AF8_USART3
-#define USART_TX_PIN          GPIO_PIN_7
-#define USART_RX_PIN          GPIO_PIN_5
-
-// USB Pins
-// These pints are only used for USB and must be in analog mode when not used.
-// They are by default configured for USB operation after reset.
-#define USB_DP_PORT           GPIOD
-#define USB_DP_PIN            GPIO_PIN_6
-
-#define USB_DM_PORT           GPIOD
-#define USB_DM_PIN            GPIO_PIN_7
-
-//--------------------------------------------------------------------+
-//    The system clock is configured as follows:
-//        System Clock source       = PLL (HSE, crystal)
-//        SYSCLK (CPU Clock)        = 64 MHz
-//        HCLK (AXI and AHB Clocks) = 64 MHz
-//        AHB Prescaler             = 1
-//        APB1 Prescaler            = 1 (APB3 Clock = 64MHz)
-//        APB2 Prescaler            = 1 (APB1 Clock = 64MHz)
-//        APB7 Prescaler            = 1 (APB2 Clock = 64MHz)
-//        HPRE5 Prescaler           = 2 (AHB5 Clock = 32MHz)
-//        HSE Frequency (Hz)        = 32 MHz
-//        PLL_M                     = 2
-//        PLL_N                     = 8
-//        PLL_P                     = 2
-//        PLL_Q                     = 2
-//        PLL_R                     = 2
-//        VDD (V)                   = 3.3 V
-//        Flash Latency             = 1  Wait States
-//--------------------------------------------------------------------+
-static void board_system_clock_config( void )
-{
-    RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
-    RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
-
-    __HAL_RCC_SYSCFG_CLK_ENABLE();
-    __HAL_RCC_PWR_CLK_ENABLE();
-
-    ( void ) HAL_PWREx_ConfigSupply( PWR_LDO_SUPPLY );
-
-    // Must be in voltage scaling mode 1 for the OTG USB HS peripheral to function
-    ( void ) HAL_PWREx_ControlVoltageScaling( PWR_REGULATOR_VOLTAGE_SCALE1 );
-
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-    RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-    RCC_OscInitStruct.HSEDiv = RCC_HSE_DIV1;
-    RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON;
-    RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSE;
-    RCC_OscInitStruct.PLL1.PLLM = 2;
-    RCC_OscInitStruct.PLL1.PLLN = 8;
-    RCC_OscInitStruct.PLL1.PLLP = 2;
-    RCC_OscInitStruct.PLL1.PLLQ = 2;
-    RCC_OscInitStruct.PLL1.PLLR = 2;
-    RCC_OscInitStruct.PLL1.PLLFractional = 0;
-    ( void ) HAL_RCC_OscConfig( &RCC_OscInitStruct );
-
-    RCC_ClkInitStruct.ClockType = ( RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
-        | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
-        | RCC_CLOCKTYPE_PCLK7 | RCC_CLOCKTYPE_HCLK5 );
-    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-    RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
-    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-    RCC_ClkInitStruct.APB7CLKDivider = RCC_HCLK_DIV1;
-    RCC_ClkInitStruct.AHB5_PLL1_CLKDivider = RCC_SYSCLK_PLL1_DIV2;
-    RCC_ClkInitStruct.AHB5_HSEHSI_CLKDivider = RCC_SYSCLK_HSEHSI_DIV1;
-
-    ( void ) HAL_RCC_ClockConfig( &RCC_ClkInitStruct, FLASH_LATENCY_1 );
-
-    ( void ) SystemCoreClockUpdate();
-
-    ( void ) HAL_ICACHE_Enable();
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32wba/boards/stm32wba_eval/board.mk b/hw/bsp/stm32wba/boards/stm32wba_eval/board.mk
deleted file mode 100644
index dc8463ca0..000000000
--- a/hw/bsp/stm32wba/boards/stm32wba_eval/board.mk
+++ /dev/null
@@ -1,6 +0,0 @@
-MCU_VARIANT = stm32wba65xx
-
-CFLAGS += -DSTM32WBA65xx
-
-# For flash-jlink target
-JLINK_DEVICE = STM32WBA65RI
diff --git a/hw/bsp/stm32wba/boards/stm32wba_nucleo/board.cmake b/hw/bsp/stm32wba/boards/stm32wba_nucleo/board.cmake
new file mode 100644
index 000000000..57bd920d3
--- /dev/null
+++ b/hw/bsp/stm32wba/boards/stm32wba_nucleo/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT stm32wba65xx)
+set(JLINK_DEVICE STM32WBA65RI)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32WBA65xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32wba/boards/stm32wba_nucleo/board.h b/hw/bsp/stm32wba/boards/stm32wba_nucleo/board.h
new file mode 100644
index 000000000..eb0622399
--- /dev/null
+++ b/hw/bsp/stm32wba/boards/stm32wba_nucleo/board.h
@@ -0,0 +1,136 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2025, Dalton Caron
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+ /* metadata:
+    name: STM32 NUCLEO-WBA65RI
+    url: https://www.st.com/en/evaluation-tools/nucleo-wba65ri.html
+ */
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+    // LED (user LED 1)
+#define LED_CLK_EN            __HAL_RCC_GPIOD_CLK_ENABLE
+#define LED_PORT              GPIOD
+#define LED_PIN               GPIO_PIN_8
+#define LED_STATE_ON          1
+
+// Button (user button 1)
+#define BUTTON_CLK_EN         __HAL_RCC_GPIOC_CLK_ENABLE
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   0
+
+// USART (on STM link USB connector)
+#define USART_GPIO_CLK_EN     __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE
+#define USART_DEV             USART3
+#define USART_CLK_EN          __HAL_RCC_USART3_CLK_ENABLE
+#define USART_TX_GPIO_PORT    GPIOA
+#define USART_RX_GPIO_PORT    GPIOA
+#define USART_GPIO_AF         GPIO_AF8_USART3
+#define USART_TX_PIN          GPIO_PIN_7
+#define USART_RX_PIN          GPIO_PIN_5
+
+// USB Pins
+// These pints are only used for USB and must be in analog mode when not used.
+// They are by default configured for USB operation after reset.
+#define USB_DP_PORT           GPIOD
+#define USB_DP_PIN            GPIO_PIN_6
+
+#define USB_DM_PORT           GPIOD
+#define USB_DM_PIN            GPIO_PIN_7
+
+//--------------------------------------------------------------------+
+//    The system clock is configured as follows:
+//        System Clock source       = PLL (HSE, crystal)
+//        SYSCLK (CPU Clock)        = 64 MHz
+//        HCLK (AXI and AHB Clocks) = 64 MHz
+//        AHB Prescaler             = 1
+//        APB1 Prescaler            = 1 (APB3 Clock = 64MHz)
+//        APB2 Prescaler            = 1 (APB1 Clock = 64MHz)
+//        APB7 Prescaler            = 1 (APB2 Clock = 64MHz)
+//        HPRE5 Prescaler           = 2 (AHB5 Clock = 32MHz)
+//        HSE Frequency (Hz)        = 32 MHz
+//        PLL_M                     = 2
+//        PLL_N                     = 8
+//        PLL_P                     = 2
+//        PLL_Q                     = 2
+//        PLL_R                     = 2
+//        VDD (V)                   = 3.3 V
+//        Flash Latency             = 1  Wait States
+//--------------------------------------------------------------------+
+static void board_system_clock_config( void )
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+
+    __HAL_RCC_SYSCFG_CLK_ENABLE();
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    ( void ) HAL_PWREx_ConfigSupply( PWR_LDO_SUPPLY );
+
+    // Must be in voltage scaling mode 1 for the OTG USB HS peripheral to function
+    ( void ) HAL_PWREx_ControlVoltageScaling( PWR_REGULATOR_VOLTAGE_SCALE1 );
+
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+    RCC_OscInitStruct.HSEDiv = RCC_HSE_DIV1;
+    RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL1.PLLM = 2;
+    RCC_OscInitStruct.PLL1.PLLN = 8;
+    RCC_OscInitStruct.PLL1.PLLP = 2;
+    RCC_OscInitStruct.PLL1.PLLQ = 2;
+    RCC_OscInitStruct.PLL1.PLLR = 2;
+    RCC_OscInitStruct.PLL1.PLLFractional = 0;
+    ( void ) HAL_RCC_OscConfig( &RCC_OscInitStruct );
+
+    RCC_ClkInitStruct.ClockType = ( RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+        | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+        | RCC_CLOCKTYPE_PCLK7 | RCC_CLOCKTYPE_HCLK5 );
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+    RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+    RCC_ClkInitStruct.APB7CLKDivider = RCC_HCLK_DIV1;
+    RCC_ClkInitStruct.AHB5_PLL1_CLKDivider = RCC_SYSCLK_PLL1_DIV2;
+    RCC_ClkInitStruct.AHB5_HSEHSI_CLKDivider = RCC_SYSCLK_HSEHSI_DIV1;
+
+    ( void ) HAL_RCC_ClockConfig( &RCC_ClkInitStruct, FLASH_LATENCY_1 );
+
+    ( void ) SystemCoreClockUpdate();
+
+    ( void ) HAL_ICACHE_Enable();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32wba/boards/stm32wba_nucleo/board.mk b/hw/bsp/stm32wba/boards/stm32wba_nucleo/board.mk
new file mode 100644
index 000000000..dc8463ca0
--- /dev/null
+++ b/hw/bsp/stm32wba/boards/stm32wba_nucleo/board.mk
@@ -0,0 +1,6 @@
+MCU_VARIANT = stm32wba65xx
+
+CFLAGS += -DSTM32WBA65xx
+
+# For flash-jlink target
+JLINK_DEVICE = STM32WBA65RI
diff --git a/hw/bsp/stm32wba/family.c b/hw/bsp/stm32wba/family.c
index bacac2fdc..923ea197c 100644
--- a/hw/bsp/stm32wba/family.c
+++ b/hw/bsp/stm32wba/family.c
@@ -23,19 +23,20 @@
  *
  * This file is part of the TinyUSB stack.
  */
+
+/* metadata:
+   manufacturer: STMicroelectronics
+*/
+
 #include <stdbool.h>
 
 #include "stm32wbaxx_hal.h"
 #include "bsp/board_api.h"
 #include "board.h"
 
- //--------------------------------------------------------------------+
- // MACRO TYPEDEF CONSTANT ENUM
- //--------------------------------------------------------------------+
-#ifndef CFG_BOARD_UART_BAUDRATE
-#define CFG_BOARD_UART_BAUDRATE 115200
-#endif
-
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
 #ifndef USART_TIMEOUT_TICKS
 #define USART_TIMEOUT_TICKS 1000
 #endif
@@ -45,189 +46,171 @@ static UART_HandleTypeDef uart_handle;
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB_OTG_HS_IRQHandler( void )
-{
-    tud_int_handler( 0 );
+void USB_OTG_HS_IRQHandler(void) {
+  tud_int_handler(0);
 }
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-static void board_gpio_configuration( void )
-{
-    GPIO_InitTypeDef gpio_init = { 0 };
-
-    USART_GPIO_CLK_EN();
-    USART_CLK_EN();
-
-    // Configure USART TX pin
-    gpio_init.Pin = USART_TX_PIN;
-    gpio_init.Mode = GPIO_MODE_AF_PP;
-    gpio_init.Pull = GPIO_NOPULL;
-    gpio_init.Speed = GPIO_SPEED_FREQ_HIGH;
-    gpio_init.Alternate = USART_GPIO_AF;
-    HAL_GPIO_Init( USART_TX_GPIO_PORT, &gpio_init );
-
-    // Configure USART RX pin
-    gpio_init.Pin = USART_RX_PIN;
-    gpio_init.Mode = GPIO_MODE_AF_PP;
-    gpio_init.Pull = GPIO_PULLUP;
-    gpio_init.Speed = GPIO_SPEED_FREQ_HIGH;
-    gpio_init.Alternate = USART_GPIO_AF;
-    HAL_GPIO_Init( USART_RX_GPIO_PORT, &gpio_init );
-
-    // Configure the LED
-    LED_CLK_EN();
-    gpio_init.Pin = LED_PIN;
-    gpio_init.Mode = GPIO_MODE_OUTPUT_PP;
-    gpio_init.Pull = GPIO_PULLUP;
-    gpio_init.Speed = GPIO_SPEED_FREQ_LOW;
-    gpio_init.Alternate = 0;
-    HAL_GPIO_Init( LED_PORT, &gpio_init );
-
-    // Default LED state is off
-    board_led_write( false );
-
-    // Configure the button
-    BUTTON_CLK_EN();
-    gpio_init.Pin = BUTTON_PIN;
-    gpio_init.Mode = GPIO_MODE_INPUT;
-    gpio_init.Pull = GPIO_PULLUP;
-    gpio_init.Speed = GPIO_SPEED_FREQ_LOW;
-    gpio_init.Alternate = 0;
-    HAL_GPIO_Init( BUTTON_PORT, &gpio_init );
-
-    // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
-    gpio_init.Pin = (GPIO_PIN_7 | GPIO_PIN_6);
-    gpio_init.Mode = GPIO_MODE_INPUT;
-    gpio_init.Pull = GPIO_NOPULL;
-    gpio_init.Speed = GPIO_SPEED_FREQ_HIGH;
-    HAL_GPIO_Init( GPIOD, &gpio_init );
+static void board_gpio_configuration(void) {
+  GPIO_InitTypeDef gpio_init = {0};
+
+  USART_GPIO_CLK_EN();
+  USART_CLK_EN();
+
+  // Configure USART TX pin
+  gpio_init.Pin = USART_TX_PIN;
+  gpio_init.Mode = GPIO_MODE_AF_PP;
+  gpio_init.Pull = GPIO_NOPULL;
+  gpio_init.Speed = GPIO_SPEED_FREQ_HIGH;
+  gpio_init.Alternate = USART_GPIO_AF;
+  HAL_GPIO_Init(USART_TX_GPIO_PORT, &gpio_init);
+
+  // Configure USART RX pin
+  gpio_init.Pin = USART_RX_PIN;
+  gpio_init.Mode = GPIO_MODE_AF_PP;
+  gpio_init.Pull = GPIO_PULLUP;
+  gpio_init.Speed = GPIO_SPEED_FREQ_HIGH;
+  gpio_init.Alternate = USART_GPIO_AF;
+  HAL_GPIO_Init(USART_RX_GPIO_PORT, &gpio_init);
+
+  // Configure the LED
+  LED_CLK_EN();
+  gpio_init.Pin = LED_PIN;
+  gpio_init.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_init.Pull = GPIO_PULLUP;
+  gpio_init.Speed = GPIO_SPEED_FREQ_LOW;
+  gpio_init.Alternate = 0;
+  HAL_GPIO_Init(LED_PORT, &gpio_init);
+
+  // Default LED state is off
+  board_led_write(false);
+
+  // Configure the button
+  BUTTON_CLK_EN();
+  gpio_init.Pin = BUTTON_PIN;
+  gpio_init.Mode = GPIO_MODE_INPUT;
+  gpio_init.Pull = GPIO_PULLUP;
+  gpio_init.Speed = GPIO_SPEED_FREQ_LOW;
+  gpio_init.Alternate = 0;
+  HAL_GPIO_Init(BUTTON_PORT, &gpio_init);
+
+  // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
+  gpio_init.Pin = (GPIO_PIN_7 | GPIO_PIN_6);
+  gpio_init.Mode = GPIO_MODE_INPUT;
+  gpio_init.Pull = GPIO_NOPULL;
+  gpio_init.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOD, &gpio_init);
 }
 
-static void board_uart_configuration( void )
-{
-    uart_handle = ( UART_HandleTypeDef ) {
-      .Instance        = USART_DEV,
-      .Init.BaudRate   = CFG_BOARD_UART_BAUDRATE,
+static void board_uart_configuration(void) {
+  uart_handle = ( UART_HandleTypeDef){
+      .Instance = USART_DEV,
+      .Init.BaudRate = CFG_BOARD_UART_BAUDRATE,
       .Init.WordLength = UART_WORDLENGTH_8B,
-      .Init.StopBits   = UART_STOPBITS_1,
-      .Init.Parity     = UART_PARITY_NONE,
-      .Init.HwFlowCtl  = UART_HWCONTROL_NONE,
-      .Init.Mode       = UART_MODE_TX_RX,
+      .Init.StopBits = UART_STOPBITS_1,
+      .Init.Parity = UART_PARITY_NONE,
+      .Init.HwFlowCtl = UART_HWCONTROL_NONE,
+      .Init.Mode = UART_MODE_TX_RX,
       .Init.OverSampling = UART_OVERSAMPLING_16
-    };
-    HAL_UART_Init( &uart_handle );
+  };
+  HAL_UART_Init(&uart_handle);
 }
 
-void board_init( void )
-{
-    board_system_clock_config();
-    board_gpio_configuration();
-    board_uart_configuration();
+void board_init(void) {
+  board_system_clock_config();
+  board_gpio_configuration();
+  board_uart_configuration();
 
-#ifdef USB_OTG_HS
-    // STM32WBA65/64/62 only has 1 USB HS port
+  #ifdef USB_OTG_HS
+  // STM32WBA65/64/62 only has 1 USB HS port
 
-    #if CFG_TUSB_OS == OPT_OS_NONE
-        // 1ms tick timer
-        SysTick_Config( SystemCoreClock / 1000 );
-    #elif CFG_TUSB_OS == OPT_OS_FREERTOS
-        // Explicitly disable systick to prevent its ISR runs before scheduler start
-        SysTick->CTRL &= ~1U;
+  #if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+  #elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
 
-        // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-        NVIC_SetPriority( OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-    #endif
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB_OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  #endif
 
-    // USB clock enable
-    __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
-    __HAL_RCC_USB_OTG_HS_PHY_CLK_ENABLE();
+  // USB clock enable
+  __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
+  __HAL_RCC_USB_OTG_HS_PHY_CLK_ENABLE();
 
-    // See the reference manual section 11.4.7 for the USB OTG powering sequence
+  // See the reference manual section 11.4.7 for the USB OTG powering sequence
 
-    // Remove the VDDUSB power isolation
-    PWR->SVMCR |= PWR_SVMCR_USV;
+  // Remove the VDDUSB power isolation
+  PWR->SVMCR |= PWR_SVMCR_USV;
 
-    // Enable VDD11USB supply by clearing VDD11USBDIS to 0
-    PWR->VOSR &= ~PWR_VOSR_VDD11USBDIS;
+  // Enable VDD11USB supply by clearing VDD11USBDIS to 0
+  PWR->VOSR &= ~PWR_VOSR_VDD11USBDIS;
 
-    // Enable USB OTG internal power by setting USBPWREN to 1
-    PWR->VOSR |= PWR_VOSR_USBPWREN;
+  // Enable USB OTG internal power by setting USBPWREN to 1
+  PWR->VOSR |= PWR_VOSR_USBPWREN;
 
-    // Wait for VDD11USB supply to be ready in VDD11USBRDY = 1
-    while ((PWR->VOSR & PWR_VOSR_VDD11USBRDY) == 0) {}
+  // Wait for VDD11USB supply to be ready in VDD11USBRDY = 1
+  while ((PWR->VOSR & PWR_VOSR_VDD11USBRDY) == 0) {}
 
-    // Enable USB OTG booster by setting USBBOOSTEN to 1
-    PWR->VOSR |= PWR_VOSR_USBBOOSTEN;
+  // Enable USB OTG booster by setting USBBOOSTEN to 1
+  PWR->VOSR |= PWR_VOSR_USBBOOSTEN;
 
-    // Wait for USB OTG booster to be ready in USBBOOSTRDY = 1
-    while ((PWR->VOSR & PWR_VOSR_USBBOOSTRDY) == 0) {}
+  // Wait for USB OTG booster to be ready in USBBOOSTRDY = 1
+  while ((PWR->VOSR & PWR_VOSR_USBBOOSTRDY) == 0) {}
 
-    // Enable USB power on Pwrctrl CR2 register
-    PWR->SVMCR |= PWR_SVMCR_USV;
+  // Enable USB power on Pwrctrl CR2 register
+  PWR->SVMCR |= PWR_SVMCR_USV;
 
-    // Set the reference clock selection (must match the clock source)
-    SYSCFG->OTGHSPHYCR &= ~SYSCFG_OTGHSPHYCR_CLKSEL;
-    SYSCFG->OTGHSPHYCR |= SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 |
-        SYSCFG_OTGHSPHYCR_CLKSEL_3;  // 32MHz clock
+  // Set the reference clock selection (must match the clock source)
+  SYSCFG->OTGHSPHYCR &= ~SYSCFG_OTGHSPHYCR_CLKSEL;
+  SYSCFG->OTGHSPHYCR |= SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 |
+      SYSCFG_OTGHSPHYCR_CLKSEL_3;// 32MHz clock
 
-    // Configuring the SYSCFG registers OTG_HS PHY
-    SYSCFG->OTGHSPHYCR |= SYSCFG_OTGHSPHYCR_EN;
+  // Configuring the SYSCFG registers OTG_HS PHY
+  SYSCFG->OTGHSPHYCR |= SYSCFG_OTGHSPHYCR_EN;
 
-    // Disable VBUS sense (B device)
-    USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+  // Disable VBUS sense (B device)
+  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
 
-    // B-peripheral session valid override enable
-    USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
-    USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
-#endif // USB_OTG_FS
+  // B-peripheral session valid override enable
+  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
+  USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
+  #endif // USB_OTG_FS
 }
 
-void board_led_write( bool state )
-{
-    HAL_GPIO_WritePin( LED_PORT, LED_PIN, state ? LED_STATE_ON : ( 1 - LED_STATE_ON ) );
-}
+void board_led_write(bool state) { HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); }
 
-uint32_t board_button_read( void )
-{
-    return HAL_GPIO_ReadPin( BUTTON_PORT, BUTTON_PIN ) == BUTTON_STATE_ACTIVE;
-}
+uint32_t board_button_read(void) { return HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN) == BUTTON_STATE_ACTIVE; }
 
-int board_uart_read( uint8_t *buf, int len )
-{
-    ( void ) buf;
-    ( void ) len;
-    return 0;
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
 }
 
-int board_uart_write( void const *buf, int len )
-{
-    ( void ) HAL_UART_Transmit( &uart_handle, ( const uint8_t * ) buf, len, USART_TIMEOUT_TICKS );
-    return len;
+int board_uart_write(void const *buf, int len) {
+  (void) HAL_UART_Transmit(&uart_handle, (const uint8_t *) buf, len, USART_TIMEOUT_TICKS);
+  return len;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler( void )
-{
-    HAL_IncTick();
-    system_ticks++;
-}
 
-uint32_t board_millis( void )
-{
-    return system_ticks;
+void SysTick_Handler(void) {
+  HAL_IncTick();
+  system_ticks++;
 }
+
+uint32_t board_millis(void) { return system_ticks; }
 #endif
 
-void HardFault_Handler( void )
-{
-    asm( "bkpt 1" );
-}
+void HardFault_Handler(void) { asm( "bkpt 1" ); }
 
 // Required by __libc_init_array in startup code if we are compiling using -nostdlib/-nostartfiles.
-void _init( void );
-void _init( void )
-{ }
+void _init(void);
+
+void _init(void) {}
diff --git a/hw/bsp/stm32wba/family.cmake b/hw/bsp/stm32wba/family.cmake
index 3f41900ea..3f42879be 100644
--- a/hw/bsp/stm32wba/family.cmake
+++ b/hw/bsp/stm32wba/family.cmake
@@ -4,7 +4,7 @@ set(ST_FAMILY wba)
 set(ST_PREFIX stm32${ST_FAMILY}xx)
 
 set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
-set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis-device-${ST_FAMILY})
 set(CMSIS_5 ${TOP}/lib/CMSIS_5)
 
 # include board specific
@@ -19,25 +19,12 @@ set(FAMILY_MCUS STM32WBA CACHE INTERNAL "")
 # ----------------------
 # Port & Speed Selection
 # ----------------------
-if (NOT DEFINED RHPORT_DEVICE)
-  set(RHPORT_DEVICE 0)
-endif ()
-if (NOT DEFINED RHPORT_HOST)
-  set(RHPORT_HOST 0)
-endif ()
-
-if (NOT DEFINED RHPORT_SPEED)
-  # WBA65/64/62 has built-in HS PHY
-  set(RHPORT_SPEED OPT_MODE_HIGH_SPEED OPT_MODE_HIGH_SPEED)
-endif ()
-if (NOT DEFINED RHPORT_DEVICE_SPEED)
-  list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED)
-endif ()
-if (NOT DEFINED RHPORT_HOST_SPEED)
-  list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED)
-endif ()
-
-cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED)
+set(RHPORT_DEVICE 0)
+set(RHPORT_HOST 0)
+
+# WBA65/64/62 has built-in HS PHY
+set(RHPORT_DEVICE_SPEED OPT_MODE_HIGH_SPEED)
+set(RHPORT_HOST_SPEED OPT_MODE_HIGH_SPEED)
 
 #------------------------------------
 # BOARD_TARGET
@@ -57,7 +44,7 @@ function(add_board_target BOARD_TARGET)
   set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
   set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
 
-  set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${UPPERCASE_MCU_VARIANT}_FLASH_ns.ld)
+  set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${UPPERCASE_MCU_VARIANT}_FLASH_ns.ld)
   set(LD_FILE_Clang ${LD_FILE_GNU})
   set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash_ns.icf)
 
@@ -66,15 +53,15 @@ function(add_board_target BOARD_TARGET)
     ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
     ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
     ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_icache.c
-	${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
-	${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
-	${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
-	${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
-	${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
-	${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
-	${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pcd.c
-	${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pcd_ex.c
-	${ST_HAL_DRIVER}/Src/${ST_PREFIX}_ll_usb.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pcd.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pcd_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_ll_usb.c
     ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
     )
   target_include_directories(${BOARD_TARGET} PUBLIC
diff --git a/hw/bsp/stm32wba/family.mk b/hw/bsp/stm32wba/family.mk
index 22f63609f..9b319921f 100644
--- a/hw/bsp/stm32wba/family.mk
+++ b/hw/bsp/stm32wba/family.mk
@@ -13,10 +13,11 @@ CFLAGS += \
 
 CFLAGS_GCC += \
   -flto \
-  -nostdlib -nostartfiles \
   -Wno-error=cast-align -Wno-unused-parameter
 
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs -Wl,--gc-sections
+LDFLAGS_GCC += \
+  -nostdlib -nostartfiles \
+  -specs=nosys.specs -specs=nano.specs -Wl,--gc-sections
 
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
@@ -44,14 +45,14 @@ INC += \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # STM32WBA HAL uses uppercase MCU_VARIANT (excluding the x's) for linking and lowercase MCU_VARIANT for startup.
-UPPERCASE_MCU_VARIANT = $(shell echo $(MCU_VARIANT) | sed 's/\([^x]\)/\U\1/g')
+UPPERCASE_MCU_VARIANT = $(subst XX,xx,$(call to_upper,$(MCU_VARIANT)))
 
 # Startup - Manually specify lowercase version for startup file
 SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
 SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
 
 # Linker
-LD_FILE_GCC ?= ${ST_CMSIS}/Source/Templates/gcc/linker/${UPPERCASE_MCU_VARIANT}_FLASH_ns.ld
+LD_FILE_GCC ?= ${FAMILY_PATH}/linker/${UPPERCASE_MCU_VARIANT}_FLASH_ns.ld
 LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash_ns.icf
 
 # flash target using on-board stlink
diff --git a/hw/bsp/stm32wba/linker/STM32WBA65xx_FLASH_ns.ld b/hw/bsp/stm32wba/linker/STM32WBA65xx_FLASH_ns.ld
new file mode 100644
index 000000000..bc1f2997d
--- /dev/null
+++ b/hw/bsp/stm32wba/linker/STM32WBA65xx_FLASH_ns.ld
@@ -0,0 +1,188 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32WBA65xx Device from STM32WBA series
+**                      2048Kbytes FLASH
+**                      512Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2024 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM       (xrw)    : ORIGIN = 0x20038000,   LENGTH = 224K
+  RAM2      (xrw)    : ORIGIN = 0x20078000,   LENGTH = 32K
+  FLASH     (rx)     : ORIGIN = 0x08100000,   LENGTH = 1024K
+}
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab :
+  {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM :
+  {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
-- 
cgit v1.3.1


From ba36df6233cd1bd09f383818f10c1ccda7b9efb4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 12 Sep 2025 11:27:31 +0700
Subject: fix warnings, update docs

---
 docs/reference/boards.rst                          | 35 +++++++++++-----------
 .../device/audio_4_channel_mic_freertos/src/main.c |  2 --
 examples/device/audio_test_freertos/src/main.c     |  2 --
 examples/device/cdc_msc_freertos/src/main.c        |  4 +--
 examples/device/cdc_msc_freertos/src/msc_disk.c    |  2 +-
 examples/device/midi_test_freertos/src/main.c      |  2 --
 .../device/uac2_speaker_fb/src/quirk_os_guessing.c |  8 ++---
 examples/device/usbtmc/src/usbtmc_app.c            |  4 +--
 hw/bsp/at32f402_405/boards/at_start_f402/board.h   |  4 +--
 .../boards/at32f403a_weact_blackpill/board.h       |  2 +-
 hw/bsp/at32f403a_407/boards/at_start_f407/board.h  |  4 +--
 hw/bsp/at32f435_437/boards/at_start_f435/board.h   |  4 +--
 hw/bsp/stm32n6/boards/stm32n6570dk/board.h         |  2 +-
 13 files changed, 34 insertions(+), 41 deletions(-)

(limited to 'docs/reference')

diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst
index a930f485b..25542264c 100644
--- a/docs/reference/boards.rst
+++ b/docs/reference/boards.rst
@@ -28,22 +28,23 @@ max78002evkit  MAX78002 EVKIT    maxim     https://www.analog.com/en/resources/e
 =============  ================  ========  =================================================================================================================  ======
 
 Artery
------
-
-==============  ==============  =============  ==================================================  ======
-Board           Name            Family         URL                                                 Note
-==============  ==============  =============  ==================================================  ======
-at_start_f402   AT-START-F402   at32f402_405   https://www.arterychip.com/en/product/AT32F402.jsp
-at_start_f405   AT-START-F405   at32f402_405   https://www.arterychip.com/en/product/AT32F405.jsp
-at_start_f403a  AT-START-F403a  at32f403a_407  https://www.arterychip.com/en/product/AT32F403A.jsp
-at_start_f407   AT-START-F407   at32f403a_407  https://www.arterychip.com/en/product/AT32F407.jsp
-at_start_f413   AT-START-F413   at32f413       https://www.arterychip.com/en/product/AT32F413.jsp
-at_start_f415   AT-START-F415   at32f415       https://www.arterychip.com/en/product/AT32F415.jsp
-at_start_f423   AT-START-F423   at32f423       https://www.arterychip.com/en/product/AT32F423.jsp
-at_start_f425   AT-START-F425   at32f425       https://www.arterychip.com/en/product/AT32F425.jsp
-at_start_f435   AT-START-F435   at32f435_437   https://www.arterychip.com/en/product/AT32F435.jsp
-at_start_f437   AT-START-F437   at32f435_437   https://www.arterychip.com/en/product/AT32F437.jsp
-==============  ==============  =============  ==================================================  ======
+------
+
+=========================  =============================  =============  ====================================================  ======
+Board                      Name                           Family         URL                                                   Note
+=========================  =============================  =============  ====================================================  ======
+at_start_f402              AT-START-F402                  at32f402_405   https://www.arterychip.com/en/product/AT32F402.jsp
+at_start_f405              AT-START-F405                  at32f402_405   https://www.arterychip.com/en/product/AT32F405.jsp
+at32f403a_weact_blackpill  WeAct BlackPill AT32F403ACGU7  at32f403a_407  https://github.com/WeActStudio/WeActStudio.BlackPill
+at_start_f403a             AT-START-F403a                 at32f403a_407  https://www.arterychip.com/en/product/AT32F403.jsp
+at_start_f407              AT-START-F407                  at32f403a_407  https://www.arterychip.com/en/product/AT32F407.jsp
+at_start_f413              AT-START-F413                  at32f413       https://www.arterychip.com/en/product/AT32F413.jsp
+at_start_f415              AT-START-F415                  at32f415       https://www.arterychip.com/en/product/AT32F415.jsp
+at_start_f423              AT-START-F423                  at32f423       https://www.arterychip.com/en/product/AT32F423.jsp
+at_start_f425              AT-START-F425                  at32f425       https://www.arterychip.com/en/product/AT32F425.jsp
+at_start_f435              AT-START-F435                  at32f435_437   https://www.arterychip.com/en/product/AT32F435.jsp
+at_start_f437              AT-START-F437                  at32f435_437   https://www.arterychip.com/en/product/AT32F437.jsp
+=========================  =============================  =============  ====================================================  ======
 
 Bridgetek
 ---------
@@ -303,7 +304,7 @@ stm32u575eval        STM32 U575 Eval                    stm32u5    https://www.s
 stm32u575nucleo      STM32 U575 Nucleo                  stm32u5    https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html
 stm32u5a5nucleo      STM32 U5a5 Nucleo                  stm32u5    https://www.st.com/en/evaluation-tools/nucleo-u5a5zj-q.html
 stm32wb55nucleo      STM32 P-NUCLEO-WB55                stm32wb    https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html
-stm32wba65nucleo     STM32 NUCLEO-WBA65RI               stm32wba   https://www.st.com/en/evaluation-tools/nucleo-wba65ri.html
+stm32wba_nucleo      STM32 NUCLEO-WBA65RI               stm32wba   https://www.st.com/en/evaluation-tools/nucleo-wba65ri.html
 ===================  =================================  =========  =================================================================  ======
 
 Sunxi
diff --git a/examples/device/audio_4_channel_mic_freertos/src/main.c b/examples/device/audio_4_channel_mic_freertos/src/main.c
index 9c76380a2..643b2f259 100644
--- a/examples/device/audio_4_channel_mic_freertos/src/main.c
+++ b/examples/device/audio_4_channel_mic_freertos/src/main.c
@@ -476,13 +476,11 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p
 //--------------------------------------------------------------------+
 void led_blinking_task(void *param) {
   (void) param;
-  static uint32_t start_ms = 0;
   static bool led_state = false;
 
   while (1) {
     // Blink every interval ms
     vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
-    start_ms += blink_interval_ms;
 
     board_led_write(led_state);
     led_state = 1 - led_state;// toggle
diff --git a/examples/device/audio_test_freertos/src/main.c b/examples/device/audio_test_freertos/src/main.c
index b2bed295f..ea06af0e2 100644
--- a/examples/device/audio_test_freertos/src/main.c
+++ b/examples/device/audio_test_freertos/src/main.c
@@ -470,13 +470,11 @@ bool tud_audio_set_itf_close_ep_cb(uint8_t rhport, tusb_control_request_t const
 //--------------------------------------------------------------------+
 void led_blinking_task(void *param) {
   (void) param;
-  static uint32_t start_ms = 0;
   static bool led_state = false;
 
   while (1) {
     // Blink every interval ms
     vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
-    start_ms += blink_interval_ms;
 
     board_led_write(led_state);
     led_state = 1 - led_state;// toggle
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index 09ccc9bf3..b20d162ab 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -229,13 +229,11 @@ void tud_cdc_rx_cb(uint8_t itf) {
 //--------------------------------------------------------------------+
 void led_blinking_task(void* param) {
   (void) param;
-  static uint32_t start_ms = 0;
-  static bool led_state = false;
+    static bool led_state = false;
 
   while (1) {
     // Blink every interval ms
     vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
-    start_ms += blink_interval_ms;
 
     board_led_write(led_state);
     led_state = 1 - led_state; // toggle
diff --git a/examples/device/cdc_msc_freertos/src/msc_disk.c b/examples/device/cdc_msc_freertos/src/msc_disk.c
index 3602c991d..849712e6a 100644
--- a/examples/device/cdc_msc_freertos/src/msc_disk.c
+++ b/examples/device/cdc_msc_freertos/src/msc_disk.c
@@ -150,7 +150,7 @@ uint8_t msc_disk[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] =
 };
 
 #if CFG_EXAMPLE_MSC_ASYNC_IO
-void msc_disk_init() {
+void msc_disk_init(void) {
 
 #if configSUPPORT_STATIC_ALLOCATION
   io_queue = xQueueCreateStatic(1, sizeof(io_ops_t), io_queue_buf, &io_queue_static);
diff --git a/examples/device/midi_test_freertos/src/main.c b/examples/device/midi_test_freertos/src/main.c
index 3e406d38d..c18ad6ada 100644
--- a/examples/device/midi_test_freertos/src/main.c
+++ b/examples/device/midi_test_freertos/src/main.c
@@ -225,13 +225,11 @@ void midi_task(void* param) {
 //--------------------------------------------------------------------+
 void led_blinking_task(void* param) {
   (void) param;
-  static uint32_t start_ms = 0;
   static bool led_state = false;
 
   while (1) {
     // Blink every interval ms
     vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS);
-    start_ms += blink_interval_ms;
 
     board_led_write(led_state);
     led_state = 1 - led_state; // toggle
diff --git a/examples/device/uac2_speaker_fb/src/quirk_os_guessing.c b/examples/device/uac2_speaker_fb/src/quirk_os_guessing.c
index 965bbd6cf..92b9ab6ee 100644
--- a/examples/device/uac2_speaker_fb/src/quirk_os_guessing.c
+++ b/examples/device/uac2_speaker_fb/src/quirk_os_guessing.c
@@ -29,12 +29,12 @@ static tusb_desc_type_t desc_req_buf[2];
 static int desc_req_idx = 0;
 
 // Place at the start of tud_descriptor_device_cb()
-void quirk_os_guessing_desc_device_cb() {
+void quirk_os_guessing_desc_device_cb(void) {
   desc_req_idx = 0;
 }
 
 // Place at the start of tud_descriptor_configuration_cb()
-void quirk_os_guessing_desc_configuration_cb() {
+void quirk_os_guessing_desc_configuration_cb(void) {
   // Skip redundant request
   if (desc_req_idx == 0 || (desc_req_idx == 1 && desc_req_buf[0] != TUSB_DESC_CONFIGURATION)) {
     desc_req_buf[desc_req_idx++] = TUSB_DESC_CONFIGURATION;
@@ -42,7 +42,7 @@ void quirk_os_guessing_desc_configuration_cb() {
 }
 
 // Place at the start of tud_descriptor_bos_cb()
-void quirk_os_guessing_desc_bos_cb() {
+void quirk_os_guessing_desc_bos_cb(void) {
   // Skip redundant request
   if (desc_req_idx == 0 || (desc_req_idx == 1 && desc_req_buf[0] != TUSB_DESC_BOS)) {
     desc_req_buf[desc_req_idx++] = TUSB_DESC_BOS;
@@ -50,7 +50,7 @@ void quirk_os_guessing_desc_bos_cb() {
 }
 
 // Place at the start of tud_descriptor_string_cb()
-void quirk_os_guessing_desc_string_cb() {
+void quirk_os_guessing_desc_string_cb(void) {
   // Skip redundant request
   if (desc_req_idx == 0 || (desc_req_idx == 1 && desc_req_buf[0] != TUSB_DESC_STRING)) {
     desc_req_buf[desc_req_idx++] = TUSB_DESC_STRING;
diff --git a/examples/device/usbtmc/src/usbtmc_app.c b/examples/device/usbtmc/src/usbtmc_app.c
index fb25982c7..e738f1008 100644
--- a/examples/device/usbtmc/src/usbtmc_app.c
+++ b/examples/device/usbtmc/src/usbtmc_app.c
@@ -99,7 +99,7 @@ usbtmc_response_capabilities_488_t const *
 #else
 usbtmc_response_capabilities_t const *
 #endif
-tud_usbtmc_get_capabilities_cb()
+tud_usbtmc_get_capabilities_cb(void)
 {
   return &tud_usbtmc_app_capabilities;
 }
@@ -161,7 +161,7 @@ bool tud_usbtmc_msg_data_cb(void *data, size_t len, bool transfer_complete)
   return true;
 }
 
-bool tud_usbtmc_msgBulkIn_complete_cb()
+bool tud_usbtmc_msgBulkIn_complete_cb(void)
 {
   if((buffer_tx_ix == buffer_len) || idnQuery) // done
   {
diff --git a/hw/bsp/at32f402_405/boards/at_start_f402/board.h b/hw/bsp/at32f402_405/boards/at_start_f402/board.h
index b11b7a80f..01b78f101 100644
--- a/hw/bsp/at32f402_405/boards/at_start_f402/board.h
+++ b/hw/bsp/at32f402_405/boards/at_start_f402/board.h
@@ -25,8 +25,8 @@
  */
 
 /* metadata:
-   name: AT-START-F405
-   url: https://www.arterychip.com/en/product/AT32F405.jsp
+   name: AT-START-F402
+   url: https://www.arterychip.com/en/product/AT32F402.jsp
 */
 
 #ifndef BOARD_H_
diff --git a/hw/bsp/at32f403a_407/boards/at32f403a_weact_blackpill/board.h b/hw/bsp/at32f403a_407/boards/at32f403a_weact_blackpill/board.h
index 005c5aed6..2dac9bc56 100644
--- a/hw/bsp/at32f403a_407/boards/at32f403a_weact_blackpill/board.h
+++ b/hw/bsp/at32f403a_407/boards/at32f403a_weact_blackpill/board.h
@@ -25,7 +25,7 @@
  */
 
 /* metadata:
-   name: WeAct Studio BlackPill AT32F403ACGU7
+   name: WeAct BlackPill AT32F403ACGU7
    url: https://github.com/WeActStudio/WeActStudio.BlackPill
 */
 
diff --git a/hw/bsp/at32f403a_407/boards/at_start_f407/board.h b/hw/bsp/at32f403a_407/boards/at_start_f407/board.h
index 753fece10..c490d7ed6 100644
--- a/hw/bsp/at32f403a_407/boards/at_start_f407/board.h
+++ b/hw/bsp/at32f403a_407/boards/at_start_f407/board.h
@@ -25,8 +25,8 @@
  */
 
 /* metadata:
-   name: AT-START-F403a
-   url: https://www.arterychip.com/en/product/AT32F403.jsp
+   name: AT-START-F407
+   url: https://www.arterychip.com/en/product/AT32F407.jsp
 */
 
 #ifndef BOARD_H_
diff --git a/hw/bsp/at32f435_437/boards/at_start_f435/board.h b/hw/bsp/at32f435_437/boards/at_start_f435/board.h
index 3522e759a..25fd81450 100644
--- a/hw/bsp/at32f435_437/boards/at_start_f435/board.h
+++ b/hw/bsp/at32f435_437/boards/at_start_f435/board.h
@@ -25,8 +25,8 @@
  */
 
 /* metadata:
-   name: AT-START-F437
-   url: https://www.arterychip.com/en/product/AT32F437.jsp
+   name: AT-START-F435
+   url: https://www.arterychip.com/en/product/AT32F435.jsp
 */
 
 #ifndef BOARD_H_
diff --git a/hw/bsp/stm32n6/boards/stm32n6570dk/board.h b/hw/bsp/stm32n6/boards/stm32n6570dk/board.h
index 96e430c7a..a3d945f76 100644
--- a/hw/bsp/stm32n6/boards/stm32n6570dk/board.h
+++ b/hw/bsp/stm32n6/boards/stm32n6570dk/board.h
@@ -25,7 +25,7 @@
  */
 
 /* metadata:
-   name: STM32N6570-DK
+   name: STM32 N6570-DK
    url: https://www.st.com/en/evaluation-tools/stm32n6570-dk.html
 */
 
-- 
cgit v1.3.1