From 6b73d786b3ddddcb1fbed51909095a46d68d2449 Mon Sep 17 00:00:00 2001
From: Zhihong Chen <zhihong.chen@hpmicro.com>
Date: Mon, 8 Dec 2025 17:14:12 +0800
Subject: update risc-v march for gcc and clang toolchains

- add `zifencei` option

Signed-off-by: Zhihong Chen <zhihong.chen@hpmicro.com>
---
 examples/build_system/cmake/cpu/rv32imac-ilp32.cmake | 4 ++--
 examples/build_system/make/cpu/rv32imac-ilp32.mk     | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'examples/build_system')

diff --git a/examples/build_system/cmake/cpu/rv32imac-ilp32.cmake b/examples/build_system/cmake/cpu/rv32imac-ilp32.cmake
index 584d90519..8c2538cee 100644
--- a/examples/build_system/cmake/cpu/rv32imac-ilp32.cmake
+++ b/examples/build_system/cmake/cpu/rv32imac-ilp32.cmake
@@ -1,13 +1,13 @@
 if (TOOLCHAIN STREQUAL "gcc")
   set(TOOLCHAIN_COMMON_FLAGS
-    -march=rv32imac_zicsr
+    -march=rv32imac_zicsr_zifencei
     -mabi=ilp32
     )
   set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")
 
 elseif (TOOLCHAIN STREQUAL "clang")
   set(TOOLCHAIN_COMMON_FLAGS
-    -march=rv32imac_zicsr
+    -march=rv32imac_zicsr_zifencei
     -mabi=ilp32
     )
   set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")
diff --git a/examples/build_system/make/cpu/rv32imac-ilp32.mk b/examples/build_system/make/cpu/rv32imac-ilp32.mk
index 19c322ebc..a7b2258d7 100644
--- a/examples/build_system/make/cpu/rv32imac-ilp32.mk
+++ b/examples/build_system/make/cpu/rv32imac-ilp32.mk
@@ -1,11 +1,11 @@
 ifeq ($(TOOLCHAIN),gcc)
   CFLAGS += \
-    -march=rv32imac_zicsr \
+    -march=rv32imac_zicsr_zifencei \
     -mabi=ilp32 \
 
 else ifeq ($(TOOLCHAIN),clang)
   CFLAGS += \
-    -march=rv32imac_zicsr \
+    -march=rv32imac_zicsr_zifencei \
     -mabi=ilp32 \
 
 else ifeq ($(TOOLCHAIN),iar)
-- 
cgit v1.3.1


From 5a7e5db78770d6fd37992b5812f910c3546f2a72 Mon Sep 17 00:00:00 2001
From: Zixun LI <admin@hifiphile.com>
Date: Tue, 16 Dec 2025 11:09:16 +0100
Subject: fix riscv toolchain

Signed-off-by: Zixun LI <admin@hifiphile.com>
---
 examples/build_system/make/toolchain/riscv_gcc.mk |  2 +-
 hw/bsp/family_support.mk                          | 17 +++++++++++++++--
 2 files changed, 16 insertions(+), 3 deletions(-)

(limited to 'examples/build_system')

diff --git a/examples/build_system/make/toolchain/riscv_gcc.mk b/examples/build_system/make/toolchain/riscv_gcc.mk
index 843aff38c..b5de12a83 100644
--- a/examples/build_system/make/toolchain/riscv_gcc.mk
+++ b/examples/build_system/make/toolchain/riscv_gcc.mk
@@ -1,7 +1,7 @@
 # makefile for arm gcc toolchain
 
 # Can be set by family, default to ARM GCC
-CROSS_COMPILE ?= riscv-none-embed-
+CROSS_COMPILE ?= riscv-none-elf-
 
 CC = $(CROSS_COMPILE)gcc
 CXX = $(CROSS_COMPILE)g++
diff --git a/hw/bsp/family_support.mk b/hw/bsp/family_support.mk
index db410a657..7122a7764 100644
--- a/hw/bsp/family_support.mk
+++ b/hw/bsp/family_support.mk
@@ -131,8 +131,21 @@ ifdef CPU_CORE
   include ${TOP}/examples/build_system/make/cpu/$(CPU_CORE).mk
 endif
 
-# toolchain specific
-include ${TOP}/examples/build_system/make/toolchain/arm_$(TOOLCHAIN).mk
+# toolchain specific - select based on CPU architecture
+ifdef CPU_CORE
+  ifneq (,$(filter cortex% arm%,$(CPU_CORE)))
+    # ARM/Cortex architecture
+    include ${TOP}/examples/build_system/make/toolchain/arm_$(TOOLCHAIN).mk
+  else ifneq (,$(filter rv%,$(CPU_CORE)))
+    # RISC-V architecture
+    include ${TOP}/examples/build_system/make/toolchain/riscv_$(TOOLCHAIN).mk
+  else
+    $(error Unsupported CPU_CORE architecture: $(CPU_CORE). Must start with cortex, arm, or rv)
+  endif
+else
+  # Default to ARM if CPU_CORE not specified
+  include ${TOP}/examples/build_system/make/toolchain/arm_$(TOOLCHAIN).mk
+endif
 
 #---------------------- FreeRTOS -----------------------
 FREERTOS_SRC = lib/FreeRTOS-Kernel
-- 
cgit v1.3.1