From 3e428451535b4f5592c85b15970df1a2af2178e7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 9 Mar 2018 16:22:10 +0700
Subject: segger studio work with ea4357

---
 .../segger/LPC43xx_Registers.xml                   | 33526 +++++++++++++++++++
 1 file changed, 33526 insertions(+)
 create mode 100644 examples/device/device_virtual_com/segger/LPC43xx_Registers.xml

(limited to 'examples/device/device_virtual_com/segger/LPC43xx_Registers.xml')

diff --git a/examples/device/device_virtual_com/segger/LPC43xx_Registers.xml b/examples/device/device_virtual_com/segger/LPC43xx_Registers.xml
new file mode 100644
index 000000000..9c0946466
--- /dev/null
+++ b/examples/device/device_virtual_com/segger/LPC43xx_Registers.xml
@@ -0,0 +1,33526 @@
+<!DOCTYPE Register_Definition_File>
+<Processor name="LPC43xx" description="Register cmsis file for LPC43xx parts">
+  <RegisterGroup name="SCT" start="0x40000000" description="State Configurable Timer (SCT) with dither engine ">
+    <Register start="+0x000" size="4" name="CONFIG" access="Read/Write" description="SCT configuration register" reset_value="0x00007E00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="UNIFY" description="SCT operation">
+        <Enum name="16_BIT" start="0" description="16-bit.The SCT operates as two 16-bit counters named L and H." />
+        <Enum name="32_BIT" start="1" description="32-bit. The SCT operates as a unified 32-bit counter." />
+      </BitField>
+      <BitField start="1" size="2" name="CLKMODE" description="SCT clock mode">
+        <Enum name="BUS_CLOCK" start="0x0" description="Bus clock. The bus clock clocks the SCT and prescalers." />
+        <Enum name="PRESCALED_BUS_CLOCK" start="0x1" description="Prescaled bus clock. The SCT clock is the bus clock, but the prescalers are  enabled to count only when sampling of the input selected by  the CKSEL field finds the selected edge. The minimum pulse  width on the clock input is 1 bus clock period. This mode is the high-performance  sampled-clock mode." />
+        <Enum name="SCT_INPUT" start="0x2" description="SCT Input. The input selected by  CKSEL clocks the SCT and prescalers. The input is synchronized to the bus clock and possibly inverted.  The minimum pulse width on the clock input is 1 bus clock  period. This mode is the low-power sampled-clock mode." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="3" size="4" name="CKSEL" description="SCT clock select">
+        <Enum name="RISING_EDGES_ON_INPU" start="0x0" description="Rising edges on input 0." />
+        <Enum name="FALLING_EDGES_ON_INP" start="0x1" description="Falling edges on input 0." />
+        <Enum name="RISING_EDGES_ON_INPU" start="0x2" description="Rising edges on input 1." />
+        <Enum name="FALLING_EDGES_ON_INP" start="0x3" description="Falling edges on input 1." />
+        <Enum name="RISING_EDGES_ON_INPU" start="0x4" description="Rising edges on input 2." />
+        <Enum name="FALLING_EDGES_ON_INP" start="0x5" description="Falling edges on input 2." />
+        <Enum name="RISING_EDGES_ON_INPU" start="0x6" description="Rising edges on input 3." />
+        <Enum name="FALLING_EDGES_ON_INP" start="0x7" description="Falling edges on input 3." />
+        <Enum name="RISING_EDGES_ON_INPU" start="0x8" description="Rising edges on input 4." />
+        <Enum name="FALLING_EDGES_ON_INP" start="0x9" description="Falling edges on input 4." />
+        <Enum name="RISING_EDGES_ON_INPU" start="0xA" description="Rising edges on input 5." />
+        <Enum name="FALLING_EDGES_ON_INP" start="0xB" description="Falling edges on input 5." />
+        <Enum name="RISING_EDGES_ON_INPU" start="0xC" description="Rising edges on input 6." />
+        <Enum name="FALLING_EDGES_ON_INP" start="0xD" description="Falling edges on input 6." />
+        <Enum name="RISING_EDGES_ON_INPU" start="0xE" description="Rising edges on input 7." />
+        <Enum name="FALLING_EDGES_ON_INP" start="0xF" description="Falling edges on input 7." />
+      </BitField>
+      <BitField start="7" size="1" name="NORELAOD_L" description="A 1 in this bit prevents the lower match and fractional match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit applies to both the  higher and lower registers when the UNIFY bit is set." />
+      <BitField start="8" size="1" name="NORELOAD_H" description="A 1 in this bit prevents the higher match and fractional match registers from being  reloaded from their respective reload registers. Software can  write to set or clear this bit at any time. This bit is not used when  the UNIFY bit is set." />
+      <BitField start="9" size="8" name="INSYNC" description="Synchronization for input n (bit 9 = input 0, bit 10 = input 1,..., bit 16 = input 7). A 1 in one of these bits subjects the corresponding input to  synchronization to the SCT clock, before it is used to create an  event. If an input is synchronous to the SCT clock, keep its bit 0 for  faster response. When the CKMODE field is 1x, the bit in this field, corresponding  to the input selected by the CKSEL field, is not used." />
+      <BitField start="17" size="1" name="AUTOLIMIT_L" description="A one in this bit causes a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit  applies to both the higher and lower registers when the UNIFY bit  is set." />
+      <BitField start="18" size="1" name="AUTOLIMIT_H" description="A one in this bit will cause a match on match register 0 to be treated  as a de-facto LIMIT condition without the need to define an  associated event. As with any LIMIT event, this automatic limit causes the  counter to be cleared to zero in uni-directional mode or to change  the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is  not used when the UNIFY bit is set." />
+      <BitField start="19" size="13" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="SCT control register" reset_value="0x00040004" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DOWN_L" description="This bit is 1 when the L or unified counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs." />
+      <BitField start="1" size="1" name="STOP_L" description="When this bit is 1 and HALT is 0, the L or unified counter does not run but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes." />
+      <BitField start="2" size="1" name="HALT_L" description="When this bit is 1, the L or unified counter does not run and no events can occur.  A reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, only software can clear this bit to restore counter operation." />
+      <BitField start="3" size="1" name="CLRCTR_L" description="Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0." />
+      <BitField start="4" size="1" name="BIDIR_L" description="L or unified counter direction select">
+        <Enum name="UP" start="0" description="Up. The counter counts up to its limit condition, then is cleared to zero." />
+        <Enum name="UPDOWN" start="1" description="Up-down. The counter counts up to its limit, then counts down to a limit condition or to 0." />
+      </BitField>
+      <BitField start="5" size="8" name="PRE_L" description="Specifies the factor by which the SCT clock is prescaled to produce the  L or unified counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRE_L+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value." />
+      <BitField start="13" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="DOWN_H" description="This bit is 1 when the H counter is counting down. Hardware sets this bit   when the counter limit is reached and BIDIR is 1. Hardware clears this bit when the counter reaches 0 or when the counter is counting down and a limit condition occurs." />
+      <BitField start="17" size="1" name="STOP_H" description="When this bit is 1 and HALT is 0, the H counter does not run but I/O  events related to the counter can occur. If such an event matches  the mask in the Start register, this bit is cleared and counting  resumes." />
+      <BitField start="18" size="1" name="HALT_H" description="When this bit is 1, the H counter does not run and no events can occur.  A reset sets this bit. When the HALT_H bit is one, the STOP_H bit is cleared. If you want to remove the halt condition and keep the SCT in the stop condition (not running), then you can change the halt and stop condition with one single write to this register. Once set, this bit can only be cleared by software to restore counter operation." />
+      <BitField start="19" size="1" name="CLRCTR_H" description="Writing a 1 to this bit clears the H counter. This bit always reads as 0." />
+      <BitField start="20" size="1" name="BIDIR_H" description="Direction select">
+        <Enum name="UP" start="0" description="Up. The H counter counts up to its limit condition, then is cleared to zero." />
+        <Enum name="UPDOWN" start="1" description="Up-down. The H counter counts up to its limit, then counts down to a limit condition or to 0." />
+      </BitField>
+      <BitField start="21" size="8" name="PRE_H" description="Specifies the factor by which the SCT clock is prescaled to produce the  H counter clock. The counter clock is clocked at the rate of the SCT  clock divided by PRELH+1. Clear the counter (by writing a 1  to the CLRCTR bit) whenever changing the PRE value." />
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x008" size="4" name="LIMIT" access="Read/Write" description="SCT limit register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="LIMMSK_L" description="If bit n is one, event n is used as a counter limit event for the L or unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
+      <BitField start="16" size="16" name="LIMMSK_H" description="If bit n is one, event n is used as a counter limit event for the H counter (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x00C" size="4" name="HALT" access="Read/Write" description="SCT halt condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="HALTMSK_L" description="If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
+      <BitField start="16" size="16" name="HALTMSK_H" description="If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x010" size="4" name="STOP" access="Read/Write" description="SCT stop condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="STOPMSK_L" description="If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
+      <BitField start="16" size="16" name="STOPMSK_H" description="If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x014" size="4" name="START" access="Read/Write" description="SCT start condition register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="STARTMSK_L" description="If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15)." />
+      <BitField start="16" size="16" name="STARTMSK_H" description="If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit 16, event 1 = bit 17, event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x018" size="4" name="DITHER" access="Read/Write" description="SCT dither condition register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="16" name="DITHMSK_L" description="If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit low counter or the unified counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle." />
+      <BitField start="16" size="16" name="DITHMSK_H" description="If bit n is one, the event n causes the dither engine to advance to the next element in the dither pattern at the start of the next counter cycle of the 16-bit high counter (event 0 = bit 0, event 1 = bit 1, event 15 = bit 15). If all bits are set to 0, the dither pattern automatically advances at the start of every new counter cycle." />
+    </Register>
+    <Register start="+0x040" size="4" name="COUNT" access="Read/Write" description="SCT counter register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CTR_L" description="When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write the lower 16 bits of the 32-bit unified counter." />
+      <BitField start="16" size="16" name="CTR_H" description="When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write the upper 16 bits of the 32-bit unified counter." />
+    </Register>
+    <Register start="+0x044" size="4" name="STATE" access="Read/Write" description="SCT state register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="STATE_L" description="State variable." />
+      <BitField start="5" size="11" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="5" name="STATE_H" description="State variable." />
+      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x048" size="4" name="INPUT" access="ReadOnly" description="SCT input register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="AIN0" description="Real-time status of input 0." />
+      <BitField start="1" size="1" name="AIN1" description="Real-time status of input 1." />
+      <BitField start="2" size="1" name="AIN2" description="Real-time status of input 2." />
+      <BitField start="3" size="1" name="AIN3" description="Real-time status of input 3." />
+      <BitField start="4" size="1" name="AIN4" description="Real-time status of input 4." />
+      <BitField start="5" size="1" name="AIN5" description="Real-time status of input 5." />
+      <BitField start="6" size="1" name="AIN6" description="Real-time status of input 6." />
+      <BitField start="7" size="1" name="AIN7" description="Real-time status of input 7." />
+      <BitField start="8" size="8" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="1" name="SIN0" description="Input 0 state synchronized to the SCT clock." />
+      <BitField start="17" size="1" name="SIN1" description="Input 1 state synchronized to the SCT clock." />
+      <BitField start="18" size="1" name="SIN2" description="Input 2 state synchronized to the SCT clock." />
+      <BitField start="19" size="1" name="SIN3" description="Input 3 state synchronized to the SCT clock." />
+      <BitField start="20" size="1" name="SIN4" description="Input 4 state synchronized to the SCT clock." />
+      <BitField start="21" size="1" name="SIN5" description="Input 5 state synchronized to the SCT clock." />
+      <BitField start="22" size="1" name="SIN6" description="Input 6 state synchronized to the SCT clock." />
+      <BitField start="23" size="1" name="SIN7" description="Input 7 state synchronized to the SCT clock." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x04C" size="4" name="REGMODE" access="Read/Write" description="SCT match/capture registers mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="REGMOD_L" description="Each bit controls one pair of match/capture registers (register 0 = bit 0, register 1 = bit 1,..., register 15 = bit 15).  0 = registers operate as match registers. 1 = registers operate as capture registers." />
+      <BitField start="16" size="16" name="REGMOD_H" description="Each bit controls one pair of match/capture registers (register 0 = bit 16, register 1 = bit 17,..., register 15 = bit 31). 0 = registers operate as match registers. 1 = registers operate as capture registers." />
+    </Register>
+    <Register start="+0x050" size="4" name="OUTPUT" access="Read/Write" description="SCT output register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="OUT" description="Writing a 1 to bit n makes the corresponding output HIGH. 0 makes the corresponding output LOW (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x054" size="4" name="OUTPUTDIRCTRL" access="Read/Write" description="SCT output counter direction control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="SETCLR0" description="Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="2" size="2" name="SETCLR1" description="Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="4" size="2" name="SETCLR2" description="Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="6" size="2" name="SETCLR3" description="Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="8" size="2" name="SETCLR4" description="Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="10" size="2" name="SETCLR5" description="Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="12" size="2" name="SETCLR6" description="Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="14" size="2" name="SETCLR7" description="Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="16" size="2" name="SETCLR8" description="Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="18" size="2" name="SETCLR9" description="Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="20" size="2" name="SETCLR10" description="Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="22" size="2" name="SETCLR11" description="Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="24" size="2" name="SETCLR12" description="Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="26" size="2" name="SETCLR13" description="Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="28" size="2" name="SETCLR14" description="Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+      <BitField start="30" size="2" name="SETCLR15" description="Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.">
+        <Enum name="INDEPENDENT" start="0x0" description="Independent. Set and clear do not depend on any counter." />
+        <Enum name="L_COUNTER" start="0x1" description="L counter. Set and clear are reversed when counter L or the unified counter is counting down." />
+        <Enum name="H_COUNTER" start="0x2" description="H counter. Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1." />
+      </BitField>
+    </Register>
+    <Register start="+0x058" size="4" name="RES" access="Read/Write" description="SCT conflict resolution register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="O0RES" description="Effect of simultaneous set and clear on output 0.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR0 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR0 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="2" size="2" name="O1RES" description="Effect of simultaneous set and clear on output 1.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR1 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR1 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="4" size="2" name="O2RES" description="Effect of simultaneous set and clear on output 2.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR2 field)." />
+        <Enum name="CLEAR_OUTPUT_N_OR_S" start="0x2" description="Clear output n (or set based on the SETCLR2 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="6" size="2" name="O3RES" description="Effect of simultaneous set and clear on output 3.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR3 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR3 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="8" size="2" name="O4RES" description="Effect of simultaneous set and clear on output 4.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR4 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR4 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="10" size="2" name="O5RES" description="Effect of simultaneous set and clear on output 5.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR5 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR5 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="12" size="2" name="O6RES" description="Effect of simultaneous set and clear on output 6.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR6 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR6 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="14" size="2" name="O7RES" description="Effect of simultaneous set and clear on output 7.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR7 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR7 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="16" size="2" name="O8RES" description="Effect of simultaneous set and clear on output 8.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR8 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR8 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="18" size="2" name="O9RES" description="Effect of simultaneous set and clear on output 9.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR9 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR9 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="20" size="2" name="O10RES" description="Effect of simultaneous set and clear on output 10.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR10 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR10 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="22" size="2" name="O11RES" description="Effect of simultaneous set and clear on output 11.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR11 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR11 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="24" size="2" name="O12RES" description="Effect of simultaneous set and clear on output 12.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR12 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR12 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="26" size="2" name="O13RES" description="Effect of simultaneous set and clear on output 13.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR13 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR13 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="28" size="2" name="O14RES" description="Effect of simultaneous set and clear on output 14.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR14 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR14 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+      <BitField start="30" size="2" name="O15RES" description="Effect of simultaneous set and clear on output 15.">
+        <Enum name="NO_CHANGE" start="0x0" description="No change." />
+        <Enum name="SET_OUTPUT_OR_CLEAR" start="0x1" description="Set output (or clear based on the SETCLR15 field)." />
+        <Enum name="CLEAR_OUTPUT_OR_SET" start="0x2" description="Clear output (or set based on the SETCLR15 field)." />
+        <Enum name="TOGGLE_OUTPUT" start="0x3" description="Toggle output." />
+      </BitField>
+    </Register>
+    <Register start="+0x05C" size="4" name="DMAREQ0" access="Read/Write" description="SCT DMA request 0 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DEV_00" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="1" size="1" name="DEV_01" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="2" size="1" name="DEV_02" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="3" size="1" name="DEV_03" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="4" size="1" name="DEV_04" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="5" size="1" name="DEV_05" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="6" size="1" name="DEV_06" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="7" size="1" name="DEV_07" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="8" size="1" name="DEV_08" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="9" size="1" name="DEV_09" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="10" size="1" name="DEV_010" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="11" size="1" name="DEV_011" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="12" size="1" name="DEV_012" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="13" size="1" name="DEV_013" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="14" size="1" name="DEV_014" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="15" size="1" name="DEV_015" description="If bit n is one, event n sets DMA request 0 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="1" name="DRL0" description="A 1 in this bit makes the SCT set DMA request 0 when it loads the  Match_L/Unified registers from the Reload_L/Unified registers." />
+      <BitField start="31" size="1" name="DRQ0" description="This read-only bit indicates the state of DMA Request 0" />
+    </Register>
+    <Register start="+0x060" size="4" name="DMAREQ1" access="Read/Write" description="SCT DMA request 1 register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DEV_10" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="1" size="1" name="DEV_11" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="2" size="1" name="DEV_12" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="3" size="1" name="DEV_13" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="4" size="1" name="DEV_14" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="5" size="1" name="DEV_15" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="6" size="1" name="DEV_16" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="7" size="1" name="DEV_17" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="8" size="1" name="DEV_18" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="9" size="1" name="DEV_19" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="10" size="1" name="DEV_110" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="11" size="1" name="DEV_111" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="12" size="1" name="DEV_112" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="13" size="1" name="DEV_113" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="14" size="1" name="DEV_114" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="15" size="1" name="DEV_115" description="If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="1" name="DRL1" description="A 1 in this bit makes the SCT set DMA request 1 when it loads the  Match L/Unified registers from the Reload L/Unified registers." />
+      <BitField start="31" size="1" name="DRQ1" description="This read-only bit indicates the state of DMA Request 1." />
+    </Register>
+    <Register start="+0x0F0" size="4" name="EVEN" access="Read/Write" description="SCT event enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="IEN0" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="1" size="1" name="IEN1" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="2" size="1" name="IEN2" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="3" size="1" name="IEN3" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="4" size="1" name="IEN4" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="5" size="1" name="IEN5" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="6" size="1" name="IEN6" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="7" size="1" name="IEN7" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="8" size="1" name="IEN8" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="9" size="1" name="IEN9" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="10" size="1" name="IEN10" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="11" size="1" name="IEN11" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="12" size="1" name="IEN12" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="13" size="1" name="IEN13" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="14" size="1" name="IEN14" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="15" size="1" name="IEN15" description="The SCT requests interrupt when bit n of this register and the event flag register are both one (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0F4" size="4" name="EVFLAG" access="Read/Write" description="SCT event flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FLAG0" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="1" size="1" name="FLAG1" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="2" size="1" name="FLAG2" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="3" size="1" name="FLAG3" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="4" size="1" name="FLAG4" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="5" size="1" name="FLAG5" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="6" size="1" name="FLAG6" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="7" size="1" name="FLAG7" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="8" size="1" name="FLAG8" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="9" size="1" name="FLAG9" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="10" size="1" name="FLAG10" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="11" size="1" name="FLAG11" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="12" size="1" name="FLAG12" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="13" size="1" name="FLAG13" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="14" size="1" name="FLAG14" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="15" size="1" name="FLAG15" description="Bit n is one if event n has occurred since reset or a 1 was last written to this bit (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0F8" size="4" name="CONEN" access="Read/Write" description="SCT conflict enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="NCEN0" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="1" size="1" name="NCEN1" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="2" size="1" name="NCEN2" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="3" size="1" name="NCEN3" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="4" size="1" name="NCEN4" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="5" size="1" name="NCEN5" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="6" size="1" name="NCEN6" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="7" size="1" name="NCEN7" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="8" size="1" name="NCEN8" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="9" size="1" name="NCEN9" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="10" size="1" name="NCEN10" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="11" size="1" name="NCEN11" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="12" size="1" name="NCEN12" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="13" size="1" name="NCEN13" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="14" size="1" name="NCEN14" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="15" size="1" name="NCEN15" description="The SCT requests interrupt when bit n of this register and the SCT conflict flag register are both one (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0FC" size="4" name="CONFLAG" access="Read/Write" description="SCT conflict flag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="NCFLAG0" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="1" size="1" name="NCFLAG1" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="2" size="1" name="NCFLAG2" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="3" size="1" name="NCFLAG3" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="4" size="1" name="NCFLAG4" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="5" size="1" name="NCFLAG5" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="6" size="1" name="NCFLAG6" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="7" size="1" name="NCFLAG7" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="8" size="1" name="NCFLAG8" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="9" size="1" name="NCFLAG9" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="10" size="1" name="NCFLAG10" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="11" size="1" name="NCFLAG11" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="12" size="1" name="NCFLAG12" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="13" size="1" name="NCFLAG13" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="14" size="1" name="NCFLAG14" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="15" size="1" name="NCFLAG15" description="Bit n is one if a no-change conflict event occurred on output n since  reset or a 1 was last written to this bit (output 0 = bit 0, output 1 = bit 1,..., output 15 = bit 15)." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved." />
+      <BitField start="30" size="1" name="BUSERRL" description="The most recent bus error from this SCT involved writing CTR  L/Unified, STATE L/Unified, MATCH L/Unified, or the Output register when the  L/U counter was not halted. A word write to certain L  and H registers can be half successful and half unsuccessful." />
+      <BitField start="31" size="1" name="BUSERRH" description="The most recent bus error from this SCT involved writing CTR H,  STATE H, MATCH H, or the Output register when the H  counter was not halted." />
+    </Register>
+    <Register start="+0x100+0" size="4" name="MATCH0" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+4" size="4" name="MATCH1" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+8" size="4" name="MATCH2" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+12" size="4" name="MATCH3" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+16" size="4" name="MATCH4" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+20" size="4" name="MATCH5" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+24" size="4" name="MATCH6" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+28" size="4" name="MATCH7" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+32" size="4" name="MATCH8" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+36" size="4" name="MATCH9" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+40" size="4" name="MATCH10" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+44" size="4" name="MATCH11" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+48" size="4" name="MATCH12" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+52" size="4" name="MATCH13" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+56" size="4" name="MATCH14" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x100+60" size="4" name="MATCH15" access="Read/Write" description="SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MATCH_L" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the L counter. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified counter." />
+      <BitField start="16" size="16" name="MATCH_H" description="When UNIFY = 0, read or write the 16-bit value to be  compared to the H counter. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified counter." />
+    </Register>
+    <Register start="+0x140+0" size="4" name="FRACMAT0" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x140+4" size="4" name="FRACMAT1" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x140+8" size="4" name="FRACMAT2" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x140+12" size="4" name="FRACMAT3" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x140+16" size="4" name="FRACMAT4" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x140+20" size="4" name="FRACMAT5" access="Read/Write" description="Fractional match registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="FRACMAT_L" description="When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="FRACMAT_H" description="When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5)." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x100+0" size="4" name="CAP0" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+4" size="4" name="CAP1" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+8" size="4" name="CAP2" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+12" size="4" name="CAP3" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+16" size="4" name="CAP4" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+20" size="4" name="CAP5" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+24" size="4" name="CAP6" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+28" size="4" name="CAP7" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+32" size="4" name="CAP8" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+36" size="4" name="CAP9" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+40" size="4" name="CAP10" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+44" size="4" name="CAP11" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+48" size="4" name="CAP12" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+52" size="4" name="CAP13" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+56" size="4" name="CAP14" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x100+60" size="4" name="CAP15" access="Read/Write" description="SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAP_L" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last captured." />
+      <BitField start="16" size="16" name="CAP_H" description="When UNIFY = 0, read the 16-bit counter value at which this register was last captured. When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last captured." />
+    </Register>
+    <Register start="+0x200+0" size="4" name="MATCHREL0" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+4" size="4" name="MATCHREL1" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+8" size="4" name="MATCHREL2" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+12" size="4" name="MATCHREL3" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+16" size="4" name="MATCHREL4" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+20" size="4" name="MATCHREL5" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+24" size="4" name="MATCHREL6" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+28" size="4" name="MATCHREL7" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+32" size="4" name="MATCHREL8" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+36" size="4" name="MATCHREL9" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+40" size="4" name="MATCHREL10" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+44" size="4" name="MATCHREL11" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+48" size="4" name="MATCHREL12" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+52" size="4" name="MATCHREL13" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+56" size="4" name="MATCHREL14" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x200+60" size="4" name="MATCHREL15" access="Read/Write" description="SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="RELOAD_L" description="When UNIFY = 0, read or write the 16-bit value to be loaded into the MATCHn_L register. When UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+      <BitField start="16" size="16" name="RELOAD_H" description="When UNIFY = 0, read or write the 16-bit to be loaded into the MATCHn_H register. When UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be loaded into the MATCHn register." />
+    </Register>
+    <Register start="+0x240+0" size="4" name="FRACMATREL0" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x240+4" size="4" name="FRACMATREL1" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x240+8" size="4" name="FRACMATREL2" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x240+12" size="4" name="FRACMATREL3" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x240+16" size="4" name="FRACMATREL4" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x240+20" size="4" name="FRACMATREL5" access="Read/Write" description="Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="RELFRAC_L" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_L register. When UNIFY = 1, read or write the lower 4 bits to be loaded into the FRACMATn register." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="4" name="RELFRAC_H" description="When UNIFY = 0, read or write the 4-bit value to be loaded into the FRACMATn_H register. When UNIFY = 1, read or write the upper 4 bits with the 4-bit value to be loaded into the FRACMATn register." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x200+0" size="4" name="CAPCTRL0" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+4" size="4" name="CAPCTRL1" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+8" size="4" name="CAPCTRL2" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+12" size="4" name="CAPCTRL3" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+16" size="4" name="CAPCTRL4" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+20" size="4" name="CAPCTRL5" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+24" size="4" name="CAPCTRL6" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+28" size="4" name="CAPCTRL7" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+32" size="4" name="CAPCTRL8" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+36" size="4" name="CAPCTRL9" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+40" size="4" name="CAPCTRL10" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+44" size="4" name="CAPCTRL11" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+48" size="4" name="CAPCTRL12" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+52" size="4" name="CAPCTRL13" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+56" size="4" name="CAPCTRL14" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x200+60" size="4" name="CAPCTRL15" access="Read/Write" description="SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CAPCON_L" description="If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15)." />
+      <BitField start="16" size="16" name="CAPCON_H" description="If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event 15 = bit 31)." />
+    </Register>
+    <Register start="+0x300+0" size="4" name="EV0_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+8" size="4" name="EV1_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+16" size="4" name="EV2_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+24" size="4" name="EV3_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+32" size="4" name="EV4_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+40" size="4" name="EV5_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+48" size="4" name="EV6_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+56" size="4" name="EV7_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+64" size="4" name="EV8_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+72" size="4" name="EV9_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+80" size="4" name="EV10_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+88" size="4" name="EV11_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+96" size="4" name="EV12_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+104" size="4" name="EV13_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+112" size="4" name="EV14_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x300+120" size="4" name="EV15_STATE" access="Read/Write" description="SCT event state register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STATEMSK0" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="1" size="1" name="STATEMSK1" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="2" size="1" name="STATEMSK2" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="3" size="1" name="STATEMSK3" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="4" size="1" name="STATEMSK4" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="5" size="1" name="STATEMSK5" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="6" size="1" name="STATEMSK6" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="7" size="1" name="STATEMSK7" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="8" size="1" name="STATEMSK8" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="9" size="1" name="STATEMSK9" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="10" size="1" name="STATEMSK10" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="11" size="1" name="STATEMSK11" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="12" size="1" name="STATEMSK12" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="13" size="1" name="STATEMSK13" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="14" size="1" name="STATEMSK14" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="15" size="1" name="STATEMSK15" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="16" size="1" name="STATEMSK16" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="17" size="1" name="STATEMSK17" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="18" size="1" name="STATEMSK18" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="19" size="1" name="STATEMSK19" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="20" size="1" name="STATEMSK20" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="21" size="1" name="STATEMSK21" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="22" size="1" name="STATEMSK22" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="23" size="1" name="STATEMSK23" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="24" size="1" name="STATEMSK24" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="25" size="1" name="STATEMSK25" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="26" size="1" name="STATEMSK26" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="27" size="1" name="STATEMSK27" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="28" size="1" name="STATEMSK28" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="29" size="1" name="STATEMSK29" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="30" size="1" name="STATEMSK30" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+      <BitField start="31" size="1" name="STATEMSK31" description="If bit m is one, event n (n= 0 to 15) happens in state m of the counter selected by the HEVENT bit (m = state number; state 0 = bit 0, state 1= bit 1,..., state 31 = bit 31)." />
+    </Register>
+    <Register start="+0x304+0" size="4" name="EV0_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+8" size="4" name="EV1_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+16" size="4" name="EV2_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+24" size="4" name="EV3_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+32" size="4" name="EV4_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+40" size="4" name="EV5_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+48" size="4" name="EV6_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+56" size="4" name="EV7_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+64" size="4" name="EV8_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+72" size="4" name="EV9_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+80" size="4" name="EV10_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+88" size="4" name="EV11_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+96" size="4" name="EV12_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+104" size="4" name="EV13_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+112" size="4" name="EV14_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304+120" size="4" name="EV15_CTRL" access="Read/Write" description="SCT event control register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MATCHSEL" description="Selects the Match register associated with this event (if any). A  match can occur only when the counter selected by the HEVENT  bit is running." />
+      <BitField start="4" size="1" name="HEVENT" description="Select L/H counter. Do not set this bit if UNIFY = 1.">
+        <Enum name="L_STATE" start="0" description="L state. Selects the L state and the L match register selected by MATCHSEL." />
+        <Enum name="H_STATE" start="1" description="H state. Selects the H state and the H match register selected by MATCHSEL." />
+      </BitField>
+      <BitField start="5" size="1" name="OUTSEL" description="Input/output select">
+        <Enum name="INPUT" start="0" description="Input. Selects the input selected by IOSEL." />
+        <Enum name="OUTPUT" start="1" description="Output. Selects the output selected by IOSEL." />
+      </BitField>
+      <BitField start="6" size="4" name="IOSEL" description="Selects the input or output signal associated with this event (if  any). Do not select an input in this register, if CKMODE is 1x. In this case the clock input is an implicit ingredient of  every event." />
+      <BitField start="10" size="2" name="IOCOND" description="Selects the I/O condition for event n. (The detection of edges on outputs lags the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT  clock period .">
+        <Enum name="LOW" start="0x0" description="LOW" />
+        <Enum name="RISE" start="0x1" description="Rise" />
+        <Enum name="FALL" start="0x2" description="Fall" />
+        <Enum name="HIGH" start="0x3" description="HIGH" />
+      </BitField>
+      <BitField start="12" size="2" name="COMBMODE" description="Selects how the specified match and I/O condition are used and combined.">
+        <Enum name="OR" start="0x0" description="OR. The event occurs when either the specified match or I/O condition occurs." />
+        <Enum name="MATCH" start="0x1" description="MATCH. Uses the specified match only." />
+        <Enum name="IO" start="0x2" description="IO. Uses the specified I/O condition only." />
+        <Enum name="AND" start="0x3" description="AND. The event occurs when the specified match and I/O condition occur simultaneously." />
+      </BitField>
+      <BitField start="14" size="1" name="STATELD" description="This bit controls how the STATEV value modifies the state  selected by HEVENT when this event is the highest-numbered  event occurring for that state.">
+        <Enum name="STATEV_VALUE_IS_ADDE" start="0" description="STATEV value is added into STATE (the carry-out is ignored)." />
+        <Enum name="STATEV_VALUE_IS_LOAD" start="1" description="STATEV value is loaded into STATE." />
+      </BitField>
+      <BitField start="15" size="5" name="STATEV" description="This value is loaded into or added to the state selected by  HEVENT, depending on STATELD, when this event is the  highest-numbered event occurring for that state. If STATELD and  STATEV are both zero, there is no change to the STATE value." />
+      <BitField start="20" size="1" name="MATCHMEM" description="If this bit is one and the COMBMODE field specifies a match  component to the triggering of this event, then a match is considered to be active whenever the counter value is  GREATER THAN OR EQUAL TO the value specified in the  match register when counting up, LESS THEN OR EQUAL TO  the match value when counting down. If this bit is zero, a match is only be active during the cycle  when the counter is equal to the match value." />
+      <BitField start="21" size="2" name="DIRECTION" description="Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR  mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.">
+        <Enum name="DIRECTION_INDEPENDEN" start="0x0" description="Direction independent. This event is triggered regardless of the count direction." />
+        <Enum name="COUNTING_UP" start="0x1" description="Counting up. This event is triggered only during up-counting when BIDIR = 1." />
+        <Enum name="COUNTING_DOWN" start="0x2" description="Counting down. This event is triggered only during down-counting when BIDIR = 1." />
+      </BitField>
+      <BitField start="23" size="9" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+0" size="4" name="OUT0_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+8" size="4" name="OUT1_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+16" size="4" name="OUT2_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+24" size="4" name="OUT3_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+32" size="4" name="OUT4_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+40" size="4" name="OUT5_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+48" size="4" name="OUT6_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+56" size="4" name="OUT7_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+64" size="4" name="OUT8_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+72" size="4" name="OUT9_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+80" size="4" name="OUT10_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+88" size="4" name="OUT11_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+96" size="4" name="OUT12_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+104" size="4" name="OUT13_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+112" size="4" name="OUT14_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500+120" size="4" name="OUT15_SET" access="Read/Write" description="SCT output 0 set register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET0" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="SET1" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="SET2" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="SET3" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="SET4" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="SET5" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="SET6" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="SET7" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="SET8" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="SET9" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="SET10" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="SET11" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="SET12" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="SET13" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="SET14" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="SET15" description="A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+0" size="4" name="OUT0_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+8" size="4" name="OUT1_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+16" size="4" name="OUT2_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+24" size="4" name="OUT3_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+32" size="4" name="OUT4_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+40" size="4" name="OUT5_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+48" size="4" name="OUT6_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+56" size="4" name="OUT7_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+64" size="4" name="OUT8_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+72" size="4" name="OUT9_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+80" size="4" name="OUT10_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+88" size="4" name="OUT11_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+96" size="4" name="OUT12_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+104" size="4" name="OUT13_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+112" size="4" name="OUT14_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+120" size="4" name="OUT15_CLR" access="Read/Write" description="SCT output 0 clear register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR0" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="1" size="1" name="CLR1" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="2" size="1" name="CLR2" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="3" size="1" name="CLR3" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="4" size="1" name="CLR4" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="5" size="1" name="CLR5" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="6" size="1" name="CLR6" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="7" size="1" name="CLR7" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="8" size="1" name="CLR8" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="9" size="1" name="CLR9" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="10" size="1" name="CLR10" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="11" size="1" name="CLR11" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="12" size="1" name="CLR12" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="13" size="1" name="CLR13" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="14" size="1" name="CLR14" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="15" size="1" name="CLR15" description="A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPDMA" start="0x40002000" description="General Purpose DMA (GPDMA) ">
+    <Register start="+0x000" size="4" name="INTSTAT" access="ReadOnly" description="DMA Interrupt Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTSTAT0" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="1" size="1" name="INTSTAT1" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="2" size="1" name="INTSTAT2" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="3" size="1" name="INTSTAT3" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="4" size="1" name="INTSTAT4" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="5" size="1" name="INTSTAT5" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="6" size="1" name="INTSTAT6" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="7" size="1" name="INTSTAT7" description="Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
+    </Register>
+    <Register start="+0x004" size="4" name="INTTCSTAT" access="ReadOnly" description="DMA Interrupt Terminal Count Request Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTTCSTAT0" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="1" size="1" name="INTTCSTAT1" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="2" size="1" name="INTTCSTAT2" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="3" size="1" name="INTTCSTAT3" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="4" size="1" name="INTTCSTAT4" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="5" size="1" name="INTTCSTAT5" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="6" size="1" name="INTTCSTAT6" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="7" size="1" name="INTTCSTAT7" description="Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
+    </Register>
+    <Register start="+0x008" size="4" name="INTTCCLEAR" access="WriteOnly" description="DMA Interrupt Terminal Count Request Clear Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="INTTCCLEAR0" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="1" size="1" name="INTTCCLEAR1" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="2" size="1" name="INTTCCLEAR2" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="3" size="1" name="INTTCCLEAR3" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="4" size="1" name="INTTCCLEAR4" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="5" size="1" name="INTTCCLEAR5" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="6" size="1" name="INTTCCLEAR6" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="7" size="1" name="INTTCCLEAR7" description="Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
+    </Register>
+    <Register start="+0x00C" size="4" name="INTERRSTAT" access="ReadOnly" description="DMA Interrupt Error Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTERRSTAT0" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="1" size="1" name="INTERRSTAT1" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="2" size="1" name="INTERRSTAT2" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="3" size="1" name="INTERRSTAT3" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="4" size="1" name="INTERRSTAT4" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="5" size="1" name="INTERRSTAT5" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="6" size="1" name="INTERRSTAT6" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="7" size="1" name="INTERRSTAT7" description="Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
+    </Register>
+    <Register start="+0x010" size="4" name="INTERRCLR" access="WriteOnly" description="DMA Interrupt Error Clear Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="INTERRCLR0" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="1" size="1" name="INTERRCLR1" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="2" size="1" name="INTERRCLR2" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="3" size="1" name="INTERRCLR3" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="4" size="1" name="INTERRCLR4" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="5" size="1" name="INTERRCLR5" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="6" size="1" name="INTERRCLR6" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="7" size="1" name="INTERRCLR7" description="Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
+    </Register>
+    <Register start="+0x014" size="4" name="RAWINTTCSTAT" access="ReadOnly" description="DMA Raw Interrupt Terminal Count Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RAWINTTCSTAT0" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="1" size="1" name="RAWINTTCSTAT1" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="2" size="1" name="RAWINTTCSTAT2" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="3" size="1" name="RAWINTTCSTAT3" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="4" size="1" name="RAWINTTCSTAT4" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="5" size="1" name="RAWINTTCSTAT5" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="6" size="1" name="RAWINTTCSTAT6" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="7" size="1" name="RAWINTTCSTAT7" description="Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
+    </Register>
+    <Register start="+0x018" size="4" name="RAWINTERRSTAT" access="ReadOnly" description="DMA Raw Error Interrupt Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RAWINTERRSTAT0" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="1" size="1" name="RAWINTERRSTAT1" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="2" size="1" name="RAWINTERRSTAT2" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="3" size="1" name="RAWINTERRSTAT3" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="4" size="1" name="RAWINTERRSTAT4" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="5" size="1" name="RAWINTERRSTAT5" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="6" size="1" name="RAWINTERRSTAT6" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="7" size="1" name="RAWINTERRSTAT7" description="Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="ENBLDCHNS" access="ReadOnly" description="DMA Enabled Channel Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENABLEDCHANNELS0" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="1" size="1" name="ENABLEDCHANNELS1" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="2" size="1" name="ENABLEDCHANNELS2" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="3" size="1" name="ENABLEDCHANNELS3" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="4" size="1" name="ENABLEDCHANNELS4" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="5" size="1" name="ENABLEDCHANNELS5" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="6" size="1" name="ENABLEDCHANNELS6" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="7" size="1" name="ENABLEDCHANNELS7" description="Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. Read undefined." />
+    </Register>
+    <Register start="+0x020" size="4" name="SOFTBREQ" access="Read/Write" description="DMA Software Burst Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SOFTBREQ0" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="1" size="1" name="SOFTBREQ1" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="2" size="1" name="SOFTBREQ2" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="3" size="1" name="SOFTBREQ3" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="4" size="1" name="SOFTBREQ4" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="5" size="1" name="SOFTBREQ5" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="6" size="1" name="SOFTBREQ6" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="7" size="1" name="SOFTBREQ7" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="8" size="1" name="SOFTBREQ8" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="9" size="1" name="SOFTBREQ9" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="10" size="1" name="SOFTBREQ10" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="11" size="1" name="SOFTBREQ11" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="12" size="1" name="SOFTBREQ12" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="13" size="1" name="SOFTBREQ13" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="14" size="1" name="SOFTBREQ14" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="15" size="1" name="SOFTBREQ15" description="Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function (refer to Table 136 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
+    </Register>
+    <Register start="+0x024" size="4" name="SOFTSREQ" access="Read/Write" description="DMA Software Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SOFTSREQ0" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="1" size="1" name="SOFTSREQ1" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="2" size="1" name="SOFTSREQ2" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="3" size="1" name="SOFTSREQ3" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="4" size="1" name="SOFTSREQ4" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="5" size="1" name="SOFTSREQ5" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="6" size="1" name="SOFTSREQ6" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="7" size="1" name="SOFTSREQ7" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="8" size="1" name="SOFTSREQ8" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="9" size="1" name="SOFTSREQ9" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="10" size="1" name="SOFTSREQ10" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="11" size="1" name="SOFTSREQ11" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="12" size="1" name="SOFTSREQ12" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="13" size="1" name="SOFTSREQ13" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="14" size="1" name="SOFTSREQ14" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="15" size="1" name="SOFTSREQ15" description="Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
+    </Register>
+    <Register start="+0x028" size="4" name="SOFTLBREQ" access="Read/Write" description="DMA Software Last Burst Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SOFTLBREQ0" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="1" size="1" name="SOFTLBREQ1" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="2" size="1" name="SOFTLBREQ2" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="3" size="1" name="SOFTLBREQ3" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="4" size="1" name="SOFTLBREQ4" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="5" size="1" name="SOFTLBREQ5" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="6" size="1" name="SOFTLBREQ6" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="7" size="1" name="SOFTLBREQ7" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="8" size="1" name="SOFTLBREQ8" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="9" size="1" name="SOFTLBREQ9" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="10" size="1" name="SOFTLBREQ10" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="11" size="1" name="SOFTLBREQ11" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="12" size="1" name="SOFTLBREQ12" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="13" size="1" name="SOFTLBREQ13" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="14" size="1" name="SOFTLBREQ14" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="15" size="1" name="SOFTLBREQ15" description="Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
+    </Register>
+    <Register start="+0x02C" size="4" name="SOFTLSREQ" access="Read/Write" description="DMA Software Last Single Request Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SOFTLSREQ0" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="1" size="1" name="SOFTLSREQ1" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="2" size="1" name="SOFTLSREQ2" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="3" size="1" name="SOFTLSREQ3" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="4" size="1" name="SOFTLSREQ4" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="5" size="1" name="SOFTLSREQ5" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="6" size="1" name="SOFTLSREQ6" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="7" size="1" name="SOFTLSREQ7" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="8" size="1" name="SOFTLSREQ8" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="9" size="1" name="SOFTLSREQ9" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="10" size="1" name="SOFTLSREQ10" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="11" size="1" name="SOFTLSREQ11" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="12" size="1" name="SOFTLSREQ12" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="13" size="1" name="SOFTLSREQ13" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="14" size="1" name="SOFTLSREQ14" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="15" size="1" name="SOFTLSREQ15" description="Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
+    </Register>
+    <Register start="+0x030" size="4" name="CONFIG" access="Read/Write" description="DMA Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="DMA Controller enable:">
+        <Enum name="DISABLED__DEFAULT_" start="0" description="Disabled (default). Disabling the DMA Controller reduces power consumption." />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="1" size="1" name="M0" description="AHB Master 0 endianness configuration:">
+        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode (default)." />
+        <Enum name="BIG_ENDIAN_MODE_" start="1" description="Big-endian mode." />
+      </BitField>
+      <BitField start="2" size="1" name="M1" description="AHB Master 1 endianness configuration:">
+        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode (default)." />
+        <Enum name="BIG_ENDIAN_MODE_" start="1" description="Big-endian mode." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
+    </Register>
+    <Register start="+0x034" size="4" name="SYNC" access="Read/Write" description="DMA Synchronization Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DMACSYNC0" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="1" size="1" name="DMACSYNC1" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="2" size="1" name="DMACSYNC2" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="3" size="1" name="DMACSYNC3" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="4" size="1" name="DMACSYNC4" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="5" size="1" name="DMACSYNC5" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="6" size="1" name="DMACSYNC6" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="7" size="1" name="DMACSYNC7" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="8" size="1" name="DMACSYNC8" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="9" size="1" name="DMACSYNC9" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="10" size="1" name="DMACSYNC10" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="11" size="1" name="DMACSYNC11" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="12" size="1" name="DMACSYNC12" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="13" size="1" name="DMACSYNC13" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="14" size="1" name="DMACSYNC14" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="15" size="1" name="DMACSYNC15" description="Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text:&#xa;0 - synchronization logic for the corresponding DMA request signals are enabled.&#xa;1 - synchronization logic for the corresponding request line signals are disabled." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read undefined. Write reserved bits as zero." />
+    </Register>
+    <Register start="+0x100+0" size="4" name="C0SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+32" size="4" name="C1SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+64" size="4" name="C2SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+96" size="4" name="C3SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+128" size="4" name="C4SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+160" size="4" name="C5SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+192" size="4" name="C6SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x100+224" size="4" name="C7SRCADDR" access="Read/Write" description="DMA Channel  Source Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRCADDR" description="DMA source address. Reading this register will return the current source address." />
+    </Register>
+    <Register start="+0x104+0" size="4" name="C0DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+32" size="4" name="C1DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+64" size="4" name="C2DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+96" size="4" name="C3DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+128" size="4" name="C4DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+160" size="4" name="C5DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+192" size="4" name="C6DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x104+224" size="4" name="C7DESTADDR" access="Read/Write" description="DMA Channel  Destination Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DESTADDR" description="DMA Destination address. Reading this register will return the current destination address." />
+    </Register>
+    <Register start="+0x108+0" size="4" name="C0LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
+        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
+        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
+      </BitField>
+      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+32" size="4" name="C1LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
+        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
+        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
+      </BitField>
+      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+64" size="4" name="C2LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
+        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
+        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
+      </BitField>
+      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+96" size="4" name="C3LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
+        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
+        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
+      </BitField>
+      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+128" size="4" name="C4LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
+        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
+        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
+      </BitField>
+      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+160" size="4" name="C5LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
+        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
+        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
+      </BitField>
+      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+192" size="4" name="C6LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
+        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
+        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
+      </BitField>
+      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x108+224" size="4" name="C7LLI" access="Read/Write" description="DMA Channel Linked List Item Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LM" description="AHB master select for loading the next LLI:">
+        <Enum name="AHB_MASTER_0_" start="0" description="AHB Master 0." />
+        <Enum name="AHB_MASTER_1_" start="1" description="AHB Master 1." />
+      </BitField>
+      <BitField start="1" size="1" name="R" description="Reserved, and must be written as 0, masked on read." />
+      <BitField start="2" size="30" name="LLI" description="Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0." />
+    </Register>
+    <Register start="+0x10C+0" size="4" name="C0CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
+        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
+        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
+        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
+        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
+        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
+        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
+        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
+        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
+      </BitField>
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
+        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
+        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
+        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
+        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
+        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
+        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
+        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
+        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
+      </BitField>
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="24" size="1" name="S" description="Source AHB master select:">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
+      </BitField>
+      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
+      </BitField>
+      <BitField start="26" size="1" name="SI" description="Source increment:">
+        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
+        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
+      </BitField>
+      <BitField start="27" size="1" name="DI" description="Destination increment:">
+        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
+        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
+      </BitField>
+      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
+        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
+        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
+      </BitField>
+      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
+        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
+        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
+      </BitField>
+      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
+        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
+        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
+      </BitField>
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
+        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
+        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
+      </BitField>
+    </Register>
+    <Register start="+0x10C+32" size="4" name="C1CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
+        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
+        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
+        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
+        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
+        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
+        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
+        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
+        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
+      </BitField>
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
+        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
+        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
+        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
+        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
+        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
+        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
+        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
+        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
+      </BitField>
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="24" size="1" name="S" description="Source AHB master select:">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
+      </BitField>
+      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
+      </BitField>
+      <BitField start="26" size="1" name="SI" description="Source increment:">
+        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
+        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
+      </BitField>
+      <BitField start="27" size="1" name="DI" description="Destination increment:">
+        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
+        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
+      </BitField>
+      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
+        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
+        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
+      </BitField>
+      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
+        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
+        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
+      </BitField>
+      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
+        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
+        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
+      </BitField>
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
+        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
+        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
+      </BitField>
+    </Register>
+    <Register start="+0x10C+64" size="4" name="C2CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
+        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
+        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
+        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
+        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
+        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
+        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
+        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
+        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
+      </BitField>
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
+        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
+        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
+        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
+        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
+        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
+        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
+        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
+        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
+      </BitField>
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="24" size="1" name="S" description="Source AHB master select:">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
+      </BitField>
+      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
+      </BitField>
+      <BitField start="26" size="1" name="SI" description="Source increment:">
+        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
+        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
+      </BitField>
+      <BitField start="27" size="1" name="DI" description="Destination increment:">
+        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
+        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
+      </BitField>
+      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
+        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
+        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
+      </BitField>
+      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
+        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
+        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
+      </BitField>
+      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
+        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
+        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
+      </BitField>
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
+        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
+        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
+      </BitField>
+    </Register>
+    <Register start="+0x10C+96" size="4" name="C3CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
+        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
+        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
+        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
+        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
+        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
+        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
+        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
+        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
+      </BitField>
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
+        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
+        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
+        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
+        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
+        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
+        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
+        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
+        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
+      </BitField>
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="24" size="1" name="S" description="Source AHB master select:">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
+      </BitField>
+      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
+      </BitField>
+      <BitField start="26" size="1" name="SI" description="Source increment:">
+        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
+        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
+      </BitField>
+      <BitField start="27" size="1" name="DI" description="Destination increment:">
+        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
+        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
+      </BitField>
+      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
+        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
+        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
+      </BitField>
+      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
+        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
+        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
+      </BitField>
+      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
+        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
+        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
+      </BitField>
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
+        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
+        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
+      </BitField>
+    </Register>
+    <Register start="+0x10C+128" size="4" name="C4CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
+        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
+        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
+        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
+        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
+        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
+        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
+        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
+        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
+      </BitField>
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
+        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
+        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
+        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
+        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
+        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
+        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
+        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
+        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
+      </BitField>
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="24" size="1" name="S" description="Source AHB master select:">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
+      </BitField>
+      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
+      </BitField>
+      <BitField start="26" size="1" name="SI" description="Source increment:">
+        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
+        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
+      </BitField>
+      <BitField start="27" size="1" name="DI" description="Destination increment:">
+        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
+        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
+      </BitField>
+      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
+        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
+        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
+      </BitField>
+      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
+        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
+        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
+      </BitField>
+      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
+        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
+        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
+      </BitField>
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
+        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
+        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
+      </BitField>
+    </Register>
+    <Register start="+0x10C+160" size="4" name="C5CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
+        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
+        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
+        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
+        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
+        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
+        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
+        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
+        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
+      </BitField>
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
+        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
+        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
+        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
+        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
+        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
+        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
+        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
+        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
+      </BitField>
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="24" size="1" name="S" description="Source AHB master select:">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
+      </BitField>
+      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
+      </BitField>
+      <BitField start="26" size="1" name="SI" description="Source increment:">
+        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
+        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
+      </BitField>
+      <BitField start="27" size="1" name="DI" description="Destination increment:">
+        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
+        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
+      </BitField>
+      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
+        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
+        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
+      </BitField>
+      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
+        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
+        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
+      </BitField>
+      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
+        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
+        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
+      </BitField>
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
+        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
+        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
+      </BitField>
+    </Register>
+    <Register start="+0x10C+192" size="4" name="C6CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
+        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
+        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
+        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
+        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
+        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
+        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
+        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
+        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
+      </BitField>
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
+        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
+        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
+        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
+        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
+        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
+        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
+        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
+        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
+      </BitField>
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="24" size="1" name="S" description="Source AHB master select:">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
+      </BitField>
+      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
+      </BitField>
+      <BitField start="26" size="1" name="SI" description="Source increment:">
+        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
+        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
+      </BitField>
+      <BitField start="27" size="1" name="DI" description="Destination increment:">
+        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
+        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
+      </BitField>
+      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
+        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
+        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
+      </BitField>
+      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
+        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
+        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
+      </BitField>
+      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
+        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
+        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
+      </BitField>
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
+        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
+        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
+      </BitField>
+    </Register>
+    <Register start="+0x10C+224" size="4" name="C7CONTROL" access="Read/Write" description="DMA Channel  Control Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TRANSFERSIZE" description="Transfer size in byte. A write to this field sets the size of the transfer when the DMA Controller is the flow controller. The transfer size value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if the DMA Controller is not the flow controller." />
+      <BitField start="12" size="3" name="SBSIZE" description="Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size (see Figure 3). The burst size is the amount of data that is transferred when the BREQ signal goes active in the source peripheral.">
+        <Enum name="SOURCE_BURST_1" start="0x0" description="Source burst size = 1" />
+        <Enum name="SOURCE_BURST_4" start="0x1" description="Source burst size = 4" />
+        <Enum name="SOURCE_BURST_8" start="0x2" description="Source burst size = 8" />
+        <Enum name="SOURCE_BURST_16" start="0x3" description="Source burst size = 16" />
+        <Enum name="SOURCE_BURST_32" start="0x4" description="Source burst size = 32" />
+        <Enum name="SOURCE_BURST_64" start="0x5" description="Source burst size = 64" />
+        <Enum name="SOURCE_BURST_128" start="0x6" description="Source burst size = 128" />
+        <Enum name="SOURCE_BURST_256" start="0x7" description="Source burst size = 256" />
+      </BitField>
+      <BitField start="15" size="3" name="DBSIZE" description="Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the BREQ signal goes active in the destination peripheral.">
+        <Enum name="DESTINATION_BURST_1" start="0x0" description="Destination burst size = 1" />
+        <Enum name="DESTINATION_BURST_4" start="0x1" description="Destination burst size = 4" />
+        <Enum name="DESTINATION_BURST_8" start="0x2" description="Destination burst size = 8" />
+        <Enum name="DESTINATION_BURST_16" start="0x3" description="Destination burst size = 16" />
+        <Enum name="DESTINATION_BURST_32" start="0x4" description="Destination burst size = 32" />
+        <Enum name="DESTINATION_BURST_64" start="0x5" description="Destination burst size = 64" />
+        <Enum name="DESTINATION_BURST_128" start="0x6" description="Destination burst size = 128" />
+        <Enum name="DESTINATION_BURST_256" start="0x7" description="Destination burst size = 256" />
+      </BitField>
+      <BitField start="18" size="3" name="SWIDTH" description="Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="21" size="3" name="DWIDTH" description="Destination transfer width. Transfers wider than the AHB master bus width are not supported. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 0x3 to 0x7 - Reserved.">
+        <Enum name="BYTE_8_BIT" start="0x0" description="Byte (8-bit)" />
+        <Enum name="HALFWORD_16_BIT" start="0x1" description="Halfword (16-bit)" />
+        <Enum name="WORD_32_BIT" start="0x2" description="Word (32-bit)" />
+      </BitField>
+      <BitField start="24" size="1" name="S" description="Source AHB master select:">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for source transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for source transfer." />
+      </BitField>
+      <BitField start="25" size="1" name="D" description="Destination AHB master select: Only Master1 can access a peripheral. Master0 can only access memory.">
+        <Enum name="AHB_MASTER_0_SELECTE" start="0" description="AHB Master 0 selected for destination transfer." />
+        <Enum name="AHB_MASTER_1_SELECTE" start="1" description="AHB Master 1 selected for destination transfer." />
+      </BitField>
+      <BitField start="26" size="1" name="SI" description="Source increment:">
+        <Enum name="NOT_INCREMENT" start="0" description="The source address is not incremented after each transfer." />
+        <Enum name="INCREMENT" start="1" description="The source address is incremented after each transfer." />
+      </BitField>
+      <BitField start="27" size="1" name="DI" description="Destination increment:">
+        <Enum name="THE_DESTINATION_ADDR" start="0" description="The destination address is not incremented after each transfer." />
+        <Enum name="THE_DESTINATION_ADDR" start="1" description="The destination address is incremented after each transfer." />
+      </BitField>
+      <BitField start="28" size="1" name="PROT1" description="Indicates that the access is in user mode or privileged mode:">
+        <Enum name="ACCESS_IS_IN_USER_MO" start="0" description="Access is in user mode" />
+        <Enum name="ACCESS_IS_IN_PRIVILE" start="1" description="Access is in privileged mode." />
+      </BitField>
+      <BitField start="29" size="1" name="PROT2" description="Indicates that the access is bufferable or not bufferable:">
+        <Enum name="ACCESS_IS_NOT_BUFFER" start="0" description="Access is not bufferable." />
+        <Enum name="ACCESS_IS_BUFFERABLE" start="1" description="Access is bufferable." />
+      </BitField>
+      <BitField start="30" size="1" name="PROT3" description="Indicates that the access is cacheable or not cacheable:">
+        <Enum name="ACCESS_IS_NOT_CACHEA" start="0" description="Access is not cacheable." />
+        <Enum name="ACCESS_IS_CACHEABLE_" start="1" description="Access is cacheable." />
+      </BitField>
+      <BitField start="31" size="1" name="I" description="Terminal count interrupt enable bit.">
+        <Enum name="THE_TERMINAL_COUNT_I" start="0" description="The terminal count interrupt is disabled." />
+        <Enum name="THE_TERMINAL_COUNT_I" start="1" description="The terminal count interrupt is enabled." />
+      </BitField>
+    </Register>
+    <Register start="+0x110+0" size="4" name="C0CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
+        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
+        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
+      </BitField>
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
+        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
+        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
+        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
+        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
+        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
+        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
+        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
+      </BitField>
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
+        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
+        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
+        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
+        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
+        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
+        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
+        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
+      </BitField>
+      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
+        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
+      </BitField>
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
+        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
+        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
+      </BitField>
+      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
+    </Register>
+    <Register start="+0x110+32" size="4" name="C1CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
+        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
+        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
+      </BitField>
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
+        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
+        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
+        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
+        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
+        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
+        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
+        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
+      </BitField>
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
+        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
+        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
+        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
+        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
+        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
+        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
+        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
+      </BitField>
+      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
+        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
+      </BitField>
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
+        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
+        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
+      </BitField>
+      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
+    </Register>
+    <Register start="+0x110+64" size="4" name="C2CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
+        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
+        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
+      </BitField>
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
+        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
+        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
+        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
+        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
+        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
+        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
+        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
+      </BitField>
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
+        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
+        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
+        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
+        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
+        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
+        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
+        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
+      </BitField>
+      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
+        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
+      </BitField>
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
+        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
+        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
+      </BitField>
+      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
+    </Register>
+    <Register start="+0x110+96" size="4" name="C3CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
+        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
+        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
+      </BitField>
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
+        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
+        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
+        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
+        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
+        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
+        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
+        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
+      </BitField>
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
+        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
+        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
+        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
+        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
+        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
+        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
+        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
+      </BitField>
+      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
+        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
+      </BitField>
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
+        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
+        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
+      </BitField>
+      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
+    </Register>
+    <Register start="+0x110+128" size="4" name="C4CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
+        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
+        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
+      </BitField>
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
+        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
+        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
+        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
+        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
+        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
+        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
+        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
+      </BitField>
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
+        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
+        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
+        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
+        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
+        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
+        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
+        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
+      </BitField>
+      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
+        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
+      </BitField>
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
+        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
+        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
+      </BitField>
+      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
+    </Register>
+    <Register start="+0x110+160" size="4" name="C5CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
+        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
+        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
+      </BitField>
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
+        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
+        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
+        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
+        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
+        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
+        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
+        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
+      </BitField>
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
+        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
+        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
+        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
+        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
+        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
+        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
+        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
+      </BitField>
+      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
+        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
+      </BitField>
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
+        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
+        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
+      </BitField>
+      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
+    </Register>
+    <Register start="+0x110+192" size="4" name="C6CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
+        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
+        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
+      </BitField>
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
+        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
+        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
+        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
+        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
+        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
+        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
+        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
+      </BitField>
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
+        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
+        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
+        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
+        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
+        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
+        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
+        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
+      </BitField>
+      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
+        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
+      </BitField>
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
+        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
+        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
+      </BitField>
+      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
+    </Register>
+    <Register start="+0x110+224" size="4" name="C7CONFIG" access="Read/Write" description="DMA Channel Configuration Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: The Channel Enable bit status can also be found by reading the EnbldChns Register. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.">
+        <Enum name="CHANNEL_DISABLED_" start="0" description="Channel disabled." />
+        <Enum name="CHANNEL_ENABLED_" start="1" description="Channel enabled." />
+      </BitField>
+      <BitField start="1" size="5" name="SRCPERIPHERAL" description="Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 136 for details.">
+        <Enum name="SOURCE_EQ_SPIFI" start="0x0" description="Source = SPIFI" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x1" description="Source = Timer 0 match 0/UART0 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_0_MAT" start="0x2" description="Source = Timer 0 match 1/UART0 receive" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x3" description="Source = Timer 1 match 0/UART1 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_1_MAT" start="0x4" description="Source = Timer 1 match 1/UART 1 receive" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x5" description="Source = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="SOURCE_EQ_TIMER_2_MAT" start="0x6" description="Source = Timer 2 match 1/UART 2 receive" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x7" description="Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="SOURCE_EQ_TIMER_3_MAT" start="0x8" description="Source = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="SOURCE_EQ_SSP0_RECEIV" start="0x9" description="Source = SSP0 receive/I2S channel 0" />
+        <Enum name="SOURCE_EQ_SSP0_TRANSM" start="0xA" description="Source = SSP0 transmit/I2S channel 1" />
+        <Enum name="SOURCE_EQ_SSP1_RECEIV" start="0xB" description="Source = SSP1 receive" />
+        <Enum name="SOURCE_EQ_SSP1_TRANSM" start="0xC" description="Source = SSP1 transmit" />
+        <Enum name="SOURCE_EQ_ADC0" start="0xD" description="Source = ADC0" />
+        <Enum name="SOURCE_EQ_ADC1" start="0xE" description="Source = ADC1" />
+        <Enum name="SOURCE_EQ_DAC" start="0xF" description="Source = DAC" />
+      </BitField>
+      <BitField start="6" size="5" name="DESTPERIPHERAL" description="Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 136 for details.">
+        <Enum name="DESTINATION_EQ_SPIFI" start="0x0" description="Destination = SPIFI" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x1" description="Destination = Timer 0 match 0/UART0 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x2" description="Destination = Timer 0 match 1/UART0 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x3" description="Destination = Timer 1 match 0/UART1 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x4" description="Destination = Timer 1 match 1/UART 1 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x5" description="Destination = Timer 2 match 0/UART 2 transmit" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x6" description="Destination = Timer 2 match 1/UART 2 receive" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x7" description="Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0" />
+        <Enum name="DESTINATION_EQ_TIMER_" start="0x8" description="Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1" />
+        <Enum name="DESTINATION_EQ_SSP0_R" start="0x9" description="Destination = SSP0 receive/I2S channel 0" />
+        <Enum name="DESTINATION_EQ_SSP0_T" start="0xA" description="Destination = SSP0 transmit/I2S channel 1" />
+        <Enum name="DESTINATION_EQ_SSP1_R" start="0xB" description="Destination = SSP1 receive" />
+        <Enum name="DESTINATION_EQ_SSP1_T" start="0xC" description="Destination = SSP1 transmit" />
+        <Enum name="DESTINATION_EQ_ADC0" start="0xD" description="Destination = ADC0" />
+        <Enum name="DESTINATION_EQ_ADC1" start="0xE" description="Destination = ADC1" />
+        <Enum name="DESTINATION_EQ_DAC" start="0xF" description="Destination = DAC" />
+      </BitField>
+      <BitField start="11" size="3" name="FLOWCNTRL" description="Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMA Controller, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Refer to Table 157 for the encoding of this field.">
+        <Enum name="MEMORY_TO_MEMORY" start="0x0" description="Memory to memory (DMA control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x1" description="Memory to peripheral (DMA control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x2" description="Peripheral to memory (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x3" description="Source peripheral to destination peripheral (DMA control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x4" description="Source peripheral to destination peripheral (destination control)" />
+        <Enum name="MEMORY_TO_PERIPHERAL" start="0x5" description="Memory to peripheral (peripheral control)" />
+        <Enum name="PERIPHERAL_TO_MEMORY" start="0x6" description="Peripheral to memory (peripheral control)" />
+        <Enum name="SOURCE_PERIPHERAL_TO" start="0x7" description="Source peripheral to destination peripheral (source control)" />
+      </BitField>
+      <BitField start="14" size="1" name="IE" description="Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel." />
+      <BitField start="15" size="1" name="ITC" description="Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel." />
+      <BitField start="16" size="1" name="L" description="Lock. When set, this bit enables locked transfers." />
+      <BitField start="17" size="1" name="A" description="Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit." />
+      <BitField start="18" size="1" name="H" description="Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.">
+        <Enum name="ENABLE_DMA_REQUESTS_" start="0" description="Enable DMA requests." />
+        <Enum name="IGNORE_FURTHER_SOURC" start="1" description="Ignore further source DMA requests." />
+      </BitField>
+      <BitField start="19" size="13" name="RESERVED" description="Reserved, do not modify, masked on read." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPIFI" start="0x40003000" description="SPI Flash Interface (SPIFI)">
+    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="SPIFI control register" reset_value="0x400FFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TIMEOUT" description="This field contains the number of serial clock periods without the processor reading data in memory mode, which will cause the SPIFI hardware to terminate the command by driving the CS pin high and negating the CMD bit in the Status register. (This allows the flash memory to enter a lower-power state.) If the processor reads data from the flash region after a time-out, the command in the Memory Command Register is issued again." />
+      <BitField start="16" size="4" name="CSHIGH" description="This field controls the minimum CS high time, expressed as a number of serial clock periods minus one." />
+      <BitField start="20" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="21" size="1" name="D_PRFTCH_DIS" description="This bit allows conditioning of memory mode prefetches based on the AHB HPROT (instruction/data) access information. A 1 in this register means that the SPIFI will not attempt a speculative prefetch when it encounters data accesses." />
+      <BitField start="22" size="1" name="INTEN" description="If this bit is 1 when a command ends, the SPIFI will assert its interrupt request output. See INTRQ in the status register for further details." />
+      <BitField start="23" size="1" name="MODE3" description="SPI Mode 3 select.">
+        <Enum name="SCK_LOW" start="0" description="SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit of each command is captured, and keeps it low while CS is HIGH." />
+        <Enum name="SCK_HIGH" start="1" description="SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of each command and while CS is HIGH, and drives it low after it drives  CS LOW. (Known serial flash devices can handle either mode, but some devices may require a particular mode for proper operation.)  MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
+      </BitField>
+      <BitField start="24" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="27" size="1" name="PRFTCH_DIS" description="Cache prefetching enable. The SPIFI includes an internal cache. A 1 in this bit disables prefetching of cache lines.">
+        <Enum name="ENABLE" start="0" description="Enable. Cache prefetching enabled." />
+        <Enum name="DISABLE" start="1" description="Disable. Disables prefetching of cache lines." />
+      </BitField>
+      <BitField start="28" size="1" name="DUAL" description="Select dual protocol.">
+        <Enum name="QUAD_PROTOCOL" start="0" description="Quad protocol. This protocol uses IO3:0." />
+        <Enum name="DUAL_PROTOCOL" start="1" description="Dual protocol. This protocol uses IO1:0." />
+      </BitField>
+      <BitField start="29" size="1" name="RFCLK" description="Select active clock edge for input data.">
+        <Enum name="RISING_EDGE" start="0" description="Rising edge. Read data is sampled on rising edges on the clock, as in classic SPI operation." />
+        <Enum name="FALLING_EDGE" start="1" description="Falling edge. Read data is sampled on falling edges of the clock, allowing a full serial clock of of time in order to maximize the serial clock frequency. MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
+      </BitField>
+      <BitField start="30" size="1" name="FBCLK" description="Feedback clock select.">
+        <Enum name="INTERNAL_CLOCK" start="0" description="Internal clock. The SPIFI samples read data using an internal clock." />
+        <Enum name="FEEDBACK_CLOCK" start="1" description="Feedback clock. Read data is sampled using a feedback clock from the SCK pin. This allows slightly more time for each received bit.  MODE3, RFCLK, and FBCLK should not all be 1, because in this case there is no final rising edge on SCK on which to sample the last data bit of the frame." />
+      </BitField>
+      <BitField start="31" size="1" name="DMAEN" description="A 1 in this bit enables the DMA Request output from the SPIFI. Set this bit only when a DMA channel is used to transfer data in peripheral mode. Do not set this bit when a DMA channel is used for memory-to-memory transfers from the SPIFI memory area. DRQEN should only be used in Command mode." />
+    </Register>
+    <Register start="+0x004" size="4" name="CMD" access="Read/Write" description="SPIFI command register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="14" name="DATALEN" description="Except when the POLL bit in this register is 1, this field controls how many data bytes are in the command. 0 indicates that the command does not contain a data field." />
+      <BitField start="14" size="1" name="POLL" description="This bit should be written as 1 only with an opcode that a) contains an input data field, and b) causes the serial flash device to return byte status repetitively (e.g., a Read Status command). When this bit is 1, the SPIFI hardware continues to read bytes until the test specified by the dataLen field is met. The hardware tests the bit in each status byte selected by DATALEN bits 2:0, until a bit is found that is equal to DATALEN bit 3. When the test succeeds, the SPIFI captures the byte that meets this test so that it can be read from the Data Register, and terminates the command by raising  CS. The end-of-command interrupt can be enabled to inform software when this occurs" />
+      <BitField start="15" size="1" name="DOUT" description="If the DATALEN field is not zero, this bit controls the direction of the data:">
+        <Enum name="INPUT_FROM_SERIAL_FL" start="0" description="Input from serial flash." />
+        <Enum name="OUTPUT_TO_SERIAL_FLA" start="1" description="Output to serial flash." />
+      </BitField>
+      <BitField start="16" size="3" name="INTLEN" description="This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes." />
+      <BitField start="19" size="2" name="FIELDFORM" description="This field controls how the fields of the command are sent.">
+        <Enum name="ALL_SERIAL" start="0x0" description="All serial. All fields of the command are serial." />
+        <Enum name="QUADDUAL_DATA" start="0x1" description="Quad/dual data. Data field is quad/dual, other fields are serial." />
+        <Enum name="SERIAL_OPCODE" start="0x2" description="Serial opcode. Opcode field is serial. Other fields are quad/dual." />
+        <Enum name="ALL_QUADDUAL" start="0x3" description="All quad/dual. All fields of the command are in quad/dual format." />
+      </BitField>
+      <BitField start="21" size="3" name="FRAMEFORM" description="This field controls the opcode and address fields.">
+        <Enum name="RESERVED" start="0x0" description="Reserved." />
+        <Enum name="OPCODE" start="0x1" description="Opcode. Opcode only, no address." />
+        <Enum name="OPCODE_ONE_BYTE" start="0x2" description="Opcode one byte. Opcode, least significant byte of address." />
+        <Enum name="OPCODE_TWO_BYTES" start="0x3" description="Opcode two bytes. Opcode, two least significant bytes of address." />
+        <Enum name="OPCODE_THREE_BYTES" start="0x4" description="Opcode three bytes. Opcode, three least significant bytes of address." />
+        <Enum name="OPCODE_FOUR_BYTES" start="0x5" description="Opcode four bytes. Opcode, 4 bytes of address." />
+        <Enum name="NO_OPCODE_THREE_BYTE" start="0x6" description="No opcode three bytes. No opcode, 3 least significant bytes of address." />
+        <Enum name="NO_OPCODE_FOUR_BYTES" start="0x7" description="No opcode four bytes. No opcode, 4 bytes of address." />
+      </BitField>
+      <BitField start="24" size="8" name="OPCODE" description="The opcode of the command (not used for some FRAMEFORM values)." />
+    </Register>
+    <Register start="+0x008" size="4" name="ADDR" access="Read/Write" description="SPIFI address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="ADDRESS" description="Address." />
+    </Register>
+    <Register start="+0x00C" size="4" name="IDATA" access="Read/Write" description="SPIFI intermediate data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="IDATA" description="Value of intermediate bytes." />
+    </Register>
+    <Register start="+0x010" size="4" name="CLIMIT" access="Read/Write" description="SPIFI cache limit register" reset_value="0x08000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CLIMIT" description="Zero-based upper limit of cacheable memory" />
+    </Register>
+    <Register start="+0x014" size="4" name="DATA" access="Read/Write" description="SPIFI data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="DATA" description="Input or output data" />
+    </Register>
+    <Register start="+0x018" size="4" name="MCMD" access="Read/Write" description="SPIFI memory command register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="14" name="RESERVED" description="Reserved." />
+      <BitField start="14" size="1" name="POLL" description="This bit should be written as 0." />
+      <BitField start="15" size="1" name="DOUT" description="This bit should be written as 0." />
+      <BitField start="16" size="3" name="INTLEN" description="This field controls how many intermediate bytes precede the data. (Each such byte may require 8 or 2 SCK cycles, depending on whether the intermediate field is in serial, 2-bit, or 4-bit format.) Intermediate bytes are output by the SPIFI, and include post-address control information, dummy and delay bytes. See the description of the Intermediate Data register for the contents of such bytes." />
+      <BitField start="19" size="2" name="FIELDFORM" description="This field controls how the fields of the command are sent.">
+        <Enum name="ALL_SERIAL" start="0x0" description="All serial. All fields of the command are serial." />
+        <Enum name="QUADDUAL_DATA" start="0x1" description="Quad/dual data. Data field is quad/dual, other fields are serial." />
+        <Enum name="SERIAL_OPCODE" start="0x2" description="Serial opcode. Opcode field is serial. Other fields are quad/dual." />
+        <Enum name="ALL_QUADDUAL" start="0x3" description="All quad/dual. All fields of the command are in quad/dual format." />
+      </BitField>
+      <BitField start="21" size="3" name="FRAMEFORM" description="This field controls the opcode and address fields.">
+        <Enum name="RESERVED" start="0x0" description="Reserved." />
+        <Enum name="RESERVED" start="0x1" description="Reserved." />
+        <Enum name="OPCODE_ONE_BYTE" start="0x2" description="Opcode one byte. Opcode, least-significant byte of address." />
+        <Enum name="OPCODE_TWO_BYTES" start="0x3" description="Opcode two bytes. Opcode, 2 least-significant bytes of address." />
+        <Enum name="OPCODE_THREE_BYTES" start="0x4" description="Opcode three bytes. Opcode, 3 least-significant bytes of address." />
+        <Enum name="OPCODE_FOUR_BYTES" start="0x5" description="Opcode four bytes. Opcode, 4 bytes of address." />
+        <Enum name="NO_OPCODE_THREE_BYTE" start="0x6" description="No opcode three bytes. No opcode, 3 least-significant bytes of address." />
+        <Enum name="NO_OPCODE_FOUR_BYTES" start="0x7" description="No opcode, 4 bytes of address." />
+      </BitField>
+      <BitField start="24" size="8" name="OPCODE" description="The opcode of the command (not used for some FRAMEFORM values)." />
+    </Register>
+    <Register start="+0x01C" size="4" name="STAT" access="Read/Write" description="SPIFI status register" reset_value="0x02000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MCINIT" description="This bit is set when software successfully writes the Memory Command register, and is cleared by Reset or by writing a 1 to the RESET bit in this register." />
+      <BitField start="1" size="1" name="CMD" description="This bit is 1 when the Command register is written. It is cleared by a hardware reset, a write to the RESET bit in this register, or the deassertion of CS which indicates that the command has completed communication with the SPI Flash." />
+      <BitField start="4" size="1" name="RESET" description="Write a 1 to this bit to abort a current command or memory mode. This bit is cleared when the hardware is ready for a new command to be written to the Command register." />
+      <BitField start="5" size="1" name="INTRQ" description="This bit reflects the SPIFI interrupt request. Write a 1 to this bit to clear it. This bit is set when a CMD was previously 1 and has been cleared due to the deassertion of CS." />
+      <BitField start="6" size="18" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="8" name="VERSION" description="The SPIFI hardware described in this chapter returns" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SDMMC" start="0x40004000" description="SD/MMC">
+    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="Control Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CONTROLLER_RESET" description="Controller reset. To reset controller, software should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles. This resets:  - BIU/CIU interface - CIU and state machines  - abort_read_data, send_irq_response, and read_wait bits of Control register  - start_cmd bit of Command register  Does not affect any registers or DMA interface, or FIFO. or host interrupts.">
+        <Enum name="NO_CHANGE" start="0" description="No change." />
+        <Enum name="RESET" start="1" description="Reset. Reset SD/MMC controller" />
+      </BitField>
+      <BitField start="1" size="1" name="FIFO_RESET" description="Fifo reset. To reset FIFO, software should set bit to 1. This bit is auto-cleared after completion of reset operation. auto-cleared after two AHB clocks.">
+        <Enum name="NO_CHANGE" start="0" description="No change." />
+        <Enum name="RESET" start="1" description="Reset. Reset to data FIFO To reset FIFO pointers" />
+      </BitField>
+      <BitField start="2" size="1" name="DMA_RESET" description="Dma reset. To reset DMA interface, software should set bit to 1. This bit is auto-cleared after two AHB clocks.">
+        <Enum name="NO_CHANGE" start="0" description="No change." />
+        <Enum name="RESET" start="1" description="Reset. Reset internal DMA interface control logic" />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="1" name="INT_ENABLE" description="Global interrupt enable/disable bit. The int port is 1 only when this bit is 1 and one or more unmasked interrupts are set.">
+        <Enum name="DISABLE_INTERRUPTS" start="0" description="Disable interrupts" />
+        <Enum name="ENABLE_INTERRUPTS" start="1" description="Enable interrupts" />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
+      <BitField start="6" size="1" name="READ_WAIT" description="Read/wait. For sending read-wait to SDIO cards.">
+        <Enum name="CLEAR_READ_WAIT" start="0" description="Clear read wait" />
+        <Enum name="ASSERT_READ_WAIT" start="1" description="Assert read wait" />
+      </BitField>
+      <BitField start="7" size="1" name="SEND_IRQ_RESPONSE" description="Send irq response. This bit automatically clears once response is sent. To wait for MMC card interrupts, the host issues CMD40, and the SD/MMC controller waits for an interrupt response from the MMC card. In the meantime, if the host wants the SD/MMC interface to exit waiting for interrupt state, it can set this bit, at which time the SD/MMC interface command state-machine sends a CMD40 response on the bus and returns to idle state.">
+        <Enum name="NO_CHANGE" start="0" description="No change" />
+        <Enum name="SEND_AUTO_IRQ_RESPON" start="1" description="Send auto IRQ response" />
+      </BitField>
+      <BitField start="8" size="1" name="ABORT_READ_DATA" description="Abort read data. Used in SDIO card suspend sequence.">
+        <Enum name="NO_CHANGE" start="0" description="No change" />
+        <Enum name="ABORT" start="1" description="Abort. After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs, software sets bit to reset data state-machine, which is waiting for next block of data. This bit automatically clears once data state machine resets to idle. Used in SDIO card suspend sequence." />
+      </BitField>
+      <BitField start="9" size="1" name="SEND_CCSD" description="Send ccsd. When set, the SD/MMC controller sends CCSD to the CE-ATA device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device. Once the CCSD pattern is sent to device, the SD/MMC interface automatically clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and generates interrupt to host if Command Done interrupt is not masked.  NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, during the boundary conditions it may happen that CCSD is sent to the CE-ATA device, even if the device signalled CCS.">
+        <Enum name="CLEAR_BIT" start="0" description="Clear bit if the SD/MMC controller does not reset the bit." />
+        <Enum name="SEND_COMMAND_COMPLET" start="1" description="Send Command Completion Signal Disable (CCSD) to CE-ATA device" />
+      </BitField>
+      <BitField start="10" size="1" name="SEND_AUTO_STOP" description="Send auto stop ccsd. NOTE: Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. When set, the SD/MMC interface automatically sends internallygenerated STOP command (CMD12) to CE-ATA device. After sending internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set and generates interrupt to host if Auto Command Done interrupt is not masked. After sending the CCSD, the SD/MMC interface automatically clears send_auto_stop_ccsd bit.">
+        <Enum name="CLEAR_THIS_BIT_IF_TH" start="0" description="Clear this bit if the SD/MMC controller does not reset the bit." />
+        <Enum name="SEND_INTERNALLY_GENE" start="1" description="Send internally generated STOP after sending CCSD to CE-ATA device." />
+      </BitField>
+      <BitField start="11" size="1" name="CEATA_DEVICE_INTERRUPT_STATUS" description="CEATA device interrupt status. Software should appropriately write to this bit after power-on reset or any other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software should set this bit.">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupts not enabled in CE-ATA device (nIEN = 1 in ATA control register)" />
+        <Enum name="ENABLED" start="1" description="Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0 in ATA control register)" />
+      </BitField>
+      <BitField start="12" size="4" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="CARD_VOLTAGE_A0" description="Controls the state of the SD_VOLT0 pin. SD/MMC card voltage control is not implemented." />
+      <BitField start="17" size="1" name="CARD_VOLTAGE_A1" description="Controls the state of the SD_VOLT1 pin. SD/MMC card voltage control is not implemented." />
+      <BitField start="18" size="1" name="CARD_VOLTAGE_A2" description="Controls the state of the SD_VOLT2 pin. SD/MMC card voltage control is not implemented." />
+      <BitField start="19" size="5" name="RESERVED" description="Reserved." />
+      <BitField start="24" size="1" name="RESERVED" description="Reserved. Always write this bit as 0." />
+      <BitField start="25" size="1" name="USE_INTERNAL_DMAC" description="SD/MMC DMA use.">
+        <Enum name="HOST" start="0" description="Host. The host performs data transfers through the slave interface" />
+        <Enum name="DMA" start="1" description="DMA. Internal DMA used for data transfer" />
+      </BitField>
+      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="PWREN" access="Read/Write" description="Power Enable Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POWER_ENABLE" description="Power on/off switch for card; once power is turned on, software should wait for regulator/switch ramp-up time before trying to initialize card.  0 - power off  1 - power on  Optional feature: port can be used as general-purpose output on the SD_POW pin." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x008" size="4" name="CLKDIV" access="Read/Write" description="Clock Divider Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CLK_DIVIDER0" description="Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on." />
+      <BitField start="8" size="8" name="CLK_DIVIDER1" description="Clock divider-1 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
+      <BitField start="16" size="8" name="CLK_DIVIDER2" description="Clock divider-2 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
+      <BitField start="24" size="8" name="CLK_DIVIDER3" description="Clock divider-3 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a value of   ff means divide by 2*255 = 510, and so on.  In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported. divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of   ff means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported." />
+    </Register>
+    <Register start="+0x00C" size="4" name="CLKSRC" access="Read/Write" description="SD Clock Source Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CLK_SOURCE" description="Clock divider source for SD card.  00 - Clock divider 0  01 - Clock divider 1  10 - Clock divider 2  11 - Clock divider 3 In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x010" size="4" name="CLKENA" access="Read/Write" description="Clock Enable Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CCLK_ENABLE" description="Clock-enable control for SD card clock. One MMC card clock supported.  0 - Clock disabled  1 - Clock enabled" />
+      <BitField start="1" size="15" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="CCLK_LOW_POWER" description="Low-power control for SD card clock. One MMC card clock supported.  0 - Non-low-power mode  1 - Low-power mode;  stop clock when card in IDLE (should be normally set to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock should not be stopped)." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x014" size="4" name="TMOUT" access="Read/Write" description="Time-out Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="RESPONSE_TIMEOUT" description="Response time-out value. Value is in number of card output clocks - cclk_out." />
+      <BitField start="8" size="24" name="DATA_TIMEOUT" description="Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card. Starvation by Host time-out. Value is in number of card output clocks - cclk_out of selected card." />
+    </Register>
+    <Register start="+0x018" size="4" name="CTYPE" access="Read/Write" description="Card Type Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CARD_WIDTH0" description="Indicates if card is 1-bit or 4-bit:  0 - 1-bit mode  1 - 4-bit mode  1 and 4-bit modes only work when 8-bit mode in CARD_WIDTH1 is not enabled (bit 16 in this register is set to 0)." />
+      <BitField start="1" size="15" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="CARD_WIDTH1" description="Indicates if card is 8-bit:  0 - Non 8-bit mode  1 - 8-bit mode." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x01C" size="4" name="BLKSIZ" access="Read/Write" description="Block Size Register" reset_value="0x200" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="BLOCK_SIZE" description="Block size" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020" size="4" name="BYTCNT" access="Read/Write" description="Byte Count Register" reset_value="0x200" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="BYTE_COUNT" description="Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. For undefined number of byte transfers, byte count should be set to 0. When byte count is set to 0, it is responsibility of host to explicitly send stop/abort command to terminate data transfer." />
+    </Register>
+    <Register start="+0x024" size="4" name="INTMASK" access="Read/Write" description="Interrupt Mask Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CDET" description="Card detect. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="1" size="1" name="RE" description="Response error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="2" size="1" name="CDONE" description="Command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="3" size="1" name="DTO" description="Data transfer over. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="8" size="1" name="RTO" description="Response time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="9" size="1" name="DRTO" description="Data read time-out. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO) /Volt_switch_int. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="13" size="1" name="SBE" description="Start-bit error. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="14" size="1" name="ACD" description="Auto command done. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/Write no CRC. Bits used to mask unwanted interrupts. Value of 0 masks interrupt; value of 1 enables interrupt." />
+      <BitField start="16" size="1" name="SDIO_INT_MASK" description="Mask SDIO interrupt. When masked, SDIO interrupt detection for card is disabled. A 0 masks an interrupt, and 1 enables an interrupt. In MMC-Ver3.3-only mode, this bit is always 0." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x028" size="4" name="CMDARG" access="Read/Write" description="Command Argument Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CMD_ARG" description="Value indicates command argument to be passed to card." />
+    </Register>
+    <Register start="+0x02C" size="4" name="CMD" access="Read/Write" description="Command Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="CMD_INDEX" description="Command index" />
+      <BitField start="6" size="1" name="RESPONSE_EXPECT" description="Response expect">
+        <Enum name="NONE" start="0" description="None. No response expected from card" />
+        <Enum name="EXPECTED" start="1" description="Expected. Response expected from card" />
+      </BitField>
+      <BitField start="7" size="1" name="RESPONSE_LENGTH" description="Response length">
+        <Enum name="SHORT" start="0" description="Short. Short response expected from card" />
+        <Enum name="LONG" start="1" description="Long. Long response expected from card" />
+      </BitField>
+      <BitField start="8" size="1" name="CHECK_RESPONSE_CRC" description="Check response crc. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller.">
+        <Enum name="DO_NOT_CHECK_RESPONS" start="0" description="Do not check response CRC" />
+        <Enum name="CHECK_RESPONSE_CRC" start="1" description="Check response CRC" />
+      </BitField>
+      <BitField start="9" size="1" name="DATA_EXPECTED" description="Data expected">
+        <Enum name="NONE" start="0" description="None. No data transfer expected (read/write)" />
+        <Enum name="DATA" start="1" description="Data. Data transfer expected (read/write)" />
+      </BitField>
+      <BitField start="10" size="1" name="READ_WRITE" description="read/write. Don't care if no data expected from card.">
+        <Enum name="READ_FROM_CARD" start="0" description="Read from card" />
+        <Enum name="WRITE_TO_CARD" start="1" description="Write to card" />
+      </BitField>
+      <BitField start="11" size="1" name="TRANSFER_MODE" description="Transfer mode. Don't care if no data expected.">
+        <Enum name="BLOCK_DATA_TRANSFER" start="0" description="Block data transfer command" />
+        <Enum name="STREAM_DATA_TRANSFER" start="1" description="Stream data transfer command" />
+      </BitField>
+      <BitField start="12" size="1" name="SEND_AUTO_STOP" description="Send auto stop. When set, the SD/MMC interface sends stop command to SD_MMC_CEATA cards at end of data transfer. Refer to Table 339 to determine:  - when send_auto_stop bit should be set, since some data transfers do not need explicit stop commands  - open-ended transfers that software should explicitly send to stop command  Additionally, when   resume is sent to resume - suspended memory access of SD-Combo card - bit should be set correctly if suspended data transfer needs send_auto_stop. Don't care if no data expected from card.">
+        <Enum name="NO_STOP_COMMAND_SENT" start="0" description="No stop command sent at end of data transfer" />
+        <Enum name="SEND_STOP_COMMAND_AT" start="1" description="Send stop command at end of data transfer" />
+      </BitField>
+      <BitField start="13" size="1" name="WAIT_PRVDATA_COMPLETE" description="Wait prvdata complete. The wait_prvdata_complete = 0 option typically used to query status of card during data transfer or to stop current data transfer; card_number should be same as in previous command.">
+        <Enum name="SEND" start="0" description="Send. Send command at once, even if previous data transfer has not completed." />
+        <Enum name="WAIT" start="1" description="Wait. Wait for previous data transfer completion before sending command." />
+      </BitField>
+      <BitField start="14" size="1" name="STOP_ABORT_CMD" description="Stop abort command. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot.">
+        <Enum name="DISABLED" start="0" description="Disabled. Neither stop nor abort command to stop current data transfer in progress. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0." />
+        <Enum name="ENABLED" start="1" description="Enabled. Stop or abort command intended to stop current data transfer in progress." />
+      </BitField>
+      <BitField start="15" size="1" name="SEND_INITIALIZATION" description="Send initialization. After power on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory).">
+        <Enum name="NO" start="0" description="No. Do not send initialization sequence (80 clocks of 1) before sending this command." />
+        <Enum name="SEND" start="1" description="Send. Send initialization sequence before sending this command." />
+      </BitField>
+      <BitField start="16" size="5" name="RESERVED" description="Reserved. Always write as 0." />
+      <BitField start="21" size="1" name="UPDATE_CLOCK_REGISTERS_ONLY" description="Update clock registers only. Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode); provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards.">
+        <Enum name="NORMAL" start="0" description="Normal. Normal command sequence" />
+        <Enum name="NO" start="1" description="No. Do not send commands, just update clock register value into card clock domain" />
+      </BitField>
+      <BitField start="22" size="1" name="READ_CEATA_DEVICE" description="Read ceata device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data time-out indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds.The SD/MMC interface should not indicate read data time-out while waiting for data from CE-ATA device.">
+        <Enum name="NO_READ" start="0" description="No read. Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device." />
+        <Enum name="READ" start="1" description="Read. Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device." />
+      </BitField>
+      <BitField start="23" size="1" name="CCS_EXPECTED" description="CCS expected. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. The SD/MMC controller sets the Data Transfer Over (DTO) bit in the RINTSTS register and generates an interrupt to the host if the Data Transfer Over interrupt is not masked.">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device." />
+        <Enum name="ENABLED" start="1" description="Enabled. Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device." />
+      </BitField>
+      <BitField start="24" size="1" name="ENABLE_BOOT" description="Enable Boot - this bit should be set only for mandatory boot mode. When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together." />
+      <BitField start="25" size="1" name="EXPECT_BOOT_ACK" description="Expect Boot Acknowledge. When Software sets this bit along with enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card." />
+      <BitField start="26" size="1" name="DISABLE_BOOT" description="Disable Boot. When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together." />
+      <BitField start="27" size="1" name="BOOT_MODE" description="Boot Mode">
+        <Enum name="MANDATORY_BOOT_OPERA" start="0" description="Mandatory Boot operation" />
+        <Enum name="ALTERNATE_BOOT_OPERA" start="1" description="Alternate Boot operation" />
+      </BitField>
+      <BitField start="28" size="1" name="VOLT_SWITCH" description="Voltage switch bit">
+        <Enum name="DISABLED" start="0" description="Disabled. No voltage switching" />
+        <Enum name="ENABLED" start="1" description="Enabled. Voltage switching enabled; must be set for CMD11 only" />
+      </BitField>
+      <BitField start="29" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="START_CMD" description="Start command. Once command is taken by CIU, this bit is cleared. When bit is set, host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt register." />
+    </Register>
+    <Register start="+0x030" size="4" name="RESP0" access="ReadOnly" description="Response Register 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RESPONSE0" description="Bit[31:0] of response" />
+    </Register>
+    <Register start="+0x034" size="4" name="RESP1" access="ReadOnly" description="Response Register 1" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RESPONSE1" description="Register represents bit[63:32] of long response. When CIU sends auto-stop command, then response is saved in register. Response for previous command sent by host is still preserved in Response 0 register. Additional auto-stop issued only for data transfer commands, and response type is always   short for them. For information on when CIU sends auto-stop commands, refer to   Auto-Stop ." />
+    </Register>
+    <Register start="+0x038" size="4" name="RESP2" access="ReadOnly" description="Response Register 2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RESPONSE2" description="Bit[95:64] of long response" />
+    </Register>
+    <Register start="+0x03C" size="4" name="RESP3" access="ReadOnly" description="Response Register 3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RESPONSE3" description="Bit[127:96] of long response" />
+    </Register>
+    <Register start="+0x040" size="4" name="MINTSTS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CDET" description="Card detect. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="1" size="1" name="RE" description="Response error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="2" size="1" name="CDONE" description="Command done. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="3" size="1" name="DTO" description="Data transfer over. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="8" size="1" name="RTO" description="Response time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="9" size="1" name="DRTO" description="Data read time-out. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO). Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="13" size="1" name="SBE" description="Start-bit error. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="14" size="1" name="ACD" description="Auto command done. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/write no CRC. Interrupt enabled only if corresponding bit in interrupt mask register is set." />
+      <BitField start="16" size="1" name="SDIO_INTERRUPT" description="Interrupt from SDIO card. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1 enables interrupt; 0 masks interrupt).  0 - No SDIO interrupt from card  1 - SDIO interrupt from card  In MMC-Ver3.3-only mode, this bit is always 0." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x044" size="4" name="RINTSTS" access="Read/Write" description="Raw Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CDET" description="Card detect. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="1" size="1" name="RE" description="Response error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="2" size="1" name="CDONE" description="Command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="3" size="1" name="DTO" description="Data transfer over. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="4" size="1" name="TXDR" description="Transmit FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="5" size="1" name="RXDR" description="Receive FIFO data request. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="6" size="1" name="RCRC" description="Response CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="7" size="1" name="DCRC" description="Data CRC error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="8" size="1" name="RTO_BAR" description="Response time-out (RTO)/Boot Ack Received (BAR). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="9" size="1" name="DRTO_BDS" description="Data read time-out (DRTO)/Boot Data Start (BDS). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="10" size="1" name="HTO" description="Data starvation-by-host time-out (HTO). Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status./Volt_switch_int" />
+      <BitField start="11" size="1" name="FRUN" description="FIFO underrun/overrun error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="12" size="1" name="HLE" description="Hardware locked write error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="13" size="1" name="SBE" description="Start-bit error. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="14" size="1" name="ACD" description="Auto command done. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="15" size="1" name="EBE" description="End-bit error (read)/write no CRC. Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status." />
+      <BitField start="16" size="1" name="SDIO_INTERRUPT" description="Interrupt from SDIO card. Writes to these bits clear them. Value of 1 clears bit and 0 leaves bit intact.  0 - No SDIO interrupt from card  1 - SDIO interrupt from card  In MMC-Ver3.3-only mode, bits always 0. Bits are logged regardless of interrupt-mask status." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x048" size="4" name="STATUS" access="ReadOnly" description="Status Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="FIFO_RX_WATERMARK" description="FIFO reached Receive watermark level; not qualified with data transfer." />
+      <BitField start="1" size="1" name="FIFO_TX_WATERMARK" description="FIFO reached Transmit watermark level; not qualified with data transfer." />
+      <BitField start="2" size="1" name="FIFO_EMPTY" description="FIFO is empty status" />
+      <BitField start="3" size="1" name="FIFO_FULL" description="FIFO is full status" />
+      <BitField start="4" size="4" name="CMDFSMSTATES" description="Command FSM states:  0 - Idle  1 - Send init sequence  2 - Tx cmd start bit  3 - Tx cmd tx bit  4 - Tx cmd index + arg  5 - Tx cmd crc7  6 - Tx cmd end bit  7 - Rx resp start bit  8 - Rx resp IRQ response  9 - Rx resp tx bit  10 - Rx resp cmd idx  11 - Rx resp data  12 - Rx resp crc7  13 - Rx resp end bit  14 - Cmd path wait NCC  15 - Wait; CMD-to-response turnaround  NOTE: The command FSM state is represented using 19 bits. The STATUS Register(7:4) has 4 bits to represent the command FSM states. Using these 4 bits, only 16 states can be represented. Thus three states cannot be represented in the STATUS(7:4) register. The three states that are not represented in the STATUS Register(7:4) are:  - Bit 16 - Wait for CCS - Bit 17 - Send CCSD  - Bit 18 - Boot Mode  Due to this, while command FSM is in   Wait for CCS state or   Send CCSD or   Boot Mode, the Status register indicates status as 0 for the bit field 7:4." />
+      <BitField start="8" size="1" name="DATA_3_STATUS" description="Raw selected card_data[3]; checks whether card is present  0 - card not present  1 - card present" />
+      <BitField start="9" size="1" name="DATA_BUSY" description="Inverted version of raw selected card_data[0]  0 - card data not busy  1 - card data busy" />
+      <BitField start="10" size="1" name="DATA_STATE_MC_BUSY" description="Data transmit or receive state-machine is busy" />
+      <BitField start="11" size="6" name="RESPONSE_INDEX" description="Index of previous response, including any auto-stop sent by core." />
+      <BitField start="17" size="13" name="FIFO_COUNT" description="FIFO count - Number of filled locations in FIFO" />
+      <BitField start="30" size="1" name="DMA_ACK" description="DMA acknowledge signal state" />
+      <BitField start="31" size="1" name="DMA_REQ" description="DMA request signal state" />
+    </Register>
+    <Register start="+0x04C" size="4" name="FIFOTH" access="Read/Write" description="FIFO Threshold Watermark Register" reset_value="0x0F800000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="TX_WMARK" description="FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming. In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: TX_WMark &gt;= 1; Recommended value: TX_WMARK = 16; (means less than or equal to FIFO_DEPTH/2)." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="12" name="RX_WMARK" description="FIFO threshold watermark level when receiving data to card. When FIFO data count reaches greater than this number, DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data. In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt. In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set. 12 bits - 1 bit less than FIFO-count of status register, which is 13 bits. Limitation: RX_WMark less than FIFO_DEPTH-2 Recommended: RX_WMARK = 15; (means greater than (FIFO_DEPTH/2) - 1)  NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at the end of packet, even if remaining bytes are less than threshold. In this case, there will be some data left in the FIFO. It is the responsibility of the application to reset the FIFO after the CCS time-out." />
+      <BitField start="28" size="3" name="DMA_MTS" description="Burst size of multiple transaction; should be programmed same as DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.The units for transfers is the H_DATA_WIDTH parameter. A single transfer (dw_dma_single assertion in case of Non DW DMA interface) would be signalled based on this value. Value should be sub-multiple of (RX_WMark + 1) and (32 - TX_WMark). For example, if FIFO_DEPTH = 16, FDATA_WIDTH = H_DATA_WIDTH  Allowed combinations for MSize and TX_WMark are:  MSize = 1, TX_WMARK = 1-15  MSize = 4, TX_WMark = 8  MSize = 4, TX_WMark = 4  MSize = 4, TX_WMark = 12  MSize = 8, TX_WMark = 8  MSize = 8, TX_WMark = 4.  Allowed combinations for MSize and RX_WMark are:  MSize = 1, RX_WMARK = 0-14  MSize = 4, RX_WMark = 3  MSize = 4, RX_WMark = 7  MSize = 4, RX_WMark = 11  MSize = 8, RX_WMark = 7  MSize = 8, RX_WMark = 11  Recommended: MSize = 8, TX_WMark = 8, RX_WMark = 7">
+        <Enum name="1_TRANSFER" start="0x0" description="1 transfer" />
+        <Enum name="4_TRANSFERS" start="0x1" description="4 transfers" />
+        <Enum name="8_TRANSFERS" start="0x2" description="8 transfers" />
+        <Enum name="16_TRANSFERS" start="0x3" description="16 transfers" />
+        <Enum name="32_TRANSFERS" start="0x4" description="32 transfers" />
+        <Enum name="64_TRANSFERS" start="0x5" description="64 transfers" />
+        <Enum name="128_TRANSFERS" start="0x6" description="128 transfers" />
+        <Enum name="256_TRANSFERS" start="0x7" description="256 transfers" />
+      </BitField>
+      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x050" size="4" name="CDETECT" access="ReadOnly" description="Card Detect Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CARD_DETECT" description="Card detect. 0 represents presence of card." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x054" size="4" name="WRTPRT" access="ReadOnly" description="Write Protect Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="WRITE_PROTECT" description="Write protect. 1 represents write protection." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x05C" size="4" name="TCBCNT" access="ReadOnly" description="Transferred CIU Card Byte Count Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TRANS_CARD_BYTE_COUNT" description="Number of bytes transferred by CIU unit to card.  Register should be read only after data transfer completes; during data transfer, register returns 0." />
+    </Register>
+    <Register start="+0x060" size="4" name="TBBCNT" access="ReadOnly" description="Transferred Host to BIU-FIFO Byte Count Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TRANS_FIFO_BYTE_COUNT" description="Number of bytes transferred between Host/DMA memory and BIU FIFO." />
+    </Register>
+    <Register start="+0x064" size="4" name="DEBNCE" access="Read/Write" description="Debounce Count Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="24" name="DEBOUNCE_COUNT" description="Number of host clocks (clk) used by debounce filter logic for card detect; typical debounce time is 5-25 ms." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x078" size="4" name="RST_N" access="Read/Write" description="Hardware Reset" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CARD_RESET" description="Hardware reset.  1 - Active mode 0 - Reset  Toggles state on SD_RST pin. This bit causes the card to enter pre-idle state, which requires it to be re-initialized." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080" size="4" name="BMOD" access="Read/Write" description="Bus Mode Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SWR" description="Software Reset. When set, the DMA Controller resets all its internal registers. SWR is read/write. It is automatically cleared after 1 clock cycle." />
+      <BitField start="1" size="1" name="FB" description="Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. FB is read/write." />
+      <BitField start="2" size="5" name="DSL" description="Descriptor Skip Length. Specifies the number of HWord/Word/Dword to skip between two unchained descriptors. This is applicable only for dual buffer structure. DSL is read/write." />
+      <BitField start="7" size="1" name="DE" description="SD/MMC DMA Enable. When set, the SD/MMC DMA is enabled. DE is read/write." />
+      <BitField start="8" size="3" name="PBL" description="Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one SD/MMC DMA transaction. The SD/MMC DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows.Transfer unit is 32 bit. PBL is a read-only value.">
+        <Enum name="1_TRANSFER" start="0x0" description="1 transfer" />
+        <Enum name="4_TRANSFERS" start="0x1" description="4 transfers" />
+        <Enum name="8_TRANSFERS" start="0x2" description="8 transfers" />
+        <Enum name="16_TRANSFERS" start="0x3" description="16 transfers" />
+        <Enum name="32_TRANSFERS" start="0x4" description="32 transfers" />
+        <Enum name="64_TRANSFERS" start="0x5" description="64 transfers" />
+        <Enum name="128_TRANSFERS" start="0x6" description="128 transfers" />
+        <Enum name="256_TRANSFERS" start="0x7" description="256 transfers" />
+      </BitField>
+      <BitField start="11" size="21" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x084" size="4" name="PLDMND" access="WriteOnly" description="Poll Demand Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PD" description="Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the SD/MMC DMA state machine to resume normal descriptor fetch operation. This is a write only register. PD bit is write-only." />
+    </Register>
+    <Register start="+0x088" size="4" name="DBADDR" access="Read/Write" description="Descriptor List Base Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SDL" description="Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the SD/MMC DMA internally. Hence these LSB bits are read-only." />
+    </Register>
+    <Register start="+0x08C" size="4" name="IDSTS" access="Read/Write" description="Internal DMAC Status Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TI" description="Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a 1 clears this bit." />
+      <BitField start="1" size="1" name="RI" description="Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit." />
+      <BitField start="2" size="1" name="FBE" description="Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears this bit." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="1" name="DU" description="Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit." />
+      <BitField start="5" size="1" name="CES" description="Card Error Summary. Indicates the status of the transaction to/from the card; also present in RINTSTS. Indicates the logical OR of the following bits:  EBE - End Bit Error  RTO - Response Time-out/Boot Ack Time-out  RCRC - Response CRC  SBE - Start Bit Error  DRTO - Data Read Time-out/BDS time-out  DCRC - Data CRC for Receive  RE - Response Error  Writing a 1 clears this bit." />
+      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="NIS" description="Normal Interrupt Summary. Logical OR of the following: IDSTS[0] - Transmit Interrupt IDSTS[1] - Receive Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing a 1 clears this bit." />
+      <BitField start="9" size="1" name="AIS" description="Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] - Fatal Bus Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] - Card Error Summary Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing a 1 clears this bit." />
+      <BitField start="10" size="3" name="EB" description="Error Bits. Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt.  001 - Host Abort received during transmission  010 - Host Abort received during reception  Others: Reserved EB is read-only." />
+      <BitField start="13" size="4" name="FSM" description="DMAC state machine present state.  0 - DMA_IDLE  1 - DMA_SUSPEND  2 - DESC_RD  3 - DESC_CHK  4 - DMA_RD_REQ_WAIT  5 - DMA_WR_REQ_WAIT  6 - DMA_RD  7 - DMA_WR  8 - DESC_CLOSE  This bit is read-only." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x090" size="4" name="IDINTEN" access="Read/Write" description="Internal DMAC Interrupt Enable Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TI" description="Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled." />
+      <BitField start="1" size="1" name="RI" description="Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled." />
+      <BitField start="2" size="1" name="FBE" description="Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="1" name="DU" description="Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled." />
+      <BitField start="5" size="1" name="CES" description="Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary." />
+      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="NIS" description="Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN[0] - Transmit Interrupt IDINTEN[1] - Receive Interrupt" />
+      <BitField start="9" size="1" name="AIS" description="Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN[2] - Fatal Bus Error Interrupt IDINTEN[4] - DU Interrupt IDINTEN[5] - Card Error Summary Interrupt" />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x094" size="4" name="DSCADDR" access="ReadOnly" description="Current Host Descriptor Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="HDA" description="Host Descriptor Address Pointer. Cleared on reset. Pointer updated by IDMAC during operation. This register points to the start address of the current descriptor read by the SD/MMC DMA." />
+    </Register>
+    <Register start="+0x098" size="4" name="BUFADDR" access="ReadOnly" description="Current Buffer Descriptor Address Register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="HBA" description="Host Buffer Address Pointer. Cleared on Reset. Pointer updated by IDMAC during operation. This register points to the current Data Buffer Address being accessed by the SD/MMC DMA." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="EMC" start="0x40005000" description="External Memory Controller (EMC) ">
+    <Register start="+0x000" size="4" name="CONTROL" access="Read/Write" description="Controls operation of the memory controller." reset_value="0x3" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="E" description="EMC Enable. Indicates if the EMC is enabled or disabled.Disabling the EMC reduces power consumption. When the memory controller is disabled the memory is not refreshed. The memory controller is enabled by setting the enable bit, or by reset. This bit must only be modified when the EMC is in idle state.[1]">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. (POR and warm reset value)." />
+      </BitField>
+      <BitField start="1" size="1" name="M" description="Address mirror. Indicates normal or reset memory map. On POR, CS1 is mirrored to both CS0 and DYCS0 memory areas. Clearing the M bit enables CS0 and DYCS0 memory to be accessed.">
+        <Enum name="NORMAL" start="0" description="Normal. Normal memory map." />
+        <Enum name="RESET" start="1" description="Reset. Reset memory map. Static memory CS1 is mirrored onto CS0 and DYCS0 (POR reset value)." />
+      </BitField>
+      <BitField start="2" size="1" name="L" description="Low-power mode. Indicates normal, or low-power mode. Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary. The memory controller returns to normal functional mode by clearing the low-power mode bit (L), or by POR. This bit must only be modified when the EMC is in idle state.[1]">
+        <Enum name="NORMAL" start="0" description="Normal. Normal mode (warm reset value)." />
+        <Enum name="LOW_POWER_MODE" start="1" description="Low-power mode." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="STATUS" access="ReadOnly" description="Provides EMC status information." reset_value="0x5" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="B" description="Busy indicator. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not:">
+        <Enum name="IDLE" start="0" description="Idle. EMC is idle (warm reset value)." />
+        <Enum name="BUSY" start="1" description="Busy. EMC is busy performing memory transactions, commands, auto-refresh cycles, or is in self-refresh mode (POR reset value)." />
+      </BitField>
+      <BitField start="1" size="1" name="S" description="Write buffer status. This bit enables the EMC to enter low-power mode or disabled mode cleanly:">
+        <Enum name="EMPTY" start="0" description="Empty. Write buffers empty (POR reset value)" />
+        <Enum name="DATA" start="1" description="Data. Write buffers contain data." />
+      </BitField>
+      <BitField start="2" size="1" name="SA" description="Self-refresh acknowledge. This bit indicates the operating mode of the EMC:">
+        <Enum name="NORMAL_MODE" start="0" description="Normal mode." />
+        <Enum name="SELF_REFRESH_MODE" start="1" description="Self-refresh mode. (POR reset value.)" />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="CONFIG" access="Read/Write" description="Configures operation of the memory controller." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM" description="Endian mode.">
+        <Enum name="LITTLE_ENDIAN_MODE" start="0" description="Little-endian mode. (POR reset value.)" />
+        <Enum name="BIG_ENDIAN_MODE" start="1" description="Big-endian mode." />
+      </BitField>
+      <BitField start="1" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
+      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="DYNAMICCONTROL" access="Read/Write" description="Controls dynamic memory operation." reset_value="0x6" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CE" description="Dynamic memory clock enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Clock enable of idle devices are deasserted to save power (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. All clock enables are driven HIGH continuously.[1]" />
+      </BitField>
+      <BitField start="1" size="1" name="CS" description="Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is stopped when there are no SDRAM transactions. The clock is also stopped during self-refresh mode.">
+        <Enum name="STOP" start="0" description="Stop. CLKOUT stops when all SDRAMs are idle and during self-refresh mode." />
+        <Enum name="RUN" start="1" description="Run. CLKOUT runs continuously (POR reset value)." />
+      </BitField>
+      <BitField start="2" size="1" name="SR" description="Self-refresh request, EMC SREFREQ. By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode. The self-refresh acknowledge bit in the Status register must be polled to discover the current operating mode of the EMC.[2]">
+        <Enum name="NORMAL_MODE" start="0" description="Normal mode." />
+        <Enum name="SELF_REFRESH" start="1" description="Self-refresh. Enter self-refresh mode (POR reset value)." />
+      </BitField>
+      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="5" size="1" name="MMC" description="Memory clock control.">
+        <Enum name="ENABLED" start="0" description="Enabled. CLKOUT enabled (POR reset value)." />
+        <Enum name="DISABLED" start="1" description="Disabled. CLKOUT disabled.[3]" />
+      </BitField>
+      <BitField start="6" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="2" name="I" description="SDRAM initialization.">
+        <Enum name="NORMAL" start="0x0" description="Normal. Issue SDRAM NORMAL operation command (POR reset value)." />
+        <Enum name="MODE" start="0x1" description="Mode. Issue SDRAM MODE command." />
+        <Enum name="PALL" start="0x2" description="PALL. Issue SDRAM PALL (precharge all) command." />
+        <Enum name="NOP" start="0x3" description="NOP. Issue SDRAM NOP (no operation) command)" />
+      </BitField>
+      <BitField start="9" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="14" size="18" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="DYNAMICREFRESH" access="Read/Write" description="Configures dynamic memory refresh operation." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="11" name="REFRESH" description="Refresh timer. Indicates the multiple of 16 EMC_CCLKs between SDRAM refresh cycles. 0x0 = Refresh disabled (POR reset value). 0x1 - 0x7FF = n x16 = 16n EMC_CCLKs between SDRAM refresh cycles. For example: 0x1 = 1 x 16 = 16 EMC_CCLKs between SDRAM refresh cycles. 0x8 = 8 x 16 = 128 EMC_CCLKs between SDRAM refresh cycles" />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="DYNAMICREADCONFIG" access="Read/Write" description="Configures the dynamic memory read strategy." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RD" description="Read data strategy.">
+        <Enum name="DO_NOT_USE" start="0x0" description="Do not use. POR reset value." />
+        <Enum name="HALF" start="0x1" description="Command delayed by 1/2 EMC_CCLK." />
+        <Enum name="HALFPLUSONE" start="0x2" description="Command delayed by 1/2 EMC_CCLK plus one clock cycle." />
+        <Enum name="HALFPLUSTWO" start="0x3" description="Command delayed by1/2 EMC_CCLK plus two clock cycles," />
+      </BitField>
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030" size="4" name="DYNAMICRP" access="Read/Write" description="Selects the precharge command period." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TRP" description="Precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x034" size="4" name="DYNAMICRAS" access="Read/Write" description="Selects the active to precharge command period." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TRAS" description="Active to precharge command period. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x038" size="4" name="DYNAMICSREX" access="Read/Write" description="Selects the self-refresh exit time." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TSREX" description="Self-refresh exit time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x03C" size="4" name="DYNAMICAPR" access="Read/Write" description="Selects the last-data-out to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TAPR" description="Last-data-out to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x040" size="4" name="DYNAMICDAL" access="Read/Write" description="Selects the data-in to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TDAL" description="Data-in to active command. 0x0 - 0xE = n clock cycles. The delay is in EMC_CCLK cycles. 0xF = 15 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x044" size="4" name="DYNAMICWR" access="Read/Write" description="Selects the write recovery time." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TWR" description="Write recovery time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x048" size="4" name="DYNAMICRC" access="Read/Write" description="Selects the active to active command period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="TRC" description="Active to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x04C" size="4" name="DYNAMICRFC" access="Read/Write" description="Selects the auto-refresh period." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="TRFC" description="Auto-refresh period and auto-refresh to active command period. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x050" size="4" name="DYNAMICXSR" access="Read/Write" description="Selects the exit self-refresh to active command time." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="TXSR" description="Exit self-refresh to active command time. 0x0 - 0x1E = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0x1F = 32 clock cycles (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x054" size="4" name="DYNAMICRRD" access="Read/Write" description="Selects the active bank A to active bank B latency." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TRRD" description="Active bank A to active bank B latency 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x058" size="4" name="DYNAMICMRD" access="Read/Write" description="Selects the load mode register to active command time." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="TMRD" description="Load mode register to active command time. 0x0 - 0xE = n + 1 clock cycles. The delay is in EMC_CCLK cycles. 0xF = 16 clock cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x080" size="4" name="STATICEXTENDEDWAIT" access="Read/Write" description="Selects time for long static memory read and write transfers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="EXTENDEDWAIT" description="Extended wait time out. 16 clock cycles (POR reset value). The delay is in EMC_CCLK cycles. 0x0 = 16 clock cycles. 0x1 - 0x3FF = (n+1) x16 clock cycles." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x100+0" size="4" name="DYNAMICCONFIG0" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="2" name="MD" description="Memory device.">
+        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
+        <Enum name="RESERVED" start="0x1" description="Reserved." />
+        <Enum name="RESERVED" start="0x2" description="Reserved." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
+      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="19" size="1" name="B" description="Buffer enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
+        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x100+32" size="4" name="DYNAMICCONFIG1" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="2" name="MD" description="Memory device.">
+        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
+        <Enum name="RESERVED" start="0x1" description="Reserved." />
+        <Enum name="RESERVED" start="0x2" description="Reserved." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
+      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="19" size="1" name="B" description="Buffer enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
+        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x100+64" size="4" name="DYNAMICCONFIG2" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="2" name="MD" description="Memory device.">
+        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
+        <Enum name="RESERVED" start="0x1" description="Reserved." />
+        <Enum name="RESERVED" start="0x2" description="Reserved." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
+      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="19" size="1" name="B" description="Buffer enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
+        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x100+96" size="4" name="DYNAMICCONFIG3" access="Read/Write" description="Selects the configuration information for dynamic memory chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="2" name="MD" description="Memory device.">
+        <Enum name="SDRAM" start="0x0" description="SDRAM (POR reset value)." />
+        <Enum name="RESERVED" start="0x1" description="Reserved." />
+        <Enum name="RESERVED" start="0x2" description="Reserved." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="5" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="6" name="AM0" description="Address mapping. See Table 382. 000000 = reset value.[1]" />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="14" size="1" name="AM1" description="Address mapping See Table 382. 0 = reset value." />
+      <BitField start="15" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="19" size="1" name="B" description="Buffer enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled for accesses to this chip select (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled for accesses to this chip select. After configuration of the dynamic memory, the buffer must be enabled for normal operation. [2]" />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
+        <Enum name="PROTECTED" start="1" description="Protected. Writes protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x104+0" size="4" name="DYNAMICRASCAS0" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
+        <Enum name="RESERVED" start="0x0" description="Reserved." />
+        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
+        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
+        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="2" name="CAS" description="CAS latency.">
+        <Enum name="RESERVED" start="0x0" description="Reserved." />
+        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
+        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
+        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x104+32" size="4" name="DYNAMICRASCAS1" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
+        <Enum name="RESERVED" start="0x0" description="Reserved." />
+        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
+        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
+        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="2" name="CAS" description="CAS latency.">
+        <Enum name="RESERVED" start="0x0" description="Reserved." />
+        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
+        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
+        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x104+64" size="4" name="DYNAMICRASCAS2" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
+        <Enum name="RESERVED" start="0x0" description="Reserved." />
+        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
+        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
+        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="2" name="CAS" description="CAS latency.">
+        <Enum name="RESERVED" start="0x0" description="Reserved." />
+        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
+        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
+        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x104+96" size="4" name="DYNAMICRASCAS3" access="Read/Write" description="Selects the RAS and CAS latencies for dynamic memory chip select 0." reset_value="0x303" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RAS" description="RAS latency (active to read/write delay).">
+        <Enum name="RESERVED" start="0x0" description="Reserved." />
+        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
+        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
+        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="2" name="CAS" description="CAS latency.">
+        <Enum name="RESERVED" start="0x0" description="Reserved." />
+        <Enum name="ONE_EMC_CCLK_CYCLE" start="0x1" description="One EMC_CCLK cycle." />
+        <Enum name="TWO_EMC_CCLK_CYCLES" start="0x2" description="Two EMC_CCLK cycles." />
+        <Enum name="THREE_EMC_CCLK_CYCLE" start="0x3" description="Three EMC_CCLK cycles (POR reset value)." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x200+0" size="4" name="STATICCONFIG0" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="MW" description="Memory width.">
+        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
+        <Enum name="16_BIT" start="0x1" description="16 bit." />
+        <Enum name="32_BIT" start="0x2" description="32 bit." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
+        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
+        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
+        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
+        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
+      </BitField>
+      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
+        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
+        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
+      </BitField>
+      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
+        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
+      </BitField>
+      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
+        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
+        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x200+32" size="4" name="STATICCONFIG1" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="MW" description="Memory width.">
+        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
+        <Enum name="16_BIT" start="0x1" description="16 bit." />
+        <Enum name="32_BIT" start="0x2" description="32 bit." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
+        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
+        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
+        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
+        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
+      </BitField>
+      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
+        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
+        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
+      </BitField>
+      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
+        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
+      </BitField>
+      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
+        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
+        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x200+64" size="4" name="STATICCONFIG2" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="MW" description="Memory width.">
+        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
+        <Enum name="16_BIT" start="0x1" description="16 bit." />
+        <Enum name="32_BIT" start="0x2" description="32 bit." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
+        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
+        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
+        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
+        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
+      </BitField>
+      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
+        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
+        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
+      </BitField>
+      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
+        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
+      </BitField>
+      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
+        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
+        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x200+96" size="4" name="STATICCONFIG3" access="Read/Write" description="Selects the memory configuration for static chip select 0." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="MW" description="Memory width.">
+        <Enum name="8_BIT" start="0x0" description="8 bit (POR reset value)." />
+        <Enum name="16_BIT" start="0x1" description="16 bit." />
+        <Enum name="32_BIT" start="0x2" description="32 bit." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="2" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="1" name="PM" description="Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.">
+        <Enum name="DISABLED" start="0" description="Disabled. (POR reset value.)" />
+        <Enum name="ENABLED" start="1" description="Enabled. Async page mode enabled (page length four)." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="1" name="PC" description="Chip select polarity. The value of the chip select polarity on power-on reset is 0.">
+        <Enum name="ACTIVE_LOW" start="0" description="Active LOW chip select." />
+        <Enum name="ACTIVE_HIGH" start="1" description="Active HIGH chip select." />
+      </BitField>
+      <BitField start="7" size="1" name="PB" description="Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.">
+        <Enum name="HIGH" start="0" description="High. For reads all the bits in BLSn[3:0] are HIGH. For writes the respective active bits in BLSn[3:0] are LOW (POR reset value)." />
+        <Enum name="LOW" start="1" description="Low. For reads the respective active bits in BLSn[3:0] are LOW. For writes the respective active bits in BLSn[3:0] are LOW." />
+      </BitField>
+      <BitField start="8" size="1" name="EW" description="Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]">
+        <Enum name="DISABLED" start="0" description="Disabled. Extended wait disabled (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Extended wait enabled." />
+      </BitField>
+      <BitField start="9" size="10" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="19" size="1" name="B" description="Buffer enable [2].">
+        <Enum name="DISABLED" start="0" description="Disabled. Buffer disabled (POR reset value)." />
+        <Enum name="ENABLED" start="1" description="Enabled. Buffer enabled." />
+      </BitField>
+      <BitField start="20" size="1" name="P" description="Write protect.">
+        <Enum name="NONE" start="0" description="None. Writes not protected (POR reset value)." />
+        <Enum name="PROTECT" start="1" description="Protect. Write protected." />
+      </BitField>
+      <BitField start="21" size="11" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x204+0" size="4" name="STATICWAITWEN0" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x204+32" size="4" name="STATICWAITWEN1" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x204+64" size="4" name="STATICWAITWEN2" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x204+96" size="4" name="STATICWAITWEN3" access="Read/Write" description="Selects the delay from chip select 0 to write enable." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITWEN" description="Wait write enable. Delay from chip select assertion to write enable. 0x0 = One EMC_CCLK cycle delay between assertion of chip select and write enable (POR reset value). 0x1 - 0xF = (n + 1) EMC_CCLK cycle delay. The delay is (WAITWEN +1) x tEMC_CCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x208+0" size="4" name="STATICWAITOEN0" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x208+32" size="4" name="STATICWAITOEN1" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x208+64" size="4" name="STATICWAITOEN2" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x208+96" size="4" name="STATICWAITOEN3" access="Read/Write" description="Selects the delay from chip select 0 or address change, whichever is later, to output enable." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITOEN" description="Wait output enable. Delay from chip select assertion to output enable. 0x0 = No delay (POR reset value). 0x1 - 0xF = n cycle delay. The delay is WAITOEN x tEMC_CCLK." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x20C+0" size="4" name="STATICWAITRD0" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x20C+32" size="4" name="STATICWAITRD1" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x20C+64" size="4" name="STATICWAITRD2" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x20C+96" size="4" name="STATICWAITRD3" access="Read/Write" description="Selects the delay from chip select 0 to a read access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITRD" description="Non-page mode read wait states or asynchronous page mode read first access wait state. Non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1E = (n + 1) EMC_CCLK cycles for read accesses. For non-sequential reads, the wait state time is (WAITRD + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycles for read accesses (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x210+0" size="4" name="STATICWAITPAGE0" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x210+32" size="4" name="STATICWAITPAGE1" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x210+64" size="4" name="STATICWAITPAGE2" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x210+96" size="4" name="STATICWAITPAGE3" access="Read/Write" description="Selects the delay for asynchronous page mode sequential accesses for chip select 0." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITPAGE" description="Asynchronous page mode read after the first read wait states. Number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1E = (n+ 1) EMC_CCLK cycle read access time. For asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (WAITPAGE + 1) x tEMC_CCLK. 0x1F = 32 EMC_CCLK cycle read access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x214+0" size="4" name="STATICWAITWR0" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x214+32" size="4" name="STATICWAITWR1" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x214+64" size="4" name="STATICWAITWR2" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x214+96" size="4" name="STATICWAITWR3" access="Read/Write" description="Selects the delay from chip select 0 to a write access." reset_value="0x1F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="WAITWR" description="Write wait states. SRAM wait state time for write accesses after the first read: 0x0 - 0x1E = (n + 2) EMC_CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tEMC_CCLK. 0x1F = 33 EMC_CCLK cycle write access time (POR reset value)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x218+0" size="4" name="STATICWAITTURN0" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x218+32" size="4" name="STATICWAITTURN1" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x218+64" size="4" name="STATICWAITTURN2" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x218+96" size="4" name="STATICWAITTURN3" access="Read/Write" description="Selects the number of bus turnaround cycles for chip select 0." reset_value="0xF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="WAITTURN" description="Bus turnaround cycles. 0x0 - 0xE = (n + 1) EMC_CCLK turnaround cycles. Bus turnaround time is (WAITTURN + 1) x tEMC_CCLK. 0xF = 16 EMC_CCLK turnaround cycles (POR reset value)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USB0" start="0x40006000" description="USB0 Host/Device/OTG controller">
+    <Register start="+0x100" size="4" name="CAPLENGTH" access="ReadOnly" description="Capability register length" reset_value="0x01000040" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CAPLENGTH" description="Indicates offset to add to the register base address at the beginning of the Operational Register" />
+      <BitField start="8" size="16" name="HCIVERSION" description="BCD encoding of the EHCI revision number supported by this host controller." />
+      <BitField start="24" size="8" name="RESERVED" description="These bits are reserved and should be set to zero." />
+    </Register>
+    <Register start="+0x104" size="4" name="HCSPARAMS" access="ReadOnly" description="Host controller structural parameters" reset_value="0x00010011" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="N_PORTS" description="Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller." />
+      <BitField start="4" size="1" name="PPC" description="Port Power Control. This field indicates whether the host controller implementation includes port power control." />
+      <BitField start="5" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
+      <BitField start="8" size="4" name="N_PCC" description="Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller." />
+      <BitField start="12" size="4" name="N_CC" description="Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller." />
+      <BitField start="16" size="1" name="PI" description="Port indicators. This bit indicates whether the ports support port indicator control." />
+      <BitField start="17" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
+      <BitField start="20" size="4" name="N_PTT" description="Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller." />
+      <BitField start="24" size="4" name="N_TT" description="Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller." />
+      <BitField start="28" size="4" name="RESERVED" description="These bits are reserved and should be set to zero." />
+    </Register>
+    <Register start="+0x108" size="4" name="HCCPARAMS" access="ReadOnly" description="Host controller capability parameters" reset_value="0x00000006" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ADC" description="64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported." />
+      <BitField start="1" size="1" name="PFL" description="Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous." />
+      <BitField start="2" size="1" name="ASP" description="Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register." />
+      <BitField start="4" size="4" name="IST" description="Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule." />
+      <BitField start="8" size="8" name="EECP" description="EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list." />
+      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
+    </Register>
+    <Register start="+0x120" size="4" name="DCIVERSION" access="ReadOnly" description="Device interface version number" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="DCIVERSION" description="The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register." />
+    </Register>
+    <Register start="+0x140" size="4" name="USBCMD_D" access="Read/Write" description="USB command (device mode)" reset_value="0x00080000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RS" description="Run/Stop">
+        <Enum name="DETACH" start="0" description="Writing a 0 to this bit will cause a detach event." />
+        <Enum name="ATTACH" start="1" description="Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." />
+      </BitField>
+      <BitField start="1" size="1" name="RST" description="Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
+        <Enum name="RESETCOMPLETE" start="0" description="Set to 0 by hardware when the reset process is complete." />
+        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." />
+      </BitField>
+      <BitField start="2" size="2" name="RESERVED" description="Not used in device mode." />
+      <BitField start="4" size="1" name="RESERVED" description="Not used in device mode." />
+      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
+      <BitField start="6" size="1" name="RESERVED" description="Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved. These bits should be set to 0." />
+      <BitField start="8" size="2" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
+      <BitField start="11" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="12" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
+      <BitField start="13" size="1" name="SUTW" description="Setup trip wire  During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)." />
+      <BitField start="14" size="1" name="ATDTW" description="Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized." />
+      <BitField start="15" size="1" name="RESERVED" description="Not used in device mode." />
+      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x140" size="4" name="USBCMD_H" access="Read/Write" description="USB command (host mode)" reset_value="0x00080000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RS" description="Run/Stop">
+        <Enum name="HALT" start="0" description="When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." />
+        <Enum name="PROCEED" start="1" description="When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." />
+      </BitField>
+      <BitField start="1" size="1" name="RST" description="Controller reset.  Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
+        <Enum name="RESETCOMPLETE" start="0" description="This bit is set to zero by hardware when the reset process is complete." />
+        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." />
+      </BitField>
+      <BitField start="2" size="1" name="FS0" description="Bit 0 of the Frame List Size bits. See Table 220. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2." />
+      <BitField start="3" size="1" name="FS1" description="Bit 1 of the Frame List Size bits. See Table 220." />
+      <BitField start="4" size="1" name="PSE" description="This bit controls whether the host controller skips processing the periodic schedule.">
+        <Enum name="DO_NOT_PROCESS_THE_P" start="0" description="Do not process the periodic schedule." />
+        <Enum name="USE_THE_PERIODICLIST" start="1" description="Use the PERIODICLISTBASE register to access the periodic schedule." />
+      </BitField>
+      <BitField start="5" size="1" name="ASE" description="This bit controls whether the host controller skips processing the asynchronous schedule.">
+        <Enum name="DO_NOT_PROCESS_THE_A" start="0" description="Do not process the asynchronous schedule." />
+        <Enum name="USE_THE_ASYNCLISTADD" start="1" description="Use the ASYNCLISTADDR to access the asynchronous schedule." />
+      </BitField>
+      <BitField start="6" size="1" name="IAA" description="This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.">
+        <Enum name="THE_HOST_CONTROLLER_" start="0" description="The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." />
+        <Enum name="SOFTWARE_MUST_WRITE_" start="1" description="Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="ASP1_0" description="Asynchronous schedule park mode Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3.  Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior." />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="11" size="1" name="ASPE" description="Asynchronous Schedule Park Mode Enable">
+        <Enum name="PARK_MODE_IS_DISABLE" start="0" description="Park mode is disabled." />
+        <Enum name="PARK_MODE_IS_ENABLED" start="1" description="Park mode is enabled." />
+      </BitField>
+      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="13" size="1" name="RESERVED" description="Not used in Host mode." />
+      <BitField start="14" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="FS2" description="Bit 2 of the Frame List Size bits. See Table 220." />
+      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x144" size="4" name="USBSTS_D" access="Read/Write" description="USB status (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="UI" description="USB interrupt">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
+      </BitField>
+      <BitField start="1" size="1" name="UEI" description="USB error interrupt">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see  Section 18.10.11.6)." />
+      </BitField>
+      <BitField start="2" size="1" name="PCI" description="Port change detect.">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="5" size="1" name="AAI" description="Not used in Device mode." />
+      <BitField start="6" size="1" name="URI" description="USB reset received">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." />
+      </BitField>
+      <BitField start="7" size="1" name="SRI" description="SOF received">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125  ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." />
+      </BitField>
+      <BitField start="8" size="1" name="SLI" description="DCSuspend">
+        <Enum name="ST" start="0" description="The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When a device controller enters a suspend state from an active state, this bit will be set to a one." />
+      </BitField>
+      <BitField start="9" size="3" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
+      <BitField start="12" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="13" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="14" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="15" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="16" size="1" name="NAKI" description="NAK interrupt bit">
+        <Enum name="ST" start="0" description="This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." />
+        <Enum name="CLEAR" start="1" description="It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
+      <BitField start="18" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="19" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
+    </Register>
+    <Register start="+0x144" size="4" name="USBSTS_H" access="Read/Write" description="USB status (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="UI" description="USB interrupt (USBINT)">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
+      </BitField>
+      <BitField start="1" size="1" name="UEI" description="USB error interrupt (USBERRINT)">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." />
+      </BitField>
+      <BitField start="2" size="1" name="PCI" description="Port change detect.">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." />
+      </BitField>
+      <BitField start="3" size="1" name="FRI" description="Frame list roll-over">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX bit 13 toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 18.6.6)." />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="5" size="1" name="AAI" description="Interrupt on async advance">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." />
+      </BitField>
+      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
+      <BitField start="7" size="1" name="SRI" description="SOF received">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." />
+      </BitField>
+      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
+      <BitField start="9" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="12" size="1" name="HCH" description="HCHalted">
+        <Enum name="RS" start="0" description="The RS bit in USBCMD is set to zero. Set by the host controller." />
+        <Enum name="HALT" start="1" description="The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." />
+      </BitField>
+      <BitField start="13" size="1" name="RCL" description="Reclamation">
+        <Enum name="NO_EMPTY_ASYNCHRONOU" start="0" description="No empty asynchronous schedule detected." />
+        <Enum name="EMPTY_ASYNCHRONOU" start="1" description="An empty asynchronous schedule is detected. Set by the host controller." />
+      </BitField>
+      <BitField start="14" size="1" name="PS" description="Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0).">
+        <Enum name="DISABLED" start="0" description="The periodic schedule status is disabled." />
+        <Enum name="DISABLED" start="1" description="The periodic schedule status is enabled." />
+      </BitField>
+      <BitField start="15" size="1" name="AS" description="Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0).">
+        <Enum name="DISABLED" start="0" description="Asynchronous schedule status is disabled." />
+        <Enum name="DISABLED" start="1" description="Asynchronous schedule status is enabled." />
+      </BitField>
+      <BitField start="16" size="1" name="RESERVED" description="Not used on Host mode." />
+      <BitField start="17" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="18" size="1" name="UAI" description="USB host asynchronous interrupt (USBHSTASYNCINT)">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
+      </BitField>
+      <BitField start="19" size="1" name="UPI" description="USB host periodic interrupt (USBHSTPERINT)">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
+      </BitField>
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x148" size="4" name="USBINTR_D" access="Read/Write" description="USB interrupt enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
+      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
+      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
+      <BitField start="3" size="1" name="RESERVED" description="Not used by the Device controller." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RESERVED" description="Not used by the Device controller." />
+      <BitField start="6" size="1" name="URE" description="USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit." />
+      <BitField start="7" size="1" name="SRE" description="SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit." />
+      <BitField start="8" size="1" name="SLE" description="Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit." />
+      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="NAKE" description="NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated." />
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="1" name="RESERVED" description="Not used by the Device controller." />
+      <BitField start="19" size="1" name="RESERVED" description="Not used by the Device controller." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x148" size="4" name="USBINTR_H" access="Read/Write" description="USB interrupt enable (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
+      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
+      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
+      <BitField start="3" size="1" name="FRE" description="Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="AAE" description="Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit." />
+      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
+      <BitField start="7" size="1" name="SRE" description="If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register." />
+      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
+      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="RESERVED" description="Not used by the host controller." />
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="1" name="UAIE" description="USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit." />
+      <BitField start="19" size="1" name="UPIA" description="USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x14C" size="4" name="FRINDEX_D" access="Read/Write" description="USB frame index (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
+      <BitField start="3" size="11" name="FRINDEX13_3" description="Current frame number of the last frame transmitted" />
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x14C" size="4" name="FRINDEX_H" access="Read/Write" description="USB frame index (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
+      <BitField start="3" size="10" name="FRINDEX12_3" description="Frame list current index." />
+      <BitField start="13" size="19" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x154" size="4" name="DEVICEADDR" access="Read/Write" description="USB device address (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="1" name="USBADRA" description="Device address advance">
+        <Enum name="INSTANTANEOUS" start="0" description="Any write to USBADR are instantaneous." />
+        <Enum name="DELAYED" start="1" description="When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." />
+      </BitField>
+      <BitField start="25" size="7" name="USBADR" description="USB device address" />
+    </Register>
+    <Register start="+0x154" size="4" name="PERIODICLISTBASE" access="Read/Write" description="Frame list base address (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="12" size="20" name="PERBASE31_12" description="Base Address (Low) These bits correspond to the memory address signals 31:12." />
+    </Register>
+    <Register start="+0x158" size="4" name="ENDPOINTLISTADDR" access="Read/Write" description="Address of endpoint list in memory" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="11" name="RESERVED" description="reserved" />
+      <BitField start="11" size="21" name="EPBASE31_11" description="Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)" />
+    </Register>
+    <Register start="+0x158" size="4" name="ASYNCLISTADDR" access="Read/Write" description="Address of endpoint list in memory" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="27" name="ASYBASE31_5" description="Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)." />
+    </Register>
+    <Register start="+0x15C" size="4" name="TTCTRL" access="Read/Write" description="Asynchronous buffer status for embedded TT (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
+      <BitField start="24" size="7" name="TTHA" description="Hub address when FS or LS device are connected directly." />
+      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x160" size="4" name="BURSTSIZE" access="Read/Write" description="Programmable burst size" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="RXPBURST" description="Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory." />
+      <BitField start="8" size="8" name="TXPBURST" description="Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x164" size="4" name="TXFILLTUNING" access="Read/Write" description="Host transmit pre-buffer packet tuning (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="TXSCHOH" description="FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set." />
+      <BitField start="8" size="5" name="TXSCHEATLTH" description="Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31." />
+      <BitField start="13" size="3" name="RESERVED" description="reserved" />
+      <BitField start="16" size="6" name="TXFIFOTHRES" description="Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267  ms when a device is connected in High-Speed Mode for OTG and SPH. The time unit represented in this register is 6.333  ms when a device is connected in Low/Full Speed Mode for OTG and SPH." />
+      <BitField start="22" size="10" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x174" size="4" name="BINTERVAL" access="Read/Write" description="Length of virtual frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="BINT" description="bInterval value (see Section 18.7.7)" />
+      <BitField start="4" size="28" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x178" size="4" name="ENDPTNAK" access="Read/Write" description="Endpoint NAK (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPRN0" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="1" size="1" name="EPRN1" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="2" size="1" name="EPRN2" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="3" size="1" name="EPRN3" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="4" size="1" name="EPRN4" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="5" size="1" name="EPRN5" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="6" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="EPTN0" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="17" size="1" name="EPTN1" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="18" size="1" name="EPTN2" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="19" size="1" name="EPTN3" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="20" size="1" name="EPTN4" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="21" size="1" name="EPTN5" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="22" size="10" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x17C" size="4" name="ENDPTNAKEN" access="Read/Write" description="Endpoint NAK Enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPRNE0" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="1" size="1" name="EPRNE1" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="2" size="1" name="EPRNE2" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="3" size="1" name="EPRNE3" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="4" size="1" name="EPRNE4" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="5" size="1" name="EPRNE5" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="6" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="EPTNE0" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="17" size="1" name="EPTNE1" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="18" size="1" name="EPTNE2" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="19" size="1" name="EPTNE3" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="20" size="1" name="EPTNE4" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="21" size="1" name="EPTNE5" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 5 corresponds to endpoint 5. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x184" size="4" name="PORTSC1_D" access="Read/Write" description="Port 1 status/control (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CCS" description="Current connect status">
+        <Enum name="DEVICE_NOT_ATTACHED_" start="0" description="Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." />
+        <Enum name="DEVICE_ATTACHED__A_" start="1" description="Device attached.  A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Not used in device mode" />
+      <BitField start="2" size="1" name="PE" description="Port enable. This bit is always 1. The device port is always enabled." />
+      <BitField start="3" size="1" name="PEC" description="Port enable/disable change This bit is always 0. The device port is always enabled." />
+      <BitField start="4" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="FPR" description="Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well.">
+        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
+        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
+      </BitField>
+      <BitField start="7" size="1" name="SUSP" description="Suspend In device mode, this is a read-only status bit .">
+        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
+        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state" />
+      </BitField>
+      <BitField start="8" size="1" name="PR" description="Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register.">
+        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
+        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
+      </BitField>
+      <BitField start="9" size="1" name="HSP" description="High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons.">
+        <Enum name="NOT_HIGHSSPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
+        <Enum name="HIGHSPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
+      </BitField>
+      <BitField start="10" size="2" name="RESERVED" description="Not used in device mode." />
+      <BitField start="12" size="1" name="RESERVED" description="Not used in device mode." />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the USB0_IND[1:0] pins.">
+        <Enum name="OFF" start="0x0" description="Port indicators are off." />
+        <Enum name="AMBER" start="0x1" description="amber" />
+        <Enum name="GREEN" start="0x2" description="green" />
+        <Enum name="UNDEFINED" start="0x3" description="undefined" />
+      </BitField>
+      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0111 to 1111 are not valid.">
+        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
+        <Enum name="J_STATE" start="0x1" description="J_STATE" />
+        <Enum name="K_STATE" start="0x2" description="K_STATE" />
+        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
+        <Enum name="PACKET" start="0x4" description="Packet" />
+        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
+        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
+      <BitField start="21" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
+      <BitField start="22" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
+      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.">
+        <Enum name="ENABLE" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
+        <Enum name="DISABLE" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
+      </BitField>
+      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
+        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
+        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." />
+      </BitField>
+      <BitField start="25" size="1" name="RESERVED" description="reserved" />
+      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating.">
+        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
+        <Enum name="INVALID_IN_DEVICE_MO" start="0x1" description="invalid in device mode" />
+        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
+      </BitField>
+      <BitField start="28" size="4" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x184" size="4" name="PORTSC1_H" access="Read/Write" description="Port 1 status/control (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CCS" description="Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it.">
+        <Enum name="NO_DEVICE_IS_PRESENT" start="0" description="No device is present." />
+        <Enum name="DEVICE_IS_PRESENT_ON" start="1" description="Device is present on the port." />
+      </BitField>
+      <BitField start="1" size="1" name="CSC" description="Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0">
+        <Enum name="NO_CHANGE_IN_CURRENT" start="0" description="No change in current status." />
+        <Enum name="CHANGE_IN_CURRENT_ST" start="1" description="Change in current status." />
+      </BitField>
+      <BitField start="2" size="1" name="PE" description="Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="PORT_DISABLED_" start="0" description="Port disabled." />
+        <Enum name="PORT_ENABLED_" start="1" description="Port enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="PEC" description="Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,">
+        <Enum name="NO_CHANGE_" start="0" description="No change." />
+        <Enum name="CHANGED" start="1" description="Port enabled/disabled status has changed." />
+      </BitField>
+      <BitField start="4" size="1" name="OCA" description="Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed.">
+        <Enum name="THE_PORT_DOES_NOT_HA" start="0" description="The port does not have an over-current condition." />
+        <Enum name="THE_PORT_HAS_CURRENT" start="1" description="The port has currently an over-current condition." />
+      </BitField>
+      <BitField start="5" size="1" name="OCC" description="Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position." />
+      <BitField start="6" size="1" name="FPR" description="Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
+        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
+      </BitField>
+      <BitField start="7" size="1" name="SUSP" description="Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 240. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
+        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." />
+      </BitField>
+      <BitField start="8" size="1" name="PR" description="Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
+        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
+      </BitField>
+      <BitField start="9" size="1" name="HSP" description="High-speed status">
+        <Enum name="NO_HISPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
+        <Enum name="HISPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
+      </BitField>
+      <BitField start="10" size="2" name="LS" description="Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS.">
+        <Enum name="SE0" start="0x0" description="SE0 (USB_DP and USB_DM LOW)" />
+        <Enum name="J_STATE" start="0x1" description="J-state (USB_DP HIGH and USB_DM LOW)" />
+        <Enum name="K_STATE" start="0x2" description="K-state (USB_DP LOW and USB_DM HIGH)" />
+        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
+      </BitField>
+      <BitField start="12" size="1" name="PP" description="Port power control Host/OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).">
+        <Enum name="PORT_POWER_OFF_" start="0" description="Port power off." />
+        <Enum name="PORT_POWER_ON_" start="1" description="Port power on." />
+      </BitField>
+      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the pins USB0_IND1 and USB0_IND0.">
+        <Enum name="PORT_INDICATORS_ARE_" start="0x0" description="Port indicators are off." />
+        <Enum name="AMBER" start="0x1" description="Amber" />
+        <Enum name="GREEN" start="0x2" description="Green" />
+        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
+      </BitField>
+      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode.  The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved.">
+        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
+        <Enum name="J_STATE" start="0x1" description="J_STATE" />
+        <Enum name="K_STATE" start="0x2" description="K_STATE" />
+        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
+        <Enum name="PACKET" start="0x4" description="Packet" />
+        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
+        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
+        <Enum name="FORCE_ENABLE_LS" start="0x7" description="FORCE_ENABLE_LS" />
+      </BitField>
+      <BitField start="20" size="1" name="WKCN" description="Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0">
+        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device connects." />
+        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." />
+      </BitField>
+      <BitField start="21" size="1" name="WKDC" description="Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device disconnects." />
+        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." />
+      </BitField>
+      <BitField start="22" size="1" name="WKOC" description="Wake on over-current enable (WKOC_E)">
+        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on over-current events." />
+        <Enum name="WRITING_A_ONE_TO_THI" start="1" description="Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." />
+      </BitField>
+      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software.">
+        <Enum name="WRITING_A_0_ENABLES_" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
+        <Enum name="WRITING_A_1_DISABLES" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
+      </BitField>
+      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
+        <Enum name="PORT_CONNECTS_AT_ANY" start="0" description="Port connects at any speed." />
+        <Enum name="WRITING_THIS_BIT_TO_" start="1" description="Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." />
+      </BitField>
+      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator.">
+        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
+        <Enum name="LOW_SPEED" start="0x1" description="Low-speed" />
+        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
+      </BitField>
+    </Register>
+    <Register start="+0x1A4" size="4" name="OTGSC" access="Read/Write" description="OTG status and control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="VD" description="VBUS_Discharge Setting this bit to 1 causes VBUS to discharge through a resistor." />
+      <BitField start="1" size="1" name="VC" description="VBUS_Charge Setting this bit to 1 causes the VBUS line to be charged. This is used for VBUS pulsing during SRP." />
+      <BitField start="2" size="1" name="HAAR" description="Hardware assist auto_reset">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLE_AUTOMATIC_RES" start="1" description="Enable automatic reset after connect on host port." />
+      </BitField>
+      <BitField start="3" size="1" name="OT" description="OTG termination This bit must be set to 1 when the OTG controller is in device mode. This controls the pull-down on USB_DM." />
+      <BitField start="4" size="1" name="DP" description="Data pulsing Setting this bit to 1 causes the pull-up on USB_DP to be asserted for data pulsing during SRP." />
+      <BitField start="5" size="1" name="IDPU" description="ID pull-up. This bit provides control over the pull-up resistor.">
+        <Enum name="PULL_UP_OFF_THE_ID_" start="0" description="Pull-up off. The ID bit will not be sampled." />
+        <Enum name="PULL_UP_ON_" start="1" description="Pull-up on." />
+      </BitField>
+      <BitField start="6" size="1" name="HADP" description="Hardware assist data pulse Write a 1 to start data pulse sequence." />
+      <BitField start="7" size="1" name="HABA" description="Hardware assist B-disconnect to A-connect">
+        <Enum name="DISABLED_" start="0" description="Disabled." />
+        <Enum name="ENABLE_AUTOMATIC_B_D" start="1" description="Enable automatic B-disconnect to A-connect sequence." />
+      </BitField>
+      <BitField start="8" size="1" name="ID" description="USB ID">
+        <Enum name="A_DEVICE" start="0" description="A-device" />
+        <Enum name="B_DEVICE" start="1" description="B-device" />
+      </BitField>
+      <BitField start="9" size="1" name="AVV" description="A-VBUS valid Reading 1 indicates that VBUS is above the A-VBUS valid threshold." />
+      <BitField start="10" size="1" name="ASV" description="A-session valid Reading 1 indicates that VBUS is above the A-session valid threshold." />
+      <BitField start="11" size="1" name="BSV" description="B-session valid Reading 1 indicates that VBUS is above the B-session valid threshold." />
+      <BitField start="12" size="1" name="BSE" description="B-session end Reading 1 indicates that VBUS is below the B-session end threshold." />
+      <BitField start="13" size="1" name="MS1T" description="1 millisecond timer toggle This bit toggles once per millisecond." />
+      <BitField start="14" size="1" name="DPS" description="Data bus pulsing status Reading a 1 indicates that data bus pulsing is detected on the port." />
+      <BitField start="15" size="1" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="IDIS" description="USB ID interrupt status This bit is set when a change on the ID input has been detected. Software must write a 1 to this bit to clear it." />
+      <BitField start="17" size="1" name="AVVIS" description="A-VBUS valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-VBUS valid threshold (4.4 V on an A-device). Software must write a 1 to this bit to clear it." />
+      <BitField start="18" size="1" name="ASVIS" description="A-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-session valid threshold (0.8 V).  Software must write a 1 to this bit to clear it." />
+      <BitField start="19" size="1" name="BSVIS" description="B-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the B-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it." />
+      <BitField start="20" size="1" name="BSEIS" description="B-Session end interrupt status This bit is set then VBUS has fallen below the B-session end threshold.  Software must write a 1 to this bit to clear it." />
+      <BitField start="21" size="1" name="ms1S" description="1 millisecond timer interrupt status This bit is set once every millisecond. Software must write a 1 to this bit to clear it." />
+      <BitField start="22" size="1" name="DPIS" description="Data pulse interrupt status This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when the CM bit in USBMODE = Host (11) and the PortPower bit in PORTSC = Off (0). Software must write a 1 to this bit to clear it." />
+      <BitField start="23" size="1" name="RESERVED" description="reserved" />
+      <BitField start="24" size="1" name="IDIE" description="USB ID interrupt enable Setting this bit enables the interrupt. Writing a 0 disables the interrupt." />
+      <BitField start="25" size="1" name="AVVIE" description="A-VBUS valid interrupt enable Setting this bit enables the A-VBUS valid interrupt. Writing a 0 disables the interrupt." />
+      <BitField start="26" size="1" name="ASVIE" description="A-session valid interrupt enable Setting this bit enables the A-session valid interrupt. Writing a 0 disables the interrupt" />
+      <BitField start="27" size="1" name="BSVIE" description="B-session valid interrupt enable Setting this bit enables the B-session valid interrupt. Writing a 0 disables the interrupt." />
+      <BitField start="28" size="1" name="BSEIE" description="B-session end interrupt enable Setting this bit enables the B-session end interrupt. Writing a 0 disables the interrupt." />
+      <BitField start="29" size="1" name="MS1E" description="1 millisecond timer interrupt enable Setting this bit enables the 1 millisecond timer interrupt. Writing a 0 disables the interrupt." />
+      <BitField start="30" size="1" name="DPIE" description="Data pulse interrupt enable Setting this bit enables the data pulse interrupt. Writing a 0 disables the interrupt" />
+      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1A8" size="4" name="USBMODE_D" access="Read/Write" description="USB device mode (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
+        <Enum name="IDLE" start="0x0" description="Idle" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
+        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
+      </BitField>
+      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
+        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
+        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
+      </BitField>
+      <BitField start="3" size="1" name="SLOM" description="Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8.">
+        <Enum name="SETUP_LOCKOUTS_ON" start="0" description="Setup Lockouts on" />
+        <Enum name="SETUP_LOCKOUTS_OFF" start="1" description="Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD)" />
+      </BitField>
+      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
+        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
+        <Enum name="DISABLED_SETTING_TH" start="1" description="Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
+      <BitField start="6" size="26" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1A8" size="4" name="USBMODE_H" access="Read/Write" description="USB mode (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CM" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
+        <Enum name="IDLE" start="0x0" description="Idle" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
+        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
+      </BitField>
+      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
+        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
+        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Not used in host mode" />
+      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
+        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
+        <Enum name="DISABLED_SETTING_TO" start="1" description="Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." />
+      </BitField>
+      <BitField start="5" size="1" name="VBPS" description="VBUS power select">
+        <Enum name="LOW" start="0" description="vbus_pwr_select is set LOW." />
+        <Enum name="HIGH" start="1" description="vbus_pwr_select is set HIGH" />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1AC" size="4" name="ENDPTSETUPSTAT" access="Read/Write" description="Endpoint setup status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENDPTSETUPSTAT0" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="1" size="1" name="ENDPTSETUPSTAT1" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="2" size="1" name="ENDPTSETUPSTAT2" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="3" size="1" name="ENDPTSETUPSTAT3" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="4" size="1" name="ENDPTSETUPSTAT4" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="5" size="1" name="ENDPTSETUPSTAT5" description="Setup endpoint status for logical endpoints 0 to 5. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="6" size="26" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1B0" size="4" name="ENDPTPRIME" access="Read/Write" description="Endpoint initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PERB0" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
+      <BitField start="1" size="1" name="PERB1" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
+      <BitField start="2" size="1" name="PERB2" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
+      <BitField start="3" size="1" name="PERB3" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
+      <BitField start="4" size="1" name="PERB4" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
+      <BitField start="5" size="1" name="PERB5" description="Prime endpoint receive buffer for physical OUT endpoints 5 to 0. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB5 = endpoint 5" />
+      <BitField start="6" size="10" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="PETB0" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
+      <BitField start="17" size="1" name="PETB1" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
+      <BitField start="18" size="1" name="PETB2" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
+      <BitField start="19" size="1" name="PETB3" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
+      <BitField start="20" size="1" name="PETB4" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
+      <BitField start="21" size="1" name="PETB5" description="Prime endpoint transmit buffer for physical IN endpoints 5 to 0. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB5 = endpoint 5" />
+      <BitField start="22" size="10" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1B4" size="4" name="ENDPTFLUSH" access="Read/Write" description="Endpoint de-initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FERB0" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
+      <BitField start="1" size="1" name="FERB1" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
+      <BitField start="2" size="1" name="FERB2" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
+      <BitField start="3" size="1" name="FERB3" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
+      <BitField start="4" size="1" name="FERB4" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
+      <BitField start="5" size="1" name="FERB5" description="Flush endpoint receive buffer for physical OUT endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB5 = endpoint 5" />
+      <BitField start="6" size="10" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="FETB0" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
+      <BitField start="17" size="1" name="FETB1" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
+      <BitField start="18" size="1" name="FETB2" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
+      <BitField start="19" size="1" name="FETB3" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
+      <BitField start="20" size="1" name="FETB4" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
+      <BitField start="21" size="1" name="FETB5" description="Flush endpoint transmit buffer for physical IN endpoints 5 to 0. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB5 = endpoint 5" />
+      <BitField start="22" size="10" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1B8" size="4" name="ENDPTSTAT" access="ReadOnly" description="Endpoint status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ERBR0" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
+      <BitField start="1" size="1" name="ERBR1" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
+      <BitField start="2" size="1" name="ERBR2" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
+      <BitField start="3" size="1" name="ERBR3" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
+      <BitField start="4" size="1" name="ERBR4" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
+      <BitField start="5" size="1" name="ERBR5" description="Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR5 = endpoint 5" />
+      <BitField start="6" size="10" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="ETBR0" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
+      <BitField start="17" size="1" name="ETBR1" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
+      <BitField start="18" size="1" name="ETBR2" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
+      <BitField start="19" size="1" name="ETBR3" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
+      <BitField start="20" size="1" name="ETBR4" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
+      <BitField start="21" size="1" name="ETBR5" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR5 = endpoint 5" />
+      <BitField start="22" size="10" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1BC" size="4" name="ENDPTCOMPLETE" access="Read/Write" description="Endpoint complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ERCE0" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
+      <BitField start="1" size="1" name="ERCE1" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
+      <BitField start="2" size="1" name="ERCE2" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
+      <BitField start="3" size="1" name="ERCE3" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
+      <BitField start="4" size="1" name="ERCE4" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
+      <BitField start="5" size="1" name="ERCE5" description="Endpoint receive complete event for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE5 = endpoint 5" />
+      <BitField start="6" size="10" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="ETCE0" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
+      <BitField start="17" size="1" name="ETCE1" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
+      <BitField start="18" size="1" name="ETCE2" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
+      <BitField start="19" size="1" name="ETCE3" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
+      <BitField start="20" size="1" name="ETCE4" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
+      <BitField start="21" size="1" name="ETCE5" description="Endpoint transmit complete event for physical IN endpoints 5 to 0. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE5 = endpoint 5" />
+      <BitField start="22" size="10" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1C0" size="4" name="ENDPTCTRL0" access="Read/Write" description="Endpoint control 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="reserved" />
+      <BitField start="2" size="2" name="RXT1_0" description="Endpoint type Endpoint 0 is always a control endpoint." />
+      <BitField start="4" size="3" name="RESERVED" description="reserved" />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
+      <BitField start="8" size="8" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="reserved" />
+      <BitField start="18" size="2" name="TXT1_0" description="Endpoint type Endpoint 0 is always a control endpoint." />
+      <BitField start="20" size="3" name="RESERVED" description="reserved" />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
+      <BitField start="24" size="8" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1C4+0" size="4" name="ENDPTCTRL1" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="RXT" description="Endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="8" size="8" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="reserved" />
+      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="ENABLED" start="0" description="Enabled" />
+        <Enum name="DISABLED" start="1" description="Disabled" />
+      </BitField>
+      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="24" size="8" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1C4+4" size="4" name="ENDPTCTRL2" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="RXT" description="Endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="8" size="8" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="reserved" />
+      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="ENABLED" start="0" description="Enabled" />
+        <Enum name="DISABLED" start="1" description="Disabled" />
+      </BitField>
+      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="24" size="8" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1C4+8" size="4" name="ENDPTCTRL3" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="RXT" description="Endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="8" size="8" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="reserved" />
+      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="ENABLED" start="0" description="Enabled" />
+        <Enum name="DISABLED" start="1" description="Disabled" />
+      </BitField>
+      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="24" size="8" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1C4+12" size="4" name="ENDPTCTRL4" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="RXT" description="Endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="8" size="8" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="reserved" />
+      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="ENABLED" start="0" description="Enabled" />
+        <Enum name="DISABLED" start="1" description="Disabled" />
+      </BitField>
+      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="24" size="8" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x1C4+16" size="4" name="ENDPTCTRL5" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="RXT" description="Endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="8" size="8" name="RESERVED" description="reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request." />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="TXT1_0" description="Tx endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="reserved" />
+      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="ENABLED" start="0" description="Enabled" />
+        <Enum name="DISABLED" start="1" description="Disabled" />
+      </BitField>
+      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="24" size="8" name="RESERVED" description="reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USB1" start="0x40007000" description="USB1 Host/Device controller ">
+    <Register start="+0x100" size="4" name="CAPLENGTH" access="ReadOnly" description="Capability register length" reset_value="0x00010040" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CAPLENGTH" description="Indicates offset to add to the register base address at the beginning of the Operational Register" />
+      <BitField start="8" size="16" name="HCIVERSION" description="BCD encoding of the EHCI revision number supported by this host controller." />
+      <BitField start="24" size="8" name="RESERVED" description="These bits are reserved and should be set to zero." />
+    </Register>
+    <Register start="+0x104" size="4" name="HCSPARAMS" access="ReadOnly" description="Host controller structural parameters" reset_value="0x00010011" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="N_PORTS" description="Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller." />
+      <BitField start="4" size="1" name="PPC" description="Port Power Control. This field indicates whether the host controller implementation includes port power control." />
+      <BitField start="5" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
+      <BitField start="8" size="4" name="N_PCC" description="Number of Ports per Companion Controller. This field indicates the number of ports supported per internal Companion Controller." />
+      <BitField start="12" size="4" name="N_CC" description="Number of Companion Controller. This field indicates the number of companion controllers associated with this USB2.0 host controller." />
+      <BitField start="16" size="1" name="PI" description="Port indicators. This bit indicates whether the ports support port indicator control." />
+      <BitField start="17" size="3" name="RESERVED" description="These bits are reserved and should be set to zero." />
+      <BitField start="20" size="4" name="N_PTT" description="Number of Ports per Transaction Translator. This field indicates the number of ports assigned to each transaction translator within the USB2.0 host controller." />
+      <BitField start="24" size="4" name="N_TT" description="Number of Transaction Translators. This field indicates the number of embedded transaction translators associated with the USB2.0 host controller." />
+      <BitField start="28" size="4" name="RESERVED" description="These bits are reserved and should be set to zero." />
+    </Register>
+    <Register start="+0x108" size="4" name="HCCPARAMS" access="ReadOnly" description="Host controller capability parameters" reset_value="0x00000005" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ADC" description="64-bit Addressing Capability. If zero, no 64-bit addressing capability is supported." />
+      <BitField start="1" size="1" name="PFL" description="Programmable Frame List Flag. If set to one, then the system software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field. The frame list must always be aligned on a 4K-boundary. This requirement ensures that the frame list is always physically contiguous." />
+      <BitField start="2" size="1" name="ASP" description="Asynchronous Schedule Park Capability. If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule.The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register." />
+      <BitField start="4" size="4" name="IST" description="Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule." />
+      <BitField start="8" size="8" name="EECP" description="EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list." />
+      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
+    </Register>
+    <Register start="+0x120" size="4" name="DCIVERSION" access="ReadOnly" description="Device interface version number" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="DCIVERSION" description="The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this register." />
+      <BitField start="16" size="16" name="RESERVED" description="These bits are reserved and should be set to zero." />
+    </Register>
+    <Register start="+0x140" size="4" name="USBCMD_D" access="Read/Write" description="USB command (device mode)" reset_value="0x00040000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RS" description="Run/Stop">
+        <Enum name="DETACH" start="0" description="Writing a 0 to this bit will cause a detach event." />
+        <Enum name="ATACH" start="1" description="Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized." />
+      </BitField>
+      <BitField start="1" size="1" name="RST" description="Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
+        <Enum name="RESETCOMPLETE" start="0" description="Set to 0 by hardware when the reset process is complete." />
+        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0." />
+      </BitField>
+      <BitField start="2" size="2" name="RESERVED" description="Not used in device mode." />
+      <BitField start="4" size="1" name="RESERVED" description="Not used in device mode." />
+      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
+      <BitField start="6" size="1" name="RESERVED" description="Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved. These bits should be set to 0." />
+      <BitField start="8" size="2" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
+      <BitField start="11" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="12" size="1" name="RESERVED" description="Reserved.These bits should be set to 0." />
+      <BitField start="13" size="1" name="SUTW" description="Setup trip wire  During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10)." />
+      <BitField start="14" size="1" name="ATDTW" description="Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized." />
+      <BitField start="15" size="1" name="FS2" description="Not used in device mode." />
+      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x140" size="4" name="USBCMD_H" access="Read/Write" description="USB command (host mode)" reset_value="0x000400B0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RS" description="Run/Stop">
+        <Enum name="HALT" start="0" description="When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one)." />
+        <Enum name="PROCEED" start="1" description="When set to a 1, the Host Controller proceeds with the execution of the schedule. The Host Controller continues execution as long as this bit is set to a one." />
+      </BitField>
+      <BitField start="1" size="1" name="RST" description="Controller reset.  Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.">
+        <Enum name="RESETCOMPLETE" start="0" description="This bit is set to zero by hardware when the reset process is complete." />
+        <Enum name="RESET" start="1" description="When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior." />
+      </BitField>
+      <BitField start="2" size="1" name="FS0" description="Bit 0 of the Frame List Size bits. See Table 281. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. Note that this field is made up from USBCMD bits 15, 3, and 2." />
+      <BitField start="3" size="1" name="FS1" description="Bit 1 of the Frame List Size bits. See Table 281" />
+      <BitField start="4" size="1" name="PSE" description="This bit controls whether the host controller skips processing the periodic schedule.">
+        <Enum name="DO_NOT_PROCESS_THE_P" start="0" description="Do not process the periodic schedule." />
+        <Enum name="USE_THE_PERIODICLIST" start="1" description="Use the PERIODICLISTBASE register to access the periodic schedule." />
+      </BitField>
+      <BitField start="5" size="1" name="ASE" description="This bit controls whether the host controller skips processing the asynchronous schedule.">
+        <Enum name="DO_NOT_PROCESS_THE_A" start="0" description="Do not process the asynchronous schedule." />
+        <Enum name="USE_THE_ASYNCLISTADD" start="1" description="Use the ASYNCLISTADDR to access the asynchronous schedule." />
+      </BitField>
+      <BitField start="6" size="1" name="IAA" description="This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule.">
+        <Enum name="ST" start="0" description="The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one." />
+        <Enum name="DOORBELL" start="1" description="Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="ASP1_0" description="Asynchronous schedule park mode. Contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3.  Software must not write 00 to this bit when Park Mode Enable is one as this will result in undefined behavior." />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="11" size="1" name="ASPE" description="Asynchronous Schedule Park Mode Enable">
+        <Enum name="PARK_MODE_IS_DISABLE" start="0" description="Park mode is disabled." />
+        <Enum name="PARK_MODE_IS_ENABLED" start="1" description="Park mode is enabled." />
+      </BitField>
+      <BitField start="12" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="13" size="1" name="RESERVED" description="Not used in Host mode." />
+      <BitField start="14" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="FS2" description="Bit 2 of the Frame List Size bits. See Table 281." />
+      <BitField start="16" size="8" name="ITC" description="Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x144" size="4" name="USBSTS_D" access="Read/Write" description="USB status (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="UI" description="USB interrupt">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
+      </BitField>
+      <BitField start="1" size="1" name="UEI" description="USB error interrupt">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. The device controller detects resume signaling only (see Section 18.10.11.6)." />
+      </BitField>
+      <BitField start="2" size="1" name="PCI" description="Port change detect.">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit (URI) and the DCSuspend bits (SLI) respectively." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="5" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="6" size="1" name="URI" description="USB reset received">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When the device controller detects a USB Reset and enters the default state, this bit will be set to a one." />
+      </BitField>
+      <BitField start="7" size="1" name="SRI" description="SOF received">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1 ms in device FS mode and every 125  ms in HS mode and will be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp." />
+      </BitField>
+      <BitField start="8" size="1" name="SLI" description="DCSuspend">
+        <Enum name="ST" start="0" description="The device controller clears the bit upon exiting from a suspend state. This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When a device controller enters a suspend state from an active state, this bit will be set to a one." />
+      </BitField>
+      <BitField start="9" size="3" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
+      <BitField start="12" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="13" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="14" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="15" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="16" size="1" name="NAKI" description="NAK interrupt bit">
+        <Enum name="ENDPCLEAR" start="0" description="This bit is automatically cleared by hardware when the all the enabled TX/RX Endpoint NAK bits are cleared." />
+        <Enum name="SET" start="1" description="It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint NAK Enable bit are set." />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
+      <BitField start="18" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="19" size="1" name="RESERVED" description="Not used in Device mode." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved. Software should only write 0 to reserved bits." />
+    </Register>
+    <Register start="+0x144" size="4" name="USBSTS_H" access="Read/Write" description="USB status (host mode)" reset_value="0x00001000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="UI" description="USB interrupt (USBINT)">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
+      </BitField>
+      <BitField start="1" size="1" name="UEI" description="USB error interrupt (USBERRINT)">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set." />
+      </BitField>
+      <BitField start="2" size="1" name="PCI" description="Port change detect.">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port." />
+      </BitField>
+      <BitField start="3" size="1" name="FRI" description="Frame list roll-over">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX bit 12 toggles (see Section 19.6.5)." />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="5" size="1" name="AAI" description="Interrupt on async advance">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source." />
+      </BitField>
+      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
+      <BitField start="7" size="1" name="SRI" description="SOF received">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="In host mode, this bit will be set every 125 ms and can be used by host controller driver as a time base." />
+      </BitField>
+      <BitField start="8" size="1" name="SLI" description="Not used by the Host controller." />
+      <BitField start="9" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="12" size="1" name="HCH" description="HCHalted">
+        <Enum name="RS" start="0" description="The RS bit in USBCMD is set to zero. Set by the host controller." />
+        <Enum name="STOP" start="1" description="The Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. because of an internal error)." />
+      </BitField>
+      <BitField start="13" size="1" name="RCL" description="Reclamation">
+        <Enum name="NO_EMPTY_ASYNCHRONOU" start="0" description="No empty asynchronous schedule detected." />
+        <Enum name="EMPTY_ASYNCHRONOU" start="1" description="An empty asynchronous schedule is detected. Set by the host controller." />
+      </BitField>
+      <BitField start="14" size="1" name="PS" description="Periodic schedule status This bit reports the current real status of the Periodic Schedule. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (if both are 1) or disabled (if both are 0).">
+        <Enum name="DISABLED" start="0" description="The periodic schedule status is disabled." />
+        <Enum name="ENABLED" start="1" description="The periodic schedule status is enabled." />
+      </BitField>
+      <BitField start="15" size="1" name="AS" description="Asynchronous schedule status This bit reports the current real status of the Asynchronous Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (if both are 1) or disabled (if both are 0).">
+        <Enum name="DISABLED" start="0" description="Asynchronous schedule status is disabled." />
+        <Enum name="ENABLED" start="1" description="Asynchronous schedule status is enabled." />
+      </BitField>
+      <BitField start="16" size="1" name="RESERVED" description="Not used on Host mode." />
+      <BitField start="17" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="18" size="1" name="UAI" description="USB host asynchronous interrupt (USBHSTASYNCINT)">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
+      </BitField>
+      <BitField start="19" size="1" name="UPI" description="USB host periodic interrupt (USBHSTPERINT)">
+        <Enum name="ST" start="0" description="This bit is cleared by software writing a one to it." />
+        <Enum name="CLEAR" start="1" description="This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than the expected number of bytes." />
+      </BitField>
+      <BitField start="20" size="12" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x148" size="4" name="USBINTR_D" access="Read/Write" description="USB interrupt enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
+      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
+      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
+      <BitField start="3" size="1" name="RESERVED" description="Not used by the Device controller." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RESERVED" description="Not used by the Device controller." />
+      <BitField start="6" size="1" name="URE" description="USB reset enable When this bit is a one, and the USB Reset Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit." />
+      <BitField start="7" size="1" name="SRE" description="SOF received enable When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the device controller will issue an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit." />
+      <BitField start="8" size="1" name="SLE" description="Sleep enable When this bit is a one, and the DCSuspend bit in the USBSTS register transitions, the device controller will issue an interrupt. The interrupt is acknowledged by software writing a one to the DCSuspend bit." />
+      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="NAKE" description="NAK interrupt enable This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated." />
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="1" name="UAIE" description="Not used by the Device controller." />
+      <BitField start="19" size="1" name="UPIA" description="Not used by the Device controller." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x148" size="4" name="USBINTR_H" access="Read/Write" description="USB interrupt enable (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="UE" description="USB interrupt enable When this bit is one, and the USBINT bit in the USBSTS register is one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit in USBSTS." />
+      <BitField start="1" size="1" name="UEE" description="USB error interrupt enable When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host/device controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register." />
+      <BitField start="2" size="1" name="PCE" description="Port change detect enable When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host/device controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit in USBSTS." />
+      <BitField start="3" size="1" name="FRE" description="Frame list rollover enable When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="AAE" description="Interrupt on asynchronous advance enable When this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit." />
+      <BitField start="6" size="1" name="RESERVED" description="Not used by the Host controller." />
+      <BitField start="7" size="1" name="SRE" description="If this bit is one and the SRI bit in the USBSTS register is one, the host controller will issue an interrupt. In host mode, the SRI bit will be set every 125 ms and can be used by the host controller as a time base. The interrupt is acknowledged by software clearing the SRI bit in the USBSTS register." />
+      <BitField start="8" size="1" name="RESERVED" description="Not used by the Host controller." />
+      <BitField start="9" size="7" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="RESERVED" description="Not used by the host controller." />
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="1" name="UAIE" description="USB host asynchronous interrupt enable When this bit is a one, and the USBHSTASYNCINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTASYNCINT bit." />
+      <BitField start="19" size="1" name="UPIA" description="USB host periodic interrupt enable When this bit is a one, and the USBHSTPERINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBHSTPERINT bit." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x14C" size="4" name="FRINDEX_D" access="ReadOnly" description="USB frame index (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
+      <BitField start="3" size="11" name="FRINDEX13_3" description="Current frame number of the last frame transmitted" />
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x14C" size="4" name="FRINDEX_H" access="Read/Write" description="USB frame index (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="FRINDEX2_0" description="Current micro frame number" />
+      <BitField start="3" size="10" name="FRINDEX12_3" description="Frame list current index for 1024 elements." />
+      <BitField start="13" size="19" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x154" size="4" name="DEVICEADDR" access="Read/Write" description="USB device address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="RESERVED" description="reserved" />
+      <BitField start="24" size="1" name="USBADRA" description="Device address advance">
+        <Enum name="ADVANCE" start="0" description="Any write to USBADR are instantaneous." />
+        <Enum name="HOLD" start="1" description="When the user writes a one to this bit at the same time or before USBADR is written, the write to USBADR fields is staged and held in a hidden register. After an IN occurs on endpoint 0 and is acknowledged, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: IN is ACKed to endpoint 0. USBADR is updated from the staging register. OUT/SETUP occurs on endpoint 0. USBADR is not updated. Device reset occurs. USBADR is set to 0. After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write the device address within 2 ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2 ms USB requirement." />
+      </BitField>
+      <BitField start="25" size="7" name="USBADR" description="USB device address" />
+    </Register>
+    <Register start="+0x154" size="4" name="PERIODICLISTBASE" access="Read/Write" description="Frame list base address" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="12" size="20" name="PERBASE31_12" description="Base Address (Low) These bits correspond to the memory address signals[31:12]." />
+    </Register>
+    <Register start="+0x158" size="4" name="ENDPOINTLISTADDR" access="Read/Write" description="Address of endpoint list in memory (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="11" name="RESERVED" description="reserved" />
+      <BitField start="11" size="21" name="EPBASE31_11" description="Endpoint list pointer (low) These bits correspond to memory address signals 31:11, respectively. This field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head per endpoint and direction.)" />
+    </Register>
+    <Register start="+0x158" size="4" name="ASYNCLISTADDR" access="Read/Write" description="Address of endpoint list in memory (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="27" name="ASYBASE31_5" description="Link pointer (Low) LPL These bits correspond to memory address signals 31:5, respectively. This field may only reference a Queue Head (OH)." />
+    </Register>
+    <Register start="+0x15C" size="4" name="TTCTRL" access="Read/Write" description="Asynchronous buffer status for embedded TT (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="RESERVED" description="Reserved." />
+      <BitField start="24" size="7" name="TTHA" description="Hub address when FS or LS device are connected directly." />
+      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x160" size="4" name="BURSTSIZE" access="Read/Write" description="Programmable burst size" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="RXPBURST" description="Programmable RX burst length This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory." />
+      <BitField start="8" size="8" name="TXPBURST" description="Programmable TX burst length This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus." />
+      <BitField start="16" size="16" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x164" size="4" name="TXFILLTUNING" access="Read/Write" description="Host transmit pre-buffer packet tuning (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="TXSCHOH" description="FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USBMODE register is set." />
+      <BitField start="8" size="5" name="TXSCHEATLTH" description="Scheduler health counter This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame . This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter. The maximum value is 31." />
+      <BitField start="13" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="6" name="TXFIFOTHRES" description="Scheduler overhead This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267  ms when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333  ms when a device is connected in Low/Full Speed Mode." />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x170" size="4" name="ULPIVIEWPORT" access="Read/Write" description="ULPI viewport" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ULPIDATWR" description="When a write operation is commanded, the  data to be sent is written to this field." />
+      <BitField start="8" size="8" name="ULPIDATRD" description="After a read operation completes, the result is  placed in this field." />
+      <BitField start="16" size="8" name="ULPIADDR" description="When a read or write operation is  commanded, the address of the operation is written to this field." />
+      <BitField start="24" size="3" name="ULPIPORT" description="For the wakeup or read/write operation to  be executed, this value must be written as 0." />
+      <BitField start="27" size="1" name="ULPISS" description="ULPI sync state. This bit represents the state of the ULPI  interface.">
+        <Enum name="IN_ANOTHER_STATE" start="0" description="In another state  (ie. carkit, serial, low power)" />
+        <Enum name="NORMAL_SYNC_STATE_" start="1" description="Normal Sync. State." />
+      </BitField>
+      <BitField start="28" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="29" size="1" name="ULPIRW" description="ULPI Read/Write control. This bit selects between running a read or write operation.">
+        <Enum name="READ" start="0" description="Read" />
+        <Enum name="WRITE" start="1" description="Write" />
+      </BitField>
+      <BitField start="30" size="1" name="ULPIRUN" description="ULPI Read/Write Run. Writing the 1 to this bit will begin the  read/write operation. The bit will automatically transition to 0 after the  read/write is complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at  the same time." />
+      <BitField start="31" size="1" name="ULPIWU" description="ULPI Wake-up.  Writing the 1 to this bit will begin the wakeup  operation. The bit will automatically transition to 0 after the wakeup is  complete. Once this bit is set, the driver can not set it back to 0. The driver must never executue a wakeup and a read/write operation at  the same time." />
+    </Register>
+    <Register start="+0x174" size="4" name="BINTERVAL" access="Read/Write" description="Length of virtual frame" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="BINT" description="bInterval value" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x178" size="4" name="ENDPTNAK" access="Read/Write" description="Endpoint NAK (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPRN0" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="1" size="1" name="EPRN1" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="2" size="1" name="EPRN2" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="3" size="1" name="EPRN3" description="Rx endpoint NAK Each RX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="EPTN16" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="17" size="1" name="EPTN17" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="18" size="1" name="EPTN18" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="19" size="1" name="EPTN19" description="Tx endpoint NAK Each TX endpoint has one bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x17C" size="4" name="ENDPTNAKEN" access="Read/Write" description="Endpoint NAK Enable (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EPRNE0" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="1" size="1" name="EPRNE1" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="2" size="1" name="EPRNE2" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="3" size="1" name="EPRNE3" description="Rx endpoint NAK enable Each bit enables the corresponding RX NAK bit. If this bit is set and the corresponding RX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="EPTNE16" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="17" size="1" name="EPTNE17" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="18" size="1" name="EPTNE18" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="19" size="1" name="EPTNE19" description="Tx endpoint NAK Each bit enables the corresponding TX NAK bit. If this bit is set and the corresponding TX endpoint NAK bit is set, the NAK interrupt bit is set. Bit 3 corresponds to endpoint 3. ... Bit 1 corresponds to endpoint 1. Bit 0 corresponds to endpoint 0." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x184" size="4" name="PORTSC1_D" access="Read/Write" description="Port 1 status/control (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CCS" description="Current connect status">
+        <Enum name="DEVICE_NOT_ATTACHED_" start="0" description="Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended." />
+        <Enum name="DEVICE_ATTACHED__A_" start="1" description="Device attached.  A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register." />
+      </BitField>
+      <BitField start="1" size="1" name="CSC" description="Not used in device mode" />
+      <BitField start="2" size="1" name="PE" description="Port enable. This bit is always 1. The device port is always enabled." />
+      <BitField start="3" size="1" name="PEC" description="Port enable/disable change This bit is always 0. The device port is always enabled." />
+      <BitField start="4" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="FPR" description="Force port resume After the device has been in Suspend State for 5 ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. When this bit transitions to a one because a J-to-K transition detected, the Port Change Detect bit in the USBSTS register is set to one as well.">
+        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
+        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
+      </BitField>
+      <BitField start="7" size="1" name="SUSP" description="Suspend In device mode, this is a read-only status bit .">
+        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
+        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state" />
+      </BitField>
+      <BitField start="8" size="1" name="PR" description="Port reset In device mode, this is a read-only status bit. A device reset from the USB bus is also indicated in the USBSTS register.">
+        <Enum name="PORT_IS_NOT_IN_THE_R" start="0" description="Port is not in the reset state." />
+        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
+      </BitField>
+      <BitField start="9" size="1" name="HSP" description="High-speed status This bit is redundant with bits 27:26 (PSPD) in this register. It is implemented for compatibility reasons.">
+        <Enum name="NOHISPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
+        <Enum name="HISPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
+      </BitField>
+      <BitField start="10" size="2" name="LS" description="Not used in device mode." />
+      <BitField start="12" size="1" name="PP" description="Not used in device mode." />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field effects the value of the USB1_IND1:0 pins.">
+        <Enum name="OFF" start="0x0" description="Port indicators are off." />
+        <Enum name="AMBER" start="0x1" description="amber" />
+        <Enum name="GREEN" start="0x2" description="green" />
+        <Enum name="UNDEFINED" start="0x3" description="undefined" />
+      </BitField>
+      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_HS/FS/LS values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x7 to 0xF are reserved.">
+        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
+        <Enum name="J_STATE" start="0x1" description="J_STATE" />
+        <Enum name="K_STATE" start="0x2" description="K_STATE" />
+        <Enum name="SE0" start="0x3" description="SE0 (host)/NAK (device)" />
+        <Enum name="PACKET" start="0x4" description="Packet" />
+        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
+        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
+      <BitField start="21" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
+      <BitField start="22" size="1" name="RESERVED" description="Not used in device mode. This bit is always 0 in device mode." />
+      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In device mode, The PHY can be put into Low Power Suspend - Clock Disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.">
+        <Enum name="ENABLED" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
+        <Enum name="DISABLED" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
+      </BitField>
+      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
+        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
+        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at full speed. It disables the chirp sequence that allows the port to identify itself as High-speed. This is useful for testing FS configurations with a HS host, hub or device." />
+      </BitField>
+      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating.">
+        <Enum name="FULL_SPEED" start="0x1" description="Full-speed" />
+        <Enum name="INVALID_IN_DEVICE_MO" start="0x2" description="invalid in device mode" />
+        <Enum name="HIGH_SPEED" start="0x3" description="High-speed" />
+      </BitField>
+      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="2" name="PTS" description="Parallel transceiver select. All other values are reserved.">
+        <Enum name="ULPI" start="0x2" description="ULPI" />
+        <Enum name="SERIAL" start="0x3" description="Serial/ 1.1 PHY (Full-speed only)" />
+      </BitField>
+    </Register>
+    <Register start="+0x184" size="4" name="PORTSC1_H" access="Read/Write" description="Port 1 status/control (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CCS" description="Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it.">
+        <Enum name="NO_DEVICE_IS_PRESENT" start="0" description="No device is present." />
+        <Enum name="DEVICE_IS_PRESENT_ON" start="1" description="Device is present on the port." />
+      </BitField>
+      <BitField start="1" size="1" name="CSC" description="Connect status change Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0">
+        <Enum name="NO_CHANGE_IN_CURRENT" start="0" description="No change in current status." />
+        <Enum name="CHANGE_IN_CURRENT_ST" start="1" description="Change in current status." />
+      </BitField>
+      <BitField start="2" size="1" name="PE" description="Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="PORT_DISABLED_" start="0" description="Port disabled." />
+        <Enum name="PORT_ENABLED_" start="1" description="Port enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="PEC" description="Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,">
+        <Enum name="NO_CHANGE_" start="0" description="No change." />
+        <Enum name="CHANGED" start="1" description="Port enabled/disabled status has changed." />
+      </BitField>
+      <BitField start="4" size="1" name="OCA" description="Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed.">
+        <Enum name="THE_PORT_DOES_NOT_HA" start="0" description="The port does not have an over-current condition." />
+        <Enum name="THE_PORT_HAS_CURRENT" start="1" description="The port has currently an over-current condition." />
+      </BitField>
+      <BitField start="5" size="1" name="OCC" description="Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position." />
+      <BitField start="6" size="1" name="FPR" description="Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="NO_RESUME" start="0" description="No resume (K-state) detected/driven on port." />
+        <Enum name="RESUME_DETECTED" start="1" description="Resume detected/driven on port." />
+      </BitField>
+      <BitField start="7" size="1" name="SUSP" description="Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 302 Port states as described by the PE and SUSP bits in the PORTSC1 register. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="PORT_NOT_IN_SUSPEND_" start="0" description="Port not in suspend state" />
+        <Enum name="PORT_IN_SUSPEND_STAT" start="1" description="Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB." />
+      </BitField>
+      <BitField start="8" size="1" name="PR" description="Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="NOT_IN_RESET" start="0" description="Port is not in the reset state." />
+        <Enum name="PORT_IS_IN_THE_RESET" start="1" description="Port is in the reset state." />
+      </BitField>
+      <BitField start="9" size="1" name="HSP" description="High-speed status">
+        <Enum name="NOHIGHSPEED" start="0" description="Host/device connected to the port is not in High-speed mode." />
+        <Enum name="HIGHSPEED" start="1" description="Host/device connected to the port is in High-speed mode." />
+      </BitField>
+      <BitField start="10" size="2" name="LS" description="Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS.">
+        <Enum name="SE0" start="0x0" description="SE0 (USB_DP and USB_DM LOW)" />
+        <Enum name="J_STATE" start="0x1" description="J-state (USB_DP HIGH and USB_DM LOW)" />
+        <Enum name="K_STATE" start="0x2" description="K-state (USB_DP LOW and USB_DM HIGH)" />
+        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
+      </BitField>
+      <BitField start="12" size="1" name="PP" description="Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).">
+        <Enum name="PORT_POWER_OFF_" start="0" description="Port power off." />
+        <Enum name="PORT_POWER_ON_" start="1" description="Port power on." />
+      </BitField>
+      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="14" size="2" name="PIC1_0" description="Port indicator control Writing to this field controls the value of the pins USB1_IND1 and USB1_IND0.">
+        <Enum name="OFF" start="0x0" description="Port indicators are off." />
+        <Enum name="AMBER" start="0x1" description="Amber" />
+        <Enum name="GREEN" start="0x2" description="Green" />
+        <Enum name="UNDEFINED" start="0x3" description="Undefined" />
+      </BitField>
+      <BitField start="16" size="4" name="PTC3_0" description="Port test control Any value other than 0000 indicates that the port is operating in test mode.  The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved.">
+        <Enum name="TEST_MODE_DISABLE" start="0x0" description="TEST_MODE_DISABLE" />
+        <Enum name="J_STATE" start="0x1" description="J_STATE" />
+        <Enum name="K_STATE" start="0x2" description="K_STATE" />
+        <Enum name="SE0_NAK" start="0x3" description="SE0 (host)/NAK (device)" />
+        <Enum name="PACKET" start="0x4" description="Packet" />
+        <Enum name="FORCE_ENABLE_HS" start="0x5" description="FORCE_ENABLE_HS" />
+        <Enum name="FORCE_ENABLE_FS" start="0x6" description="FORCE_ENABLE_FS" />
+        <Enum name="FORCE_ENABLE_LS" start="0x7" description="FORCE_ENABLE_LS" />
+      </BitField>
+      <BitField start="20" size="1" name="WKCN" description="Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0">
+        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device connects." />
+        <Enum name="ENABLE_DEVICE_CON" start="1" description="Writing this bit to a one enables the port to be sensitive to device connects as wake-up events." />
+      </BitField>
+      <BitField start="21" size="1" name="WKDC" description="Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.">
+        <Enum name="DISABLES_THE_PORT_TO" start="0" description="Disables the port to wake up on device disconnects." />
+        <Enum name="ENABLE_DEVICE_CON" start="1" description="Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events." />
+      </BitField>
+      <BitField start="22" size="1" name="WKOC" description="Wake on over-current enable (WKOC_E)">
+        <Enum name="DISABLES_OVERCURRENT" start="0" description="Disables the port to wake up on over-current events." />
+        <Enum name="ENABLE_OVERCURRENT" start="1" description="Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events." />
+      </BitField>
+      <BitField start="23" size="1" name="PHCD" description="PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software.">
+        <Enum name="ENABLE_PHY_CLK" start="0" description="Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled)." />
+        <Enum name="DISABLE_PHY_CLK" start="1" description="Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled)." />
+      </BitField>
+      <BitField start="24" size="1" name="PFSC" description="Port force full speed connect">
+        <Enum name="ANYSPEED" start="0" description="Port connects at any speed." />
+        <Enum name="FULLSPEED" start="1" description="Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device." />
+      </BitField>
+      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="26" size="2" name="PSPD" description="Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator.">
+        <Enum name="FULL_SPEED" start="0x0" description="Full-speed" />
+        <Enum name="LOW_SPEED" start="0x1" description="Low-speed" />
+        <Enum name="HIGH_SPEED" start="0x2" description="High-speed" />
+      </BitField>
+      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="2" name="PTS" description="Parallel transceiver select. All other values are reserved.">
+        <Enum name="ULPI" start="0x2" description="ULPI" />
+        <Enum name="SERIAL" start="0x3" description="Serial/ 1.1 PHY (Full-speed only)" />
+      </BitField>
+    </Register>
+    <Register start="+0x1A8" size="4" name="USBMODE_D" access="Read/Write" description="USB mode (device mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
+        <Enum name="IDLE" start="0x0" description="Idle" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
+        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
+      </BitField>
+      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
+        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
+        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
+      </BitField>
+      <BitField start="3" size="1" name="SLOM" description="Setup Lockout mode In device mode, this bit controls behavior of the setup lock mechanism. See Section 18.10.8.">
+        <Enum name="SETUP_LOCKOUTS_ON" start="0" description="Setup Lockouts on" />
+        <Enum name="SETUP_LOCKOUTS_OFF" start="1" description="Setup Lockouts Off (DCD requires the use of Setup Buffer Tripwire in USBCMD)" />
+      </BitField>
+      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
+        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
+        <Enum name="DISABLED_SETTING_TH" start="1" description="Disabled. Setting this bit to one disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is active." />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Not used in device mode." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1A8" size="4" name="USBMODE_H" access="Read/Write" description="USB mode (host mode)" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CM1_0" description="Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register.">
+        <Enum name="IDLE" start="0x0" description="Idle" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="DEVICE_CONTROLLER" start="0x2" description="Device controller" />
+        <Enum name="HOST_CONTROLLER" start="0x3" description="Host controller" />
+      </BitField>
+      <BitField start="2" size="1" name="ES" description="Endian select This bit can change the byte ordering of the transfer buffers. The bit fields in the microprocessor interface and the DMA data structures (including the setup buffer within the device QH) are unaffected by the value of this bit, because they are based upon 32-bit words.">
+        <Enum name="LITTLE_ENDIAN_FIRST" start="0" description="Little endian: first byte referenced in least significant byte of 32-bit word." />
+        <Enum name="BIG_ENDIAN_FIRST_BY" start="1" description="Big endian: first byte referenced in most significant byte of 32-bit word." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Not used in host mode" />
+      <BitField start="4" size="1" name="SDIS" description="Stream disable mode  The use of this feature substantially limits the overall USB performance that can be achieved.">
+        <Enum name="NOT_DISABLED" start="0" description="Not disabled" />
+        <Enum name="DISABLED_SETTING_TO" start="1" description="Disabled. Setting to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet is launched onto the USB. Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature." />
+      </BitField>
+      <BitField start="5" size="1" name="VBPS" description="VBUS power select">
+        <Enum name="LOW" start="0" description="vbus_pwr_select is set LOW." />
+        <Enum name="HIGH" start="1" description="vbus_pwr_select is set HIGH" />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1AC" size="4" name="ENDPTSETUPSTAT" access="Read/Write" description="Endpoint setup status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENDPTSETUPSTAT0" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="1" size="1" name="ENDPTSETUPSTAT1" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="2" size="1" name="ENDPTSETUPSTAT2" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="3" size="1" name="ENDPTSETUPSTAT3" description="Setup endpoint status for logical endpoints. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lockout mechanism is engaged." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1B0" size="4" name="ENDPTPRIME" access="Read/Write" description="Endpoint initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PERB0" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
+      <BitField start="1" size="1" name="PERB1" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
+      <BitField start="2" size="1" name="PERB2" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
+      <BitField start="3" size="1" name="PERB3" description="Prime endpoint receive buffer for physical OUT endpoints. For each OUT endpoint, a corresponding bit is set to 1 by software to request a buffer be prepared for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB0 = endpoint 0 ... PERB3 = endpoint 3" />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="PETB0" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
+      <BitField start="17" size="1" name="PETB1" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
+      <BitField start="18" size="1" name="PETB2" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
+      <BitField start="19" size="1" name="PETB3" description="Prime endpoint transmit buffer for physical IN endpoints. For each IN endpoint a corresponding bit is set to one by software to request a buffer be prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.  PETB0 = endpoint 0 ... PETB3 = endpoint 3" />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1B4" size="4" name="ENDPTFLUSH" access="Read/Write" description="Endpoint de-initialization" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FERB0" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
+      <BitField start="1" size="1" name="FERB1" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
+      <BitField start="2" size="1" name="FERB2" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
+      <BitField start="3" size="1" name="FERB3" description="Flush endpoint receive buffer for physical OUT endpoints. Writing a one to a bit(s) will clear any primed buffers. FERB0 = endpoint 0 ... FERB3 = endpoint 3" />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="FETB0" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
+      <BitField start="17" size="1" name="FETB1" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
+      <BitField start="18" size="1" name="FETB2" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
+      <BitField start="19" size="1" name="FETB3" description="Flush endpoint transmit buffer for physical IN endpoints. Writing a one to a bit(s) will clear any primed buffers.  FETB0 = endpoint 0 ... FETB3 = endpoint 3" />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1B8" size="4" name="ENDPTSTAT" access="ReadOnly" description="Endpoint status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ERBR0" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
+      <BitField start="1" size="1" name="ERBR1" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
+      <BitField start="2" size="1" name="ERBR2" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
+      <BitField start="3" size="1" name="ERBR3" description="Endpoint receive buffer ready for physical OUT endpoints. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 ... ERBR3 = endpoint 3" />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="ETBR0" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
+      <BitField start="17" size="1" name="ETBR1" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
+      <BitField start="18" size="1" name="ETBR2" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
+      <BitField start="19" size="1" name="ETBR3" description="Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 ... ETBR3 = endpoint 3" />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1BC" size="4" name="ENDPTCOMPLETE" access="Read/Write" description="Endpoint complete" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ERCE0" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
+      <BitField start="1" size="1" name="ERCE1" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
+      <BitField start="2" size="1" name="ERCE2" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
+      <BitField start="3" size="1" name="ERCE3" description="Endpoint receive complete event for physical OUT endpoints. This bit is set to 1 by hardware when receive event (OUT/SETUP) occurred. ERCE0 = endpoint 0 ... ERCE3 = endpoint 3" />
+      <BitField start="4" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="ETCE0" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
+      <BitField start="17" size="1" name="ETCE1" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
+      <BitField start="18" size="1" name="ETCE2" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
+      <BitField start="19" size="1" name="ETCE3" description="Endpoint transmit complete event for physical IN endpoints. This bit is set to 1 by hardware when a transmit event (IN/INTERRUPT) occurred. ETCE0 = endpoint 0 ... ETCE3 = endpoint 3" />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1C0" size="4" name="ENDPTCTRL0" access="Read/Write" description="Endpoint control 0" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="RXT" description="Endpoint type Endpoint 0 is always a control endpoint." />
+      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
+      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_" start="0" description="Endpoint ok." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1]" />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="TXT" description="Endpoint type Endpoint 0 is always a control endpoint." />
+      <BitField start="20" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1C4+0" size="4" name="ENDPTCTRL1" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="RXT" description="Endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="ENABLED" start="0" description="Enabled" />
+        <Enum name="DISABLED" start="1" description="Disabled" />
+      </BitField>
+      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1C4+4" size="4" name="ENDPTCTRL2" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="RXT" description="Endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="ENABLED" start="0" description="Enabled" />
+        <Enum name="DISABLED" start="1" description="Disabled" />
+      </BitField>
+      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1C4+8" size="4" name="ENDPTCTRL3" access="Read/Write" description="Endpoint control " reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXS" description="Rx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="RXT" description="Endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="RXI" description="Rx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="6" size="1" name="RXR" description="Rx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="7" size="1" name="RXE" description="Rx endpoint enable An endpoint should be enabled only after it has been configured.">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="TXS" description="Tx endpoint stall">
+        <Enum name="ENDPOINT_OK_THIS_BI" start="0" description="Endpoint ok. This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint, and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared." />
+        <Enum name="ENDPOINT_STALLED_SOF" start="1" description="Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request.[1]" />
+      </BitField>
+      <BitField start="17" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="TXT" description="Tx endpoint type">
+        <Enum name="CONTROL" start="0x0" description="Control" />
+        <Enum name="ISOCHRONOUS" start="0x1" description="Isochronous" />
+        <Enum name="BULK" start="0x2" description="Bulk" />
+        <Enum name="INTERRUPT" start="0x3" description="Interrupt" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="21" size="1" name="TXI" description="Tx data toggle inhibit This bit is only used for test and should always be written as zero. Writing a one to this bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.">
+        <Enum name="ENABLED" start="0" description="Enabled" />
+        <Enum name="DISABLED" start="1" description="Disabled" />
+      </BitField>
+      <BitField start="22" size="1" name="TXR" description="Tx data toggle reset Write 1 to reset the PID sequence. Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PIDs between the host and device." />
+      <BitField start="23" size="1" name="TXE" description="Tx endpoint enable An endpoint should be enabled only after it has been configured">
+        <Enum name="ENDPOINT_DISABLED_" start="0" description="Endpoint disabled." />
+        <Enum name="ENDPOINT_ENABLED_" start="1" description="Endpoint enabled." />
+      </BitField>
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LCD" start="0x40008000" description="LCD controller ">
+    <Register start="+0x000" size="4" name="TIMH" access="Read/Write" description="Horizontal Timing Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="6" name="PPL" description="Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen. PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the number of pixel clocks that occur before the HFP is applied. Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19." />
+      <BitField start="8" size="8" name="HSW" description="Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. Program with desired value minus 1." />
+      <BitField start="16" size="8" name="HFP" description="Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with desired value minus 1." />
+      <BitField start="24" size="8" name="HBP" description="Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with desired value minus 1." />
+    </Register>
+    <Register start="+0x004" size="4" name="TIMV" access="Read/Write" description="Vertical Timing Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="LPP" description="Lines per panel. This is the number of active lines per screen. The LPP field specifies the total number of lines or rows on the LCD panel being controlled. LPP is a 10 bit value allowing between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1. For dual panel displays, program the register with the number of lines on each of the upper and lower panels." />
+      <BitField start="10" size="6" name="VSW" description="Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The 6 bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the register with the number of lines required, minus one. The number of horizontal synchronization lines must be small (for example, program to zero) for passive STN LCDs. The higher the value the worse the contrast on STN LCDs." />
+      <BitField start="16" size="8" name="VFP" description="Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8 bit VFP field specifies the number of line clocks to insert at the end of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of line clock periods to wait. After the count has elapsed, the vertical synchronization signal, LCDFP, is asserted in active mode, or extra line clocks are inserted as specified by the VSW bit field in passive mode. VFP generates 0-255 line clock cycles. Program to zero on passive displays for improved contrast." />
+      <BitField start="24" size="8" name="VBP" description="Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical synchronization period. The 8 bit VBP field specifies the number of line clocks inserted at the beginning of each frame. The VBP count starts immediately after the vertical synchronization signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count value in VBP sets the number of line clock periods inserted before the next frame. VBP generates 0-255 extra line clock cycles. Program to zero on passive displays for improved contrast." />
+    </Register>
+    <Register start="+0x008" size="4" name="POL" access="Read/Write" description="Clock and Signal Polarity Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="PCD_LO" description="Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this register) and PCD_LO, is used to derive the LCD panel clock frequency LCDDCLK from the input clock, LCDDCLK = LCDCLK/(PCD+2). For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are output per LCDDCLK cycle, so the panel clock is 0.375 times the pixel rate. For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register. Note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in STN modes: Single panel color mode, PCD = 1 (LCDDCLK = LCDCLK/3). Dual panel color mode, PCD = 4 (LCDDCLK = LCDCLK/6). Single panel monochrome 4-bit interface mode, PCD = 2(LCDDCLK = LCDCLK/4). Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, PCD = 6(LCDDCLK = LCDCLK/8). Dual panel monochrome 8-bit interface mode, PCD = 14(LCDDCLK = LCDCLK/16)." />
+      <BitField start="5" size="1" name="CLKSEL" description="Clock Select. This bit controls the selection of the source for LCDCLK. 0 = the clock source for the LCD block is CCLK. 1 = the clock source for the LCD block is LCDCLKIN (external clock input for the LVD)." />
+      <BitField start="6" size="5" name="ACB" description="AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation. Program this field with the required value minus one to apply the number of line clocks between each toggle of the AC bias pin, LCDENAB. This field has no effect if the LCD is operating in TFT mode, when the LCDENAB pin is used as a data enable signal." />
+      <BitField start="11" size="1" name="IVS" description="Invert vertical synchronization. The IVS bit inverts the polarity of the LCDFP signal. 0 = LCDFP pin is active HIGH and inactive LOW. 1 = LCDFP pin is active LOW and inactive HIGH." />
+      <BitField start="12" size="1" name="IHS" description="Invert horizontal synchronization. The IHS bit inverts the polarity of the LCDLP signal. 0 = LCDLP pin is active HIGH and inactive LOW. 1 = LCDLP pin is active LOW and inactive HIGH." />
+      <BitField start="13" size="1" name="IPC" description="Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven out onto the LCD data lines. 0 = Data is driven on the LCD data lines on the rising edge of LCDDCLK. 1 = Data is driven on the LCD data lines on the falling edge of LCDDCLK." />
+      <BitField start="14" size="1" name="IOE" description="Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode. In this mode, the LCDENAB pin is used as an enable that indicates to the LCD panel when valid display data is available. In active display mode, data is driven onto the LCD data lines at the programmed edge of LCDDCLK when LCDENAB is in its active state. 0 = LCDENAB output pin is active HIGH in TFT mode. 1 = LCDENAB output pin is active LOW in TFT mode." />
+      <BitField start="15" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="10" name="CPL" description="Clocks per line. This field specifies the number of actual LCDDCLK clocks to the LCD panel on each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to the PPL bit in the TIMH register for the LCD display to work correctly." />
+      <BitField start="26" size="1" name="BCD" description="Bypass pixel clock divider. Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays." />
+      <BitField start="27" size="5" name="PCD_HI" description="Upper five bits of panel clock divisor. See description for PCD_LO, in bits [4:0] of this register." />
+    </Register>
+    <Register start="+0x00C" size="4" name="LE" access="Read/Write" description="Line End Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="LED" description="Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock, LCDDCLK. Program with number of LCDCLK clock periods minus 1." />
+      <BitField start="7" size="9" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="1" name="LEE" description="LCD Line end enable. 0 = LCDLE disabled (held LOW). 1 = LCDLE signal active." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="UPBASE" access="Read/Write" description="Upper Panel Frame Base Address register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="29" name="LCDUPBASE" description="LCD upper panel base address. This is the start address of the upper panel frame data in memory and is doubleword aligned." />
+    </Register>
+    <Register start="+0x014" size="4" name="LPBASE" access="Read/Write" description="Lower Panel Frame Base Address register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="29" name="LCDLPBASE" description="LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned." />
+    </Register>
+    <Register start="+0x018" size="4" name="CTRL" access="Read/Write" description="LCD Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LCDEN" description="LCD enable control bit. 0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are low. 1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP, LCDENAB, and LCDLE are high. See LCD power-up and power-down sequence for details on LCD power sequencing." />
+      <BitField start="1" size="3" name="LCDBPP" description="LCD bits per pixel: Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode." />
+      <BitField start="4" size="1" name="LCDBW" description="STN LCD monochrome/color selection. 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode." />
+      <BitField start="5" size="1" name="LCDTFT" description="LCD panel TFT type selection. 0 = LCD is an STN display. Use gray scaler. 1 = LCD is a TFT display. Do not use gray scaler." />
+      <BitField start="6" size="1" name="LCDMONO8" description="Monochrome LCD interface width. This bit controls whether a monochrome STN LCD uses a 4 or 8-bit parallel interface. It has no meaning in other modes and must be programmed to zero. 0 = monochrome LCD uses a 4-bit interface. 1 = monochrome LCD uses a 8-bit interface." />
+      <BitField start="7" size="1" name="LCDDUAL" description="Single or Dual LCD panel selection. STN LCD interface is: 0 = single-panel. 1 = dual-panel." />
+      <BitField start="8" size="1" name="BGR" description="Color format selection. 0 = RGB: normal output. 1 = BGR: red and blue swapped." />
+      <BitField start="9" size="1" name="BEBO" description="Big-endian Byte Order. Controls byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order." />
+      <BitField start="10" size="1" name="BEPO" description="Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats.  See Pixel serializer for more information on the data format." />
+      <BitField start="11" size="1" name="LCDPWR" description="LCD power enable. 0 = power not gated through to LCD panel and LCDV[23:0] signals disabled, (held LOW). 1 = power gated through to LCD panel and LCDV[23:0] signals enabled, (active).  See LCD power-up and power-down sequence for details on LCD power sequencing." />
+      <BitField start="12" size="2" name="LCDVCOMP" description="LCD Vertical Compare Interrupt. Generate VComp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch." />
+      <BitField start="14" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="1" name="WATERMARK" description="LCD DMA FIFO watermark level. Controls when DMA requests are generated: 0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more empty locations. 1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more empty locations." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="INTMSK" access="Read/Write" description="Interrupt Mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="1" size="1" name="FUFIM" description="FIFO underflow interrupt enable. 0: The FIFO underflow interrupt is disabled. 1: Interrupt will be generated when the FIFO underflows." />
+      <BitField start="2" size="1" name="LNBUIM" description="LCD next base address update interrupt enable. 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers." />
+      <BitField start="3" size="1" name="VCOMPIM" description="Vertical compare interrupt enable. 0: The vertical compare time interrupt is disabled. 1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp field in the CTRL register) is reached." />
+      <BitField start="4" size="1" name="BERIM" description="AHB master error interrupt enable. 0: The AHB Master error interrupt is disabled. 1: Interrupt will be generated when an AHB Master error occurs." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="INTRAW" access="ReadOnly" description="Raw Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="1" size="1" name="FUFRIS" description="FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have been read accessed when empty causing an underflow condition to occur. Generates an interrupt if the FUFIM bit in the INTMSK register is set." />
+      <BitField start="2" size="1" name="LNBURIS" description="LCD next address base update raw interrupt status. Mode dependent. Set when the current base address registers have been successfully updated by the next address registers. Signifies that a new next address can be loaded if double buffering is in use. Generates an interrupt if the LNBUIM bit in the INTMSK register is set." />
+      <BitField start="3" size="1" name="VCOMPRIS" description="Vertical compare raw interrupt status. Set when one of the four vertical regions is reached, as selected by the LcdVComp bits in the CTRL register. Generates an interrupt if the VCompIM bit in the INTMSK register is set." />
+      <BitField start="4" size="1" name="BERRAW" description="AHB master bus error raw interrupt status. Set when the AHB master interface receives a bus error response from a slave. Generates an interrupt if the BERIM bit in the INTMSK register is set." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="INTSTAT" access="ReadOnly" description="Masked Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="1" size="1" name="FUFMIS" description="FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the INTRAW register and the FUFIM bit in the INTMSK register are set." />
+      <BitField start="2" size="1" name="LNBUMIS" description="LCD next address base update masked interrupt status. Set when the both the LNBURIS bit in the INTRAW register and the LNBUIM bit in the INTMSK register are set." />
+      <BitField start="3" size="1" name="VCOMPMIS" description="Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the INTRAW register and the VCompIM bit in the INTMSK register are set." />
+      <BitField start="4" size="1" name="BERMIS" description="AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the INTRAW register and the BERIM bit in the INTMSK register are set." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="INTCLR" access="WriteOnly" description="Interrupt Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="1" size="1" name="FUFIC" description="FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt." />
+      <BitField start="2" size="1" name="LNBUIC" description="LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address base update interrupt." />
+      <BitField start="3" size="1" name="VCOMPIC" description="Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt." />
+      <BitField start="4" size="1" name="BERIC" description="AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="UPCURR" access="ReadOnly" description="Upper Panel Current Address Value register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="LCDUPCURR" description="LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA address." />
+    </Register>
+    <Register start="+0x030" size="4" name="LPCURR" access="ReadOnly" description="Lower Panel Current Address Value register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="LCDLPCURR" description="LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA address." />
+    </Register>
+    <Register start="+0x200+0" size="4" name="PAL[0]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+4" size="4" name="PAL[1]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+8" size="4" name="PAL[2]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+12" size="4" name="PAL[3]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+16" size="4" name="PAL[4]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+20" size="4" name="PAL[5]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+24" size="4" name="PAL[6]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+28" size="4" name="PAL[7]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+32" size="4" name="PAL[8]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+36" size="4" name="PAL[9]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+40" size="4" name="PAL[10]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+44" size="4" name="PAL[11]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+48" size="4" name="PAL[12]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+52" size="4" name="PAL[13]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+56" size="4" name="PAL[14]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+60" size="4" name="PAL[15]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+64" size="4" name="PAL[16]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+68" size="4" name="PAL[17]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+72" size="4" name="PAL[18]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+76" size="4" name="PAL[19]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+80" size="4" name="PAL[20]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+84" size="4" name="PAL[21]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+88" size="4" name="PAL[22]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+92" size="4" name="PAL[23]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+96" size="4" name="PAL[24]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+100" size="4" name="PAL[25]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+104" size="4" name="PAL[26]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+108" size="4" name="PAL[27]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+112" size="4" name="PAL[28]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+116" size="4" name="PAL[29]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+120" size="4" name="PAL[30]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+124" size="4" name="PAL[31]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+128" size="4" name="PAL[32]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+132" size="4" name="PAL[33]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+136" size="4" name="PAL[34]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+140" size="4" name="PAL[35]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+144" size="4" name="PAL[36]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+148" size="4" name="PAL[37]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+152" size="4" name="PAL[38]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+156" size="4" name="PAL[39]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+160" size="4" name="PAL[40]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+164" size="4" name="PAL[41]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+168" size="4" name="PAL[42]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+172" size="4" name="PAL[43]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+176" size="4" name="PAL[44]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+180" size="4" name="PAL[45]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+184" size="4" name="PAL[46]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+188" size="4" name="PAL[47]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+192" size="4" name="PAL[48]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+196" size="4" name="PAL[49]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+200" size="4" name="PAL[50]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+204" size="4" name="PAL[51]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+208" size="4" name="PAL[52]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+212" size="4" name="PAL[53]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+216" size="4" name="PAL[54]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+220" size="4" name="PAL[55]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+224" size="4" name="PAL[56]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+228" size="4" name="PAL[57]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+232" size="4" name="PAL[58]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+236" size="4" name="PAL[59]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+240" size="4" name="PAL[60]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+244" size="4" name="PAL[61]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+248" size="4" name="PAL[62]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+252" size="4" name="PAL[63]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+256" size="4" name="PAL[64]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+260" size="4" name="PAL[65]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+264" size="4" name="PAL[66]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+268" size="4" name="PAL[67]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+272" size="4" name="PAL[68]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+276" size="4" name="PAL[69]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+280" size="4" name="PAL[70]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+284" size="4" name="PAL[71]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+288" size="4" name="PAL[72]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+292" size="4" name="PAL[73]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+296" size="4" name="PAL[74]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+300" size="4" name="PAL[75]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+304" size="4" name="PAL[76]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+308" size="4" name="PAL[77]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+312" size="4" name="PAL[78]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+316" size="4" name="PAL[79]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+320" size="4" name="PAL[80]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+324" size="4" name="PAL[81]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+328" size="4" name="PAL[82]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+332" size="4" name="PAL[83]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+336" size="4" name="PAL[84]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+340" size="4" name="PAL[85]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+344" size="4" name="PAL[86]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+348" size="4" name="PAL[87]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+352" size="4" name="PAL[88]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+356" size="4" name="PAL[89]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+360" size="4" name="PAL[90]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+364" size="4" name="PAL[91]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+368" size="4" name="PAL[92]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+372" size="4" name="PAL[93]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+376" size="4" name="PAL[94]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+380" size="4" name="PAL[95]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+384" size="4" name="PAL[96]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+388" size="4" name="PAL[97]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+392" size="4" name="PAL[98]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+396" size="4" name="PAL[99]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+400" size="4" name="PAL[100]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+404" size="4" name="PAL[101]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+408" size="4" name="PAL[102]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+412" size="4" name="PAL[103]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+416" size="4" name="PAL[104]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+420" size="4" name="PAL[105]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+424" size="4" name="PAL[106]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+428" size="4" name="PAL[107]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+432" size="4" name="PAL[108]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+436" size="4" name="PAL[109]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+440" size="4" name="PAL[110]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+444" size="4" name="PAL[111]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+448" size="4" name="PAL[112]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+452" size="4" name="PAL[113]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+456" size="4" name="PAL[114]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+460" size="4" name="PAL[115]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+464" size="4" name="PAL[116]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+468" size="4" name="PAL[117]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+472" size="4" name="PAL[118]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+476" size="4" name="PAL[119]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+480" size="4" name="PAL[120]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+484" size="4" name="PAL[121]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+488" size="4" name="PAL[122]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+492" size="4" name="PAL[123]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+496" size="4" name="PAL[124]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+500" size="4" name="PAL[125]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+504" size="4" name="PAL[126]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+508" size="4" name="PAL[127]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+512" size="4" name="PAL[128]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+516" size="4" name="PAL[129]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+520" size="4" name="PAL[130]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+524" size="4" name="PAL[131]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+528" size="4" name="PAL[132]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+532" size="4" name="PAL[133]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+536" size="4" name="PAL[134]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+540" size="4" name="PAL[135]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+544" size="4" name="PAL[136]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+548" size="4" name="PAL[137]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+552" size="4" name="PAL[138]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+556" size="4" name="PAL[139]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+560" size="4" name="PAL[140]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+564" size="4" name="PAL[141]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+568" size="4" name="PAL[142]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+572" size="4" name="PAL[143]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+576" size="4" name="PAL[144]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+580" size="4" name="PAL[145]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+584" size="4" name="PAL[146]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+588" size="4" name="PAL[147]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+592" size="4" name="PAL[148]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+596" size="4" name="PAL[149]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+600" size="4" name="PAL[150]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+604" size="4" name="PAL[151]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+608" size="4" name="PAL[152]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+612" size="4" name="PAL[153]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+616" size="4" name="PAL[154]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+620" size="4" name="PAL[155]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+624" size="4" name="PAL[156]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+628" size="4" name="PAL[157]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+632" size="4" name="PAL[158]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+636" size="4" name="PAL[159]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+640" size="4" name="PAL[160]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+644" size="4" name="PAL[161]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+648" size="4" name="PAL[162]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+652" size="4" name="PAL[163]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+656" size="4" name="PAL[164]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+660" size="4" name="PAL[165]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+664" size="4" name="PAL[166]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+668" size="4" name="PAL[167]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+672" size="4" name="PAL[168]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+676" size="4" name="PAL[169]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+680" size="4" name="PAL[170]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+684" size="4" name="PAL[171]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+688" size="4" name="PAL[172]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+692" size="4" name="PAL[173]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+696" size="4" name="PAL[174]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+700" size="4" name="PAL[175]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+704" size="4" name="PAL[176]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+708" size="4" name="PAL[177]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+712" size="4" name="PAL[178]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+716" size="4" name="PAL[179]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+720" size="4" name="PAL[180]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+724" size="4" name="PAL[181]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+728" size="4" name="PAL[182]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+732" size="4" name="PAL[183]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+736" size="4" name="PAL[184]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+740" size="4" name="PAL[185]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+744" size="4" name="PAL[186]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+748" size="4" name="PAL[187]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+752" size="4" name="PAL[188]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+756" size="4" name="PAL[189]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+760" size="4" name="PAL[190]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+764" size="4" name="PAL[191]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+768" size="4" name="PAL[192]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+772" size="4" name="PAL[193]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+776" size="4" name="PAL[194]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+780" size="4" name="PAL[195]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+784" size="4" name="PAL[196]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+788" size="4" name="PAL[197]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+792" size="4" name="PAL[198]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+796" size="4" name="PAL[199]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+800" size="4" name="PAL[200]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+804" size="4" name="PAL[201]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+808" size="4" name="PAL[202]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+812" size="4" name="PAL[203]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+816" size="4" name="PAL[204]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+820" size="4" name="PAL[205]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+824" size="4" name="PAL[206]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+828" size="4" name="PAL[207]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+832" size="4" name="PAL[208]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+836" size="4" name="PAL[209]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+840" size="4" name="PAL[210]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+844" size="4" name="PAL[211]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+848" size="4" name="PAL[212]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+852" size="4" name="PAL[213]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+856" size="4" name="PAL[214]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+860" size="4" name="PAL[215]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+864" size="4" name="PAL[216]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+868" size="4" name="PAL[217]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+872" size="4" name="PAL[218]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+876" size="4" name="PAL[219]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+880" size="4" name="PAL[220]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+884" size="4" name="PAL[221]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+888" size="4" name="PAL[222]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+892" size="4" name="PAL[223]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+896" size="4" name="PAL[224]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+900" size="4" name="PAL[225]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+904" size="4" name="PAL[226]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+908" size="4" name="PAL[227]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+912" size="4" name="PAL[228]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+916" size="4" name="PAL[229]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+920" size="4" name="PAL[230]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+924" size="4" name="PAL[231]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+928" size="4" name="PAL[232]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+932" size="4" name="PAL[233]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+936" size="4" name="PAL[234]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+940" size="4" name="PAL[235]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+944" size="4" name="PAL[236]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+948" size="4" name="PAL[237]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+952" size="4" name="PAL[238]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+956" size="4" name="PAL[239]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+960" size="4" name="PAL[240]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+964" size="4" name="PAL[241]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+968" size="4" name="PAL[242]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+972" size="4" name="PAL[243]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+976" size="4" name="PAL[244]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+980" size="4" name="PAL[245]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+984" size="4" name="PAL[246]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+988" size="4" name="PAL[247]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+992" size="4" name="PAL[248]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+996" size="4" name="PAL[249]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+1000" size="4" name="PAL[250]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+1004" size="4" name="PAL[251]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+1008" size="4" name="PAL[252]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+1012" size="4" name="PAL[253]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+1016" size="4" name="PAL[254]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x200+1020" size="4" name="PAL[255]" access="Read/Write" description="256x16-bit Color Palette registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="R04_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="5" size="5" name="G04_0" description="Green palette data." />
+      <BitField start="10" size="5" name="B04_0" description="Blue palette data." />
+      <BitField start="15" size="1" name="I0" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+      <BitField start="16" size="5" name="R14_0" description="Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome displays only the red palette data is used. All of the palette registers have the same bit fields." />
+      <BitField start="21" size="5" name="G14_0" description="Green palette data." />
+      <BitField start="26" size="5" name="B14_0" description="Blue palette data." />
+      <BitField start="31" size="1" name="I1" description="Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities." />
+    </Register>
+    <Register start="+0x800+0" size="4" name="CRSR_IMG[0]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+4" size="4" name="CRSR_IMG[1]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+8" size="4" name="CRSR_IMG[2]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+12" size="4" name="CRSR_IMG[3]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+16" size="4" name="CRSR_IMG[4]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+20" size="4" name="CRSR_IMG[5]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+24" size="4" name="CRSR_IMG[6]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+28" size="4" name="CRSR_IMG[7]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+32" size="4" name="CRSR_IMG[8]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+36" size="4" name="CRSR_IMG[9]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+40" size="4" name="CRSR_IMG[10]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+44" size="4" name="CRSR_IMG[11]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+48" size="4" name="CRSR_IMG[12]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+52" size="4" name="CRSR_IMG[13]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+56" size="4" name="CRSR_IMG[14]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+60" size="4" name="CRSR_IMG[15]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+64" size="4" name="CRSR_IMG[16]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+68" size="4" name="CRSR_IMG[17]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+72" size="4" name="CRSR_IMG[18]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+76" size="4" name="CRSR_IMG[19]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+80" size="4" name="CRSR_IMG[20]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+84" size="4" name="CRSR_IMG[21]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+88" size="4" name="CRSR_IMG[22]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+92" size="4" name="CRSR_IMG[23]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+96" size="4" name="CRSR_IMG[24]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+100" size="4" name="CRSR_IMG[25]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+104" size="4" name="CRSR_IMG[26]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+108" size="4" name="CRSR_IMG[27]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+112" size="4" name="CRSR_IMG[28]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+116" size="4" name="CRSR_IMG[29]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+120" size="4" name="CRSR_IMG[30]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+124" size="4" name="CRSR_IMG[31]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+128" size="4" name="CRSR_IMG[32]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+132" size="4" name="CRSR_IMG[33]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+136" size="4" name="CRSR_IMG[34]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+140" size="4" name="CRSR_IMG[35]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+144" size="4" name="CRSR_IMG[36]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+148" size="4" name="CRSR_IMG[37]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+152" size="4" name="CRSR_IMG[38]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+156" size="4" name="CRSR_IMG[39]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+160" size="4" name="CRSR_IMG[40]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+164" size="4" name="CRSR_IMG[41]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+168" size="4" name="CRSR_IMG[42]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+172" size="4" name="CRSR_IMG[43]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+176" size="4" name="CRSR_IMG[44]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+180" size="4" name="CRSR_IMG[45]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+184" size="4" name="CRSR_IMG[46]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+188" size="4" name="CRSR_IMG[47]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+192" size="4" name="CRSR_IMG[48]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+196" size="4" name="CRSR_IMG[49]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+200" size="4" name="CRSR_IMG[50]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+204" size="4" name="CRSR_IMG[51]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+208" size="4" name="CRSR_IMG[52]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+212" size="4" name="CRSR_IMG[53]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+216" size="4" name="CRSR_IMG[54]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+220" size="4" name="CRSR_IMG[55]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+224" size="4" name="CRSR_IMG[56]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+228" size="4" name="CRSR_IMG[57]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+232" size="4" name="CRSR_IMG[58]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+236" size="4" name="CRSR_IMG[59]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+240" size="4" name="CRSR_IMG[60]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+244" size="4" name="CRSR_IMG[61]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+248" size="4" name="CRSR_IMG[62]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+252" size="4" name="CRSR_IMG[63]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+256" size="4" name="CRSR_IMG[64]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+260" size="4" name="CRSR_IMG[65]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+264" size="4" name="CRSR_IMG[66]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+268" size="4" name="CRSR_IMG[67]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+272" size="4" name="CRSR_IMG[68]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+276" size="4" name="CRSR_IMG[69]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+280" size="4" name="CRSR_IMG[70]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+284" size="4" name="CRSR_IMG[71]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+288" size="4" name="CRSR_IMG[72]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+292" size="4" name="CRSR_IMG[73]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+296" size="4" name="CRSR_IMG[74]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+300" size="4" name="CRSR_IMG[75]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+304" size="4" name="CRSR_IMG[76]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+308" size="4" name="CRSR_IMG[77]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+312" size="4" name="CRSR_IMG[78]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+316" size="4" name="CRSR_IMG[79]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+320" size="4" name="CRSR_IMG[80]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+324" size="4" name="CRSR_IMG[81]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+328" size="4" name="CRSR_IMG[82]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+332" size="4" name="CRSR_IMG[83]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+336" size="4" name="CRSR_IMG[84]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+340" size="4" name="CRSR_IMG[85]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+344" size="4" name="CRSR_IMG[86]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+348" size="4" name="CRSR_IMG[87]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+352" size="4" name="CRSR_IMG[88]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+356" size="4" name="CRSR_IMG[89]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+360" size="4" name="CRSR_IMG[90]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+364" size="4" name="CRSR_IMG[91]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+368" size="4" name="CRSR_IMG[92]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+372" size="4" name="CRSR_IMG[93]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+376" size="4" name="CRSR_IMG[94]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+380" size="4" name="CRSR_IMG[95]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+384" size="4" name="CRSR_IMG[96]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+388" size="4" name="CRSR_IMG[97]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+392" size="4" name="CRSR_IMG[98]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+396" size="4" name="CRSR_IMG[99]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+400" size="4" name="CRSR_IMG[100]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+404" size="4" name="CRSR_IMG[101]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+408" size="4" name="CRSR_IMG[102]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+412" size="4" name="CRSR_IMG[103]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+416" size="4" name="CRSR_IMG[104]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+420" size="4" name="CRSR_IMG[105]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+424" size="4" name="CRSR_IMG[106]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+428" size="4" name="CRSR_IMG[107]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+432" size="4" name="CRSR_IMG[108]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+436" size="4" name="CRSR_IMG[109]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+440" size="4" name="CRSR_IMG[110]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+444" size="4" name="CRSR_IMG[111]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+448" size="4" name="CRSR_IMG[112]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+452" size="4" name="CRSR_IMG[113]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+456" size="4" name="CRSR_IMG[114]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+460" size="4" name="CRSR_IMG[115]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+464" size="4" name="CRSR_IMG[116]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+468" size="4" name="CRSR_IMG[117]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+472" size="4" name="CRSR_IMG[118]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+476" size="4" name="CRSR_IMG[119]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+480" size="4" name="CRSR_IMG[120]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+484" size="4" name="CRSR_IMG[121]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+488" size="4" name="CRSR_IMG[122]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+492" size="4" name="CRSR_IMG[123]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+496" size="4" name="CRSR_IMG[124]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+500" size="4" name="CRSR_IMG[125]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+504" size="4" name="CRSR_IMG[126]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+508" size="4" name="CRSR_IMG[127]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+512" size="4" name="CRSR_IMG[128]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+516" size="4" name="CRSR_IMG[129]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+520" size="4" name="CRSR_IMG[130]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+524" size="4" name="CRSR_IMG[131]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+528" size="4" name="CRSR_IMG[132]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+532" size="4" name="CRSR_IMG[133]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+536" size="4" name="CRSR_IMG[134]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+540" size="4" name="CRSR_IMG[135]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+544" size="4" name="CRSR_IMG[136]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+548" size="4" name="CRSR_IMG[137]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+552" size="4" name="CRSR_IMG[138]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+556" size="4" name="CRSR_IMG[139]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+560" size="4" name="CRSR_IMG[140]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+564" size="4" name="CRSR_IMG[141]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+568" size="4" name="CRSR_IMG[142]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+572" size="4" name="CRSR_IMG[143]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+576" size="4" name="CRSR_IMG[144]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+580" size="4" name="CRSR_IMG[145]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+584" size="4" name="CRSR_IMG[146]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+588" size="4" name="CRSR_IMG[147]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+592" size="4" name="CRSR_IMG[148]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+596" size="4" name="CRSR_IMG[149]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+600" size="4" name="CRSR_IMG[150]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+604" size="4" name="CRSR_IMG[151]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+608" size="4" name="CRSR_IMG[152]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+612" size="4" name="CRSR_IMG[153]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+616" size="4" name="CRSR_IMG[154]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+620" size="4" name="CRSR_IMG[155]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+624" size="4" name="CRSR_IMG[156]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+628" size="4" name="CRSR_IMG[157]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+632" size="4" name="CRSR_IMG[158]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+636" size="4" name="CRSR_IMG[159]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+640" size="4" name="CRSR_IMG[160]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+644" size="4" name="CRSR_IMG[161]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+648" size="4" name="CRSR_IMG[162]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+652" size="4" name="CRSR_IMG[163]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+656" size="4" name="CRSR_IMG[164]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+660" size="4" name="CRSR_IMG[165]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+664" size="4" name="CRSR_IMG[166]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+668" size="4" name="CRSR_IMG[167]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+672" size="4" name="CRSR_IMG[168]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+676" size="4" name="CRSR_IMG[169]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+680" size="4" name="CRSR_IMG[170]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+684" size="4" name="CRSR_IMG[171]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+688" size="4" name="CRSR_IMG[172]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+692" size="4" name="CRSR_IMG[173]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+696" size="4" name="CRSR_IMG[174]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+700" size="4" name="CRSR_IMG[175]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+704" size="4" name="CRSR_IMG[176]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+708" size="4" name="CRSR_IMG[177]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+712" size="4" name="CRSR_IMG[178]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+716" size="4" name="CRSR_IMG[179]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+720" size="4" name="CRSR_IMG[180]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+724" size="4" name="CRSR_IMG[181]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+728" size="4" name="CRSR_IMG[182]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+732" size="4" name="CRSR_IMG[183]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+736" size="4" name="CRSR_IMG[184]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+740" size="4" name="CRSR_IMG[185]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+744" size="4" name="CRSR_IMG[186]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+748" size="4" name="CRSR_IMG[187]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+752" size="4" name="CRSR_IMG[188]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+756" size="4" name="CRSR_IMG[189]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+760" size="4" name="CRSR_IMG[190]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+764" size="4" name="CRSR_IMG[191]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+768" size="4" name="CRSR_IMG[192]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+772" size="4" name="CRSR_IMG[193]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+776" size="4" name="CRSR_IMG[194]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+780" size="4" name="CRSR_IMG[195]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+784" size="4" name="CRSR_IMG[196]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+788" size="4" name="CRSR_IMG[197]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+792" size="4" name="CRSR_IMG[198]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+796" size="4" name="CRSR_IMG[199]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+800" size="4" name="CRSR_IMG[200]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+804" size="4" name="CRSR_IMG[201]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+808" size="4" name="CRSR_IMG[202]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+812" size="4" name="CRSR_IMG[203]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+816" size="4" name="CRSR_IMG[204]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+820" size="4" name="CRSR_IMG[205]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+824" size="4" name="CRSR_IMG[206]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+828" size="4" name="CRSR_IMG[207]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+832" size="4" name="CRSR_IMG[208]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+836" size="4" name="CRSR_IMG[209]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+840" size="4" name="CRSR_IMG[210]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+844" size="4" name="CRSR_IMG[211]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+848" size="4" name="CRSR_IMG[212]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+852" size="4" name="CRSR_IMG[213]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+856" size="4" name="CRSR_IMG[214]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+860" size="4" name="CRSR_IMG[215]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+864" size="4" name="CRSR_IMG[216]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+868" size="4" name="CRSR_IMG[217]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+872" size="4" name="CRSR_IMG[218]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+876" size="4" name="CRSR_IMG[219]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+880" size="4" name="CRSR_IMG[220]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+884" size="4" name="CRSR_IMG[221]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+888" size="4" name="CRSR_IMG[222]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+892" size="4" name="CRSR_IMG[223]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+896" size="4" name="CRSR_IMG[224]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+900" size="4" name="CRSR_IMG[225]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+904" size="4" name="CRSR_IMG[226]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+908" size="4" name="CRSR_IMG[227]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+912" size="4" name="CRSR_IMG[228]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+916" size="4" name="CRSR_IMG[229]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+920" size="4" name="CRSR_IMG[230]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+924" size="4" name="CRSR_IMG[231]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+928" size="4" name="CRSR_IMG[232]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+932" size="4" name="CRSR_IMG[233]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+936" size="4" name="CRSR_IMG[234]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+940" size="4" name="CRSR_IMG[235]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+944" size="4" name="CRSR_IMG[236]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+948" size="4" name="CRSR_IMG[237]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+952" size="4" name="CRSR_IMG[238]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+956" size="4" name="CRSR_IMG[239]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+960" size="4" name="CRSR_IMG[240]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+964" size="4" name="CRSR_IMG[241]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+968" size="4" name="CRSR_IMG[242]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+972" size="4" name="CRSR_IMG[243]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+976" size="4" name="CRSR_IMG[244]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+980" size="4" name="CRSR_IMG[245]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+984" size="4" name="CRSR_IMG[246]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+988" size="4" name="CRSR_IMG[247]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+992" size="4" name="CRSR_IMG[248]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+996" size="4" name="CRSR_IMG[249]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+1000" size="4" name="CRSR_IMG[250]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+1004" size="4" name="CRSR_IMG[251]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+1008" size="4" name="CRSR_IMG[252]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+1012" size="4" name="CRSR_IMG[253]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+1016" size="4" name="CRSR_IMG[254]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0x800+1020" size="4" name="CRSR_IMG[255]" access="Read/Write" description="Cursor Image registers" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CRSR_IMG" description="Cursor Image data. The 256 words of the cursor image registers define the appearance of either one 64x64 cursor or 4 32x32 cursors." />
+    </Register>
+    <Register start="+0xC00" size="4" name="CRSR_CTRL" access="Read/Write" description="Cursor Control register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CrsrOn" description="Cursor enable. 0 = Cursor is not displayed. 1 = Cursor is displayed." />
+      <BitField start="1" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="4" size="2" name="CRSRNUM1_0" description="Cursor image number. If the selected cursor size is 6x64, this field has no effect. If the selected cursor size is 32x32: 00 = Cursor0. 01 = Cursor1. 10 = Cursor2. 11 = Cursor3." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC04" size="4" name="CRSR_CFG" access="Read/Write" description="Cursor Configuration register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CrsrSize" description="Cursor size selection. 0 = 32x32 pixel cursor. Allows for 4 defined cursors. 1 = 64x64 pixel cursor." />
+      <BitField start="1" size="1" name="FRAMESYNC" description="Cursor frame synchronization type. 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC08" size="4" name="CRSR_PAL0" access="Read/Write" description="Cursor Palette register 0" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="RED" description="Red color component" />
+      <BitField start="8" size="8" name="GREEN" description="Green color component" />
+      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC0C" size="4" name="CRSR_PAL1" access="Read/Write" description="Cursor Palette register 1" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="RED" description="Red color component" />
+      <BitField start="8" size="8" name="GREEN" description="Green color component" />
+      <BitField start="16" size="8" name="BLUE" description="Blue color component." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC10" size="4" name="CRSR_XY" access="Read/Write" description="Cursor XY Position register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="CRSRX" description="X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is at the left of the display." />
+      <BitField start="10" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="10" name="CRSRY" description="Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is at the top of the display." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC14" size="4" name="CRSR_CLIP" access="Read/Write" description="Cursor Clip Position register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="CRSRCLIPX" description="Cursor clip position for X direction. Distance from the left edge of the cursor image to the first displayed pixel in the cursor. When 0, the first pixel of the cursor line is displayed." />
+      <BitField start="6" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="6" name="CRSRCLIPY" description="Cursor clip position for Y direction. Distance from the top of the cursor image to the first displayed pixel in the cursor. When 0, the first displayed pixel is from the top line of the cursor image." />
+      <BitField start="14" size="18" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC20" size="4" name="CRSR_INTMSK" access="Read/Write" description="Cursor Interrupt Mask register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CRSRIM" description="Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set, the cursor interrupts the processor immediately after reading of the last word of cursor image." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC24" size="4" name="CRSR_INTCLR" access="WriteOnly" description="Cursor Interrupt Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CRSRIC" description="Cursor interrupt clear. Writing a 0 to this bit has no effect. Writing a 1 to this bit causes the cursor interrupt status to be cleared." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC28" size="4" name="CRSR_INTRAW" access="ReadOnly" description="Cursor Raw Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CRSRRIS" description="Cursor raw interrupt status. The cursor interrupt status is set immediately after the last data is read from the cursor image for the current frame. This bit is cleared by writing to the CrsrIC bit in the CRSR_INTCLR register." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xC2C" size="4" name="CRSR_INTSTAT" access="ReadOnly" description="Cursor Masked Interrupt Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CRSRMIS" description="Cursor masked interrupt status. The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the CRSR_INTMSK register is set. The bit remains clear if the CRSR_INTMSK register is clear. This bit is cleared by writing to the CRSR_INTCLR register." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="EEPROM" start="0x4000E000" description="EEPROM">
+    <Register start="+0x000" size="4" name="CMD" access="Read/Write" description="EEPROM command register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CMD" description="Command. Read data shows the last command executed on the EEPROM. 110 = erase/program page All other values are reserved." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x008" size="4" name="RWSTATE" access="Read/Write" description="EEPROM read wait state register" reset_value="0x00000905" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="RPHASE2" description="Wait states 2 (minus 1 encoded). The number of system clock periods to meet the read operations TRPHASE2 duration." />
+      <BitField start="8" size="8" name="RPHASE1" description="Wait states 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TRPHASE1." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x00C" size="4" name="AUTOPROG" access="Read/Write" description="EEPROM auto programming register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="AUTOPROG" description="Auto programming mode: 00 = auto programming off 01 = erase/program cycle is triggered after 1 word is written 10 = erase/program cycle is triggered after a write to AHB address ending with  ......1111100 (last word of a page)" />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x010" size="4" name="WSTATE" access="Read/Write" description="EEPROM wait state register" reset_value="0x00020602" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PHASE3" description="Wait states for phase 3 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE3." />
+      <BitField start="8" size="8" name="PHASE2" description="Wait states for phase 2 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE2." />
+      <BitField start="16" size="8" name="PHASE1" description="Wait states for phase 1 (minus 1 encoded). The number of system clock periods to meet a duration equal to TPHASE1." />
+      <BitField start="24" size="7" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="31" size="1" name="LCK_PARWEP" description="Lock timing parameters for write, erase and program operation  0 = WSTATE and CLKDIV registers have R/W access  1 = WSTATE and CLKDIV registers have R only access" />
+    </Register>
+    <Register start="+0x014" size="4" name="CLKDIV" access="Read/Write" description="EEPROM clock divider register" reset_value="0x00000063" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CLKDIV" description="Division factor (minus 1 encoded)." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0x018" size="4" name="PWRDWN" access="Read/Write" description="EEPROM power-down register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PWRDWN" description="Power down mode bit. 0 = not in power down mode. 1 = power down mode." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xFD8" size="4" name="INTENCLR" access="WriteOnly" description="EEPROM interrupt enable clear" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="2" size="1" name="PROG_CLR_EN" description="Clear program operation finished interrupt enable bit for EEPROM. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xFDC" size="4" name="INTENSET" access="WriteOnly" description="EEPROM interrupt enable set" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="2" size="1" name="PROG_SET_EN" description="Set program operation finished interrupt enable bit for EEPROM device 1. 0 = leave corresponding bit unchanged. 1 = set corresponding bit." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="EEPROM interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="END_OF_PROG" description="EEPROM program operation finished interrupt status bit. Bit is: - set when this operation has finished OR when one is written to the corresponding bit of the INTSTATSET register. - cleared when one is written to the corresponding bit of the INTSTATCLR register." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xFE4" size="4" name="INTEN" access="ReadOnly" description="EEPROM interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="EE_PROG_DONE" description="EEPROM program operation finished interrupt enable bit. Bit is: - set when one is written in the corresponding bit of the INTENSET register. - cleared when one is written to the corresponding bit of the INTENCLR register." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0xFE8" size="4" name="INTSTATCLR" access="WriteOnly" description="EEPROM interrupt status clear" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="2" size="1" name="PROG_CLR_ST" description="Clear program operation finished interrupt status bit for EEPROM device. 0 = leave corresponding bit unchanged. 1 = clear corresponding bit." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ETHERNET" start="0x40010000" description="Ethernet">
+    <Register start="+0x0000" size="4" name="MAC_CONFIG" access="Read/Write" description="MAC configuration register" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="1" name="RE" description="Receiver enable When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and will not receive any further frames from the MII." />
+      <BitField start="3" size="1" name="TE" description="Transmitter Enable  When this bit is set, the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and will not transmit any further frames." />
+      <BitField start="4" size="1" name="DF" description="Deferral Check  When this bit is set, the deferral check function is enabled in the MAC. The MAC will issue a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status when the transmit state machine is deferred for more than 24,288 bit times in 10/100-Mbps mode. If the Core is configured for 1000 Mbps operation, or if the Jumbo frame mode is enabled in 10/100-Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but is prevented because of an active CRS (carrier sense) signal on the MII. Defer time is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts.  When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration." />
+      <BitField start="5" size="2" name="BL" description="Back-Off Limit  The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only to Half-Duplex mode and is reserved (RO) in Full-Duplex-only configuration.  00: k = min (n, 10)  01: k = min (n, 8)  10: k = min (n, 4)  11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 &lt;= r  &lt;= 2k." />
+      <BitField start="7" size="1" name="ACS" description="Automatic Pad/CRC Stripping  When this bit is set, the MAC strips the Pad/FCS field on incoming frames only if the length's field value is less than or equal to 1,500 bytes. All received frames with length field greater than or equal to 1,501 bytes are passed to the application without stripping the Pad/FCS field.  When this bit is reset, the MAC will pass all incoming frames to the Host unmodified." />
+      <BitField start="8" size="1" name="RESERVED" description="Link Up/Down  Indicates whether the link is up or down during the transmission of configuration in SMII interface:  0 = Link down 1 = Link up" />
+      <BitField start="9" size="1" name="DR" description="Disable Retry  When this bit is set, the MAC will attempt only 1 transmission. When a collision occurs on the MII, the MAC will ignore the current frame transmission and report a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC will attempt retries based on the settings of BL. This bit is applicable only to Half-Duplex mode and is reserved (RO with default value) in Full- Duplex-only configuration." />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="DM" description="Duplex Mode  When this bit is set, the MAC operates in a Full-Duplex mode where it can transmit and receive simultaneously." />
+      <BitField start="12" size="1" name="LM" description="Loopback Mode  When this bit is set, the MAC operates in loopback mode at MII. The MII Receive clock input is required for the loopback to work properly, as the Transmit clock is not looped-back internally." />
+      <BitField start="13" size="1" name="DO" description="Disable Receive Own  When this bit is set, the MAC disables the reception of frames in Half-Duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting.  This bit is not applicable if the MAC is operating in Full-Duplex mode." />
+      <BitField start="14" size="1" name="FES" description="Speed Indicates the speed in Fast Ethernet (MII) mode:  0 = 10 Mbps 1 = 100 Mbps" />
+      <BitField start="15" size="1" name="PS" description="Port select   1 = MII (100 Mbp) - this is the only allowed value." />
+      <BitField start="16" size="1" name="DCRS" description="Disable carrier sense during transmission When set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in Half-Duplex mode. This request results in no errors generated due to Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors due to Carrier Sense and will even abort the transmissions." />
+      <BitField start="17" size="3" name="IFG" description="Inter-frame gap These bits control the minimum IFG between frames during transmission.  000 = 96 bit times 001 = 88 bit times 010 = 80 bit times ... 000 = 40 bit times Note that in Half-Duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100) only. Lower values are not considered" />
+      <BitField start="20" size="1" name="JE" description="Jumbo Frame Enable  When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status." />
+      <BitField start="21" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="22" size="1" name="JD" description="Jabber Disable  When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes.  When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission." />
+      <BitField start="23" size="1" name="WD" description="Watchdog Disable  When this bit is set, the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16,384 bytes.  When this bit is reset, the MAC allows no more than 2,048 bytes (10,240 if JE is set high) of the frame being received and cuts off any bytes received after that." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0004" size="4" name="MAC_FRAME_FILTER" access="Read/Write" description="MAC frame filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PR" description="Promiscuous Mode  When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. The SA/DA Filter Fails status bits of the Receive Status Word will always be cleared when PR is set." />
+      <BitField start="1" size="1" name="HUC" description="Hash Unicast When set, MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers." />
+      <BitField start="2" size="1" name="HMC" description="Hash Multicast When set, MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers." />
+      <BitField start="3" size="1" name="DAIF" description="DA Inverse Filtering  When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames.  When reset, normal filtering of frames is performed." />
+      <BitField start="4" size="1" name="PM" description="Pass All Multicast  When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed.  When reset, filtering of multicast frame depends on HMC bit." />
+      <BitField start="5" size="1" name="DBF" description="Disable Broadcast Frames  When this bit is set, the AFM module filters all incoming broadcast frames.  When this bit is reset, the AFM module passes all received broadcast frames." />
+      <BitField start="6" size="2" name="PCF" description="Pass Control Frames  These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames). Note that the processing of PAUSE control frames depends only on RFE of the Flow Control Register.  00 = MAC filters all control frames from reaching the application.  01 = MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter.  10 = MAC forwards all control frames to application even if they fail the Address Filter.  11 = MAC forwards control frames that pass the Address Filter." />
+      <BitField start="8" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="HPF" description="Hash or perfect filter When set, this bit configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by HMC or HUC bits. When low and if the HUC/HMC bit is set, the frame is passed only if it matches the Hash filter." />
+      <BitField start="11" size="20" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="RA" description="Receive all When this bit is set, the MAC Receiver module passes to the Application all frames received irrespective of whether they pass the address filter. The result of the SA/DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes to the Application only those frames that pass the SA/DA address filter." />
+    </Register>
+    <Register start="+0x0008" size="4" name="MAC_HASHTABLE_HIGH" access="Read/Write" description="Hash table high register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="HTH" description="Hash table high This field contains the upper 32 bits of Hash table." />
+    </Register>
+    <Register start="+0x000C" size="4" name="MAC_HASHTABLE_LOW" access="Read/Write" description="Hash table low register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="HTL" description="Hash table low This field contains the upper 32 bits of Hash table." />
+    </Register>
+    <Register start="+0x0010" size="4" name="MAC_MII_ADDR" access="Read/Write" description="MII address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GB" description="MII busy This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  This bit should read a logic 0 before writing to this register and the MAC_MII_DATA register. This bit must also be set to 0 during a Write to this register. During a PHY register access, this bit will be set to 1 by the Application to indicate that a Read or Write access is in progress. The MAC_MII_DATA register should be kept valid until this bit is cleared by the MAC during a PHY Write operation. The MAC_MII_DATA register is invalid until this bit is cleared by the MAC during a PHY Read operation. This register should not be written to until this bit is cleared." />
+      <BitField start="1" size="1" name="W" description="MII write When set, this bit tells the PHY that this will be a Write operation using the MII Data register. If this bit is not set, this will be a Read operation, placing the data in the MII Data register." />
+      <BitField start="2" size="4" name="CR" description="CSR clock range The CSR Clock Range selection determines the frequency of the MDC clock. The suggested range of CLK_M4_ETHERNET frequency applicable for each value below (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz.  When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when CLK_M4_ETHERNET is of frequency 100 MHz and you program these bits as 1010, then the resultant MDC clock will be of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the values given below only if the interfacing chips supports faster MDC clocks.  See Table 554 for bit values." />
+      <BitField start="6" size="5" name="GR" description="MII register These bits select the desired MII register in the selected PHY device." />
+      <BitField start="11" size="5" name="PA" description="Physical layer address This field tells which of the 32 possible PHY devices are being accessed." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0014" size="4" name="MAC_MII_DATA" access="Read/Write" description="MII data register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="GD" description="MII data This contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0018" size="4" name="MAC_FLOW_CTRL" access="Read/Write" description="Flow control register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FCB" description="Flow Control Busy/Backpressure Activate  This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  This bit initiates a Pause Control frame in Full-Duplex mode. In Full-Duplex mode, this bit should be read as 0 before writing to the Flow Control register. To initiate a Pause control frame, the Application must set this bit to 1. During a transfer of the Control Frame, this bit will continue to be set to signify that a frame transmission is in progress. After the completion of Pause control frame transmission, the MAC will reset this bit to 0. The Flow Control register should not be written to until this bit is cleared. In Half-Duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC Core. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the flow controller input signal for the backpressure function. When the MAC is configured to Full- Duplex mode, the BPA is automatically disabled." />
+      <BitField start="1" size="1" name="TFE" description="Transmit Flow Control Enable  In Full-Duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC will not transmit any Pause frames. In Half-Duplex mode, when this bit is set, the MAC enables the back-pressure operation. When this bit is reset, the backpressure feature is disabled." />
+      <BitField start="2" size="1" name="RFE" description="Receive Flow Control Enable  When this bit is set, the MAC will decode the received Pause frame and disable its transmitter for a specified (Pause Time) time. When this bit is reset, the decode function of the Pause frame is disabled." />
+      <BitField start="3" size="1" name="UP" description="Unicast Pause Frame Detect  When this bit is set, the MAC will detect the Pause frames with the station's unicast address specified in MAC Address0 High Register and MAC Address0 Low Register, in addition to the detecting Pause frames with the unique multicast address. When this bit is reset, the MAC will detect only a Pause frame with the unique multicast address specified in the 802.3x standard." />
+      <BitField start="4" size="2" name="PLT" description="Pause Low Threshold  This field configures the threshold of the PAUSE timer at which the input flow control is checked for automatic retransmission of PAUSE Frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 0x100 (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the flow control signal is asserted at 228 (256 - 28) slot-times after the first PAUSE frame is transmitted." />
+      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="7" size="1" name="DZPQ" description="Disable Zero-Quanta Pause  When set, this bit disables the automatic generation of Zero-Quanta Pause Control frames on the deassertion of the flow-control signal from the FIFO layer. When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled." />
+      <BitField start="8" size="8" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="16" name="PT" description="Pause time This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain, then consecutive writes to this register should be performed only after at least 4 clock cycles in the destination clock domain." />
+    </Register>
+    <Register start="+0x001C" size="4" name="MAC_VLAN_TAG" access="Read/Write" description="VLAN tag register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="VL" description="VLAN Tag Identifier for Receive Frames  This contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to the fifteenth and sixteenth bytes of the frames being received for VLAN frames. Bits[15:13] are the User Priority, Bit[12] is the Canonical Format Indicator (CFI) and bits[11:0] are the VLAN tag's VLAN Identifier (VID) field. When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison.  If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and sixteenth bytes for VLAN tag comparison, and declares all frames with a Type field value of 0x8100 to be VLAN frames." />
+      <BitField start="16" size="1" name="ETV" description="Enable 12-Bit VLAN Tag Comparison  When this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLAN tag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared with the corresponding field in the received VLAN-tagged frame.  When this bit is reset, all 16 bits of the received VLAN frame's fifteenth and sixteenth bytes are used for comparison." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0024" size="4" name="MAC_DEBUG" access="ReadOnly" description="Debug register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXIDLESTAT" description="When high, it indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state." />
+      <BitField start="1" size="2" name="FIFOSTAT0" description="When high, it indicates the active state of the small FIFO Read and Write controllers respectively of the MAC receive Frame Controller module." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="1" name="RXFIFOSTAT1" description="When high, it indicates that the MTL RxFIFO Write Controller is active and transferring a received frame to the FIFO." />
+      <BitField start="5" size="2" name="RXFIFOSTAT" description="State of the RxFIFO read Controller:  00 = idle state 01 = reading frame data 10 = reading frame status (or Time stamp) 11 = flushing the frame data and status" />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="RXFIFOLVL" description="Status of the RxFIFO Fill-level  00 = RxFIFO Empty  01 = RxFIFO fill-level below flow-control de-activate threshold  10 = RxFIFO fill-level above flow-control activate threshold  11 = RxFIFO Full" />
+      <BitField start="10" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="TXIDLESTAT" description="When high, it indicates that the MAC MII transmit protocol engine is actively transmitting data and not in IDLE state." />
+      <BitField start="17" size="2" name="TXSTAT" description="State of the MAC Transmit Frame Controller module:  00 = idle 01 = Waiting for Status of previous frame or IFG/backoff period to be over  10 = Generating and transmitting a PAUSE control frame (in full duplex mode)  11 = Transferring input frame for transmission" />
+      <BitField start="19" size="1" name="PAUSE" description="When high, it indicates that the MAC transmitter is in PAUSE condition (in full-duplex only) and hence will not schedule any frame for transmission." />
+      <BitField start="20" size="2" name="TXFIFOSTAT" description="State of the TxFIFO read Controller  00 = idle state 01 = READ state (transferring data to MAC transmitter)  10 = Waiting for TxStatus from MAC transmitter  11 = Writing the received TxStatus or flushing the TxFIFO" />
+      <BitField start="22" size="1" name="TXFIFOSTAT1" description="When high, it indicates that the TxFIFO Write Controller is active and transferring data to the TxFIFO." />
+      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="1" name="TXFIFOLVL" description="When high, it indicates that the TxFIFO is not empty and has some data left for transmission." />
+      <BitField start="25" size="1" name="TXFIFOFULL" description="When high, it indicates that the TxStatus FIFO is full and hence the controller will not be accepting any more frames for transmission." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0028" size="4" name="MAC_RWAKE_FRFLT" access="Read/Write" description="Remote wake-up frame filter" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="ADDR" description="WKUPFMFILTER address" />
+    </Register>
+    <Register start="+0x002C" size="4" name="MAC_PMT_CTRL_STAT" access="Read/Write" description="PMT control and status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Power-down This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When set, all received frames will be dropped. This bit is cleared automatically when a magic packet or Wake-Up frame is received, and Power-Down mode is disabled. Frames received after this bit is cleared are forwarded to the application.This bit must only be set when either the Magic Packet Enable or Wake- Up Frame Enable bit is set high." />
+      <BitField start="1" size="1" name="MPE" description="Magic packet enable When set, enables generation of a power management event due to Magic Packet reception." />
+      <BitField start="2" size="1" name="WFE" description="Wake-up frame enable When set, enables generation of a power management event due to wake-up frame reception." />
+      <BitField start="3" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="MPR" description="Magic Packet Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  When set, this bit indicates the power management event was generated by the reception of a Magic Packet. This bit is cleared by a Read into this register." />
+      <BitField start="6" size="1" name="WFR" description="Wake-up Frame Received This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.   When set, this bit indicates the power management event was generated due to reception of a wake-up frame. This bit is cleared by a Read into this register." />
+      <BitField start="7" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="9" size="1" name="GU" description="Global Unicast When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a wake-up frame." />
+      <BitField start="10" size="21" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="WFFRPR" description="Wake-up Frame Filter Register Pointer Reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When set, resets the Remote Wake-up Frame Filter register pointer to 000. It is automatically cleared after 1 clock cycle." />
+    </Register>
+    <Register start="+0x0038" size="4" name="MAC_INTR" access="ReadOnly" description="Interrupt status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="3" size="1" name="PMT" description="PMT Interrupt Status  This bit is set whenever a Magic packet or Wake-on-LAN frame is received in Power- Down mode (See bits 5 and 6 in Table 560). This bit is cleared when both bits[6:5] are cleared because of a read operation to the PMT Control and Status register." />
+      <BitField start="4" size="5" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="TS" description="Timestamp interrupt status When Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true:  - The system time value equals or exceeds the value specified in the Target Time High and Low registers  - There is an overflow in the seconds register  This bit is cleared on reading the byte 0 of the Timestamp Status register (Table 576).  Otherwise, when default Time stamping is enabled, this bit when set indicates that the system time value equals or exceeds the value specified in the Target Time registers. In this mode, this bit is cleared after the completion of the read of this Interrupt Status Register[9]. In all other modes, this bit is reserved." />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="11" size="21" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x003C" size="4" name="MAC_INTR_MASK" access="Read/Write" description="Interrupt mask register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="3" size="1" name="PMTIM" description="PMT Interrupt Mask  This bit when set, will disable the assertion of the interrupt signal due to the setting of PMT Interrupt Status bit in Table 561." />
+      <BitField start="4" size="5" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="TSIM" description="Timestamp interrupt mask When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Table 561" />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0040" size="4" name="MAC_ADDR0_HIGH" access="Read/Write" description="MAC address 0 high register" reset_value="0x8000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="A47_32" description="MAC Address0 [47:32]  This field contains the upper 16 bits (47:32) of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames." />
+      <BitField start="16" size="15" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="MO" description="Always 1" />
+    </Register>
+    <Register start="+0x0044" size="4" name="MAC_ADDR0_LOW" access="Read/Write" description="MAC address 0 low register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="A31_0" description="MAC Address0 [31:0]  This field contains the lower 32 bits of the 6-byte first MAC address. This is used by the MAC for filtering for received frames and for inserting the MAC address in the Transmit Flow Control (PAUSE) Frames." />
+    </Register>
+    <Register start="+0x0700" size="4" name="MAC_TIMESTP_CTRL" access="Read/Write" description="Time stamp control register" reset_value="0x00002000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TSENA" description="Time stamp Enable  When this bit, is set the timestamping is enabled for transmit and receive frames. When disabled timestamp is not added for transmit and receive frames and the TimeStamp Generator is also suspended. User has to always initialize the TimeStamp (system time) after enabling this mode." />
+      <BitField start="1" size="1" name="TSCFUPDT" description="Time stamp Fine or Coarse Update  When set, indicates that the system times update to be done using fine update method. When reset it indicates the system time stamp update to be done using Coarse method. This bit is reserved if the fine correction option is not enabled." />
+      <BitField start="2" size="1" name="TSINIT" description="Time stamp Initialize This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the system time is initialized (over-written) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the initialize is complete." />
+      <BitField start="3" size="1" name="TSUPDT" description="Time stamp Update  This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the system time is updated (added/subtracted) with the value specified in the Time stamp High Update and Time stamp Low Update registers. This register bit should be read zero before updating it. This bit is reset once the update is completed in hardware." />
+      <BitField start="4" size="1" name="TSTRIG" description="Time stamp Interrupt Trigger Enable  This register field can be read and written by the application (Read and Write), and is cleared to 0 by the Ethernet core (Self Clear).  When set, the Time stamp interrupt is generated when the System Time becomes greater than the value written in Target Time register. This bit is reset after the generation of Time stamp Trigger Interrupt." />
+      <BitField start="5" size="1" name="TSADDREG" description="Addend Reg Update  When set, the contents of the Time stamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. This is a reserved bit when only coarse correction option is selected." />
+      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="TSENALL" description="Enable Time stamp for All Frames  When set, the Time stamp snapshot is enabled for all frames received by the core." />
+      <BitField start="9" size="1" name="TSCTRLSSR" description="Time stamp Digital or Binary rollover control  When set, the Time stamp Low register rolls over after 0x3B9A_C9FF value (i.e., 1 nanosecond accuracy) and increments the Time stamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and this bit value." />
+      <BitField start="10" size="1" name="TSVER2ENA" description="Enable PTP packet snooping for version 2 format  When set, the PTP packets are snooped using the 1588 version 2 format else snooped using the version 1 format." />
+      <BitField start="11" size="1" name="TSIPENA" description="Enable Time stamp Snapshot for PTP over Ethernet frames  When set, the Time stamp snapshot is taken for frames which have PTP messages in Ethernet frames (PTP over Ethernet) also. By default snapshots are taken for UDP-IP-Ethernet PTP packets." />
+      <BitField start="12" size="1" name="TSIPV6ENA" description="Enable Time stamp Snapshot for IPv6 frames  When set, the Time stamp snapshot is taken for IPv6 frames." />
+      <BitField start="13" size="1" name="TSIPV4ENA" description="Enable Time stamp Snapshot for IPv4 frames  When set, the Time stamp snapshot is taken for IPv4 frames." />
+      <BitField start="14" size="1" name="TSEVNTENA" description="Enable Time stamp Snapshot for Event Messages  When set, the Time stamp snapshot is taken for event messages only. When reset snapshot is taken for all other messages except Announce, Management and Signaling." />
+      <BitField start="15" size="1" name="TSMSTRENA" description="Enable Snapshot for Messages Relevant to Master  When set, the snapshot is taken for messages relevant to master node only else snapshot is taken for messages relevant to slave node. This is valid only for ordinary clock and boundary clock node." />
+      <BitField start="16" size="2" name="TSCLKTYPE" description="Select the type of clock node  The following are the options to select the type of clock node:  00 = ordinary clock 01 = boundary clock 10 = end-to-end transparent clock 11 = peer-to-peer transparent clock" />
+      <BitField start="18" size="1" name="TSENMACADDR" description="Enable MAC address for PTP frame filtering  When set, uses the DA MAC address (that matches any MAC Address register except the default MAC address 0) to filter the PTP frames when PTP is sent directly over Ethernet." />
+    </Register>
+    <Register start="+0x0704" size="4" name="SUBSECOND_INCR" access="Read/Write" description="Sub-second increment register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="SSINC" description="Sub-second increment value. The value programmed in this register is accumulated with the contents of the sub-second register. For example, to achieve an accuracy of 20 ns, the value to be programmed is 20. (Program 0x14 with a 50 MHz reference clock if 1 ns accuracy is selected.)" />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0708" size="4" name="SECONDS" access="ReadOnly" description="System time seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TSS" description="Time stamp second The value in this field indicates the current value in seconds of the System Time maintained by the core." />
+    </Register>
+    <Register start="+0x070C" size="4" name="NANOSECONDS" access="ReadOnly" description="System time nanoseconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="31" name="TSSS" description="Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR in the MAC_TIMESTAMP_CTRL register is set, each bit represents 1 ns and the maximum value will be 0x3B9A_C9FF, after which it rolls-over to zero)." />
+      <BitField start="31" size="1" name="PSNT" description="Positive or negative time This bit indicates positive or negative time value. If the bit is reset, it indicates that the time representation is positive, and if it is set, it indicates negative time value. (This bit represents the 32nd bit of the nanoseconds value when the Advance Time stamp feature is enabled)." />
+    </Register>
+    <Register start="+0x0710" size="4" name="SECONDSUPDATE" access="Read/Write" description="System time seconds update register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TSS" description="Time stamp second The value in this field indicates the time, in seconds, to be initialized or added to the system time." />
+    </Register>
+    <Register start="+0x0714" size="4" name="NANOSECONDSUPDATE" access="Read/Write" description="System time nanoseconds update register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="31" name="TSSS" description="Time stamp sub seconds The value in this field has the sub second representation of time, with an accuracy of 0.46 nano-second. (When TSCTRLSSR is set in the Time stamp control register, each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF.)" />
+      <BitField start="31" size="1" name="ADDSUB" description="Add or subtract time When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register." />
+    </Register>
+    <Register start="+0x0718" size="4" name="ADDEND" access="Read/Write" description="Time stamp addend register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TSAR" description="Time stamp addend This register indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization." />
+    </Register>
+    <Register start="+0x071C" size="4" name="TARGETSECONDS" access="Read/Write" description="Target time seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TSTR" description="Target time seconds register This register stores the time in seconds. When the Time stamp value matches or exceeds both Target Time stamp registers, the MAC, if enabled, generates an interrupt." />
+    </Register>
+    <Register start="+0x0720" size="4" name="TARGETNANOSECONDS" access="Read/Write" description="Target time nanoseconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="31" name="TSTR" description="Target Time stamp low  This register stores the time in (signed) nanoseconds. When the value of the Time stamp matches the Target Time stamp registers (both), the MAC will generate an interrupt if enabled. (This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Time stamp control register.)" />
+      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0724" size="4" name="HIGHWORD" access="Read/Write" description="System time higher word seconds register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TSHWR" description="Time stamp higher word Contains the most significant 16-bits of the Time stamp seconds value. The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0728" size="4" name="TIMESTAMPSTAT" access="ReadOnly" description="Time stamp status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TSSOVF" description="Time stamp seconds overflow When set, indicates that the seconds value of the Time stamp (when supporting version 2 format) has overflowed beyond 0xFFFF_FFFF." />
+      <BitField start="1" size="1" name="TSTARGT" description="Time stamp target reached When set, indicates the value of system time is greater or equal to the value specified in the Target Time High and Low registers" />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x1000" size="4" name="DMA_BUS_MODE" access="Read/Write" description="Bus Mode Register" reset_value="0x00020100" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SWR" description="Software reset This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When this bit is set, the MAC DMA Controller resets all MAC Subsystem internal registers and logic. It is cleared automatically after the reset operation has completed in all of the core clock domains. Read a 0 value in this bit before re-programming any register of the core.  The reset operation is completed only when all the resets in all the active clock domains are de-asserted. Hence it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for software reset completion." />
+      <BitField start="1" size="1" name="DA" description="DMA arbitration scheme 0 = Round-robin with Rx:Tx priority given in bits [15:14]  1 = Rx has priority over Tx" />
+      <BitField start="2" size="5" name="DSL" description="Descriptor skip length This bit specifies the number of Word to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When DSL value equals zero, then the descriptor table is taken as contiguous by the DMA, in Ring mode." />
+      <BitField start="7" size="1" name="ATDS" description="Alternate descriptor size When set, the alternate descriptor (see Section 26.7.6.3) size is increased to 32 bytes (8 DWORDS). This is required when the Advanced Time-Stamp feature or Full IPC Offload Engine is enabled in the receiver.  When reset, the descriptor size reverts back to 4 DWORDs (16 bytes)." />
+      <BitField start="8" size="6" name="PBL" description="Programmable burst length These bits indicate the maximum number of beats to be transferred in one DMA transaction. This will be the maximum value that is used in a single block Read/Write. The DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. When USP is set high, this PBL value is applicable for TxDMA transactions only.  The PBL values have the following limitations.  The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified (as given below). For different data bus widths and FIFO sizes, the valid PBL range (including x8 mode) is provided in the following table. If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered. Do not program out-of-range PBL values, because the system may not behave properly." />
+      <BitField start="14" size="2" name="PR" description="Rx-to-Tx priority ratio RxDMA requests given priority over TxDMA requests in the following ratio. This is valid only when the DA bit is reset.  00 = 1-to-1 01 = 2-to-1 10 = 3-to-1 11 = 4-to-1" />
+      <BitField start="16" size="1" name="FB" description="Fixed burst This bit controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations." />
+      <BitField start="17" size="6" name="RPBL" description="RxDMA PBL These bits indicate the maximum number of beats to be transferred in one RxDMA transaction. This will be the maximum value that is used in a single block Read/Write. The RxDMA will always attempt to burst as specified in RPBL each time it starts a Burst transfer on the host bus. RPBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value will result in undefined behavior. These bits are valid and applicable only when USP is set high." />
+      <BitField start="23" size="1" name="USP" description="Use separate PBL When set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL while the PBL value in bits [13:8] is applicable to TxDMA operations only. When reset to low, the PBL value in bits [13:8] is applicable for both DMA engines." />
+      <BitField start="24" size="1" name="PBL8X" description="8 x PBL mode When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) eight times. Thus the DMA will transfer data in to a maximum of 8, 16, 32, 64, 128, and 256 beats depending on the PBL value.  This bit function is not backward compatible. Before version 3.50a, this bit was 4xPBL." />
+      <BitField start="25" size="1" name="AAL" description="Address-aligned beats When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data buffer's start address) is not aligned, but subsequent bursts are aligned to the address." />
+      <BitField start="26" size="1" name="MB" description="Mixed burst When this bit is set high and FB bit is low, the AHB master interface will start all bursts of length more than 16 with INCR (undefined burst) whereas it will revert to fixed burst transfers (INCRx and SINGLE) for burst-length of 16 and below." />
+      <BitField start="27" size="1" name="TXPR" description="When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus." />
+      <BitField start="28" size="4" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1004" size="4" name="DMA_TRANS_POLL_DEMAND" access="Read/Write" description="Transmit poll demand register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TPD" description="Transmit poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered.  When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Transmit Descriptor register (Section 26.6.37). If that descriptor is not available (owned by Host), transmission returns to the Suspend state and bit 2 in the DMA_STAT Register is asserted. If the descriptor is available, transmission resumes." />
+    </Register>
+    <Register start="+0x1008" size="4" name="DMA_REC_POLL_DEMAND" access="Read/Write" description="Receive poll demand register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RPD" description="Receive poll demand This register field can be read by the application, and when a write operation is performed with any data value, an event is triggered.  When these bits are written with any value, the DMA reads the current descriptor pointed to by the Current Host Receive Descriptor register (Section 26.6.38). If that descriptor is not available (owned by Host), reception returns to the Suspended state and bit 7 in the DMA_STAT Register is not asserted. If the descriptor is available, the Receive DMA returns to active state." />
+    </Register>
+    <Register start="+0x100C" size="4" name="DMA_REC_DES_ADDR" access="Read/Write" description="Receive descriptor list address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRL" description="Start of receive list This field contains the base address of the First Descriptor in the Receive Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only." />
+    </Register>
+    <Register start="+0x1010" size="4" name="DMA_TRANS_DES_ADDR" access="Read/Write" description="Transmit descriptor list address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="SRL" description="Start of transmit list This field contains the base address of the First Descriptor in the Transmit Descriptor list. The LSB bit 1 will be ignored and taken as all-zero by the DMA internally. Hence these LSB bits are Read Only." />
+    </Register>
+    <Register start="+0x1014" size="4" name="DMA_STAT" access="Read/Write" description="Status register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TI" description="Transmit interrupt This bit indicates that frame transmission is finished and TDES1[31] is set in the First Descriptor." />
+      <BitField start="1" size="1" name="TPS" description="Transmit process stopped This bit is set when the transmission is stopped." />
+      <BitField start="2" size="1" name="TU" description="Transmit buffer unavailable  This bit indicates that the Next Descriptor in the Transmit List is owned by the host and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing transmit descriptors, the host should change the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command." />
+      <BitField start="3" size="1" name="TJT" description="Transmit jabber timeout  This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter had been excessively active. The transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert." />
+      <BitField start="4" size="1" name="OVF" description="Receive overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to application, the overflow status is set in RDES0[11]." />
+      <BitField start="5" size="1" name="UNF" description="Transmit underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set." />
+      <BitField start="6" size="1" name="RI" description="Receive interrupt  This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state." />
+      <BitField start="7" size="1" name="RU" description="Receive buffer unavailable  This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA. Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor was owned by the DMA." />
+      <BitField start="8" size="1" name="RPS" description="Received process stopped This bit is asserted when the Receive Process enters the Stopped state." />
+      <BitField start="9" size="1" name="RWT" description="Receive watchdog timeout  This bit is asserted when a frame with a length greater than 2,048 bytes is received (10,240 when Jumbo Frame mode is enabled)." />
+      <BitField start="10" size="1" name="ETI" description="Early transmit interrupt  This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO." />
+      <BitField start="11" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="13" size="1" name="FBI" description="Fatal bus error interrupt This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses." />
+      <BitField start="14" size="1" name="ERI" description="Early receive interrupt  This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt bit 6 in this register automatically clears this bit." />
+      <BitField start="15" size="1" name="AIE" description="Abnormal interrupt summary  Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register:  DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error Only unmasked bits affect the Abnormal Interrupt Summary bit.  This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared." />
+      <BitField start="16" size="1" name="NIS" description="Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register:  DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt Only unmasked bits affect the Normal Interrupt Summary bit.  This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a corresponding bit that causes NIS to be set is cleared." />
+      <BitField start="17" size="3" name="RS" description="Receive Process State These bits indicate the receive DMA state machine state. This field does not generate an interrupt. 000 = Stopped: Reset or Stop Receive Command issued.  001 = Running: Fetching Receive Transfer Descriptor.  010 = Reserved. 011 = Running: Waiting for receive packet.  100 = Suspended: Receive Descriptor Unavailable.  101 = Running: Closing Receive Descriptor.  110 = TIME_STAMP write state.  111 = Running: Transferring the receive packet data from receive buffer to host memory." />
+      <BitField start="20" size="3" name="TS" description="Transmit Process State These bits indicate the transmit DMA state machine state. This field does not generate an interrupt. 000 = Stopped; Reset or Stop Transmit Command issued.  001 = Running; Fetching Transmit Transfer Descriptor.  010 = Running; Waiting for status.  011 = Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO).  100 = TIME_STAMP write state.  101 = Reserved. 110 = Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow.  111 = Running; Closing Transmit Descriptor." />
+      <BitField start="23" size="1" name="EB1" description="Error bit 1 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during data transfer by TxDMA. 0 = Error during data transfer by RxDMA." />
+      <BitField start="24" size="1" name="EB2" description="Error bit 2 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during read transfer. 0 = Error during write transfer." />
+      <BitField start="25" size="1" name="EB3" description="Error bit 3 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt.  1 = Error during descriptor access. 0 = Error during data buffer access." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1018" size="4" name="DMA_OP_MODE" access="Read/Write" description="Operation mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="1" size="1" name="SR" description="Start/stop receive When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes incoming frames. Descriptor acquisition is attempted from the current position in the list, which is the address set by the DMA_REC_DES_ADDR register or the position retained when the Receive process was previously stopped. If no descriptor is owned by the DMA, reception is suspended and Receive Buffer Unavailable bit (bit 7 in DMA_STAT register) is set. The Start Receive command is effective only when reception has stopped. If the command was issued before setting the DMA_REC_DES_ADDR, DMA behavior is unpredictable." />
+      <BitField start="2" size="1" name="OSF" description="Operate on second frame When this bit is set, this bit instructs the DMA to process a second frame of Transmit data even before status for first frame is obtained." />
+      <BitField start="3" size="2" name="RTC" description="Receive threshold control These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are transferred automatically. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1.  00 = 64 01 = 32 10 = 96 11 = 128" />
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="FUF" description="Forward undersized good frames When set, the Rx FIFO will forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC).  When reset, the Rx FIFO will drop all frames of less than 64 bytes, unless it is already transferred due to lower value of Receive Threshold (e.g., RTC = 01)." />
+      <BitField start="7" size="1" name="FEF" description="Forward error frames When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, , watchdog timeout, overflow). However, if the frame's start byte (write) pointer is already transferred to the read controller side (in Threshold mode), then the frames are not dropped. When FEF is set, all frames except runt error frames are forwarded to the DMA. But when RxFIFO overflows when a partial frame is written, then such frames are dropped even when FEF is set." />
+      <BitField start="8" size="5" name="RESERVED" description="Reserved" />
+      <BitField start="13" size="1" name="ST" description="Start/Stop Transmission Command  When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by the DMA_TRANS_DES_ADDR register or from the position retained when transmission was stopped previously. If the current descriptor is not owned by the DMA, transmission enters the Suspended state and Transmit Buffer Unavailable (DMA_STAT register, bit 2) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting the DMA_TRANS_DES_ADDR register, then the DMA behavior is unpredictable.  When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and becomes the current position when transmission is restarted. The stop transmission command is effective only the transmission of the current frame is complete or when the transmission is in the Suspended state." />
+      <BitField start="14" size="3" name="TTC" description="Transmit threshold control These three bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when the TSF bit (Bit 21) is reset. 000 = 64 001 = 128 010 = 192 011 = 256 100 = 40 101 = 32 110 = 24 111 = 16" />
+      <BitField start="17" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="20" size="1" name="FTF" description="Flush transmit FIFO This register field can be read by the application (Read), can be set to 1 by the application with a register write of 1 (Write Set), and is cleared to 0 by the Ethernet core (Self Clear). The application cannot clear this type of field, and a register write of 0 to this bit has no effect on this field.  When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost/flushed. This bit is cleared internally when the flushing operation is completed fully. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter will not be flushed. It will be scheduled for transmission and will result in underflow and runt frame transmission.  The flush operation completes only after emptying the TxFIFO of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host. In order to complete this flush operation, the PHY transmit clock is required to be active." />
+      <BitField start="21" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="1" name="DFF" description="Disable flushing of received frames When this bit is set, the RxDMA does not flush any frames due to the unavailability of receive descriptors/buffers as it does normally when this bit is reset. (See)." />
+      <BitField start="25" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="27" size="5" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x101C" size="4" name="DMA_INT_EN" access="Read/Write" description="Interrupt enable register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TIE" description="Transmit interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Interrupt is enabled. When this bit is reset, Transmit Interrupt is disabled." />
+      <BitField start="1" size="1" name="TSE" description="Transmit stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmission Stopped Interrupt is enabled. When this bit is reset, Transmission Stopped Interrupt is disabled." />
+      <BitField start="2" size="1" name="TUE" description="Transmit buffer unavailable enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, Transmit Buffer Unavailable Interrupt is disabled." />
+      <BitField start="3" size="1" name="TJE" description="Transmit jabber timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, Transmit Jabber Timeout Interrupt is disabled." />
+      <BitField start="4" size="1" name="OVE" description="Overflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Overflow Interrupt is enabled. When this bit is reset, Overflow Interrupt is disabled." />
+      <BitField start="5" size="1" name="UNE" description="Underflow interrupt enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Transmit Underflow Interrupt is enabled. When this bit is reset, Underflow Interrupt is disabled." />
+      <BitField start="6" size="1" name="RIE" description="Receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Receive Interrupt is enabled. When this bit is reset, Receive Interrupt is disabled." />
+      <BitField start="7" size="1" name="RUE" description="Receive buffer unavailable enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled." />
+      <BitField start="8" size="1" name="RSE" description="Received stopped enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped Interrupt is disabled." />
+      <BitField start="9" size="1" name="RWE" description="Receive watchdog timeout enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive Watchdog Timeout Interrupt is disabled." />
+      <BitField start="10" size="1" name="ETE" description="Early transmit interrupt enable When this bit is set with an Abnormal Interrupt Summary Enable (bit 15 in this register), Early Transmit Interrupt is enabled. When this bit is reset, Early Transmit Interrupt is disabled." />
+      <BitField start="11" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="13" size="1" name="FBE" description="Fatal bus error enable When this bit is set with Abnormal Interrupt Summary Enable (bit 15 in this register), the Fatal Bus Error Interrupt is enabled. When this bit is reset, Fatal Bus Error Enable Interrupt is disabled." />
+      <BitField start="14" size="1" name="ERE" description="Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable (bit 16 in this register), Early Receive Interrupt is enabled. When this bit is reset, Early Receive Interrupt is disabled." />
+      <BitField start="15" size="1" name="AIE" description="Abnormal interrupt summary enable When this bit is set, an Abnormal Interrupt is enabled. When this bit is reset, an Abnormal Interrupt is disabled. This bit enables the following bits  DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error" />
+      <BitField start="16" size="1" name="NIE" description="Normal interrupt summary enable When this bit is set, a normal interrupt is enabled. When this bit is reset, a normal interrupt is disabled. This bit enables the following bits:  DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt" />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1020" size="4" name="DMA_MFRM_BUFOF" access="ReadOnly" description="Missed frame and buffer overflow register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="FMC" description="Number of frames missed This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  Indicates the number of frames missed by the controller due to the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with." />
+      <BitField start="16" size="1" name="OC" description="Overflow bit for missed frame counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field." />
+      <BitField start="17" size="11" name="FMA" description="Number of frames missed by the application This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field.  Indicates the number of frames missed by the application. This counter is incremented each time the MTL asserts the sideband signal. The counter is cleared when this register is read with ." />
+      <BitField start="28" size="1" name="OF" description="Overflow bit for FIFO overflow counter This register field can be read by the application (Read), can be set to 1 by the Ethernet core on a certain internal event (Self Set), and is automatically cleared to 0 on a register read. A register write of 0 has no effect on this field." />
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1024" size="4" name="DMA_REC_INT_WDT" access="Read/Write" description="Receive interrupt watchdog timer register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="RIWT" description="RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the RxDMA completes the transfer of a frame for which the RI status bit is not set due to the setting in the corresponding descriptor RDES1[31]. When the watch-dog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when RI bit is set high due to automatic setting of RI as per RDES1[31] of any received frame." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x1048" size="4" name="DMA_CURHOST_TRANS_DES" access="ReadOnly" description="Current host transmit descriptor register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="HTD" description="Host Transmit Descriptor Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
+    </Register>
+    <Register start="+0x104C" size="4" name="DMA_CURHOST_REC_DES" access="ReadOnly" description="Current host receive descriptor register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="HRD" description="Host Receive Descriptor Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
+    </Register>
+    <Register start="+0x1050" size="4" name="DMA_CURHOST_TRANS_BUF" access="ReadOnly" description="Current host transmit buffer address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="HTB" description="Host Transmit Buffer Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
+    </Register>
+    <Register start="+0x1054" size="4" name="DMA_CURHOST_REC_BUF" access="ReadOnly" description="Current host receive buffer address register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="HRB" description="Host Receive Buffer Address Pointer  Cleared on Reset. Pointer updated by DMA during operation." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ATIMER" start="0x40040000" description="Alarm timer ">
+    <Register start="+0x000" size="4" name="DOWNCOUNTER" access="Read/Write" description="Downcounter register" reset_value="0x000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CVAL" description="When equal to zero an interrupt is raised. When equal to zero PRESET is loaded and counting continues." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="PRESET" access="Read/Write" description="Preset value register" reset_value="0x000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="PRESETVAL" description="Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFD8" size="4" name="CLR_EN" access="WriteOnly" description="Interrupt clear enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLR_EN" description="Writing a 1 to this bit clears the interrupt enable bit in the ENABLE register." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFDC" size="4" name="SET_EN" access="WriteOnly" description="Interrupt set enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SET_EN" description="Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFE0" size="4" name="STATUS" access="ReadOnly" description="Status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="STAT" description="A 1 in this bit shows that the STATUS interrupt has been raised." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFE4" size="4" name="ENABLE" access="ReadOnly" description="Enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EN" description="A 1 in this bit shows that the STATUS interrupt has been enabled and that the STATUS interrupt request signal is asserted when STAT = 1 in the STATUS register." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFE8" size="4" name="CLR_STAT" access="WriteOnly" description="Clear register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CSTAT" description="Writing a 1 to this bit clears the STATUS interrupt bit in the STATUS register." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFEC" size="4" name="SET_STAT" access="WriteOnly" description="Set register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SSTAT" description="Writing a 1 to this bit sets the STATUS interrupt bit in the STATUS register." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="REGFILE" start="0x40041000" description=" RTC REGFILE ">
+    <Register start="+0x000+0" size="4" name="REGFILE[0]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+4" size="4" name="REGFILE[1]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+8" size="4" name="REGFILE[2]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+12" size="4" name="REGFILE[3]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+16" size="4" name="REGFILE[4]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+20" size="4" name="REGFILE[5]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+24" size="4" name="REGFILE[6]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+28" size="4" name="REGFILE[7]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+32" size="4" name="REGFILE[8]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+36" size="4" name="REGFILE[9]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+40" size="4" name="REGFILE[10]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+44" size="4" name="REGFILE[11]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+48" size="4" name="REGFILE[12]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+52" size="4" name="REGFILE[13]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+56" size="4" name="REGFILE[14]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+60" size="4" name="REGFILE[15]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+64" size="4" name="REGFILE[16]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+68" size="4" name="REGFILE[17]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+72" size="4" name="REGFILE[18]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+76" size="4" name="REGFILE[19]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+80" size="4" name="REGFILE[20]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+84" size="4" name="REGFILE[21]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+88" size="4" name="REGFILE[22]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+92" size="4" name="REGFILE[23]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+96" size="4" name="REGFILE[24]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+100" size="4" name="REGFILE[25]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+104" size="4" name="REGFILE[26]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+108" size="4" name="REGFILE[27]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+112" size="4" name="REGFILE[28]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+116" size="4" name="REGFILE[29]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+120" size="4" name="REGFILE[30]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+124" size="4" name="REGFILE[31]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+128" size="4" name="REGFILE[32]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+132" size="4" name="REGFILE[33]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+136" size="4" name="REGFILE[34]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+140" size="4" name="REGFILE[35]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+144" size="4" name="REGFILE[36]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+148" size="4" name="REGFILE[37]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+152" size="4" name="REGFILE[38]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+156" size="4" name="REGFILE[39]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+160" size="4" name="REGFILE[40]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+164" size="4" name="REGFILE[41]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+168" size="4" name="REGFILE[42]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+172" size="4" name="REGFILE[43]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+176" size="4" name="REGFILE[44]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+180" size="4" name="REGFILE[45]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+184" size="4" name="REGFILE[46]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+188" size="4" name="REGFILE[47]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+192" size="4" name="REGFILE[48]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+196" size="4" name="REGFILE[49]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+200" size="4" name="REGFILE[50]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+204" size="4" name="REGFILE[51]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+208" size="4" name="REGFILE[52]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+212" size="4" name="REGFILE[53]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+216" size="4" name="REGFILE[54]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+220" size="4" name="REGFILE[55]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+224" size="4" name="REGFILE[56]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+228" size="4" name="REGFILE[57]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+232" size="4" name="REGFILE[58]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+236" size="4" name="REGFILE[59]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+240" size="4" name="REGFILE[60]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+244" size="4" name="REGFILE[61]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+248" size="4" name="REGFILE[62]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+    <Register start="+0x000+252" size="4" name="REGFILE[63]" access="Read/Write" description="General purpose storage register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REGVAL" description="General purpose storage." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="PMC" start="0x40042000" description="Power Management Controller (PMC)">
+    <Register start="+0x000" size="4" name="PD0_SLEEP0_HW_ENA" access="Read/Write" description="Hardware sleep event enable register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_EVENT0" description="Writing a 1 enables the Cortex-M4 core to put the part&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;into any of the Power-down modes Deep-sleep,&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Power-down, or Deep power-down depending on the&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;value in the PD0_SLEEP0_MODE register." />
+      <BitField start="1" size="1" name="ENA_EVENT1" description="Writing a 1 enables the Cortex-M0 core and the&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Cortex-M0 subsystem core to put the part into any of&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;the Power-down modes Deep-sleep, Power-down, or&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Deep power-down depending on the value in the&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;PD0_SLEEP0_MODE register." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="PD0_SLEEP0_MODE" access="Read/Write" description="Sleep power mode register" reset_value="0x003FFF7F" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWR_STATE" description="Selects between Deep-sleep, Power-down, and Deep power-down modes.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Only one of the following three values can be programmed in this register:&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 00AA = Deep-sleep mode&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 FCBA = Power-down mode&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 3CBA = Power-down mode with M0SUB SRAM maintained&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0x0030 FF7F = Deep power-down mode" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CREG" start="0x40043000" description="Configuration Registers (CREG)">
+    <Register start="+0x004" size="4" name="CREG0" access="Read/Write" description="Chip configuration register 32 kHz oscillator output and BOD control register." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="EN1KHZ" description="Enable 1 kHz output.">
+        <Enum name="1_KHZ_OUTPUT_DISABLE" start="0" description="1 kHz output disabled." />
+        <Enum name="1_KHZ_OUTPUT_ENABLED" start="1" description="1 kHz output enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="EN32KHZ" description="Enable 32 kHz output">
+        <Enum name="32_KHZ_OUTPUT_DISABL" start="0" description="32 kHz output disabled." />
+        <Enum name="32_KHZ_OUTPUT_ENABLE" start="1" description="32 kHz output enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="RESET32KHZ" description="32 kHz oscillator reset">
+        <Enum name="CLEAR_RESET" start="0" description="Clear reset." />
+        <Enum name="RESET_ACTIVE" start="1" description="Reset active." />
+      </BitField>
+      <BitField start="3" size="1" name="PD32KHZ" description="32 kHz power control.">
+        <Enum name="POWERED" start="0" description="Powered." />
+        <Enum name="POWERED_DOWN" start="1" description="Powered-down." />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="1" name="USB0PHY" description="USB0 PHY power control.">
+        <Enum name="ENABLE_USB0_PHY_POWE" start="0" description="Enable USB0 PHY power." />
+        <Enum name="DISABLE_USB0_PHY" start="1" description="Disable USB0 PHY. PHY powered down." />
+      </BitField>
+      <BitField start="6" size="2" name="ALARMCTRL" description="RTC_ALARM pin output control">
+        <Enum name="RTC_ALARM" start="0x0" description="RTC alarm." />
+        <Enum name="EVENT_ROUTER_EVENT" start="0x1" description="Event router event." />
+        <Enum name="RESERVED" start="0x2" description="Reserved." />
+        <Enum name="INACTIVE" start="0x3" description="Inactive." />
+      </BitField>
+      <BitField start="8" size="2" name="BODLVL1" description="BOD trip level to generate an interrupt. See the LPC43xx data sheets for the trip values.">
+        <Enum name="LEVEL_0_INTERRUPT" start="0x0" description="Level 0 interrupt" />
+        <Enum name="LEVEL_1_INTERRUPT" start="0x1" description="Level 1 interrupt" />
+        <Enum name="LEVEL_2_INTERRUPT" start="0x2" description="Level 2 interrupt" />
+        <Enum name="LEVEL_3_INTERRUPT" start="0x3" description="Level 3 interrupt" />
+      </BitField>
+      <BitField start="10" size="2" name="BODLVL2" description="BOD trip level to generate a reset. See the LPC43xx data sheets for the trip values.">
+        <Enum name="LEVEL_0_RESET" start="0x0" description="Level 0 reset" />
+        <Enum name="LEVEL_1_RESET" start="0x1" description="Level 1 reset" />
+        <Enum name="LEVEL_2_RESET" start="0x2" description="Level 2 reset" />
+        <Enum name="LEVEL_3_RESET" start="0x3" description="Level 3 reset" />
+      </BitField>
+      <BitField start="12" size="2" name="SAMPLECTRL" description="SAMPLE pin input/output control">
+        <Enum name="RESERVED" start="0x0" description="Reserved" />
+        <Enum name="SAMPLE_OUTPUT_FROM_T" start="0x1" description="Sample output from the event monitor/recorder." />
+        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x2" description="Output from the event router." />
+        <Enum name="RESERVED" start="0x3" description="Reserved." />
+      </BitField>
+      <BitField start="14" size="2" name="WAKEUP0CTRL" description="WAKEUP0 pin input/output control">
+        <Enum name="INPUT_TO_THE_EVENT_R" start="0x0" description="Input to the event router." />
+        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x1" description="Output from the event router." />
+        <Enum name="RESERVED" start="0x2" description="Reserved." />
+        <Enum name="INPUT_TO_THE_EVENT_R" start="0x3" description="Input to the event router." />
+      </BitField>
+      <BitField start="16" size="2" name="WAKEUP1CTRL" description="WAKEUP1 pin input/output control">
+        <Enum name="INPUT_TO_EVENT_ROUTE" start="0x0" description="Input to event router." />
+        <Enum name="OUTPUT_FROM_THE_EVEN" start="0x1" description="Output from the event router." />
+        <Enum name="RESERVED" start="0x2" description="Reserved" />
+        <Enum name="INPUT_TO_EVENT_ROUTE" start="0x3" description="Input to event router." />
+      </BitField>
+      <BitField start="18" size="14" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x100" size="4" name="M4MEMMAP" access="Read/Write" description="ARM Cortex-M4 memory mapping" reset_value="0x10400000" reset_mask="0xFFFFFFFF">
+      <BitField start="12" size="20" name="M4MAP" description="Shadow address when accessing memory at address 0x0000 0000" />
+    </Register>
+    <Register start="+0x118" size="4" name="CREG5" access="Read/Write" description="Chip configuration register 5. Controls JTAG access." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="10" name="RESERVED" description="Reserved." />
+      <BitField start="10" size="1" name="M0SUBTAPSEL" description="JTAG debug disable for M0SUB co-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect." />
+        <Enum name="DISABLE_JTAG_DEBUG" start="1" description="Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." />
+      </BitField>
+      <BitField start="11" size="1" name="M4TAPSEL" description="JTAG debug disable for M4 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect." />
+        <Enum name="DISABLE_JTAG_DEBUG" start="1" description="Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." />
+      </BitField>
+      <BitField start="12" size="1" name="M0APPTAPSEL" description="JTAG debug disable for M0APPco-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect." />
+        <Enum name="DISABLE_JTAG_DEBUG" start="1" description="Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source." />
+      </BitField>
+      <BitField start="13" size="19" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x11C" size="4" name="DMAMUX" access="Read/Write" description="DMA mux control" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="DMAMUXPER0" description="Select DMA to peripheral connection for DMA peripheral 0.">
+        <Enum name="SPIFI" start="0x0" description="SPIFI" />
+        <Enum name="SCT_CTOUT_2" start="0x1" description="SCT CTOUT_2" />
+        <Enum name="SGPIO14" start="0x2" description="SGPIO14" />
+        <Enum name="TIMER3_MATCH_1" start="0x3" description="Timer3 match 1" />
+      </BitField>
+      <BitField start="2" size="2" name="DMAMUXPER1" description="Select DMA to peripheral connection for DMA peripheral 1">
+        <Enum name="TIMER0_MATCH_0" start="0x0" description="Timer0 match 0" />
+        <Enum name="USART0_TRANSMIT" start="0x1" description="USART0 transmit" />
+        <Enum name="RESERVED" start="0x2" description="Reserved" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="4" size="2" name="DMAMUXPER2" description="Select DMA to peripheral connection for DMA peripheral 2.">
+        <Enum name="TIMER0_MATCH_1" start="0x0" description="Timer0 match 1" />
+        <Enum name="USART0_RECEIVE" start="0x1" description="USART0 receive" />
+        <Enum name="RESERVED" start="0x2" description="Reserved" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="6" size="2" name="DMAMUXPER3" description="Select DMA to peripheral connection for DMA peripheral 3.">
+        <Enum name="TIMER1_MATCH_0" start="0x0" description="Timer1 match 0" />
+        <Enum name="UART1_TRANSMIT" start="0x1" description="UART1 transmit" />
+        <Enum name="I2S1_DMA_REQUEST_1" start="0x2" description="I2S1 DMA request 1" />
+        <Enum name="SSP1_TRANSMIT" start="0x3" description="SSP1 transmit" />
+      </BitField>
+      <BitField start="8" size="2" name="DMAMUXPER4" description="Select DMA to peripheral connection for DMA peripheral 4.">
+        <Enum name="TIMER1_MATCH_1" start="0x0" description="Timer1 match 1" />
+        <Enum name="UART1_RECEIVE" start="0x1" description="UART1 receive" />
+        <Enum name="I2S1_DMA_REQUEST_2" start="0x2" description="I2S1 DMA request 2" />
+        <Enum name="SSP1_RECEIVE" start="0x3" description="SSP1 receive" />
+      </BitField>
+      <BitField start="10" size="2" name="DMAMUXPER5" description="Select DMA to peripheral connection for DMA peripheral 5.">
+        <Enum name="TIMER2_MATCH_0" start="0x0" description="Timer2 match 0" />
+        <Enum name="USART2_TRANSMIT" start="0x1" description="USART2 transmit" />
+        <Enum name="SSP1_TRANSMIT" start="0x2" description="SSP1 transmit" />
+        <Enum name="SGPIO15" start="0x3" description="SGPIO15" />
+      </BitField>
+      <BitField start="12" size="2" name="DMAMUXPER6" description="Selects DMA to peripheral connection for DMA peripheral 6.">
+        <Enum name="TIMER2_MATCH_1" start="0x0" description="Timer2 match 1" />
+        <Enum name="USART2_RECEIVE" start="0x1" description="USART2 receive" />
+        <Enum name="SSP1_RECEIVE" start="0x2" description="SSP1 receive" />
+        <Enum name="SGPIO14" start="0x3" description="SGPIO14" />
+      </BitField>
+      <BitField start="14" size="2" name="DMAMUXPER7" description="Selects DMA to peripheral connection for DMA peripheral 7.">
+        <Enum name="TIMER3_MATCH_0" start="0x0" description="Timer3 match 0" />
+        <Enum name="USART3_TRANSMIT" start="0x1" description="USART3 transmit" />
+        <Enum name="SCT_DMA_REQUEST_0" start="0x2" description="SCT DMA request 0" />
+        <Enum name="ADCHS_WRITE" start="0x3" description="ADCHS write" />
+      </BitField>
+      <BitField start="16" size="2" name="DMAMUXPER8" description="Select DMA to peripheral connection for DMA peripheral 8.">
+        <Enum name="TIMER3_MATCH_1" start="0x0" description="Timer3 match 1" />
+        <Enum name="USART3_RECEIVE" start="0x1" description="USART3 receive" />
+        <Enum name="SCT_DMA_REQUEST_1" start="0x2" description="SCT DMA request 1" />
+        <Enum name="ADCHS_READ" start="0x3" description="ADCHS read" />
+      </BitField>
+      <BitField start="18" size="2" name="DMAMUXPER9" description="Select DMA to peripheral connection for DMA peripheral 9.">
+        <Enum name="SSP0_RECEIVE" start="0x0" description="SSP0 receive" />
+        <Enum name="I2S0_DMA_REQUEST_1" start="0x1" description="I2S0 DMA request 1" />
+        <Enum name="SCT_DMA_REQUEST_1" start="0x2" description="SCT DMA request 1" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="20" size="2" name="DMAMUXPER10" description="Select DMA to peripheral connection for DMA peripheral 10.">
+        <Enum name="SSP0_TRANSMIT" start="0x0" description="SSP0 transmit" />
+        <Enum name="I2S0_DMA_REQUEST_2" start="0x1" description="I2S0 DMA request 2" />
+        <Enum name="SCT_DMA_REQUEST_0" start="0x2" description="SCT DMA request 0" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="22" size="2" name="DMAMUXPER11" description="Selects DMA to peripheral connection for DMA peripheral 11.">
+        <Enum name="SSP1_RECEIVE" start="0x0" description="SSP1 receive" />
+        <Enum name="SGPIO14" start="0x1" description="SGPIO14" />
+        <Enum name="USART0_TRANSMIT" start="0x2" description="USART0 transmit" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="24" size="2" name="DMAMUXPER12" description="Select DMA to peripheral connection for DMA peripheral 12.">
+        <Enum name="SSP1_TRANSMIT" start="0x0" description="SSP1 transmit" />
+        <Enum name="SGPIO15" start="0x1" description="SGPIO15" />
+        <Enum name="USART0_RECEIVE" start="0x2" description="USART0 receive" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="26" size="2" name="DMAMUXPER13" description="Select DMA to peripheral connection for DMA peripheral 13.">
+        <Enum name="ADC0" start="0x0" description="ADC0" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="SSP1_RECEIVE" start="0x2" description="SSP1 receive" />
+        <Enum name="USART3_RECEIVE" start="0x3" description="USART3 receive" />
+      </BitField>
+      <BitField start="28" size="2" name="DMAMUXPER14" description="Select DMA to peripheral connection for DMA peripheral 14.">
+        <Enum name="ADC1" start="0x0" description="ADC1" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="SSP1_TRANSMIT" start="0x2" description="SSP1 transmit" />
+        <Enum name="USART3_TRANSMIT" start="0x3" description="USART3 transmit" />
+      </BitField>
+      <BitField start="30" size="2" name="DMAMUXPER15" description="Select DMA to peripheral connection for DMA peripheral 15.">
+        <Enum name="DAC" start="0x0" description="DAC" />
+        <Enum name="SCT_CTOUT_3" start="0x1" description="SCT CTOUT_3" />
+        <Enum name="SGPIO15" start="0x2" description="SGPIO15" />
+        <Enum name="TIMER3_MATCH_0" start="0x3" description="Timer3 match 0" />
+      </BitField>
+    </Register>
+    <Register start="+0x120" size="4" name="FLASHCFGA" access="Read/Write" description="Flash accelerator configuration register for flash bank A" reset_value="0x8000F03A" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="RESERVED" description="Reserved. Do not change these bits from the reset value." />
+      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.">
+        <Enum name="1_BASE_M4_CLK_CLOCK" start="0x0" description="1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz." />
+        <Enum name="2_BASE_M4_CLK_CLOCKS" start="0x1" description="2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz." />
+        <Enum name="3_BASE_M4_CLK_CLOCKS" start="0x2" description="3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz." />
+        <Enum name="4_BASE_M4_CLK_CLOCKS" start="0x3" description="4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz." />
+        <Enum name="5_BASE_M4_CLK_CLOCKS" start="0x4" description="5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz." />
+        <Enum name="6_BASE_M4_CLK_CLOCKS" start="0x5" description="6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz." />
+        <Enum name="7_BASE_M4_CLK_CLOCKS" start="0x6" description="7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz." />
+        <Enum name="8_BASE_M4_CLK_CLOCKS" start="0x7" description="8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz." />
+        <Enum name="9_BASE_M4_CLK_CLOCKS" start="0x8" description="9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz." />
+        <Enum name="10_BASE_M4_CLK_CLOCK" start="0x9" description="10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions." />
+      </BitField>
+      <BitField start="16" size="15" name="RESERVED" description="Reserved. Write zeros only to these bits." />
+      <BitField start="31" size="1" name="POW" description="Flash bank A power control">
+        <Enum name="POWER_DOWN" start="0" description="Power-down" />
+        <Enum name="ACTIVE" start="1" description="Active (Default)" />
+      </BitField>
+    </Register>
+    <Register start="+0x124" size="4" name="FLASHCFGB" access="Read/Write" description="Flash accelerator configuration register for flash bank B" reset_value="0x8000F03A" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="RESERVED" description="Reserved. Do not change these bits from the reset value." />
+      <BitField start="12" size="4" name="FLASHTIM" description="Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access. Warning: Improper setting of this value may result in incorrect operation of the device. All other values are allowed but may not be optimal for the supported clock frequencies.">
+        <Enum name="1_BASE_M4_CLK_CLOCK" start="0x0" description="1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz." />
+        <Enum name="2_BASE_M4_CLK_CLOCKS" start="0x1" description="2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz." />
+        <Enum name="3_BASE_M4_CLK_CLOCKS" start="0x2" description="3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz." />
+        <Enum name="4_BASE_M4_CLK_CLOCKS" start="0x3" description="4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz." />
+        <Enum name="5_BASE_M4_CLK_CLOCKS" start="0x4" description="5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz." />
+        <Enum name="6_BASE_M4_CLK_CLOCKS" start="0x5" description="6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz." />
+        <Enum name="7_BASE_M4_CLK_CLOCKS" start="0x6" description="7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz." />
+        <Enum name="8_BASE_M4_CLK_CLOCKS" start="0x7" description="8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz." />
+        <Enum name="9_BASE_M4_CLK_CLOCKS" start="0x8" description="9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz." />
+        <Enum name="10_BASE_M4_CLK_CLOCK" start="0x9" description="10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting for all allowed conditions." />
+      </BitField>
+      <BitField start="16" size="15" name="RESERVED" description="Reserved. Write zeros only to these bits." />
+      <BitField start="31" size="1" name="POW" description="Flash bank A power control">
+        <Enum name="POWER_DOWN" start="0" description="Power-down" />
+        <Enum name="ACTIVE" start="1" description="Active (Default)" />
+      </BitField>
+    </Register>
+    <Register start="+0x128" size="4" name="ETBCFG" access="Read/Write" description="ETB RAM configuration" reset_value="0x1" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ETB" description="Select SRAM interface">
+        <Enum name="ETB_ACCESSES_SRAM_AT" start="0" description="ETB accesses SRAM at address 0x2000 C000." />
+        <Enum name="AHB_ACCESSES_SRAM_AT" start="1" description="AHB accesses SRAM at address 0x2000 C000." />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x12C" size="4" name="CREG6" access="Read/Write" description="Chip configuration register 6. Controls multiple functions : Ethernet interface, SCT output, I2S0/1 inputs, EMC clock." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="ETHMODE" description="Selects the Ethernet mode. Reset the ethernet after changing the PHY interface. All other settings are reserved.">
+        <Enum name="MII" start="0x0" description="MII" />
+        <Enum name="RMII" start="0x4" description="RMII" />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="CTOUTCTRL" description="Selects the functionality of the SCT outputs.">
+        <Enum name="COMBINE_SCT_AND_TIME" start="0" description="Combine SCT and timer match outputs. SCT outputs are Red with timer outputs." />
+        <Enum name="SCT_OUTPUTS_ONLY" start="1" description="SCT outputs only. SCT outputs are used without timer match outputs." />
+      </BitField>
+      <BitField start="5" size="7" name="RESERVED" description="Reserved." />
+      <BitField start="12" size="1" name="I2S0_TX_SCK_IN_SEL" description="I2S0_TX_SCK input select">
+        <Enum name="I2S_REGISTER" start="0" description="I2S Register. I2S clock selected as defined by the I2S transmit mode register Table 960." />
+        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
+      </BitField>
+      <BitField start="13" size="1" name="I2S0_RX_SCK_IN_SEL" description="I2S0_RX_SCK input select">
+        <Enum name="I2S_REGISTER" start="0" description="I2S Register. I2S clock selected as defined by the I2S receive mode register Table 961." />
+        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
+      </BitField>
+      <BitField start="14" size="1" name="I2S1_TX_SCK_IN_SEL" description="I2S1_TX_SCK input select">
+        <Enum name="I2S_REGISTER" start="0" description="I2S register. I2S clock selected as defined by the I2S transmit mode register Table 960." />
+        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S transmit clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
+      </BitField>
+      <BitField start="15" size="1" name="I2S1_RX_SCK_IN_SEL" description="I2S1_RX_SCK input select">
+        <Enum name="I2S_REGISTER" start="0" description="I2S register. I2S clock selected as defined by the I2S receive mode register Table 961." />
+        <Enum name="BASE_AUDIO_CLK_FOR_I" start="1" description="BASE_AUDIO_CLK for I2S receive clock MCLK input and MCLK output. The I2S must be configured in slave mode." />
+      </BitField>
+      <BitField start="16" size="1" name="EMC_CLK_SEL" description="EMC_CLK divided clock select (see Section 21.1).">
+        <Enum name="DIVIDE_BY_1" start="0" description="Divide by 1. EMC_CLK_DIV not divided." />
+        <Enum name="DIVIDE_BY_2" start="1" description="Divide by 2. EMC_CLK_DIV divided by 2." />
+      </BitField>
+      <BitField start="17" size="15" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x130" size="4" name="M4TXEVENT" access="Read/Write" description="Cortex-M4 TXEV event clear" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TXEVCLR" description="Cortex-M4 TXEV event.">
+        <Enum name="CLEAR_THE_TXEV_EVENT" start="0" description="Clear the TXEV event." />
+        <Enum name="NO_EFFECT" start="1" description="No effect." />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x200" size="4" name="CHIPID" access="ReadOnly" description="Part ID" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="32" name="ID" description="Boundary scan ID code 0x5906 002B or 0x6906 002B = LPC4350/30/20/10 (flashless parts) 0x4906 002B = LPC4357/53 (parts with on-chip flash)" />
+    </Register>
+    <Register start="+0x308" size="4" name="M0SUBMEMMAP" access="Read/Write" description="ARM Cortex-M0SUB memory mapping" reset_value="0x18400000" reset_mask="0xFFFFFFFF">
+      <BitField start="12" size="20" name="M0SUBMAP" description="Shadow address when accessing memory at address 0x0000 0000" />
+    </Register>
+    <Register start="+0x314" size="4" name="M0SUBTXEVENT" access="Read/Write" description="Cortex-M0SUB TXEV event clear" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TXEVCLR" description="Cortex-M0SUB TXEV event handling.">
+        <Enum name="CLEAR_THE_TXEV_EVENT" start="0" description="Clear the TXEV event." />
+        <Enum name="NO_EFFECT" start="1" description="No effect." />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x400" size="4" name="M0APPTXEVENT" access="Read/Write" description="Cortex-M0APP TXEV event clear" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TXEVCLR" description="Cortex-M0APP TXEV event handling.">
+        <Enum name="CLEAR_THE_TXEV_EVENT" start="0" description="Clear the TXEV event." />
+        <Enum name="NO_EFFECT" start="1" description="No effect." />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x404" size="4" name="M0APPMEMMAP" access="Read/Write" description="ARM Cortex-M0APP memory mapping" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
+      <BitField start="12" size="20" name="M0APPMAP" description="Shadow address when accessing memory at address 0x0000 0000" />
+    </Register>
+    <Register start="+0x500" size="4" name="USB0FLADJ" access="Read/Write" description="USB0 frame length adjust register" reset_value="0x20" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="FLTV" description="Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600" size="4" name="USB1FLADJ" access="Read/Write" description="USB1 frame length adjust register" reset_value="0x20" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="FLTV" description="Frame length timing value The frame length is given in the number of high-speed bit times in decimal format. Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (0x20), which results in a SOF cycle time of 60000. 0x00 = 59488 (= 59488 + 0 x 16) 0x01 = 59504 (= 59488 + 1 x 16) 0x02 = 59520 (= 59488 + 2 x 16) ... 0x1F = 59984 (= 59488 + 31 x 16) 0x20 = 60000 (= 59488 + 32 x 16) ... 0x3E = 60480 (= 59488 + 62 x 16) 0x3F = 60496 (= 59488 + 63 x 16)" />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="EVENTROUTER" start="0x40044000" description="Event router">
+    <Register start="+0x000" size="4" name="HILO" access="Read/Write" description="Level configuration register" reset_value="0x000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WAKEUP0_L" description="Level detect mode for WAKEUP0 event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect falling edge if bit 0 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP0 pin if bit 0 in the EDGE register is 0. Detect rising edge if bit 0 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="1" size="1" name="WAKEUP1_L" description="Level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP1 pin if bit 1 in the EDGE register is 0." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP1 pin if bit 1 in the EDGE register is 0. Detect rising edge if bit 1 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP2_L" description="Level detect mode for WAKEUP2 event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect falling edge if bit 2 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP2 pin if bit 2 in the EDGE register is 0. Detect rising edge if bit 2 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="3" size="1" name="WAKEUP3_L" description="Level detect mode for WAKEUP3 event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect falling edge if bit 3 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level on the WAKEUP3 pin if bit 3 in the EDGE register is 0. Detect rising edge if bit 3 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="4" size="1" name="ATIMER_L" description="Level detect mode for alarm timer event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect falling edge if bit 4 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the alarm timer interrupt if bit 4 in the EDGE register is 0. Detect rising edge if bit 4 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="5" size="1" name="RTC_L" description="Level detect mode for RTC event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect falling edge if bit 5 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the RTC interrupt if bit 5 in the EDGE register is 0. Detect rising edge if bit 5 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="6" size="1" name="BOD_L" description="Level detect mode for BOD event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect falling edge if bit 6 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the BOD interrupt if bit 6 in the EDGE register is 0. Detect rising edge if bit 6 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="7" size="1" name="WWDT_L" description="Level detect mode for WWDT event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect falling edge if bit 7 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the WWDT interrupt if bit 7 in the EDGE register is 0. Detect rising edge if bit 7 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="8" size="1" name="ETH_L" description="Level detect mode for Ethernet event">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect falling edge if bit 8 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the Ethernet interrupt if bit 8 in the EDGE register is 0. Detect rising edge if bit 8 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="9" size="1" name="USB0_L" description="Level detect mode for USB0 event">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect falling edge if bit 9 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the USB0 interrupt if bit 9 in the EDGE register is 0. Detect rising edge if bit 9 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="10" size="1" name="USB1_L" description="Level detect mode for USB1 event">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect falling edge if bit 10 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the USB1 interrupt if bit 10 in the EDGE register is 0. Detect rising edge if bit 10 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="11" size="1" name="SDMMC_L" description="Level detect mode for SD/MMC event">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect falling edge if bit 11 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the SD/MMC interrupt if bit 11 in the EDGE register is 0. Detect rising edge if bit 11 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="12" size="1" name="CAN_L" description="Level detect mode for C_CAN event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect falling edge if bit 12 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the combined C_CAN interrupt if bit 12 in the EDGE register is 0. Detect rising edge if bit 12 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="13" size="1" name="TIM2_L" description="Level detect mode for combined timer output 2 event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level GIMA output 25 if bit 13 in the EDGE register is 0. Detect falling edge if bit 13 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level GIMA output 25 if bit 13 in the EDGE register is 0. Detect rising edge if bit 13 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="14" size="1" name="TIM6_L" description="Level detect mode for combined timer output 6 event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect falling edge if bit 14 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of GIMA output 26 if bit 14 in the EDGE register is 0. Detect rising edge if bit 14 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="15" size="1" name="QEI_L" description="Level detect mode for QEI event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect falling edge if bit 15 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of the QEI interrupt if bit 15 in the EDGE register is 0. Detect rising edge if bit 15 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="16" size="1" name="TIM14_L" description="Level detect mode for combined timer output 14 event.">
+        <Enum name="DETECT_LOW_LEVEL" start="0" description="Detect LOW level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect falling edge if bit 16 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL" start="1" description="Detect HIGH level of GIMA output 27 if bit 16 in the EDGE register is 0. Detect rising edge if bit 16 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="19" size="1" name="RESET_L" description="Level detect mode for Reset">
+        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 17 in the EDGE register is 0. Detect falling edge if bit 17 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 17 in the EDGE register is 0. Detect rising edge if bit 17 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="20" size="1" name="BODRESET_L" description="Level detect mode for BOD Reset">
+        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 20 in the EDGE register is 0. Detect falling edge if bit 20 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 20 in the EDGE register is 0. Detect rising edge if bit 20 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="21" size="1" name="DPDRESET_L" description="Level detect mode for Deep power-down Reset">
+        <Enum name="DETECT_LOW_LEVEL_IF" start="0" description="Detect LOW level if bit 21 in the EDGE register is 0. Detect falling edge if bit 21 in the EDGE register is 1." />
+        <Enum name="DETECT_HIGH_LEVEL_IF" start="1" description="Detect HIGH level if bit 21 in the EDGE register is 0. Detect rising edge if bit 21 in the EDGE register is 1." />
+      </BitField>
+      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="EDGE" access="Read/Write" description="Edge configuration" reset_value="0x000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WAKEUP0_E" description="Edge detect mode for WAKEUP0 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP0 pin. Detect falling edge if bit 0 in the HILO register is 0. Detect rising edge if bit 0 in the HILO register is 1." />
+      </BitField>
+      <BitField start="1" size="1" name="WAKEUP1_E" description="Edge/level detect mode for WAKEUP1 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP1 pin. Detect falling edge if bit 1 in the HILO register is 0. Detect rising edge if bit 1 in the HILO register is 1." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP2_E" description="Edge/level detect mode for WAKEUP2 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP2 pin. Detect falling edge if bit 2 in the HILO register is 0. Detect rising edge if bit 2 in the HILO register is 1." />
+      </BitField>
+      <BitField start="3" size="1" name="WAKEUP3_E" description="Edge/level detect mode for WAKEUP3 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_WAKEU" start="1" description="Edge detect of WAKEUP3 pin. Detect falling edge if bit 30 in the HILO register is 0. Detect rising edge if bit 3 in the HILO register is 1." />
+      </BitField>
+      <BitField start="4" size="1" name="ATIMER_E" description="Edge/level detect mode for alarm timer event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_A" start="1" description="Edge detect of the alarm timer interrupt. Detect falling edge if bit 4 in the HILO register is 0. Detect rising edge if bit 4 in the HILO register is 1." />
+      </BitField>
+      <BitField start="5" size="1" name="RTC_E" description="Edge/level detect mode for RTC event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the RTC interrupt. Detect falling edge if bit 5 in the HILO register is 0. Detect rising edge if bit 5 in the HILO register is 1." />
+      </BitField>
+      <BitField start="6" size="1" name="BOD_E" description="Edge/level detect mode for BOD event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_B" start="1" description="Edge detect of the BOD interrupt. Detect falling edge if bit 6 in the HILO register is 0. Detect rising edge if bit 6 in the HILO register is 1." />
+      </BitField>
+      <BitField start="7" size="1" name="WWDT_E" description="Edge/level detect mode for WWDTD event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_W" start="1" description="Edge detect of the WWDT interrupt. Detect falling edge if bit 7 in the HILO register is 0. Detect rising edge if bit 7 in the HILO register is 1." />
+      </BitField>
+      <BitField start="8" size="1" name="ETH_E" description="Edge/level detect mode for ethernet event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_E" start="1" description="Edge detect of the Ethernet interrupt. Detect falling edge if bit 8 in the HILO register is 0. Detect rising edge if bit 8 in the HILO register is 1." />
+      </BitField>
+      <BitField start="9" size="1" name="USB0_E" description="Edge/level detect mode for USB0 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_U" start="1" description="Edge detect of the USB0 event. Detect falling edge if bit 9 in the HILO register is 0. Detect rising edge if bit 9 in the HILO register is 1." />
+      </BitField>
+      <BitField start="10" size="1" name="USB1_E" description="Edge/level detect mode for USB1 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_U" start="1" description="Edge detect of the USB1 interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." />
+      </BitField>
+      <BitField start="11" size="1" name="SDMMC_E" description="Edge/level detect mode for SD/MMC event.The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_S" start="1" description="Edge detect of the SD/MMC interrupt. Detect falling edge if bit 10 in the HILO register is 0. Detect rising edge if bit 10 in the HILO register is 1." />
+      </BitField>
+      <BitField start="12" size="1" name="CAN_E" description="Edge/level detect mode for C_CAN event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_C" start="1" description="Edge detect of the combined C_CAN interrupt. Detect falling edge if bit 12 in the HILO register is 0. Detect rising edge if bit 12 in the HILO register is 1." />
+      </BitField>
+      <BitField start="13" size="1" name="TIM2_E" description="Edge/level detect mode for combined timer output 2 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 25. Detect falling edge if bit 13 in the HILO register is 0. Detect rising edge if bit 13 in the HILO register is 1." />
+      </BitField>
+      <BitField start="14" size="1" name="TIM6_E" description="Edge/level detect mode for combined timer output 6 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 26. Detect falling edge if bit 14 in the HILO register is 0. Detect rising edge if bit 14 in the HILO register is 1." />
+      </BitField>
+      <BitField start="15" size="1" name="QEI_E" description="Edge/level detect mode for QEI interrupt signal. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_QEI_I" start="1" description="Edge detect of QEI interrupt. Detect falling edge if bit 15 in the HILO register is 0. Detect rising edge if bit 15 in the HILO register is 1." />
+      </BitField>
+      <BitField start="16" size="1" name="TIM14_E" description="Edge/level detect mode for combined timer output 14 event. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_GIMA" start="1" description="Edge detect of GIMA output 27. Detect falling edge if bit 16 in the HILO register is 0. Detect rising edge if bit 16 in the HILO register is 1." />
+      </BitField>
+      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="19" size="1" name="RESET_E" description="Edge/level detect mode for Reset. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 19 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." />
+      </BitField>
+      <BitField start="20" size="1" name="BODRESET_E" description="Edge detect of the BOD reset signal. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 20 in the HILO register is 0. Detect rising edge if bit 19 in the HILO register is 1." />
+      </BitField>
+      <BitField start="21" size="1" name="DPDRESET_E" description="Edge detect of the deep power-down reset signal. The corresponding bit in the EDGE register must be 0.">
+        <Enum name="LEVEL_DETECT" start="0" description="Level detect." />
+        <Enum name="EDGE_DETECT_OF_THE_R" start="1" description="Edge detect of the reset signal. Detect falling edge if bit 21 in the HILO register is 0. Detect rising edge if bit 21 in the HILO register is 1." />
+      </BitField>
+      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFD8" size="4" name="CLR_EN" access="WriteOnly" description="Clear event enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WAKEUP0_CLREN" description="Writing a 1 to this bit clears the event enable bit 0 in the ENABLE register." />
+      <BitField start="1" size="1" name="WAKEUP1_CLREN" description="Writing a 1 to this bit clears the event enable bit 1 in the ENABLE register." />
+      <BitField start="2" size="1" name="WAKEUP2_CLREN" description="Writing a 1 to this bit clears the event enable bit 2 in the ENABLE register." />
+      <BitField start="3" size="1" name="WAKEUP3_CLREN" description="Writing a 1 to this bit clears the event enable bit 3 in the ENABLE register." />
+      <BitField start="4" size="1" name="ATIMER_CLREN" description="Writing a 1 to this bit clears the event enable bit 4 in the ENABLE register." />
+      <BitField start="5" size="1" name="RTC_CLREN" description="Writing a 1 to this bit clears the event enable bit 5 in the ENABLE register." />
+      <BitField start="6" size="1" name="BOD_CLREN" description="Writing a 1 to this bit clears the event enable bit 6 in the ENABLE register." />
+      <BitField start="7" size="1" name="WWDT_CLREN" description="Writing a 1 to this bit clears the event enable bit 7 in the ENABLE register." />
+      <BitField start="8" size="1" name="ETH_CLREN" description="Writing a 1 to this bit clears the event enable bit 8 in the ENABLE register." />
+      <BitField start="9" size="1" name="USB0_CLREN" description="Writing a 1 to this bit clears the event enable bit 9 in the ENABLE register." />
+      <BitField start="10" size="1" name="USB1_CLREN" description="Writing a 1 to this bit clears the event enable bit 10 in the ENABLE register." />
+      <BitField start="11" size="1" name="SDMMC_CLREN" description="Writing a 1 to this bit clears the event enable bit 11 in the ENABLE register." />
+      <BitField start="12" size="1" name="CAN_CLREN" description="Writing a 1 to this bit clears the event enable bit 12 in the ENABLE register." />
+      <BitField start="13" size="1" name="TIM2_CLREN" description="Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register." />
+      <BitField start="14" size="1" name="TIM6_CLREN" description="Writing a 1 to this bit clears the event enable bit 14 in the ENABLE register." />
+      <BitField start="15" size="1" name="QEI_CLREN" description="Writing a 1 to this bit clears the event enable bit 15 in the ENABLE register." />
+      <BitField start="16" size="1" name="TIM14_CLREN" description="Writing a 1 to this bit clears the event enable bit 16 in the ENABLE register." />
+      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="19" size="1" name="RESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 19 in the ENABLE register." />
+      <BitField start="20" size="1" name="BODRESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 20 in the ENABLE register." />
+      <BitField start="21" size="1" name="DPDRESET_CLREN" description="Writing a 1 to this bit clears the event enable bit 21 in the ENABLE register." />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFDC" size="4" name="SET_EN" access="WriteOnly" description="Set event enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WAKEUP0_SETEN" description="Writing a 1 to this bit sets the event enable bit 0 in the ENABLE register." />
+      <BitField start="1" size="1" name="WAKEUP1_SETEN" description="Writing a 1 to this bit sets the event enable bit 1 in the ENABLE register." />
+      <BitField start="2" size="1" name="WAKEUP2_SETEN" description="Writing a 1 to this bit sets the event enable bit 2 in the ENABLE register." />
+      <BitField start="3" size="1" name="WAKEUP3_SETEN" description="Writing a 1 to this bit sets the event enable bit 3 in the ENABLE register." />
+      <BitField start="4" size="1" name="ATIMER_SETEN" description="Writing a 1 to this bit sets the event enable bit 4 in the ENABLE register." />
+      <BitField start="5" size="1" name="RTC_SETEN" description="Writing a 1 to this bit sets the event enable bit 5 in the ENABLE register." />
+      <BitField start="6" size="1" name="BOD_SETEN" description="Writing a 1 to this bit sets the event enable bit 6 in the ENABLE register." />
+      <BitField start="7" size="1" name="WWDT_SETEN" description="Writing a 1 to this bit sets the event enable bit 7 in the ENABLE register." />
+      <BitField start="8" size="1" name="ETH_SETEN" description="Writing a 1 to this bit sets the event enable bit 8 in the ENABLE register." />
+      <BitField start="9" size="1" name="USB0_SETEN" description="Writing a 1 to this bit sets the event enable bit 9 in the ENABLE register." />
+      <BitField start="10" size="1" name="USB1_SETEN" description="Writing a 1 to this bit sets the event enable bit 10 in the ENABLE register." />
+      <BitField start="11" size="1" name="SDMMC_SETEN" description="Writing a 1 to this bit sets the event enable bit 11 in the ENABLE register." />
+      <BitField start="12" size="1" name="CAN_SETEN" description="Writing a 1 to this bit sets the event enable bit 12 in the ENABLE register." />
+      <BitField start="13" size="1" name="TIM2_SETEN" description="Writing a 1 to this bit sets the event enable bit 13 in the ENABLE register." />
+      <BitField start="14" size="1" name="TIM6_SETEN" description="Writing a 1 to this bit sets the event enable bit 14 in the ENABLE register." />
+      <BitField start="15" size="1" name="QEI_SETEN" description="Writing a 1 to this bit sets the event enable bit 15 in the ENABLE register." />
+      <BitField start="16" size="1" name="TIM14_SETEN" description="Writing a 1 to this bit sets the event enable bit 16 in the ENABLE register." />
+      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="19" size="1" name="RESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 19 in the ENABLE register." />
+      <BitField start="20" size="1" name="BODRESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 20 in the ENABLE register." />
+      <BitField start="21" size="1" name="DPDRESET_SETEN" description="Writing a 1 to this bit sets the event enable bit 21 in the ENABLE register." />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFE0" size="4" name="STATUS" access="ReadOnly" description="Event Status register" reset_value="0x03FDFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WAKEUP0_ST" description="A 1 in this bit shows that the WAKEUP0 event has been raised." />
+      <BitField start="1" size="1" name="WAKEUP1_ST" description="A 1 in this bit shows that the WAKEUP1 event has been raised." />
+      <BitField start="2" size="1" name="WAKEUP2_ST" description="A 1 in this bit shows that the WAKEUP2 event has been raised." />
+      <BitField start="3" size="1" name="WAKEUP3_ST" description="A 1 in this bit shows that the WAKEUP3 event has been raised." />
+      <BitField start="4" size="1" name="ATIMER_ST" description="A 1 in this bit shows that the ATIMER event has been raised." />
+      <BitField start="5" size="1" name="RTC_ST" description="A 1 in this bit shows that the RTC event has been raised." />
+      <BitField start="6" size="1" name="BOD_ST" description="A 1 in this bit shows that the BOD event has been raised." />
+      <BitField start="7" size="1" name="WWDT_ST" description="A 1 in this bit shows that the WWDT event has been raised." />
+      <BitField start="8" size="1" name="ETH_ST" description="A 1 in this bit shows that the ETHERNET event has been raised." />
+      <BitField start="9" size="1" name="USB0_ST" description="A 1 in this bit shows that the USB0 event has been raised." />
+      <BitField start="10" size="1" name="USB1_ST" description="A 1 in this bit shows that the USB1 event has been raised." />
+      <BitField start="11" size="1" name="SDMMC_ST" description="A 1 in this bit indicates that the SDMMC event has been raised." />
+      <BitField start="12" size="1" name="CAN_ST" description="A 1 in this bit shows that the C_CAN event has been raised." />
+      <BitField start="13" size="1" name="TIM2_ST" description="A 1 in this bit shows that the combined timer 2 output event has been raised." />
+      <BitField start="14" size="1" name="TIM6_ST" description="A 1 in this bit shows that the combined timer 6 output event has been raised." />
+      <BitField start="15" size="1" name="QEI_ST" description="A 1 in this bit shows that the QEI event has been raised." />
+      <BitField start="16" size="1" name="TIM14_ST" description="A 1 in this bit shows that the combined timer 14 output event has been raised." />
+      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="19" size="1" name="RESET_ST" description="A 1 in this bit shows that the reset event has been raised." />
+      <BitField start="20" size="1" name="BODRESET_ST" description="A 1 in this bit indicates that the reset event has been raised." />
+      <BitField start="21" size="1" name="DPDRESET_ST" description="A 1 in this bit indicates that the reset event has been raised." />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFE4" size="4" name="ENABLE" access="ReadOnly" description="Event Enable register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WAKEUP0_EN" description="A 1 in this bit shows that the WAKEUP0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="1" size="1" name="WAKEUP1_EN" description="A 1 in this bit shows that the WAKEUP1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="2" size="1" name="WAKEUP2_EN" description="A 1 in this bit shows that the WAKEUP2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="3" size="1" name="WAKEUP3_EN" description="A 1 in this bit shows that the WAKEUP3 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="4" size="1" name="ATIMER_EN" description="A 1 in this bit shows that the ATIMER event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="5" size="1" name="RTC_EN" description="A 1 in this bit shows that the RTC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="6" size="1" name="BOD_EN" description="A 1 in this bit shows that the BOD event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="7" size="1" name="WWDT_EN" description="A 1 in this bit shows that the WWDT event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="8" size="1" name="ETH_EN" description="A 1 in this bit shows that the ETHERNET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="9" size="1" name="USB0_EN" description="A 1 in this bit shows that the USB0 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="10" size="1" name="USB1_EN" description="A 1 in this bit shows that the USB1 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="11" size="1" name="SDMMC_EN" description="A 1 in this bit indicates that the SDMMC event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="12" size="1" name="CAN_EN" description="A 1 in this bit shows that the CAN event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="13" size="1" name="TIM2_EN" description="A 1 in this bit shows that the TIM2 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="14" size="1" name="TIM6_EN" description="A 1 in this bit shows that the TIM6 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="15" size="1" name="QEI_EN" description="A 1 in this bit shows that the QEI event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="16" size="1" name="TIM14_EN" description="A 1 in this bit shows that the TIM14 event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="17" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="19" size="1" name="RESET_EN" description="A 1 in this bit shows that the RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="20" size="1" name="BODRESET_EN" description="A 1 in this bit indicates that the BOD RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="21" size="1" name="DPDRESET_EN" description="A 1 in this bit indicates that the deep power-down RESET event has been enabled. This event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the STATUS register." />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFE8" size="4" name="CLR_STAT" access="WriteOnly" description="Clear event status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WAKEUP0_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 0 in the STATUS register." />
+      <BitField start="1" size="1" name="WAKEUP1_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 1 in the STATUS register." />
+      <BitField start="2" size="1" name="WAKEUP2_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 2 in the STATUS register." />
+      <BitField start="3" size="1" name="WAKEUP3_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 3 in the STATUS register." />
+      <BitField start="4" size="1" name="ATIMER_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 4 in the STATUS register." />
+      <BitField start="5" size="1" name="RTC_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 5 in the STATUS register." />
+      <BitField start="6" size="1" name="BOD_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 6 in the STATUS register." />
+      <BitField start="7" size="1" name="WWDT_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 7 in the STATUS register." />
+      <BitField start="8" size="1" name="ETH_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 8 in the STATUS register." />
+      <BitField start="9" size="1" name="USB0_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 9 in the STATUS register." />
+      <BitField start="10" size="1" name="USB1_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 10 in the STATUS register." />
+      <BitField start="11" size="1" name="SDMMC_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 11 in the STATUS register." />
+      <BitField start="12" size="1" name="CAN_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 12 in the STATUS register." />
+      <BitField start="13" size="1" name="TIM2_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 13 in the STATUS register." />
+      <BitField start="14" size="1" name="TIM6_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 14 in the STATUS register." />
+      <BitField start="15" size="1" name="QEI_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 15 in the STATUS register." />
+      <BitField start="16" size="1" name="TIM14_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 16 in the STATUS register." />
+      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="19" size="1" name="RESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 19 in the STATUS register." />
+      <BitField start="20" size="1" name="BODRESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 20 in the STATUS register." />
+      <BitField start="21" size="1" name="DPDRESET_CLRST" description="Writing a 1 to this bit clears the STATUS event bit 21 in the STATUS register." />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0xFEC" size="4" name="SET_STAT" access="WriteOnly" description="Set event status register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WAKEUP0_SETST" description="Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS register." />
+      <BitField start="1" size="1" name="WAKEUP1_SETST" description="Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS register." />
+      <BitField start="2" size="1" name="WAKEUP2_SETST" description="Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS register." />
+      <BitField start="3" size="1" name="WAKEUP3_SETST" description="Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS register." />
+      <BitField start="4" size="1" name="ATIMER_SETST" description="Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS register." />
+      <BitField start="5" size="1" name="RTC_SETST" description="Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS register." />
+      <BitField start="6" size="1" name="BOD_SETST" description="Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS register." />
+      <BitField start="7" size="1" name="WWDT_SETST" description="Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register." />
+      <BitField start="8" size="1" name="ETH_SETST" description="Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS register." />
+      <BitField start="9" size="1" name="USB0_SETST" description="Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS register." />
+      <BitField start="10" size="1" name="USB1_SETST" description="Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS register." />
+      <BitField start="11" size="1" name="SDMMC_SETST" description="Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS register." />
+      <BitField start="12" size="1" name="CAN_SETST" description="Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS register." />
+      <BitField start="13" size="1" name="TIM2_SETST" description="Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register." />
+      <BitField start="14" size="1" name="TIM6_SETST" description="Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register." />
+      <BitField start="15" size="1" name="QEI_SETST" description="Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS register." />
+      <BitField start="16" size="1" name="TIM14_SETST" description="Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS register." />
+      <BitField start="17" size="2" name="RESERVED" description="Reserved." />
+      <BitField start="19" size="1" name="RESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS register." />
+      <BitField start="20" size="1" name="BODRESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 20 in the STATUS register." />
+      <BitField start="21" size="1" name="DPDRESET_SETST" description="Writing a 1 to this bit sets the STATUS event bit 21 in the STATUS register." />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RTC" start="0x40046000" description="Real-Time Clock (RTC) and event recorder ">
+    <Register start="+0x000" size="4" name="ILR" access="WriteOnly" description="Interrupt Location Register" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RTCCIF" description="When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt." />
+      <BitField start="1" size="1" name="RTCALF" description="When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="CCR" access="Read/Write" description="Clock Control Register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CLKEN" description="Clock Enable.">
+        <Enum name="DISABLED" start="0" description="The time counters are disabled so that they may be initialized." />
+        <Enum name="ENABLED" start="1" description="The time counters are enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="CTCRST" description="CTC Reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect." />
+        <Enum name="RESET" start="1" description="When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software." />
+      </BitField>
+      <BitField start="2" size="2" name="RESERVED" description="Internal test mode controls. These bits must be 0 for normal RTC operation." />
+      <BitField start="4" size="1" name="CCALEN" description="Calibration counter enable.">
+        <Enum name="ENABLED" start="0" description="The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 29.6.6.2 and  Section 29.7.1." />
+        <Enum name="DISABLED" start="1" description="The calibration counter is disabled and reset to zero." />
+      </BitField>
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="CIIR" access="Read/Write" description="Counter Increment Interrupt Register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="IMSEC" description="When 1, an increment of the Second value generates an interrupt." />
+      <BitField start="1" size="1" name="IMMIN" description="When 1, an increment of the Minute value generates an interrupt." />
+      <BitField start="2" size="1" name="IMHOUR" description="When 1, an increment of the Hour value generates an interrupt." />
+      <BitField start="3" size="1" name="IMDOM" description="When 1, an increment of the Day of Month value generates an interrupt." />
+      <BitField start="4" size="1" name="IMDOW" description="When 1, an increment of the Day of Week value generates an interrupt." />
+      <BitField start="5" size="1" name="IMDOY" description="When 1, an increment of the Day of Year value generates an interrupt." />
+      <BitField start="6" size="1" name="IMMON" description="When 1, an increment of the Month value generates an interrupt." />
+      <BitField start="7" size="1" name="IMYEAR" description="When 1, an increment of the Year value generates an interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="AMR" access="Read/Write" description="Alarm Mask Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="AMRSEC" description="When 1, the Second value is not compared for the alarm." />
+      <BitField start="1" size="1" name="AMRMIN" description="When 1, the Minutes value is not compared for the alarm." />
+      <BitField start="2" size="1" name="AMRHOUR" description="When 1, the Hour value is not compared for the alarm." />
+      <BitField start="3" size="1" name="AMRDOM" description="When 1, the Day of Month value is not compared for the alarm." />
+      <BitField start="4" size="1" name="AMRDOW" description="When 1, the Day of Week value is not compared for the alarm." />
+      <BitField start="5" size="1" name="AMRDOY" description="When 1, the Day of Year value is not compared for the alarm." />
+      <BitField start="6" size="1" name="AMRMON" description="When 1, the Month value is not compared for the alarm." />
+      <BitField start="7" size="1" name="AMRYEAR" description="When 1, the Year value is not compared for the alarm." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="CTIME0" access="ReadOnly" description="Consolidated Time Register 0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
+      <BitField start="6" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
+      <BitField start="14" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
+      <BitField start="21" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="24" size="3" name="DOW" description="Day of week value in the range of 0 to 6" />
+      <BitField start="27" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="CTIME1" access="ReadOnly" description="Consolidated Time Register 1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
+      <BitField start="5" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
+      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="CTIME2" access="ReadOnly" description="Consolidated Time Register 2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="SEC" access="Read/Write" description="Seconds Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="MIN" access="Read/Write" description="Minutes Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="HRS" access="Read/Write" description="Hours Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="DOM" access="Read/Write" description="Day of Month Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030" size="4" name="DOW" access="Read/Write" description="Day of Week Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x034" size="4" name="DOY" access="Read/Write" description="Day of Year Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
+      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x038" size="4" name="MONTH" access="Read/Write" description="Months Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x03C" size="4" name="YEAR" access="Read/Write" description="Years Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x040" size="4" name="CALIBRATION" access="Read/Write" description="Calibration Value Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="17" name="CALVAL" description="If enabled, the calibration counter counts up to this value. The maximum value is 131 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0." />
+      <BitField start="17" size="1" name="CALDIR" description="Calibration direction">
+        <Enum name="FORWARD_CALIBRATION_" start="0" description="Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds." />
+        <Enum name="BACKWARD_CALIBRATION" start="1" description="Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second." />
+      </BitField>
+    </Register>
+    <Register start="+0x060" size="4" name="ASEC" access="Read/Write" description="Alarm value for Seconds" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="SECONDS" description="Seconds value in the range of 0 to 59" />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x064" size="4" name="AMIN" access="Read/Write" description="Alarm value for Minutes" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="MINUTES" description="Minutes value in the range of 0 to 59" />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x068" size="4" name="AHRS" access="Read/Write" description="Alarm value for Hours" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="HOURS" description="Hours value in the range of 0 to 23" />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x6C" size="4" name="ADOM" access="Read/Write" description="Alarm value for Day of Month" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="DOM" description="Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year)." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="ADOW" access="Read/Write" description="Alarm value for Day of Week" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="DOW" description="Day of week value in the range of 0 to 6." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x074" size="4" name="ADOY" access="Read/Write" description="Alarm value for Day of Year" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="9" name="DOY" description="Day of year value in the range of 1 to 365 (366 for leap years)." />
+      <BitField start="9" size="23" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x078" size="4" name="AMON" access="Read/Write" description="Alarm value for Months" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="MONTH" description="Month value in the range of 1 to 12." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x07C" size="4" name="AYRS" access="Read/Write" description="Alarm value for Year" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="YEAR" description="Year value in the range of 0 to 4095." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x084" size="4" name="ERCONTRO" access="Read/Write" description="Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTWAKE_EN0" description="Interrupt and wake-up enable for channel 0.">
+        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 0." />
+        <Enum name="ENABLED" start="1" description="An event in channel 0 will trigger an (RTC) interrupt and a wake-up request." />
+      </BitField>
+      <BitField start="1" size="1" name="GPCLEAR_EN0" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0.">
+        <Enum name="DISABLED" start="0" description="Channel 0 has no influence on the general purpose registers." />
+        <Enum name="ENABLED" start="1" description="An event in channel 0 will clear the general purpose registers asynchronously." />
+      </BitField>
+      <BitField start="2" size="1" name="POL0" description="Selects the polarity of an event on input pin WAKEUP0.">
+        <Enum name="NEGATIVE" start="0" description="A channel 0 event is defined as a negative edge on WAKEUP0." />
+        <Enum name="POSITIVE" start="1" description="A channel 0 event is defined as a positive edge on WAKEUP0." />
+      </BitField>
+      <BitField start="3" size="1" name="EV0_INPUT_EN" description="Event enable control for channel 0. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
+        <Enum name="DISABLED" start="0" description="Event 0 input is disabled and forced high internally." />
+        <Enum name="ENABLED" start="1" description="Event 0 input is enabled." />
+      </BitField>
+      <BitField start="4" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="10" size="1" name="INTWAKE_EN1" description="Interrupt and wake-up enable for channel 1.">
+        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 1." />
+        <Enum name="ENABLED" start="1" description="An event in channel 1 will trigger an (RTC) interrupt and a wake-up request." />
+      </BitField>
+      <BitField start="11" size="1" name="GPCLEAR_EN1" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1.">
+        <Enum name="DISABLED" start="0" description="Channel 1 has no influence on the general purpose registers." />
+        <Enum name="ENABLED" start="1" description="A n event in channel 1 will clear the general purpose registers asynchronously." />
+      </BitField>
+      <BitField start="12" size="1" name="POL1" description="Selects the polarity of an event on input pin WAKEUP1.">
+        <Enum name="NEGATIVE" start="0" description="A channel 1 event is defined as a negative edge on WAKEUP1." />
+        <Enum name="POSITIVE" start="1" description="A channel 1 event is defined as a positive edge on WAKEUP1." />
+      </BitField>
+      <BitField start="13" size="1" name="EV1_INPUT_EN" description="Event enable control for channel 1. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
+        <Enum name="DISABLED" start="0" description="Event 1 input is disabled and forced high internally." />
+        <Enum name="ENABLED" start="1" description="Event 1 input is enabled." />
+      </BitField>
+      <BitField start="14" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="20" size="1" name="INTWAKE_EN2" description="Interrupt and wake-up enable for channel 2.">
+        <Enum name="DISABLED" start="0" description="No interrupt or wake-up will be generated by event channel 2." />
+        <Enum name="ENABLED" start="1" description="An event in channel 2 will trigger an (RTC) interrupt and a wake-up request." />
+      </BitField>
+      <BitField start="21" size="1" name="GPCLEAR_EN2" description="Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2.">
+        <Enum name="DISABLED" start="0" description="Channel 2 has no influence on the general purpose registers." />
+        <Enum name="ENABLED" start="1" description="An event in channel 2 will clear the general purpose registers asynchronously." />
+      </BitField>
+      <BitField start="22" size="1" name="POL2" description="Selects the polarity of an event on input pin WAKEUP2.">
+        <Enum name="NEGATIVE" start="0" description="A channel 2 event is defined as a negative edge on WAKEUP2." />
+        <Enum name="POSITIVE" start="1" description="A channel 2 event is defined as a positive edge on WAKEUP2." />
+      </BitField>
+      <BitField start="23" size="1" name="EV2_INPUT_EN" description="Event enable control for channel 2. Event Inputs should remain DISABLED when not being used for event detection, particularly if the associated pin is being used for some other function.">
+        <Enum name="DISABLED" start="0" description="Event 2 input is disabled and forced high internally." />
+        <Enum name="ENABLED" start="1" description="Event 2 input is enabled." />
+      </BitField>
+      <BitField start="24" size="6" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="30" size="2" name="ERMODE" description="Controls enabling the Event Monitor/Recorder and selecting its operating frequency. Event Monitor/Recorder registers can always be written to regardless of the state of these bits. Events occurring during the 1-sec interval immediately following enabling of the clocks may not be recognized.">
+        <Enum name="DISABLE_EVENT_MONITO" start="0x0" description="Disable Event Monitor/Recorder clocks. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected." />
+        <Enum name="16_HZ_SAMPLE_CLOCK" start="0x1" description="16 Hz sample clock. Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out." />
+        <Enum name="64_HZ_SAMPLE_CLOCK" start="0x2" description="64 Hz sample clock. Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out." />
+        <Enum name="1_KHZ_SAMPLE_CLOCK" start="0x3" description="1 kHz sample clock. Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out." />
+      </BitField>
+    </Register>
+    <Register start="+0x080" size="4" name="ERSTATUS" access="Read/Write" description="Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EV0" description="Channel0 event flag (WAKEUP0 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
+        <Enum name="NO_CHANGE" start="0" description="No event change on channel 0." />
+        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 0." />
+      </BitField>
+      <BitField start="1" size="1" name="EV1" description="Channel1 Event flag (WAKEUP1 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
+        <Enum name="NO_CHANGE" start="0" description="No event change on channel 1." />
+        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 1." />
+      </BitField>
+      <BitField start="2" size="1" name="EV2" description="Channel2 Event flag (WAKEUP2 pin). Set at the end of any second if there has been an event during the preceding second. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
+        <Enum name="NO_CHANGE" start="0" description="No event change on channel 2." />
+        <Enum name="EVENT" start="1" description="At least one event has occurred on channel 2." />
+      </BitField>
+      <BitField start="3" size="1" name="GP_CLEARED" description="General purpose register asynchronous clear flag. This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
+        <Enum name="NO_CHANGE" start="0" description="General purpose registers have not been asynchronous cleared." />
+        <Enum name="EVENT" start="1" description="General purpose registers have been asynchronous cleared." />
+      </BitField>
+      <BitField start="4" size="27" name="RESERVED" description="Reserved. Read value is undefined, only zero should be written." />
+      <BitField start="31" size="1" name="WAKEUP" description="Interrupt/wake-up request flag (Read-only). This bit is cleared by writing a 1 to it. Writing 0 has no effect.">
+        <Enum name="NOINTERRUPTWAKEUP" start="0" description="No interrupt/wake-up request is pending" />
+        <Enum name="INTERRUPTWAKEUP" start="1" description="An interrupt/wake-up request is pending." />
+      </BitField>
+    </Register>
+    <Register start="+0x088" size="4" name="ERCOUNTERS" access="ReadOnly" description="Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="COUNTER0" description="Value of the counter for Event 0. If the counter reaches full count (the value 7), it remains there if additional events occur. This counter is cleared when the corresponding EVx bit in the ERSTATUS register is cleared by software." />
+      <BitField start="3" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="3" name="COUNTER1" description="Value of the counter for event 1. See description for COUNTER0." />
+      <BitField start="11" size="5" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="3" name="COUNTER2" description="Value of the counter for event 2. See description for COUNTER0." />
+      <BitField start="19" size="13" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x090+0" size="4" name="ERFIRSTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
+      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
+      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
+      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x090+4" size="4" name="ERFIRSTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
+      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
+      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
+      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x090+8" size="4" name="ERFIRSTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
+      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
+      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
+      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x0A0+0" size="4" name="ERLASTSTAMP0" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
+      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
+      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
+      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x0A0+4" size="4" name="ERLASTSTAMP1" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
+      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
+      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
+      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x0A0+8" size="4" name="ERLASTSTAMP2" access="ReadOnly" description="Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="SEC" description="Seconds value in the range of 0 to 59." />
+      <BitField start="6" size="6" name="MIN" description="Minutes value in the range of 0 to 59." />
+      <BitField start="12" size="5" name="HOUR" description="Hours value in the range of 0 to 23." />
+      <BitField start="17" size="9" name="DOY" description="Day of Year value in the range of 1 to 366." />
+      <BitField start="26" size="6" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CGU" start="0x40050000" description="Clock Generation Unit (CGU)">
+    <Register start="+0x014" size="4" name="FREQ_MON" access="Read/Write" description="Frequency monitor register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="9" name="RCNT" description="9-bit reference clock-counter value" />
+      <BitField start="9" size="14" name="FCNT" description="14-bit selected clock-counter value" />
+      <BitField start="23" size="1" name="MEAS" description="Measure frequency">
+        <Enum name="RCNT_AND_FCNT_DISABL" start="0" description="RCNT and FCNT disabled" />
+        <Enum name="FREQUENCY_COUNTERS_S" start="1" description="Frequency counters started" />
+      </BitField>
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection for the clock to be measured. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR_D" start="0x00" description="32 kHz oscillator (default)" />
+        <Enum name="IRC" start="0x01" description="IRC" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="RESERVED" start="0x05" description="Reserved" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
+        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="RESERVED" start="0x0A" description="Reserved" />
+        <Enum name="RESERVED" start="0x0B" description="Reserved" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x018" size="4" name="XTAL_OSC_CTRL" access="Read/Write" description="Crystal oscillator control register" reset_value="0x00000005" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENABLE" description="Oscillator-pad enable. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!">
+        <Enum name="ENABLE" start="0" description="Enable" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down (default)" />
+      </BitField>
+      <BitField start="1" size="1" name="BYPASS" description="Configure crystal operation or external-clock input pin XTAL1. Do not change the BYPASS and ENABLE bits in one write-action: this will result in unstable device operation!">
+        <Enum name="CRYSTAL" start="0" description="Crystal. Operation with crystal connected (default)." />
+        <Enum name="BYPASS_MODE" start="1" description="Bypass mode. Use this mode when an external clock source is used instead of a crystal." />
+      </BitField>
+      <BitField start="2" size="1" name="HF" description="Select frequency range">
+        <Enum name="LOW" start="0" description="Low. Oscillator low-frequency mode (crystal or external clock source 1 to 20 MHz). Between 15 MHz and 20 MHz, the state of the HF bit is don't care." />
+        <Enum name="HIGH" start="1" description="High. Oscillator high-frequency mode; crystal or external clock source 15 to 25 MHz. Between 15 MHz and 20 MHz, the state of the HF bit is don't care." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x01C" size="4" name="PLL0USB_STAT" access="ReadOnly" description="PLL0USB status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LOCK" description="PLL0 lock indicator" />
+      <BitField start="1" size="1" name="FR" description="PLL0 free running indicator" />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020" size="4" name="PLL0USB_CTRL" access="Read/Write" description="PLL0USB control register" reset_value="0x01000003" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="PLL0 power down">
+        <Enum name="PLL0_ENABLED" start="0" description="PLL0 enabled" />
+        <Enum name="PLL0_POWERED_DOWN" start="1" description="PLL0 powered down" />
+      </BitField>
+      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
+        <Enum name="CCO_CLOCK_SENT_TO_PO" start="0" description="CCO clock sent to post-dividers. Use this in normal operation." />
+        <Enum name="PLL0_INPUT_CLOCK_SEN" start="1" description="PLL0 input clock sent to post-dividers (default)." />
+      </BitField>
+      <BitField start="2" size="1" name="DIRECTI" description="PLL0 direct input" />
+      <BitField start="3" size="1" name="DIRECTO" description="PLL0 direct output" />
+      <BitField start="4" size="1" name="CLKEN" description="PLL0 clock enable" />
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="FRM" description="Free running mode" />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
+      <BitField start="9" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x024" size="4" name="PLL0USB_MDIV" access="Read/Write" description="PLL0USB M-divider register" reset_value="0x05F85B6A" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="17" name="MDEC" description="Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071." />
+      <BitField start="17" size="5" name="SELP" description="Bandwidth select P value" />
+      <BitField start="22" size="6" name="SELI" description="Bandwidth select I value" />
+      <BitField start="28" size="4" name="SELR" description="Bandwidth select R value; SELR = 0." />
+    </Register>
+    <Register start="+0x028" size="4" name="PLL0USB_NP_DIV" access="Read/Write" description="PLL0USB N/P-divider register" reset_value="0x000B1002" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="PDEC" description="Decoded P-divider coefficient value" />
+      <BitField start="7" size="5" name="RESERVED" description="Reserved" />
+      <BitField start="12" size="10" name="NDEC" description="Decoded N-divider coefficient value" />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x02C" size="4" name="PLL0AUDIO_STAT" access="ReadOnly" description="PLL0AUDIO status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LOCK" description="PLL0 lock indicator" />
+      <BitField start="1" size="1" name="FR" description="PLL0 free running indicator" />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x030" size="4" name="PLL0AUDIO_CTRL" access="Read/Write" description="PLL0AUDIO control register" reset_value="0x01004003" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="PLL0 power down">
+        <Enum name="PLL0_ENABLED" start="0" description="PLL0 enabled" />
+        <Enum name="PLL0_POWERED_DOWN" start="1" description="PLL0 powered down" />
+      </BitField>
+      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
+        <Enum name="CCO_CLOCK_SENT_TO_PO" start="0" description="CCO clock sent to post-dividers. Use this in normal operation." />
+        <Enum name="PLL0_INPUT_CLOCK_SEN" start="1" description="PLL0 input clock sent to post-dividers (default)." />
+      </BitField>
+      <BitField start="2" size="1" name="DIRECTI" description="PLL0 direct input" />
+      <BitField start="3" size="1" name="DIRECTO" description="PLL0 direct output" />
+      <BitField start="4" size="1" name="CLKEN" description="PLL0 clock enable" />
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="FRM" description="Free running mode" />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
+      <BitField start="9" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved. Reads as zero. Do not write one to this register." />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="1" name="PLLFRACT_REQ" description="Fractional PLL word write request. Set this bit to 1 if the fractional divider is enabled in the SEL_EXT bit." />
+      <BitField start="13" size="1" name="SEL_EXT" description="Select fractional divider.">
+        <Enum name="FRAC_ENABLED" start="0" description="FRAC Enabled. Enable fractional divider." />
+        <Enum name="MDEC_ENABLED" start="1" description="MDEC enabled. Fractional divider not used." />
+      </BitField>
+      <BitField start="14" size="1" name="MOD_PD" description="Sigma-Delta modulator power-down">
+        <Enum name="ENABLED" start="0" description="Enabled. Sigma-Delta modulator enabled" />
+        <Enum name="DISABLED" start="1" description="Disabled. Sigma-Delta modulator powered down" />
+      </BitField>
+      <BitField start="15" size="9" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x034" size="4" name="PLL0AUDIO_MDIV" access="Read/Write" description="PLL0AUDIO M-divider register" reset_value="0x05F85B6A" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="17" name="MDEC" description="Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x038" size="4" name="PLL0AUDIO_NP_DIV" access="Read/Write" description="PLL0AUDIO N/P-divider register" reset_value="0x000B1002" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="PDEC" description="Decoded P-divider coefficient value" />
+      <BitField start="7" size="5" name="RESERVED" description="Reserved" />
+      <BitField start="12" size="10" name="NDEC" description="Decoded N-divider coefficient value" />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x03C" size="4" name="PLL0AUDIO_FRAC" access="Read/Write" description="PLL0AUDIO fractional divider register" reset_value="0x00200000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="22" name="PLLFRACT_CTRL" description="PLL fractional divider control word" />
+      <BitField start="22" size="10" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x040" size="4" name="PLL1_STAT" access="ReadOnly" description="PLL1 status register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LOCK" description="PLL1 lock indicator" />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x044" size="4" name="PLL1_CTRL" access="Read/Write" description="PLL1 control register" reset_value="0x01000003" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="PLL1 power down">
+        <Enum name="PLL1_ENABLED" start="0" description="PLL1 enabled" />
+        <Enum name="PLL1_POWERED_DOWN" start="1" description="PLL1 powered down" />
+      </BitField>
+      <BitField start="1" size="1" name="BYPASS" description="Input clock bypass control">
+        <Enum name="NORMAL" start="0" description="Normal. CCO clock sent to post-dividers. Use for normal operation." />
+        <Enum name="INPUT_CLOCK" start="1" description="Input clock. PLL1 input clock sent to post-dividers (default)." />
+      </BitField>
+      <BitField start="2" size="1" name="RESERVED" description="Reserved. Do not write one to this bit." />
+      <BitField start="3" size="3" name="RESERVED" description="Reserved. Do not write one to these bits." />
+      <BitField start="6" size="1" name="FBSEL" description="PLL feedback select.">
+        <Enum name="CCO_OUT" start="0" description="CCO out. CCO output is used as feedback divider input clock." />
+        <Enum name="PLL_OUT" start="1" description="PLL out. PLL output clock (clkout) is used as feedback divider input clock. Use for normal operation." />
+      </BitField>
+      <BitField start="7" size="1" name="DIRECT" description="PLL direct CCO output">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="8" size="2" name="PSEL" description="Post-divider division ratio P. The value applied is 2xP.">
+        <Enum name="1" start="0x0" description="1" />
+        <Enum name="PEQ2" start="0x1" description="2 (default)" />
+        <Enum name="PEQ4" start="0x2" description="4" />
+        <Enum name="8" start="0x3" description="8" />
+      </BitField>
+      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="2" name="NSEL" description="Pre-divider division ratio N">
+        <Enum name="1" start="0x0" description="1" />
+        <Enum name="NEQ2" start="0x1" description="2" />
+        <Enum name="NEQ3" start="0x2" description="3 (default)" />
+        <Enum name="4" start="0x3" description="4" />
+      </BitField>
+      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="8" name="MSEL" description="Feedback-divider division ratio (M) 00000000 = 1 00000001 = 2  ... 11111111 = 256" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="RESERVED" start="0x05" description="Reserved" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
+        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
+        <Enum name="RESERVED" start="0x09" description="Reserved" />
+        <Enum name="RESERVED" start="0x0A" description="Reserved" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x048" size="4" name="IDIVA_CTRL" access="Read/Write" description="Integer divider A control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Integer divider A power down">
+        <Enum name="ENABLED" start="0" description="Enabled. IDIVA enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="IDIV" description="Integer divider A divider values  (1/(IDIV + 1))">
+        <Enum name="DIV1" start="0x0" description="1 (default)" />
+        <Enum name="DIV2" start="0x1" description="2" />
+        <Enum name="DIV3" start="0x2" description="3" />
+        <Enum name="DIV4" start="0x3" description="4" />
+      </BitField>
+      <BitField start="4" size="7" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
+        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x04C" size="4" name="IDIVB_CTRL" access="Read/Write" description="Integer divider B control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Integer divider power down">
+        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
+      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x050" size="4" name="IDIVC_CTRL" access="Read/Write" description="Integer divider C control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Integer divider power down">
+        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
+      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x054" size="4" name="IDIVD_CTRL" access="Read/Write" description="Integer divider D control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Integer divider power down">
+        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="4" name="IDIV" description="Integer divider B, C, D divider values (1/(IDIV + 1)) 0000 = 1 (default) 0001 = 2  ... 1111 = 16" />
+      <BitField start="6" size="5" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x058" size="4" name="IDIVE_CTRL" access="Read/Write" description="Integer divider E control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Integer divider power down">
+        <Enum name="ENABLED" start="0" description="Enabled. IDIV enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="8" name="IDIV" description="Integer divider E divider values  (1/(IDIV + 1)) 00000000 = 1 (default) 00000001 = 2  ... 111111111 = 256" />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x05C" size="4" name="BASE_SAFE_CLK" access="ReadOnly" description="Output stage 0 control register for base clock BASE_SAFE_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x060" size="4" name="BASE_USB0_CLK" access="Read/Write" description="Output stage 1 control register for base clock BASE_USB0_CLK" reset_value="0x07000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
+        <Enum name="PLL0USB" start="0x07" description="PLL0USB (default)" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x064" size="4" name="BASE_PERIPH_CLK" access="Read/Write" description="Output stage 2 control register for base clock BASE_PERIPH_CLK" reset_value="0x07000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x068" size="4" name="BASE_USB1_CLK" access="Read/Write" description="Output stage 3 control register for base clock BASE_USB1_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="ENABLED" start="0" description="Enabled. Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="Power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0USB" start="0x07" description="PLL0USB" />
+        <Enum name="PLL0AUDIO" start="0x08" description="PLL0AUDIO" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x06C" size="4" name="BASE_M4_CLK" access="Read/Write" description="Output stage BASE_M4_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x070" size="4" name="BASE_SPIFI_CLK" access="Read/Write" description="Output stage BASE_SPIFI_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x074" size="4" name="BASE_SPI_CLK" access="Read/Write" description="Output stage BASE_SPI_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x078" size="4" name="BASE_PHY_RX_CLK" access="Read/Write" description="Output stage BASE_PHY_RX_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x07C" size="4" name="BASE_PHY_TX_CLK" access="Read/Write" description="Output stage BASE_PHY_TX_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080" size="4" name="BASE_APB1_CLK" access="Read/Write" description="Output stage BASE_APB1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x084" size="4" name="BASE_APB3_CLK" access="Read/Write" description="Output stage BASE_APB3_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x088" size="4" name="BASE_LCD_CLK" access="Read/Write" description="Output stage BASE_LCD_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x090" size="4" name="BASE_SDIO_CLK" access="Read/Write" description="Output stage BASE_SDIO_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x094" size="4" name="BASE_SSP0_CLK" access="Read/Write" description="Output stage BASE_SSP0_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x098" size="4" name="BASE_SSP1_CLK" access="Read/Write" description="Output stage BASE_SSP1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x09C" size="4" name="BASE_UART0_CLK" access="Read/Write" description="Output stage BASE_UART0_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0A0" size="4" name="BASE_UART1_CLK" access="Read/Write" description="Output stage BASE_UART1_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0A4" size="4" name="BASE_UART2_CLK" access="Read/Write" description="Output stage BASE_UART2_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0A8" size="4" name="BASE_UART3_CLK" access="Read/Write" description="Output stage BASE_UART3_CLK control register" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="DISABLED" start="0" description="Disabled. Autoblocking disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock source selection. All other values are reserved.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0AC" size="4" name="BASE_OUT_CLK" access="Read/Write" description="Output stage 20 control register for base clock BASE_OUT_CLK" reset_value="0x01000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
+        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="RESERVED" start="0x05" description="Reserved" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="PLL0_FOR_USB" start="0x07" description="PLL0 (for USB)" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0C0" size="4" name="BASE_AUDIO_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_AUDIO_CLK" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
+        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="RESERVED" start="0x05" description="Reserved" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="RESERVED" start="0x07" description="Reserved" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0C4" size="4" name="BASE_CGU_OUT0_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_CGU_OUT0_CLK" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
+        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="RESERVED" start="0x05" description="Reserved" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="RESERVED" start="0x07" description="Reserved" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0C8" size="4" name="BASE_CGU_OUT1_CLK" access="Read/Write" description="Output stage 25 control register for base clock BASE_CGU_OUT1_CLK" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="PD" description="Output stage power down">
+        <Enum name="OUTPUT_STAGE_ENABLED" start="0" description="Output stage enabled (default)" />
+        <Enum name="POWER_DOWN" start="1" description="power-down" />
+      </BitField>
+      <BitField start="1" size="10" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="AUTOBLOCK" description="Block clock automatically during frequency change">
+        <Enum name="AUTOBLOCKING_DISABLE" start="0" description="Autoblocking disabled" />
+        <Enum name="AUTOBLOCKING_ENABLED" start="1" description="Autoblocking enabled" />
+      </BitField>
+      <BitField start="12" size="12" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="5" name="CLK_SEL" description="Clock-source selection.">
+        <Enum name="32_KHZ_OSCILLATOR" start="0x00" description="32 kHz oscillator" />
+        <Enum name="IRC_DEFAULT" start="0x01" description="IRC (default)" />
+        <Enum name="ENET_RX_CLK" start="0x02" description="ENET_RX_CLK" />
+        <Enum name="ENET_TX_CLK" start="0x03" description="ENET_TX_CLK" />
+        <Enum name="GP_CLKIN" start="0x04" description="GP_CLKIN" />
+        <Enum name="RESERVED" start="0x05" description="Reserved" />
+        <Enum name="CRYSTAL_OSCILLATOR" start="0x06" description="Crystal oscillator" />
+        <Enum name="RESERVED" start="0x07" description="Reserved" />
+        <Enum name="PLL0_FOR_AUDIO" start="0x08" description="PLL0 (for audio)" />
+        <Enum name="PLL1" start="0x09" description="PLL1" />
+        <Enum name="IDIVA" start="0x0C" description="IDIVA" />
+        <Enum name="IDIVB" start="0x0D" description="IDIVB" />
+        <Enum name="IDIVC" start="0x0E" description="IDIVC" />
+        <Enum name="IDIVD" start="0x0F" description="IDIVD" />
+        <Enum name="IDIVE" start="0x10" description="IDIVE" />
+      </BitField>
+      <BitField start="29" size="3" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CCU1" start="0x40051000" description="Clock Control Unit (CCU)">
+    <Register start="+0x000" size="4" name="PM" access="Read/Write" description="CCU1 power mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Initiate power-down mode">
+        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
+        <Enum name="CLOCKS_WITH_WAKE_UP_" start="1" description="Clocks with wake-up mode enabled (W = 1) are disabled." />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="BASE_STAT" access="ReadOnly" description="CCU1 base clocks status register" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="BASE_APB3_CLK_IND" description="Base clock indicator for BASE_APB3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="1" size="1" name="BASE_APB1_CLK_IND" description="Base clock indicator for BASE_APB1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="2" size="1" name="BASE_SPIFI_CLK_IND" description="Base clock indicator for BASE_SPIFI_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="3" size="1" name="BASE_M3_CLK_IND" description="Base clock indicator for BASE_M3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="7" size="1" name="BASE_USB0_CLK_IND" description="Base clock indicator for BASE_USB0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="8" size="1" name="BASE_USB1_CLK_IND" description="Base clock indicator for BASE_USB1_CLK 0 = All branch clocks switched off. 1 = at least one branch clock running." />
+      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x100" size="4" name="CLK_APB3_BUS_CFG" access="Read/Write" description="CLK_APB3_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0108" size="4" name="CLK_APB3_I2C1_CFG" access="Read/Write" description="CLK_APB3_I2C1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0110" size="4" name="CLK_APB3_DAC_CFG" access="Read/Write" description="CLK_APB3_DAC clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0118" size="4" name="CLK_APB3_ADC0_CFG" access="Read/Write" description="CLK_APB3_ADC0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0120" size="4" name="CLK_APB3_ADC1_CFG" access="Read/Write" description="CLK_APB3_ADC1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0128" size="4" name="CLK_APB3_CAN0_CFG" access="Read/Write" description="CLK_APB3_CAN0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200" size="4" name="CLK_APB1_BUS_CFG" access="Read/Write" description="CLK_APB1_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0208" size="4" name="CLK_APB1_MOTOCONPWM_CFG" access="Read/Write" description="CLK_APB1_MOTOCONPWM clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0210" size="4" name="CLK_APB1_I2C0_CFG" access="Read/Write" description="CLK_ABP1_I2C0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0218" size="4" name="CLK_APB1_I2S_CFG" access="Read/Write" description="CLK_APB1_I2S clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0220" size="4" name="CLK_APB1_CAN1_CFG" access="Read/Write" description="CLK_APB1_CAN1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300" size="4" name="CLK_SPIFI_CFG" access="Read/Write" description="CLK_SPIFI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x400" size="4" name="CLK_M4_BUS_CFG" access="Read/Write" description="CLK_M4_BUS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0408" size="4" name="CLK_M4_SPIFI_CFG" access="Read/Write" description="CLK_M4_SPIFI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0410" size="4" name="CLK_M4_GPIO_CFG" access="Read/Write" description="CLK_M4_GPIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0418" size="4" name="CLK_M4_LCD_CFG" access="Read/Write" description="CLK_M4_LCD clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0420" size="4" name="CLK_M4_ETHERNET_CFG" access="Read/Write" description="CLK_M4_ETHERNET clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0428" size="4" name="CLK_M4_USB0_CFG" access="Read/Write" description="CLK_M4_USB0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0430" size="4" name="CLK_M4_EMC_CFG" access="Read/Write" description="CLK_M4_EMC clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0438" size="4" name="CLK_M4_SDIO_CFG" access="Read/Write" description="CLK_M4_SDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0440" size="4" name="CLK_M4_DMA_CFG" access="Read/Write" description="CLK_M4_DMA clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0448" size="4" name="CLK_M4_M4CORE_CFG" access="Read/Write" description="CLK_M4_M4CORE clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0468" size="4" name="CLK_M4_SCT_CFG" access="Read/Write" description="CLK_M4_SCT clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0470" size="4" name="CLK_M4_USB1_CFG" access="Read/Write" description="CLK_M4_USB1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0478" size="4" name="CLK_M4_EMCDIV_CFG" access="Read/Write" description="CLK_M4_EMCDIV clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="5" size="3" name="DIV" description="Clock divider value">
+        <Enum name="DIVIDEBY1" start="0x0" description="No division. Divide by 1." />
+        <Enum name="DIVIDEBY2" start="0x1" description="Divide by 2." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0480" size="4" name="CLK_M4_FLASHA_CFG" access="Read/Write" description="CLK_M4_FLASHA clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0488" size="4" name="CLK_M4_FLASHB_CFG" access="Read/Write" description="CLK_M4_FLASHB clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0490" size="4" name="CLK_M4_M0APP_CFG" access="Read/Write" description="CLK_M0APP_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0498" size="4" name="CLK_M4_ADCHS_CFG" access="Read/Write" description="CLK_ADCHS_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x04A0" size="4" name="CLK_M4_EEPROM_CFG" access="Read/Write" description="CLK_EEPROM_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500" size="4" name="CLK_M4_WWDT_CFG" access="Read/Write" description="CLK_M4_WWDT clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0508" size="4" name="CLK_M4_USART0_CFG" access="Read/Write" description="CLK_M4_USART0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0510" size="4" name="CLK_M4_UART1_CFG" access="Read/Write" description="CLK_M4_UART1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0518" size="4" name="CLK_M4_SSP0_CFG" access="Read/Write" description="CLK_M4_SSP0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0520" size="4" name="CLK_M4_TIMER0_CFG" access="Read/Write" description="CLK_M4_TIMER0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0528" size="4" name="CLK_M4_TIMER1_CFG" access="Read/Write" description="CLK_M4_TIMER1clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0530" size="4" name="CLK_M4_SCU_CFG" access="Read/Write" description="CLK_M4_SCU clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0538" size="4" name="CLK_M4_CREG_CFG" access="Read/Write" description="CLK_M4_CREGclock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600" size="4" name="CLK_M4_RITIMER_CFG" access="Read/Write" description="CLK_M4_RITIMER clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0608" size="4" name="CLK_M4_USART2_CFG" access="Read/Write" description="CLK_M4_USART2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0610" size="4" name="CLK_M4_USART3_CFG" access="Read/Write" description="CLK_M4_USART3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0618" size="4" name="CLK_M4_TIMER2_CFG" access="Read/Write" description="CLK_M4_TIMER2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0620" size="4" name="CLK_M4_TIMER3_CFG" access="Read/Write" description="CLK_M4_TIMER3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0628" size="4" name="CLK_M4_SSP1_CFG" access="Read/Write" description="CLK_M4_SSP1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0630" size="4" name="CLK_M4_QEI_CFG" access="Read/Write" description="CLK_M4_QEIclock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0700" size="4" name="CLK_PERIPH_BUS_CFG" access="Read/Write" description="CLK_PERIPH_BUS_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0710" size="4" name="CLK_PERIPH_CORE_CFG" access="Read/Write" description="CLK_PERIPH_CORE_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0718" size="4" name="CLK_PERIPH_SGPIO_CFG" access="Read/Write" description="CLK_PERIPH_SGPIO_CFG clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x800" size="4" name="CLK_USB0_CFG" access="Read/Write" description="CLK_M4_USB0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
+        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x900" size="4" name="CLK_USB1_CFG" access="Read/Write" description="CLK_USB1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
+        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xA00" size="4" name="CLK_SPI_CFG" access="Read/Write" description="CLK_SPI clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
+        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xB00" size="4" name="CLK_ADCHS_CFG" access="Read/Write" description="CLK_ADCHS clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="AUTO_IS_DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="AUTO_IS_ENABLED_" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="WAKE_UP_IS_DISABLED_" start="0" description="Wake-up is disabled." />
+        <Enum name="WAKE_UP_IS_ENABLED_" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x104" size="4" name="CLK_APB3_BUS_STAT" access="ReadOnly" description="CLK_APB3_BUS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x010C" size="4" name="CLK_APB3_I2C1_STAT" access="ReadOnly" description="CLK_APB3_I2C1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0114" size="4" name="CLK_APB3_DAC_STAT" access="ReadOnly" description="CLK_APB3_DAC clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x011C" size="4" name="CLK_APB3_ADC0_STAT" access="ReadOnly" description="CLK_APB3_ADC0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0124" size="4" name="CLK_APB3_ADC1_STAT" access="ReadOnly" description="CLK_APB3_ADC1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x012C" size="4" name="CLK_APB3_CAN0_STAT" access="ReadOnly" description="CLK_APB3_CAN0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x204" size="4" name="CLK_APB1_BUS_STAT" access="ReadOnly" description="CLK_APB1_BUS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020C" size="4" name="CLK_APB1_MOTOCONPWM_STAT" access="ReadOnly" description="CLK_APB1_MOTOCONPWM clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0214" size="4" name="CLK_APB1_I2C0_STAT" access="ReadOnly" description="CLK_APB1_I2C0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x021C" size="4" name="CLK_APB1_I2S_STAT" access="ReadOnly" description="CLK_APB1_I2S clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0224" size="4" name="CLK_APB1_CAN1_STAT" access="ReadOnly" description="CLK_APB1_CAN1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x304" size="4" name="CLK_SPIFI_STAT" access="ReadOnly" description="CLK_APB1_SPIFI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x404" size="4" name="CLK_M4_BUS_STAT" access="ReadOnly" description="CLK_M4_BUSclock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x040C" size="4" name="CLK_M4_SPIFI_STAT" access="ReadOnly" description="CLK_M4_SPIFI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0414" size="4" name="CLK_M4_GPIO_STAT" access="ReadOnly" description="CLK_M4_GPIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x041C" size="4" name="CLK_M4_LCD_STAT" access="ReadOnly" description="CLK_M4_LCD clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0424" size="4" name="CLK_M4_ETHERNET_STAT" access="ReadOnly" description="CLK_M4_ETHERNET clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x042C" size="4" name="CLK_M4_USB0_STAT" access="ReadOnly" description="CLK_M4_USB0  clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0434" size="4" name="CLK_M4_EMC_STAT" access="ReadOnly" description="CLK_M4_EMC clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x043C" size="4" name="CLK_M4_SDIO_STAT" access="ReadOnly" description="CLK_M4_SDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0444" size="4" name="CLK_M4_DMA_STAT" access="ReadOnly" description="CLK_M4_DMA clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x044C" size="4" name="CLK_M4_M4CORE_STAT" access="ReadOnly" description="CLK_M4_M3CORE clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x046C" size="4" name="CLK_M4_SCT_STAT" access="ReadOnly" description="CLK_M4_SCT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0474" size="4" name="CLK_M4_USB1_STAT" access="ReadOnly" description="CLK_M4_USB1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x047C" size="4" name="CLK_M4_EMCDIV_STAT" access="ReadOnly" description="CLK_M4_EMCDIV clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0484" size="4" name="CLK_M4_FLASHA_STAT" access="ReadOnly" description="CLK_M4_FLASHA clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x048C" size="4" name="CLK_M4_FLASHB_STAT" access="ReadOnly" description="CLK_M4_FLASHB clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0494" size="4" name="CLK_M4_M0APP_STAT" access="ReadOnly" description="CLK_M4_MOAPP clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x049C" size="4" name="CLK_M4_ADCHS_STAT" access="ReadOnly" description="CLK_M4_ADCHS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x04A4" size="4" name="CLK_M4_EEPROM_STAT" access="ReadOnly" description="CLK_M4_EEPROM clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504" size="4" name="CLK_M4_WWDT_STAT" access="ReadOnly" description="CLK_M4_WWDT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x050C" size="4" name="CLK_M4_USART0_STAT" access="ReadOnly" description="CLK_M4_USART0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0514" size="4" name="CLK_M4_UART1_STAT" access="ReadOnly" description="CLK_M4_UART1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x051C" size="4" name="CLK_M4_SSP0_STAT" access="ReadOnly" description="CLK_M4_SSP0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0524" size="4" name="CLK_M4_TIMER0_STAT" access="ReadOnly" description="CLK_M4_TIMER0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x052C" size="4" name="CLK_M4_TIMER1_STAT" access="ReadOnly" description="CLK_M4_TIMER1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0534" size="4" name="CLK_M4_SCU_STAT" access="ReadOnly" description="CLK_SCU_XXX clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x053C" size="4" name="CLK_M4_CREG_STAT" access="ReadOnly" description="CLK_M4_CREG clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x604" size="4" name="CLK_M4_RITIMER_STAT" access="ReadOnly" description="CLK_M4_RITIMER clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x060C" size="4" name="CLK_M4_USART2_STAT" access="ReadOnly" description="CLK_M4_USART2 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0614" size="4" name="CLK_M4_USART3_STAT" access="ReadOnly" description="CLK_M4_USART3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x061C" size="4" name="CLK_M4_TIMER2_STAT" access="ReadOnly" description="CLK_M4_TIMER2 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0624" size="4" name="CLK_M4_TIMER3_STAT" access="ReadOnly" description="CLK_M4_TIMER3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x062C" size="4" name="CLK_M4_SSP1_STAT" access="ReadOnly" description="CLK_M4_SSP1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0634" size="4" name="CLK_M4_QEI_STAT" access="ReadOnly" description="CLK_M4_QEI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0704" size="4" name="CLK_PERIPH_BUS_STAT" access="ReadOnly" description="CLK_PERIPH_BUS_STAT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0714" size="4" name="CLK_PERIPH_CORE_STAT" access="ReadOnly" description="CLK_CORE_BUS_STAT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x071C" size="4" name="CLK_PERIPH_SGPIO_STAT" access="ReadOnly" description="CLK_CORE_SGPIO_STAT clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x804" size="4" name="CLK_USB0_STAT" access="ReadOnly" description="CLK_USB0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x904" size="4" name="CLK_USB1_STAT" access="ReadOnly" description="CLK_USB1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xA04" size="4" name="CLK_SPI_STAT" access="ReadOnly" description="CLK_SPI clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xB04" size="4" name="CLK_ADCHS_STAT" access="ReadOnly" description="CLK_ADCHS clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CCU2" start="0x40052000" description="Clock Control Unit (CCU2)">
+    <Register start="+0x000" size="4" name="PM" access="Read/Write" description="Power mode register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD" description="Initiate power-down mode">
+        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
+        <Enum name="CLOCKS_WITH_WAKE_UP_" start="1" description="Clocks with wake-up mode enabled (W = 1) are disabled." />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="BASE_STAT" access="ReadOnly" description="CCU base clocks status register" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="1" size="1" name="BASE_UART3_CLK" description="Base clock indicator for BASE_UART3_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="2" size="1" name="BASE_UART2_CLK" description="Base clock indicator for BASE_UART2_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="3" size="1" name="BASE_UART1_CLK" description="Base clock indicator for BASE_UART1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="4" size="1" name="BASE_UART0_CLK" description="Base clock indicator for BASE_UART0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="5" size="1" name="BASE_SSP1_CLK" description="Base clock indicator for BASE_SSP1_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="6" size="1" name="BASE_SSP0_CLK" description="Base clock indicator for BASE_SSP0_CLK 0 = All branch clocks switched off. 1 = At least one branch clock running." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x100" size="4" name="CLK_AUDIO_CFG" access="Read/Write" description="CLK_AUDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x200" size="4" name="CLK_APB2_USART3_CFG" access="Read/Write" description="CLK_APB2_USART3 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x300" size="4" name="CLK_APB2_USART2_CFG" access="Read/Write" description="CLK_APB2_USART2 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x400" size="4" name="CLK_APB0_UART1_BUS_CFG" access="Read/Write" description="CLK_APB2_UART1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x500" size="4" name="CLK_APB0_USART0_CFG" access="Read/Write" description="CLK_APB2_USART0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x700" size="4" name="CLK_APB0_SSP0_CFG" access="Read/Write" description="CLK_APB0_SSP0 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x600" size="4" name="CLK_APB2_SSP1_CFG" access="Read/Write" description="CLK_APB2_SSP1 clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x800" size="4" name="CLK_SDIO_CFG" access="Read/Write" description="CLK_SDIO clock configuration register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable">
+        <Enum name="DISABLED" start="0" description="Clock is disabled." />
+        <Enum name="ENABLED" start="1" description="Clock is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable">
+        <Enum name="DISABLED_" start="0" description="Auto is disabled." />
+        <Enum name="ENABLED" start="1" description="Auto is enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable">
+        <Enum name="DISABLED" start="0" description="Wake-up is disabled." />
+        <Enum name="ENABLED" start="1" description="Wake-up is enabled." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x104" size="4" name="CLK_AUDIO_STAT" access="ReadOnly" description="CLK_AUDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x204" size="4" name="CLK_APB2_USART3_STAT" access="ReadOnly" description="CLK_APB2_USART3 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0304" size="4" name="CLK_APB2_USART2_STAT" access="ReadOnly" description="CLK_APB2_USART clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0404" size="4" name="CLK_APB0_UART1_STAT" access="ReadOnly" description="CLK_APB0_UART1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0504" size="4" name="CLK_APB0_USART0_STAT" access="ReadOnly" description="CLK_APB0_USART0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0604" size="4" name="CLK_APB2_SSP1_STAT" access="ReadOnly" description="CLK_APB2_SSP1 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0704" size="4" name="CLK_APB0_SSP0_STAT" access="ReadOnly" description="CLK_APB0_SSP0 clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0804" size="4" name="CLK_SDIO_STAT" access="ReadOnly" description="CLK_SDIO clock status register" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN" description="Run enable status 0 = clock is disabled. 1 = clock is enabled." />
+      <BitField start="1" size="1" name="AUTO" description="Auto (AHB disable mechanism) enable status 0 = Auto is disabled. 1 = Auto is enabled." />
+      <BitField start="2" size="1" name="WAKEUP" description="Wake-up mechanism enable status 0 = Wake-up is disabled. 1 = Wake-up is enabled." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RGU" start="0x40053000" description="Reset Generation Unit (RGU)">
+    <Register start="+0x100" size="4" name="RESET_CTRL0" access="WriteOnly" description="Reset control register 0" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CORE_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="1" size="1" name="PERIPH_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles." />
+      <BitField start="2" size="1" name="MASTER_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="1" name="WWDT_RST" description="Writing a one to this bit has no effect." />
+      <BitField start="5" size="1" name="CREG_RST" description="Writing a one to this bit has no effect." />
+      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="BUS_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Do not use during normal operation" />
+      <BitField start="9" size="1" name="SCU_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="12" size="1" name="M0_SUB_RST" description="Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software." />
+      <BitField start="13" size="1" name="M4_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="14" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="15" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="LCD_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="17" size="1" name="USB0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="18" size="1" name="USB1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="19" size="1" name="DMA_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="20" size="1" name="SDIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="21" size="1" name="EMC_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="22" size="1" name="ETHERNET_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="25" size="1" name="FLASHA_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="27" size="1" name="EEPROM_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="28" size="1" name="GPIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="29" size="1" name="FLASHB_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x104" size="4" name="RESET_CTRL1" access="WriteOnly" description="Reset control register 1" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="TIMER0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="1" size="1" name="TIMER1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="2" size="1" name="TIMER2_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="3" size="1" name="TIMER3_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="4" size="1" name="RITIMER_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="5" size="1" name="SCT_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="6" size="1" name="MOTOCONPWM_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="7" size="1" name="QEI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="8" size="1" name="ADC0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="9" size="1" name="ADC1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="10" size="1" name="DAC_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="12" size="1" name="UART0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="13" size="1" name="UART1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="14" size="1" name="UART2_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="15" size="1" name="UART3_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="16" size="1" name="I2C0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="17" size="1" name="I2C1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="18" size="1" name="SSP0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="19" size="1" name="SSP1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="20" size="1" name="I2S_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="21" size="1" name="SPIFI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="22" size="1" name="CAN1_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="23" size="1" name="CAN0_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="24" size="1" name="M0APP_RST" description="Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software." />
+      <BitField start="25" size="1" name="SGPIO_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="26" size="1" name="SPI_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="27" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="28" size="1" name="ADCHS_RST" description="Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle." />
+      <BitField start="29" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x110" size="4" name="RESET_STATUS0" access="Read/Write" description="Reset status register 0" reset_value="0x55550050" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="2" size="2" name="PERIPH_RST" description="Status of the PERIPH_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="4" size="2" name="MASTER_RST" description="Status of the MASTER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator - this reset is self-clearing 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="6" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="WWDT_RST" description="Status of the WWDT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved" />
+      <BitField start="10" size="2" name="CREG_RST" description="Status of the CREG_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reserved" />
+      <BitField start="12" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="2" name="BUS_RST" description="Status of the BUS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="18" size="2" name="SCU_RST" description="Status of the SCU_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="20" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="2" name="M0SUB_RST" description="Status of the M0SUB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="26" size="2" name="M4_RST" description="Status of the M4_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x114" size="4" name="RESET_STATUS1" access="Read/Write" description="Reset status register 1" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="LCD_RST" description="Status of the LCD_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="2" size="2" name="USB0_RST" description="Status of the USB0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="4" size="2" name="USB1_RST" description="Status of the USB1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="6" size="2" name="DMA_RST" description="Status of the DMA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="8" size="2" name="SDIO_RST" description="Status of the SDIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="10" size="2" name="EMC_RST" description="Status of the EMC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="12" size="2" name="ETHERNET_RST" description="Status of the ETHERNET_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="14" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="18" size="2" name="FLASHA_RST" description="Status of the FLASHA_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="20" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="22" size="2" name="EEPROM_RST" description="Status of the EEPROM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="24" size="2" name="GPIO_RST" description="Status of the GPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="26" size="2" name="FLASHB_RST" description="Status of the FLASHB_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x118" size="4" name="RESET_STATUS2" access="Read/Write" description="Reset status register 2" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="TIMER0_RST" description="Status of the TIMER0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="2" size="2" name="TIMER1_RST" description="Status of the TIMER1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="4" size="2" name="TIMER2_RST" description="Status of the TIMER2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="6" size="2" name="TIMER3_RST" description="Status of the TIMER3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="8" size="2" name="RITIMER_RST" description="Status of the RITIMER_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="10" size="2" name="SCT_RST" description="Status of the SCT_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="12" size="2" name="MOTOCONPWM_RST" description="Status of the MOTOCONPWM_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="14" size="2" name="QEI_RST" description="Status of the QEI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="16" size="2" name="ADC0_RST" description="Status of the ADC0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="18" size="2" name="ADC1_RST" description="Status of the ADC1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="20" size="2" name="DAC_RST" description="Status of the DAC_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="2" name="UART0_RST" description="Status of the UART0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="26" size="2" name="UART1_RST" description="Status of the UART1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="28" size="2" name="UART2_RST" description="Status of the UART2_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="30" size="2" name="UART3_RST" description="Status of the UART3_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+    </Register>
+    <Register start="+0x11C" size="4" name="RESET_STATUS3" access="Read/Write" description="Reset status register 3" reset_value="0x55555555" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="I2C0_RST" description="Status of the I2C0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="2" size="2" name="I2C1_RST" description="Status of the I2C1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="4" size="2" name="SSP0_RST" description="Status of the SSP0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="6" size="2" name="SSP1_RST" description="Status of the SSP1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="8" size="2" name="I2S_RST" description="Status of the I2S_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="10" size="2" name="SPIFI_RST" description="Status of the SPIFI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="12" size="2" name="CAN1_RST" description="Status of the CAN1_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="14" size="2" name="CAN0_RST" description="Status of the CAN0_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="16" size="2" name="M0APP_RST" description="Status of the M0APP_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="18" size="2" name="SGPIO_RST" description="Status of the SGPIO_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="20" size="2" name="SPI_RST" description="Status of the SPI_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="22" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="2" name="ADCHS_RST" description="Status of the ADCHS_RST reset generator output 00 = No reset activated 01 = Reset output activated by input to the reset generator 10 = Reserved 11 = Reset output activated by software write to RESET_CTRL register" />
+      <BitField start="26" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="28" size="2" name="RESERVED" description="Reserved" />
+      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x150" size="4" name="RESET_ACTIVE_STATUS0" access="ReadOnly" description="Reset active status register 0" reset_value="0xFFFFEFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CORE_RST" description="Current status of the CORE_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="1" size="1" name="PERIPH_RST" description="Current status of the PERIPH_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="2" size="1" name="MASTER_RST" description="Current status of the MASTER_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="1" name="WWDT_RST" description="Current status of the WWDT_RS 0 = Reset asserted 1 = No reset" />
+      <BitField start="5" size="1" name="CREG_RST" description="Current status of the CREG_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="6" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="BUS_RST" description="Current status of the BUS_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="9" size="1" name="SCU_RST" description="Current status of the SCU_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="10" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="11" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="12" size="1" name="M0SUB_RST" description="Current status of the M0SUB_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="13" size="1" name="M4_RST" description="Current status of the M4_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="14" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="15" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="1" name="LCD_RST" description="Current status of the LCD_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="17" size="1" name="USB0_RST" description="Current status of the USB0_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="18" size="1" name="USB1_RST" description="Current status of the USB1_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="19" size="1" name="DMA_RST" description="Current status of the DMA_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="20" size="1" name="SDIO_RST" description="Current status of the SDIO_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="21" size="1" name="EMC_RST" description="Current status of the EMC_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="22" size="1" name="ETHERNET_RST" description="Current status of the ETHERNET_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="23" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="24" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="25" size="1" name="FLASHA_RST" description="Current status of the FLASHA_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="26" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="27" size="1" name="EEPROM_RST" description="Current status of the EEPROM_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="28" size="1" name="GPIO_RST" description="Current status of the GPIO_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="29" size="1" name="FLASHB_RST" description="Current status of the FLASHB_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="30" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x154" size="4" name="RESET_ACTIVE_STATUS1" access="ReadOnly" description="Reset active status register 1" reset_value="0xFEFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TIMER0_RST" description="Current status of the TIMER0_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="1" size="1" name="TIMER1_RST" description="Current status of the TIMER1_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="2" size="1" name="TIMER2_RST" description="Current status of the TIMER2_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="3" size="1" name="TIMER3_RST" description="Current status of the TIMER3_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="4" size="1" name="RITIMER_RST" description="Current status of the RITIMER_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="5" size="1" name="SCT_RST" description="Current status of the SCT_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="6" size="1" name="MOTOCONPWM_RST" description="Current status of the MOTOCONPWM_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="7" size="1" name="QEI_RST" description="Current status of the QEI_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="8" size="1" name="ADC0_RST" description="Current status of the ADC0_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="9" size="1" name="ADC1_RST" description="Current status of the ADC1_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="10" size="1" name="DAC_RST" description="Current status of the DAC_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="11" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="12" size="1" name="UART0_RST" description="Current status of the UART0_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="13" size="1" name="UART1_RST" description="Current status of the UART1_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="14" size="1" name="UART2_RST" description="Current status of the UART2_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="15" size="1" name="UART3_RST" description="Current status of the UART3_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="16" size="1" name="I2C0_RST" description="Current status of the I2C0_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="17" size="1" name="I2C1_RST" description="Current status of the I2C1_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="18" size="1" name="SSP0_RST" description="Current status of the SSP0_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="19" size="1" name="SSP1_RST" description="Current status of the SSP1_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="20" size="1" name="I2S_RST" description="Current status of the I2S_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="21" size="1" name="SPIFI_RST" description="Current status of the SPIFI_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="22" size="1" name="CAN1_RST" description="Current status of the CAN1_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="23" size="1" name="CAN0_RST" description="Current status of the CAN0_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="24" size="1" name="M0APP_RST" description="Current status of the M0APP_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="25" size="1" name="SGPIO_RST" description="Current status of the SGPIO_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="26" size="1" name="SPI_RST" description="Current status of the SPI_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="27" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="28" size="1" name="ADCHS_RST" description="Current status of the ADCHS_RST 0 = Reset asserted 1 = No reset" />
+      <BitField start="29" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="30" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="31" size="1" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x404" size="4" name="RESET_EXT_STAT1" access="Read/Write" description="Reset external status register 1 for PERIPH_RST" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="1" size="1" name="CORE_RESET" description="Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x408" size="4" name="RESET_EXT_STAT2" access="Read/Write" description="Reset external status register 2 for MASTER_RST" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x414" size="4" name="RESET_EXT_STAT5" access="Read/Write" description="Reset external status register 5 for CREG_RST" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="1" size="1" name="CORE_RESET" description="Reset activated by CORE_RST output. Write 0 to clear. 0 = Reset not activated 1 = Reset activated" />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x420" size="4" name="RESET_EXT_STAT8" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0424" size="4" name="RESET_EXT_STAT9" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x430" size="4" name="RESET_EXT_STAT12" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x434" size="4" name="RESET_EXT_STAT13" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x440" size="4" name="RESET_EXT_STAT16" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0444" size="4" name="RESET_EXT_STAT17" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0448" size="4" name="RESET_EXT_STAT18" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x044C" size="4" name="RESET_EXT_STAT19" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0450" size="4" name="RESET_EXT_STAT20" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0454" size="4" name="RESET_EXT_STAT21" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0458" size="4" name="RESET_EXT_STAT22" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0464" size="4" name="RESET_EXT_STAT25" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x046C" size="4" name="RESET_EXT_STAT27" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x470" size="4" name="RESET_EXT_STAT28" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0474" size="4" name="RESET_EXT_STAT29" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="3" size="1" name="MASTER_RESET" description="Reset activated by MASTER_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x480" size="4" name="RESET_EXT_STAT32" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0484" size="4" name="RESET_EXT_STAT33" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0488" size="4" name="RESET_EXT_STAT34" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x048C" size="4" name="RESET_EXT_STAT35" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0490" size="4" name="RESET_EXT_STAT36" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0494" size="4" name="RESET_EXT_STAT37" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x0498" size="4" name="RESET_EXT_STAT38" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x049C" size="4" name="RESET_EXT_STAT39" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04A0" size="4" name="RESET_EXT_STAT40" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04A4" size="4" name="RESET_EXT_STAT41" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04A8" size="4" name="RESET_EXT_STAT42" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04B0" size="4" name="RESET_EXT_STAT44" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04B4" size="4" name="RESET_EXT_STAT45" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04B8" size="4" name="RESET_EXT_STAT46" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04BC" size="4" name="RESET_EXT_STAT47" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04C0" size="4" name="RESET_EXT_STAT48" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04C4" size="4" name="RESET_EXT_STAT49" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04C8" size="4" name="RESET_EXT_STAT50" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04CC" size="4" name="RESET_EXT_STAT51" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04D0" size="4" name="RESET_EXT_STAT52" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04D4" size="4" name="RESET_EXT_STAT53" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04D8" size="4" name="RESET_EXT_STAT54" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04DC" size="4" name="RESET_EXT_STAT55" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04E0" size="4" name="RESET_EXT_STAT56" access="Read/Write" description="Reset external status register" reset_value="0x8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04E4" size="4" name="RESET_EXT_STAT57" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04E8" size="4" name="RESET_EXT_STAT58" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+    <Register start="+0x04F0" size="4" name="RESET_EXT_STAT60" access="Read/Write" description="Reset external status register" reset_value="0x4" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+      <BitField start="2" size="1" name="PERIPHERAL_RESET" description="Reset activated by PERIPHERAL_RST output. Write 0 to clear. 0 = Reset not activated  1 = Reset activated" />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. Do not modify; read as logic 0." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="WWDT" start="0x40080000" description="Windowed Watchdog timer (WWDT) ">
+    <Register start="+0x000" size="4" name="MOD" access="Read/Write" description="Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="WDEN" description="Watchdog enable bit. This bit is Set Only.">
+        <Enum name="WWDTSTOPPED" start="0" description="The watchdog timer is stopped." />
+        <Enum name="WWDTRUN" start="1" description="The watchdog timer is running." />
+      </BitField>
+      <BitField start="1" size="1" name="WDRESET" description="Watchdog reset enable bit. This bit is Set Only.">
+        <Enum name="WWDTINT" start="0" description="A watchdog time-out will not cause a chip reset." />
+        <Enum name="WWDTRESET" start="1" description="A watchdog time-out will cause a chip reset." />
+      </BitField>
+      <BitField start="2" size="1" name="WDTOF" description="Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. This flag is cleared by software writing a 0 to this bit." />
+      <BitField start="3" size="1" name="WDINT" description="Watchdog interrupt flag. Set when the timer reaches the value in the WARNINT register. Cleared by software by writing a 1 to this bit." />
+      <BitField start="4" size="1" name="WDPROTECT" description="Watchdog update mode. This bit is Set Only.">
+        <Enum name="NO_LOCK" start="0" description="The watchdog time-out value (WDTC) can be changed at any time." />
+        <Enum name="LOCK" start="1" description="The watchdog time-out value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW." />
+      </BitField>
+      <BitField start="5" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="TC" access="Read/Write" description="Watchdog timer constant register. This register determines the time-out value." reset_value="0xFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="WDTC" description="Watchdog time-out value." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="FEED" access="WriteOnly" description="Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="Feed" description="Feed value should be 0xAA followed by 0x55." />
+    </Register>
+    <Register start="+0x00C" size="4" name="TV" access="ReadOnly" description="Watchdog timer value register. This register reads out the current value of the Watchdog timer." reset_value="0xFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="Count" description="Counter timer value." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="WARNINT" access="Read/Write" description="Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="WDWARNINT" description="Watchdog warning interrupt compare value." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="WINDOW" access="Read/Write" description="Watchdog timer window register. This register contains the Watchdog window value." reset_value="0x00FFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="24" name="WDWINDOW" description="Watchdog window value." />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART0" start="0x40081000" description="USART0_2_3">
+    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
+      </BitField>
+      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
+        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
+        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
+      </BitField>
+      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
+        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
+        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
+        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
+        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
+        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
+      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
+      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
+        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
+      </BitField>
+      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
+        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
+        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
+        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
+        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
+        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
+        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
+        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
+        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
+      </BitField>
+      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
+        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
+        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
+      </BitField>
+      <BitField start="3" size="1" name="PE" description="Parity Enable">
+        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
+        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
+      </BitField>
+      <BitField start="4" size="2" name="PS" description="Parity Select.">
+        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
+        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
+        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
+        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
+      </BitField>
+      <BitField start="6" size="1" name="BC" description="Break Control.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
+      </BitField>
+      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
+        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
+        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
+      </BitField>
+      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
+      </BitField>
+      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
+      </BitField>
+      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
+      </BitField>
+      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
+      </BitField>
+      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
+        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
+        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
+      </BitField>
+      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
+        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
+        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
+      </BitField>
+      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
+        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
+        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
+      </BitField>
+      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
+        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
+        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
+        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
+        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
+      </BitField>
+      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
+        <Enum name="MODE_0" start="0" description="Mode 0." />
+        <Enum name="MODE_1" start="1" description="Mode 1." />
+      </BitField>
+      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
+        <Enum name="NO_RESTART" start="0" description="No restart." />
+        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
+        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
+        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
+        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
+        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
+      </BitField>
+      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
+        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
+      </BitField>
+      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
+      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
+      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
+      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
+        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
+        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
+      </BitField>
+      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
+        <Enum name="T_EQ_0" start="0" description="T = 0" />
+        <Enum name="T_EQ_1" start="1" description="T = 1" />
+      </BitField>
+      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
+      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
+        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
+        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="AADEN" description="AAD enable">
+        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
+      </BitField>
+      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
+        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
+        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
+        <Enum name="DISABLED" start="0" description="Disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
+        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
+        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
+      </BitField>
+      <BitField start="2" size="1" name="FES" description="Edge sampling.">
+        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
+        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
+      </BitField>
+      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
+        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
+        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
+      </BitField>
+      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
+        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
+        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
+      </BitField>
+      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
+        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
+        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
+      </BitField>
+      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
+        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
+        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART2" start="0x400C1000" description="USART0_2_3">
+    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
+      </BitField>
+      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
+        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
+        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
+      </BitField>
+      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
+        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
+        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
+        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
+        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
+        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
+      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
+      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
+        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
+      </BitField>
+      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
+        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
+        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
+        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
+        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
+        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
+        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
+        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
+        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
+      </BitField>
+      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
+        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
+        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
+      </BitField>
+      <BitField start="3" size="1" name="PE" description="Parity Enable">
+        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
+        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
+      </BitField>
+      <BitField start="4" size="2" name="PS" description="Parity Select.">
+        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
+        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
+        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
+        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
+      </BitField>
+      <BitField start="6" size="1" name="BC" description="Break Control.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
+      </BitField>
+      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
+        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
+        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
+      </BitField>
+      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
+      </BitField>
+      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
+      </BitField>
+      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
+      </BitField>
+      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
+      </BitField>
+      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
+        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
+        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
+      </BitField>
+      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
+        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
+        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
+      </BitField>
+      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
+        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
+        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
+      </BitField>
+      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
+        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
+        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
+        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
+        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
+      </BitField>
+      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
+        <Enum name="MODE_0" start="0" description="Mode 0." />
+        <Enum name="MODE_1" start="1" description="Mode 1." />
+      </BitField>
+      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
+        <Enum name="NO_RESTART" start="0" description="No restart." />
+        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
+        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
+        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
+        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
+        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
+      </BitField>
+      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
+        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
+      </BitField>
+      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
+      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
+      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
+      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
+        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
+        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
+      </BitField>
+      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
+        <Enum name="T_EQ_0" start="0" description="T = 0" />
+        <Enum name="T_EQ_1" start="1" description="T = 1" />
+      </BitField>
+      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
+      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
+        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
+        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="AADEN" description="AAD enable">
+        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
+      </BitField>
+      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
+        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
+        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
+        <Enum name="DISABLED" start="0" description="Disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
+        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
+        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
+      </BitField>
+      <BitField start="2" size="1" name="FES" description="Edge sampling.">
+        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
+        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
+      </BitField>
+      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
+        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
+        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
+      </BitField>
+      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
+        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
+        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
+      </BitField>
+      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
+        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
+        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
+      </BitField>
+      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
+        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
+        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART3" start="0x400C2000" description="USART0_2_3">
+    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="RBR" description="Receiver buffer. The USART Receiver Buffer Register contains the oldest received byte in the USART RX FIFO." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x000" size="4" name="THR" access="None" description="Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0)." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the USART Transmit Holding Register causes the data to be stored in the USART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLLSB" description="Divisor latch LSB. The USART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the USART." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1)." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLMSB" description="Divisor latch MSB.  The USART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the USART." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0)." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for USART. It also controls the Character Receive Time-out interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for USART. The status of this interrupt can be read from LSR[5].">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupt." />
+      </BitField>
+      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the USART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="1" name="ABEOINTEN" description="Enables the end of auto-baud interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTEN" description="Enables the auto-baud time-out interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status.  Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
+        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
+        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
+      </BitField>
+      <BitField start="1" size="3" name="INTID" description="Interrupt identification.  IER[3:1] identifies an interrupt corresponding to the USART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
+        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
+        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
+        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
+        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
+        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
+      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt.  True if auto-baud has finished successfully and interrupt is enabled." />
+      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt.  True if auto-baud has timed out and interrupt is enabled." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls USART FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FIFOEN" description="FIFO Enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. USART FIFOs are disabled. Must not be used in the application." />
+        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both USART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper USART operation. Any transition on this bit will automatically clear the USART FIFOs." />
+      </BitField>
+      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in USART Rx FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of USART FIFOs." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in USART TX FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode." />
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver USART FIFO characters must be written before an interrupt is activated.">
+        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
+        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
+        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
+        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
+        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
+        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
+        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
+        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
+      </BitField>
+      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
+        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
+        <Enum name="2_STOP_BITS_1" start="1" description="2 stop bits (1.5 if LCR[1:0]=00)." />
+      </BitField>
+      <BitField start="3" size="1" name="PE" description="Parity Enable">
+        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
+        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
+      </BitField>
+      <BitField start="4" size="2" name="PS" description="Parity Select.">
+        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
+        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
+        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
+        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
+      </BitField>
+      <BitField start="6" size="1" name="BC" description="Break Control.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin USART TXD is forced to logic 0 when LCR[6] is active high." />
+      </BitField>
+      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the USART RBR FIFO is empty.">
+        <Enum name="EMPTY" start="0" description="Empty. RBR is empty." />
+        <Enum name="DATA" start="1" description="Data. RBR contains valid data." />
+      </BitField>
+      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when USART RSR has a new character assembled and the USART RBR FIFO is full. In this case, the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
+      </BitField>
+      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
+      </BitField>
+      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
+      </BitField>
+      <BitField start="4" size="1" name="BI" description="Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the USART RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Break interrupt status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Break interrupt status is active." />
+      </BitField>
+      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty USART THR and is cleared on a THR write.">
+        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
+        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
+      </BitField>
+      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
+        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
+        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
+      </BitField>
+      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO.">
+        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no USART RX errors or FCR[0]=0." />
+        <Enum name="ERROR" start="1" description="Error. USART RBR contains at least one USART RX error." />
+      </BitField>
+      <BitField start="8" size="1" name="TXERR" description="Error in transmitted character.   A NACK response is given by the receiver in Smart card T=0 mode. This bit is cleared when the LSR register is read.">
+        <Enum name="NO_ERROR" start="0" description="No error. No error (normal default condition)." />
+        <Enum name="NACK" start="1" description="NACK. A NACK response is received during Smart card T=0 operation." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. Eight-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="PAD" description="Scratch pad. A readable, writable byte." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="START" description="Start bit. This bit is automatically cleared after auto-baud completion.">
+        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
+        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
+      </BitField>
+      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
+        <Enum name="MODE_0" start="0" description="Mode 0." />
+        <Enum name="MODE_1" start="1" description="Mode 1." />
+      </BitField>
+      <BitField start="2" size="1" name="AUTORESTART" description="Restart bit.">
+        <Enum name="NO_RESTART" start="0" description="No restart." />
+        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next USART Rx falling edge)" />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
+        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
+        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="ICR" access="Read/Write" description="IrDA control register (USART3 only)" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="IRDAEN" description="IrDA mode enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. IrDA mode on USART3 is disabled, USART3 acts as a standard USART." />
+        <Enum name="ENABLED" start="1" description="Enabled. IrDA mode on USART3 is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="IRDAINV" description="Serial input direction.">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted. The serial input is not inverted." />
+        <Enum name="INVERTED" start="1" description="Inverted. The serial input is inverted. This has no effect on the serial output." />
+      </BitField>
+      <BitField start="2" size="1" name="FIXPULSEEN" description="IrDA fixed pulse width mode.">
+        <Enum name="DISABLED" start="0" description="Disabled. IrDA fixed pulse width mode disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. IrDA fixed pulse width mode enabled." />
+      </BitField>
+      <BitField start="3" size="3" name="PULSEDIV" description="Configures the pulse when FixPulseEn = 1. See Table 885 for details." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DIVADDVAL" description="Baud rate generation pre-scaler divisor value.  If this field is 0, fractional baud rate generator will not impact the USART baud rate." />
+      <BitField start="4" size="4" name="MULVAL" description="Baud rate pre-scaler multiplier value.  This field must be greater or equal 1 for USART to operate properly, regardless of whether the fractional baud rate generator is used or not." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="OSR" access="Read/Write" description="Oversampling Register. Controls the degree of oversampling during each bit time." reset_value="0xF0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="1" size="3" name="OSFRAC" description="Fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ..., 111 = 0.875)" />
+      <BitField start="4" size="4" name="OSINT" description="Integer part of the oversampling ratio, minus 1. The reset values equate to the normal operating mode of 16 input clocks per bit time." />
+      <BitField start="8" size="7" name="FDINT" description="In Smart Card mode, these bits act as a more-significant extension of the OSint field, allowing an oversampling ratio up to 2048 as required by ISO7816-3. In Smart Card mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372." />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x040" size="4" name="HDEN" access="Read/Write" description="Half-duplex enable Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="HDEN" description="Half-duplex mode enable">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable half-duplex mode." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable half-duplex mode." />
+      </BitField>
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x048" size="4" name="SCICTRL" access="Read/Write" description="Smart card interface control register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SCIEN" description="Smart Card Interface Enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Smart card interface disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. synchronous half duplex smart card interface is enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="NACKDIS" description="NACK response disable. Only applicable in T=0.">
+        <Enum name="ENABLED" start="0" description="Enabled. A NACK response is enabled." />
+        <Enum name="DISABLED" start="1" description="Disabled. A NACK response is inhibited." />
+      </BitField>
+      <BitField start="2" size="1" name="PROTSEL" description="Protocol selection as defined in the ISO7816-3 standard.">
+        <Enum name="T_EQ_0" start="0" description="T = 0" />
+        <Enum name="T_EQ_1" start="1" description="T = 1" />
+      </BitField>
+      <BitField start="3" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="5" size="3" name="TXRETRY" description="Maximum number of retransmissions in case of a negative acknowledge (protocol T=0). When the retry counter is exceeded, the USART will be locked until the FIFO is cleared. A TX error interrupt is generated when enabled." />
+      <BitField start="8" size="8" name="GUARDTIME" description="Extra guard time. No extra guard time (0x0) results in a standard guard time as defined in ISO 7816-3, depending on the protocol type. A guard time of 0xFF indicates a minimal guard time as defined for the selected protocol." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="NMMEN" description="NMM enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="RXDIS" description="Receiver enable.">
+        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
+        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="AADEN" description="AAD enable">
+        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="DCTRL" description="Direction control for DIR pin.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
+      </BitField>
+      <BitField start="5" size="1" name="OINV" description="Direction control pin polarity. This bit reverses the polarity of the direction control signal on the DIR pin.">
+        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
+        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLY" description="Contains the direction control delay value. This register works in conjunction with an 8-bit counter." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x058" size="4" name="SYNCCTRL" access="Read/Write" description="Synchronous mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SYNC" description="Enables synchronous mode.">
+        <Enum name="DISABLED" start="0" description="Disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="CSRC" description="Clock source select.">
+        <Enum name="SLAVE_MODE" start="0" description="Slave mode. Synchronous slave mode (SCLK in)" />
+        <Enum name="MASTER_MODE" start="1" description="Master mode. Synchronous master mode (SCLK out)" />
+      </BitField>
+      <BitField start="2" size="1" name="FES" description="Edge sampling.">
+        <Enum name="RISING" start="0" description="Rising. RxD is sampled on the rising edge of SCLK." />
+        <Enum name="FALLING" start="1" description="Falling. RxD is sampled on the falling edge of SCLK." />
+      </BitField>
+      <BitField start="3" size="1" name="TSBYPASS" description="Transmit synchronization bypass in synchronous slave mode.">
+        <Enum name="SYNCHRONIZED" start="0" description="Synchronized. The input clock is synchronized prior to being used in clock edge detection logic." />
+        <Enum name="NOT_SYNCHRONIZED" start="1" description="Not synchronized. The input clock is not synchronized prior to being used in clock edge detection logic. This allows for a high er input clock rate at the expense of potential metastability." />
+      </BitField>
+      <BitField start="4" size="1" name="CSCEN" description="Continuous master clock enable (used only when CSRC is 1)">
+        <Enum name="ON_CHARACTER" start="0" description="On character. SCLK cycles only when characters are being sent on TxD." />
+        <Enum name="CONTINUOUSLY" start="1" description="Continuously. SCLK runs continuously (characters can be received on RxD independently from transmission on TxD)." />
+      </BitField>
+      <BitField start="5" size="1" name="SSSDIS" description="Start/stop bits">
+        <Enum name="SEND" start="0" description="Send. Send start and stop bits as in other modes." />
+        <Enum name="DO_NOT_SEND" start="1" description="Do not send. Do not send start/stop bits." />
+      </BitField>
+      <BitField start="6" size="1" name="CCCLR" description="Continuous clock clear">
+        <Enum name="SOFTWARE" start="0" description="Software. CSCEN is under software control." />
+        <Enum name="HARDWARE" start="1" description="Hardware. Hardware clears CSCEN after each character is received." />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off USART transmitter for use with software flow control." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART1" start="0x40082000" description="UART1">
+    <Register start="+0x000" size="4" name="RBR" access="None" description="Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="RBR" description="Receiver Buffer. Contains the oldest received byte in the UART1 RX FIFO." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x000" size="4" name="THR" access="WriteOnly" description="Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="8" name="THR" description="Transmit Holding Register. Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
+    </Register>
+    <Register start="+0x000" size="4" name="DLL" access="Read/Write" description="Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)" reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLLSB" description="Divisor Latch LSB.  The UART1 Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART1." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="DLM" access="Read/Write" description="Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1)" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLMSB" description="Divisor Latch MSB.  The UART1 Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART1." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="IER" access="Read/Write" description="Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0)" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RBRIE" description="RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the RDA interrupts." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the RDA interrupts." />
+      </BitField>
+      <BitField start="1" size="1" name="THREIE" description="THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the THRE interrupts." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the THRE interrupts." />
+      </BitField>
+      <BitField start="2" size="1" name="RXIE" description="RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the RX line status interrupts." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the RX line status interrupts." />
+      </BitField>
+      <BitField start="3" size="1" name="MSIE" description="Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the modem interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the modem interrupt." />
+      </BitField>
+      <BitField start="4" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="7" size="1" name="CTSIE" description="CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable the CTS interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable the CTS interrupt." />
+      </BitField>
+      <BitField start="8" size="1" name="ABEOIE" description="Enables the end of auto-baud interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable end of auto-baud Interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable end of auto-baud Interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOIE" description="Enables the auto-baud time-out interrupt.">
+        <Enum name="DISABLE" start="0" description="Disable. Disable auto-baud time-out Interrupt." />
+        <Enum name="ENABLE" start="1" description="Enable. Enable auto-baud time-out Interrupt." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="IIR" access="ReadOnly" description="Interrupt ID Register. Identifies which interrupt(s) are pending." reset_value="0x01" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INTSTATUS" description="Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].">
+        <Enum name="INTERRUPT_PENDING" start="0" description="Interrupt pending. At least one interrupt is pending." />
+        <Enum name="NOT_PENDING" start="1" description="Not pending. No interrupt is pending." />
+      </BitField>
+      <BitField start="1" size="3" name="INTID" description="Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).">
+        <Enum name="RLS" start="0x3" description="RLS. Priority 1 (highest). (Highest) Receive Line Status (RLS)." />
+        <Enum name="RDA" start="0x2" description="RDA. Priority 2 - Receive Data Available (RDA)." />
+        <Enum name="CTI" start="0x6" description="CTI. Priority 2 - Character Time-out Indicator (CTI)." />
+        <Enum name="THRE" start="0x1" description="THRE. Priority 3 - THRE Interrupt." />
+        <Enum name="RESERVED" start="0x0" description="Reserved. Priority 4 (lowest) - Reserved." />
+      </BitField>
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="FIFOENABLE" description="Copies of FCR[0]." />
+      <BitField start="8" size="1" name="ABEOINT" description="End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled." />
+      <BitField start="9" size="1" name="ABTOINT" description="Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled." />
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="FCR" access="WriteOnly" description="FIFO Control Register. Controls UART1 FIFO usage and modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FIFOEN" description="FIFO enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Must not be used in the application." />
+        <Enum name="ENABLED" start="1" description="Enabled. Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs." />
+      </BitField>
+      <BitField start="1" size="1" name="RXFIFORES" description="RX FIFO Reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of UART1 FIFOs." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="2" size="1" name="TXFIFORES" description="TX FIFO Reset.">
+        <Enum name="NO_EFFECT" start="0" description="No effect. No impact on either of UART1 FIFOs." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing." />
+      </BitField>
+      <BitField start="3" size="1" name="DMAMODE" description="DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 39.6.6.1." />
+      <BitField start="4" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="2" name="RXTRIGLVL" description="RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.">
+        <Enum name="LEVEL_0" start="0x0" description="Level 0. Trigger level 0 (1 character or 0x01)." />
+        <Enum name="LEVEL_1" start="0x1" description="Level 1. Trigger level 1 (4 characters or 0x04)." />
+        <Enum name="LEVEL_2" start="0x2" description="Level 2. Trigger level 2 (8 characters or 0x08)." />
+        <Enum name="LEVEL_3" start="0x3" description="Level 3. Trigger level 3 (14 characters or 0x0E)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits." />
+    </Register>
+    <Register start="+0x00C" size="4" name="LCR" access="Read/Write" description="Line Control Register. Contains controls for frame formatting and break generation." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WLS" description="Word Length Select.">
+        <Enum name="5_BIT_CHARACTER_LENG" start="0x0" description="5-bit character length." />
+        <Enum name="6_BIT_CHARACTER_LENG" start="0x1" description="6-bit character length." />
+        <Enum name="7_BIT_CHARACTER_LENG" start="0x2" description="7-bit character length." />
+        <Enum name="8_BIT_CHARACTER_LENG" start="0x3" description="8-bit character length." />
+      </BitField>
+      <BitField start="2" size="1" name="SBS" description="Stop Bit Select.">
+        <Enum name="1_STOP_BIT" start="0" description="1 stop bit." />
+        <Enum name="2_STOP_BITS" start="1" description="2 stop bits. (1.5 if LCR[1:0]=00)." />
+      </BitField>
+      <BitField start="3" size="1" name="PE" description="Parity Enable.">
+        <Enum name="DISABLE_PARITY_GENER" start="0" description="Disable parity generation and checking." />
+        <Enum name="ENABLE_PARITY_GENERA" start="1" description="Enable parity generation and checking." />
+      </BitField>
+      <BitField start="4" size="2" name="PS" description="Parity Select.">
+        <Enum name="ODD_PARITY" start="0x0" description="Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd." />
+        <Enum name="EVEN_PARITY" start="0x1" description="Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even." />
+        <Enum name="FORCE_HIGH" start="0x2" description="Force HIGH. Forced 1 stick parity." />
+        <Enum name="FORCE_LOW" start="0x3" description="Force LOW. Forced 0 stick parity." />
+      </BitField>
+      <BitField start="6" size="1" name="BC" description="Break Control.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable break transmission." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high." />
+      </BitField>
+      <BitField start="7" size="1" name="DLAB" description="Divisor Latch Access Bit (DLAB)">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable access to Divisor Latches." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable access to Divisor Latches." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="MCR" access="Read/Write" description="Modem Control Register. Contains controls for flow control handshaking and loopback mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DTRCTRL" description="DTR Control.  Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active." />
+      <BitField start="1" size="1" name="RTSCTRL" description="RTS Control.  Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active." />
+      <BitField start="2" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="4" size="1" name="LMS" description="Loopback Mode Select.  The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable modem loopback mode." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable modem loopback mode." />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="1" name="RTSEN" description="RTS enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable auto-rts flow control." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable auto-rts flow control." />
+      </BitField>
+      <BitField start="7" size="1" name="CTSEN" description="CTS enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable auto-cts flow control." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable auto-cts flow control." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="LSR" access="None" description="Line Status Register. Contains flags for transmit and receive status, including line errors." reset_value="0x60" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RDR" description="Receiver Data Ready.  LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.">
+        <Enum name="EMPTY" start="0" description="Empty. The UART1 receiver FIFO is empty." />
+        <Enum name="DATA" start="1" description="Data. The UART1 receiver FIFO is not empty." />
+      </BitField>
+      <BitField start="1" size="1" name="OE" description="Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Overrun error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Overrun error status is active." />
+      </BitField>
+      <BitField start="2" size="1" name="PE" description="Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Parity error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Parity error status is active." />
+      </BitField>
+      <BitField start="3" size="1" name="FE" description="Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.">
+        <Enum name="INACTIVE" start="0" description="Inactive. Framing error status is inactive." />
+        <Enum name="ACTIVE" start="1" description="Active. Framing error status is active." />
+      </BitField>
+      <BitField start="4" size="1" name="BI" description="Break Interrupt.  When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.">
+        <Enum name="BREAK_INTERRUPT_STAT" start="0" description="Break interrupt status is inactive." />
+        <Enum name="BREAK_INTERRUPT_STAT" start="1" description="Break interrupt status is active." />
+      </BitField>
+      <BitField start="5" size="1" name="THRE" description="Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.">
+        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR contains valid data." />
+        <Enum name="EMPTY" start="1" description="Empty. THR is empty." />
+      </BitField>
+      <BitField start="6" size="1" name="TEMT" description="Transmitter Empty.  TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.">
+        <Enum name="NOT_EMPTY" start="0" description="Not empty. THR and/or the TSR contains valid data." />
+        <Enum name="EMPTY" start="1" description="Empty. THR and the TSR are empty." />
+      </BitField>
+      <BitField start="7" size="1" name="RXFE" description="Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.">
+        <Enum name="NO_ERROR" start="0" description="No error. RBR contains no UART1 RX errors or FCR[0]=0." />
+        <Enum name="ERROR" start="1" description="Error. UART1 RBR contains at least one UART1 RX error." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="MSR" access="None" description="Modem Status Register. Contains handshake signal status flags." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DCTS" description="Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.">
+        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, CTS." />
+        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, CTS." />
+      </BitField>
+      <BitField start="1" size="1" name="DDSR" description="Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.">
+        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, DSR." />
+        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, DSR." />
+      </BitField>
+      <BitField start="2" size="1" name="TERI" description="Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.">
+        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, RI." />
+        <Enum name="RISING" start="1" description="Rising. Low-to-high transition detected on RI." />
+      </BitField>
+      <BitField start="3" size="1" name="DDCD" description="Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.">
+        <Enum name="NO_CHANGE" start="0" description="No change. No change detected on modem input, DCD." />
+        <Enum name="STATE_CHANGE" start="1" description="State change. State change detected on modem input, DCD." />
+      </BitField>
+      <BitField start="4" size="1" name="CTS" description="Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode." />
+      <BitField start="5" size="1" name="DSR" description="Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode." />
+      <BitField start="6" size="1" name="RI" description="Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode." />
+      <BitField start="7" size="1" name="DCD" description="Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="SCR" access="Read/Write" description="Scratch Pad Register. 8-bit temporary storage for software." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Pad" description="Scratch pad. A readable, writable byte." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, the value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="ACR" access="Read/Write" description="Auto-baud Control Register. Contains controls for the auto-baud feature." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="START" description="Auto-baud start bit. This bit is automatically cleared after auto-baud completion.">
+        <Enum name="STOP" start="0" description="Stop. Auto-baud stop (auto-baud is not running)." />
+        <Enum name="START" start="1" description="Start. Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion." />
+      </BitField>
+      <BitField start="1" size="1" name="MODE" description="Auto-baud mode select bit.">
+        <Enum name="MODE_0" start="0" description="Mode 0." />
+        <Enum name="MODE_1" start="1" description="Mode 1." />
+      </BitField>
+      <BitField start="2" size="1" name="AUTORESTART" description="Auto-baud restart bit.">
+        <Enum name="NO_RESTART" start="0" description="No restart" />
+        <Enum name="RESTART" start="1" description="Restart. Restart in case of time-out (counter restarts at next UART1 Rx falling edge)" />
+      </BitField>
+      <BitField start="3" size="5" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="1" name="ABEOINTCLR" description="End of auto-baud interrupt clear bit (write-only).">
+        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="9" size="1" name="ABTOINTCLR" description="Auto-baud time-out interrupt clear bit (write-only).">
+        <Enum name="NO_EFFECT" start="0" description="No effect. Writing a 0 has no impact." />
+        <Enum name="CLEAR" start="1" description="Clear. Writing a 1 will clear the corresponding interrupt in the IIR." />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="FDR" access="Read/Write" description="Fractional Divider Register. Generates a clock input for the baud rate divider." reset_value="0x10" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DIVADDVAL" description="Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate." />
+      <BitField start="4" size="4" name="MULVAL" description="Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x04C" size="4" name="RS485CTRL" access="Read/Write" description="RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="NMMEN" description="Multidrop mode select.">
+        <Enum name="DISABLED" start="0" description="Disabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the USART to set the parity error and generate an interrupt." />
+      </BitField>
+      <BitField start="1" size="1" name="RXDIS" description="Receive enable.">
+        <Enum name="ENABLED" start="0" description="Enabled. The receiver is enabled." />
+        <Enum name="DISABLED" start="1" description="Disabled.The receiver is disabled." />
+      </BitField>
+      <BitField start="2" size="1" name="AADEN" description="Auto Address Detect enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Auto Address Detect (AAD) is disabled." />
+        <Enum name="ENABLED" start="1" description="Enabled. Auto Address Detect (AAD) is enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="SEL" description="Direction control.">
+        <Enum name="RTS" start="0" description="RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control." />
+        <Enum name="DTR" start="1" description="DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control." />
+      </BitField>
+      <BitField start="4" size="1" name="DCTRL" description="Direction control enable.">
+        <Enum name="DISABLED" start="0" description="Disabled. Disable Auto Direction Control." />
+        <Enum name="ENABLED" start="1" description="Enabled. Enable Auto Direction Control." />
+      </BitField>
+      <BitField start="5" size="1" name="OINV" description="Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.">
+        <Enum name="LOW" start="0" description="Low. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted." />
+        <Enum name="HIGH" start="1" description="High. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x050" size="4" name="RS485ADRMATCH" access="Read/Write" description="RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADRMATCH" description="Contains the address match value." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x054" size="4" name="RS485DLY" access="Read/Write" description="RS-485/EIA-485 direction control delay." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DLY" description="Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x05C" size="4" name="TER" access="Read/Write" description="Transmit Enable Register. Turns off UART transmitter for use with software flow control." reset_value="0x80" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TXEN" description="Transmit enable.  After reset transmission is enabled. When the TXEN bit is de-asserted, no data will be transmitted although data may be pending in the TSR or THR." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SSP0" start="0x40083000" description="SSP0/1">
+    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
+        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
+        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
+        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
+        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
+        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
+        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
+        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
+        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
+        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
+        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
+        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
+        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
+        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
+      </BitField>
+      <BitField start="4" size="2" name="FRF" description="Frame Format.">
+        <Enum name="SPI" start="0x0" description="SPI" />
+        <Enum name="TI" start="0x1" description="TI" />
+        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
+        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
+      </BitField>
+      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
+        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
+        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
+      </BitField>
+      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
+        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
+        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
+      </BitField>
+      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
+        <Enum name="NORMAL" start="0" description="During normal operation." />
+        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
+      </BitField>
+      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
+        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
+        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
+      </BitField>
+      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
+        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
+        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
+      </BitField>
+      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
+      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
+      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
+      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
+      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
+      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
+      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
+      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
+      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
+      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
+      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
+      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
+      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SSP1" start="0x400C5000" description="SSP0/1">
+    <Register start="+0x000" size="4" name="CR0" access="Read/Write" description="Control Register 0. Selects the serial clock rate, bus type, and data size." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DSS" description="Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.">
+        <Enum name="4_BIT_TRANSFER" start="0x3" description="4-bit transfer" />
+        <Enum name="5_BIT_TRANSFER" start="0x4" description="5-bit transfer" />
+        <Enum name="6_BIT_TRANSFER" start="0x5" description="6-bit transfer" />
+        <Enum name="7_BIT_TRANSFER" start="0x6" description="7-bit transfer" />
+        <Enum name="8_BIT_TRANSFER" start="0x7" description="8-bit transfer" />
+        <Enum name="9_BIT_TRANSFER" start="0x8" description="9-bit transfer" />
+        <Enum name="10_BIT_TRANSFER" start="0x9" description="10-bit transfer" />
+        <Enum name="11_BIT_TRANSFER" start="0xA" description="11-bit transfer" />
+        <Enum name="12_BIT_TRANSFER" start="0xB" description="12-bit transfer" />
+        <Enum name="13_BIT_TRANSFER" start="0xC" description="13-bit transfer" />
+        <Enum name="14_BIT_TRANSFER" start="0xD" description="14-bit transfer" />
+        <Enum name="15_BIT_TRANSFER" start="0xE" description="15-bit transfer" />
+        <Enum name="16_BIT_TRANSFER" start="0xF" description="16-bit transfer" />
+      </BitField>
+      <BitField start="4" size="2" name="FRF" description="Frame Format.">
+        <Enum name="SPI" start="0x0" description="SPI" />
+        <Enum name="TI" start="0x1" description="TI" />
+        <Enum name="MICROWIRE" start="0x2" description="Microwire" />
+        <Enum name="THIS_COMBINATION_IS_" start="0x3" description="This combination is not supported and should not be used." />
+      </BitField>
+      <BitField start="6" size="1" name="CPOL" description="Clock Out Polarity. This bit is only used in SPI mode.">
+        <Enum name="BUS_LOW" start="0" description="SSP controller maintains the bus clock low between frames." />
+        <Enum name="BUS_HIGH" start="1" description="SSP controller maintains the bus clock high between frames." />
+      </BitField>
+      <BitField start="7" size="1" name="CPHA" description="Clock Out Phase. This bit is only used in SPI mode.">
+        <Enum name="FIRST_CLOCK" start="0" description="SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line." />
+        <Enum name="SECOND_CLOCK" start="1" description="SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line." />
+      </BitField>
+      <BitField start="8" size="8" name="SCR" description="Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="CR1" access="Read/Write" description="Control Register 1. Selects master/slave and other modes." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="LBM" description="Loop Back Mode.">
+        <Enum name="NORMAL" start="0" description="During normal operation." />
+        <Enum name="OUPTU" start="1" description="Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)." />
+      </BitField>
+      <BitField start="1" size="1" name="SSE" description="SSP Enable.">
+        <Enum name="DISABLED" start="0" description="The SSP controller is disabled." />
+        <Enum name="ENABLED" start="1" description="The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit." />
+      </BitField>
+      <BitField start="2" size="1" name="MS" description="Master/Slave Mode.This bit can only be written when the SSE bit is 0.">
+        <Enum name="MASTER" start="0" description="The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line." />
+        <Enum name="SLAVE" start="1" description="The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines." />
+      </BitField>
+      <BitField start="3" size="1" name="SOD" description="Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO)." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="DR" access="None" description="Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="DATA" description="Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="SR" access="ReadOnly" description="Status Register" reset_value="0x00000003" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TFE" description="Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not." />
+      <BitField start="1" size="1" name="TNF" description="Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not." />
+      <BitField start="2" size="1" name="RNE" description="Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not." />
+      <BitField start="3" size="1" name="RFF" description="Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not." />
+      <BitField start="4" size="1" name="BSY" description="Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty." />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="CPSR" access="Read/Write" description="Clock Prescale Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="CPSDVSR" description="This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="IMSC" access="Read/Write" description="Interrupt Mask Set and Clear Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORIM" description="Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
+      <BitField start="1" size="1" name="RTIM" description="Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXIM" description="Software should set this bit to enable interrupt when the Rx FIFO is at least half full." />
+      <BitField start="3" size="1" name="TXIM" description="Software should set this bit to enable interrupt when the Tx FIFO is at least half empty." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="RIS" access="ReadOnly" description="Raw Interrupt Status Register" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORRIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs." />
+      <BitField start="1" size="1" name="RTRIS" description="This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXRIS" description="This bit is 1 if the Rx FIFO is at least half full." />
+      <BitField start="3" size="1" name="TXRIS" description="This bit is 1 if the Tx FIFO is at least half empty." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="MIS" access="ReadOnly" description="Masked Interrupt Status Register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RORMIS" description="This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled." />
+      <BitField start="1" size="1" name="RTMIS" description="This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1])." />
+      <BitField start="2" size="1" name="RXMIS" description="This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled." />
+      <BitField start="3" size="1" name="TXMIS" description="This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="ICR" access="WriteOnly" description="SSPICR Interrupt Clear Register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="RORIC" description="Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt." />
+      <BitField start="1" size="1" name="RTIC" description="Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1])." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="DMACR" access="Read/Write" description="SSP0 DMA control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RXDMAE" description="Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled." />
+      <BitField start="1" size="1" name="TXDMAE" description="Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled" />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIMER0" start="0x40084000" description="Timer0/1/2/3">
+    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
+      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
+      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
+      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
+      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
+      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
+      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
+      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
+      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TC" description="Timer counter value." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
+    </Register>
+    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
+    </Register>
+    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
+      </BitField>
+      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
+      </BitField>
+      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
+      </BitField>
+      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
+        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
+      </BitField>
+      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
+      </BitField>
+      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
+      </BitField>
+      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
+        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
+      </BitField>
+      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
+      </BitField>
+      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
+      </BitField>
+      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
+        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
+      </BitField>
+      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
+      </BitField>
+      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
+      </BitField>
+      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
+      </BitField>
+      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
+        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
+        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
+      </BitField>
+      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
+        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
+        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
+        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
+        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIMER1" start="0x40085000" description="Timer0/1/2/3">
+    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
+      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
+      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
+      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
+      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
+      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
+      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
+      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
+      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TC" description="Timer counter value." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
+    </Register>
+    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
+    </Register>
+    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
+      </BitField>
+      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
+      </BitField>
+      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
+      </BitField>
+      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
+        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
+      </BitField>
+      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
+      </BitField>
+      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
+      </BitField>
+      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
+        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
+      </BitField>
+      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
+      </BitField>
+      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
+      </BitField>
+      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
+        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
+      </BitField>
+      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
+      </BitField>
+      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
+      </BitField>
+      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
+      </BitField>
+      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
+        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
+        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
+      </BitField>
+      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
+        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
+        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
+        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
+        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIMER2" start="0x400C3000" description="Timer0/1/2/3">
+    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
+      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
+      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
+      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
+      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
+      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
+      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
+      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
+      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TC" description="Timer counter value." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
+    </Register>
+    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
+    </Register>
+    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
+      </BitField>
+      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
+      </BitField>
+      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
+      </BitField>
+      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
+        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
+      </BitField>
+      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
+      </BitField>
+      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
+      </BitField>
+      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
+        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
+      </BitField>
+      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
+      </BitField>
+      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
+      </BitField>
+      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
+        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
+      </BitField>
+      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
+      </BitField>
+      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
+      </BitField>
+      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
+      </BitField>
+      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
+        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
+        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
+      </BitField>
+      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
+        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
+        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
+        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
+        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIMER3" start="0x400C4000" description="Timer0/1/2/3">
+    <Register start="+0x000" size="4" name="IR" access="Read/Write" description="Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0INT" description="Interrupt flag for match channel 0." />
+      <BitField start="1" size="1" name="MR1INT" description="Interrupt flag for match channel 1." />
+      <BitField start="2" size="1" name="MR2INT" description="Interrupt flag for match channel 2." />
+      <BitField start="3" size="1" name="MR3INT" description="Interrupt flag for match channel 3." />
+      <BitField start="4" size="1" name="CR0INT" description="Interrupt flag for capture channel 0 event." />
+      <BitField start="5" size="1" name="CR1INT" description="Interrupt flag for capture channel 1 event." />
+      <BitField start="6" size="1" name="CR2INT" description="Interrupt flag for capture channel 2 event." />
+      <BitField start="7" size="1" name="CR3INT" description="Interrupt flag for capture channel 3 event." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="TCR" access="Read/Write" description="Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CEN" description="When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled." />
+      <BitField start="1" size="1" name="CRST" description="When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero." />
+      <BitField start="2" size="30" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="TC" access="Read/Write" description="Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="TC" description="Timer counter value." />
+    </Register>
+    <Register start="+0x00C" size="4" name="PR" access="Read/Write" description="Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PM" description="Prescale counter maximum value." />
+    </Register>
+    <Register start="+0x010" size="4" name="PC" access="Read/Write" description="Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PC" description="Prescale counter value." />
+    </Register>
+    <Register start="+0x014" size="4" name="MCR" access="Read/Write" description="Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MR0I" description="Interrupt on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled. Interrupt is generated when MR0 matches the value in the TC." />
+      </BitField>
+      <BitField start="1" size="1" name="MR0R" description="Reset on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR0 matches it." />
+      </BitField>
+      <BitField start="2" size="1" name="MR0S" description="Stop on MR0">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC." />
+      </BitField>
+      <BitField start="3" size="1" name="MR1I" description="Interrupt on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled." />
+        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR1 matches the value in the TC." />
+      </BitField>
+      <BitField start="4" size="1" name="MR1R" description="Reset on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="RESET" start="1" description="Reset. TC will be reset if MR1 matches it." />
+      </BitField>
+      <BitField start="5" size="1" name="MR1S" description="Stop on MR1">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC." />
+      </BitField>
+      <BitField start="6" size="1" name="MR2I" description="Interrupt on MR2">
+        <Enum name="DISABLED" start="0" description="Disabled. Interrupt is disabled" />
+        <Enum name="MATCH" start="1" description="Match. Interrupt is generated when MR2 matches the value in the TC." />
+      </BitField>
+      <BitField start="7" size="1" name="MR2R" description="Reset on MR2">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR2 matches it." />
+      </BitField>
+      <BitField start="8" size="1" name="MR2S" description="Stop on MR2.">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC." />
+      </BitField>
+      <BitField start="9" size="1" name="MR3I" description="Interrupt on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. This interrupt is disabled." />
+        <Enum name="INTERRUPT" start="1" description="Interrupt. Interrupt is generated when MR3 matches the value in the TC." />
+      </BitField>
+      <BitField start="10" size="1" name="MR3R" description="Reset on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="MATCH" start="1" description="Match. TC will be reset if MR3 matches it." />
+      </BitField>
+      <BitField start="11" size="1" name="MR3S" description="Stop on MR3">
+        <Enum name="DISABLED" start="0" description="Disabled. Feature disabled." />
+        <Enum name="STOP" start="1" description="Stop. TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="MR0" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="MR1" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="MR2" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x018+12" size="4" name="MR3" access="Read/Write" description="Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MATCH" description="Timer counter match value." />
+    </Register>
+    <Register start="+0x028" size="4" name="CCR" access="Read/Write" description="Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0RE" description="Capture on CAPn.0 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="1" size="1" name="CAP0FE" description="Capture on CAPn.0 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="2" size="1" name="CAP0I" description="Interrupt on CAPn.0 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR0 load due to a CAPn.0 event will generate an interrupt." />
+      </BitField>
+      <BitField start="3" size="1" name="CAP1RE" description="Capture on CAPn.1 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="4" size="1" name="CAP1FE" description="Capture on CAPn.1 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="5" size="1" name="CAP1I" description="Interrupt on CAPn.1 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR1 load due to a CAPn.1 event will generate an interrupt." />
+      </BitField>
+      <BitField start="6" size="1" name="CAP2RE" description="Capture on CAPn.2 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="7" size="1" name="CAP2FE" description="Capture on CAPn.2 falling edge:">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="High to low. A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="8" size="1" name="CAP2I" description="Interrupt on CAPn.2 event">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR2 load due to a CAPn.2 event will generate an interrupt." />
+      </BitField>
+      <BitField start="9" size="1" name="CAP3RE" description="Capture on CAPn.3 rising edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOW_TO_HIGH" start="1" description="Low to high. A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="10" size="1" name="CAP3FE" description="High to low. Capture on CAPn.3 falling edge">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="HIGH_TO_LOW" start="1" description="A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loaded with the contents of TC." />
+      </BitField>
+      <BitField start="11" size="1" name="CAP3I" description="Interrupt on CAPn.3 event:">
+        <Enum name="DISABLED" start="0" description="Disabled. This feature is disabled." />
+        <Enum name="LOAD" start="1" description="Load. A CR3 load due to a CAPn.3 event will generate an interrupt." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C+0" size="4" name="CR0" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+4" size="4" name="CR1" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+8" size="4" name="CR2" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x02C+12" size="4" name="CR3" access="ReadOnly" description="Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Timer counter capture value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="EMR" access="Read/Write" description="External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively)." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EM0" description="External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="1" size="1" name="EM1" description="External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="2" size="1" name="EM2" description="External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="3" size="1" name="EM3" description="External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high)." />
+      <BitField start="4" size="2" name="EMC0" description="External Match Control 0. Determines the functionality of External Match 0.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="6" size="2" name="EMC1" description="External Match Control 1. Determines the functionality of External Match 1.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="8" size="2" name="EMC2" description="External Match Control 2. Determines the functionality of External Match 2.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="10" size="2" name="EMC3" description="External Match Control 3. Determines the functionality of External Match 3.">
+        <Enum name="NOP" start="0x0" description="Do Nothing." />
+        <Enum name="CLEAR" start="0x1" description="Clear. Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out)." />
+        <Enum name="SET" start="0x2" description="Set. Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out)." />
+        <Enum name="TOGGLE" start="0x3" description="Toggle. Toggle the corresponding External Match bit/output." />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x070" size="4" name="CTCR" access="Read/Write" description="Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="CTMODE" description="Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.">
+        <Enum name="TIMER_MODE" start="0x0" description="Timer Mode. Counts every rising PCLK edge" />
+        <Enum name="COUNTER_MODE_RISING" start="0x1" description="Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_FALLING" start="0x2" description="Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2." />
+        <Enum name="COUNTER_MODE_EDGES" start="0x3" description="Counter Mode edges. TC is incremented on both edges on the CAP input selected by bits 3:2." />
+      </BitField>
+      <BitField start="2" size="2" name="CINSEL" description="Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.">
+        <Enum name="CAP0" start="0x0" description="CAP0. CAPn.0 for TIMERn" />
+        <Enum name="CAP1" start="0x1" description="CAP1. CAPn.1 for TIMERn" />
+        <Enum name="CAP2" start="0x2" description="CAP2. CAPn.2 for TIMERn" />
+        <Enum name="CAP3" start="0x3" description="CAP3. CAPn.3 for TIMERn" />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SCU" start="0x40086000" description="System Control Unit (SCU) I/O configuration ">
+    <Register start="+0x000+0" size="4" name="SFSP0_0" access="Read/Write" description="Pin configuration register for pins P0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x000+4" size="4" name="SFSP0_1" access="Read/Write" description="Pin configuration register for pins P0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+0" size="4" name="SFSP1_0" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+4" size="4" name="SFSP1_1" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+8" size="4" name="SFSP1_2" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+12" size="4" name="SFSP1_3" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+16" size="4" name="SFSP1_4" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+20" size="4" name="SFSP1_5" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+24" size="4" name="SFSP1_6" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+28" size="4" name="SFSP1_7" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+32" size="4" name="SFSP1_8" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+36" size="4" name="SFSP1_9" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+40" size="4" name="SFSP1_10" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+44" size="4" name="SFSP1_11" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+48" size="4" name="SFSP1_12" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+52" size="4" name="SFSP1_13" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+56" size="4" name="SFSP1_14" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+60" size="4" name="SFSP1_15" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x080+64" size="4" name="SFSP1_16" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0C4" size="4" name="SFSP1_17" access="Read/Write" description="Pin configuration register for pins P1_17" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
+        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0C8+0" size="4" name="SFSP1_18" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0C8+4" size="4" name="SFSP1_19" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0C8+8" size="4" name="SFSP1_20" access="Read/Write" description="Pin configuration register for pins P1" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x100+0" size="4" name="SFSP2_0" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x100+4" size="4" name="SFSP2_1" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x100+8" size="4" name="SFSP2_2" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x10C+0" size="4" name="SFSP2_3" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
+        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x10C+4" size="4" name="SFSP2_4" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
+        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x10C+8" size="4" name="SFSP2_5" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
+        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x118+0" size="4" name="SFSP2_6" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x118+4" size="4" name="SFSP2_7" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x118+8" size="4" name="SFSP2_8" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x118+12" size="4" name="SFSP2_9" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x118+16" size="4" name="SFSP2_10" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x118+20" size="4" name="SFSP2_11" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x118+24" size="4" name="SFSP2_12" access="Read/Write" description="Pin configuration register for pins P2" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x180+0" size="4" name="SFSP3_0" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x180+4" size="4" name="SFSP3_1" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x180+8" size="4" name="SFSP3_2" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x18C" size="4" name="SFSP3_3" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
+        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
+        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x190+0" size="4" name="SFSP3_4" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x190+4" size="4" name="SFSP3_5" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x190+8" size="4" name="SFSP3_6" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x190+12" size="4" name="SFSP3_7" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x190+16" size="4" name="SFSP3_8" access="Read/Write" description="Pin configuration register for pins P3" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+0" size="4" name="SFSP4_0" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+4" size="4" name="SFSP4_1" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+8" size="4" name="SFSP4_2" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+12" size="4" name="SFSP4_3" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+16" size="4" name="SFSP4_4" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+20" size="4" name="SFSP4_5" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+24" size="4" name="SFSP4_6" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+28" size="4" name="SFSP4_7" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+32" size="4" name="SFSP4_8" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+36" size="4" name="SFSP4_9" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x200+40" size="4" name="SFSP4_10" access="Read/Write" description="Pin configuration register for pins P4" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x280+0" size="4" name="SFSP5_0" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x280+4" size="4" name="SFSP5_1" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x280+8" size="4" name="SFSP5_2" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x280+12" size="4" name="SFSP5_3" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x280+16" size="4" name="SFSP5_4" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x280+20" size="4" name="SFSP5_5" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x280+24" size="4" name="SFSP5_6" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x280+28" size="4" name="SFSP5_7" access="Read/Write" description="Pin configuration register for pins P5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+0" size="4" name="SFSP6_0" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+4" size="4" name="SFSP6_1" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+8" size="4" name="SFSP6_2" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+12" size="4" name="SFSP6_3" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+16" size="4" name="SFSP6_4" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+20" size="4" name="SFSP6_5" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+24" size="4" name="SFSP6_6" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+28" size="4" name="SFSP6_7" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+32" size="4" name="SFSP6_8" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+36" size="4" name="SFSP6_9" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+40" size="4" name="SFSP6_10" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+44" size="4" name="SFSP6_11" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x300+48" size="4" name="SFSP6_12" access="Read/Write" description="Pin configuration register for pins P6" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x380+0" size="4" name="SFSP7_0" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x380+4" size="4" name="SFSP7_1" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x380+8" size="4" name="SFSP7_2" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x380+12" size="4" name="SFSP7_3" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x380+16" size="4" name="SFSP7_4" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x380+20" size="4" name="SFSP7_5" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x380+24" size="4" name="SFSP7_6" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x380+28" size="4" name="SFSP7_7" access="Read/Write" description="Pin configuration register for pins P7" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x400+0" size="4" name="SFSP8_0" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x400+4" size="4" name="SFSP8_1" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x400+8" size="4" name="SFSP8_2" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x40C+0" size="4" name="SFSP8_3" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x40C+4" size="4" name="SFSP8_4" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x40C+8" size="4" name="SFSP8_5" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x40C+12" size="4" name="SFSP8_6" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x40C+16" size="4" name="SFSP8_7" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x40C+20" size="4" name="SFSP8_8" access="Read/Write" description="Pin configuration register for pins P8" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x480+0" size="4" name="SFSP9_0" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
+        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="SLOW" start="0" description="Slow" />
+        <Enum name="FAST" start="1" description="Fast" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="EHD" description="Select drive strength">
+        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x480+4" size="4" name="SFSP9_1" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
+        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="SLOW" start="0" description="Slow" />
+        <Enum name="FAST" start="1" description="Fast" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="EHD" description="Select drive strength">
+        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x480+8" size="4" name="SFSP9_2" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
+        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="SLOW" start="0" description="Slow" />
+        <Enum name="FAST" start="1" description="Fast" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="EHD" description="Select drive strength">
+        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x480+12" size="4" name="SFSP9_3" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
+        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="SLOW" start="0" description="Slow" />
+        <Enum name="FAST" start="1" description="Fast" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="EHD" description="Select drive strength">
+        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x480+16" size="4" name="SFSP9_4" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
+        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="SLOW" start="0" description="Slow" />
+        <Enum name="FAST" start="1" description="Fast" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="EHD" description="Select drive strength">
+        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x480+20" size="4" name="SFSP9_5" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
+        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="SLOW" start="0" description="Slow" />
+        <Enum name="FAST" start="1" description="Fast" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="EHD" description="Select drive strength">
+        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x480+24" size="4" name="SFSP9_6" access="Read/Write" description="Pin configuration register for pins P9" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad">
+        <Enum name="DISABLE_PULL_DOWN_" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN_" start="1" description="Enable pull-down." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up" />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="SLOW" start="0" description="Slow" />
+        <Enum name="FAST" start="1" description="Fast" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="8" size="2" name="EHD" description="Select drive strength">
+        <Enum name="STANDARD_DRIVE_4_MA" start="0x0" description="Standard drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra-high drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x500" size="4" name="SFSPA_0" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+0" size="4" name="SFSPA_1" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
+        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+4" size="4" name="SFSPA_2" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
+        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x504+8" size="4" name="SFSPA_3" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up" />
+      </BitField>
+      <BitField start="5" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="2" name="EHD" description="Select drive strength.">
+        <Enum name="NORMAL_DRIVE_4_MA_D" start="0x0" description="Normal-drive: 4 mA drive strength" />
+        <Enum name="MEDIUM_DRIVE_8_MA_D" start="0x1" description="Medium-drive: 8 mA drive strength" />
+        <Enum name="HIGH_DRIVE_14_MA_DR" start="0x2" description="High-drive: 14 mA drive strength" />
+        <Enum name="ULTRA_HIGH_DRIVE_20" start="0x3" description="Ultra high-drive: 20 mA drive strength" />
+      </BitField>
+      <BitField start="10" size="22" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x510" size="4" name="SFSPA_4" access="Read/Write" description="Pin configuration register for pins PA" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x580+0" size="4" name="SFSPB_0" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x580+4" size="4" name="SFSPB_1" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x580+8" size="4" name="SFSPB_2" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x580+12" size="4" name="SFSPB_3" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x580+16" size="4" name="SFSPB_4" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x580+20" size="4" name="SFSPB_5" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x580+24" size="4" name="SFSPB_6" access="Read/Write" description="Pin configuration register for pins PB" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+0" size="4" name="SFSPC_0" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+4" size="4" name="SFSPC_1" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+8" size="4" name="SFSPC_2" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+12" size="4" name="SFSPC_3" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+16" size="4" name="SFSPC_4" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+20" size="4" name="SFSPC_5" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+24" size="4" name="SFSPC_6" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+28" size="4" name="SFSPC_7" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+32" size="4" name="SFSPC_8" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+36" size="4" name="SFSPC_9" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+40" size="4" name="SFSPC_10" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+44" size="4" name="SFSPC_11" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+48" size="4" name="SFSPC_12" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+52" size="4" name="SFSPC_13" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x600+56" size="4" name="SFSPC_14" access="Read/Write" description="Pin configuration register for pins PC" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+0" size="4" name="SFSPD_0" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+4" size="4" name="SFSPD_1" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+8" size="4" name="SFSPD_2" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+12" size="4" name="SFSPD_3" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+16" size="4" name="SFSPD_4" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+20" size="4" name="SFSPD_5" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+24" size="4" name="SFSPD_6" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+28" size="4" name="SFSPD_7" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+32" size="4" name="SFSPD_8" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+36" size="4" name="SFSPD_9" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+40" size="4" name="SFSPD_10" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+44" size="4" name="SFSPD_11" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+48" size="4" name="SFSPD_12" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+52" size="4" name="SFSPD_13" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+56" size="4" name="SFSPD_14" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+60" size="4" name="SFSPD_15" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x680+64" size="4" name="SFSPD_16" access="Read/Write" description="Pin configuration register for pins PD" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+0" size="4" name="SFSPE_0" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+4" size="4" name="SFSPE_1" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+8" size="4" name="SFSPE_2" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+12" size="4" name="SFSPE_3" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+16" size="4" name="SFSPE_4" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+20" size="4" name="SFSPE_5" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+24" size="4" name="SFSPE_6" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+28" size="4" name="SFSPE_7" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+32" size="4" name="SFSPE_8" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+36" size="4" name="SFSPE_9" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+40" size="4" name="SFSPE_10" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+44" size="4" name="SFSPE_11" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+48" size="4" name="SFSPE_12" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+52" size="4" name="SFSPE_13" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+56" size="4" name="SFSPE_14" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x700+60" size="4" name="SFSPE_15" access="Read/Write" description="Pin configuration register for pins PE" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+0" size="4" name="SFSPF_0" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+4" size="4" name="SFSPF_1" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+8" size="4" name="SFSPF_2" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+12" size="4" name="SFSPF_3" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+16" size="4" name="SFSPF_4" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+20" size="4" name="SFSPF_5" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+24" size="4" name="SFSPF_6" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+28" size="4" name="SFSPF_7" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+32" size="4" name="SFSPF_8" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+36" size="4" name="SFSPF_9" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+40" size="4" name="SFSPF_10" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x780+44" size="4" name="SFSPF_11" access="Read/Write" description="Pin configuration register for pins PF" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Select Slew rate.">
+        <Enum name="SLOW_LOW_NOISE_WITH" start="0" description="Slow (low noise with medium speed)" />
+        <Enum name="FAST_MEDIUM_NOISE_W" start="1" description="Fast (medium noise with fast speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_GLITCH" start="0" description="Enable input glitch filter" />
+        <Enum name="DISABLE_INPUT_GLITCH" start="1" description="Disable input glitch filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xC00+0" size="4" name="SFSCLK_0" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
+        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
+        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xC00+4" size="4" name="SFSCLK_1" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
+        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
+        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xC00+8" size="4" name="SFSCLK_2" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
+        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
+        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xC00+12" size="4" name="SFSCLK_3" access="Read/Write" description="Pin configuration register for pins CLK" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="MODE" description="Select pin function.">
+        <Enum name="FUNCTION_0_DEFAULT" start="0x0" description="Function 0 (default)" />
+        <Enum name="FUNCTION_1" start="0x1" description="Function 1" />
+        <Enum name="FUNCTION_2" start="0x2" description="Function 2" />
+        <Enum name="FUNCTION_3" start="0x3" description="Function 3" />
+        <Enum name="FUNCTION_4" start="0x4" description="Function 4" />
+        <Enum name="FUNCTION_5" start="0x5" description="Function 5" />
+        <Enum name="FUNCTION_6" start="0x6" description="Function 6" />
+        <Enum name="FUNCTION_7" start="0x7" description="Function 7" />
+      </BitField>
+      <BitField start="3" size="1" name="EPD" description="Enable pull-down resistor at pad.">
+        <Enum name="DISABLE_PULL_DOWN" start="0" description="Disable pull-down." />
+        <Enum name="ENABLE_PULL_DOWN" start="1" description="Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+      </BitField>
+      <BitField start="4" size="1" name="EPUN" description="Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset.">
+        <Enum name="ENABLE_PULL_UP" start="0" description="Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode." />
+        <Enum name="DISABLE_PULL_UP" start="1" description="Disable pull-up." />
+      </BitField>
+      <BitField start="5" size="1" name="EHS" description="Slew rate">
+        <Enum name="FAST_LOW_NOISE_WITH" start="0" description="Fast (low noise with fast speed)" />
+        <Enum name="HIGH_SPEED_MEDIUM_N" start="1" description="High-speed (medium noise with high speed)" />
+      </BitField>
+      <BitField start="6" size="1" name="EZI" description="Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving.">
+        <Enum name="DISABLE_INPUT_BUFFER" start="0" description="Disable input buffer" />
+        <Enum name="ENABLE_INPUT_BUFFER" start="1" description="Enable input buffer" />
+      </BitField>
+      <BitField start="7" size="1" name="ZIF" description="Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.">
+        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
+        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xC80" size="4" name="SFSUSB" access="Read/Write" description="Pin configuration register for pins USB1_DM and USB1_DP" reset_value="0x02" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="USB_AIM" description="Differential data input AIP/AIM.">
+        <Enum name="GOING_LOW_WITH_FULL" start="0" description="Going LOW with full speed edge rate" />
+        <Enum name="GOING_HIGH_WITH_FULL" start="1" description="Going HIGH with full speed edge rate" />
+      </BitField>
+      <BitField start="1" size="1" name="USB_ESEA" description="Control signal for differential input or single input.">
+        <Enum name="RESERVED" start="0" description="Reserved. Do not use." />
+        <Enum name="SINGLE_INPUT" start="1" description="Single input. Enables USB1. Use with the on-chip full-speed PHY." />
+      </BitField>
+      <BitField start="2" size="1" name="USB_EPD" description="Enable pull-down connect.">
+        <Enum name="PULL_DOWN_DISCONNECT" start="0" description="Pull-down disconnected" />
+        <Enum name="PULL_DOWN_CONNECTED" start="1" description="Pull-down connected" />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="4" size="1" name="USB_EPWR" description="Power mode.">
+        <Enum name="POWER_SAVING_MODE_S" start="0" description="Power saving mode (Suspend mode)" />
+        <Enum name="NORMAL_MODE" start="1" description="Normal mode" />
+      </BitField>
+      <BitField start="5" size="1" name="USB_VBUS" description="Enable the vbus_valid signal. This signal is monitored by the USB1 block. Use this bit for software de-bouncing of the VBUS sense signal or to indicate the VBUS state to the USB1 controller when the VBUS signal is present but the USB1_VBUS function is not connected in the SFSP2_5 register.  The setting of this bit has no effect if the USB1_VBUS function of pin P2_5 is enabled through the SFSP2_5 register.">
+        <Enum name="VBUS_SIGNAL_LOW_OR_I" start="0" description="VBUS signal LOW or inactive" />
+        <Enum name="VBUS_SIGNAL_HIGH_OR" start="1" description="VBUS signal HIGH or active" />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xC84" size="4" name="SFSI2C0" access="Read/Write" description="Pin configuration register for I2C0-bus pins" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SCL_EFP" description="Select input glitch filter time constant for the SCL pin.">
+        <Enum name="50_NS_GLITCH_FILTER" start="0" description="50 ns glitch filter" />
+        <Enum name="3_NS_GLITCH_FILTER" start="1" description="3 ns glitch filter" />
+      </BitField>
+      <BitField start="1" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
+      <BitField start="2" size="1" name="SCL_EHD" description="Select I2C mode for the SCL pin.">
+        <Enum name="STANDARDFAST_MODE" start="0" description="Standard/Fast mode transmit" />
+        <Enum name="FAST_MODE_PLUS_TRANS" start="1" description="Fast-mode Plus transmit" />
+      </BitField>
+      <BitField start="3" size="1" name="SCL_EZI" description="Enable the input receiver for the SCL pin. Always write a 1 to this bit when using the I2C0.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="4" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="7" size="1" name="SCL_ZIF" description="Enable or disable input glitch filter for the SCL pin. The filter time constant is determined by bit EFP.">
+        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
+        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
+      </BitField>
+      <BitField start="8" size="1" name="SDA_EFP" description="Select input glitch filter time constant for the SDA pin.">
+        <Enum name="50_NS_GLITCH_FILTER" start="0" description="50 ns glitch filter" />
+        <Enum name="3_NS_GLITCH_FILTER" start="1" description="3 ns glitch filter" />
+      </BitField>
+      <BitField start="9" size="1" name="RESERVED" description="Reserved. Always write a 0 to this bit." />
+      <BitField start="10" size="1" name="SDA_EHD" description="Select I2C mode for the SDA pin.">
+        <Enum name="STANDARDFAST_MODE" start="0" description="Standard/Fast mode transmit" />
+        <Enum name="FAST_MODE_PLUS_TRANS" start="1" description="Fast-mode Plus transmit" />
+      </BitField>
+      <BitField start="11" size="1" name="SDA_EZI" description="Enable the input receiver for the SDA pin. Always write a 1 to this bit when using the I2C0.">
+        <Enum name="DISABLED" start="0" description="Disabled" />
+        <Enum name="ENABLED" start="1" description="Enabled" />
+      </BitField>
+      <BitField start="12" size="3" name="RESERVED" description="Reserved" />
+      <BitField start="15" size="1" name="SDA_ZIF" description="Enable or disable input glitch filter for the SDA pin. The filter time constant is determined by bit SDA_EFP.">
+        <Enum name="ENABLE_INPUT_FILTER" start="0" description="Enable input filter" />
+        <Enum name="DISABLE_INPUT_FILTER" start="1" description="Disable input filter" />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xC88" size="4" name="ENAIO0" access="Read/Write" description="ADC0 function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ADC0_0" description="Select ADC0_0">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_3." />
+        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_0 selected on pin P4_3" />
+      </BitField>
+      <BitField start="1" size="1" name="ADC0_1" description="Select ADC0_1">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_1." />
+        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_1 selected on pin P4_1." />
+      </BitField>
+      <BitField start="2" size="1" name="ADC0_2" description="Select ADC0_2">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_8." />
+        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_2 selected on pin PF_8." />
+      </BitField>
+      <BitField start="3" size="1" name="ADC0_3" description="Select ADC0_3">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_5." />
+        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_3 selected on pin P7_5." />
+      </BitField>
+      <BitField start="4" size="1" name="ADC0_4" description="Select ADC0_4">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_4." />
+        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_4 selected on pin P7_4." />
+      </BitField>
+      <BitField start="5" size="1" name="ADC0_5" description="Select ADC0_5">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_10." />
+        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_5 selected on pin PF_10." />
+      </BitField>
+      <BitField start="6" size="1" name="ADC0_6" description="Select ADC0_6">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PB_6." />
+        <Enum name="ANALOG_FUNCTION_ADC0" start="1" description="Analog function ADC0_6 selected on pin PB_6." />
+      </BitField>
+    </Register>
+    <Register start="+0xC8C" size="4" name="ENAIO1" access="Read/Write" description="ADC1 function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ADC1_0" description="Select ADC1_0">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PC_3." />
+        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_0 selected on pin PC_3." />
+      </BitField>
+      <BitField start="1" size="1" name="ADC1_1" description="Select ADC1_1">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PC_0." />
+        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_1 selected on pin PC_0." />
+      </BitField>
+      <BitField start="2" size="1" name="ADC1_2" description="Select ADC1_2">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_9." />
+        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_2 selected on pin PF_9." />
+      </BitField>
+      <BitField start="3" size="1" name="ADC1_3" description="Select ADC1_3">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_6." />
+        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_3 selected on pin PF_6." />
+      </BitField>
+      <BitField start="4" size="1" name="ADC1_4" description="Select ADC1_4">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_5." />
+        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_4 selected on pin PF_5." />
+      </BitField>
+      <BitField start="5" size="1" name="ADC1_5" description="Select ADC1_5">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_11." />
+        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_5 selected on pin PF_11." />
+      </BitField>
+      <BitField start="6" size="1" name="ADC1_6" description="Select ADC1_6">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P7_7." />
+        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_6 selected on pin P7_7." />
+      </BitField>
+      <BitField start="7" size="1" name="ADC1_7" description="Select ADC1_7.">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_7." />
+        <Enum name="ANALOG_FUNCTION_ADC1" start="1" description="Analog function ADC1_7 selected on pin PF_7." />
+      </BitField>
+    </Register>
+    <Register start="+0xC90" size="4" name="ENAIO2" access="Read/Write" description="Analog function select register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DAC" description="Select DAC">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin P4_4." />
+        <Enum name="ANALOG_FUNCTION_DAC" start="1" description="Analog function DAC selected on pin P4_4." />
+      </BitField>
+      <BitField start="4" size="1" name="BG" description="Select band gap output. To measure the band gap, disable the pull-up on pin PF_7 and connect PF_7 to the digital pad. Do not use the digital pad nor the ADC1_7 on the board when measuring the band gap (see Section 15.4.8.1).">
+        <Enum name="DIGITAL_FUNCTION_SEL" start="0" description="Digital function selected on pin PF_7." />
+        <Enum name="BAND_GAP_OUTPUT_SELE" start="1" description="Band gap output selected for pin PF_7." />
+      </BitField>
+    </Register>
+    <Register start="+0xD00" size="4" name="EMCDELAYCLK" access="Read/Write" description="EMC clock delay register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CLK_DELAY" description="EMC_CLKn SDRAM clock output delay. 0x0 = no delay 0x1111 approximately 0.5 ns delay 0x2222 approximately 1.0 ns delay 0x3333 approximately 1.5 ns delay 0x4444 approximately 2.0 ns delay 0x5555 approximately 2.5 ns delay 0x6666 approximately 3.0 ns delay 0x7777 approximately 3.5 ns delay" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
+    </Register>
+    <Register start="+0xD80" size="4" name="SDDELAY" access="Read/Write" description="SD/MMC sample and drive delay register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="SAMPLE_DELAY" description="SD/MMC sample delay. The delay value is SAMPLE_DELAY x 0.5 ns." />
+      <BitField start="4" size="4" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
+      <BitField start="8" size="4" name="DRV_DELAY" description="SD/MMC drive delay. The delay value is DRV_DELAY x 0.5 ns. The values DRV_DELAY = 0 and DRV_DELAY = 1 are not allowed." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved. Do not write ones to reserved register bits." />
+    </Register>
+    <Register start="+0xE00" size="4" name="PINTSEL0" access="Read/Write" description="Pin interrupt select register for pin interrupts 0 to 3." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="INTPIN0" description="Pint interrupt 0: Select the pin number within the GPIO port selected by the PORTSEL0 bit in this register." />
+      <BitField start="5" size="3" name="PORTSEL0" description="Pin interrupt 0: Select the port for the pin number to be selected in the INTPIN0 bits of this register.">
+        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
+        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
+        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
+        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
+        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
+        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
+        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
+        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
+      </BitField>
+      <BitField start="8" size="5" name="INTPIN1" description="Pint interrupt 1: Select the pin number within the GPIO port selected by the PORTSEL1 bit in this register." />
+      <BitField start="13" size="3" name="PORTSEL1" description="Pin interrupt 1: Select the port for the pin number to be selected in the INTPIN1 bits of this register.">
+        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
+        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
+        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
+        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
+        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
+        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
+        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
+        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
+      </BitField>
+      <BitField start="16" size="5" name="INTPIN2" description="Pint interrupt 2: Select the pin number within the GPIO port selected by the PORTSEL2 bit in this register." />
+      <BitField start="21" size="3" name="PORTSEL2" description="Pin interrupt 2: Select the port for the pin number to be selected in the INTPIN2 bits of this register.">
+        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
+        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
+        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
+        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
+        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
+        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
+        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
+        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
+      </BitField>
+      <BitField start="24" size="5" name="INTPIN3" description="Pint interrupt 3: Select the pin number within the GPIO port selected by the PORTSEL3 bit in this register." />
+      <BitField start="29" size="3" name="PORTSEL3" description="Pin interrupt 3: Select the port for the pin number to be selected in the INTPIN3 bits of this register.">
+        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
+        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
+        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
+        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
+        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
+        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
+        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
+        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
+      </BitField>
+    </Register>
+    <Register start="+0xE04" size="4" name="PINTSEL1" access="Read/Write" description="Pin interrupt select register for pin interrupts 4 to 7." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="INTPIN4" description="Pint interrupt 4: Select the pin number within the GPIO port selected by the PORTSEL4 bit in this register." />
+      <BitField start="5" size="3" name="PORTSEL4" description="Pin interrupt 4: Select the port for the pin number to be selected in the INTPIN4 bits of this register.">
+        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
+        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
+        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
+        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
+        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
+        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
+        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
+        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
+      </BitField>
+      <BitField start="8" size="5" name="INTPIN5" description="Pint interrupt 5: Select the pin number within the GPIO port selected by the PORTSEL5 bit in this register." />
+      <BitField start="13" size="3" name="PORTSEL5" description="Pin interrupt 5: Select the port for the pin number to be selected in the INTPIN5 bits of this register.">
+        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
+        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
+        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
+        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
+        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
+        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
+        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
+        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
+      </BitField>
+      <BitField start="16" size="5" name="INTPIN6" description="Pint interrupt 6: Select the pin number within the GPIO port selected by the PORTSEL6 bit in this register." />
+      <BitField start="21" size="3" name="PORTSEL6" description="Pin interrupt 6: Select the port for the pin number to be selected in the INTPIN6 bits of this register.">
+        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
+        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
+        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
+        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
+        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
+        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
+        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
+        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
+      </BitField>
+      <BitField start="24" size="5" name="INTPIN7" description="Pint interrupt 7: Select the pin number within the GPIO port selected by the PORTSEL7 bit in this register." />
+      <BitField start="29" size="3" name="PORTSEL7" description="Pin interrupt 7: Select the port for the pin number to be selected in the INTPIN7 bits of this register.">
+        <Enum name="GPIO_PORT_0" start="0x0" description="GPIO Port 0" />
+        <Enum name="GPIO_PORT_1" start="0x1" description="GPIO Port 1" />
+        <Enum name="GPIO_PORT_2" start="0x2" description="GPIO Port 2" />
+        <Enum name="GPIO_PORT_3" start="0x3" description="GPIO Port 3" />
+        <Enum name="GPIO_PORT_4" start="0x4" description="GPIO Port 4" />
+        <Enum name="GPIO_PORT_5" start="0x5" description="GPIO Port 5" />
+        <Enum name="GPIO_PORT_6" start="0x6" description="GPIO Port 6" />
+        <Enum name="GPIO_PORT_7" start="0x7" description="GPIO Port 7" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIO_PIN_INT" start="0x40087000" description="GPIO pin interrupt">
+    <Register start="+0x000" size="4" name="ISEL" access="Read/Write" description="Pin Interrupt Mode register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PMODE0" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="1" size="1" name="PMODE1" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="2" size="1" name="PMODE2" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="3" size="1" name="PMODE3" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="4" size="1" name="PMODE4" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="5" size="1" name="PMODE5" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="6" size="1" name="PMODE6" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="7" size="1" name="PMODE7" description="Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive" />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x004" size="4" name="IENR" access="Read/Write" description="Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENRL0" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="1" size="1" name="ENRL1" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="2" size="1" name="ENRL2" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="3" size="1" name="ENRL3" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="4" size="1" name="ENRL4" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="5" size="1" name="ENRL5" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="6" size="1" name="ENRL6" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="7" size="1" name="ENRL7" description="Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable rising edge or level interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x008" size="4" name="SIENR" access="WriteOnly" description="Set Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="SETENRL0" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="1" size="1" name="SETENRL1" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="2" size="1" name="SETENRL2" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="3" size="1" name="SETENRL3" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="4" size="1" name="SETENRL4" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="5" size="1" name="SETENRL5" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="6" size="1" name="SETENRL6" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="7" size="1" name="SETENRL7" description="Ones written to this address set bits in the PINTEN_R, thus enabling interrupts. Bit n sets bit n in the PINTEN_R register. 0 = No operation. 1 = Enable rising edge or level interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x00C" size="4" name="CIENR" access="WriteOnly" description="Clear Pin Interrupt Enable (Rising) register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CENRL0" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="1" size="1" name="CENRL1" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="2" size="1" name="CENRL2" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="3" size="1" name="CENRL3" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="4" size="1" name="CENRL4" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="5" size="1" name="CENRL5" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="6" size="1" name="CENRL6" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="7" size="1" name="CENRL7" description="Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x010" size="4" name="IENF" access="Read/Write" description="Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENAF0" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="1" size="1" name="ENAF1" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="2" size="1" name="ENAF2" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="3" size="1" name="ENAF3" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="4" size="1" name="ENAF4" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="5" size="1" name="ENAF5" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="6" size="1" name="ENAF6" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="7" size="1" name="ENAF7" description="Enables the falling edge or configures the active level interrupt for each pin interrupt. Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active interrupt level HIGH." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x014" size="4" name="SIENF" access="WriteOnly" description="Set Pin Interrupt Enable Falling Edge / Active Level register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="SETENAF0" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="1" size="1" name="SETENAF1" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="2" size="1" name="SETENAF2" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="3" size="1" name="SETENAF3" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="4" size="1" name="SETENAF4" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="5" size="1" name="SETENAF5" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="6" size="1" name="SETENAF6" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="7" size="1" name="SETENAF7" description="Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable falling edge interrupt." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x018" size="4" name="CIENF" access="WriteOnly" description="Clear Pin Interrupt Enable Falling Edge / Active Level address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CENAF0" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="1" size="1" name="CENAF1" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="2" size="1" name="CENAF2" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="3" size="1" name="CENAF3" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="4" size="1" name="CENAF4" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="5" size="1" name="CENAF5" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="6" size="1" name="CENAF6" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="7" size="1" name="CENAF7" description="Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or falling edge interrupt disabled." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C" size="4" name="RISE" access="Read/Write" description="Pin Interrupt Rising Edge register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RDET0" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="1" size="1" name="RDET1" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="2" size="1" name="RDET2" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="3" size="1" name="RDET3" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="4" size="1" name="RDET4" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="5" size="1" name="RDET5" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="6" size="1" name="RDET6" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="7" size="1" name="RDET7" description="Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 0: No rising edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear rising edge detection for this pin." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x020" size="4" name="FALL" access="Read/Write" description="Pin Interrupt Falling Edge register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FDET0" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="1" size="1" name="FDET1" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="2" size="1" name="FDET2" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="3" size="1" name="FDET3" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="4" size="1" name="FDET4" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="5" size="1" name="FDET5" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="6" size="1" name="FDET6" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="7" size="1" name="FDET7" description="Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 0: No falling edge has been detected on this pin since Reset or the last time a one was written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or the last time a one was written to this bit. Write 1: clear falling edge detection for this pin." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x024" size="4" name="IST" access="Read/Write" description="Pin Interrupt Status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PSTAT0" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="1" size="1" name="PSTAT1" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="2" size="1" name="PSTAT2" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="3" size="1" name="PSTAT3" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="4" size="1" name="PSTAT4" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="5" size="1" name="PSTAT5" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="6" size="1" name="PSTAT6" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="7" size="1" name="PSTAT7" description="Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for this interrupt pin.  Write 0: no operation. Read 1: interrupt is being requested for this interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. Write 1 (level-sensitive): switch the active level for this pin (in the PINTENT_F register)." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIO_GROUP_INT0" start="0x40088000" description="GPIO group interrupt 0">
+    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
+        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
+        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
+      </BitField>
+      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
+        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
+        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
+      </BitField>
+      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
+        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
+        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+8" size="4" name="PORT_POL2" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+12" size="4" name="PORT_POL3" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+16" size="4" name="PORT_POL4" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+20" size="4" name="PORT_POL5" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+24" size="4" name="PORT_POL6" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+28" size="4" name="PORT_POL7" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+8" size="4" name="PORT_ENA2" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+12" size="4" name="PORT_ENA3" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+16" size="4" name="PORT_ENA4" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+20" size="4" name="PORT_ENA5" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+24" size="4" name="PORT_ENA6" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+28" size="4" name="PORT_ENA7" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIO_GROUP_INT1" start="0x40089000" description="GPIO group interrupt 0">
+    <Register start="+0x000" size="4" name="CTRL" access="Read/Write" description="GPIO grouped interrupt control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INT" description="Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.">
+        <Enum name="NO_INTERRUPT_REQUEST" start="0" description="No interrupt request is pending." />
+        <Enum name="INTERRUPT_REQUEST_IS" start="1" description="Interrupt request is active." />
+      </BitField>
+      <BitField start="1" size="1" name="COMB" description="Combine enabled inputs for group interrupt">
+        <Enum name="OR_FUNCTIONALITY_A_" start="0" description="OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity)." />
+        <Enum name="AND_FUNCTIONALITY_A" start="1" description="AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity)." />
+      </BitField>
+      <BitField start="2" size="1" name="TRIG" description="Group interrupt trigger">
+        <Enum name="EDGE_TRIGGERED" start="0" description="Edge-triggered" />
+        <Enum name="LEVEL_TRIGGERED" start="1" description="Level-triggered" />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020+0" size="4" name="PORT_POL0" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+4" size="4" name="PORT_POL1" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+8" size="4" name="PORT_POL2" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+12" size="4" name="PORT_POL3" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+16" size="4" name="PORT_POL4" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+20" size="4" name="PORT_POL5" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+24" size="4" name="PORT_POL6" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x020+28" size="4" name="PORT_POL7" access="Read/Write" description="GPIO grouped interrupt port  polarity register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="POL_0" description="Configure pin polarity of port  pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m . 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="1" size="1" name="POL_1" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="2" size="1" name="POL_2" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="3" size="1" name="POL_3" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="4" size="1" name="POL_4" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="5" size="1" name="POL_5" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="6" size="1" name="POL_6" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="7" size="1" name="POL_7" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="8" size="1" name="POL_8" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="9" size="1" name="POL_9" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="10" size="1" name="POL_10" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="11" size="1" name="POL_11" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="12" size="1" name="POL_12" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="13" size="1" name="POL_13" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="14" size="1" name="POL_14" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="15" size="1" name="POL_15" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="16" size="1" name="POL_16" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="17" size="1" name="POL_17" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="18" size="1" name="POL_18" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="19" size="1" name="POL_19" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="20" size="1" name="POL_20" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="21" size="1" name="POL_21" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="22" size="1" name="POL_22" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="23" size="1" name="POL_23" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="24" size="1" name="POL_24" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="25" size="1" name="POL_25" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="26" size="1" name="POL_26" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="27" size="1" name="POL_27" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="28" size="1" name="POL_28" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="29" size="1" name="POL_29" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="30" size="1" name="POL_30" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+      <BitField start="31" size="1" name="POL_31" description="Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin contributes to the group interrupt." />
+    </Register>
+    <Register start="+0x040+0" size="4" name="PORT_ENA0" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+4" size="4" name="PORT_ENA1" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+8" size="4" name="PORT_ENA2" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+12" size="4" name="PORT_ENA3" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+16" size="4" name="PORT_ENA4" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+20" size="4" name="PORT_ENA5" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+24" size="4" name="PORT_ENA6" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+    <Register start="+0x040+28" size="4" name="PORT_ENA7" access="Read/Write" description="GPIO grouped interrupt port m enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ENA_0" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="1" size="1" name="ENA_1" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="2" size="1" name="ENA_2" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="3" size="1" name="ENA_3" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="4" size="1" name="ENA_4" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="5" size="1" name="ENA_5" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="6" size="1" name="ENA_6" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="7" size="1" name="ENA_7" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="8" size="1" name="ENA_8" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="9" size="1" name="ENA_9" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="10" size="1" name="ENA_10" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="11" size="1" name="ENA_11" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="12" size="1" name="ENA_12" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="13" size="1" name="ENA_13" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="14" size="1" name="ENA_14" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="15" size="1" name="ENA_15" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="16" size="1" name="ENA_16" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="17" size="1" name="ENA_17" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="18" size="1" name="ENA_18" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="19" size="1" name="ENA_19" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="20" size="1" name="ENA_20" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="21" size="1" name="ENA_21" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="22" size="1" name="ENA_22" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="23" size="1" name="ENA_23" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="24" size="1" name="ENA_24" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="25" size="1" name="ENA_25" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="26" size="1" name="ENA_26" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="27" size="1" name="ENA_27" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="28" size="1" name="ENA_28" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="29" size="1" name="ENA_29" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="30" size="1" name="ENA_30" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+      <BitField start="31" size="1" name="ENA_31" description="Enable port m pin for group interrupt. Bit n corresponds to pin GPIOm[n] of port m. 0 = the port m pin is disabled and does not contribute to the grouped interrupt. 1 = the port m pin is enabled and contributes to the grouped interrupt." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MCPWM" start="0x400A0000" description="Motor Control PWM (MOTOCONPWM) ">
+    <Register start="+0x000" size="4" name="CON" access="ReadOnly" description="PWM Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RUN0" description="Stops/starts timer channel 0.">
+        <Enum name="STOP_" start="0" description="Stop." />
+        <Enum name="RUN_" start="1" description="Run." />
+      </BitField>
+      <BitField start="1" size="1" name="CENTER0" description="Edge/center aligned operation for channel 0.">
+        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
+        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
+      </BitField>
+      <BitField start="2" size="1" name="POLA0" description="Selects polarity of the MCOA0 and MCOB0 pins.">
+        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
+        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
+      </BitField>
+      <BitField start="3" size="1" name="DTE0" description="Controls the dead-time feature for channel 0.">
+        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
+        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
+      </BitField>
+      <BitField start="4" size="1" name="DISUP0" description="Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).">
+        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
+        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
+      </BitField>
+      <BitField start="5" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="RUN1" description="Stops/starts timer channel 1.">
+        <Enum name="STOP_" start="0" description="Stop." />
+        <Enum name="RUN_" start="1" description="Run." />
+      </BitField>
+      <BitField start="9" size="1" name="CENTER1" description="Edge/center aligned operation for channel 1.">
+        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
+        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
+      </BitField>
+      <BitField start="10" size="1" name="POLA1" description="Selects polarity of the MCOA1 and MCOB1 pins.">
+        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
+        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
+      </BitField>
+      <BitField start="11" size="1" name="DTE1" description="Controls the dead-time feature for channel 1.">
+        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
+        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
+      </BitField>
+      <BitField start="12" size="1" name="DISUP1" description="Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).">
+        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
+        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
+      </BitField>
+      <BitField start="13" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="16" size="1" name="RUN2" description="Stops/starts timer channel 2.">
+        <Enum name="STOP_" start="0" description="Stop." />
+        <Enum name="RUN_" start="1" description="Run." />
+      </BitField>
+      <BitField start="17" size="1" name="CENTER2" description="Edge/center aligned operation for channel 2.">
+        <Enum name="EDGE_ALIGNED_" start="0" description="Edge-aligned." />
+        <Enum name="CENTER_ALIGNED_" start="1" description="Center-aligned." />
+      </BitField>
+      <BitField start="18" size="1" name="POLA2" description="Selects polarity of the MCOA2 and MCOB2 pins.">
+        <Enum name="PASSIVE_STATE_IS_LOW" start="0" description="Passive state is LOW, active state is HIGH." />
+        <Enum name="PASSIVE_STATE_IS_HIG" start="1" description="Passive state is HIGH, active state is LOW." />
+      </BitField>
+      <BitField start="19" size="1" name="DTE2" description="Controls the dead-time feature for channel 1.">
+        <Enum name="DEAD_TIME_DISABLED_" start="0" description="Dead-time disabled." />
+        <Enum name="DEAD_TIME_ENABLED_" start="1" description="Dead-time enabled." />
+      </BitField>
+      <BitField start="20" size="1" name="DISUP2" description="Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).">
+        <Enum name="UPDATE" start="0" description="Functional registers are updated from the write registers at the end of each PWM cycle." />
+        <Enum name="NOUPDATE" start="1" description="Functional registers remain the same as long as the timer is running." />
+      </BitField>
+      <BitField start="21" size="8" name="RESERVED" description="Reserved." />
+      <BitField start="29" size="1" name="INVBDC" description="Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.">
+        <Enum name="OPPOSITE" start="0" description="The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time)." />
+        <Enum name="SAME" start="1" description="The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)" />
+      </BitField>
+      <BitField start="30" size="1" name="ACMODE" description="3-phase AC mode select (see Section 24.8.7).">
+        <Enum name="3_PHASE_AC_MODE_OFF" start="0" description="3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register." />
+        <Enum name="3_PHASE_AC_MODE_ON_" start="1" description="3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0." />
+      </BitField>
+      <BitField start="31" size="1" name="DCMODE" description="3-phase DC mode select (see Section 24.8.6).">
+        <Enum name="3_PHASE_DC_MODE_OFF" start="0" description="3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)" />
+        <Enum name="3_PHASE_DC_MODE_ON_" start="1" description="3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs." />
+      </BitField>
+    </Register>
+    <Register start="+0x004" size="4" name="CON_SET" access="WriteOnly" description="PWM Control set address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="RUN0_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="1" size="1" name="CENTER0_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="2" size="1" name="POLA0_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="3" size="1" name="DTE0_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="4" size="1" name="DISUP0_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="5" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="8" size="1" name="RUN1_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="9" size="1" name="CENTER1_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="10" size="1" name="POLA1_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="11" size="1" name="DTE1_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="12" size="1" name="DISUP1_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="13" size="3" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="16" size="1" name="RUN2_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="17" size="1" name="CENTER2_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="18" size="1" name="POLA2_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="19" size="1" name="DTE2_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="20" size="1" name="DISUP2_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="21" size="8" name="RESERVED" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="29" size="1" name="INVBDC_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="30" size="1" name="ACMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
+      <BitField start="31" size="1" name="DCMODE_SET" description="Writing a one sets the corresponding bit in the CON register." />
+    </Register>
+    <Register start="+0x008" size="4" name="CON_CLR" access="WriteOnly" description="PWM Control clear address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="RUN0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="1" size="1" name="CENTER0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="2" size="1" name="POLA0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="3" size="1" name="DTE0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="4" size="1" name="DISUP0_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="5" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="8" size="1" name="RUN1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="9" size="1" name="CENTER1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="10" size="1" name="POLA1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="11" size="1" name="DTE1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="12" size="1" name="DISUP1_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="13" size="3" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="16" size="1" name="RUN2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="17" size="1" name="CENTER2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="18" size="1" name="POLA2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="19" size="1" name="DTE2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="20" size="1" name="DISUP2_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="21" size="8" name="RESERVED" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="29" size="1" name="INVBDC_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="30" size="1" name="ACMOD_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+      <BitField start="31" size="1" name="DCMODE_CLR" description="Writing a one clears the corresponding bit in the CON register." />
+    </Register>
+    <Register start="+0x00C" size="4" name="CAPCON" access="ReadOnly" description="Capture Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CAP0MCI0_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0." />
+      <BitField start="1" size="1" name="CAP0MCI0_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0." />
+      <BitField start="2" size="1" name="CAP0MCI1_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1." />
+      <BitField start="3" size="1" name="CAP0MCI1_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1." />
+      <BitField start="4" size="1" name="CAP0MCI2_RE" description="A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2." />
+      <BitField start="5" size="1" name="CAP0MCI2_FE" description="A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2." />
+      <BitField start="6" size="1" name="CAP1MCI0_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0." />
+      <BitField start="7" size="1" name="CAP1MCI0_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0." />
+      <BitField start="8" size="1" name="CAP1MCI1_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1." />
+      <BitField start="9" size="1" name="CAP1MCI1_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1." />
+      <BitField start="10" size="1" name="CAP1MCI2_RE" description="A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2." />
+      <BitField start="11" size="1" name="CAP1MCI2_FE" description="A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2." />
+      <BitField start="12" size="1" name="CAP2MCI0_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0." />
+      <BitField start="13" size="1" name="CAP2MCI0_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0." />
+      <BitField start="14" size="1" name="CAP2MCI1_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1." />
+      <BitField start="15" size="1" name="CAP2MCI1_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1." />
+      <BitField start="16" size="1" name="CAP2MCI2_RE" description="A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2." />
+      <BitField start="17" size="1" name="CAP2MCI2_FE" description="A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2." />
+      <BitField start="18" size="1" name="RT0" description="If this bit is 1, TC0 is reset by a channel 0 capture event." />
+      <BitField start="19" size="1" name="RT1" description="If this bit is 1, TC1 is reset by a channel 1 capture event." />
+      <BitField start="20" size="1" name="RT2" description="If this bit is 1, TC2 is reset by a channel 2 capture event." />
+      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x010" size="4" name="CAPCON_SET" access="WriteOnly" description="Capture Control set address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CAP0MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="1" size="1" name="CAP0MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="2" size="1" name="CAP0MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="3" size="1" name="CAP0MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="4" size="1" name="CAP0MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="5" size="1" name="CAP0MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="6" size="1" name="CAP1MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="7" size="1" name="CAP1MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="8" size="1" name="CAP1MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="9" size="1" name="CAP1MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="10" size="1" name="CAP1MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="11" size="1" name="CAP1MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="12" size="1" name="CAP2MCI0_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="13" size="1" name="CAP2MCI0_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="14" size="1" name="CAP2MCI1_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="15" size="1" name="CAP2MCI1_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="16" size="1" name="CAP2MCI2_RE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="17" size="1" name="CAP2MCI2_FE_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="18" size="1" name="RT0_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="19" size="1" name="RT1_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="20" size="1" name="RT2_SET" description="Writing a one sets the corresponding bits in the CAPCON register." />
+      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x014" size="4" name="CAPCON_CLR" access="WriteOnly" description="Event Control clear address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CAP0MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="1" size="1" name="CAP0MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="2" size="1" name="CAP0MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="3" size="1" name="CAP0MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="4" size="1" name="CAP0MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="5" size="1" name="CAP0MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="6" size="1" name="CAP1MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="7" size="1" name="CAP1MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="8" size="1" name="CAP1MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="9" size="1" name="CAP1MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="10" size="1" name="CAP1MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="11" size="1" name="CAP1MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="12" size="1" name="CAP2MCI0_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="13" size="1" name="CAP2MCI0_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="14" size="1" name="CAP2MCI1_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="15" size="1" name="CAP2MCI1_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="16" size="1" name="CAP2MCI2_RE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="17" size="1" name="CAP2MCI2_FE_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="18" size="1" name="RT0_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="19" size="1" name="RT1_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="20" size="1" name="RT2_CLR" description="Writing a one clears the corresponding bits in the CAPCON register." />
+      <BitField start="21" size="11" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x018+0" size="4" name="TC0" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
+    </Register>
+    <Register start="+0x018+4" size="4" name="TC1" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
+    </Register>
+    <Register start="+0x018+8" size="4" name="TC2" access="Read/Write" description="Timer Counter register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCTC" description="Timer/Counter value." />
+    </Register>
+    <Register start="+0x024+0" size="4" name="LIM0" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
+    </Register>
+    <Register start="+0x024+4" size="4" name="LIM1" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
+    </Register>
+    <Register start="+0x024+8" size="4" name="LIM2" access="Read/Write" description="Limit register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCLIM" description="Limit value." />
+    </Register>
+    <Register start="+0x030+0" size="4" name="MAT0" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCMAT" description="Match value." />
+    </Register>
+    <Register start="+0x030+4" size="4" name="MAT1" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCMAT" description="Match value." />
+    </Register>
+    <Register start="+0x030+8" size="4" name="MAT2" access="Read/Write" description="Match register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MCMAT" description="Match value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="DT" access="Read/Write" description="Dead time register" reset_value="0x3FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="10" name="DT0" description="Dead time for channel 0.[1]" />
+      <BitField start="10" size="10" name="DT1" description="Dead time for channel 1.[2]" />
+      <BitField start="20" size="10" name="DT2" description="Dead time for channel 2.[2]" />
+      <BitField start="30" size="2" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x040" size="4" name="CCP" access="Read/Write" description="Communication Pattern register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="CCPA0" description="Communication pattern output A, channel 0.">
+        <Enum name="MCOA0_PASSIVE_" start="0" description="MCOA0 passive." />
+        <Enum name="INTERNAL_MCOA0_" start="1" description="internal MCOA0." />
+      </BitField>
+      <BitField start="1" size="1" name="CCPB0" description="Communication pattern output B, channel 0.">
+        <Enum name="MCOB0_PASSIVE_" start="0" description="MCOB0 passive." />
+        <Enum name="MCOB0_TRACKS_INTERNA" start="1" description="MCOB0 tracks internal MCOA0." />
+      </BitField>
+      <BitField start="2" size="1" name="CCPA1" description="Communication pattern output A, channel 1.">
+        <Enum name="MCOA1_PASSIVE_" start="0" description="MCOA1 passive." />
+        <Enum name="MCOA1_TRACKS_INTERNA" start="1" description="MCOA1 tracks internal MCOA0." />
+      </BitField>
+      <BitField start="3" size="1" name="CCPB1" description="Communication pattern output B, channel 1.">
+        <Enum name="MCOB1_PASSIVE_" start="0" description="MCOB1 passive." />
+        <Enum name="MCOB1_TRACKS_INTERNA" start="1" description="MCOB1 tracks internal MCOA0." />
+      </BitField>
+      <BitField start="4" size="1" name="CCPA2" description="Communication pattern output A, channel 2.">
+        <Enum name="MCOA2_PASSIVE_" start="0" description="MCOA2 passive." />
+        <Enum name="MCOA2_TRACKS_INTERNA" start="1" description="MCOA2 tracks internal MCOA0." />
+      </BitField>
+      <BitField start="5" size="1" name="CCPB2" description="Communication pattern output B, channel 2.">
+        <Enum name="MCOB2_PASSIVE_" start="0" description="MCOB2 passive." />
+        <Enum name="MCOB2_TRACKS_INTERNA" start="1" description="MCOB2 tracks internal MCOA0." />
+      </BitField>
+      <BitField start="6" size="26" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x044+0" size="4" name="CAP0" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
+    </Register>
+    <Register start="+0x044+4" size="4" name="CAP1" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
+    </Register>
+    <Register start="+0x044+8" size="4" name="CAP2" access="ReadOnly" description="Capture register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="CAP" description="Current TC value at a capture event." />
+    </Register>
+    <Register start="+0x050" size="4" name="INTEN" access="ReadOnly" description="Interrupt Enable read address" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ILIM0" description="Limit interrupt for channel 0.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="1" size="1" name="IMAT0" description="Match interrupt for channel 0.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="ICAP0" description="Capture interrupt for channel 0.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="ILIM1" description="Limit interrupt for channel 1.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="5" size="1" name="IMAT1" description="Match interrupt for channel 1.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="6" size="1" name="ICAP1" description="Capture interrupt for channel 1.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="ILIM2" description="Limit interrupt for channel 2.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="9" size="1" name="IMAT2" description="Match interrupt for channel 2.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="10" size="1" name="ICAP2" description="Capture interrupt for channel 2.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="ABORT" description="Fast abort interrupt.">
+        <Enum name="INTERRUPT_DISABLED_" start="0" description="Interrupt disabled." />
+        <Enum name="INTERRUPT_ENABLED_" start="1" description="Interrupt enabled." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x054" size="4" name="INTEN_SET" access="WriteOnly" description="Interrupt Enable set address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="ILIM0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="1" size="1" name="IMAT0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="2" size="1" name="ICAP0_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="ILIM1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="5" size="1" name="IMAT1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="6" size="1" name="ICAP1_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="9" size="1" name="ILIM2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="10" size="1" name="IMAT2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="11" size="1" name="ICAP2_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="12" size="3" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="ABORT_SET" description="Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x058" size="4" name="INTEN_CLR" access="WriteOnly" description="Interrupt Enable clear address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="ILIM0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="1" size="1" name="IMAT0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="2" size="1" name="ICAP0_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="ILIM1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="5" size="1" name="IMAT1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="6" size="1" name="ICAP1_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="ILIM2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="9" size="1" name="IMAT2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="10" size="1" name="ICAP2_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="ABORT_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x068" size="4" name="INTF" access="ReadOnly" description="Interrupt flags read address" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ILIM0_F" description="Limit interrupt flag for channel 0.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="1" size="1" name="IMAT0_F" description="Match interrupt flag for channel 0.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="2" size="1" name="ICAP0_F" description="Capture interrupt flag for channel 0.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="ILIM1_F" description="Limit interrupt flag for channel 1.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="5" size="1" name="IMAT1_F" description="Match interrupt flag for channel 1.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="6" size="1" name="ICAP1_F" description="Capture interrupt flag for channel 1.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="ILIM2_F" description="Limit interrupt flag for channel 2.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="9" size="1" name="IMAT2_F" description="Match interrupt flag for channel 2.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="10" size="1" name="ICAP2_F" description="Capture interrupt flag for channel 2.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="ABORT_F" description="Fast abort interrupt flag.">
+        <Enum name="THIS_INTERRUPT_SOURC" start="0" description="This interrupt source is not contributing to the MCPWM interrupt request." />
+        <Enum name="IF_THE_CORRESPONDING" start="1" description="If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x06C" size="4" name="INTF_SET" access="WriteOnly" description="Interrupt flags set address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="ILIM0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="1" size="1" name="IMAT0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="2" size="1" name="ICAP0_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="ILIM1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="5" size="1" name="IMAT1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="6" size="1" name="ICAP1_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="ILIM2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="9" size="1" name="IMAT2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="10" size="1" name="ICAP2_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="11" size="4" name="RESERVED" description="Reserved." />
+      <BitField start="15" size="1" name="ABORT_F_SET" description="Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x070" size="4" name="INTF_CLR" access="WriteOnly" description="Interrupt flags clear address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="ILIM0_F_CLR" description="Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request." />
+      <BitField start="1" size="1" name="IMAT0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="2" size="1" name="ICAP0_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="3" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="4" size="1" name="ILIM1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="5" size="1" name="IMAT1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="6" size="1" name="ICAP1_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="1" name="ILIM2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="9" size="1" name="IMAT2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="10" size="1" name="ICAP2_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="11" size="4" name="RESERVED" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="15" size="1" name="ABORT_F_CLR" description="Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x05C" size="4" name="CNTCON" access="ReadOnly" description="Count Control read address" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="TC0MCI0_RE" description="Counter 0 rising edge mode, channel 0.">
+        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 0." />
+        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI0." />
+      </BitField>
+      <BitField start="1" size="1" name="TC0MCI0_FE" description="Counter 0 falling edge mode, channel 0.">
+        <Enum name="NOEFECT" start="0" description="A falling edge on MCI0 does not affect counter 0." />
+        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI0." />
+      </BitField>
+      <BitField start="2" size="1" name="TC0MCI1_RE" description="Counter 0 rising edge mode, channel 1.">
+        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 0." />
+        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI1." />
+      </BitField>
+      <BitField start="3" size="1" name="TC0MCI1_FE" description="Counter 0 falling edge mode, channel 1.">
+        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI1 does not affect counter 0." />
+        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI1." />
+      </BitField>
+      <BitField start="4" size="1" name="TC0MCI2_RE" description="Counter 0 rising edge mode, channel 2.">
+        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 0." />
+        <Enum name="RISING" start="1" description="If MODE0 is 1, counter 0 advances on a rising edge on MCI2." />
+      </BitField>
+      <BitField start="5" size="1" name="TC0MCI2_FE" description="Counter 0 falling edge mode, channel 2.">
+        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 0." />
+        <Enum name="FALLING" start="1" description="If MODE0 is 1, counter 0 advances on a falling edge on MCI2." />
+      </BitField>
+      <BitField start="6" size="1" name="TC1MCI0_RE" description="Counter 1 rising edge mode, channel 0.">
+        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 1." />
+        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI0." />
+      </BitField>
+      <BitField start="7" size="1" name="TC1MCI0_FE" description="Counter 1 falling edge mode, channel 0.">
+        <Enum name="RISING" start="0" description="A falling edge on MCI0 does not affect counter 1." />
+        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI0." />
+      </BitField>
+      <BitField start="8" size="1" name="TC1MCI1_RE" description="Counter 1 rising edge mode, channel 1.">
+        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 1." />
+        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI1." />
+      </BitField>
+      <BitField start="9" size="1" name="TC1MCI1_FE" description="Counter 1 falling edge mode, channel 1.">
+        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 1." />
+        <Enum name="FALLING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI1." />
+      </BitField>
+      <BitField start="10" size="1" name="TC1MCI2_RE" description="Counter 1 rising edge mode, channel 2.">
+        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI2 does not affect counter 1." />
+        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a rising edge on MCI2." />
+      </BitField>
+      <BitField start="11" size="1" name="TC1MCI2_FE" description="Counter 1 falling edge mode, channel 2.">
+        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI2 does not affect counter 1." />
+        <Enum name="RISING" start="1" description="If MODE1 is 1, counter 1 advances on a falling edge on MCI2." />
+      </BitField>
+      <BitField start="12" size="1" name="TC2MCI0_RE" description="Counter 2 rising edge mode, channel 0.">
+        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI0 does not affect counter 2." />
+        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI0." />
+      </BitField>
+      <BitField start="13" size="1" name="TC2MCI0_FE" description="Counter 2 falling edge mode, channel 0.">
+        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI0 does not affect counter 2." />
+        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI0." />
+      </BitField>
+      <BitField start="14" size="1" name="TC2MCI1_RE" description="Counter 2 rising edge mode, channel 1.">
+        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI1 does not affect counter 2." />
+        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI1." />
+      </BitField>
+      <BitField start="15" size="1" name="TC2MCI1_FE" description="Counter 2 falling edge mode, channel 1.">
+        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI1 does not affect counter 2." />
+        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI1." />
+      </BitField>
+      <BitField start="16" size="1" name="TC2MCI2_RE" description="Counter 2 rising edge mode, channel 2.">
+        <Enum name="NOEFFECT" start="0" description="A rising edge on MCI2 does not affect counter 2." />
+        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a rising edge on MCI2." />
+      </BitField>
+      <BitField start="17" size="1" name="TC2MCI2_FE" description="Counter 2 falling edge mode, channel 2.">
+        <Enum name="NOEFFECT" start="0" description="A falling edge on MCI2 does not affect counter 2." />
+        <Enum name="FALLING" start="1" description="If MODE2 is 1, counter 2 advances on a falling edge on MCI2." />
+      </BitField>
+      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
+      <BitField start="29" size="1" name="CNTR0" description="Channel 0 counter/timer mode.">
+        <Enum name="CHANNEL_0_IS_IN_TIME" start="0" description="Channel 0 is in timer mode." />
+        <Enum name="CHANNEL_0_IS_IN_COUN" start="1" description="Channel 0 is in counter mode." />
+      </BitField>
+      <BitField start="30" size="1" name="CNTR1" description="Channel 1 counter/timer mode.">
+        <Enum name="CHANNEL_1_IS_IN_TIME" start="0" description="Channel 1 is in timer mode." />
+        <Enum name="CHANNEL_1_IS_IN_COUN" start="1" description="Channel 1 is in counter mode." />
+      </BitField>
+      <BitField start="31" size="1" name="CNTR2" description="Channel 2 counter/timer mode.">
+        <Enum name="CHANNEL_2_IS_IN_TIME" start="0" description="Channel 2 is in timer mode." />
+        <Enum name="CHANNEL_2_IS_IN_COUN" start="1" description="Channel 2 is in counter mode." />
+      </BitField>
+    </Register>
+    <Register start="+0x060" size="4" name="CNTCON_SET" access="WriteOnly" description="Count Control set address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="TC0MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="1" size="1" name="TC0MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="2" size="1" name="TC0MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="3" size="1" name="TC0MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="4" size="1" name="TC0MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="5" size="1" name="TC0MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="6" size="1" name="TC1MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="7" size="1" name="TC1MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="8" size="1" name="TC1MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="9" size="1" name="TC1MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="10" size="1" name="TC1MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="11" size="1" name="TC1MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="12" size="1" name="TC2MCI0_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="13" size="1" name="TC2MCI0_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="14" size="1" name="TC2MCI1_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="15" size="1" name="TC2MCI1_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="16" size="1" name="TC2MCI2_RE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="17" size="1" name="TC2MCI2_FE_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
+      <BitField start="29" size="1" name="CNTR0_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="30" size="1" name="CNTR1_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+      <BitField start="31" size="1" name="CNTR2_SET" description="Writing a one sets the corresponding bit in the CNTCON register." />
+    </Register>
+    <Register start="+0x064" size="4" name="CNTCON_CLR" access="WriteOnly" description="Count Control clear address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="TC0MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="1" size="1" name="TC0MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="2" size="1" name="TC0MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="3" size="1" name="TC0MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="4" size="1" name="TC0MCI2_RE" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="5" size="1" name="TC0MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="6" size="1" name="TC1MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="7" size="1" name="TC1MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="8" size="1" name="TC1MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="9" size="1" name="TC1MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="10" size="1" name="TC1MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="11" size="1" name="TC1MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="12" size="1" name="TC2MCI0_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="13" size="1" name="TC2MCI0_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="14" size="1" name="TC2MCI1_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="15" size="1" name="TC2MCI1_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="16" size="1" name="TC2MCI2_RE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="17" size="1" name="TC2MCI2_FE_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="18" size="11" name="RESERVED" description="Reserved." />
+      <BitField start="29" size="1" name="CNTR0_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="30" size="1" name="CNTR1_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+      <BitField start="31" size="1" name="CNTR2_CLR" description="Writing a one clears the corresponding bit in the CNTCON register." />
+    </Register>
+    <Register start="+0x074" size="4" name="CAP_CLR" access="WriteOnly" description="Capture clear address" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CAP_CLR0" description="Writing a 1 to this bit clears the CAP0 register." />
+      <BitField start="1" size="1" name="CAP_CLR1" description="Writing a 1 to this bit clears the CAP1 register." />
+      <BitField start="2" size="1" name="CAP_CLR2" description="Writing a 1 to this bit clears the CAP2 register." />
+      <BitField start="3" size="29" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C0" start="0x400A1000" description="I2C-bus interface">
+    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
+      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
+      <BitField start="4" size="1" name="STO" description="STOP flag." />
+      <BitField start="5" size="1" name="STA" description="START flag." />
+      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
+      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
+      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
+      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
+        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
+        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
+      </BitField>
+      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
+        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
+        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
+      </BitField>
+      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
+        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
+        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
+    </Register>
+    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C1" start="0x400E0000" description="I2C-bus interface">
+    <Register start="+0x000" size="4" name="CONSET" access="Read/Write" description="I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="AA" description="Assert acknowledge flag." />
+      <BitField start="3" size="1" name="SI" description="I2C interrupt flag." />
+      <BitField start="4" size="1" name="STO" description="STOP flag." />
+      <BitField start="5" size="1" name="STA" description="START flag." />
+      <BitField start="6" size="1" name="I2EN" description="I2C interface enable." />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed." reset_value="0xF8" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="These bits are unused and are always 0." />
+      <BitField start="3" size="5" name="Status" description="These bits give the actual status information about the I 2C interface." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="DAT" access="Read/Write" description="I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Data" description="This register holds data values that have been received or are to be transmitted." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="ADR0" access="Read/Write" description="I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="SCLH" access="Read/Write" description="SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock." reset_value="0x04" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SCLH" description="Count for SCL HIGH time period selection." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="SCLL" access="Read/Write" description="SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode." reset_value="0x04" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SCLL" description="Count for SCL low time period selection." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="CONCLR" access="WriteOnly" description="I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="AAC" description="Assert acknowledge Clear bit." />
+      <BitField start="3" size="1" name="SIC" description="I2C interrupt Clear bit." />
+      <BitField start="4" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="5" size="1" name="STAC" description="START flag Clear bit." />
+      <BitField start="6" size="1" name="I2ENC" description="I2C interface Disable bit." />
+      <BitField start="7" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="MMCTRL" access="Read/Write" description="Monitor mode control register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MM_ENA" description="Monitor mode enable.">
+        <Enum name="MONITOR_MODE_DISABLE" start="0" description="Monitor mode disabled." />
+        <Enum name="THE_I_2C_MODULE_WILL" start="1" description="The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line." />
+      </BitField>
+      <BitField start="1" size="1" name="ENA_SCL" description="SCL output enable.">
+        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line." />
+        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]" />
+      </BitField>
+      <BitField start="2" size="1" name="MATCH_ALL" description="Select interrupt register match.">
+        <Enum name="WHEN_THIS_BIT_IS_CLE" start="0" description="When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned." />
+        <Enum name="WHEN_THIS_BIT_IS_SET" start="1" description="When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus." />
+      </BitField>
+      <BitField start="3" size="29" name="RESERVED" description="Reserved. The value read from reserved bits is not defined." />
+    </Register>
+    <Register start="+0x020+0" size="4" name="ADR1" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020+4" size="4" name="ADR2" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020+8" size="4" name="ADR3" access="Read/Write" description="I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="GC" description="General Call enable bit." />
+      <BitField start="1" size="7" name="Address" description="The I2C device address for slave mode." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="DATA_BUFFER" access="ReadOnly" description="Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Data" description="This register holds contents of the 8 MSBs of the DAT shift register." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+0" size="4" name="MASK0" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+4" size="4" name="MASK1" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+8" size="4" name="MASK2" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030+12" size="4" name="MASK3" access="Read/Write" description="I2C Slave address mask register" reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved. User software should not write ones to reserved bits. This bit reads always back as 0." />
+      <BitField start="1" size="7" name="MASK" description="Mask bits." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2S0" start="0x400A2000" description="I2S interface ">
+    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
+        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
+        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
+        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
+        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
+      </BitField>
+      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
+      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
+      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
+      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
+      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
+      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
+        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
+        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
+        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
+        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
+      </BitField>
+      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
+      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
+      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
+      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
+      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
+    </Register>
+    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
+    </Register>
+    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
+      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
+      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
+      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
+      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
+      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
+      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
+      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
+      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
+      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
+      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
+        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
+      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
+        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
+      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2S1" start="0x400A3000" description="I2S interface ">
+    <Register start="+0x000" size="4" name="DAO" access="Read/Write" description="I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel." reset_value="0x87E1" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
+        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
+        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
+        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
+        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
+      </BitField>
+      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
+      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
+      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously resets the transmit channel and FIFO." />
+      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE." />
+      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
+      <BitField start="15" size="1" name="MUTE" description="When 1, the transmit channel sends only zeroes." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="DAI" access="Read/Write" description="I2S Digital Audio Input Register. Contains control bits for the I2S receive channel." reset_value="0x07E1" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="WORDWIDTH" description="Selects the number of bytes in data as follows:">
+        <Enum name="8_BIT_DATA" start="0x0" description="8-bit data" />
+        <Enum name="16_BIT_DATA" start="0x1" description="16-bit data" />
+        <Enum name="RESERVED" start="0x2" description="Reserved, do not use this setting" />
+        <Enum name="32_BIT_DATA" start="0x3" description="32-bit data" />
+      </BitField>
+      <BitField start="2" size="1" name="MONO" description="When 1, data is of monaural format. When 0, the data is in stereo format." />
+      <BitField start="3" size="1" name="STOP" description="When 1, disables accesses on FIFOs, places the transmit channel in mute mode." />
+      <BitField start="4" size="1" name="RESET" description="When 1, asynchronously reset the transmit channel and FIFO." />
+      <BitField start="5" size="1" name="WS_SEL" description="When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE." />
+      <BitField start="6" size="9" name="WS_HALFPERIOD" description="Word select half period minus 1, i.e. WS 64clk period -&gt; ws_halfperiod = 31." />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="TXFIFO" access="WriteOnly" description="I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="I2STXFIFO" description="8 x 32-bit transmit FIFO." />
+    </Register>
+    <Register start="+0x00C" size="4" name="RXFIFO" access="None" description="I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="I2SRXFIFO" description="8 x 32-bit transmit FIFO." />
+    </Register>
+    <Register start="+0x010" size="4" name="STATE" access="ReadOnly" description="I2S Status Feedback Register. Contains status information about the I2S interface." reset_value="0x7" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="IRQ" description="This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register." />
+      <BitField start="1" size="1" name="DMAREQ1" description="This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register." />
+      <BitField start="2" size="1" name="DMAREQ2" description="This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register." />
+      <BitField start="3" size="5" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="4" name="RX_LEVEL" description="Reflects the current level of the Receive FIFO." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_LEVEL" description="Reflects the current level of the Transmit FIFO." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="DMA1" access="Read/Write" description="I2S DMA Configuration Register 1. Contains control information for DMA request 1." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S receive." />
+      <BitField start="1" size="1" name="TX_DMA1_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
+      <BitField start="2" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="4" name="RX_DEPTH_DMA1" description="Set the FIFO level that triggers a receive DMA request on DMA1." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_DEPTH_DMA1" description="Set the FIFO level that triggers a transmit DMA request on DMA1." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x018" size="4" name="DMA2" access="Read/Write" description="I2S DMA Configuration Register 2. Contains control information for DMA request 2." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S receive." />
+      <BitField start="1" size="1" name="TX_DMA2_ENABLE" description="When 1, enables DMA1 for I2S transmit." />
+      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="4" name="RX_DEPTH_DMA2" description="Set the FIFO level that triggers a receive DMA request on DMA2." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_DEPTH_DMA2" description="Set the FIFO level that triggers a transmit DMA request on DMA2." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="IRQ" access="Read/Write" description="I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RX_IRQ_ENABLE" description="When 1, enables I2S receive interrupt." />
+      <BitField start="1" size="1" name="TX_IRQ_ENABLE" description="When 1, enables I2S transmit interrupt." />
+      <BitField start="2" size="6" name="RESERVED" description="Reserved." />
+      <BitField start="8" size="4" name="RX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
+      <BitField start="12" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="16" size="4" name="TX_DEPTH_IRQ" description="Set the FIFO level on which to create an irq request." />
+      <BitField start="20" size="12" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x020" size="4" name="TXRATE" access="Read/Write" description="I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
+      <BitField start="8" size="8" name="X_DIVIDER" description="I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x024" size="4" name="RXRATE" access="Read/Write" description="I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="Y_DIVIDER" description="I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock." />
+      <BitField start="8" size="8" name="X_DIVIDER" description="I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x028" size="4" name="TXBITRATE" access="Read/Write" description="I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="TX_BITRATE" description="I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x02C" size="4" name="RXBITRATE" access="Read/Write" description="I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RX_BITRATE" description="I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x030" size="4" name="TXMODE" access="Read/Write" description="I2S Transmit mode control." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="TXCLKSEL" description="Clock source selection for the transmit bit clock divider.">
+        <Enum name="SELECT_THE_TX_FRACTI" start="0x0" description="Select the TX fractional rate divider clock output as the source" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="SELECT_THE_RX_MCLK_S" start="0x2" description="Select the RX_MCLK signal as the TX_MCLK clock source" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="2" size="1" name="TX4PIN" description="Transmit 4-pin mode selection. When 1, enables 4-pin mode." />
+      <BitField start="3" size="1" name="TXMCENA" description="Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x034" size="4" name="RXMODE" access="Read/Write" description="I2S Receive mode control." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RXCLKSEL" description="Clock source selection for the receive bit clock divider.">
+        <Enum name="SELECT_THE_RX_FRACTI" start="0x0" description="Select the RX fractional rate divider clock output as the source" />
+        <Enum name="RESERVED" start="0x1" description="Reserved" />
+        <Enum name="SELECT_THE_TX_MCLK_S" start="0x2" description="Select the TX_MCLK signal as the RX_MCLK clock source" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="2" size="1" name="RX4PIN" description="Receive 4-pin mode selection. When 1, enables 4-pin mode." />
+      <BitField start="3" size="1" name="RXMCENA" description="Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="C_CAN1" start="0x400A4000" description="C_CAN ">
+    <Register start="+0x000" size="4" name="CNTL" access="Read/Write" description="CAN control" reset_value="0x0001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INIT" description="Initialization">
+        <Enum name="INITIALIZATION_IS_ST" start="1" description="Initialization is started. On reset, software needs to initialize the CAN controller." />
+        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
+      </BitField>
+      <BitField start="1" size="1" name="IE" description="Module interrupt enable">
+        <Enum name="ENABLE_CAN_INTERRUPT" start="1" description="Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared." />
+        <Enum name="DISABLE_CAN_INTERRUP" start="0" description="Disable CAN interrupts. The interrupt line is always HIGH." />
+      </BitField>
+      <BitField start="2" size="1" name="SIE" description="Status change interrupt enable">
+        <Enum name="ENABLE_STATUS_CHANGE" start="1" description="Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected." />
+        <Enum name="DISABLE_STATUS_CHANG" start="0" description="Disable status change interrupts. No status change interrupt will be generated." />
+      </BitField>
+      <BitField start="3" size="1" name="EIE" description="Error interrupt enable">
+        <Enum name="ENABLE_ERROR_INTERRU" start="1" description="Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt." />
+        <Enum name="DISABLE_ERROR_INTERR" start="0" description="Disable error interrupt. No error status interrupt will be generated." />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="reserved" />
+      <BitField start="5" size="1" name="DAR" description="Disable automatic retransmission">
+        <Enum name="DISABLED" start="1" description="Automatic retransmission disabled." />
+        <Enum name="ENABLED" start="0" description="Automatic retransmission of disturbed messages enabled." />
+      </BitField>
+      <BitField start="6" size="1" name="CCE" description="Configuration change enable">
+        <Enum name="THE_CPU_HAS_WRITE_AC" start="1" description="The CPU has write access to the CANBT register while the INIT bit is one." />
+        <Enum name="THE_CPU_HAS_NO_WRITE" start="0" description="The CPU has no write access to the bit timing register." />
+      </BitField>
+      <BitField start="7" size="1" name="TEST" description="Test mode enable">
+        <Enum name="TEST_MODE_" start="1" description="Test mode." />
+        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="STAT" access="Read/Write" description="Status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="LEC" description="Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates.">
+        <Enum name="NO_ERROR_" start="0x0" description="No error." />
+        <Enum name="STUFF_ERROR_MORE_TH" start="0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." />
+        <Enum name="FORM_ERROR_A_FIXED_" start="0x2" description="Form error: A fixed format part of a received frame has the wrong format." />
+        <Enum name="ACKERROR_THE_MESSAG" start="0x3" description="AckError: The message this CAN core transmitted was not acknowledged." />
+        <Enum name="BIT1ERROR_DURING_TH" start="0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant." />
+        <Enum name="BIT0ERROR_DURING_TH" start="0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)." />
+        <Enum name="CRCERROR_THE_CRC_CH" start="0x6" description="CRCError: The CRC checksum was incorrect in the message received." />
+        <Enum name="UNUSED_NO_CAN_BUS_E" start="0x7" description="Unused: No CAN bus event was detected (written by the CPU)." />
+      </BitField>
+      <BitField start="3" size="1" name="TXOK" description="Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
+        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)." />
+        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was reset by the CPU, no message has been successfully transmitted." />
+      </BitField>
+      <BitField start="4" size="1" name="RXOK" description="Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
+        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering." />
+        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was last reset by the CPU, no message has been successfully transmitted." />
+      </BitField>
+      <BitField start="5" size="1" name="EPASS" description="Error passive">
+        <Enum name="PASSIVE" start="1" description="The CAN controller is in the error passive state as defined in the  CAN 2.0 specification." />
+        <Enum name="ACTIVE" start="0" description="The CAN controller is in the error active state." />
+      </BitField>
+      <BitField start="6" size="1" name="EWARN" description="Warning status">
+        <Enum name="AT_LEAST_ONE_OF_THE_" start="1" description="At least one of the error counters in the EML has reached the error warning limit of 96." />
+        <Enum name="BOTH_ERROR_COUNTERS_" start="0" description="Both error counters are below the error warning limit of 96." />
+      </BitField>
+      <BitField start="7" size="1" name="BOFF" description="Busoff status">
+        <Enum name="BUSOFF" start="1" description="The CAN controller is in busoff state." />
+        <Enum name="NOBUSOFF" start="0" description="The CAN module is not in busoff." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x008" size="4" name="EC" access="ReadOnly" description="Error counter" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="TEC_7_0" description="Transmit error counter Current value of the transmit error counter (maximum value 127)" />
+      <BitField start="8" size="7" name="REC_6_0" description="Receive error counter Current value of the receive error counter (maximum value 255)." />
+      <BitField start="15" size="1" name="RP" description="Receive error passive">
+        <Enum name="PASSIVE" start="1" description="The receive counter has reached the error passive level as defined in the  CAN2.0 specification." />
+        <Enum name="BELOWPASSIVE" start="0" description="The receive counter is below the error passive level." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x00C" size="4" name="BT" access="Read/Write" description="Bit timing register" reset_value="0x2301" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="BRP" description="Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1].  Valid programmed values are 0x01 - 0x3F[1]." />
+      <BitField start="6" size="2" name="SJW" description="(Re)synchronization jump width Valid programmed values are 0 to 3[1]." />
+      <BitField start="8" size="4" name="TSEG1" description="Time segment after the sample point Valid values are 0 to 7[1]." />
+      <BitField start="12" size="3" name="TSEG2" description="Time segment before the sample point Valid values are 1 to 15[1]." />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x010" size="4" name="INT" access="ReadOnly" description="Interrupt register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="INTID15_0" description="0x0000= No interrupt is pending 0x0001 to 0x0020 = Number of message object which caused the interrupt. 0x0021 to 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 to 0xFFFF = Unused" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x014" size="4" name="TEST" access="Read/Write" description="Test register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="RESERVED" description="tbd." />
+      <BitField start="2" size="1" name="BASIC" description="Basic mode">
+        <Enum name="IF1_TX_if2_rx" start="1" description="IF1 registers used as TX buffer, IF2 registers used as RX buffer." />
+        <Enum name="BASIC_MODE_DISABLED_" start="0" description="Basic mode disabled." />
+      </BitField>
+      <BitField start="3" size="1" name="SILENT" description="Silent mode">
+        <Enum name="SILENT" start="1" description="The module is in silent mode." />
+        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
+      </BitField>
+      <BitField start="4" size="1" name="LBACK" description="Loop back mode">
+        <Enum name="ENABLED" start="1" description="Loop back mode is enabled." />
+        <Enum name="DISABLED" start="0" description="Loop back mode is disabled." />
+      </BitField>
+      <BitField start="5" size="2" name="TX1_0" description="Control of TD pins">
+        <Enum name="LEVEL_AT_THE_TD_PIN_" start="0x0" description="Level at the TD pin is controlled by the CAN controller. This is the value at reset." />
+        <Enum name="THE_SAMPLE_POINT_CAN" start="0x1" description="The sample point can be monitored at the TD pin." />
+        <Enum name="TD_PIN_IS_DRIVEN_LOW" start="0x2" description="TD pin is driven LOW/dominant." />
+        <Enum name="TD_PIN_IS_DRIVEN_HIG" start="0x3" description="TD pin is driven HIGH/recessive." />
+      </BitField>
+      <BitField start="7" size="1" name="RX" description="Monitors the actual value of the RD Pin">
+        <Enum name="THE_CAN_BUS_IS_RECES" start="1" description="The CAN bus is recessive (RD = 1)." />
+        <Enum name="THE_CAN_BUS_IS_DOMIN" start="0" description="The CAN bus is dominant (RD = 0)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x018" size="4" name="BRPE" access="Read/Write" description="Baud rate prescaler extension register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="BRPE" description="Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020+0" size="4" name="IF1_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
+      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
+      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020+96" size="4" name="IF2_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
+      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
+      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
+        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
+      </BitField>
+      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
+        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
+      </BitField>
+      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
+        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
+        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
+      </BitField>
+      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
+      <BitField start="4" size="1" name="CTRL" description="Access control bits">
+        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
+        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
+      </BitField>
+      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
+        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
+        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
+      </BitField>
+      <BitField start="6" size="1" name="MASK" description="Access mask bits">
+        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
+        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
+      </BitField>
+      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
+        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
+      </BitField>
+      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
+        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
+      </BitField>
+      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
+        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
+        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
+      </BitField>
+      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
+      <BitField start="4" size="1" name="CTRL" description="Access control bits">
+        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
+        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
+      </BitField>
+      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
+        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
+        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
+      </BitField>
+      <BitField start="6" size="1" name="MASK" description="Access mask bits">
+        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
+        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
+      </BitField>
+      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
+        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
+      </BitField>
+      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
+        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
+      </BitField>
+      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
+        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
+        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
+      </BitField>
+      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
+        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
+        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
+      </BitField>
+      <BitField start="4" size="1" name="CTRL" description="Access control bits">
+        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
+        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
+      </BitField>
+      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
+        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
+        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
+      </BitField>
+      <BitField start="6" size="1" name="MASK" description="Access mask bits">
+        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
+        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
+      </BitField>
+      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
+        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
+      </BitField>
+      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
+        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
+      </BitField>
+      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
+        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
+        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
+      </BitField>
+      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
+        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
+        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
+      </BitField>
+      <BitField start="4" size="1" name="CTRL" description="Access control bits">
+        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
+        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
+      </BitField>
+      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
+        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
+        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
+      </BitField>
+      <BitField start="6" size="1" name="MASK" description="Access mask bits">
+        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
+        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
+      </BitField>
+      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x028+0" size="4" name="IF1_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
+      <BitField start="16" size="16" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x028+96" size="4" name="IF2_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
+      <BitField start="16" size="16" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x02C+0" size="4" name="IF1_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
+        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
+        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
+      </BitField>
+      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
+        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
+        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x02C+96" size="4" name="IF2_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
+        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
+        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
+      </BitField>
+      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
+        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
+        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x030+0" size="4" name="IF1_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x030+96" size="4" name="IF2_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x034+0" size="4" name="IF1_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
+      <BitField start="13" size="1" name="DIR" description="Message direction">
+        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
+        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
+      </BitField>
+      <BitField start="14" size="1" name="XTD" description="Extend identifier">
+        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
+        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
+      </BitField>
+      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
+        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
+        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x034+96" size="4" name="IF2_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
+      <BitField start="13" size="1" name="DIR" description="Message direction">
+        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
+        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
+      </BitField>
+      <BitField start="14" size="1" name="XTD" description="Extend identifier">
+        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
+        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
+      </BitField>
+      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
+        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
+        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x038+0" size="4" name="IF1_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
+      <BitField start="4" size="3" name="RESERVED" description="reserved" />
+      <BitField start="7" size="1" name="EOB" description="End of buffer">
+        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
+        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
+      </BitField>
+      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
+        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
+        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
+      </BitField>
+      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
+        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
+        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
+      </BitField>
+      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
+        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
+        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
+      </BitField>
+      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
+        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
+        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
+      </BitField>
+      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
+        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
+        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
+      </BitField>
+      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
+        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
+        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
+      </BitField>
+      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
+        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
+        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
+      </BitField>
+      <BitField start="15" size="1" name="NEWDAT" description="New data">
+        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
+        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x038+96" size="4" name="IF2_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
+      <BitField start="4" size="3" name="RESERVED" description="reserved" />
+      <BitField start="7" size="1" name="EOB" description="End of buffer">
+        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
+        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
+      </BitField>
+      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
+        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
+        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
+      </BitField>
+      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
+        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
+        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
+      </BitField>
+      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
+        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
+        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
+      </BitField>
+      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
+        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
+        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
+      </BitField>
+      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
+        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
+        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
+      </BitField>
+      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
+        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
+        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
+      </BitField>
+      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
+        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
+        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
+      </BitField>
+      <BitField start="15" size="1" name="NEWDAT" description="New data">
+        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
+        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x03C+0" size="4" name="IF1_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
+      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x03C+96" size="4" name="IF2_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
+      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x040+0" size="4" name="IF1_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
+      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x040+96" size="4" name="IF2_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
+      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x044+0" size="4" name="IF1_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
+      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x044+96" size="4" name="IF2_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
+      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x048+0" size="4" name="IF1_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
+      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x048+96" size="4" name="IF2_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
+      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x100" size="4" name="TXREQ1" access="ReadOnly" description="Transmission request 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TXRQST16_1" description="Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x104" size="4" name="TXREQ2" access="ReadOnly" description="Transmission request 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TXRQST32_17" description="Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x120" size="4" name="ND1" access="ReadOnly" description="New data 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="NEWDAT16_1" description="New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x124" size="4" name="ND2" access="ReadOnly" description="New data 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="NEWDAT32_17" description="New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x140" size="4" name="IR1" access="ReadOnly" description="Interrupt pending 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="INTPND16_1" description="Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x144" size="4" name="IR2" access="ReadOnly" description="Interrupt pending 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="INTPND32_17" description="Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x160" size="4" name="MSGV1" access="ReadOnly" description="Message valid 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MSGVAL16_1" description="Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x164" size="4" name="MSGV2" access="ReadOnly" description="Message valid 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MSGVAL32_17" description="Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x180" size="4" name="CLKDIV" access="Read/Write" description="CAN clock divider register" reset_value="0x0001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="CLKDIVVAL" description="&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Clock divider value &#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;CAN_CLK = PCLK/(CLKDIVVAL +1)&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0000: CAN_CLK = PCLK divided by 1.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0001: CAN_CLK = PCLK divided by 2.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0010: CAN_CLK = PCLK divided by 3.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0011: CAN_CLK = PCLK divided by 4.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0100: CAN_CLK = PCLK divided by 5.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;...&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;1111: CAN_CLK = PCLK divided by 16.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;" />
+      <BitField start="4" size="28" name="RESERVED" description="reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RITIMER" start="0x400C0000" description="Repetitive Interrupt Timer (RIT) ">
+    <Register start="+0x000" size="4" name="COMPVAL" access="Read/Write" description="Compare register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RICOMP" description="Compare register. Holds the compare value which is compared to the counter." />
+    </Register>
+    <Register start="+0x004" size="4" name="MASK" access="Read/Write" description="Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RIMASK" description="Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true)." />
+    </Register>
+    <Register start="+0x008" size="4" name="CTRL" access="Read/Write" description="Control register." reset_value="0xC" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RITINT" description="Interrupt flag">
+        <Enum name="THIS_BIT_IS_SET_TO_1" start="1" description="This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect." />
+        <Enum name="THE_COUNTER_VALUE_DO" start="0" description="The counter value does not equal the masked compare value." />
+      </BitField>
+      <BitField start="1" size="1" name="RITENCLR" description="Timer enable clear">
+        <Enum name="THE_TIMER_WILL_BE_CL" start="1" description="The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag." />
+        <Enum name="THE_TIMER_WILL_NOT_B" start="0" description="The timer will not be cleared to 0." />
+      </BitField>
+      <BitField start="2" size="1" name="RITENBR" description="Timer enable for debug">
+        <Enum name="THE_TIMER_IS_HALTED_" start="1" description="The timer is halted when the processor is halted for debugging." />
+        <Enum name="DEBUG_HAS_NO_EFFECT_" start="0" description="Debug has no effect on the timer operation." />
+      </BitField>
+      <BitField start="3" size="1" name="RITEN" description="Timer enable.">
+        <Enum name="TIMER_ENABLED_THIS_" start="1" description="Timer enabled. This can be overruled by a debug halt if enabled in bit 2." />
+        <Enum name="TIMER_DISABLED_" start="0" description="Timer disabled." />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="COUNTER" access="Read/Write" description="32-bit counter" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="RICOUNTER" description="32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="QEI" start="0x400C6000" description="Quadrature Encoder Interface (QEI) ">
+    <Register start="+0x000" size="4" name="CON" access="WriteOnly" description="Control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESP" description="Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared." />
+      <BitField start="1" size="1" name="RESPI" description="Reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs. Autoclears when the position counter is cleared." />
+      <BitField start="2" size="1" name="RESV" description="Reset velocity. When set = 1, resets the velocity counter to all zeros and reloads the velocity timer. Autoclears when the velocity counter is cleared." />
+      <BitField start="3" size="1" name="RESI" description="Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared." />
+      <BitField start="4" size="28" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x008" size="4" name="CONF" access="Read/Write" description="Configuration register" reset_value="0x000F0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRINV" description="Direction invert. When = 1, complements the DIR bit." />
+      <BitField start="1" size="1" name="SIGMODE" description="Signal Mode. When = 0, PhA and PhB function as quadrature encoder inputs. When = 1, PhA functions as the direction signal and PhB functions as the clock signal." />
+      <BitField start="2" size="1" name="CAPMODE" description="Capture Mode. When = 0, only PhA edges are counted (2X). When = 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range." />
+      <BitField start="3" size="1" name="INVINX" description="Invert Index. When set, inverts the sense of the index input." />
+      <BitField start="4" size="1" name="CRESPI" description="Continuously reset position counter on index. When set = 1, resets the position counter to all zeros when an index pulse occurs at the next position increase (recalibration). Auto-clears when the position counter is cleared." />
+      <BitField start="5" size="11" name="RESERVED" description="Reserved" />
+      <BitField start="16" size="4" name="INXGATE" description="Index gating configuration: when INXGATE(19)=1, pass the index when Pha=0 and Phb=0, else block. when INXGATE(18)=1, pass the index when Pha=0 and Phb=1, else block. when INXGATE(17)=1, pass the index when Pha=1 and Phb=1, else block. when INXGATE(16)=1, pass the index when Pha=1 and Phb=0, else block." />
+      <BitField start="20" size="12" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="STAT" access="ReadOnly" description="Encoder status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIR" description="Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 516." />
+      <BitField start="1" size="31" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x00C" size="4" name="POS" access="ReadOnly" description="Position register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="POS" description="Current position value." />
+    </Register>
+    <Register start="+0x010" size="4" name="MAXPOS" access="Read/Write" description="Maximum position register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MAXPOS" description="Maximum position value." />
+    </Register>
+    <Register start="+0x014" size="4" name="CMPOS0" access="Read/Write" description="position compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PCMP0" description="Position compare value 0." />
+    </Register>
+    <Register start="+0x018" size="4" name="CMPOS1" access="Read/Write" description="position compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PCMP1" description="Position compare value 1." />
+    </Register>
+    <Register start="+0x01C" size="4" name="CMPOS2" access="Read/Write" description="position compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PCMP2" description="Position compare value 2." />
+    </Register>
+    <Register start="+0x020" size="4" name="INXCNT" access="ReadOnly" description="Index count register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="ENCPOS" description="Current encoder position value." />
+    </Register>
+    <Register start="+0x024" size="4" name="INXCMP0" access="Read/Write" description="Index compare register 0" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="ICMP0" description="Index compare value." />
+    </Register>
+    <Register start="+0x028" size="4" name="LOAD" access="Read/Write" description="Velocity timer reload register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="VELLOAD" description="Current velocity timer load value." />
+    </Register>
+    <Register start="+0x02C" size="4" name="TIME" access="ReadOnly" description="Velocity timer register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="VELVAL" description="Current velocity timer value." />
+    </Register>
+    <Register start="+0x030" size="4" name="VEL" access="ReadOnly" description="Velocity counter register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="VELPC" description="Current velocity pulse count." />
+    </Register>
+    <Register start="+0x034" size="4" name="CAP" access="ReadOnly" description="Velocity capture register" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="VELCAP" description="Velocity capture value." />
+    </Register>
+    <Register start="+0x038" size="4" name="VELCOMP" access="Read/Write" description="Velocity compare register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="VELCMP" description="Velocity compare value." />
+    </Register>
+    <Register start="+0x03C" size="4" name="FILTERPHA" access="Read/Write" description="Digital filter register on input phase A (QEI_A)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="FILTA" description="Digital filter sampling delay" />
+    </Register>
+    <Register start="+0x040" size="4" name="FILTERPHB" access="Read/Write" description="Digital filter register on input phase B (QEI_B)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="FILTB" description="Digital filter sampling delay" />
+    </Register>
+    <Register start="+0x044" size="4" name="FILTERINX" access="Read/Write" description="Digital filter register on input index (QEI_IDX)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="FITLINX" description="Digital filter sampling delay" />
+    </Register>
+    <Register start="+0x048" size="4" name="WINDOW" access="Read/Write" description="Index acceptance window register" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="WINDOW" description="Index acceptance window width" />
+    </Register>
+    <Register start="+0x04C" size="4" name="INXCMP1" access="Read/Write" description="Index compare register 1" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="ICMP1" description="Index compare value 1." />
+    </Register>
+    <Register start="+0x050" size="4" name="INXCMP2" access="Read/Write" description="Index compare register 2" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="ICMP2" description="Index compare value 2." />
+    </Register>
+    <Register start="+0xFD8" size="4" name="IEC" access="WriteOnly" description="Interrupt enable clear register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INX_EN" description="Indicates that an index pulse was detected." />
+      <BitField start="1" size="1" name="TIM_EN" description="Indicates that a velocity timer overflow occurred" />
+      <BitField start="2" size="1" name="VELC_EN" description="Indicates that captured velocity is less than compare velocity." />
+      <BitField start="3" size="1" name="DIR_EN" description="Indicates that a change of direction was detected." />
+      <BitField start="4" size="1" name="ERR_EN" description="Indicates that an encoder phase error was detected." />
+      <BitField start="5" size="1" name="ENCLK_EN" description="Indicates that and encoder clock pulse was detected." />
+      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
+      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
+      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
+      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
+      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
+      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
+      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
+      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
+      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
+      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xFDC" size="4" name="IES" access="WriteOnly" description="Interrupt enable set register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INX_EN" description="Indicates that an index pulse was detected." />
+      <BitField start="1" size="1" name="TIM_EN" description="Indicates that a velocity timer overflow occurred" />
+      <BitField start="2" size="1" name="VELC_EN" description="Indicates that captured velocity is less than compare velocity." />
+      <BitField start="3" size="1" name="DIR_EN" description="Indicates that a change of direction was detected." />
+      <BitField start="4" size="1" name="ERR_EN" description="Indicates that an encoder phase error was detected." />
+      <BitField start="5" size="1" name="ENCLK_EN" description="Indicates that and encoder clock pulse was detected." />
+      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
+      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
+      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
+      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
+      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
+      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
+      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
+      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
+      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
+      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xFE0" size="4" name="INTSTAT" access="ReadOnly" description="Interrupt status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
+      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
+      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
+      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
+      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
+      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
+      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
+      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
+      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
+      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
+      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
+      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
+      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
+      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
+      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
+      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xFE4" size="4" name="IE" access="ReadOnly" description="Interrupt enable register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
+      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
+      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
+      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
+      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
+      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
+      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
+      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
+      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
+      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
+      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
+      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
+      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
+      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
+      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
+      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xFE8" size="4" name="CLR" access="WriteOnly" description="Interrupt status clear register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
+      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
+      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
+      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
+      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
+      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
+      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
+      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
+      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
+      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
+      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
+      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
+      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
+      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
+      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0xFEC" size="4" name="SET" access="WriteOnly" description="Interrupt status set register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INX_Int" description="Indicates that an index pulse was detected." />
+      <BitField start="1" size="1" name="TIM_Int" description="Indicates that a velocity timer overflow occurred" />
+      <BitField start="2" size="1" name="VELC_Int" description="Indicates that captured velocity is less than compare velocity." />
+      <BitField start="3" size="1" name="DIR_Int" description="Indicates that a change of direction was detected." />
+      <BitField start="4" size="1" name="ERR_Int" description="Indicates that an encoder phase error was detected." />
+      <BitField start="5" size="1" name="ENCLK_Int" description="Indicates that and encoder clock pulse was detected." />
+      <BitField start="6" size="1" name="POS0_Int" description="Indicates that the position 0 compare value is equal to the current position." />
+      <BitField start="7" size="1" name="POS1_Int" description="Indicates that the position 1compare value is equal to the current position." />
+      <BitField start="8" size="1" name="POS2_Int" description="Indicates that the position 2 compare value is equal to the current position." />
+      <BitField start="9" size="1" name="REV_Int" description="Indicates that the index compare value is equal to the current index count." />
+      <BitField start="10" size="1" name="POS0REV_Int" description="Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set." />
+      <BitField start="11" size="1" name="POS1REV_Int" description="Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set." />
+      <BitField start="12" size="1" name="POS2REV_Int" description="Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set." />
+      <BitField start="13" size="1" name="REV1_Int" description="Indicates that the index 1 compare value is equal to the current index count." />
+      <BitField start="14" size="1" name="REV2_Int" description="Indicates that the index 2 compare value is equal to the current index count." />
+      <BitField start="15" size="1" name="MAXPOS_Int" description="Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GIMA" start="0x400C7000" description="Global Input Multiplexer Array (GIMA)">
+    <Register start="+0x000" size="4" name="CAP0_0_IN" access="Read/Write" description="Timer 0 CAP0_0 capture input multiplexer (GIMA output 0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
+        <Enum name="SGPIO3" start="0x1" description="SGPIO3" />
+        <Enum name="T0_CAP0" start="0x2" description="T0_CAP0" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="CAP0_1_IN" access="Read/Write" description="Timer 0 CAP0_1 capture input multiplexer (GIMA output 1)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
+        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
+        <Enum name="T0_CAP1" start="0x2" description="T0_CAP1" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x008" size="4" name="CAP0_2_IN" access="Read/Write" description="Timer 0 CAP0_2 capture input multiplexer (GIMA output 2)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_2" start="0x0" description="CTIN_2" />
+        <Enum name="SGPIO3_DIV" start="0x1" description="SGPIO3_DIV" />
+        <Enum name="T0_CAP2" start="0x2" description="T0_CAP2" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x00C" size="4" name="CAP0_3_IN" access="Read/Write" description="Timer 0 CAP0_3 capture input multiplexer (GIMA output 3)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTOUT_15_OR_T3_MAT3" start="0x0" description="CTOUT_15 or T3_MAT3" />
+        <Enum name="T0_CAP3" start="0x1" description="T0_CAP3" />
+        <Enum name="T3_MAT3" start="0x2" description="T3_MAT3" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x010" size="4" name="CAP1_0_IN" access="Read/Write" description="Timer 1 CAP1_0 capture input multiplexer (GIMA output 4)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
+        <Enum name="SGPIO12" start="0x1" description="SGPIO12" />
+        <Enum name="T1_CAP0" start="0x2" description="T1_CAP0" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x014" size="4" name="CAP1_1_IN" access="Read/Write" description="Timer 1 CAP1_1 capture input multiplexer (GIMA output 5)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_3" start="0x0" description="CTIN_3" />
+        <Enum name="USART0_TX_ACTIVE" start="0x1" description="USART0 TX active" />
+        <Enum name="T1_CAP1" start="0x2" description="T1_CAP1" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x018" size="4" name="CAP1_2_IN" access="Read/Write" description="Timer 1 CAP1_2 capture input multiplexer (GIMA output 6)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_4" start="0x0" description="CTIN_4" />
+        <Enum name="USART0_RX_ACTIVE" start="0x1" description="USART0 RX active" />
+        <Enum name="T1_CAP2" start="0x2" description="T1_CAP2" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x01C" size="4" name="CAP1_3_IN" access="Read/Write" description="Timer 1 CAP1_3 capture input multiplexer (GIMA output 7)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTOUT_3_OR_T0_MAT3" start="0x0" description="CTOUT_3 or T0_MAT3" />
+        <Enum name="T1_CAP3" start="0x1" description="T1_CAP3" />
+        <Enum name="T0_MAT3" start="0x2" description="T0_MAT3" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020" size="4" name="CAP2_0_IN" access="Read/Write" description="Timer 2 CAP2_0 capture input multiplexer (GIMA output 8)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
+        <Enum name="SGPIO12_DIV" start="0x1" description="SGPIO12_DIV" />
+        <Enum name="T2_CAP0" start="0x2" description="T2_CAP0" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x024" size="4" name="CAP2_1_IN" access="Read/Write" description="Timer 2 CAP2_1 capture input multiplexer (GIMA output 9)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
+        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
+        <Enum name="_I2S1_RX_MWS" start="0x2" description="- I2S1_RX_MWS" />
+        <Enum name="T2_CAP1" start="0x3" description="T2_CAP1" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x028" size="4" name="CAP2_2_IN" access="Read/Write" description="Timer 2 CAP2_2 capture input multiplexer (GIMA output 10)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTIN_5" start="0x0" description="CTIN_5" />
+        <Enum name="USART2_RX_ACTIVE" start="0x1" description="USART2 RX active" />
+        <Enum name="_I2S1_TX_MWS" start="0x2" description="- I2S1_TX_MWS" />
+        <Enum name="T2_CAP2" start="0x3" description="T2_CAP2" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x02C" size="4" name="CAP2_3_IN" access="Read/Write" description="Timer 2 CAP2_3 capture input multiplexer (GIMA output 11)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTOUT_7_OR_T1_MAT3" start="0x0" description="CTOUT_7 or T1_MAT3" />
+        <Enum name="T2_CAP3" start="0x1" description="T2_CAP3" />
+        <Enum name="T1_MAT3" start="0x2" description="T1_MAT3" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x030" size="4" name="CAP3_0_IN" access="Read/Write" description="Timer 3 CAP3_0 capture input multiplexer (GIMA output 12)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
+        <Enum name="I2S0_RX_MWS" start="0x1" description="I2S0_RX_MWS" />
+        <Enum name="T3_CAP0" start="0x2" description="T3_CAP0" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x034" size="4" name="CAP3_1_IN" access="Read/Write" description="Timer 3 CAP3_1 capture input multiplexer (GIMA output 13)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTIN_6" start="0x0" description="CTIN_6" />
+        <Enum name="USART3_TX_ACTIVE" start="0x1" description="USART3 TX active" />
+        <Enum name="TBD__I2S0_TX_MWS" start="0x2" description="TBD - I2S0_TX_MWS" />
+        <Enum name="T3_CAP1" start="0x3" description="T3_CAP1" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x038" size="4" name="CAP3_2_IN" access="Read/Write" description="Timer 3 CAP3_2 capture input multiplexer (GIMA output 14)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTIN_7" start="0x0" description="CTIN_7" />
+        <Enum name="USART3_RX_ACTIVE" start="0x1" description="USART3 RX active" />
+        <Enum name="SOF0_START_OF_FRAME" start="0x2" description="SOF0 (Start-Of-Frame USB0)" />
+        <Enum name="T3_CAP2" start="0x3" description="T3_CAP2" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x03C" size="4" name="CAP3_3_IN" access="Read/Write" description="Timer 3 CAP3_3 capture input multiplexer (GIMA output 15)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTOUT11_OR_T2_MAT3" start="0x0" description="CTOUT11 or T2_MAT3" />
+        <Enum name="SOF1_START_OF_FRAME" start="0x1" description="SOF1 (Start-Of-Frame USB1)" />
+        <Enum name="T3_CAP3" start="0x2" description="T3_CAP3" />
+        <Enum name="T2_MAT3" start="0x3" description="T2_MAT3" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x040" size="4" name="CTIN_0_IN" access="Read/Write" description="SCT CTIN_0 capture input multiplexer (GIMA output 16)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_0" start="0x0" description="CTIN_0" />
+        <Enum name="SGPIO3" start="0x1" description="SGPIO3" />
+        <Enum name="SGPIO3_DIV" start="0x2" description="SGPIO3_DIV" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x044" size="4" name="CTIN_1_IN" access="Read/Write" description="SCT CTIN_1 capture input multiplexer (GIMA output 17)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_1" start="0x0" description="CTIN_1" />
+        <Enum name="USART2_TX_ACTIVE" start="0x1" description="USART2 TX active" />
+        <Enum name="SGPIO12" start="0x2" description="SGPIO12" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x048" size="4" name="CTIN_2_IN" access="Read/Write" description="SCT CTIN_2 capture input multiplexer (GIMA output 18)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_2" start="0x0" description="CTIN_2" />
+        <Enum name="SGPIO12" start="0x1" description="SGPIO12" />
+        <Enum name="SGPIO12_DIV" start="0x2" description="SGPIO12_DIV" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x04C" size="4" name="CTIN_3_IN" access="Read/Write" description="SCT CTIN_3 capture input multiplexer (GIMA output 19)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTIN_3" start="0x0" description="CTIN_3" />
+        <Enum name="USART0_TX_ACTIVE" start="0x1" description="USART0 TX active" />
+        <Enum name="RESERVED" start="0x2" description="Reserved" />
+        <Enum name="RESERVED" start="0x3" description="Reserved" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x050" size="4" name="CTIN_4_IN" access="Read/Write" description="SCT CTIN_4 capture input multiplexer (GIMA output 20)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTIN_4" start="0x0" description="CTIN_4" />
+        <Enum name="USART0_RX_ACTIVE" start="0x1" description="USART0 RX active" />
+        <Enum name="_I2S1_RX_MWS1" start="0x2" description="- I2S1_RX_MWS1" />
+        <Enum name="_I2S1_TX_MWS1" start="0x3" description="- I2S1_TX_MWS1" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x054" size="4" name="CTIN_5_IN" access="Read/Write" description="SCT CTIN_5 capture input multiplexer (GIMA output 21)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTIN_5" start="0x0" description="CTIN_5" />
+        <Enum name="USART2_RX_ACTIVE" start="0x1" description="USART2 RX active" />
+        <Enum name="SGPIO12_DIV" start="0x2" description="SGPIO12_DIV" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x058" size="4" name="CTIN_6_IN" access="Read/Write" description="SCT CTIN_6 capture input multiplexer (GIMA output 22)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTIN_6" start="0x0" description="CTIN_6" />
+        <Enum name="USART3_TX_ACTIVE" start="0x1" description="USART3 TX active" />
+        <Enum name="I2S0_RX_MWS" start="0x2" description="I2S0_RX_MWS" />
+        <Enum name="I2S0_TX_MWS" start="0x3" description="I2S0_TX_MWS" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x05C" size="4" name="CTIN_7_IN" access="Read/Write" description="SCT CTIN_7 capture input multiplexer (GIMA output 23)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x4 to 0xF are reserved.">
+        <Enum name="CTIN_7" start="0x0" description="CTIN_7" />
+        <Enum name="USART3_RX_ACTIVE" start="0x1" description="USART3 RX active" />
+        <Enum name="SOF0_START_OF_FRAME" start="0x2" description="SOF0 (Start-Of-Frame USB0)" />
+        <Enum name="SOF1_START_OF_FRAME" start="0x3" description="SOF1 (Start-Of-Frame USB1)" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x060" size="4" name="ADCHS_TRIGGER_IN" access="Read/Write" description="ADCHS trigger input multiplexer (GIMA output 24)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0xA to 0xF are reserved.">
+        <Enum name="GPIO6_28" start="0x0" description="GPIO6[28]" />
+        <Enum name="GPIO5_3" start="0x1" description="GPIO5[3]" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO12" start="0x3" description="SGPIO12" />
+        <Enum name="RESERVED" start="0x4" description="Reserved" />
+        <Enum name="MCOB2" start="0x5" description="MCOB2" />
+        <Enum name="CTOUT_0_OR_T0_MAT0" start="0x6" description="CTOUT_0 or T0_MAT0" />
+        <Enum name="CTOUT_8_OR_T2_MAT0" start="0x7" description="CTOUT_8 or T2_MAT0" />
+        <Enum name="T0_MAT0" start="0x8" description="T0_MAT0" />
+        <Enum name="T2_MAT0" start="0x9" description="T2_MAT0" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x064" size="4" name="EVENTROUTER_13_IN" access="Read/Write" description="Event router   input 13 multiplexer (GIMA output 25)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTOUT_2_OR_T0_MAT2" start="0x0" description="CTOUT_2 or T0_MAT2" />
+        <Enum name="SGPIO3" start="0x1" description="SGPIO3" />
+        <Enum name="T0_MAT2" start="0x2" description="T0_MAT2" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x068" size="4" name="EVENTROUTER_14_IN" access="Read/Write" description="Event router   input 14 multiplexer (GIMA output 26)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x3 to 0xF are reserved.">
+        <Enum name="CTOUT_6_OR_T1_MAT2" start="0x0" description="CTOUT_6 or T1_MAT2" />
+        <Enum name="SGPIO12" start="0x1" description="SGPIO12" />
+        <Enum name="T1_MAT2" start="0x2" description="T1_MAT2" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x06C" size="4" name="EVENTROUTER_16_IN" access="Read/Write" description="Event router   input 16 multiplexer (GIMA output 27)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
+        <Enum name="CTOUT_14_OR_T3_MAT2" start="0x0" description="CTOUT_14 or T3_MAT2" />
+        <Enum name="T3_MAT2" start="0x1" description="T3_MAT2" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x070" size="4" name="ADCSTART0_IN" access="Read/Write" description="ADC start0   input   multiplexer (GIMA output 28)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
+        <Enum name="CTOUT_15_OR_T3_MAT3" start="0x0" description="CTOUT_15 or T3_MAT3" />
+        <Enum name="T0_MAT0" start="0x1" description="T0_MAT0" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x074" size="4" name="ADCSTART1_IN" access="Read/Write" description="ADC start1 input   multiplexer (GIMA output 29)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INV" description="Invert input">
+        <Enum name="NOT_INVERTED" start="0" description="Not inverted." />
+        <Enum name="INPUT_INVERTED" start="1" description="Input inverted." />
+      </BitField>
+      <BitField start="1" size="1" name="EDGE" description="Enable rising edge detection">
+        <Enum name="NO_EDGE_DETECTION" start="0" description="No edge detection." />
+        <Enum name="RISING_EDGE_DETECTIO" start="1" description="Rising edge detection enabled." />
+      </BitField>
+      <BitField start="2" size="1" name="SYNCH" description="Enable   synchronization">
+        <Enum name="DISABLE__SYNCHRONIZ" start="0" description="Disable   synchronization." />
+        <Enum name="ENABLE__SYNCHRONIZA" start="1" description="Enable   synchronization." />
+      </BitField>
+      <BitField start="3" size="1" name="PULSE" description="Enable single pulse generation.">
+        <Enum name="DISABLE_SINGLE_PULSE" start="0" description="Disable single pulse generation." />
+        <Enum name="ENABLE_SINGLE_PULSE" start="1" description="Enable single pulse generation." />
+      </BitField>
+      <BitField start="4" size="4" name="SELECT" description="Select input. Values 0x2 to 0xF are reserved.">
+        <Enum name="CTOUT_8_OR_T2_MAT0" start="0x0" description="CTOUT_8 or T2_MAT0" />
+        <Enum name="T2_MAT0" start="0x1" description="T2_MAT0" />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DAC" start="0x400E1000" description="Digital-to-Analog Converter (DAC) ">
+    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="DAC register. Holds the conversion data." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="6" size="10" name="VALUE" description="After the selected settling time after this field is written with a new VALUE, the voltage on the DACOUT pin (with respect to VSSA) is VALUE/1024 X VDDA." />
+      <BitField start="16" size="1" name="BIAS" description="Settling time">
+        <Enum name="SHORT" start="0" description="The settling time of the DAC is 1 micros max, and the maximum current is 700 microA." />
+        <Enum name="LONG" start="1" description="The settling time of the DAC is 2.5 micros and the maximum current is 350 microA." />
+      </BitField>
+      <BitField start="17" size="15" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="CTRL" access="Read/Write" description="DAC control register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INT_DMA_REQ" description="DMA request">
+        <Enum name="CLR" start="0" description="This bit is cleared on any write to the DACR register." />
+        <Enum name="SET" start="1" description="This bit is set by hardware when the timer times out." />
+      </BitField>
+      <BitField start="1" size="1" name="DBLBUF_ENA" description="DMA double-buffering">
+        <Enum name="DISABLED" start="0" description="DACR double-buffering is disabled." />
+        <Enum name="ENABLED" start="1" description="When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter." />
+      </BitField>
+      <BitField start="2" size="1" name="CNT_ENA" description="DMA time-out">
+        <Enum name="DISABLED" start="0" description="Time-out counter operation is disabled." />
+        <Enum name="ENABLED" start="1" description="Time-out counter operation is enabled." />
+      </BitField>
+      <BitField start="3" size="1" name="DMA_ENA" description="DMA enable">
+        <Enum name="DISABLED" start="0" description="DMA access is disabled." />
+        <Enum name="ENABLED" start="1" description="DMA Burst Request Input 15 is enabled for the DAC (see Table 136)." />
+      </BitField>
+      <BitField start="4" size="28" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="CNTVAL" access="Read/Write" description="DAC counter value register." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="VALUE" description="16-bit reload value for the DAC interrupt/DMA timer." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="C_CAN0" start="0x400E2000" description="C_CAN ">
+    <Register start="+0x000" size="4" name="CNTL" access="Read/Write" description="CAN control" reset_value="0x0001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="INIT" description="Initialization">
+        <Enum name="INITIALIZATION_IS_ST" start="1" description="Initialization is started. On reset, software needs to initialize the CAN controller." />
+        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
+      </BitField>
+      <BitField start="1" size="1" name="IE" description="Module interrupt enable">
+        <Enum name="ENABLE_CAN_INTERRUPT" start="1" description="Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared." />
+        <Enum name="DISABLE_CAN_INTERRUP" start="0" description="Disable CAN interrupts. The interrupt line is always HIGH." />
+      </BitField>
+      <BitField start="2" size="1" name="SIE" description="Status change interrupt enable">
+        <Enum name="ENABLE_STATUS_CHANGE" start="1" description="Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected." />
+        <Enum name="DISABLE_STATUS_CHANG" start="0" description="Disable status change interrupts. No status change interrupt will be generated." />
+      </BitField>
+      <BitField start="3" size="1" name="EIE" description="Error interrupt enable">
+        <Enum name="ENABLE_ERROR_INTERRU" start="1" description="Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt." />
+        <Enum name="DISABLE_ERROR_INTERR" start="0" description="Disable error interrupt. No error status interrupt will be generated." />
+      </BitField>
+      <BitField start="4" size="1" name="RESERVED" description="reserved" />
+      <BitField start="5" size="1" name="DAR" description="Disable automatic retransmission">
+        <Enum name="DISABLED" start="1" description="Automatic retransmission disabled." />
+        <Enum name="ENABLED" start="0" description="Automatic retransmission of disturbed messages enabled." />
+      </BitField>
+      <BitField start="6" size="1" name="CCE" description="Configuration change enable">
+        <Enum name="THE_CPU_HAS_WRITE_AC" start="1" description="The CPU has write access to the CANBT register while the INIT bit is one." />
+        <Enum name="THE_CPU_HAS_NO_WRITE" start="0" description="The CPU has no write access to the bit timing register." />
+      </BitField>
+      <BitField start="7" size="1" name="TEST" description="Test mode enable">
+        <Enum name="TEST_MODE_" start="1" description="Test mode." />
+        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x004" size="4" name="STAT" access="Read/Write" description="Status register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="LEC" description="Last error code Type of the last error to occur on the CAN bus.The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error. The unused code 111 may be written by the CPU to check for updates.">
+        <Enum name="NO_ERROR_" start="0x0" description="No error." />
+        <Enum name="STUFF_ERROR_MORE_TH" start="0x1" description="Stuff error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed." />
+        <Enum name="FORM_ERROR_A_FIXED_" start="0x2" description="Form error: A fixed format part of a received frame has the wrong format." />
+        <Enum name="ACKERROR_THE_MESSAG" start="0x3" description="AckError: The message this CAN core transmitted was not acknowledged." />
+        <Enum name="BIT1ERROR_DURING_TH" start="0x4" description="Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a HIGH/recessive level (bit of logical value 1), but the monitored bus value was LOW/dominant." />
+        <Enum name="BIT0ERROR_DURING_TH" start="0x5" description="Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a LOW/dominant level (data or identifier bit logical value 0), but the monitored Bus value was HIGH/recessive. During busoff recovery this status is set each time a sequence of 11 HIGH/recessive bits has been monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at LOW/dominant or continuously disturbed)." />
+        <Enum name="CRCERROR_THE_CRC_CH" start="0x6" description="CRCError: The CRC checksum was incorrect in the message received." />
+        <Enum name="UNUSED_NO_CAN_BUS_E" start="0x7" description="Unused: No CAN bus event was detected (written by the CPU)." />
+      </BitField>
+      <BitField start="3" size="1" name="TXOK" description="Transmitted a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
+        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last reset by the CPU, a message has been successfully transmitted (error free and acknowledged by at least one other node)." />
+        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was reset by the CPU, no message has been successfully transmitted." />
+      </BitField>
+      <BitField start="4" size="1" name="RXOK" description="Received a message successfully This bit is reset by the CPU. It is never reset by the CAN controller.">
+        <Enum name="MSGTRANSFER" start="1" description="Since this bit was last set to zero by the CPU, a message has been successfully received independent of the result of acceptance filtering." />
+        <Enum name="NOMSGTRANSFER" start="0" description="Since this bit was last reset by the CPU, no message has been successfully transmitted." />
+      </BitField>
+      <BitField start="5" size="1" name="EPASS" description="Error passive">
+        <Enum name="PASSIVE" start="1" description="The CAN controller is in the error passive state as defined in the  CAN 2.0 specification." />
+        <Enum name="ACTIVE" start="0" description="The CAN controller is in the error active state." />
+      </BitField>
+      <BitField start="6" size="1" name="EWARN" description="Warning status">
+        <Enum name="AT_LEAST_ONE_OF_THE_" start="1" description="At least one of the error counters in the EML has reached the error warning limit of 96." />
+        <Enum name="BOTH_ERROR_COUNTERS_" start="0" description="Both error counters are below the error warning limit of 96." />
+      </BitField>
+      <BitField start="7" size="1" name="BOFF" description="Busoff status">
+        <Enum name="BUSOFF" start="1" description="The CAN controller is in busoff state." />
+        <Enum name="NOBUSOFF" start="0" description="The CAN module is not in busoff." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x008" size="4" name="EC" access="ReadOnly" description="Error counter" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="TEC_7_0" description="Transmit error counter Current value of the transmit error counter (maximum value 127)" />
+      <BitField start="8" size="7" name="REC_6_0" description="Receive error counter Current value of the receive error counter (maximum value 255)." />
+      <BitField start="15" size="1" name="RP" description="Receive error passive">
+        <Enum name="PASSIVE" start="1" description="The receive counter has reached the error passive level as defined in the  CAN2.0 specification." />
+        <Enum name="BELOWPASSIVE" start="0" description="The receive counter is below the error passive level." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x00C" size="4" name="BT" access="Read/Write" description="Bit timing register" reset_value="0x2301" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="BRP" description="Baud rate prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 63[1].  Valid programmed values are 0x01 - 0x3F[1]." />
+      <BitField start="6" size="2" name="SJW" description="(Re)synchronization jump width Valid programmed values are 0 to 3[1]." />
+      <BitField start="8" size="4" name="TSEG1" description="Time segment after the sample point Valid values are 0 to 7[1]." />
+      <BitField start="12" size="3" name="TSEG2" description="Time segment before the sample point Valid values are 1 to 15[1]." />
+      <BitField start="15" size="17" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x010" size="4" name="INT" access="ReadOnly" description="Interrupt register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="INTID15_0" description="0x0000= No interrupt is pending 0x0001 to 0x0020 = Number of message object which caused the interrupt. 0x0021 to 0x7FFF = Unused 0x8000 = Status interrupt 0x8001 to 0xFFFF = Unused" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x014" size="4" name="TEST" access="Read/Write" description="Test register" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="2" name="RESERVED" description="tbd." />
+      <BitField start="2" size="1" name="BASIC" description="Basic mode">
+        <Enum name="IF1_TX_if2_rx" start="1" description="IF1 registers used as TX buffer, IF2 registers used as RX buffer." />
+        <Enum name="BASIC_MODE_DISABLED_" start="0" description="Basic mode disabled." />
+      </BitField>
+      <BitField start="3" size="1" name="SILENT" description="Silent mode">
+        <Enum name="SILENT" start="1" description="The module is in silent mode." />
+        <Enum name="NORMAL_OPERATION_" start="0" description="Normal operation." />
+      </BitField>
+      <BitField start="4" size="1" name="LBACK" description="Loop back mode">
+        <Enum name="ENABLED" start="1" description="Loop back mode is enabled." />
+        <Enum name="DISABLED" start="0" description="Loop back mode is disabled." />
+      </BitField>
+      <BitField start="5" size="2" name="TX1_0" description="Control of TD pins">
+        <Enum name="LEVEL_AT_THE_TD_PIN_" start="0x0" description="Level at the TD pin is controlled by the CAN controller. This is the value at reset." />
+        <Enum name="THE_SAMPLE_POINT_CAN" start="0x1" description="The sample point can be monitored at the TD pin." />
+        <Enum name="TD_PIN_IS_DRIVEN_LOW" start="0x2" description="TD pin is driven LOW/dominant." />
+        <Enum name="TD_PIN_IS_DRIVEN_HIG" start="0x3" description="TD pin is driven HIGH/recessive." />
+      </BitField>
+      <BitField start="7" size="1" name="RX" description="Monitors the actual value of the RD Pin">
+        <Enum name="THE_CAN_BUS_IS_RECES" start="1" description="The CAN bus is recessive (RD = 1)." />
+        <Enum name="THE_CAN_BUS_IS_DOMIN" start="0" description="The CAN bus is dominant (RD = 0)." />
+      </BitField>
+      <BitField start="8" size="24" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x018" size="4" name="BRPE" access="Read/Write" description="Baud rate prescaler extension register" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="BRPE" description="Baud rate prescaler extension By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. Hardware interprets the value as the value of BRPE (MSBs) and BRP (LSBs) plus one. Allowed values are 0x00 to 0x0F" />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020+0" size="4" name="IF1_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
+      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
+      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x020+96" size="4" name="IF2_CMDREQ" access="Read/Write" description="Message interface  command request " reset_value="0x0001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="MESSNUM" description="Message number 0x01 to 0x20 = Valid message numbers The message object in the message RAM is selected for data transfer. 0x00 = Not a valid message number. This value is interpreted as 0x20.[1] 0x21 to 0x3F = Not a valid message number. This value is interpreted as 0x01 - 0x1F.[1]" />
+      <BitField start="6" size="9" name="RESERVED" description="Reserved" />
+      <BitField start="15" size="1" name="BUSY" description="BUSY flag. Set to one by hardware when writing to this Command request register. Set to zero by hardware when read/write action to this Command request register has finished." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
+        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
+      </BitField>
+      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
+        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
+      </BitField>
+      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
+        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
+        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
+      </BitField>
+      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
+      <BitField start="4" size="1" name="CTRL" description="Access control bits">
+        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
+        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
+      </BitField>
+      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
+        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
+        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
+      </BitField>
+      <BitField start="6" size="1" name="MASK" description="Access mask bits">
+        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
+        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
+      </BitField>
+      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_W" access="Read/Write" description="Message interface command mask (write direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to message object." />
+        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
+      </BitField>
+      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to message object." />
+        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
+      </BitField>
+      <BitField start="2" size="1" name="TXRQST" description="Access transmission request bit">
+        <Enum name="REQUEST_A_TRANSMISSI" start="1" description="Request a transmission. Set the TXRQST bit IF1/2_MCTRL." />
+        <Enum name="NO_TRANSMISSION_REQU" start="0" description="No transmission request. TXRQSRT bit unchanged in IF1/2_MCTRL. If a transmission is requested by programming this bit, the TXRQST bit in the CANIFn_MCTRL register is ignored." />
+      </BitField>
+      <BitField start="3" size="1" name="CLRINTPND" description="This bit is ignored in the write direction." />
+      <BitField start="4" size="1" name="CTRL" description="Access control bits">
+        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to message object" />
+        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
+      </BitField>
+      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
+        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to message object." />
+        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
+      </BitField>
+      <BitField start="6" size="1" name="MASK" description="Access mask bits">
+        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to message object." />
+        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
+      </BitField>
+      <BitField start="7" size="1" name="WR_RD" description="Write transfer Transfer data from the selected message buffer registers to the message object addressed by the command request register CANIFn_CMDREQ." />
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x024+0" size="4" name="IF1_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
+        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
+      </BitField>
+      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
+        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
+      </BitField>
+      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
+        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
+        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
+      </BitField>
+      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
+        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
+        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
+      </BitField>
+      <BitField start="4" size="1" name="CTRL" description="Access control bits">
+        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
+        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
+      </BitField>
+      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
+        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
+        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
+      </BitField>
+      <BitField start="6" size="1" name="MASK" description="Access mask bits">
+        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
+        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
+      </BitField>
+      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x024+96" size="4" name="IF2_CMDMSK_R" access="Read/Write" description="Message interface  command mask (read direction)" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DATA_B" description="Access data bytes 4-7">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 4-7 to IFx message buffer register." />
+        <Enum name="DATA_BYTES_4_7_UNCHA" start="0" description="data bytes 4-7 unchanged." />
+      </BitField>
+      <BitField start="1" size="1" name="DATA_A" description="Access data bytes 0-3">
+        <Enum name="TRANSFER_DATA_BYTES_" start="1" description="Transfer data bytes 0-3 to IFx message buffer." />
+        <Enum name="DATA_BYTES_0_3_UNCHA" start="0" description="data bytes 0-3 unchanged." />
+      </BitField>
+      <BitField start="2" size="1" name="NEWDAT" description="Access new data bit">
+        <Enum name="CLEAR_NEWDAT_BIT_IN_" start="1" description="Clear NEWDAT bit in the message object." />
+        <Enum name="NEWDAT_BIT_REMAINS_U" start="0" description="NEWDAT bit remains unchanged. A read access to a message object can be combined with the reset of the control bits INTPND and NEWDAT in IF1/2_MCTRL. The values of these bits transferred to the IFx Message Control Register always reflect the status before resetting these bits." />
+      </BitField>
+      <BitField start="3" size="1" name="CLRINTPND" description="Clear interrupt pending bit.">
+        <Enum name="CLEAR_INTPND_BIT_IN_" start="1" description="Clear INTPND bit in the message object." />
+        <Enum name="INTPND_BIT_REMAINS_U" start="0" description="INTPND bit remains unchanged." />
+      </BitField>
+      <BitField start="4" size="1" name="CTRL" description="Access control bits">
+        <Enum name="TRANSFER_CONTROL_BIT" start="1" description="Transfer control bits to IFx message buffer." />
+        <Enum name="CONTROL_BITS_UNCHANG" start="0" description="Control bits unchanged." />
+      </BitField>
+      <BitField start="5" size="1" name="ARB" description="Access arbitration bits">
+        <Enum name="TRANSFER_IDENTIFIER" start="1" description="Transfer Identifier, DIR, XTD, and MSGVAL bits to IFx message buffer register." />
+        <Enum name="ARBITRATION_BITS_UNC" start="0" description="Arbitration bits unchanged." />
+      </BitField>
+      <BitField start="6" size="1" name="MASK" description="Access mask bits">
+        <Enum name="TRANSFER_IDENTIFIER_" start="1" description="Transfer Identifier MASK + MDIR + MXTD to IFx message buffer register." />
+        <Enum name="MASK_BITS_UNCHANGED_" start="0" description="Mask bits unchanged." />
+      </BitField>
+      <BitField start="7" size="1" name="WR_RD" description="Read transfer Transfer data from the message object addressed by the command request register to the selected message buffer registers CANIFn_CMDREQ." />
+      <BitField start="8" size="24" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x028+0" size="4" name="IF1_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
+      <BitField start="16" size="16" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x028+96" size="4" name="IF2_MSK1" access="Read/Write" description="Message interface  mask 1" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MSK15_0" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
+      <BitField start="16" size="16" name="RESERVED" description="reserved" />
+    </Register>
+    <Register start="+0x02C+0" size="4" name="IF1_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
+        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
+        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
+      </BitField>
+      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
+        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
+        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x02C+96" size="4" name="IF2_MSK2" access="Read/Write" description="Message interface 1 mask 2" reset_value="0xFFFF" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="13" name="MSK28_16" description="Identifier mask 0 = The corresponding bit in the identifier of the message can not inhibit the match in the acceptance filtering. 1 = The corresponding identifier bit is used for acceptance filtering." />
+      <BitField start="13" size="1" name="RESERVED" description="Reserved" />
+      <BitField start="14" size="1" name="MDIR" description="Mask message direction">
+        <Enum name="THE_MESSAGE_DIRECTIO" start="1" description="The message direction bit (DIR) is used for acceptance filtering." />
+        <Enum name="THE_MESSAGE_DIRECTIO" start="0" description="The message direction bit (DIR) has no effect on acceptance filtering." />
+      </BitField>
+      <BitField start="15" size="1" name="MXTD" description="Mask extend identifier">
+        <Enum name="THE_EXTENDED_IDENTIF" start="1" description="The extended identifier bit (IDE) is used for acceptance filtering." />
+        <Enum name="THE_EXTENDED_IDENTIF" start="0" description="The extended identifier bit (IDE) has no effect on acceptance filtering." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x030+0" size="4" name="IF1_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x030+96" size="4" name="IF2_ARB1" access="Read/Write" description="Message interface 1 arbitration 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="ID15_0" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x034+0" size="4" name="IF1_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
+      <BitField start="13" size="1" name="DIR" description="Message direction">
+        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
+        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
+      </BitField>
+      <BitField start="14" size="1" name="XTD" description="Extend identifier">
+        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
+        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
+      </BitField>
+      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
+        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
+        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x034+96" size="4" name="IF2_ARB2" access="Read/Write" description="Message interface 1 arbitration 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="13" name="ID28_16" description="Message identifier  29-bit identifier (extended frame) 11-bit identifier (standard frame)" />
+      <BitField start="13" size="1" name="DIR" description="Message direction">
+        <Enum name="DIRECTION_EQ_TRANSMIT" start="1" description="Direction = transmit. On TXRQST, the respective Message Object is transmitted as a Data Frame. On reception of a Remote Frame with matching identifier, the TXRQST bit of this Message Object is set (if RMTEN = one)." />
+        <Enum name="DIRECTION_EQ_RECEIVE_" start="0" description="Direction = receive. On TXRQST, a Remote Frame with the identifier of this Message Object is transmitted. On reception of a Data Frame with matching identifier, that message is stored in this Message Object." />
+      </BitField>
+      <BitField start="14" size="1" name="XTD" description="Extend identifier">
+        <Enum name="THE_29_BIT_EXTENDED_" start="1" description="The 29-bit extended identifier will be used for this message object." />
+        <Enum name="THE_11_BIT_STANDARD_" start="0" description="The 11-bit standard identifier will be used for this message object." />
+      </BitField>
+      <BitField start="15" size="1" name="MSGVAL" description="Message valid The CPU must reset the MSGVAL bit of all unused Messages Objects during the initialization before it resets bit INIT in the CAN Control Register. This bit must also be reset before the identifier ID28:0, the control bits XTD, DIR, or the Data Length Code DLC3:0 are modified, or if the Messages Object is no longer required.">
+        <Enum name="THE_MESSAGE_OBJECT_I" start="1" description="The message object is configured and should be considered by the message handler." />
+        <Enum name="THE_MESSAGE_OBJECT_I" start="0" description="The message object is ignored by the message handler." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x038+0" size="4" name="IF1_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
+      <BitField start="4" size="3" name="RESERVED" description="reserved" />
+      <BitField start="7" size="1" name="EOB" description="End of buffer">
+        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
+        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
+      </BitField>
+      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
+        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
+        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
+      </BitField>
+      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
+        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
+        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
+      </BitField>
+      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
+        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
+        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
+      </BitField>
+      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
+        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
+        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
+      </BitField>
+      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
+        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
+        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
+      </BitField>
+      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
+        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
+        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
+      </BitField>
+      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
+        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
+        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
+      </BitField>
+      <BitField start="15" size="1" name="NEWDAT" description="New data">
+        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
+        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x038+96" size="4" name="IF2_MCTRL" access="Read/Write" description="Message interface 1 message control" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DLC3_0" description="Data length code The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 0000 to 1000 = Data frame has 0 - 8 data bytes. 1001 to 1111 = Data frame has 8 data bytes." />
+      <BitField start="4" size="3" name="RESERVED" description="reserved" />
+      <BitField start="7" size="1" name="EOB" description="End of buffer">
+        <Enum name="SINGLE_MESSAGE_OBJEC" start="1" description="Single message object or last message object of a FIFO buffer." />
+        <Enum name="MESSAGE_OBJECT_BELON" start="0" description="Message object belongs to a FIFO buffer and is not the last message object of that FIFO buffer." />
+      </BitField>
+      <BitField start="8" size="1" name="TXRQST" description="Transmit request">
+        <Enum name="REQUEST" start="1" description="The transmission of this message object is requested and is not yet done" />
+        <Enum name="WAIT" start="0" description="This message object is not waiting for transmission." />
+      </BitField>
+      <BitField start="9" size="1" name="RMTEN" description="Remote enable">
+        <Enum name="TXRQSTSET" start="1" description="At the reception of a remote frame, TXRQST is set." />
+        <Enum name="UNCHANGED" start="0" description="At the reception of a remote frame, TXRQST is left unchanged." />
+      </BitField>
+      <BitField start="10" size="1" name="RXIE" description="Receive interrupt enable">
+        <Enum name="INTPNDSET" start="1" description="INTPND will be set after successful reception of a frame." />
+        <Enum name="UNCHANGED" start="0" description="INTPND will be left unchanged after successful reception of a frame." />
+      </BitField>
+      <BitField start="11" size="1" name="TXIE" description="Transmit interrupt enable">
+        <Enum name="INTPNDSET" start="1" description="INTPND will be set after a successful reception of a frame." />
+        <Enum name="UNCHANGED" start="0" description="The INTPND bit will be left unchanged after a successful reception of a frame." />
+      </BitField>
+      <BitField start="12" size="1" name="UMASK" description="Use acceptance mask If UMASK is set to 1, the message object's mask bits have to be programmed during initialization of the message object before MAGVAL is set to 1.">
+        <Enum name="USE_MASK" start="1" description="Use mask (MSK[28:0], MXTD, and MDIR) for acceptance filtering." />
+        <Enum name="MASK_IGNORED_" start="0" description="Mask ignored." />
+      </BitField>
+      <BitField start="13" size="1" name="INTPND" description="Interrupt pending">
+        <Enum name="INTSOURCE" start="1" description="This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority." />
+        <Enum name="NOINTSOURCE" start="0" description="This message object is not the source of an interrupt." />
+      </BitField>
+      <BitField start="14" size="1" name="MSGLST" description="Message lost (only valid for message objects in the direction receive).">
+        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The Message Handler stored a new message into this object when NEWDAT was still set, the CPU has lost a message." />
+        <Enum name="NO_MESSAGE_LOST_SINC" start="0" description="No message lost since this bit was reset last by the CPU." />
+      </BitField>
+      <BitField start="15" size="1" name="NEWDAT" description="New data">
+        <Enum name="THE_MESSAGE_HANDLER_" start="1" description="The message handler or the CPU has written new data into the data portion of this message object." />
+        <Enum name="NO_NEW_DATA_HAS_BEEN" start="0" description="No new data has been written into the data portion of this message object by the message handler since this flag was cleared last by the CPU." />
+      </BitField>
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x03C+0" size="4" name="IF1_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
+      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x03C+96" size="4" name="IF2_DA1" access="Read/Write" description="Message interface  data A1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA0" description="Data byte 0" />
+      <BitField start="8" size="8" name="DATA1" description="Data byte 1" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x040+0" size="4" name="IF1_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
+      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x040+96" size="4" name="IF2_DA2" access="Read/Write" description="Message interface 1 data A2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA2" description="Data byte 2" />
+      <BitField start="8" size="8" name="DATA3" description="Data byte 3" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x044+0" size="4" name="IF1_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
+      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x044+96" size="4" name="IF2_DB1" access="Read/Write" description="Message interface 1 data B1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA4" description="Data byte 4" />
+      <BitField start="8" size="8" name="DATA5" description="Data byte 5" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x048+0" size="4" name="IF1_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
+      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x048+96" size="4" name="IF2_DB2" access="Read/Write" description="Message interface 1 data B2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATA6" description="Data byte 6" />
+      <BitField start="8" size="8" name="DATA7" description="Data byte 7" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x100" size="4" name="TXREQ1" access="ReadOnly" description="Transmission request 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TXRQST16_1" description="Transmission request bit of message objects 16 to 1. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x104" size="4" name="TXREQ2" access="ReadOnly" description="Transmission request 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="TXRQST32_17" description="Transmission request bit of message objects 32 to 17. 0 = This message object is not waiting for transmission. 1 = The transmission of this message object is requested and not yet done." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x120" size="4" name="ND1" access="ReadOnly" description="New data 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="NEWDAT16_1" description="New data bits of message objects 16 to 1. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x124" size="4" name="ND2" access="ReadOnly" description="New data 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="NEWDAT32_17" description="New data bits of message objects 32 to 17. 0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU. 1 = The Message Handler or the CPU has written new data into the data portion of this Message Object." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x140" size="4" name="IR1" access="ReadOnly" description="Interrupt pending 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="INTPND16_1" description="Interrupt pending bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x144" size="4" name="IR2" access="ReadOnly" description="Interrupt pending 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="INTPND32_17" description="Interrupt pending bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is the source of an interrupt." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x160" size="4" name="MSGV1" access="ReadOnly" description="Message valid 1" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MSGVAL16_1" description="Message valid bits of message objects 16 to 1. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x164" size="4" name="MSGV2" access="ReadOnly" description="Message valid 2" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="MSGVAL32_17" description="Message valid bits of message objects 32 to 17. 0 = This message object is ignored by the message handler. 1 = This message object is configured and should be considered by the message handler." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x180" size="4" name="CLKDIV" access="Read/Write" description="CAN clock divider register" reset_value="0x0001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="CLKDIVVAL" description="&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;Clock divider value &#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;CAN_CLK = PCLK/(CLKDIVVAL +1)&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0000: CAN_CLK = PCLK divided by 1.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0001: CAN_CLK = PCLK divided by 2.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0010: CAN_CLK = PCLK divided by 3.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0011: CAN_CLK = PCLK divided by 4.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;0100: CAN_CLK = PCLK divided by 5.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;...&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;1111: CAN_CLK = PCLK divided by 16.&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#xa;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;&#x9;" />
+      <BitField start="4" size="28" name="RESERVED" description="reserved" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADC0" start="0x400E3000" description="10-bit Analog-to-Digital Converter (ADC) ">
+    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="SEL" description="Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01." />
+      <BitField start="8" size="8" name="CLKDIV" description="The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
+      <BitField start="16" size="1" name="BURST" description="Burst mode">
+        <Enum name="SOFTWARE" start="0" description="Conversions are software controlled and require 11 clocks." />
+        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is  in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start." />
+      </BitField>
+      <BitField start="17" size="3" name="CLKS" description="This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).">
+        <Enum name="11_CLOCKS_10_BITS" start="0x0" description="11 clocks / 10 bits" />
+        <Enum name="10_CLOCKS_9_BITS" start="0x1" description="10 clocks / 9 bits" />
+        <Enum name="9_CLOCKS_8_BITS" start="0x2" description="9 clocks / 8 bits" />
+        <Enum name="8_CLOCKS_7_BITS" start="0x3" description="8 clocks / 7 bits" />
+        <Enum name="7_CLOCKS_6_BITS" start="0x4" description="7 clocks / 6 bits" />
+        <Enum name="6_CLOCKS_5_BITS" start="0x5" description="6 clocks / 5 bits" />
+        <Enum name="5_CLOCKS_4_BITS" start="0x6" description="5 clocks / 4 bits" />
+        <Enum name="4_CLOCKS_3_BITS" start="0x7" description="4 clocks / 3 bits" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="21" size="1" name="PDN" description="Power mode">
+        <Enum name="POWERDOWN" start="0" description="The A/D converter is in Power-down mode." />
+        <Enum name="RUNNING" start="1" description="The A/D converter is operational." />
+      </BitField>
+      <BitField start="22" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):">
+        <Enum name="NO_START" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
+        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
+        <Enum name="CTOUT_15" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)." />
+        <Enum name="CTOUT_8" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)." />
+        <Enum name="ADCTRIG0" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input." />
+        <Enum name="ADCTRIG1" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input." />
+        <Enum name="MCOA2" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2." />
+        <Enum name="RESERVED_" start="0x7" description="Reserved." />
+      </BitField>
+      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 0x2 -0x6. In these cases:">
+        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected signal." />
+        <Enum name="FALLING" start="1" description="Start conversion on a falling edge on the selected signal." />
+      </BitField>
+      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="GDR" access="ReadOnly" description="A/D Global Data Register. Contains the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. These bits always read as zeroes." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="8" name="RESERVED" description="Reserved. These bits always read as zeroes." />
+      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the LS bits were converted." />
+      <BitField start="27" size="3" name="RESERVED" description="Reserved. These bits always read as zeroes." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written. If the AD0/1CR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
+    </Register>
+    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x00000100" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADINTEN" description="These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." />
+      <BitField start="8" size="1" name="ADGINTEN" description="When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts." />
+      <BitField start="9" size="23" name="RESERVED" description="Reserved. Always 0." />
+    </Register>
+    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DONE" description="These bits mirror the DONE status flags that appear in the result register for each A/D channel." />
+      <BitField start="8" size="8" name="OVERUN" description="These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously." />
+      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved. Always 0." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADC1" start="0x400E4000" description="10-bit Analog-to-Digital Converter (ADC) ">
+    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="SEL" description="Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0 selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01." />
+      <BitField start="8" size="8" name="CLKDIV" description="The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable." />
+      <BitField start="16" size="1" name="BURST" description="Burst mode">
+        <Enum name="SOFTWARE" start="0" description="Conversions are software controlled and require 11 clocks." />
+        <Enum name="BURST" start="1" description="The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that is  in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start." />
+      </BitField>
+      <BitField start="17" size="3" name="CLKS" description="This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).">
+        <Enum name="11_CLOCKS_10_BITS" start="0x0" description="11 clocks / 10 bits" />
+        <Enum name="10_CLOCKS_9_BITS" start="0x1" description="10 clocks / 9 bits" />
+        <Enum name="9_CLOCKS_8_BITS" start="0x2" description="9 clocks / 8 bits" />
+        <Enum name="8_CLOCKS_7_BITS" start="0x3" description="8 clocks / 7 bits" />
+        <Enum name="7_CLOCKS_6_BITS" start="0x4" description="7 clocks / 6 bits" />
+        <Enum name="6_CLOCKS_5_BITS" start="0x5" description="6 clocks / 5 bits" />
+        <Enum name="5_CLOCKS_4_BITS" start="0x6" description="5 clocks / 4 bits" />
+        <Enum name="4_CLOCKS_3_BITS" start="0x7" description="4 clocks / 3 bits" />
+      </BitField>
+      <BitField start="20" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="21" size="1" name="PDN" description="Power mode">
+        <Enum name="POWERDOWN" start="0" description="The A/D converter is in Power-down mode." />
+        <Enum name="RUNNING" start="1" description="The A/D converter is operational." />
+      </BitField>
+      <BitField start="22" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="24" size="3" name="START" description="When the BURST bit is 0, these bits control whether and when an A/D conversion is started (also see Figure 56):">
+        <Enum name="NO_START" start="0x0" description="No start (this value should be used when clearing PDN to 0)." />
+        <Enum name="START_CONVERSION_NOW" start="0x1" description="Start conversion now." />
+        <Enum name="CTOUT_15" start="0x2" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_15 (combined timer output 15)." />
+        <Enum name="CTOUT_8" start="0x3" description="Start conversion when the edge selected by bit 27 occurs on CTOUT_8 (combined timer output 8)." />
+        <Enum name="ADCTRIG0" start="0x4" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 input." />
+        <Enum name="ADCTRIG1" start="0x5" description="Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 input." />
+        <Enum name="MCOA2" start="0x6" description="Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2." />
+        <Enum name="RESERVED_" start="0x7" description="Reserved." />
+      </BitField>
+      <BitField start="27" size="1" name="EDGE" description="This bit is significant only when the START field contains 0x2 -0x6. In these cases:">
+        <Enum name="RISING" start="0" description="Start conversion on a rising edge on the selected signal." />
+        <Enum name="FALLING" start="1" description="Start conversion on a falling edge on the selected signal." />
+      </BitField>
+      <BitField start="28" size="4" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="GDR" access="ReadOnly" description="A/D Global Data Register. Contains the result of the most recent A/D conversion." reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. These bits always read as zeroes." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VSSA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="8" name="RESERVED" description="Reserved. These bits always read as zeroes." />
+      <BitField start="24" size="3" name="CHN" description="These bits contain the channel from which the LS bits were converted." />
+      <BitField start="27" size="3" name="RESERVED" description="Reserved. These bits always read as zeroes." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written. If the AD0/1CR is written while a conversion is still in progress, this bit is set and a new conversion is started." />
+    </Register>
+    <Register start="+0x00C" size="4" name="INTEN" access="Read/Write" description="A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt." reset_value="0x00000100" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="ADINTEN" description="These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc." />
+      <BitField start="8" size="1" name="ADGINTEN" description="When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts." />
+      <BitField start="9" size="23" name="RESERVED" description="Reserved. Always 0." />
+    </Register>
+    <Register start="+0x010+0" size="4" name="DR[0]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+4" size="4" name="DR[1]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+8" size="4" name="DR[2]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+12" size="4" name="DR[3]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+16" size="4" name="DR[4]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+20" size="4" name="DR[5]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+24" size="4" name="DR[6]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x010+28" size="4" name="DR[7]" access="ReadOnly" description="A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="6" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="6" size="10" name="V_VREF" description="When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA." />
+      <BitField start="16" size="14" name="RESERVED" description="Reserved. Always 0." />
+      <BitField start="30" size="1" name="OVERRUN" description="This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register." />
+      <BitField start="31" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read." />
+    </Register>
+    <Register start="+0x030" size="4" name="STAT" access="ReadOnly" description="A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DONE" description="These bits mirror the DONE status flags that appear in the result register for each A/D channel." />
+      <BitField start="8" size="8" name="OVERUN" description="These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously." />
+      <BitField start="16" size="1" name="ADINT" description="This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register." />
+      <BitField start="17" size="15" name="RESERVED" description="Reserved. Always 0." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADCHS" start="0x400F0000" description="12-bit Analog-to-Digital Converter  High-Speed (ADCHS)">
+    <Register start="+0x0000" size="4" name="FLUSH" access="WriteOnly" description="Flushes FIFO" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FIFO_FLUSH" description="1= fifo is cleared" />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0004" size="4" name="DMA_REQ" access="Read/Write" description="Set or clear DMA write request" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DMA_REQ_WR" description="1 = Dma_req_wr is set (initially used to fill second table),  0 = Dma_req_wr is cleared" />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0008" size="4" name="FIFO_STS" access="ReadOnly" description="Indicates FIFO fill level status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="5" name="LEVEL" description="0 = FIFO is empty  1...15 = FIFO is partially full  16 = FIFO is full" />
+      <BitField start="5" size="27" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x000C" size="4" name="FIFO_CFG" access="Read/Write" description="Configures FIFO fill level that triggers interrupt and packing 1 or 2 samples per word." reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PACKED_READ" description="0 = one sample is packed in one 32-bit read cycle  1 = two samples are packed in one 32-bit read cycle" />
+      <BitField start="1" size="5" name="LEVEL" description="When the FIFO contains more or equal than FIFO_LEVEL samples interrupt flag FIFO_FULL interrupt will be set and DMA_Read_Req will be raised." />
+      <BitField start="6" size="26" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0010" size="4" name="TRIGGER" access="WriteOnly" description="Enable software trigger to start descriptor processing" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SW_TRIGGER" description="Auto cleared" />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0014" size="4" name="DSCR_STS" access="Read/Write" description="Indicates active descriptor table and descriptor entry" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="ACT_TABLE" description="0 = table 0 is active  1 = table 1 is active." />
+      <BitField start="1" size="3" name="ACT_DESCRIPTOR" description="ID of the descriptor that is active." />
+      <BitField start="4" size="28" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0018" size="4" name="POWER_DOWN" access="Read/Write" description="Set or clear power down mode" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PD_CTRL" description="0 = disable power down mode. Register holds value until set by writing 1 to this bit or by descriptor processor when descriptor field POWER_DOWN is set.   1 = enable power down mode. Register holds value until cleared by writing 0 to this bit or by descriptor processor when waking up RECOVERY_TIME before a conversion." />
+      <BitField start="1" size="31" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x001C" size="4" name="CONFIG" access="Read/Write" description="Configures external trigger mode, store channel ID in FIFO and walk-up recovery time from power down." reset_value="0x00002400" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="TRIGGER__MASK" description="00 = triggers off  01 = software trigger only  10 = external trigger only  11 = both triggers allowed" />
+      <BitField start="2" size="2" name="TRIGGER_MODE" description="00 = rising external trigger  01 = falling external trigger  10 = low external trigger  11 = high external trigger" />
+      <BitField start="4" size="1" name="TRIGGER_SYNC" description="0  = do not synchronize external  trigger input  1 = synchronize external  trigger input" />
+      <BitField start="5" size="1" name="CHANNEL_ID_EN" description="0 = do not add channel ID to FIFO output data  1 = add channel ID to FIFO output data" />
+      <BitField start="6" size="8" name="RECOVERY_TIME" description="ADC recovery time from power down" />
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0020" size="4" name="THR_A" access="Read/Write" description="Configures window comparator A levels." reset_value="0x0FFF0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="THR_LOW_A" description="Low Compare Threshold Register A:   Contains the lower  threshold  level for automatic threshold comparison for any channels linked to threshold pair A." />
+      <BitField start="16" size="12" name="THR_HIGH_A" description="High Compare Threshold Register A:   Contains the upper threshold  level for automatic threshold comparison for any channels linked to threshold pair A." />
+      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0024" size="4" name="THR_B" access="Read/Write" description="Configures window comparator B levels." reset_value="0x0FFF0000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="THR_LOW_B" description="Low Compare Threshold Register B:   Contains the lower  threshold  level for automatic threshold comparison for any channels linked to threshold pair A." />
+      <BitField start="16" size="12" name="THR_HIGH_B" description="High Compare Threshold Register B:   Contains the upper threshold  level for automatic threshold comparison for any channels linked to threshold pair A." />
+      <BitField start="28" size="4" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0028+0" size="4" name="LAST_SAMPLE[0]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
+      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
+      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
+      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
+      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
+      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
+      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0028+4" size="4" name="LAST_SAMPLE[1]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
+      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
+      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
+      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
+      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
+      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
+      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0028+8" size="4" name="LAST_SAMPLE[2]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
+      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
+      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
+      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
+      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
+      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
+      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0028+12" size="4" name="LAST_SAMPLE[3]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
+      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
+      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
+      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
+      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
+      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
+      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0028+16" size="4" name="LAST_SAMPLE[4]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
+      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
+      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
+      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
+      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
+      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
+      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0028+20" size="4" name="LAST_SAMPLE[5]" access="ReadOnly" description="Contains last converted sample of input M [M=0..5) and result of window comparator." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DONE" description="This bit is set to 1 when an A/D conversion on this channel completes.  This bit is cleared whenever this register is read." />
+      <BitField start="1" size="1" name="OVERRUN" description="This bit will be set to a 1 if a new conversion on this channel completes and overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit is set.  This bit is cleared, along with the DONE bit, whenever this register is read.  This bit (in any of the registers) will cause an overrun interrupt request to be asserted if the overrun interrupt is enabled." />
+      <BitField start="2" size="2" name="THCMP_RANGE" description="Threshold Range Comparison result  00: In Range  01: Below Range  10: Above Range  11: Reserved" />
+      <BitField start="4" size="2" name="THCMP_CROSS" description="Threshold Crossing Comparison result  00: No Threshold Crossing detected  01: Downward Threshold Crossing detected  10: Upward Threshold Crossing detected  11: Reserved" />
+      <BitField start="6" size="12" name="SAMPLE" description="12-Bit value of last converted sample for this channel" />
+      <BitField start="17" size="4" name="RESERVED" description="Reserved" />
+      <BitField start="21" size="11" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0104" size="4" name="ADC_SPEED" access="Read/Write" description="ADC speed control" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="DGEC0" description="Speed0" />
+      <BitField start="4" size="4" name="DGEC1" description="Speed1" />
+      <BitField start="8" size="4" name="DGEC2" description="Speed2" />
+      <BitField start="12" size="4" name="DGEC3" description="Speed3" />
+      <BitField start="16" size="4" name="DGEC4" description="Speed4" />
+      <BitField start="20" size="4" name="DGEC5" description="Speed5" />
+      <BitField start="24" size="8" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0108" size="4" name="POWER_CONTROL" access="Read/Write" description="Configures ADC power vs. speed, DC-in biasing, output format and power gating." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="CRS" description="current setting for power versus speed programming" />
+      <BitField start="4" size="6" name="DCINNEG" description="AC-DC coupling selection  0 = No dc bias  1 = DC bias on vin_neg side" />
+      <BitField start="10" size="6" name="DCINPOS" description="AC-DC coupling selection  0 = No dc bias  1 = DC bias on vin_pos side" />
+      <BitField start="16" size="1" name="TWOS" description="Output data format selection  0 = offset binary  1 = two's complement" />
+      <BitField start="17" size="1" name="POWER_SWITCH" description="0 = ADC is powered down 1 = ADC is active" />
+      <BitField start="18" size="1" name="BGAP_SWITCH" description="0 = ADC band gap reference is powered down  1 = ADC band gap reference is active" />
+      <BitField start="19" size="13" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0200+0" size="4" name="FIFO_OUTPUT[0]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
+      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
+      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
+      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
+      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
+      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
+    </Register>
+    <Register start="+0x0200+4" size="4" name="FIFO_OUTPUT[1]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
+      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
+      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
+      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
+      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
+      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
+    </Register>
+    <Register start="+0x0200+8" size="4" name="FIFO_OUTPUT[2]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
+      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
+      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
+      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
+      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
+      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
+    </Register>
+    <Register start="+0x0200+12" size="4" name="FIFO_OUTPUT[3]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
+      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
+      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
+      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
+      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
+      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
+    </Register>
+    <Register start="+0x0200+16" size="4" name="FIFO_OUTPUT[4]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
+      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
+      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
+      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
+      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
+      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
+    </Register>
+    <Register start="+0x0200+20" size="4" name="FIFO_OUTPUT[5]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
+      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
+      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
+      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
+      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
+      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
+    </Register>
+    <Register start="+0x0200+24" size="4" name="FIFO_OUTPUT[6]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
+      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
+      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
+      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
+      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
+      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
+    </Register>
+    <Register start="+0x0200+28" size="4" name="FIFO_OUTPUT[7]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
+      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
+      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
+      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
+      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
+      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
+    </Register>
+    <Register start="+0x0200+32" size="4" name="FIFO_OUTPUT[8]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
+      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
+      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
+      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
+      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
+      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
+    </Register>
+    <Register start="+0x0200+36" size="4" name="FIFO_OUTPUT[9]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
+      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
+      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
+      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
+      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
+      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
+    </Register>
+    <Register start="+0x0200+40" size="4" name="FIFO_OUTPUT[10]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
+      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
+      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
+      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
+      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
+      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
+    </Register>
+    <Register start="+0x0200+44" size="4" name="FIFO_OUTPUT[11]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
+      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
+      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
+      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
+      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
+      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
+    </Register>
+    <Register start="+0x0200+48" size="4" name="FIFO_OUTPUT[12]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
+      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
+      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
+      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
+      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
+      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
+    </Register>
+    <Register start="+0x0200+52" size="4" name="FIFO_OUTPUT[13]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
+      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
+      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
+      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
+      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
+      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
+    </Register>
+    <Register start="+0x0200+56" size="4" name="FIFO_OUTPUT[14]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
+      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
+      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
+      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
+      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
+      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
+    </Register>
+    <Register start="+0x0200+60" size="4" name="FIFO_OUTPUT[15]" access="ReadOnly" description="FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="SAMPLE" description="Value of first converted sample" />
+      <BitField start="12" size="3" name="CHAN_ID" description="Channel number of first converted sample:  000: channel _0 or CHANNEL_ID_EN =0  001: channel _1  010: channel _2  011: channel _3  100: channel _4  101: channel _5  110: reserved  111: recovery_ error" />
+      <BitField start="15" size="1" name="EMPTY" description="0: FIFO not empty  1: FIFO empty" />
+      <BitField start="16" size="12" name="SAMPLE2" description="Value of second converted sample.  This field is only valid if PACKED_READ is set else it is 0x0" />
+      <BitField start="28" size="3" name="CHAN_ID2" description="Channel number of second converted sample   This field is only valid if CHANNEL_ID_EN and PACKED_READ are set else it is 0x0" />
+      <BitField start="31" size="1" name="EMPTY2" description="0: FIFO not empty  1: FIFO empty and PACKED_READ is set" />
+    </Register>
+    <Register start="+0x0300+0" size="4" name="DESCRIPTOR0_[0]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
+      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
+      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
+      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
+      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
+      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
+      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
+      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
+      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
+    </Register>
+    <Register start="+0x0300+4" size="4" name="DESCRIPTOR0_[1]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
+      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
+      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
+      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
+      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
+      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
+      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
+      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
+      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
+    </Register>
+    <Register start="+0x0300+8" size="4" name="DESCRIPTOR0_[2]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
+      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
+      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
+      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
+      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
+      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
+      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
+      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
+      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
+    </Register>
+    <Register start="+0x0300+12" size="4" name="DESCRIPTOR0_[3]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
+      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
+      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
+      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
+      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
+      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
+      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
+      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
+      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
+    </Register>
+    <Register start="+0x0300+16" size="4" name="DESCRIPTOR0_[4]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
+      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
+      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
+      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
+      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
+      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
+      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
+      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
+      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
+    </Register>
+    <Register start="+0x0300+20" size="4" name="DESCRIPTOR0_[5]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
+      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
+      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
+      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
+      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
+      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
+      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
+      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
+      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
+    </Register>
+    <Register start="+0x0300+24" size="4" name="DESCRIPTOR0_[6]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
+      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
+      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
+      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
+      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
+      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
+      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
+      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
+      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
+    </Register>
+    <Register start="+0x0300+28" size="4" name="DESCRIPTOR0_[7]" access="Read/Write" description="Table 0 descriptor n, n= 0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input  0  1: convert input  1  2: convert input  2  3: convert input  3  4: convert input  4  5: convert input  5  6,7: reserved" />
+      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
+      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
+      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
+      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample). Continue with next descriptor (wraps around after top)." />
+      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
+      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
+      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
+      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
+    </Register>
+    <Register start="+0x0320+0" size="4" name="DESCRIPTOR1_[0]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
+      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
+      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
+      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
+      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
+      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
+      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
+      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
+      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
+    </Register>
+    <Register start="+0x0320+4" size="4" name="DESCRIPTOR1_[1]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
+      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
+      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
+      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
+      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
+      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
+      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
+      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
+      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
+    </Register>
+    <Register start="+0x0320+8" size="4" name="DESCRIPTOR1_[2]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
+      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
+      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
+      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
+      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
+      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
+      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
+      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
+      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
+    </Register>
+    <Register start="+0x0320+12" size="4" name="DESCRIPTOR1_[3]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
+      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
+      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
+      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
+      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
+      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
+      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
+      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
+      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
+    </Register>
+    <Register start="+0x0320+16" size="4" name="DESCRIPTOR1_[4]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
+      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
+      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
+      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
+      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
+      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
+      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
+      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
+      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
+    </Register>
+    <Register start="+0x0320+20" size="4" name="DESCRIPTOR1_[5]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
+      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
+      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
+      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
+      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
+      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
+      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
+      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
+      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
+    </Register>
+    <Register start="+0x0320+24" size="4" name="DESCRIPTOR1_[6]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
+      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
+      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
+      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
+      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
+      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
+      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
+      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
+      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
+    </Register>
+    <Register start="+0x0320+28" size="4" name="DESCRIPTOR1_[7]" access="Read/Write" description="Table 1 descriptors n, n=0 to 7" reset_value="0x000090E0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="CHANNEL_NR" description="0: convert input 0  1: convert input 1  2: convert input 2  3: convert input 3  4: convert input 4  5: convert input 5  6,7: reserved" />
+      <BitField start="3" size="1" name="HALT" description="0: After this descriptor continue with the next descriptor.  1: halt after this descriptor is processed. Restart at a new trigger." />
+      <BitField start="4" size="1" name="INTERRUPT" description="1: Raise interrupt when ADC result is available" />
+      <BitField start="5" size="1" name="POWER_DOWN" description="1: Power down after this conversion." />
+      <BitField start="6" size="2" name="BRANCH" description="00: Continue with next descriptor (wraps around after top).  01: Branch to the first descriptor in this table.  10: Swap tables and branch to the first descriptor of the new table.  11: reserved (do not store sample).  Continue with next descriptor (wraps around after top)." />
+      <BitField start="8" size="14" name="MATCH_VALUE" description="Evaluate this descriptor when descriptor timer value is equal to match value." />
+      <BitField start="22" size="2" name="THRESHOLD_SEL" description="Indicates which threshold comparison level register set is to be used:  00: no comparison,  01: THR_A.   10: THR_B.  11: Reserved" />
+      <BitField start="24" size="1" name="RESET_TIMER" description="1: reset descriptor timer." />
+      <BitField start="25" size="6" name="RESERVED" description="Reserved" />
+      <BitField start="31" size="1" name="UPDATE_TABLE" description="1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set.  This field is write only. A read returns 0x0." />
+    </Register>
+    <Register start="+0x0F00" size="4" name="CLR_EN0" access="WriteOnly" description="Interrupt 0 clear mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="CEN0" description="Interrupt clear enable" />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0F04" size="4" name="SET_EN0" access="WriteOnly" description="Interrupt 0 set mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="SEN0" description="Interrupt set enable" />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0F08" size="4" name="MASK0" access="ReadOnly" description="Interrupt 0 mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="M0" description="Interrupt enable" />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0F0C" size="4" name="STATUS0" access="ReadOnly" description="Interrupt 0 status. Interrupt 0 contains FIFO fill level, descriptor status and ADC range under/overflow" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="FIFO_FULL" description="0: number of samples in FIFO less than or equal to FIFO_LEVEL  1: number of samples in FIFO is more than FIFO_LEVEL" />
+      <BitField start="1" size="1" name="FIFO_EMPTY" description="0: FIFO is not empty   1: FIFO is empty" />
+      <BitField start="2" size="1" name="FIFO_OVERFLOW" description="FIFO was full; conversion sample is not stored  and lost" />
+      <BitField start="3" size="1" name="DSCR_DONE" description="The descriptor INTERRUPT field was enabled and its sample is converted." />
+      <BitField start="4" size="1" name="DSCR_ERROR" description="The ADC was not fully woken up when a sample was converted and the conversion results is unreliable" />
+      <BitField start="5" size="1" name="ADC_OVF" description="Converted sample value was over range of the 12 bit output code." />
+      <BitField start="6" size="1" name="ADC_UNF" description="Converted sample value was under range of the 12 bit output code." />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0F10" size="4" name="CLR_STAT0" access="WriteOnly" description="Interrupt 0 clear status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="CSTAT0" description="Interrupt clear status" />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0F14" size="4" name="SET_STAT0" access="WriteOnly" description="Interrupt 0 set status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="7" name="SSTAT0" description="Interrupt set status" />
+      <BitField start="7" size="25" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0F20" size="4" name="CLR_EN1" access="WriteOnly" description="Interrupt 1 mask clear enable." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="30" name="CEN1" description="Interrupt clear enable" />
+      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0F24" size="4" name="SET_EN1" access="WriteOnly" description="Interrupt 1 mask set enable" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="30" name="SEN1" description="Interrupt set enable" />
+      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0F28" size="4" name="MASK1" access="ReadOnly" description="Interrupt 1 mask" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="30" name="M1" description="Interrupt enable" />
+      <BitField start="30" size="2" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0F2C" size="4" name="STATUS1" access="ReadOnly" description="Interrupt 1 status. Interrupt 1 contains window comparator results and register last LAST_SAMPLE[M] overrun." reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="THCMP_BRANGE0" description="Input channel 0 result below  range" />
+      <BitField start="1" size="1" name="THCMP_ARANGE0" description="Input channel 0 result above range" />
+      <BitField start="2" size="1" name="THCMP_DCROSS0" description="Input channel 0 result  downward threshold crossing detected" />
+      <BitField start="3" size="1" name="THCMP_UCROSS0" description="Input channel 0 result upward threshold crossing detected" />
+      <BitField start="4" size="1" name="OVERRUN_0" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [0]  before it has been read" />
+      <BitField start="5" size="1" name="THCMP_BRANGE1" description="Input channel 1 result below  range" />
+      <BitField start="6" size="1" name="THCMP_ARANGE1" description="Input channel 1 result above range" />
+      <BitField start="7" size="1" name="THCMP_DCROSS1" description="Input channel 1 result  downward threshold crossing detected" />
+      <BitField start="8" size="1" name="THCMP_UCROSS1" description="Input channel 1 result upward threshold crossing detected" />
+      <BitField start="9" size="1" name="OVERRUN_1" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [1]  before it has been read" />
+      <BitField start="10" size="1" name="THCMP_BRANGE2" description="Input channel 2 result below  range" />
+      <BitField start="11" size="1" name="THCMP_ARANGE2" description="Input channel 2 result above range" />
+      <BitField start="12" size="1" name="THCMP_DCROSS2" description="Input channel 2 result  downward threshold crossing detected" />
+      <BitField start="13" size="1" name="THCMP_UCROSS2" description="Input channel 2 result upward threshold crossing detected" />
+      <BitField start="14" size="1" name="OVERRUN_2" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [2]  before it has been read" />
+      <BitField start="15" size="1" name="THCMP_BRANGE3" description="Input channel 3 result below  range" />
+      <BitField start="16" size="1" name="THCMP_ARANGE3" description="Input channel 3 result above range" />
+      <BitField start="17" size="1" name="THCMP_DCROSS3" description="Input channel 3 result  downward threshold crossing detected" />
+      <BitField start="18" size="1" name="THCMP_UCROSS3" description="Input channel 3 result upward threshold crossing detected" />
+      <BitField start="19" size="1" name="OVERRUN_3" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [3]  before it has been read" />
+      <BitField start="20" size="1" name="THCMP_BRANGE4" description="Input channel 4 result below  range" />
+      <BitField start="21" size="1" name="THCMP_ARANGE4" description="Input channel 4 result above range" />
+      <BitField start="22" size="1" name="THCMP_DCROSS4" description="Input channel 4 result  downward threshold crossing detected" />
+      <BitField start="23" size="1" name="THCMP_UCROSS4" description="Input channel 4 result upward threshold crossing detected" />
+      <BitField start="24" size="1" name="OVERRUN_4" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [4]  before it has been read" />
+      <BitField start="25" size="1" name="THCMP_BRANGE5" description="Input channel 5 result below  range" />
+      <BitField start="26" size="1" name="THCMP_ARANGE5" description="Input channel 5 result above range" />
+      <BitField start="27" size="1" name="THCMP_DCROSS5" description="Input channel 5 result  downward threshold crossing detected" />
+      <BitField start="28" size="1" name="THCMP_UCROSS5" description="Input channel 5 result upward threshold crossing detected" />
+      <BitField start="29" size="1" name="OVERRUN_5" description="A new conversion on channel m completed and has overwritten the previous contents of  register  LAST_SAMPLE [5]  before it has been read" />
+      <BitField start="30" size="2" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F30" size="4" name="CLR_STAT1" access="WriteOnly" description="Interrupt 1 clear status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="30" name="CSTAT1" description="Interrupt clear status" />
+      <BitField start="30" size="2" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F34" size="4" name="SET_STAT1" access="WriteOnly" description="Interrupt 1 set status" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="30" name="SSTAT1" description="Interrupt set status" />
+      <BitField start="30" size="2" name="RESERVED" description="Reserved." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIO_PORT" start="0x400F4000" description="GPIO port ">
+    <Register start="+0x0000+0" size="1" name="B[0]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+1" size="1" name="B[1]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+2" size="1" name="B[2]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+3" size="1" name="B[3]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+4" size="1" name="B[4]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+5" size="1" name="B[5]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+6" size="1" name="B[6]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+7" size="1" name="B[7]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+8" size="1" name="B[8]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+9" size="1" name="B[9]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+10" size="1" name="B[10]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+11" size="1" name="B[11]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+12" size="1" name="B[12]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+13" size="1" name="B[13]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+14" size="1" name="B[14]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+15" size="1" name="B[15]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+16" size="1" name="B[16]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+17" size="1" name="B[17]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+18" size="1" name="B[18]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+19" size="1" name="B[19]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+20" size="1" name="B[20]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+21" size="1" name="B[21]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+22" size="1" name="B[22]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+23" size="1" name="B[23]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+24" size="1" name="B[24]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+25" size="1" name="B[25]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+26" size="1" name="B[26]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+27" size="1" name="B[27]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+28" size="1" name="B[28]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+29" size="1" name="B[29]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+30" size="1" name="B[30]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+31" size="1" name="B[31]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+32" size="1" name="B[32]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+33" size="1" name="B[33]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+34" size="1" name="B[34]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+35" size="1" name="B[35]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+36" size="1" name="B[36]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+37" size="1" name="B[37]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+38" size="1" name="B[38]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+39" size="1" name="B[39]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+40" size="1" name="B[40]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+41" size="1" name="B[41]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+42" size="1" name="B[42]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+43" size="1" name="B[43]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+44" size="1" name="B[44]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+45" size="1" name="B[45]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+46" size="1" name="B[46]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+47" size="1" name="B[47]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+48" size="1" name="B[48]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+49" size="1" name="B[49]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+50" size="1" name="B[50]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+51" size="1" name="B[51]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+52" size="1" name="B[52]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+53" size="1" name="B[53]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+54" size="1" name="B[54]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+55" size="1" name="B[55]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+56" size="1" name="B[56]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+57" size="1" name="B[57]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+58" size="1" name="B[58]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+59" size="1" name="B[59]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+60" size="1" name="B[60]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+61" size="1" name="B[61]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+62" size="1" name="B[62]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+63" size="1" name="B[63]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+64" size="1" name="B[64]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+65" size="1" name="B[65]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+66" size="1" name="B[66]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+67" size="1" name="B[67]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+68" size="1" name="B[68]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+69" size="1" name="B[69]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+70" size="1" name="B[70]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+71" size="1" name="B[71]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+72" size="1" name="B[72]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+73" size="1" name="B[73]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+74" size="1" name="B[74]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+75" size="1" name="B[75]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+76" size="1" name="B[76]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+77" size="1" name="B[77]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+78" size="1" name="B[78]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+79" size="1" name="B[79]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+80" size="1" name="B[80]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+81" size="1" name="B[81]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+82" size="1" name="B[82]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+83" size="1" name="B[83]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+84" size="1" name="B[84]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+85" size="1" name="B[85]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+86" size="1" name="B[86]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+87" size="1" name="B[87]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+88" size="1" name="B[88]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+89" size="1" name="B[89]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+90" size="1" name="B[90]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+91" size="1" name="B[91]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+92" size="1" name="B[92]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+93" size="1" name="B[93]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+94" size="1" name="B[94]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+95" size="1" name="B[95]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+96" size="1" name="B[96]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+97" size="1" name="B[97]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+98" size="1" name="B[98]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+99" size="1" name="B[99]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+100" size="1" name="B[100]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+101" size="1" name="B[101]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+102" size="1" name="B[102]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+103" size="1" name="B[103]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+104" size="1" name="B[104]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+105" size="1" name="B[105]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+106" size="1" name="B[106]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+107" size="1" name="B[107]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+108" size="1" name="B[108]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+109" size="1" name="B[109]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+110" size="1" name="B[110]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+111" size="1" name="B[111]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+112" size="1" name="B[112]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+113" size="1" name="B[113]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+114" size="1" name="B[114]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+115" size="1" name="B[115]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+116" size="1" name="B[116]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+117" size="1" name="B[117]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+118" size="1" name="B[118]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+119" size="1" name="B[119]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+120" size="1" name="B[120]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+121" size="1" name="B[121]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+122" size="1" name="B[122]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+123" size="1" name="B[123]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+124" size="1" name="B[124]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+125" size="1" name="B[125]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+126" size="1" name="B[126]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+127" size="1" name="B[127]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+128" size="1" name="B[128]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+129" size="1" name="B[129]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+130" size="1" name="B[130]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+131" size="1" name="B[131]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+132" size="1" name="B[132]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+133" size="1" name="B[133]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+134" size="1" name="B[134]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+135" size="1" name="B[135]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+136" size="1" name="B[136]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+137" size="1" name="B[137]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+138" size="1" name="B[138]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+139" size="1" name="B[139]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+140" size="1" name="B[140]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+141" size="1" name="B[141]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+142" size="1" name="B[142]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+143" size="1" name="B[143]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+144" size="1" name="B[144]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+145" size="1" name="B[145]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+146" size="1" name="B[146]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+147" size="1" name="B[147]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+148" size="1" name="B[148]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+149" size="1" name="B[149]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+150" size="1" name="B[150]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+151" size="1" name="B[151]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+152" size="1" name="B[152]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+153" size="1" name="B[153]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+154" size="1" name="B[154]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+155" size="1" name="B[155]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+156" size="1" name="B[156]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+157" size="1" name="B[157]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+158" size="1" name="B[158]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+159" size="1" name="B[159]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+160" size="1" name="B[160]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+161" size="1" name="B[161]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+162" size="1" name="B[162]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+163" size="1" name="B[163]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+164" size="1" name="B[164]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+165" size="1" name="B[165]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+166" size="1" name="B[166]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+167" size="1" name="B[167]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+168" size="1" name="B[168]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+169" size="1" name="B[169]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+170" size="1" name="B[170]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+171" size="1" name="B[171]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+172" size="1" name="B[172]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+173" size="1" name="B[173]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+174" size="1" name="B[174]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+175" size="1" name="B[175]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+176" size="1" name="B[176]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+177" size="1" name="B[177]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+178" size="1" name="B[178]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+179" size="1" name="B[179]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+180" size="1" name="B[180]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+181" size="1" name="B[181]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+182" size="1" name="B[182]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+183" size="1" name="B[183]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+184" size="1" name="B[184]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+185" size="1" name="B[185]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+186" size="1" name="B[186]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+187" size="1" name="B[187]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+188" size="1" name="B[188]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+189" size="1" name="B[189]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+190" size="1" name="B[190]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+191" size="1" name="B[191]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+192" size="1" name="B[192]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+193" size="1" name="B[193]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+194" size="1" name="B[194]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+195" size="1" name="B[195]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+196" size="1" name="B[196]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+197" size="1" name="B[197]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+198" size="1" name="B[198]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+199" size="1" name="B[199]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+200" size="1" name="B[200]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+201" size="1" name="B[201]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+202" size="1" name="B[202]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+203" size="1" name="B[203]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+204" size="1" name="B[204]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+205" size="1" name="B[205]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+206" size="1" name="B[206]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+207" size="1" name="B[207]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+208" size="1" name="B[208]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+209" size="1" name="B[209]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+210" size="1" name="B[210]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+211" size="1" name="B[211]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+212" size="1" name="B[212]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+213" size="1" name="B[213]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+214" size="1" name="B[214]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+215" size="1" name="B[215]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+216" size="1" name="B[216]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+217" size="1" name="B[217]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+218" size="1" name="B[218]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+219" size="1" name="B[219]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+220" size="1" name="B[220]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+221" size="1" name="B[221]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+222" size="1" name="B[222]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+223" size="1" name="B[223]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+224" size="1" name="B[224]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+225" size="1" name="B[225]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+226" size="1" name="B[226]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+227" size="1" name="B[227]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+228" size="1" name="B[228]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+229" size="1" name="B[229]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+230" size="1" name="B[230]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+231" size="1" name="B[231]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+232" size="1" name="B[232]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+233" size="1" name="B[233]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+234" size="1" name="B[234]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+235" size="1" name="B[235]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+236" size="1" name="B[236]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+237" size="1" name="B[237]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+238" size="1" name="B[238]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+239" size="1" name="B[239]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+240" size="1" name="B[240]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+241" size="1" name="B[241]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+242" size="1" name="B[242]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+243" size="1" name="B[243]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+244" size="1" name="B[244]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+245" size="1" name="B[245]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+246" size="1" name="B[246]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+247" size="1" name="B[247]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+248" size="1" name="B[248]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+249" size="1" name="B[249]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+250" size="1" name="B[250]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+251" size="1" name="B[251]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+252" size="1" name="B[252]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+253" size="1" name="B[253]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+254" size="1" name="B[254]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x0000+255" size="1" name="B[255]" access="Read/Write" description="Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31" reset_value="0" reset_mask="0xFF">
+      <BitField start="0" size="1" name="PBYTE" description="Read: state of the GPIOm[n] pin, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. Write: loads the pin's output bit." />
+    </Register>
+    <Register start="+0x1000+0" size="4" name="W[0]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+4" size="4" name="W[1]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+8" size="4" name="W[2]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+12" size="4" name="W[3]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+16" size="4" name="W[4]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+20" size="4" name="W[5]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+24" size="4" name="W[6]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+28" size="4" name="W[7]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+32" size="4" name="W[8]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+36" size="4" name="W[9]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+40" size="4" name="W[10]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+44" size="4" name="W[11]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+48" size="4" name="W[12]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+52" size="4" name="W[13]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+56" size="4" name="W[14]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+60" size="4" name="W[15]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+64" size="4" name="W[16]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+68" size="4" name="W[17]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+72" size="4" name="W[18]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+76" size="4" name="W[19]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+80" size="4" name="W[20]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+84" size="4" name="W[21]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+88" size="4" name="W[22]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+92" size="4" name="W[23]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+96" size="4" name="W[24]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+100" size="4" name="W[25]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+104" size="4" name="W[26]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+108" size="4" name="W[27]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+112" size="4" name="W[28]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+116" size="4" name="W[29]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+120" size="4" name="W[30]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+124" size="4" name="W[31]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+128" size="4" name="W[32]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+132" size="4" name="W[33]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+136" size="4" name="W[34]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+140" size="4" name="W[35]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+144" size="4" name="W[36]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+148" size="4" name="W[37]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+152" size="4" name="W[38]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+156" size="4" name="W[39]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+160" size="4" name="W[40]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+164" size="4" name="W[41]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+168" size="4" name="W[42]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+172" size="4" name="W[43]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+176" size="4" name="W[44]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+180" size="4" name="W[45]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+184" size="4" name="W[46]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+188" size="4" name="W[47]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+192" size="4" name="W[48]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+196" size="4" name="W[49]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+200" size="4" name="W[50]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+204" size="4" name="W[51]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+208" size="4" name="W[52]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+212" size="4" name="W[53]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+216" size="4" name="W[54]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+220" size="4" name="W[55]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+224" size="4" name="W[56]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+228" size="4" name="W[57]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+232" size="4" name="W[58]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+236" size="4" name="W[59]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+240" size="4" name="W[60]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+244" size="4" name="W[61]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+248" size="4" name="W[62]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+252" size="4" name="W[63]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+256" size="4" name="W[64]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+260" size="4" name="W[65]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+264" size="4" name="W[66]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+268" size="4" name="W[67]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+272" size="4" name="W[68]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+276" size="4" name="W[69]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+280" size="4" name="W[70]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+284" size="4" name="W[71]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+288" size="4" name="W[72]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+292" size="4" name="W[73]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+296" size="4" name="W[74]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+300" size="4" name="W[75]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+304" size="4" name="W[76]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+308" size="4" name="W[77]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+312" size="4" name="W[78]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+316" size="4" name="W[79]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+320" size="4" name="W[80]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+324" size="4" name="W[81]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+328" size="4" name="W[82]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+332" size="4" name="W[83]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+336" size="4" name="W[84]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+340" size="4" name="W[85]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+344" size="4" name="W[86]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+348" size="4" name="W[87]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+352" size="4" name="W[88]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+356" size="4" name="W[89]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+360" size="4" name="W[90]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+364" size="4" name="W[91]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+368" size="4" name="W[92]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+372" size="4" name="W[93]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+376" size="4" name="W[94]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+380" size="4" name="W[95]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+384" size="4" name="W[96]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+388" size="4" name="W[97]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+392" size="4" name="W[98]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+396" size="4" name="W[99]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+400" size="4" name="W[100]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+404" size="4" name="W[101]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+408" size="4" name="W[102]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+412" size="4" name="W[103]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+416" size="4" name="W[104]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+420" size="4" name="W[105]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+424" size="4" name="W[106]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+428" size="4" name="W[107]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+432" size="4" name="W[108]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+436" size="4" name="W[109]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+440" size="4" name="W[110]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+444" size="4" name="W[111]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+448" size="4" name="W[112]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+452" size="4" name="W[113]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+456" size="4" name="W[114]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+460" size="4" name="W[115]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+464" size="4" name="W[116]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+468" size="4" name="W[117]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+472" size="4" name="W[118]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+476" size="4" name="W[119]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+480" size="4" name="W[120]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+484" size="4" name="W[121]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+488" size="4" name="W[122]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+492" size="4" name="W[123]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+496" size="4" name="W[124]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+500" size="4" name="W[125]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+504" size="4" name="W[126]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+508" size="4" name="W[127]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+512" size="4" name="W[128]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+516" size="4" name="W[129]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+520" size="4" name="W[130]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+524" size="4" name="W[131]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+528" size="4" name="W[132]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+532" size="4" name="W[133]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+536" size="4" name="W[134]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+540" size="4" name="W[135]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+544" size="4" name="W[136]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+548" size="4" name="W[137]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+552" size="4" name="W[138]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+556" size="4" name="W[139]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+560" size="4" name="W[140]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+564" size="4" name="W[141]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+568" size="4" name="W[142]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+572" size="4" name="W[143]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+576" size="4" name="W[144]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+580" size="4" name="W[145]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+584" size="4" name="W[146]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+588" size="4" name="W[147]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+592" size="4" name="W[148]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+596" size="4" name="W[149]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+600" size="4" name="W[150]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+604" size="4" name="W[151]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+608" size="4" name="W[152]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+612" size="4" name="W[153]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+616" size="4" name="W[154]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+620" size="4" name="W[155]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+624" size="4" name="W[156]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+628" size="4" name="W[157]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+632" size="4" name="W[158]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+636" size="4" name="W[159]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+640" size="4" name="W[160]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+644" size="4" name="W[161]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+648" size="4" name="W[162]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+652" size="4" name="W[163]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+656" size="4" name="W[164]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+660" size="4" name="W[165]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+664" size="4" name="W[166]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+668" size="4" name="W[167]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+672" size="4" name="W[168]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+676" size="4" name="W[169]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+680" size="4" name="W[170]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+684" size="4" name="W[171]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+688" size="4" name="W[172]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+692" size="4" name="W[173]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+696" size="4" name="W[174]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+700" size="4" name="W[175]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+704" size="4" name="W[176]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+708" size="4" name="W[177]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+712" size="4" name="W[178]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+716" size="4" name="W[179]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+720" size="4" name="W[180]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+724" size="4" name="W[181]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+728" size="4" name="W[182]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+732" size="4" name="W[183]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+736" size="4" name="W[184]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+740" size="4" name="W[185]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+744" size="4" name="W[186]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+748" size="4" name="W[187]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+752" size="4" name="W[188]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+756" size="4" name="W[189]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+760" size="4" name="W[190]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+764" size="4" name="W[191]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+768" size="4" name="W[192]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+772" size="4" name="W[193]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+776" size="4" name="W[194]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+780" size="4" name="W[195]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+784" size="4" name="W[196]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+788" size="4" name="W[197]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+792" size="4" name="W[198]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+796" size="4" name="W[199]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+800" size="4" name="W[200]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+804" size="4" name="W[201]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+808" size="4" name="W[202]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+812" size="4" name="W[203]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+816" size="4" name="W[204]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+820" size="4" name="W[205]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+824" size="4" name="W[206]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+828" size="4" name="W[207]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+832" size="4" name="W[208]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+836" size="4" name="W[209]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+840" size="4" name="W[210]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+844" size="4" name="W[211]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+848" size="4" name="W[212]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+852" size="4" name="W[213]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+856" size="4" name="W[214]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+860" size="4" name="W[215]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+864" size="4" name="W[216]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+868" size="4" name="W[217]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+872" size="4" name="W[218]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+876" size="4" name="W[219]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+880" size="4" name="W[220]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+884" size="4" name="W[221]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+888" size="4" name="W[222]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+892" size="4" name="W[223]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+896" size="4" name="W[224]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+900" size="4" name="W[225]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+904" size="4" name="W[226]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+908" size="4" name="W[227]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+912" size="4" name="W[228]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+916" size="4" name="W[229]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+920" size="4" name="W[230]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+924" size="4" name="W[231]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+928" size="4" name="W[232]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+932" size="4" name="W[233]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+936" size="4" name="W[234]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+940" size="4" name="W[235]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+944" size="4" name="W[236]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+948" size="4" name="W[237]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+952" size="4" name="W[238]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+956" size="4" name="W[239]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+960" size="4" name="W[240]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+964" size="4" name="W[241]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+968" size="4" name="W[242]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+972" size="4" name="W[243]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+976" size="4" name="W[244]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+980" size="4" name="W[245]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+984" size="4" name="W[246]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+988" size="4" name="W[247]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+992" size="4" name="W[248]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+996" size="4" name="W[249]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+1000" size="4" name="W[250]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+1004" size="4" name="W[251]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+1008" size="4" name="W[252]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+1012" size="4" name="W[253]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+1016" size="4" name="W[254]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x1000+1020" size="4" name="W[255]" access="Read/Write" description="Word pin registers port 0 to 5" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="PWORD" description="Read 0: pin is LOW.  Write 0: clear output bit. Read 0xFFFF FFFF: pin is HIGH.  Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit." />
+    </Register>
+    <Register start="+0x2000+0" size="4" name="DIR0" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+    </Register>
+    <Register start="+0x2000+4" size="4" name="DIR1" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+    </Register>
+    <Register start="+0x2000+8" size="4" name="DIR2" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+    </Register>
+    <Register start="+0x2000+12" size="4" name="DIR3" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+    </Register>
+    <Register start="+0x2000+16" size="4" name="DIR4" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+    </Register>
+    <Register start="+0x2000+20" size="4" name="DIR5" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+    </Register>
+    <Register start="+0x2000+24" size="4" name="DIR6" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+    </Register>
+    <Register start="+0x2000+28" size="4" name="DIR7" access="Read/Write" description="Direction registers port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="DIRP0" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="1" size="1" name="DIRP1" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="2" size="1" name="DIRP2" description="Selects pin direction for  GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="3" size="1" name="DIRP3" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="4" size="1" name="DIRP4" description="Selects pin direction for GPIOm[n] pin (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="5" size="1" name="DIRP5" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="6" size="1" name="DIRP6" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="7" size="1" name="DIRP7" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="8" size="1" name="DIRP8" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="9" size="1" name="DIRP9" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="10" size="1" name="DIRP10" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="11" size="1" name="DIRP11" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="12" size="1" name="DIRP12" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="13" size="1" name="DIRP13" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="14" size="1" name="DIRP14" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="15" size="1" name="DIRP15" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="16" size="1" name="DIRP16" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="17" size="1" name="DIRP17" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="18" size="1" name="DIRP18" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="19" size="1" name="DIRP19" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="20" size="1" name="DIRP20" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="21" size="1" name="DIRP21" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="22" size="1" name="DIRP22" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="23" size="1" name="DIRP23" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="24" size="1" name="DIRP24" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="25" size="1" name="DIRP25" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="26" size="1" name="DIRP26" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="27" size="1" name="DIRP27" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="28" size="1" name="DIRP28" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="29" size="1" name="DIRP29" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="30" size="1" name="DIRP30" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+      <BitField start="31" size="1" name="DIRP31" description="Selects pin direction for pin GPIOm[n] (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = input. 1 = output." />
+    </Register>
+    <Register start="+0x2080+0" size="4" name="MASK0" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+    </Register>
+    <Register start="+0x2080+4" size="4" name="MASK1" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+    </Register>
+    <Register start="+0x2080+8" size="4" name="MASK2" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+    </Register>
+    <Register start="+0x2080+12" size="4" name="MASK3" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+    </Register>
+    <Register start="+0x2080+16" size="4" name="MASK4" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+    </Register>
+    <Register start="+0x2080+20" size="4" name="MASK5" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+    </Register>
+    <Register start="+0x2080+24" size="4" name="MASK6" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+    </Register>
+    <Register start="+0x2080+28" size="4" name="MASK7" access="Read/Write" description="Mask register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MASKP0" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="1" size="1" name="MASKP1" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="2" size="1" name="MASKP2" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="3" size="1" name="MASKP3" description="Controls which bits corresponding to GPIOm[n] are active in the PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="4" size="1" name="MASKP4" description="Controls which bits corresponding to GPIOm[n] are active in the P0/1PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="5" size="1" name="MASKP5" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="6" size="1" name="MASKP6" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="7" size="1" name="MASKP7" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="8" size="1" name="MASKP8" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="9" size="1" name="MASKP9" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="10" size="1" name="MASKP10" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="11" size="1" name="MASKP11" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="12" size="1" name="MASKP12" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="13" size="1" name="MASKP13" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="14" size="1" name="MASKP14" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="15" size="1" name="MASKP15" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="16" size="1" name="MASKP16" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="17" size="1" name="MASKP17" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="18" size="1" name="MASKP18" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="19" size="1" name="MASKP19" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="20" size="1" name="MASKP20" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="21" size="1" name="MASKP21" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="22" size="1" name="MASKP22" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="23" size="1" name="MASKP23" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="24" size="1" name="MASKP24" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="25" size="1" name="MASKP25" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="26" size="1" name="MASKP26" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="27" size="1" name="MASKP27" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="28" size="1" name="MASKP28" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="29" size="1" name="MASKP29" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="30" size="1" name="MASKP30" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+      <BitField start="31" size="1" name="MASKP31" description="Controls which bits corresponding to GPIOm[n] are active in the  PIN register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected." />
+    </Register>
+    <Register start="+0x2100+0" size="4" name="PIN0" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+    </Register>
+    <Register start="+0x2100+4" size="4" name="PIN1" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+    </Register>
+    <Register start="+0x2100+8" size="4" name="PIN2" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+    </Register>
+    <Register start="+0x2100+12" size="4" name="PIN3" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+    </Register>
+    <Register start="+0x2100+16" size="4" name="PIN4" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+    </Register>
+    <Register start="+0x2100+20" size="4" name="PIN5" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+    </Register>
+    <Register start="+0x2100+24" size="4" name="PIN6" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+    </Register>
+    <Register start="+0x2100+28" size="4" name="PIN7" access="Read/Write" description="Port pin register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="PORT0" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="1" size="1" name="PORT1" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="2" size="1" name="PORT2" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="3" size="1" name="PORT3" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="4" size="1" name="PORT4" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="5" size="1" name="PORT5" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="6" size="1" name="PORT6" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="7" size="1" name="PORT7" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="8" size="1" name="PORT8" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="9" size="1" name="PORT9" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="10" size="1" name="PORT10" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="11" size="1" name="PORT11" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="12" size="1" name="PORT12" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="13" size="1" name="PORT13" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="14" size="1" name="PORT14" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="15" size="1" name="PORT15" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="16" size="1" name="PORT16" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="17" size="1" name="PORT17" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="18" size="1" name="PORT18" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="19" size="1" name="PORT19" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="20" size="1" name="PORT20" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="21" size="1" name="PORT21" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="22" size="1" name="PORT22" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="23" size="1" name="PORT23" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="24" size="1" name="PORT24" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="25" size="1" name="PORT25" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="26" size="1" name="PORT26" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="27" size="1" name="PORT27" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="28" size="1" name="PORT28" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="29" size="1" name="PORT29" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="30" size="1" name="PORT30" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+      <BitField start="31" size="1" name="PORT31" description="Reads pin states or loads output bits (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit." />
+    </Register>
+    <Register start="+0x2180+0" size="4" name="MPIN0" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+    </Register>
+    <Register start="+0x2180+4" size="4" name="MPIN1" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+    </Register>
+    <Register start="+0x2180+8" size="4" name="MPIN2" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+    </Register>
+    <Register start="+0x2180+12" size="4" name="MPIN3" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+    </Register>
+    <Register start="+0x2180+16" size="4" name="MPIN4" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+    </Register>
+    <Register start="+0x2180+20" size="4" name="MPIN5" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+    </Register>
+    <Register start="+0x2180+24" size="4" name="MPIN6" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+    </Register>
+    <Register start="+0x2180+28" size="4" name="MPIN7" access="Read/Write" description="Masked port register port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MPORTP0" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="1" size="1" name="MPORTP1" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="2" size="1" name="MPORTP2" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="3" size="1" name="MPORTP3" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="4" size="1" name="MPORTP4" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="5" size="1" name="MPORTP5" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="6" size="1" name="MPORTP6" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="7" size="1" name="MPORTP7" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="8" size="1" name="MPORTP8" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="9" size="1" name="MPORTP9" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="10" size="1" name="MPORTP10" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="11" size="1" name="MPORTP11" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="12" size="1" name="MPORTP12" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="13" size="1" name="MPORTP13" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="14" size="1" name="MPORTP14" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="15" size="1" name="MPORTP15" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="16" size="1" name="MPORTP16" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="17" size="1" name="MPORTP17" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="18" size="1" name="MPORTP18" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="19" size="1" name="MPORTP19" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="20" size="1" name="MPORTP20" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="21" size="1" name="MPORTP21" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="22" size="1" name="MPORTP22" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="23" size="1" name="MPORTP23" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="24" size="1" name="MPORTP24" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="25" size="1" name="MPORTP25" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="26" size="1" name="MPORTP26" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="27" size="1" name="MPORTP27" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="28" size="1" name="MPORTP28" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="29" size="1" name="MPORTP29" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="30" size="1" name="MPORTP30" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+      <BitField start="31" size="1" name="MPORTP31" description="Masked port register (bit 0 = GPIOm[0], bit 1 = GPIOm[1], ..., bit 31 = GPIOm[31]). 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0." />
+    </Register>
+    <Register start="+0x2200+0" size="4" name="SET0" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+    </Register>
+    <Register start="+0x2200+4" size="4" name="SET1" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+    </Register>
+    <Register start="+0x2200+8" size="4" name="SET2" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+    </Register>
+    <Register start="+0x2200+12" size="4" name="SET3" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+    </Register>
+    <Register start="+0x2200+16" size="4" name="SET4" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+    </Register>
+    <Register start="+0x2200+20" size="4" name="SET5" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+    </Register>
+    <Register start="+0x2200+24" size="4" name="SET6" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+    </Register>
+    <Register start="+0x2200+28" size="4" name="SET7" access="Read/Write" description="Write: Set register for port m  Read: output bits for port m" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SETP0" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="1" size="1" name="SETP1" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="2" size="1" name="SETP2" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="3" size="1" name="SETP3" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="4" size="1" name="SETP4" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="5" size="1" name="SETP5" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="6" size="1" name="SETP6" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="7" size="1" name="SETP7" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="8" size="1" name="SETP8" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="9" size="1" name="SETP9" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="10" size="1" name="SETP10" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="11" size="1" name="SETP11" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="12" size="1" name="SETP12" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="13" size="1" name="SETP13" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="14" size="1" name="SETP14" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="15" size="1" name="SETP15" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="16" size="1" name="SETP16" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="17" size="1" name="SETP17" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="18" size="1" name="SETP18" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="19" size="1" name="SETP19" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="20" size="1" name="SETP20" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="21" size="1" name="SETP21" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="22" size="1" name="SETP22" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="23" size="1" name="SETP23" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="24" size="1" name="SETP24" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="25" size="1" name="SETP25" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="26" size="1" name="SETP26" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="27" size="1" name="SETP27" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="28" size="1" name="SETP28" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="29" size="1" name="SETP29" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="30" size="1" name="SETP30" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+      <BitField start="31" size="1" name="SETP31" description="Read or set output bits. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit." />
+    </Register>
+    <Register start="+0x2280+0" size="4" name="CLR0" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+    </Register>
+    <Register start="+0x2280+4" size="4" name="CLR1" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+    </Register>
+    <Register start="+0x2280+8" size="4" name="CLR2" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+    </Register>
+    <Register start="+0x2280+12" size="4" name="CLR3" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+    </Register>
+    <Register start="+0x2280+16" size="4" name="CLR4" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+    </Register>
+    <Register start="+0x2280+20" size="4" name="CLR5" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+    </Register>
+    <Register start="+0x2280+24" size="4" name="CLR6" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+    </Register>
+    <Register start="+0x2280+28" size="4" name="CLR7" access="WriteOnly" description="Clear port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="CLRP00" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="1" size="1" name="CLRP01" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="2" size="1" name="CLRP02" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="3" size="1" name="CLRP03" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="4" size="1" name="CLRP04" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="5" size="1" name="CLRP05" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="6" size="1" name="CLRP06" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="7" size="1" name="CLRP07" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="8" size="1" name="CLRP08" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="9" size="1" name="CLRP09" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="10" size="1" name="CLRP010" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="11" size="1" name="CLRP011" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="12" size="1" name="CLRP012" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="13" size="1" name="CLRP013" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="14" size="1" name="CLRP014" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="15" size="1" name="CLRP015" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="16" size="1" name="CLRP016" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="17" size="1" name="CLRP017" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="18" size="1" name="CLRP018" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="19" size="1" name="CLRP019" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="20" size="1" name="CLRP020" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="21" size="1" name="CLRP021" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="22" size="1" name="CLRP022" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="23" size="1" name="CLRP023" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="24" size="1" name="CLRP024" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="25" size="1" name="CLRP025" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="26" size="1" name="CLRP026" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="27" size="1" name="CLRP027" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="28" size="1" name="CLRP028" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="29" size="1" name="CLRP029" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="30" size="1" name="CLRP030" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+      <BitField start="31" size="1" name="CLRP031" description="Clear output bits: 0 = No operation. 1 = Clear output bit." />
+    </Register>
+    <Register start="+0x2300+0" size="4" name="NOT0" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+    </Register>
+    <Register start="+0x2300+4" size="4" name="NOT1" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+    </Register>
+    <Register start="+0x2300+8" size="4" name="NOT2" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+    </Register>
+    <Register start="+0x2300+12" size="4" name="NOT3" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+    </Register>
+    <Register start="+0x2300+16" size="4" name="NOT4" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+    </Register>
+    <Register start="+0x2300+20" size="4" name="NOT5" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+    </Register>
+    <Register start="+0x2300+24" size="4" name="NOT6" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+    </Register>
+    <Register start="+0x2300+28" size="4" name="NOT7" access="WriteOnly" description="Toggle port m" reset_value="0" reset_mask="0x00000000">
+      <BitField start="0" size="1" name="NOTP0" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="1" size="1" name="NOTP1" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="2" size="1" name="NOTP2" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="3" size="1" name="NOTP3" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="4" size="1" name="NOTP4" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="5" size="1" name="NOTP5" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="6" size="1" name="NOTP6" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="7" size="1" name="NOTP7" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="8" size="1" name="NOTP8" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="9" size="1" name="NOTP9" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="10" size="1" name="NOTP10" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="11" size="1" name="NOTP11" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="12" size="1" name="NOTP12" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="13" size="1" name="NOTP13" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="14" size="1" name="NOTP14" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="15" size="1" name="NOTP15" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="16" size="1" name="NOTP16" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="17" size="1" name="NOTP17" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="18" size="1" name="NOTP18" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="19" size="1" name="NOTP19" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="20" size="1" name="NOTP20" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="21" size="1" name="NOTP21" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="22" size="1" name="NOTP22" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="23" size="1" name="NOTP23" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="24" size="1" name="NOTP24" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="25" size="1" name="NOTP25" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="26" size="1" name="NOTP26" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="27" size="1" name="NOTP27" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="28" size="1" name="NOTP28" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="29" size="1" name="NOTP29" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="30" size="1" name="NOTP30" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+      <BitField start="31" size="1" name="NOTP31" description="Toggle output bits: 0 = no operation. 1 = Toggle output bit." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI" start="0x40100000" description="SPI ">
+    <Register start="+0x000" size="4" name="CR" access="Read/Write" description="SPI Control Register. This register controls the operation of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="2" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="2" size="1" name="BITENABLE" description="The SPI controller sends and receives 8 bits of data per transfer.">
+        <Enum name="THE_SPI_CONTROLLER_S" start="1" description="The SPI controller sends and receives the number of bits selected by bits 11:8." />
+      </BitField>
+      <BitField start="3" size="1" name="CPHA" description="Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending.">
+        <Enum name="FIRST_EDGE" start="0" description="Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal." />
+        <Enum name="SECOND_EDGE" start="1" description="Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active." />
+      </BitField>
+      <BitField start="4" size="1" name="CPOL" description="Clock polarity control.">
+        <Enum name="SCK_IS_ACTIVE_HIGH_" start="0" description="SCK is active high." />
+        <Enum name="SCK_IS_ACTIVE_LOW_" start="1" description="SCK is active low." />
+      </BitField>
+      <BitField start="5" size="1" name="MSTR" description="Master mode select.">
+        <Enum name="SLAVE" start="0" description="The SPI operates in Slave mode." />
+        <Enum name="MASTER" start="1" description="The SPI operates in Master mode." />
+      </BitField>
+      <BitField start="6" size="1" name="LSBF" description="LSB First controls which direction each byte is shifted when transferred.">
+        <Enum name="MSB" start="0" description="SPI data is transferred MSB (bit 7) first." />
+        <Enum name="LSB" start="1" description="SPI data is transferred LSB (bit 0) first." />
+      </BitField>
+      <BitField start="7" size="1" name="SPIE" description="Serial peripheral interrupt enable.">
+        <Enum name="INTBLOCK" start="0" description="SPI interrupts are inhibited." />
+        <Enum name="HWINT" start="1" description="A hardware interrupt is generated each time the SPIF or MODF bits are activated." />
+      </BitField>
+      <BitField start="8" size="4" name="BITS" description="When bit 2 of this register is 1, this field controls the number of bits per transfer:">
+        <Enum name="8_BITS_PER_TRANSFER" start="0x8" description="8 bits per transfer" />
+        <Enum name="9_BITS_PER_TRANSFER" start="0x9" description="9 bits per transfer" />
+        <Enum name="10_BITS_PER_TRANSFER" start="0xA" description="10 bits per transfer" />
+        <Enum name="11_BITS_PER_TRANSFER" start="0xB" description="11 bits per transfer" />
+        <Enum name="12_BITS_PER_TRANSFER" start="0xC" description="12 bits per transfer" />
+        <Enum name="13_BITS_PER_TRANSFER" start="0xD" description="13 bits per transfer" />
+        <Enum name="14_BITS_PER_TRANSFER" start="0xE" description="14 bits per transfer" />
+        <Enum name="15_BITS_PER_TRANSFER" start="0xF" description="15 bits per transfer" />
+        <Enum name="16_BITS_PER_TRANSFER" start="0x0" description="16 bits per transfer" />
+      </BitField>
+      <BitField start="12" size="20" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x004" size="4" name="SR" access="ReadOnly" description="SPI Status Register. This register shows the status of the SPI." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="1" name="ABRT" description="Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register." />
+      <BitField start="4" size="1" name="MODF" description="Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register." />
+      <BitField start="5" size="1" name="ROVR" description="Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register." />
+      <BitField start="6" size="1" name="WCOL" description="Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register." />
+      <BitField start="7" size="1" name="SPIF" description="SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x008" size="4" name="DR" access="None" description="SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="DATALOW" description="SPI Bi-directional data port." />
+      <BitField start="8" size="8" name="DATAHIGH" description="If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x00C" size="4" name="CCR" access="Read/Write" description="SPI Clock Counter Register. This register controls the frequency of a master's SCK0." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="COUNTER" description="SPI0 Clock counter setting." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x010" size="4" name="TCR" access="Read/Write" description="SPI Test Control register. For functional testing only." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="1" size="7" name="TEST" description="SPI test mode. When 0, the SPI operates normally. When 1, SCK will always be on, independent of master mode select and data availability setting." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x014" size="4" name="TSR" access="Read/Write" description="SPI Test Status register. For functional testing only." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="3" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="3" size="1" name="ABRT" description="Slave abort." />
+      <BitField start="4" size="1" name="MODF" description="Mode fault." />
+      <BitField start="5" size="1" name="ROVR" description="Read overrun." />
+      <BitField start="6" size="1" name="WCOL" description="Write collision." />
+      <BitField start="7" size="1" name="SPIF" description="SPI transfer complete flag." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+    <Register start="+0x01C" size="4" name="INT" access="Read/Write" description="SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface." reset_value="0x00" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="SPIF" description="SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software." />
+      <BitField start="1" size="7" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+      <BitField start="8" size="24" name="RESERVED" description="Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SGPIO" start="0x40101000" description="Serial GPIO (SGPIO)">
+    <Register start="+0x0000+0" size="4" name="OUT_MUX_CFG[0]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
+        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
+        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
+        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
+        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
+        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
+        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
+        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
+        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
+        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
+        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
+        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
+        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
+      </BitField>
+      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
+        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
+        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
+        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
+        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
+        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0000+4" size="4" name="OUT_MUX_CFG[1]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
+        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
+        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
+        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
+        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
+        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
+        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
+        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
+        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
+        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
+        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
+        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
+        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
+      </BitField>
+      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
+        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
+        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
+        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
+        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
+        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0000+8" size="4" name="OUT_MUX_CFG[2]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
+        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
+        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
+        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
+        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
+        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
+        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
+        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
+        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
+        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
+        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
+        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
+        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
+      </BitField>
+      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
+        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
+        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
+        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
+        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
+        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0000+12" size="4" name="OUT_MUX_CFG[3]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
+        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
+        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
+        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
+        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
+        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
+        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
+        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
+        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
+        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
+        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
+        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
+        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
+      </BitField>
+      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
+        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
+        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
+        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
+        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
+        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0000+16" size="4" name="OUT_MUX_CFG[4]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
+        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
+        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
+        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
+        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
+        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
+        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
+        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
+        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
+        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
+        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
+        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
+        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
+      </BitField>
+      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
+        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
+        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
+        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
+        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
+        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0000+20" size="4" name="OUT_MUX_CFG[5]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
+        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
+        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
+        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
+        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
+        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
+        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
+        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
+        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
+        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
+        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
+        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
+        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
+      </BitField>
+      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
+        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
+        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
+        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
+        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
+        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0000+24" size="4" name="OUT_MUX_CFG[6]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
+        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
+        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
+        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
+        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
+        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
+        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
+        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
+        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
+        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
+        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
+        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
+        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
+      </BitField>
+      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
+        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
+        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
+        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
+        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
+        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0000+28" size="4" name="OUT_MUX_CFG[7]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
+        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
+        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
+        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
+        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
+        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
+        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
+        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
+        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
+        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
+        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
+        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
+        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
+      </BitField>
+      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
+        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
+        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
+        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
+        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
+        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0000+32" size="4" name="OUT_MUX_CFG[8]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
+        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
+        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
+        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
+        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
+        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
+        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
+        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
+        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
+        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
+        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
+        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
+        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
+      </BitField>
+      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
+        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
+        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
+        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
+        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
+        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0000+36" size="4" name="OUT_MUX_CFG[9]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
+        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
+        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
+        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
+        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
+        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
+        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
+        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
+        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
+        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
+        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
+        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
+        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
+      </BitField>
+      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
+        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
+        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
+        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
+        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
+        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0000+40" size="4" name="OUT_MUX_CFG[10]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
+        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
+        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
+        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
+        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
+        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
+        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
+        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
+        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
+        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
+        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
+        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
+        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
+      </BitField>
+      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
+        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
+        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
+        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
+        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
+        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0000+44" size="4" name="OUT_MUX_CFG[11]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
+        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
+        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
+        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
+        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
+        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
+        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
+        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
+        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
+        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
+        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
+        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
+        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
+      </BitField>
+      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
+        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
+        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
+        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
+        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
+        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0000+48" size="4" name="OUT_MUX_CFG[12]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
+        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
+        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
+        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
+        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
+        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
+        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
+        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
+        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
+        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
+        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
+        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
+        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
+      </BitField>
+      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
+        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
+        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
+        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
+        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
+        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0000+52" size="4" name="OUT_MUX_CFG[13]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
+        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
+        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
+        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
+        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
+        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
+        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
+        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
+        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
+        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
+        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
+        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
+        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
+      </BitField>
+      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
+        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
+        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
+        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
+        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
+        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0000+56" size="4" name="OUT_MUX_CFG[14]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
+        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
+        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
+        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
+        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
+        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
+        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
+        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
+        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
+        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
+        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
+        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
+        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
+      </BitField>
+      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
+        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
+        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
+        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
+        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
+        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0000+60" size="4" name="OUT_MUX_CFG[15]" access="Read/Write" description="Pin multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="4" name="P_OUT_CFG" description="Output control of output SGPIOn. All other values are reserved.">
+        <Enum name="DOUT_DOUTM1" start="0x0" description="dout_doutm1 (1-bit mode)" />
+        <Enum name="DOUT_DOUTM2A" start="0x1" description="dout_doutm2a (2-bit mode 2a)" />
+        <Enum name="DOUT_DOUTM2B" start="0x2" description="dout_doutm2b (2-bit mode 2b)" />
+        <Enum name="DOUT_DOUTM2C" start="0x3" description="dout_doutm2c (2-bit mode 2c)" />
+        <Enum name="GPIO_OUT_LEVEL_SET" start="0x4" description="gpio_out (level set by GPIO_OUTREG)" />
+        <Enum name="DOUT_DOUTM4A" start="0x5" description="dout_doutm4a (4-bit mode 4a)" />
+        <Enum name="DOUT_DOUTM4B" start="0x6" description="dout_doutm4b (4-bit mode 4b)" />
+        <Enum name="DOUT_DOUTM4C" start="0x7" description="dout_doutm4c (4-bit mode 4c)" />
+        <Enum name="CLK_OUT" start="0x8" description="clk_out" />
+        <Enum name="DOUT_DOUTM8A" start="0x9" description="dout_doutm8a (8-bit mode 8a)" />
+        <Enum name="DOUT_DOUTM8B" start="0xA" description="dout_doutm8b (8-bit mode 8b)" />
+        <Enum name="DOUT_DOUTM8C" start="0xB" description="dout_doutm8c (8-bit mode 8c)" />
+      </BitField>
+      <BitField start="4" size="3" name="P_OE_CFG" description="Output enable source. All other values are reserved.">
+        <Enum name="GPIO_OE_STATE_SET_B" start="0x0" description="gpio_oe (state set by GPIO_OEREG)" />
+        <Enum name="DOUT_OEM1_1_BIT_MOD" start="0x4" description="dout_oem1 (1-bit mode)" />
+        <Enum name="DOUT_OEM2_2_BIT_MOD" start="0x5" description="dout_oem2 (2-bit mode)" />
+        <Enum name="DOUT_OEM4_4_BIT_MOD" start="0x6" description="dout_oem4 (4-bit mode)" />
+        <Enum name="DOUT_OEM8_8_BIT_MOD" start="0x7" description="dout_oem8 (8-bit mode)" />
+      </BitField>
+      <BitField start="7" size="25" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0040+0" size="4" name="SGPIO_MUX_CFG[0]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
+        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
+        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
+      </BitField>
+      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
+        <Enum name="SLICE_D" start="0x0" description="Slice D" />
+        <Enum name="SLICE_H" start="0x1" description="Slice H" />
+        <Enum name="SLICE_O" start="0x2" description="Slice O" />
+        <Enum name="SLICE_P" start="0x3" description="Slice P" />
+      </BitField>
+      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
+        <Enum name="ENABLE" start="0x0" description="Enable" />
+        <Enum name="DISABLE" start="0x1" description="Disable" />
+        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
+        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
+      </BitField>
+      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
+        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
+        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
+        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
+        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
+      </BitField>
+      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
+        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
+        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
+      </BitField>
+      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
+        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
+        <Enum name="2_SLICES" start="0x1" description="2 slices" />
+        <Enum name="4_SLICES" start="0x2" description="4 slices" />
+        <Enum name="8_SLICES" start="0x3" description="8 slices" />
+      </BitField>
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0040+4" size="4" name="SGPIO_MUX_CFG[1]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
+        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
+        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
+      </BitField>
+      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
+        <Enum name="SLICE_D" start="0x0" description="Slice D" />
+        <Enum name="SLICE_H" start="0x1" description="Slice H" />
+        <Enum name="SLICE_O" start="0x2" description="Slice O" />
+        <Enum name="SLICE_P" start="0x3" description="Slice P" />
+      </BitField>
+      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
+        <Enum name="ENABLE" start="0x0" description="Enable" />
+        <Enum name="DISABLE" start="0x1" description="Disable" />
+        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
+        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
+      </BitField>
+      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
+        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
+        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
+        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
+        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
+      </BitField>
+      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
+        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
+        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
+      </BitField>
+      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
+        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
+        <Enum name="2_SLICES" start="0x1" description="2 slices" />
+        <Enum name="4_SLICES" start="0x2" description="4 slices" />
+        <Enum name="8_SLICES" start="0x3" description="8 slices" />
+      </BitField>
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0040+8" size="4" name="SGPIO_MUX_CFG[2]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
+        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
+        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
+      </BitField>
+      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
+        <Enum name="SLICE_D" start="0x0" description="Slice D" />
+        <Enum name="SLICE_H" start="0x1" description="Slice H" />
+        <Enum name="SLICE_O" start="0x2" description="Slice O" />
+        <Enum name="SLICE_P" start="0x3" description="Slice P" />
+      </BitField>
+      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
+        <Enum name="ENABLE" start="0x0" description="Enable" />
+        <Enum name="DISABLE" start="0x1" description="Disable" />
+        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
+        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
+      </BitField>
+      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
+        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
+        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
+        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
+        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
+      </BitField>
+      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
+        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
+        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
+      </BitField>
+      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
+        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
+        <Enum name="2_SLICES" start="0x1" description="2 slices" />
+        <Enum name="4_SLICES" start="0x2" description="4 slices" />
+        <Enum name="8_SLICES" start="0x3" description="8 slices" />
+      </BitField>
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0040+12" size="4" name="SGPIO_MUX_CFG[3]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
+        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
+        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
+      </BitField>
+      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
+        <Enum name="SLICE_D" start="0x0" description="Slice D" />
+        <Enum name="SLICE_H" start="0x1" description="Slice H" />
+        <Enum name="SLICE_O" start="0x2" description="Slice O" />
+        <Enum name="SLICE_P" start="0x3" description="Slice P" />
+      </BitField>
+      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
+        <Enum name="ENABLE" start="0x0" description="Enable" />
+        <Enum name="DISABLE" start="0x1" description="Disable" />
+        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
+        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
+      </BitField>
+      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
+        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
+        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
+        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
+        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
+      </BitField>
+      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
+        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
+        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
+      </BitField>
+      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
+        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
+        <Enum name="2_SLICES" start="0x1" description="2 slices" />
+        <Enum name="4_SLICES" start="0x2" description="4 slices" />
+        <Enum name="8_SLICES" start="0x3" description="8 slices" />
+      </BitField>
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0040+16" size="4" name="SGPIO_MUX_CFG[4]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
+        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
+        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
+      </BitField>
+      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
+        <Enum name="SLICE_D" start="0x0" description="Slice D" />
+        <Enum name="SLICE_H" start="0x1" description="Slice H" />
+        <Enum name="SLICE_O" start="0x2" description="Slice O" />
+        <Enum name="SLICE_P" start="0x3" description="Slice P" />
+      </BitField>
+      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
+        <Enum name="ENABLE" start="0x0" description="Enable" />
+        <Enum name="DISABLE" start="0x1" description="Disable" />
+        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
+        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
+      </BitField>
+      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
+        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
+        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
+        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
+        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
+      </BitField>
+      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
+        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
+        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
+      </BitField>
+      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
+        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
+        <Enum name="2_SLICES" start="0x1" description="2 slices" />
+        <Enum name="4_SLICES" start="0x2" description="4 slices" />
+        <Enum name="8_SLICES" start="0x3" description="8 slices" />
+      </BitField>
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0040+20" size="4" name="SGPIO_MUX_CFG[5]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
+        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
+        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
+      </BitField>
+      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
+        <Enum name="SLICE_D" start="0x0" description="Slice D" />
+        <Enum name="SLICE_H" start="0x1" description="Slice H" />
+        <Enum name="SLICE_O" start="0x2" description="Slice O" />
+        <Enum name="SLICE_P" start="0x3" description="Slice P" />
+      </BitField>
+      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
+        <Enum name="ENABLE" start="0x0" description="Enable" />
+        <Enum name="DISABLE" start="0x1" description="Disable" />
+        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
+        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
+      </BitField>
+      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
+        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
+        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
+        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
+        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
+      </BitField>
+      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
+        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
+        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
+      </BitField>
+      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
+        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
+        <Enum name="2_SLICES" start="0x1" description="2 slices" />
+        <Enum name="4_SLICES" start="0x2" description="4 slices" />
+        <Enum name="8_SLICES" start="0x3" description="8 slices" />
+      </BitField>
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0040+24" size="4" name="SGPIO_MUX_CFG[6]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
+        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
+        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
+      </BitField>
+      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
+        <Enum name="SLICE_D" start="0x0" description="Slice D" />
+        <Enum name="SLICE_H" start="0x1" description="Slice H" />
+        <Enum name="SLICE_O" start="0x2" description="Slice O" />
+        <Enum name="SLICE_P" start="0x3" description="Slice P" />
+      </BitField>
+      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
+        <Enum name="ENABLE" start="0x0" description="Enable" />
+        <Enum name="DISABLE" start="0x1" description="Disable" />
+        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
+        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
+      </BitField>
+      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
+        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
+        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
+        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
+        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
+      </BitField>
+      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
+        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
+        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
+      </BitField>
+      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
+        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
+        <Enum name="2_SLICES" start="0x1" description="2 slices" />
+        <Enum name="4_SLICES" start="0x2" description="4 slices" />
+        <Enum name="8_SLICES" start="0x3" description="8 slices" />
+      </BitField>
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0040+28" size="4" name="SGPIO_MUX_CFG[7]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
+        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
+        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
+      </BitField>
+      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
+        <Enum name="SLICE_D" start="0x0" description="Slice D" />
+        <Enum name="SLICE_H" start="0x1" description="Slice H" />
+        <Enum name="SLICE_O" start="0x2" description="Slice O" />
+        <Enum name="SLICE_P" start="0x3" description="Slice P" />
+      </BitField>
+      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
+        <Enum name="ENABLE" start="0x0" description="Enable" />
+        <Enum name="DISABLE" start="0x1" description="Disable" />
+        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
+        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
+      </BitField>
+      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
+        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
+        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
+        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
+        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
+      </BitField>
+      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
+        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
+        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
+      </BitField>
+      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
+        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
+        <Enum name="2_SLICES" start="0x1" description="2 slices" />
+        <Enum name="4_SLICES" start="0x2" description="4 slices" />
+        <Enum name="8_SLICES" start="0x3" description="8 slices" />
+      </BitField>
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0040+32" size="4" name="SGPIO_MUX_CFG[8]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
+        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
+        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
+      </BitField>
+      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
+        <Enum name="SLICE_D" start="0x0" description="Slice D" />
+        <Enum name="SLICE_H" start="0x1" description="Slice H" />
+        <Enum name="SLICE_O" start="0x2" description="Slice O" />
+        <Enum name="SLICE_P" start="0x3" description="Slice P" />
+      </BitField>
+      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
+        <Enum name="ENABLE" start="0x0" description="Enable" />
+        <Enum name="DISABLE" start="0x1" description="Disable" />
+        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
+        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
+      </BitField>
+      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
+        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
+        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
+        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
+        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
+      </BitField>
+      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
+        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
+        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
+      </BitField>
+      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
+        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
+        <Enum name="2_SLICES" start="0x1" description="2 slices" />
+        <Enum name="4_SLICES" start="0x2" description="4 slices" />
+        <Enum name="8_SLICES" start="0x3" description="8 slices" />
+      </BitField>
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0040+36" size="4" name="SGPIO_MUX_CFG[9]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
+        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
+        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
+      </BitField>
+      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
+        <Enum name="SLICE_D" start="0x0" description="Slice D" />
+        <Enum name="SLICE_H" start="0x1" description="Slice H" />
+        <Enum name="SLICE_O" start="0x2" description="Slice O" />
+        <Enum name="SLICE_P" start="0x3" description="Slice P" />
+      </BitField>
+      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
+        <Enum name="ENABLE" start="0x0" description="Enable" />
+        <Enum name="DISABLE" start="0x1" description="Disable" />
+        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
+        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
+      </BitField>
+      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
+        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
+        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
+        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
+        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
+      </BitField>
+      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
+        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
+        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
+      </BitField>
+      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
+        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
+        <Enum name="2_SLICES" start="0x1" description="2 slices" />
+        <Enum name="4_SLICES" start="0x2" description="4 slices" />
+        <Enum name="8_SLICES" start="0x3" description="8 slices" />
+      </BitField>
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0040+40" size="4" name="SGPIO_MUX_CFG[10]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
+        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
+        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
+      </BitField>
+      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
+        <Enum name="SLICE_D" start="0x0" description="Slice D" />
+        <Enum name="SLICE_H" start="0x1" description="Slice H" />
+        <Enum name="SLICE_O" start="0x2" description="Slice O" />
+        <Enum name="SLICE_P" start="0x3" description="Slice P" />
+      </BitField>
+      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
+        <Enum name="ENABLE" start="0x0" description="Enable" />
+        <Enum name="DISABLE" start="0x1" description="Disable" />
+        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
+        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
+      </BitField>
+      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
+        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
+        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
+        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
+        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
+      </BitField>
+      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
+        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
+        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
+      </BitField>
+      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
+        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
+        <Enum name="2_SLICES" start="0x1" description="2 slices" />
+        <Enum name="4_SLICES" start="0x2" description="4 slices" />
+        <Enum name="8_SLICES" start="0x3" description="8 slices" />
+      </BitField>
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0040+44" size="4" name="SGPIO_MUX_CFG[11]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
+        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
+        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
+      </BitField>
+      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
+        <Enum name="SLICE_D" start="0x0" description="Slice D" />
+        <Enum name="SLICE_H" start="0x1" description="Slice H" />
+        <Enum name="SLICE_O" start="0x2" description="Slice O" />
+        <Enum name="SLICE_P" start="0x3" description="Slice P" />
+      </BitField>
+      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
+        <Enum name="ENABLE" start="0x0" description="Enable" />
+        <Enum name="DISABLE" start="0x1" description="Disable" />
+        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
+        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
+      </BitField>
+      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
+        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
+        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
+        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
+        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
+      </BitField>
+      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
+        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
+        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
+      </BitField>
+      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
+        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
+        <Enum name="2_SLICES" start="0x1" description="2 slices" />
+        <Enum name="4_SLICES" start="0x2" description="4 slices" />
+        <Enum name="8_SLICES" start="0x3" description="8 slices" />
+      </BitField>
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0040+48" size="4" name="SGPIO_MUX_CFG[12]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
+        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
+        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
+      </BitField>
+      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
+        <Enum name="SLICE_D" start="0x0" description="Slice D" />
+        <Enum name="SLICE_H" start="0x1" description="Slice H" />
+        <Enum name="SLICE_O" start="0x2" description="Slice O" />
+        <Enum name="SLICE_P" start="0x3" description="Slice P" />
+      </BitField>
+      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
+        <Enum name="ENABLE" start="0x0" description="Enable" />
+        <Enum name="DISABLE" start="0x1" description="Disable" />
+        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
+        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
+      </BitField>
+      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
+        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
+        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
+        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
+        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
+      </BitField>
+      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
+        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
+        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
+      </BitField>
+      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
+        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
+        <Enum name="2_SLICES" start="0x1" description="2 slices" />
+        <Enum name="4_SLICES" start="0x2" description="4 slices" />
+        <Enum name="8_SLICES" start="0x3" description="8 slices" />
+      </BitField>
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0040+52" size="4" name="SGPIO_MUX_CFG[13]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
+        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
+        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
+      </BitField>
+      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
+        <Enum name="SLICE_D" start="0x0" description="Slice D" />
+        <Enum name="SLICE_H" start="0x1" description="Slice H" />
+        <Enum name="SLICE_O" start="0x2" description="Slice O" />
+        <Enum name="SLICE_P" start="0x3" description="Slice P" />
+      </BitField>
+      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
+        <Enum name="ENABLE" start="0x0" description="Enable" />
+        <Enum name="DISABLE" start="0x1" description="Disable" />
+        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
+        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
+      </BitField>
+      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
+        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
+        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
+        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
+        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
+      </BitField>
+      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
+        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
+        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
+      </BitField>
+      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
+        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
+        <Enum name="2_SLICES" start="0x1" description="2 slices" />
+        <Enum name="4_SLICES" start="0x2" description="4 slices" />
+        <Enum name="8_SLICES" start="0x3" description="8 slices" />
+      </BitField>
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0040+56" size="4" name="SGPIO_MUX_CFG[14]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
+        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
+        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
+      </BitField>
+      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
+        <Enum name="SLICE_D" start="0x0" description="Slice D" />
+        <Enum name="SLICE_H" start="0x1" description="Slice H" />
+        <Enum name="SLICE_O" start="0x2" description="Slice O" />
+        <Enum name="SLICE_P" start="0x3" description="Slice P" />
+      </BitField>
+      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
+        <Enum name="ENABLE" start="0x0" description="Enable" />
+        <Enum name="DISABLE" start="0x1" description="Disable" />
+        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
+        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
+      </BitField>
+      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
+        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
+        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
+        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
+        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
+      </BitField>
+      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
+        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
+        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
+      </BitField>
+      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
+        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
+        <Enum name="2_SLICES" start="0x1" description="2 slices" />
+        <Enum name="4_SLICES" start="0x2" description="4 slices" />
+        <Enum name="8_SLICES" start="0x3" description="8 slices" />
+      </BitField>
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0040+60" size="4" name="SGPIO_MUX_CFG[15]" access="Read/Write" description="SGPIO multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="EXT_CLK_ENABLE" description="Select clock signal.">
+        <Enum name="INTERNAL_CLOCK_SIGNA" start="0x0" description="Internal clock signal (slice)" />
+        <Enum name="EXTERNAL_CLOCK_SIGNA" start="0x1" description="External clock signal (pin)" />
+      </BitField>
+      <BitField start="1" size="2" name="CLK_SOURCE_PIN_MODE" description="Select source clock pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="3" size="2" name="CLK_SOURCE_SLICE_MODE" description="Select clock source slice. Note that slices D, H, O and P do not support this mode.">
+        <Enum name="SLICE_D" start="0x0" description="Slice D" />
+        <Enum name="SLICE_H" start="0x1" description="Slice H" />
+        <Enum name="SLICE_O" start="0x2" description="Slice O" />
+        <Enum name="SLICE_P" start="0x3" description="Slice P" />
+      </BitField>
+      <BitField start="5" size="2" name="QUALIFIER_MODE" description="Select qualifier mode.">
+        <Enum name="ENABLE" start="0x0" description="Enable" />
+        <Enum name="DISABLE" start="0x1" description="Disable" />
+        <Enum name="SLICE_SEE_BITS_QUAL" start="0x2" description="Slice (see bits QUALIFIER_SLICE_MODE in this register)" />
+        <Enum name="EXTERNAL_SGPIO_PIN" start="0x3" description="External SGPIO pin (SGPIO8, SGPIO9, SGPIO10, or SGPIO11)" />
+      </BitField>
+      <BitField start="7" size="2" name="QUALIFIER_PIN_MODE" description="Select qualifier pin.">
+        <Enum name="SGPIO8" start="0x0" description="SGPIO8" />
+        <Enum name="SGPIO9" start="0x1" description="SGPIO9" />
+        <Enum name="SGPIO10" start="0x2" description="SGPIO10" />
+        <Enum name="SGPIO11" start="0x3" description="SGPIO11" />
+      </BitField>
+      <BitField start="9" size="2" name="QUALIFIER_SLICE_MODE" description="Select qualifier slice.">
+        <Enum name="SLICE_A" start="0x0" description="Slice A, but for slice A slice D is used." />
+        <Enum name="SLICE_H" start="0x1" description="Slice H, but for slice H slice O is used." />
+        <Enum name="SLICE_I" start="0x2" description="Slice I, but for slice I slice D is used." />
+        <Enum name="SLICE_P" start="0x3" description="Slice P, but for slice P slice O is used." />
+      </BitField>
+      <BitField start="11" size="1" name="CONCAT_ENABLE" description="Enable concatenation.">
+        <Enum name="EXTERNAL_DATA_PIN" start="0x0" description="External data pin" />
+        <Enum name="CONCATENATE_DATA" start="0x1" description="Concatenate data" />
+      </BitField>
+      <BitField start="12" size="2" name="CONCAT_ORDER" description="Select concatenation order">
+        <Enum name="SELF_LOOP" start="0x0" description="Self-loop" />
+        <Enum name="2_SLICES" start="0x1" description="2 slices" />
+        <Enum name="4_SLICES" start="0x2" description="4 slices" />
+        <Enum name="8_SLICES" start="0x3" description="8 slices" />
+      </BitField>
+      <BitField start="14" size="18" name="RESERVED" description="Reserved" />
+    </Register>
+    <Register start="+0x0080+0" size="4" name="SLICE_MUX_CFG[0]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
+        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
+        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
+      </BitField>
+      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
+        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
+        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
+      </BitField>
+      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
+        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
+        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
+      </BitField>
+      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
+        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
+        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
+      </BitField>
+      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
+        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
+        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
+        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
+        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
+      </BitField>
+      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
+        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
+        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
+        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
+        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
+      </BitField>
+      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
+        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
+        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0080+4" size="4" name="SLICE_MUX_CFG[1]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
+        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
+        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
+      </BitField>
+      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
+        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
+        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
+      </BitField>
+      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
+        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
+        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
+      </BitField>
+      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
+        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
+        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
+      </BitField>
+      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
+        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
+        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
+        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
+        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
+      </BitField>
+      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
+        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
+        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
+        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
+        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
+      </BitField>
+      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
+        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
+        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0080+8" size="4" name="SLICE_MUX_CFG[2]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
+        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
+        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
+      </BitField>
+      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
+        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
+        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
+      </BitField>
+      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
+        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
+        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
+      </BitField>
+      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
+        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
+        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
+      </BitField>
+      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
+        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
+        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
+        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
+        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
+      </BitField>
+      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
+        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
+        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
+        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
+        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
+      </BitField>
+      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
+        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
+        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0080+12" size="4" name="SLICE_MUX_CFG[3]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
+        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
+        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
+      </BitField>
+      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
+        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
+        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
+      </BitField>
+      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
+        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
+        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
+      </BitField>
+      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
+        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
+        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
+      </BitField>
+      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
+        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
+        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
+        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
+        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
+      </BitField>
+      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
+        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
+        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
+        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
+        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
+      </BitField>
+      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
+        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
+        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0080+16" size="4" name="SLICE_MUX_CFG[4]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
+        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
+        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
+      </BitField>
+      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
+        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
+        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
+      </BitField>
+      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
+        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
+        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
+      </BitField>
+      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
+        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
+        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
+      </BitField>
+      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
+        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
+        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
+        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
+        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
+      </BitField>
+      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
+        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
+        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
+        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
+        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
+      </BitField>
+      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
+        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
+        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0080+20" size="4" name="SLICE_MUX_CFG[5]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
+        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
+        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
+      </BitField>
+      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
+        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
+        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
+      </BitField>
+      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
+        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
+        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
+      </BitField>
+      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
+        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
+        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
+      </BitField>
+      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
+        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
+        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
+        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
+        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
+      </BitField>
+      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
+        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
+        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
+        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
+        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
+      </BitField>
+      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
+        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
+        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0080+24" size="4" name="SLICE_MUX_CFG[6]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
+        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
+        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
+      </BitField>
+      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
+        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
+        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
+      </BitField>
+      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
+        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
+        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
+      </BitField>
+      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
+        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
+        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
+      </BitField>
+      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
+        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
+        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
+        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
+        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
+      </BitField>
+      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
+        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
+        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
+        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
+        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
+      </BitField>
+      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
+        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
+        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0080+28" size="4" name="SLICE_MUX_CFG[7]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
+        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
+        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
+      </BitField>
+      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
+        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
+        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
+      </BitField>
+      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
+        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
+        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
+      </BitField>
+      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
+        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
+        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
+      </BitField>
+      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
+        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
+        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
+        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
+        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
+      </BitField>
+      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
+        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
+        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
+        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
+        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
+      </BitField>
+      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
+        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
+        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0080+32" size="4" name="SLICE_MUX_CFG[8]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
+        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
+        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
+      </BitField>
+      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
+        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
+        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
+      </BitField>
+      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
+        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
+        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
+      </BitField>
+      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
+        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
+        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
+      </BitField>
+      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
+        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
+        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
+        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
+        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
+      </BitField>
+      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
+        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
+        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
+        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
+        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
+      </BitField>
+      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
+        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
+        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0080+36" size="4" name="SLICE_MUX_CFG[9]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
+        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
+        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
+      </BitField>
+      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
+        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
+        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
+      </BitField>
+      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
+        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
+        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
+      </BitField>
+      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
+        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
+        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
+      </BitField>
+      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
+        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
+        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
+        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
+        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
+      </BitField>
+      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
+        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
+        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
+        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
+        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
+      </BitField>
+      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
+        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
+        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0080+40" size="4" name="SLICE_MUX_CFG[10]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
+        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
+        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
+      </BitField>
+      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
+        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
+        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
+      </BitField>
+      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
+        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
+        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
+      </BitField>
+      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
+        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
+        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
+      </BitField>
+      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
+        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
+        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
+        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
+        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
+      </BitField>
+      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
+        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
+        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
+        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
+        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
+      </BitField>
+      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
+        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
+        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0080+44" size="4" name="SLICE_MUX_CFG[11]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
+        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
+        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
+      </BitField>
+      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
+        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
+        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
+      </BitField>
+      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
+        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
+        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
+      </BitField>
+      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
+        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
+        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
+      </BitField>
+      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
+        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
+        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
+        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
+        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
+      </BitField>
+      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
+        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
+        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
+        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
+        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
+      </BitField>
+      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
+        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
+        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0080+48" size="4" name="SLICE_MUX_CFG[12]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
+        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
+        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
+      </BitField>
+      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
+        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
+        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
+      </BitField>
+      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
+        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
+        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
+      </BitField>
+      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
+        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
+        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
+      </BitField>
+      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
+        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
+        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
+        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
+        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
+      </BitField>
+      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
+        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
+        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
+        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
+        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
+      </BitField>
+      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
+        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
+        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0080+52" size="4" name="SLICE_MUX_CFG[13]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
+        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
+        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
+      </BitField>
+      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
+        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
+        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
+      </BitField>
+      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
+        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
+        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
+      </BitField>
+      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
+        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
+        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
+      </BitField>
+      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
+        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
+        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
+        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
+        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
+      </BitField>
+      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
+        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
+        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
+        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
+        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
+      </BitField>
+      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
+        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
+        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0080+56" size="4" name="SLICE_MUX_CFG[14]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
+        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
+        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
+      </BitField>
+      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
+        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
+        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
+      </BitField>
+      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
+        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
+        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
+      </BitField>
+      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
+        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
+        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
+      </BitField>
+      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
+        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
+        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
+        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
+        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
+      </BitField>
+      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
+        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
+        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
+        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
+        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
+      </BitField>
+      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
+        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
+        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0080+60" size="4" name="SLICE_MUX_CFG[15]" access="Read/Write" description="Slice multiplexer configuration registers." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="1" name="MATCH_MODE" description="Match mode. Selects whether the match filter is active or whether data is captured.">
+        <Enum name="DO_NOT_MATCH_DATA" start="0x0" description="Do not match data." />
+        <Enum name="MATCH_DATA" start="0x1" description="Match data." />
+      </BitField>
+      <BitField start="1" size="1" name="CLK_CAPTURE_MODE" description="Capture clock mode">
+        <Enum name="USE_RISING_CLOCK_EDG" start="0x0" description="Use rising clock edge." />
+        <Enum name="USE_FALLING_CLOCK_ED" start="0x1" description="Use falling clock edge." />
+      </BitField>
+      <BitField start="2" size="1" name="CLKGEN_MODE" description="Clock generation mode. Selects the clock generated by the slice counter or by an external pin or other slice as shift clock.">
+        <Enum name="USE_CLOCK_INTERNALLY" start="0x0" description="Use clock internally generated by COUNTER." />
+        <Enum name="USE_EXTERNAL_CLOCK_F" start="0x1" description="Use external clock from a pin or other slice." />
+      </BitField>
+      <BitField start="3" size="1" name="INV_OUT_CLK" description="Invert output clock">
+        <Enum name="NORMAL_CLOCK" start="0x0" description="Normal clock." />
+        <Enum name="INVERTED_CLOCK" start="0x1" description="Inverted clock." />
+      </BitField>
+      <BitField start="4" size="2" name="DATA_CAPTURE_MODE" description="Condition for input bit match interrupt">
+        <Enum name="DETECT_RISING_EDGE" start="0x0" description="Detect rising edge." />
+        <Enum name="DETECT_FALLING_EDGE" start="0x1" description="Detect falling edge." />
+        <Enum name="DETECT_LOW_LEVEL" start="0x2" description="Detect LOW level." />
+        <Enum name="DETECT_HIGH_LEVEL" start="0x3" description="Detect HIGH level." />
+      </BitField>
+      <BitField start="6" size="2" name="PARALLEL_MODE" description="Parallel mode">
+        <Enum name="SHIFT_1_BIT_PER_CLOC" start="0x0" description="Shift 1 bit per clock." />
+        <Enum name="SHIFT_2_BITS_PER_CLO" start="0x1" description="Shift 2 bits per clock." />
+        <Enum name="SHIFT_4_BITS_PER_CLO" start="0x2" description="Shift 4 bits per clock." />
+        <Enum name="SHIFT_1_BYTE_PER_CLO" start="0x3" description="Shift 1 byte per clock." />
+      </BitField>
+      <BitField start="8" size="1" name="INV_QUALIFIER" description="Inversion qualifier">
+        <Enum name="USE_NORMAL_QUALIFIER" start="0x0" description="Use normal qualifier." />
+        <Enum name="USE_INVERTED_QUALIFI" start="0x1" description="Use inverted qualifier." />
+      </BitField>
+      <BitField start="9" size="23" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x00C0+0" size="4" name="REG[0]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
+    </Register>
+    <Register start="+0x00C0+4" size="4" name="REG[1]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
+    </Register>
+    <Register start="+0x00C0+8" size="4" name="REG[2]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
+    </Register>
+    <Register start="+0x00C0+12" size="4" name="REG[3]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
+    </Register>
+    <Register start="+0x00C0+16" size="4" name="REG[4]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
+    </Register>
+    <Register start="+0x00C0+20" size="4" name="REG[5]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
+    </Register>
+    <Register start="+0x00C0+24" size="4" name="REG[6]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
+    </Register>
+    <Register start="+0x00C0+28" size="4" name="REG[7]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
+    </Register>
+    <Register start="+0x00C0+32" size="4" name="REG[8]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
+    </Register>
+    <Register start="+0x00C0+36" size="4" name="REG[9]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
+    </Register>
+    <Register start="+0x00C0+40" size="4" name="REG[10]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
+    </Register>
+    <Register start="+0x00C0+44" size="4" name="REG[11]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
+    </Register>
+    <Register start="+0x00C0+48" size="4" name="REG[12]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
+    </Register>
+    <Register start="+0x00C0+52" size="4" name="REG[13]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
+    </Register>
+    <Register start="+0x00C0+56" size="4" name="REG[14]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
+    </Register>
+    <Register start="+0x00C0+60" size="4" name="REG[15]" access="Read/Write" description="Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0)" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG" description="At each active shift clock the register shifts right;  loading REG(31) with data captured from DIN(n) and  DOUT(n) is set to REG(0)." />
+    </Register>
+    <Register start="+0x0100+0" size="4" name="REG_SS[0]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
+    </Register>
+    <Register start="+0x0100+4" size="4" name="REG_SS[1]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
+    </Register>
+    <Register start="+0x0100+8" size="4" name="REG_SS[2]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
+    </Register>
+    <Register start="+0x0100+12" size="4" name="REG_SS[3]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
+    </Register>
+    <Register start="+0x0100+16" size="4" name="REG_SS[4]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
+    </Register>
+    <Register start="+0x0100+20" size="4" name="REG_SS[5]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
+    </Register>
+    <Register start="+0x0100+24" size="4" name="REG_SS[6]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
+    </Register>
+    <Register start="+0x0100+28" size="4" name="REG_SS[7]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
+    </Register>
+    <Register start="+0x0100+32" size="4" name="REG_SS[8]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
+    </Register>
+    <Register start="+0x0100+36" size="4" name="REG_SS[9]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
+    </Register>
+    <Register start="+0x0100+40" size="4" name="REG_SS[10]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
+    </Register>
+    <Register start="+0x0100+44" size="4" name="REG_SS[11]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
+    </Register>
+    <Register start="+0x0100+48" size="4" name="REG_SS[12]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
+    </Register>
+    <Register start="+0x0100+52" size="4" name="REG_SS[13]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
+    </Register>
+    <Register start="+0x0100+56" size="4" name="REG_SS[14]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
+    </Register>
+    <Register start="+0x0100+60" size="4" name="REG_SS[15]" access="Read/Write" description="Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="REG_SS" description="Each time POS reaches 0x0 the contents of REG_SS  is exchanged with the content of REG." />
+    </Register>
+    <Register start="+0x0140+0" size="4" name="PRESET[0]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0140+4" size="4" name="PRESET[1]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0140+8" size="4" name="PRESET[2]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0140+12" size="4" name="PRESET[3]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0140+16" size="4" name="PRESET[4]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0140+20" size="4" name="PRESET[5]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0140+24" size="4" name="PRESET[6]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0140+28" size="4" name="PRESET[7]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0140+32" size="4" name="PRESET[8]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0140+36" size="4" name="PRESET[9]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0140+40" size="4" name="PRESET[10]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0140+44" size="4" name="PRESET[11]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0140+48" size="4" name="PRESET[12]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0140+52" size="4" name="PRESET[13]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0140+56" size="4" name="PRESET[14]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0140+60" size="4" name="PRESET[15]" access="Read/Write" description="Reload value of COUNT0, loaded when COUNT0 reaches 0x0" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="PRESET" description="Counter reload value; loaded when COUNT reaches  0x0." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0180+0" size="4" name="COUNT[0]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0180+4" size="4" name="COUNT[1]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0180+8" size="4" name="COUNT[2]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0180+12" size="4" name="COUNT[3]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0180+16" size="4" name="COUNT[4]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0180+20" size="4" name="COUNT[5]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0180+24" size="4" name="COUNT[6]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0180+28" size="4" name="COUNT[7]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0180+32" size="4" name="COUNT[8]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0180+36" size="4" name="COUNT[9]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0180+40" size="4" name="COUNT[10]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0180+44" size="4" name="COUNT[11]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0180+48" size="4" name="COUNT[12]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0180+52" size="4" name="COUNT[13]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0180+56" size="4" name="COUNT[14]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0180+60" size="4" name="COUNT[15]" access="Read/Write" description="Down counter, counts down each clock cycle." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="12" name="COUNT" description="Down counter, counts down each shift clock cycle.  Next count after 0x0 is PRESET." />
+      <BitField start="12" size="20" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C0+0" size="4" name="POS[0]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
+      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C0+4" size="4" name="POS[1]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
+      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C0+8" size="4" name="POS[2]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
+      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C0+12" size="4" name="POS[3]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
+      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C0+16" size="4" name="POS[4]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
+      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C0+20" size="4" name="POS[5]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
+      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C0+24" size="4" name="POS[6]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
+      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C0+28" size="4" name="POS[7]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
+      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C0+32" size="4" name="POS[8]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
+      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C0+36" size="4" name="POS[9]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
+      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C0+40" size="4" name="POS[10]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
+      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C0+44" size="4" name="POS[11]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
+      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C0+48" size="4" name="POS[12]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
+      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C0+52" size="4" name="POS[13]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
+      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C0+56" size="4" name="POS[14]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
+      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x01C0+60" size="4" name="POS[15]" access="Read/Write" description="Each time COUNT0 reaches 0x0 POS counts down." reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="8" name="POS" description="Each time COUNT reaches 0x0 POS counts down." />
+      <BitField start="8" size="8" name="POS_RESET" description="Reload value for POS after POS reaches 0x0." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0200" size="4" name="MASK_A" access="Read/Write" description="Mask for pattern match function of slice A" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MASK_A" description="Mask for pattern match function of slice A  0 = No effect. 1 = Mask this bit." />
+    </Register>
+    <Register start="+0x0204" size="4" name="MASK_H" access="Read/Write" description="Mask for pattern match function of slice H" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MASK_H" description="Mask for pattern match function of slice H  0 = No effect. 1 = Mask this bit." />
+    </Register>
+    <Register start="+0x0208" size="4" name="MASK_I" access="Read/Write" description="Mask for pattern match function of slice I" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MASK_I" description="Mask for pattern match function of slice I  0 = No effect . 1 = Mask this bit." />
+    </Register>
+    <Register start="+0x020C" size="4" name="MASK_P" access="Read/Write" description="Mask for pattern match function of slice P" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="32" name="MASK_P" description="Mask for pattern match function of slice P  0 = No effect. 1 = Mask this bit." />
+    </Register>
+    <Register start="+0x0210" size="4" name="GPIO_INREG" access="ReadOnly" description="GPIO input status register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="GPIO_INi" description="Bit i reflects the input state of SGPIO pin i . 0 = LOW 1 = HIGH" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0214" size="4" name="GPIO_OUTREG" access="Read/Write" description="GPIO output control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="GPIO_OUT" description="GPIO output register. Bit i sets the output of SGPIO pin i. 0 = LOW 1 = HIGH" />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0218" size="4" name="GPIO_OENREG" access="Read/Write" description="GPIO OE control register" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="GPIO_OE" description="Bit i selects the output enable state of SGPIO pin i. 0 = GPIO output i is tri-stated . 1 = GPIO output i is active." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x021C" size="4" name="CTRL_ENABLE" access="Read/Write" description="Enables the slice COUNT counter" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CTRL_EN" description="Slice count enable. Bit n controls slice n (0 = slice A, ..., 15 = slice P). 0 = Disables slice shift clock. 1 = Starts COUNTn or external shift clock." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0220" size="4" name="CTRL_DISABLE" access="Read/Write" description="Disables the slice POS counter" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CTRL_DIS" description="Slice count disable. Bit n controls slice n, (0 = slice A, ..., 15 = slice P). 0 = Enables COUNT and POS counters. The counters start counting when the CTRL_EN bit or bits are set in the CTRL_ENABLED register. 1 = Disables POS counter of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F00" size="4" name="CLR_EN_0" access="WriteOnly" description="Shift clock interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CLR_SCI" description="1 = Shift clock interrupt clear mask of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F04" size="4" name="SET_EN_0" access="WriteOnly" description="Shift clock interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SET_SCI" description="1 = Shift clock interrupt set mask of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F08" size="4" name="ENABLE_0" access="ReadOnly" description="Shift clock interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="ENABLE_SCI" description="1 = Shift clock interrupt enable of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F0C" size="4" name="STATUS_0" access="ReadOnly" description="Shift clock interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="STATUS_SCI" description="Shift clock interrupt status of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F10" size="4" name="CLR_STATUS_0" access="WriteOnly" description="Shift clock interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CLR_STATUS_SCI" description="Shift clock interrupt clear status of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F14" size="4" name="SET_STATUS_0" access="WriteOnly" description="Shift clock interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SET_STATUS_SCI" description="Shift clock interrupt set status of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F20" size="4" name="CLR_EN_1" access="WriteOnly" description="Exchange clock interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CLR_EN_CCI" description="1 = Exchange clock interrupt clear mask of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F24" size="4" name="SET_EN_1" access="WriteOnly" description="Exchange clock interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SET_EN_CCI" description="1 = Exchange clock interrupt set mask of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F28" size="4" name="ENABLE_1" access="ReadOnly" description="Exchange clock interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="ENABLE_CCI" description="Exchange clock interrupt enable of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F2C" size="4" name="STATUS_1" access="ReadOnly" description="Exchange clock interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="STATUS_CCI" description="Exchange clock interrupt status of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F30" size="4" name="CLR_STATUS_1" access="WriteOnly" description="Exchange clock interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CLR_STATUS_CCI" description="Exchange clock interrupt clear status of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F34" size="4" name="SET_STATUS_1" access="WriteOnly" description="Exchange clock interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SET_STATUS_CCI" description="Exchange clock interrupt set status of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F40" size="4" name="CLR_EN_2" access="WriteOnly" description="Pattern match interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CLR_EN2_PMI" description="1 = Match interrupt clear mask of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F44" size="4" name="SET_EN_2" access="WriteOnly" description="Pattern match interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SET_EN_PMI" description="1 = Match interrupt set mask of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F48" size="4" name="ENABLE_2" access="ReadOnly" description="Pattern match interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="ENABLE_PMI" description="Match interrupt enable of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F4C" size="4" name="STATUS_2" access="ReadOnly" description="Pattern match interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="STATUS_PMI" description="Match interrupt status of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F50" size="4" name="CLR_STATUS_2" access="WriteOnly" description="Pattern match interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CLR_STATUS_PMI" description="Match interrupt clear status of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F54" size="4" name="SET_STATUS_2" access="WriteOnly" description="Pattern match interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SET_STATUS_PMI" description="Match interrupt set status of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F60" size="4" name="CLR_EN_3" access="WriteOnly" description="Input interrupt clear mask" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CLR_EN_INPI" description="1 = Input interrupt clear mask of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F64" size="4" name="SET_EN_3" access="WriteOnly" description="Input bit match interrupt set mask" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SET_EN_INPI" description="1 = Input interrupt set mask of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F68" size="4" name="ENABLE_3" access="ReadOnly" description="Input bit match interrupt enable" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="ENABLE3_INPI" description="Input interrupt enable of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F6C" size="4" name="STATUS_3" access="ReadOnly" description="Input bit match interrupt status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="STATUS_INPI" description="Input interrupt status of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F70" size="4" name="CLR_STATUS_3" access="WriteOnly" description="Input bit match interrupt clear status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="CLR_STATUS_INPI" description="Input interrupt clear status of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+    <Register start="+0x0F74" size="4" name="SET_STATUS_3" access="WriteOnly" description="Input bit match interrupt set status" reset_value="0" reset_mask="0xFFFFFFFF">
+      <BitField start="0" size="16" name="SET_STATUS_INPI" description="Shift interrupt set status of slice n." />
+      <BitField start="16" size="16" name="RESERVED" description="Reserved." />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="NVIC" start="0xE000E100" description="Nested Vectored Interrupt Controller">
+    <Register name="NVIC_ISER0" description="Interrupt Set-Enable Register 0" start="0xE000E100">
+      <BitField name="DAC" start="0" size="1" />
+      <BitField name="DMA" start="2" size="1" />
+      <BitField name="FLASH" start="4" size="1" />
+      <BitField name="ETHERNET" start="5" size="1" />
+      <BitField name="SDIO" start="6" size="1" />
+      <BitField name="LCD" start="7" size="1" />
+      <BitField name="USB0" start="8" size="1" />
+      <BitField name="USB1" start="9" size="1" />
+      <BitField name="SCT" start="10" size="1" />
+      <BitField name="RITIMER" start="11" size="1" />
+      <BitField name="TIMER0" start="12" size="1" />
+      <BitField name="TIMER1" start="13" size="1" />
+      <BitField name="TIMER2" start="14" size="1" />
+      <BitField name="TIMER3" start="15" size="1" />
+      <BitField name="MCPWM" start="16" size="1" />
+      <BitField name="ADC0" start="17" size="1" />
+      <BitField name="I2C0" start="18" size="1" />
+      <BitField name="I2C1" start="19" size="1" />
+      <BitField name="SPI_INT" start="20" size="1" />
+      <BitField name="ADC1" start="21" size="1" />
+      <BitField name="SSP0" start="22" size="1" />
+      <BitField name="SSP1" start="23" size="1" />
+      <BitField name="USART0" start="24" size="1" />
+      <BitField name="UART1" start="25" size="1" />
+      <BitField name="USART2" start="26" size="1" />
+      <BitField name="USART3" start="27" size="1" />
+      <BitField name="I2S0" start="28" size="1" />
+      <BitField name="I2S1" start="29" size="1" />
+      <BitField name="SPIFI" start="30" size="1" />
+      <BitField name="SGPIO_IINT" start="31" size="1" />
+    </Register>
+    <Register name="NVIC_ISER1" description="Interrupt Set-Enable Register 1" start="0xE000E104">
+      <BitField name="PIN_INT0" start="0" size="1" />
+      <BitField name="PIN_INT1" start="1" size="1" />
+      <BitField name="PIN_INT2" start="2" size="1" />
+      <BitField name="PIN_INT3" start="3" size="1" />
+      <BitField name="PIN_INT4" start="4" size="1" />
+      <BitField name="PIN_INT5" start="5" size="1" />
+      <BitField name="PIN_INT6" start="6" size="1" />
+      <BitField name="PIN_INT7" start="7" size="1" />
+      <BitField name="GINT0" start="8" size="1" />
+      <BitField name="GINT1" start="9" size="1" />
+      <BitField name="EVENTROUTER" start="10" size="1" />
+      <BitField name="C_CAN1" start="11" size="1" />
+      <BitField name="ADCHS" start="13" size="1" />
+      <BitField name="ATIMER" start="14" size="1" />
+      <BitField name="RTC" start="15" size="1" />
+      <BitField name="WWDT" start="17" size="1" />
+      <BitField name="C_CAN0" start="19" size="1" />
+      <BitField name="QEI" start="20" size="1" />
+    </Register>
+    <Register name="NVIC_ICER0" description="Interrupt Clear-Enable Register 0" start="0xE000E180">
+      <BitField name="DAC" start="0" size="1" />
+      <BitField name="DMA" start="2" size="1" />
+      <BitField name="FLASH" start="4" size="1" />
+      <BitField name="ETHERNET" start="5" size="1" />
+      <BitField name="SDIO" start="6" size="1" />
+      <BitField name="LCD" start="7" size="1" />
+      <BitField name="USB0" start="8" size="1" />
+      <BitField name="USB1" start="9" size="1" />
+      <BitField name="SCT" start="10" size="1" />
+      <BitField name="RITIMER" start="11" size="1" />
+      <BitField name="TIMER0" start="12" size="1" />
+      <BitField name="TIMER1" start="13" size="1" />
+      <BitField name="TIMER2" start="14" size="1" />
+      <BitField name="TIMER3" start="15" size="1" />
+      <BitField name="MCPWM" start="16" size="1" />
+      <BitField name="ADC0" start="17" size="1" />
+      <BitField name="I2C0" start="18" size="1" />
+      <BitField name="I2C1" start="19" size="1" />
+      <BitField name="SPI_INT" start="20" size="1" />
+      <BitField name="ADC1" start="21" size="1" />
+      <BitField name="SSP0" start="22" size="1" />
+      <BitField name="SSP1" start="23" size="1" />
+      <BitField name="USART0" start="24" size="1" />
+      <BitField name="UART1" start="25" size="1" />
+      <BitField name="USART2" start="26" size="1" />
+      <BitField name="USART3" start="27" size="1" />
+      <BitField name="I2S0" start="28" size="1" />
+      <BitField name="I2S1" start="29" size="1" />
+      <BitField name="SPIFI" start="30" size="1" />
+      <BitField name="SGPIO_IINT" start="31" size="1" />
+    </Register>
+    <Register name="NVIC_ICER1" description="Interrupt Clear-Enable Register 1" start="0xE000E184">
+      <BitField name="PIN_INT0" start="0" size="1" />
+      <BitField name="PIN_INT1" start="1" size="1" />
+      <BitField name="PIN_INT2" start="2" size="1" />
+      <BitField name="PIN_INT3" start="3" size="1" />
+      <BitField name="PIN_INT4" start="4" size="1" />
+      <BitField name="PIN_INT5" start="5" size="1" />
+      <BitField name="PIN_INT6" start="6" size="1" />
+      <BitField name="PIN_INT7" start="7" size="1" />
+      <BitField name="GINT0" start="8" size="1" />
+      <BitField name="GINT1" start="9" size="1" />
+      <BitField name="EVENTROUTER" start="10" size="1" />
+      <BitField name="C_CAN1" start="11" size="1" />
+      <BitField name="ADCHS" start="13" size="1" />
+      <BitField name="ATIMER" start="14" size="1" />
+      <BitField name="RTC" start="15" size="1" />
+      <BitField name="WWDT" start="17" size="1" />
+      <BitField name="C_CAN0" start="19" size="1" />
+      <BitField name="QEI" start="20" size="1" />
+    </Register>
+    <Register name="NVIC_ISPR0" description="Interrupt Set-Pending Register 0" start="0xE000E200">
+      <BitField name="DAC" start="0" size="1" />
+      <BitField name="DMA" start="2" size="1" />
+      <BitField name="FLASH" start="4" size="1" />
+      <BitField name="ETHERNET" start="5" size="1" />
+      <BitField name="SDIO" start="6" size="1" />
+      <BitField name="LCD" start="7" size="1" />
+      <BitField name="USB0" start="8" size="1" />
+      <BitField name="USB1" start="9" size="1" />
+      <BitField name="SCT" start="10" size="1" />
+      <BitField name="RITIMER" start="11" size="1" />
+      <BitField name="TIMER0" start="12" size="1" />
+      <BitField name="TIMER1" start="13" size="1" />
+      <BitField name="TIMER2" start="14" size="1" />
+      <BitField name="TIMER3" start="15" size="1" />
+      <BitField name="MCPWM" start="16" size="1" />
+      <BitField name="ADC0" start="17" size="1" />
+      <BitField name="I2C0" start="18" size="1" />
+      <BitField name="I2C1" start="19" size="1" />
+      <BitField name="SPI_INT" start="20" size="1" />
+      <BitField name="ADC1" start="21" size="1" />
+      <BitField name="SSP0" start="22" size="1" />
+      <BitField name="SSP1" start="23" size="1" />
+      <BitField name="USART0" start="24" size="1" />
+      <BitField name="UART1" start="25" size="1" />
+      <BitField name="USART2" start="26" size="1" />
+      <BitField name="USART3" start="27" size="1" />
+      <BitField name="I2S0" start="28" size="1" />
+      <BitField name="I2S1" start="29" size="1" />
+      <BitField name="SPIFI" start="30" size="1" />
+      <BitField name="SGPIO_IINT" start="31" size="1" />
+    </Register>
+    <Register name="NVIC_ISPR1" description="Interrupt Set-Pending Register 1" start="0xE000E204">
+      <BitField name="PIN_INT0" start="0" size="1" />
+      <BitField name="PIN_INT1" start="1" size="1" />
+      <BitField name="PIN_INT2" start="2" size="1" />
+      <BitField name="PIN_INT3" start="3" size="1" />
+      <BitField name="PIN_INT4" start="4" size="1" />
+      <BitField name="PIN_INT5" start="5" size="1" />
+      <BitField name="PIN_INT6" start="6" size="1" />
+      <BitField name="PIN_INT7" start="7" size="1" />
+      <BitField name="GINT0" start="8" size="1" />
+      <BitField name="GINT1" start="9" size="1" />
+      <BitField name="EVENTROUTER" start="10" size="1" />
+      <BitField name="C_CAN1" start="11" size="1" />
+      <BitField name="ADCHS" start="13" size="1" />
+      <BitField name="ATIMER" start="14" size="1" />
+      <BitField name="RTC" start="15" size="1" />
+      <BitField name="WWDT" start="17" size="1" />
+      <BitField name="C_CAN0" start="19" size="1" />
+      <BitField name="QEI" start="20" size="1" />
+    </Register>
+    <Register name="NVIC_ICPR0" description="Interrupt Clear-Pending Register 0" start="0xE000E280">
+      <BitField name="DAC" start="0" size="1" />
+      <BitField name="DMA" start="2" size="1" />
+      <BitField name="FLASH" start="4" size="1" />
+      <BitField name="ETHERNET" start="5" size="1" />
+      <BitField name="SDIO" start="6" size="1" />
+      <BitField name="LCD" start="7" size="1" />
+      <BitField name="USB0" start="8" size="1" />
+      <BitField name="USB1" start="9" size="1" />
+      <BitField name="SCT" start="10" size="1" />
+      <BitField name="RITIMER" start="11" size="1" />
+      <BitField name="TIMER0" start="12" size="1" />
+      <BitField name="TIMER1" start="13" size="1" />
+      <BitField name="TIMER2" start="14" size="1" />
+      <BitField name="TIMER3" start="15" size="1" />
+      <BitField name="MCPWM" start="16" size="1" />
+      <BitField name="ADC0" start="17" size="1" />
+      <BitField name="I2C0" start="18" size="1" />
+      <BitField name="I2C1" start="19" size="1" />
+      <BitField name="SPI_INT" start="20" size="1" />
+      <BitField name="ADC1" start="21" size="1" />
+      <BitField name="SSP0" start="22" size="1" />
+      <BitField name="SSP1" start="23" size="1" />
+      <BitField name="USART0" start="24" size="1" />
+      <BitField name="UART1" start="25" size="1" />
+      <BitField name="USART2" start="26" size="1" />
+      <BitField name="USART3" start="27" size="1" />
+      <BitField name="I2S0" start="28" size="1" />
+      <BitField name="I2S1" start="29" size="1" />
+      <BitField name="SPIFI" start="30" size="1" />
+      <BitField name="SGPIO_IINT" start="31" size="1" />
+    </Register>
+    <Register name="NVIC_ICPR1" description="Interrupt Clear-Pending Register 1" start="0xE000E284">
+      <BitField name="PIN_INT0" start="0" size="1" />
+      <BitField name="PIN_INT1" start="1" size="1" />
+      <BitField name="PIN_INT2" start="2" size="1" />
+      <BitField name="PIN_INT3" start="3" size="1" />
+      <BitField name="PIN_INT4" start="4" size="1" />
+      <BitField name="PIN_INT5" start="5" size="1" />
+      <BitField name="PIN_INT6" start="6" size="1" />
+      <BitField name="PIN_INT7" start="7" size="1" />
+      <BitField name="GINT0" start="8" size="1" />
+      <BitField name="GINT1" start="9" size="1" />
+      <BitField name="EVENTROUTER" start="10" size="1" />
+      <BitField name="C_CAN1" start="11" size="1" />
+      <BitField name="ADCHS" start="13" size="1" />
+      <BitField name="ATIMER" start="14" size="1" />
+      <BitField name="RTC" start="15" size="1" />
+      <BitField name="WWDT" start="17" size="1" />
+      <BitField name="C_CAN0" start="19" size="1" />
+      <BitField name="QEI" start="20" size="1" />
+    </Register>
+    <Register name="NVIC_IABR0" description="Interrupt Active Bit Register 0" start="0xE000E300" access="ReadOnly">
+      <BitField name="DAC" start="0" size="1" />
+      <BitField name="DMA" start="2" size="1" />
+      <BitField name="FLASH" start="4" size="1" />
+      <BitField name="ETHERNET" start="5" size="1" />
+      <BitField name="SDIO" start="6" size="1" />
+      <BitField name="LCD" start="7" size="1" />
+      <BitField name="USB0" start="8" size="1" />
+      <BitField name="USB1" start="9" size="1" />
+      <BitField name="SCT" start="10" size="1" />
+      <BitField name="RITIMER" start="11" size="1" />
+      <BitField name="TIMER0" start="12" size="1" />
+      <BitField name="TIMER1" start="13" size="1" />
+      <BitField name="TIMER2" start="14" size="1" />
+      <BitField name="TIMER3" start="15" size="1" />
+      <BitField name="MCPWM" start="16" size="1" />
+      <BitField name="ADC0" start="17" size="1" />
+      <BitField name="I2C0" start="18" size="1" />
+      <BitField name="I2C1" start="19" size="1" />
+      <BitField name="SPI_INT" start="20" size="1" />
+      <BitField name="ADC1" start="21" size="1" />
+      <BitField name="SSP0" start="22" size="1" />
+      <BitField name="SSP1" start="23" size="1" />
+      <BitField name="USART0" start="24" size="1" />
+      <BitField name="UART1" start="25" size="1" />
+      <BitField name="USART2" start="26" size="1" />
+      <BitField name="USART3" start="27" size="1" />
+      <BitField name="I2S0" start="28" size="1" />
+      <BitField name="I2S1" start="29" size="1" />
+      <BitField name="SPIFI" start="30" size="1" />
+      <BitField name="SGPIO_IINT" start="31" size="1" />
+    </Register>
+    <Register name="NVIC_IABR1" description="Interrupt Active Bit Register 1" start="0xE000E304" access="ReadOnly">
+      <BitField name="PIN_INT0" start="0" size="1" />
+      <BitField name="PIN_INT1" start="1" size="1" />
+      <BitField name="PIN_INT2" start="2" size="1" />
+      <BitField name="PIN_INT3" start="3" size="1" />
+      <BitField name="PIN_INT4" start="4" size="1" />
+      <BitField name="PIN_INT5" start="5" size="1" />
+      <BitField name="PIN_INT6" start="6" size="1" />
+      <BitField name="PIN_INT7" start="7" size="1" />
+      <BitField name="GINT0" start="8" size="1" />
+      <BitField name="GINT1" start="9" size="1" />
+      <BitField name="EVENTROUTER" start="10" size="1" />
+      <BitField name="C_CAN1" start="11" size="1" />
+      <BitField name="ADCHS" start="13" size="1" />
+      <BitField name="ATIMER" start="14" size="1" />
+      <BitField name="RTC" start="15" size="1" />
+      <BitField name="WWDT" start="17" size="1" />
+      <BitField name="C_CAN0" start="19" size="1" />
+      <BitField name="QEI" start="20" size="1" />
+    </Register>
+    <Register name="NVIC_IPR0" description="Interrupt Priority Register 0" start="0xE000E400">
+      <BitField name="DAC" start="5" size="3" />
+      <BitField name="DMA" start="21" size="3" />
+    </Register>
+    <Register name="NVIC_IPR1" description="Interrupt Priority Register 1" start="0xE000E404">
+      <BitField name="FLASH" start="5" size="3" />
+      <BitField name="ETHERNET" start="13" size="3" />
+      <BitField name="SDIO" start="21" size="3" />
+      <BitField name="LCD" start="29" size="3" />
+    </Register>
+    <Register name="NVIC_IPR2" description="Interrupt Priority Register 2" start="0xE000E408">
+      <BitField name="USB0" start="5" size="3" />
+      <BitField name="USB1" start="13" size="3" />
+      <BitField name="SCT" start="21" size="3" />
+      <BitField name="RITIMER" start="29" size="3" />
+    </Register>
+    <Register name="NVIC_IPR3" description="Interrupt Priority Register 3" start="0xE000E40C">
+      <BitField name="TIMER0" start="5" size="3" />
+      <BitField name="TIMER1" start="13" size="3" />
+      <BitField name="TIMER2" start="21" size="3" />
+      <BitField name="TIMER3" start="29" size="3" />
+    </Register>
+    <Register name="NVIC_IPR4" description="Interrupt Priority Register 4" start="0xE000E410">
+      <BitField name="MCPWM" start="5" size="3" />
+      <BitField name="ADC0" start="13" size="3" />
+      <BitField name="I2C0" start="21" size="3" />
+      <BitField name="I2C1" start="29" size="3" />
+    </Register>
+    <Register name="NVIC_IPR5" description="Interrupt Priority Register 5" start="0xE000E414">
+      <BitField name="SPI_INT" start="5" size="3" />
+      <BitField name="ADC1" start="13" size="3" />
+      <BitField name="SSP0" start="21" size="3" />
+      <BitField name="SSP1" start="29" size="3" />
+    </Register>
+    <Register name="NVIC_IPR6" description="Interrupt Priority Register 6" start="0xE000E418">
+      <BitField name="USART0" start="5" size="3" />
+      <BitField name="UART1" start="13" size="3" />
+      <BitField name="USART2" start="21" size="3" />
+      <BitField name="USART3" start="29" size="3" />
+    </Register>
+    <Register name="NVIC_IPR7" description="Interrupt Priority Register 7" start="0xE000E41C">
+      <BitField name="I2S0" start="5" size="3" />
+      <BitField name="I2S1" start="13" size="3" />
+      <BitField name="SPIFI" start="21" size="3" />
+      <BitField name="SGPIO_IINT" start="29" size="3" />
+    </Register>
+    <Register name="NVIC_IPR8" description="Interrupt Priority Register 8" start="0xE000E420">
+      <BitField name="PIN_INT0" start="5" size="3" />
+      <BitField name="PIN_INT1" start="13" size="3" />
+      <BitField name="PIN_INT2" start="21" size="3" />
+      <BitField name="PIN_INT3" start="29" size="3" />
+    </Register>
+    <Register name="NVIC_IPR9" description="Interrupt Priority Register 9" start="0xE000E424">
+      <BitField name="PIN_INT4" start="5" size="3" />
+      <BitField name="PIN_INT5" start="13" size="3" />
+      <BitField name="PIN_INT6" start="21" size="3" />
+      <BitField name="PIN_INT7" start="29" size="3" />
+    </Register>
+    <Register name="NVIC_IPR10" description="Interrupt Priority Register 10" start="0xE000E428">
+      <BitField name="GINT0" start="5" size="3" />
+      <BitField name="GINT1" start="13" size="3" />
+      <BitField name="EVENTROUTER" start="21" size="3" />
+      <BitField name="C_CAN1" start="29" size="3" />
+    </Register>
+    <Register name="NVIC_IPR11" description="Interrupt Priority Register 11" start="0xE000E42C">
+      <BitField name="ADCHS" start="13" size="3" />
+      <BitField name="ATIMER" start="21" size="3" />
+      <BitField name="RTC" start="29" size="3" />
+    </Register>
+    <Register name="NVIC_IPR12" description="Interrupt Priority Register 12" start="0xE000E430">
+      <BitField name="WWDT" start="13" size="3" />
+      <BitField name="C_CAN0" start="29" size="3" />
+    </Register>
+    <Register name="NVIC_IPR13" description="Interrupt Priority Register 13" start="0xE000E434">
+      <BitField name="QEI" start="5" size="3" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
+    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
+      <BitField name="COUNTFLAG" start="16" size="1" description="Counter Flag" />
+      <BitField name="CLKSOURCE" start="2" size="1" description="Timer Clock Source" />
+      <BitField name="TICKINT" start="1" size="1" description="Tick Interrupt Enable" />
+      <BitField name="ENABLE" start="0" size="1" description="Enable SysTick Timer" />
+    </Register>
+    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
+      <BitField name="RELOAD" start="0" size="24" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
+    </Register>
+    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
+      <BitField name="CURRENT" start="0" size="24" description="The current value of the SysTick counter" />
+    </Register>
+    <Register name="SYST_CALIB" start="0xE000E01C" access="ReadOnly" description="SysTick Calibration Value Register">
+      <BitField name="NOREF" start="31" size="1" description="Indicates whether the device provides a reference clock to the processor" />
+      <BitField name="SKEW" start="30" size="1" description="Indicates whether the TENMS value is exact" />
+      <BitField name="TENMS" start="0" size="24" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SCB" start="" description="System Control Block">
+    <Register name="ACTLR" start="0xE000E008" description="Auxiliary Control Register">
+      <BitField name="DISOOFP" start="9" size="1" description="Disables floating pointinstructions completing outof order with respect to integer instructions" />
+      <BitField name="DISFPCA" start="8" size="1" description="When set to 1, disables IT folding" />
+      <BitField name="DISFOLD" start="2" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
+      <BitField name="DISDEFWBUF" start="1" size="1" description="When set to 1, disables write buffer use during default memory map accesses" />
+      <BitField name="DISMCYCINT" start="0" size="1" description="When set to 1, disables interruption of load multiple and store multiple instructions" />
+    </Register>
+    <Register name="CPUID" start="0xE000ED00" access="ReadOnly" description="CPUID Register">
+      <BitField name="IMPLEMENTER" start="24" size="8" description="Implementer Code" />
+      <BitField name="VARIANT" start="20" size="4" description="Variant Number" />
+      <BitField name="PARTNO" start="4" size="12" description="Part Number" />
+      <BitField name="REVISION" start="0" size="4" description="Revision Number" />
+    </Register>
+    <Register name="ICSR" start="0xE000ED04" description="Interrupt Control and State Register">
+      <BitField name="NMIPENDSET" start="31" size="1" description="NMI set-pending bit" />
+      <BitField name="PENDSVSET" start="28" size="1" description="PendSV set-pending bit" />
+      <BitField name="PENDSVCLR" start="27" size="1" description="PendSV clear-pending bit" />
+      <BitField name="PENDSTSET" start="26" size="1" description="SysTick exception set-pending bit" />
+      <BitField name="PENDSTCLR" start="25" size="1" description="SysTick exception clear-pending bit" />
+      <BitField name="ISRPREEMPT" start="23" size="1" description="" />
+      <BitField name="ISRPENDING" start="22" size="1" description="Interrupt pending flag" />
+      <BitField name="VECTPENDING" start="12" size="9" description="Indicates the exception number of the highest priority pending enabled exception" />
+      <BitField name="RETTOBASE" start="11" size="1" description="Indicates whether there are preempted active exceptions" />
+      <BitField name="VECTACTIVE" start="0" size="9" description="Contains the active exception number" />
+    </Register>
+    <Register name="VTOR" start="0xE000ED08" description="Vector Table Offset Register">
+      <BitField name="TBLOFF" start="7" size="25" description="Vector table base offset field" />
+    </Register>
+    <Register name="AIRCR" start="0xE000ED0C" description="Application Interrupt and Reset Control Register">
+      <BitField name="VECTKEY" start="16" size="16" description="Register key" />
+      <BitField name="ENDIANESS" start="15" size="1" description="Data endianness bit" />
+      <BitField name="PRIGROUP" start="8" size="3" description="Interrupt priority grouping field" />
+      <BitField name="SYSRESETREQ" start="2" size="1" description="System reset request bit" />
+      <BitField name="VECTCLRACTIVE" start="1" size="1" description="" />
+      <BitField name="VECTRESET" start="0" size="1" description="" />
+    </Register>
+    <Register name="SCR" start="0xE000ED10" description="System Control Register">
+      <BitField name="SEVONPEND" start="4" size="1" description="Send event on pending bit" />
+      <BitField name="SLEEPDEEP" start="2" size="1" description="Controls whether the processor uses sleep or deep sleep as its low power mode" />
+      <BitField name="SLEEPONEXIT" start="1" size="1" description="Indicates sleep-on-exit when returning from Handler mode to Thread mode" />
+    </Register>
+    <Register name="CCR" start="0xE000ED14" access="ReadOnly" description="Configuration and Control Register">
+      <BitField name="STKALIGN" start="9" size="1" description="Indicates stack alignment on exception entry" />
+      <BitField name="BFHFNMIGN" start="8" size="1" description="Enables handlers with priority -1 or-2 to ignore data BusFaults caused by load and store instructions" />
+      <BitField name="DIV_0_TRP" start="4" size="1" description="Enables faulting or halting when the processor executes an SDIVor UDIV instruction with a divisor of 0" />
+      <BitField name="UNALIGN_TRP" start="3" size="1" description="Enables unaligned access traps" />
+      <BitField name="USERSETMPEND" start="1" size="1" description="Enables unprivileged software access to the STIR" />
+      <BitField name="NONBASETHRDENA" start="0" size="1" description="Indicates how the processor enters Thread mode" />
+    </Register>
+    <Register name="SHPR1" start="0xE000ED18" description="System Handler Priority Register 1">
+      <BitField name="PRI_6" start="21" size="3" description="Priority of system handler 6 (UsageFault)" />
+      <BitField name="PRI_5" start="13" size="3" description="Priority of system handler 5 (BusFault)" />
+      <BitField name="PRI_4" start="5" size="3" description="Priority of system handler 4 (MemManage)" />
+    </Register>
+    <Register name="SHPR2" start="0xE000ED1C" description="System Handler Priority Register 2">
+      <BitField name="PRI_11" start="29" size="3" description="Priority of system handler 11 (SVCall)" />
+    </Register>
+    <Register name="SHPR3" start="0xE000ED20" description="System Handler Priority Register 3">
+      <BitField name="PRI_15" start="29" size="3" description="Priority of system handler 15 (SysTick)" />
+      <BitField name="PRI_14" start="21" size="3" description="Priority of system handler 14 (PendSV)" />
+    </Register>
+    <Register name="SHCSR" start="0xE000ED24" description="System Handler Control and State Register">
+      <BitField name="USGFAULTENA" start="18" size="1" description="UsageFault enable Bit" />
+      <BitField name="BUSFAULTENA" start="17" size="1" description="BusFault Enable Bit" />
+      <BitField name="MEMFAULTENA" start="16" size="1" description="MemManage Enable Bit" />
+      <BitField name="SVCALLPENDED" start="15" size="1" description="SVCall Pending Bit" />
+      <BitField name="BUSFAULTPENDED" start="14" size="1" description="BusFault Exception Pending Bit" />
+      <BitField name="MEMFAULTPENDED" start="13" size="1" description="MemManage Exception Pending Bit" />
+      <BitField name="USGFAULTPENDED" start="12" size="1" description="UsageFault Exception Pending Bit" />
+      <BitField name="SYSTICKACT" start="11" size="1" description="SysTick Exception Active Bit" />
+      <BitField name="PENDSVACT" start="10" size="1" description="PendSV Exception Active Bit" />
+      <BitField name="MONITORACT" start="8" size="1" description="Debug Monitor Active Bit" />
+      <BitField name="SVCALLACT" start="7" size="1" description="SVCall Active Bit" />
+      <BitField name="USGFAULTACT" start="3" size="1" description="UsageFault Exception Active Bit" />
+      <BitField name="BUSFAULTACT" start="1" size="1" description="BusFault Exception Active Bit" />
+      <BitField name="MEMFAULTACT" start="0" size="1" description="MemManage Exception Active Bit" />
+    </Register>
+    <Register name="MMSR" start="0xE000ED28" size="1" description="MemManage Fault Status Register">
+      <BitField name="MMARVALID" start="7" size="1" description="MemManage Fault Address Register(MMFAR) valid flag" />
+      <BitField name="MLSPERR" start="5" size="1" description="Indicates a MemManage fault occurred during floating-point lazy state preservation" />
+      <BitField name="MSTKERR" start="4" size="1" description="MemManage fault on stacking for exception entry" />
+      <BitField name="MUNSTKERR" start="3" size="1" description="MemManage fault on unstacking for a return from exception" />
+      <BitField name="DACCVIOL" start="1" size="1" description="Data access violation flag" />
+      <BitField name="IACCVIOL" start="0" size="1" description="Instruction access violation flag" />
+    </Register>
+    <Register name="BFSR" start="0xE000ED29" size="1" description="BusFault Status Register">
+      <BitField name="BFARVALID" start="7" size="1" description="BusFault Address Register(BFAR) valid flag" />
+      <BitField name="LSPERR" start="5" size="1" description="Indicates a bus fault occurred during floating-point lazy state preservation" />
+      <BitField name="STKERR" start="4" size="1" description="BusFault on stacking for exception entry" />
+      <BitField name="UNSTKERR" start="3" size="1" description="BusFault on unstacking for a return from exception" />
+      <BitField name="IMPRECISERR" start="2" size="1" description="Imprecise data bus error" />
+      <BitField name="PRECISERR" start="1" size="1" description="Precise data bus error" />
+      <BitField name="IBUSERR" start="0" size="1" description="Instruction bus error" />
+    </Register>
+    <Register name="UFSR" start="0xE000ED2A" size="2" description="UsageFault Status Register">
+      <BitField name="DIVBYZERO" start="9" size="1" description="Divide by zero UsageFault" />
+      <BitField name="UNALIGNED" start="8" size="1" description="Unaligned access UsageFault" />
+      <BitField name="NOCP" start="3" size="1" description="No coprocessor UsageFault" />
+      <BitField name="INVPC" start="2" size="1" description="Invalid PC load UsageFault, causedby an invalid PC load by EXC_RETURN" />
+      <BitField name="INVSTATE" start="1" size="1" description="Invalid state UsageFault" />
+      <BitField name="UNDEFINSTR" start="0" size="1" description="Undefined instruction UsageFault" />
+    </Register>
+    <Register name="HFSR" start="0xE000ED2C" description="HardFault Status Register">
+      <BitField name="DEBUGEVT" start="31" size="1" description="" />
+      <BitField name="FORCED" start="30" size="1" description="Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled" />
+      <BitField name="VECTTBL" start="1" size="1" description="Indicates a BusFault on a vectortable read during exception processing" />
+    </Register>
+    <Register name="DFSR" start="0xE000ED30" description="Debug Fault Status Register">
+      <BitField name="EXTERNAL" start="4" size="1" description="" />
+      <BitField name="VCATCH" start="3" size="1" description="" />
+      <BitField name="DWTTRAP" start="2" size="1" description="" />
+      <BitField name="BKPT" start="1" size="1" description="" />
+      <BitField name="HALTED" start="0" size="1" description="" />
+    </Register>
+    <Register name="MMAR" start="0xE000ED34" description="MemManage Fault Address Register">
+      <BitField name="ADDRESS" start="0" size="32" description="When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the MemManage fault" />
+    </Register>
+    <Register name="BFAR" start="0xE000ED38" description="BusFault Address Register">
+      <BitField name="ADDRESS" start="0" size="32" description="When the BFARVALID bit of the BFSR is set to1, this field holds the address of the location that generated the BusFault" />
+    </Register>
+    <Register name="AFSR" start="0xE000ED3C" description="Auxiliary Fault Status Register">
+      <BitField name="IMPDEF" start="0" size="32" description="Implementation defined, the bits map to the AUXFAULT input signals" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="FPU" description="Floating Point Unit">
+    <Register name="CPACR" start="0xE000ED88" description="Coprocessor Access Control Register">
+      <BitField name="CP11" start="22" size="2" description="Access privileges for coprocessor 11" />
+      <BitField name="CP10" start="20" size="2" description="Access privileges for coprocessor 10" />
+    </Register>
+    <Register name="FPCCR" start="0xE000EF34" description="Floating-point Context Control Register">
+      <BitField name="ASPEN" start="31" size="1" description="Automatic State Preservation" />
+      <BitField name="LSPEN" start="30" size="1" description="Lazy State Preservation Enabled" />
+      <BitField name="MONRDY" start="8" size="1" description="Monitor Ready" />
+      <BitField name="BFRDY" start="6" size="1" description="BusFault Ready" />
+      <BitField name="MMRDY" start="5" size="1" description="MemManage Ready" />
+      <BitField name="HFRDY" start="4" size="1" description="HardFault Ready" />
+      <BitField name="THREAD" start="3" size="1" description="Thread Mode Allocated Stack Frame" />
+      <BitField name="USER" start="1" size="1" description="User Allocated Stack Frame" />
+      <BitField name="LSPACT" start="0" size="1" description="Lazy State Preservation Active" />
+    </Register>
+    <Register name="FPCAR" start="0xE000EF38" description="Floating-point Context Address Register">
+      <BitField name="ADDRESSS" start="3" size="29" description="The location of the unpopulated floating-point register space allocated on an exception stack frame" />
+    </Register>
+    <Register name="FPDSCR" start="0xE000EF3C" description="Floating-point Status Control Register">
+      <BitField name="N" start="31" size="1" description="Negative condition code flag" />
+      <BitField name="Z" start="30" size="1" description="Zero condition code flag" />
+      <BitField name="C" start="29" size="1" description="Carry condition code flag" />
+      <BitField name="V" start="28" size="1" description="Overflow condition code flag" />
+      <BitField name="AHP" start="26" size="1" description="Alternative half-precision control bit" />
+      <BitField name="DN" start="25" size="1" description="Default NaN mode control bit" />
+      <BitField name="FZ" start="24" size="1" description="Flush-to-zero mode control bit" />
+      <BitField name="RMode" start="22" size="2" description="Rounding Mode control field" />
+      <BitField name="IDC" start="7" size="1" description="Input Denormal cumulative exception bit" />
+      <BitField name="IXC" start="4" size="1" description="Inexact cumulative exception bit" />
+      <BitField name="UFC" start="3" size="1" description="Underflow cumulative exception bit" />
+      <BitField name="OFC" start="2" size="1" description="Overflow cumulative exception bit" />
+      <BitField name="DZC" start="1" size="1" description="Division by Zero cumulative exception bit" />
+      <BitField name="IOC" start="0" size="1" description="Invalid Operation cumulative exception bit" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MPU" start="0xE000ED90" description="Memory Protection Unit">
+    <Register name="MPU_TYPE" start="0xE000ED90" access="ReadOnly" description="MPU Type Register">
+      <BitField name="IREGION" start="16" size="8" description="Number of supported MPU instruction regions" />
+      <BitField name="DREGION" start="8" size="8" description="Number of supported MPU data regions" />
+      <BitField name="SEPARATE" start="0" size="1" description="Support for unified or separate instruction and date memory maps" />
+    </Register>
+    <Register name="MPU_CTRL" start="0xE000ED94" description="MPU Control Register">
+      <BitField name="PRIVDEFENA" start="2" size="1" description="Enables privileged software access to the default memory map" />
+      <BitField name="HFNMIENA" start="1" size="1" description="Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers" />
+      <BitField name="ENABLE" start="0" size="1" description="Enable MPU" />
+    </Register>
+    <Register name="MPU_RNR" start="0xE000ED98" description="MPU Region Number Register">
+      <BitField name="REGION" start="0" size="8" description="Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers" />
+    </Register>
+    <Register name="MPU_RBAR" start="0xE000ED9C" description="MPU Region Base Address Register">
+      <BitField name="ADDR" start="5" size="27" description="Region base address field" />
+      <BitField name="VALID" start="4" size="1" description="MPU Region Number valid bit" />
+      <BitField name="REGION" start="0" size="4" description="MPU region field" />
+    </Register>
+    <Register name="MPU_RASR" start="0xE000EDA0" description="MPU Region Attribute and Size Register">
+      <BitField name="XN" start="28" size="1" description="Instruction access disable bit" />
+      <BitField name="AP" start="24" size="3" description="Access permission field" />
+      <BitField name="TEX" start="19" size="3" description="Memory access attribute" />
+      <BitField name="S" start="18" size="1" description="Shareable bit" />
+      <BitField name="C" start="17" size="1" description="Memory access attribute" />
+      <BitField name="B" start="16" size="1" description="Memory access attribute" />
+      <BitField name="SRD" start="8" size="8" description="Subregion disable bits" />
+      <BitField name="SIZE" start="1" size="5" description="MPU protection region size" />
+      <BitField name="ENABLE" start="0" size="1" description="Region enable bit" />
+    </Register>
+  </RegisterGroup>
+</Processor>
-- 
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