From c566db87b32a412f2a2739c4706446e132c26369 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 10 Oct 2025 13:47:11 +0200 Subject: example/dfu: add MSOS 2.0 descriptor for auto driver loading Signed-off-by: HiFiPhile --- examples/device/dfu/src/usb_descriptors.c | 202 +++++++++++++++------- examples/device/dfu_runtime/src/usb_descriptors.c | 198 +++++++++++++++------ 2 files changed, 284 insertions(+), 116 deletions(-) (limited to 'examples') diff --git a/examples/device/dfu/src/usb_descriptors.c b/examples/device/dfu/src/usb_descriptors.c index fd469aaf2..c05bb37d7 100644 --- a/examples/device/dfu/src/usb_descriptors.c +++ b/examples/device/dfu/src/usb_descriptors.c @@ -24,8 +24,8 @@ */ #include "bsp/board_api.h" -#include "tusb.h" #include "class/dfu/dfu_device.h" +#include "tusb.h" /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug. * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC. @@ -33,48 +33,46 @@ * Auto ProductID layout's Bitmap: * [MSB] HID | MSC | CDC [LSB] */ -#define _PID_MAP(itf, n) ( (CFG_TUD_##itf) << (n) ) -#define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \ - _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) ) +#define _PID_MAP(itf, n) ((CFG_TUD_##itf) << (n)) +#define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \ + _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4)) //--------------------------------------------------------------------+ // Device Descriptors //--------------------------------------------------------------------+ tusb_desc_device_t const desc_device = -{ - .bLength = sizeof(tusb_desc_device_t), - .bDescriptorType = TUSB_DESC_DEVICE, - .bcdUSB = 0x0200, - - #if CFG_TUD_CDC - // Use Interface Association Descriptor (IAD) for CDC - // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1) - .bDeviceClass = TUSB_CLASS_MISC, - .bDeviceSubClass = MISC_SUBCLASS_COMMON, - .bDeviceProtocol = MISC_PROTOCOL_IAD, - #else - .bDeviceClass = 0x00, - .bDeviceSubClass = 0x00, - .bDeviceProtocol = 0x00, - #endif - - .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, - - .idVendor = 0xCafe, - .idProduct = USB_PID, - .bcdDevice = 0x0100, - - .iManufacturer = 0x01, - .iProduct = 0x02, - .iSerialNumber = 0x03, - - .bNumConfigurations = 0x01 -}; + { + .bLength = sizeof(tusb_desc_device_t), + .bDescriptorType = TUSB_DESC_DEVICE, + .bcdUSB = 0x0201, + +#if CFG_TUD_CDC + // Use Interface Association Descriptor (IAD) for CDC + // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1) + .bDeviceClass = TUSB_CLASS_MISC, + .bDeviceSubClass = MISC_SUBCLASS_COMMON, + .bDeviceProtocol = MISC_PROTOCOL_IAD, +#else + .bDeviceClass = 0x00, + .bDeviceSubClass = 0x00, + .bDeviceProtocol = 0x00, +#endif + + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + + .idVendor = 0xCafe, + .idProduct = USB_PID, + .bcdDevice = 0x0100, + + .iManufacturer = 0x01, + .iProduct = 0x02, + .iSerialNumber = 0x03, + + .bNumConfigurations = 0x01}; // Invoked when received GET DEVICE DESCRIPTOR // Application return pointer to descriptor -uint8_t const * tud_descriptor_device_cb(void) -{ +uint8_t const *tud_descriptor_device_cb(void) { return (uint8_t const *) &desc_device; } @@ -83,36 +81,122 @@ uint8_t const * tud_descriptor_device_cb(void) //--------------------------------------------------------------------+ // Number of Alternate Interface (each for 1 flash partition) -#define ALT_COUNT 2 +#define ALT_COUNT 2 -enum -{ +enum { ITF_NUM_DFU_MODE, ITF_NUM_TOTAL }; -#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_DFU_DESC_LEN(ALT_COUNT)) +#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_DFU_DESC_LEN(ALT_COUNT)) #define FUNC_ATTRS (DFU_ATTR_CAN_UPLOAD | DFU_ATTR_CAN_DOWNLOAD | DFU_ATTR_MANIFESTATION_TOLERANT) uint8_t const desc_configuration[] = -{ - // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), + { + // Config number, interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), - // Interface number, Alternate count, starting string index, attributes, detach timeout, transfer size - TUD_DFU_DESCRIPTOR(ITF_NUM_DFU_MODE, ALT_COUNT, 4, FUNC_ATTRS, 1000, CFG_TUD_DFU_XFER_BUFSIZE), + // Interface number, Alternate count, starting string index, attributes, detach timeout, transfer size + TUD_DFU_DESCRIPTOR(ITF_NUM_DFU_MODE, ALT_COUNT, 4, FUNC_ATTRS, 1000, CFG_TUD_DFU_XFER_BUFSIZE), }; // Invoked when received GET CONFIGURATION DESCRIPTOR // Application return pointer to descriptor // Descriptor contents must exist long enough for transfer to complete -uint8_t const * tud_descriptor_configuration_cb(uint8_t index) -{ - (void) index; // for multiple configurations +uint8_t const *tud_descriptor_configuration_cb(uint8_t index) { + (void) index;// for multiple configurations return desc_configuration; } +//--------------------------------------------------------------------+ +// BOS Descriptor +//--------------------------------------------------------------------+ + +/* Microsoft OS 2.0 registry property descriptor +Per MS requirements https://msdn.microsoft.com/en-us/library/windows/hardware/hh450799(v=vs.85).aspx +device should create DeviceInterfaceGUIDs. It can be done by driver and +in case of real PnP solution device should expose MS "Microsoft OS 2.0 +registry property descriptor". Such descriptor can insert any record +into Windows registry per device/configuration/interface. In our case it +will insert "DeviceInterfaceGUIDs" multistring property. +GUID is freshly generated and should be OK to use. +https://developers.google.com/web/fundamentals/native-hardware/build-for-webusb/ +(Section Microsoft OS compatibility descriptors) +*/ + +#define BOS_TOTAL_LEN (TUD_BOS_DESC_LEN + TUD_BOS_MICROSOFT_OS_DESC_LEN) + +#define MS_OS_20_DESC_LEN 0xA2 + +#define VENDOR_REQUEST_MICROSOFT 1 + +// BOS Descriptor is required for webUSB +uint8_t const desc_bos[] = + { + // total length, number of device caps + TUD_BOS_DESCRIPTOR(BOS_TOTAL_LEN, 1), + + // Microsoft OS 2.0 descriptor + TUD_BOS_MS_OS_20_DESCRIPTOR(MS_OS_20_DESC_LEN, 1)}; + +uint8_t const *tud_descriptor_bos_cb(void) { + return desc_bos; +} + +uint8_t const desc_ms_os_20[] = + { + // Set header: length, type, windows version, total length + U16_TO_U8S_LE(0x000A), U16_TO_U8S_LE(MS_OS_20_SET_HEADER_DESCRIPTOR), U32_TO_U8S_LE(0x06030000), U16_TO_U8S_LE(MS_OS_20_DESC_LEN), + + // MS OS 2.0 Compatible ID descriptor: length, type, compatible ID, sub compatible ID + U16_TO_U8S_LE(0x0014), U16_TO_U8S_LE(MS_OS_20_FEATURE_COMPATBLE_ID), 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,// sub-compatible + + // MS OS 2.0 Registry property descriptor: length, type + U16_TO_U8S_LE(MS_OS_20_DESC_LEN - 0x0A - 0x14), U16_TO_U8S_LE(MS_OS_20_FEATURE_REG_PROPERTY), + U16_TO_U8S_LE(0x0007), U16_TO_U8S_LE(0x002A),// wPropertyDataType, wPropertyNameLength and PropertyName "DeviceInterfaceGUIDs\0" in UTF-16 + 'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00, 't', 0x00, 'e', 0x00, + 'r', 0x00, 'f', 0x00, 'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00, 'U', 0x00, 'I', 0x00, 'D', 0x00, 's', 0x00, 0x00, 0x00, + U16_TO_U8S_LE(0x0050),// wPropertyDataLength + //bPropertyData: {3E7E0711-DF3B-4158-A32F-E5951B2AB9A1}. + '{', 0x00, '3', 0x00, 'E', 0x00, '7', 0x00, 'E', 0x00, '0', 0x00, '7', 0x00, '1', 0x00, '1', 0x00, '-', 0x00, + 'D', 0x00, 'F', 0x00, '3', 0x00, 'B', 0x00, '-', 0x00, '4', 0x00, '1', 0x00, '5', 0x00, '8', 0x00, '-', 0x00, + 'A', 0x00, '3', 0x00, '2', 0x00, 'F', 0x00, '-', 0x00, 'E', 0x00, '5', 0x00, '9', 0x00, '5', 0x00, '1', 0x00, + 'B', 0x00, '2', 0x00, 'A', 0x00, 'B', 0x00, '9', 0x00, 'A', 0x00, '1', 0x00, '}', 0x00, 0x00, 0x00, 0x00, 0x00}; + +TU_VERIFY_STATIC(sizeof(desc_ms_os_20) == MS_OS_20_DESC_LEN, "Incorrect size"); + +// Invoked when a control transfer occurred on an interface of this class +// Driver response accordingly to the request and the transfer stage (setup/data/ack) +// return false to stall control endpoint (e.g unsupported request) +bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request) { + // nothing to with DATA & ACK stage + if (stage != CONTROL_STAGE_SETUP) return true; + + switch (request->bmRequestType_bit.type) { + case TUSB_REQ_TYPE_VENDOR: + switch (request->bRequest) { + case VENDOR_REQUEST_MICROSOFT: + if (request->wIndex == 7) { + return tud_control_xfer(rhport, request, (void *) (uintptr_t) desc_ms_os_20, MS_OS_20_DESC_LEN); + } else { + return false; + } + + default: + break; + } + break; + + default: + break; + } + + // stall unknown request + return false; +} + //--------------------------------------------------------------------+ // String Descriptors //--------------------------------------------------------------------+ @@ -127,13 +211,13 @@ enum { // array of pointer to string descriptors char const *string_desc_arr[] = -{ - (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409) - "TinyUSB", // 1: Manufacturer - "TinyUSB Device", // 2: Product - NULL, // 3: Serials will use unique ID if possible - "FLASH", // 4: DFU Partition 1 - "EEPROM", // 5: DFU Partition 2 + { + (const char[]){0x09, 0x04},// 0: is supported language is English (0x0409) + "TinyUSB", // 1: Manufacturer + "TinyUSB Device", // 2: Product + NULL, // 3: Serials will use unique ID if possible + "FLASH", // 4: DFU Partition 1 + "EEPROM", // 5: DFU Partition 2 }; static uint16_t _desc_str[32 + 1]; @@ -144,7 +228,7 @@ uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { (void) langid; size_t chr_count; - switch ( index ) { + switch (index) { case STRID_LANGID: memcpy(&_desc_str[1], string_desc_arr[0], 2); chr_count = 1; @@ -158,17 +242,17 @@ uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors. // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors - if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL; + if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) return NULL; const char *str = string_desc_arr[index]; // Cap at max char chr_count = strlen(str); - size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type - if ( chr_count > max_count ) chr_count = max_count; + size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1;// -1 for string type + if (chr_count > max_count) chr_count = max_count; // Convert ASCII string into UTF-16 - for ( size_t i = 0; i < chr_count; i++ ) { + for (size_t i = 0; i < chr_count; i++) { _desc_str[1 + i] = str[i]; } break; diff --git a/examples/device/dfu_runtime/src/usb_descriptors.c b/examples/device/dfu_runtime/src/usb_descriptors.c index 7ac53d255..5742ed3ec 100644 --- a/examples/device/dfu_runtime/src/usb_descriptors.c +++ b/examples/device/dfu_runtime/src/usb_descriptors.c @@ -24,8 +24,8 @@ */ #include "bsp/board_api.h" -#include "tusb.h" #include "class/dfu/dfu_rt_device.h" +#include "tusb.h" /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug. * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC. @@ -33,48 +33,46 @@ * Auto ProductID layout's Bitmap: * [MSB] HID | MSC | CDC [LSB] */ -#define _PID_MAP(itf, n) ( (CFG_TUD_##itf) << (n) ) -#define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \ - _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) ) +#define _PID_MAP(itf, n) ((CFG_TUD_##itf) << (n)) +#define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \ + _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4)) //--------------------------------------------------------------------+ // Device Descriptors //--------------------------------------------------------------------+ tusb_desc_device_t const desc_device = -{ - .bLength = sizeof(tusb_desc_device_t), - .bDescriptorType = TUSB_DESC_DEVICE, - .bcdUSB = 0x0200, - - #if CFG_TUD_CDC - // Use Interface Association Descriptor (IAD) for CDC - // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1) - .bDeviceClass = TUSB_CLASS_MISC, - .bDeviceSubClass = MISC_SUBCLASS_COMMON, - .bDeviceProtocol = MISC_PROTOCOL_IAD, - #else - .bDeviceClass = 0x00, - .bDeviceSubClass = 0x00, - .bDeviceProtocol = 0x00, - #endif - - .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, - - .idVendor = 0xCafe, - .idProduct = USB_PID, - .bcdDevice = 0x0100, - - .iManufacturer = 0x01, - .iProduct = 0x02, - .iSerialNumber = 0x03, - - .bNumConfigurations = 0x01 -}; + { + .bLength = sizeof(tusb_desc_device_t), + .bDescriptorType = TUSB_DESC_DEVICE, + .bcdUSB = 0x0201, + +#if CFG_TUD_CDC + // Use Interface Association Descriptor (IAD) for CDC + // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1) + .bDeviceClass = TUSB_CLASS_MISC, + .bDeviceSubClass = MISC_SUBCLASS_COMMON, + .bDeviceProtocol = MISC_PROTOCOL_IAD, +#else + .bDeviceClass = 0x00, + .bDeviceSubClass = 0x00, + .bDeviceProtocol = 0x00, +#endif + + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + + .idVendor = 0xCafe, + .idProduct = USB_PID, + .bcdDevice = 0x0100, + + .iManufacturer = 0x01, + .iProduct = 0x02, + .iSerialNumber = 0x03, + + .bNumConfigurations = 0x01}; // Invoked when received GET DEVICE DESCRIPTOR // Application return pointer to descriptor -uint8_t const * tud_descriptor_device_cb(void) -{ +uint8_t const *tud_descriptor_device_cb(void) { return (uint8_t const *) &desc_device; } @@ -82,33 +80,119 @@ uint8_t const * tud_descriptor_device_cb(void) // Configuration Descriptor //--------------------------------------------------------------------+ -enum -{ +enum { ITF_NUM_DFU_RT, ITF_NUM_TOTAL }; -#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_DFU_RT_DESC_LEN) +#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_DFU_RT_DESC_LEN) uint8_t const desc_configuration[] = -{ - // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), + { + // Config number, interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), - // Interface number, string index, attributes, detach timeout, transfer size */ - TUD_DFU_RT_DESCRIPTOR(ITF_NUM_DFU_RT, 4, 0x0d, 1000, 4096), + // Interface number, string index, attributes, detach timeout, transfer size */ + TUD_DFU_RT_DESCRIPTOR(ITF_NUM_DFU_RT, 4, 0x0d, 1000, 4096), }; // Invoked when received GET CONFIGURATION DESCRIPTOR // Application return pointer to descriptor // Descriptor contents must exist long enough for transfer to complete -uint8_t const * tud_descriptor_configuration_cb(uint8_t index) -{ - (void) index; // for multiple configurations +uint8_t const *tud_descriptor_configuration_cb(uint8_t index) { + (void) index;// for multiple configurations return desc_configuration; } +//--------------------------------------------------------------------+ +// BOS Descriptor +//--------------------------------------------------------------------+ + +/* Microsoft OS 2.0 registry property descriptor +Per MS requirements https://msdn.microsoft.com/en-us/library/windows/hardware/hh450799(v=vs.85).aspx +device should create DeviceInterfaceGUIDs. It can be done by driver and +in case of real PnP solution device should expose MS "Microsoft OS 2.0 +registry property descriptor". Such descriptor can insert any record +into Windows registry per device/configuration/interface. In our case it +will insert "DeviceInterfaceGUIDs" multistring property. +GUID is freshly generated and should be OK to use. +https://developers.google.com/web/fundamentals/native-hardware/build-for-webusb/ +(Section Microsoft OS compatibility descriptors) +*/ + +#define BOS_TOTAL_LEN (TUD_BOS_DESC_LEN + TUD_BOS_MICROSOFT_OS_DESC_LEN) + +#define MS_OS_20_DESC_LEN 0xA2 + +#define VENDOR_REQUEST_MICROSOFT 1 + +// BOS Descriptor is required for webUSB +uint8_t const desc_bos[] = + { + // total length, number of device caps + TUD_BOS_DESCRIPTOR(BOS_TOTAL_LEN, 1), + + // Microsoft OS 2.0 descriptor + TUD_BOS_MS_OS_20_DESCRIPTOR(MS_OS_20_DESC_LEN, 1)}; + +uint8_t const *tud_descriptor_bos_cb(void) { + return desc_bos; +} + +uint8_t const desc_ms_os_20[] = + { + // Set header: length, type, windows version, total length + U16_TO_U8S_LE(0x000A), U16_TO_U8S_LE(MS_OS_20_SET_HEADER_DESCRIPTOR), U32_TO_U8S_LE(0x06030000), U16_TO_U8S_LE(MS_OS_20_DESC_LEN), + + // MS OS 2.0 Compatible ID descriptor: length, type, compatible ID, sub compatible ID + U16_TO_U8S_LE(0x0014), U16_TO_U8S_LE(MS_OS_20_FEATURE_COMPATBLE_ID), 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,// sub-compatible + + // MS OS 2.0 Registry property descriptor: length, type + U16_TO_U8S_LE(MS_OS_20_DESC_LEN - 0x0A - 0x14), U16_TO_U8S_LE(MS_OS_20_FEATURE_REG_PROPERTY), + U16_TO_U8S_LE(0x0007), U16_TO_U8S_LE(0x002A),// wPropertyDataType, wPropertyNameLength and PropertyName "DeviceInterfaceGUIDs\0" in UTF-16 + 'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00, 't', 0x00, 'e', 0x00, + 'r', 0x00, 'f', 0x00, 'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00, 'U', 0x00, 'I', 0x00, 'D', 0x00, 's', 0x00, 0x00, 0x00, + U16_TO_U8S_LE(0x0050),// wPropertyDataLength + //bPropertyData: {F7CC2C68-3B14-4D72-B876-1A981AD2C9E5}. + '{', 0x00, 'F', 0x00, '7', 0x00, 'C', 0x00, 'C', 0x00, '2', 0x00, 'C', 0x00, '6', 0x00, '8', 0x00, '-', 0x00, + '3', 0x00, 'B', 0x00, '1', 0x00, '4', 0x00, '-', 0x00, '4', 0x00, 'D', 0x00, '7', 0x00, '2', 0x00, '-', 0x00, + 'B', 0x00, '8', 0x00, '7', 0x00, '6', 0x00, '-', 0x00, '1', 0x00, 'A', 0x00, '9', 0x00, '8', 0x00, '1', 0x00, + 'A', 0x00, 'D', 0x00, '2', 0x00, 'C', 0x00, '9', 0x00, 'E', 0x00, '5', 0x00, '}', 0x00, 0x00, 0x00, 0x00, 0x00}; + +TU_VERIFY_STATIC(sizeof(desc_ms_os_20) == MS_OS_20_DESC_LEN, "Incorrect size"); + +// Invoked when a control transfer occurred on an interface of this class +// Driver response accordingly to the request and the transfer stage (setup/data/ack) +// return false to stall control endpoint (e.g unsupported request) +bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request) { + // nothing to with DATA & ACK stage + if (stage != CONTROL_STAGE_SETUP) return true; + + switch (request->bmRequestType_bit.type) { + case TUSB_REQ_TYPE_VENDOR: + switch (request->bRequest) { + case VENDOR_REQUEST_MICROSOFT: + if (request->wIndex == 7) { + return tud_control_xfer(rhport, request, (void *) (uintptr_t) desc_ms_os_20, MS_OS_20_DESC_LEN); + } else { + return false; + } + + default: + break; + } + break; + + default: + break; + } + + // stall unknown request + return false; +} + //--------------------------------------------------------------------+ // String Descriptors //--------------------------------------------------------------------+ @@ -123,12 +207,12 @@ enum { // array of pointer to string descriptors char const *string_desc_arr[] = -{ - (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409) - "TinyUSB", // 1: Manufacturer - "TinyUSB Device", // 2: Product - NULL, // 3: Serials will use unique ID if possible - "TinyUSB DFU runtime", // 4: DFU runtime + { + (const char[]){0x09, 0x04},// 0: is supported language is English (0x0409) + "TinyUSB", // 1: Manufacturer + "TinyUSB Device", // 2: Product + NULL, // 3: Serials will use unique ID if possible + "TinyUSB DFU runtime", // 4: DFU runtime }; static uint16_t _desc_str[32 + 1]; @@ -139,7 +223,7 @@ uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { (void) langid; size_t chr_count; - switch ( index ) { + switch (index) { case STRID_LANGID: memcpy(&_desc_str[1], string_desc_arr[0], 2); chr_count = 1; @@ -153,17 +237,17 @@ uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors. // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors - if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL; + if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) return NULL; const char *str = string_desc_arr[index]; // Cap at max char chr_count = strlen(str); - size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type - if ( chr_count > max_count ) chr_count = max_count; + size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1;// -1 for string type + if (chr_count > max_count) chr_count = max_count; // Convert ASCII string into UTF-16 - for ( size_t i = 0; i < chr_count; i++ ) { + for (size_t i = 0; i < chr_count; i++) { _desc_str[1 + i] = str[i]; } break; -- cgit v1.3.1 From b8cea4ad766ea40de88fdaa28c19e69f5bc25f9d Mon Sep 17 00:00:00 2001 From: Tobi Date: Thu, 30 Oct 2025 14:06:17 +0100 Subject: Added bufferless operation to the video capture example. Can be tested with e.g. nanoCH32V305 board with the following settings: - tusb_config.h - #define CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE 1024 - #define CFG_TUD_VIDEO_STREAMING_BULK 1 - #define CFG_EXAMPLE_VIDEO_DISABLE_MJPEG - #define CFG_EXAMPLE_VIDEO_BUFFERLESS and - usb_descriptor.h - #define FRAME_RATE 60 --- examples/device/video_capture/src/main.c | 69 +++++++++++++++++++------ examples/device/video_capture/src/tusb_config.h | 1 + 2 files changed, 55 insertions(+), 15 deletions(-) (limited to 'examples') diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index 29656e944..b01830dfe 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -56,6 +56,20 @@ void video_task(void* param); void freertos_init_task(void); #endif +#if !defined(CFG_EXAMPLE_VIDEO_READONLY) || defined(CFG_EXAMPLE_VIDEO_BUFFERLESS) +/* EBU color bars: https://stackoverflow.com/questions/6939422 */ +static uint8_t const bar_color[8][4] = { + /* Y, U, Y, V */ + { 235, 128, 235, 128}, /* 100% White */ + { 219, 16, 219, 138}, /* Yellow */ + { 188, 154, 188, 16}, /* Cyan */ + { 173, 42, 173, 26}, /* Green */ + { 78, 214, 78, 230}, /* Magenta */ + { 63, 102, 63, 240}, /* Red */ + { 32, 240, 32, 118}, /* Blue */ + { 16, 128, 16, 128}, /* Black */ +}; +#endif //--------------------------------------------------------------------+ // Main @@ -111,12 +125,43 @@ void tud_resume_cb(void) { blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED; } +#ifdef CFG_EXAMPLE_VIDEO_BUFFERLESS + +#ifndef CFG_EXAMPLE_VIDEO_DISABLE_MJPEG + #error Demo only supports YUV2 please define CFG_EXAMPLE_VIDEO_DISABLE_MJPEG +#endif + +void tud_video_prepare_payload_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void* payload_buf, size_t payload_size, size_t offset) +{ + static uint32_t frame_counter = 0; + (void)ctl_idx; + (void)stm_idx; + + /* Offset will be zero at the start of a new frame */ + if (!offset) frame_counter++; + + for (size_t buf_pos = 0; buf_pos < payload_size; buf_pos += 2) { + + /* Position within the current line (pixel relative) */ + int line_pos = ((offset + buf_pos)>>1) % FRAME_WIDTH; + + /* Choose color based on the position and change the table offset every 4 frames */ + const uint8_t* color = bar_color[(line_pos/(FRAME_WIDTH / 8) + (frame_counter>>2)) % 8]; + + /* Copy pixel data for odd or even pixels */ + memcpy(&((uint8_t*)payload_buf)[buf_pos], &color[(line_pos & 1) ? 2 : 0], 2); + } + +} +#endif + //--------------------------------------------------------------------+ // USB Video //--------------------------------------------------------------------+ static unsigned frame_num = 0; static unsigned tx_busy = 0; static unsigned interval_ms = 1000 / FRAME_RATE; +#ifndef CFG_EXAMPLE_VIDEO_BUFFERLESS #ifdef CFG_EXAMPLE_VIDEO_READONLY // For mcus that does not have enough SRAM for frame buffer, we use fixed frame data. @@ -145,18 +190,6 @@ static struct { static uint8_t frame_buffer[FRAME_WIDTH * FRAME_HEIGHT * 16 / 8]; static void fill_color_bar(uint8_t* buffer, unsigned start_position) { - /* EBU color bars: https://stackoverflow.com/questions/6939422 */ - static uint8_t const bar_color[8][4] = { - /* Y, U, Y, V */ - { 235, 128, 235, 128}, /* 100% White */ - { 219, 16, 219, 138}, /* Yellow */ - { 188, 154, 188, 16}, /* Cyan */ - { 173, 42, 173, 26}, /* Green */ - { 78, 214, 78, 230}, /* Magenta */ - { 63, 102, 63, 240}, /* Red */ - { 32, 240, 32, 118}, /* Blue */ - { 16, 128, 16, 128}, /* Black */ - }; uint8_t* p; /* Generate the 1st line */ @@ -183,6 +216,8 @@ static void fill_color_bar(uint8_t* buffer, unsigned start_position) { #endif +#endif /* NDEF CFG_EXAMPLE_VIDEO_BUFFERLESS */ + static void video_send_frame(void) { static unsigned start_ms = 0; static unsigned already_sent = 0; @@ -197,7 +232,9 @@ static void video_send_frame(void) { already_sent = 1; tx_busy = 1; start_ms = board_millis(); -#ifdef CFG_EXAMPLE_VIDEO_READONLY +#if defined(CFG_EXAMPLE_VIDEO_BUFFERLESS) + tud_video_n_frame_xfer(0, 0, NULL, FRAME_WIDTH * FRAME_HEIGHT * 16 / 8); +#elif defined (CFG_EXAMPLE_VIDEO_READONLY) #if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG) tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4], FRAME_WIDTH * FRAME_HEIGHT * 16/8); @@ -216,13 +253,15 @@ static void video_send_frame(void) { start_ms += interval_ms; tx_busy = 1; -#ifdef CFG_EXAMPLE_VIDEO_READONLY +#if defined(CFG_EXAMPLE_VIDEO_BUFFERLESS) + tud_video_n_frame_xfer(0, 0, NULL, FRAME_WIDTH * FRAME_HEIGHT * 16 / 8); +#elif defined(CFG_EXAMPLE_VIDEO_READONLY) #if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG) tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4], FRAME_WIDTH * FRAME_HEIGHT * 16/8); #else tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)frames[frame_num % 8].buffer, frames[frame_num % 8].size); - #endif + #endif #else fill_color_bar(frame_buffer, frame_num); tud_video_n_frame_xfer(0, 0, (void*) frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16 / 8); diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h index 390152e16..1aa1a5ce7 100644 --- a/examples/device/video_capture/src/tusb_config.h +++ b/examples/device/video_capture/src/tusb_config.h @@ -110,6 +110,7 @@ //#define CFG_EXAMPLE_VIDEO_READONLY //#define CFG_EXAMPLE_VIDEO_DISABLE_MJPEG +//#define CFG_EXAMPLE_VIDEO_BUFFERLESS #ifdef __cplusplus } -- cgit v1.3.1 From 889cde7d4b31b30f34abc6e304445403bdf4ced4 Mon Sep 17 00:00:00 2001 From: Tobi Date: Thu, 30 Oct 2025 15:01:52 +0100 Subject: Video class: Changed pararameters of payload request to a dedicated structure in order to meet coding guideliness --- examples/device/video_capture/src/main.c | 10 +++++----- src/class/video/video_device.c | 13 ++++++++----- src/class/video/video_device.h | 12 +++++++++++- 3 files changed, 24 insertions(+), 11 deletions(-) (limited to 'examples') diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index b01830dfe..77ffd7bef 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -131,25 +131,25 @@ void tud_resume_cb(void) { #error Demo only supports YUV2 please define CFG_EXAMPLE_VIDEO_DISABLE_MJPEG #endif -void tud_video_prepare_payload_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void* payload_buf, size_t payload_size, size_t offset) +void tud_video_prepare_payload_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, tud_video_payload_request_t* request) { static uint32_t frame_counter = 0; (void)ctl_idx; (void)stm_idx; /* Offset will be zero at the start of a new frame */ - if (!offset) frame_counter++; + if (!request->offset) frame_counter++; - for (size_t buf_pos = 0; buf_pos < payload_size; buf_pos += 2) { + for (size_t buf_pos = 0; buf_pos < request->length; buf_pos += 2) { /* Position within the current line (pixel relative) */ - int line_pos = ((offset + buf_pos)>>1) % FRAME_WIDTH; + int line_pos = ((request->offset + buf_pos)>>1) % FRAME_WIDTH; /* Choose color based on the position and change the table offset every 4 frames */ const uint8_t* color = bar_color[(line_pos/(FRAME_WIDTH / 8) + (frame_counter>>2)) % 8]; /* Copy pixel data for odd or even pixels */ - memcpy(&((uint8_t*)payload_buf)[buf_pos], &color[(line_pos & 1) ? 2 : 0], 2); + memcpy(&((uint8_t*)request->buf)[buf_pos], &color[(line_pos & 1) ? 2 : 0], 2); } } diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 00f192af6..326f5c13d 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -214,12 +214,10 @@ TU_ATTR_WEAK int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, return VIDEO_ERROR_NONE; } -TU_ATTR_WEAK void tud_video_prepare_payload_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void* payload_buf, size_t payload_size, size_t offset) { +TU_ATTR_WEAK void tud_video_prepare_payload_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, tud_video_payload_request_t* request) { (void) ctl_idx; (void) stm_idx; - (void) payload_buf; - (void) payload_size; - (void) offset; + (void) request; } //--------------------------------------------------------------------+ @@ -871,7 +869,12 @@ static uint_fast16_t _prepare_in_payload(videod_streaming_interface_t *stm, uint if (stm->buffer) { memcpy(&ep_buf[hdr_len], stm->buffer + stm->offset, data_len); } else { - tud_video_prepare_payload_cb(stm->index_vc, stm->index_vs, &ep_buf[hdr_len], data_len, stm->offset); + tud_video_payload_request_t rqst = { + .buf = &ep_buf[hdr_len], + .length = data_len, + .offset = stm->offset + }; + tud_video_prepare_payload_cb(stm->index_vc, stm->index_vs, &rqst); } stm->offset += data_len; remaining -= data_len; diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h index b3094dd81..f14555e4f 100644 --- a/src/class/video/video_device.h +++ b/src/class/video/video_device.h @@ -35,6 +35,16 @@ extern "C" { #endif + +//--------------------------------------------------------------------+ +// Payload request +//--------------------------------------------------------------------+ +typedef struct TU_ATTR_PACKED { + void* buf; /* Payload buffer to be filled */ + size_t length; /* Length of the requested data in bytes */ + size_t offset; /* Offset within the frame (in bytes) */ +} tud_video_payload_request_t; + //--------------------------------------------------------------------+ // Application API (Multiple Ports) // CFG_TUD_VIDEO > 1 @@ -91,7 +101,7 @@ int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, * @param[in] payload_size Size of payload_buf (requested data size) * @param[in] offset Current byte offset relative to given bufsize from tud_video_n_frame_xfer (framesize) * @return video_error_code_t */ -void tud_video_prepare_payload_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void* payload_buf, size_t payload_size, size_t offset); +void tud_video_prepare_payload_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, tud_video_payload_request_t* request); //--------------------------------------------------------------------+ // INTERNAL USBD-CLASS DRIVER API -- cgit v1.3.1 From cee793796ca6feb2164201c6915592a04bf496d2 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 31 Oct 2025 10:49:33 +0100 Subject: Add boundary check Signed-off-by: HiFiPhile --- examples/device/dfu/src/main.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'examples') diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c index c0c848837..43e0af9a5 100644 --- a/examples/device/dfu/src/main.c +++ b/examples/device/dfu/src/main.c @@ -187,7 +187,9 @@ uint16_t tud_dfu_upload_cb(uint8_t alt, uint16_t block_num, uint8_t* data, uint1 (void) block_num; (void) length; - uint16_t const xfer_len = (uint16_t) strlen(upload_image[alt]); + TU_VERIFY(block_num == 0, 0); // for this example we only support single block upload + + uint16_t const xfer_len = tu_min16((uint16_t) strlen(upload_image[alt]), length); memcpy(data, upload_image[alt], xfer_len); return xfer_len; -- cgit v1.3.1 From 6b3970d5ff7547778ed5e1fc295dcfd1fbcad7e8 Mon Sep 17 00:00:00 2001 From: Tobi Date: Fri, 31 Oct 2025 17:29:58 +0100 Subject: Fixed trailing whitespaces in files (used wrong editor) --- examples/device/video_capture/src/main.c | 14 +++++++------- src/class/video/video_device.c | 6 +++--- 2 files changed, 10 insertions(+), 10 deletions(-) (limited to 'examples') diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index 77ffd7bef..ede8e3e4c 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -138,15 +138,15 @@ void tud_video_prepare_payload_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, tu (void)stm_idx; /* Offset will be zero at the start of a new frame */ - if (!request->offset) frame_counter++; + if (!request->offset) frame_counter++; for (size_t buf_pos = 0; buf_pos < request->length; buf_pos += 2) { /* Position within the current line (pixel relative) */ - int line_pos = ((request->offset + buf_pos)>>1) % FRAME_WIDTH; - + int line_pos = ((request->offset + buf_pos)>>1) % FRAME_WIDTH; + /* Choose color based on the position and change the table offset every 4 frames */ - const uint8_t* color = bar_color[(line_pos/(FRAME_WIDTH / 8) + (frame_counter>>2)) % 8]; + const uint8_t* color = bar_color[(line_pos/(FRAME_WIDTH / 8) + (frame_counter>>2)) % 8]; /* Copy pixel data for odd or even pixels */ memcpy(&((uint8_t*)request->buf)[buf_pos], &color[(line_pos & 1) ? 2 : 0], 2); @@ -233,7 +233,7 @@ static void video_send_frame(void) { tx_busy = 1; start_ms = board_millis(); #if defined(CFG_EXAMPLE_VIDEO_BUFFERLESS) - tud_video_n_frame_xfer(0, 0, NULL, FRAME_WIDTH * FRAME_HEIGHT * 16 / 8); + tud_video_n_frame_xfer(0, 0, NULL, FRAME_WIDTH * FRAME_HEIGHT * 16 / 8); #elif defined (CFG_EXAMPLE_VIDEO_READONLY) #if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG) tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4], @@ -254,14 +254,14 @@ static void video_send_frame(void) { tx_busy = 1; #if defined(CFG_EXAMPLE_VIDEO_BUFFERLESS) - tud_video_n_frame_xfer(0, 0, NULL, FRAME_WIDTH * FRAME_HEIGHT * 16 / 8); + tud_video_n_frame_xfer(0, 0, NULL, FRAME_WIDTH * FRAME_HEIGHT * 16 / 8); #elif defined(CFG_EXAMPLE_VIDEO_READONLY) #if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG) tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4], FRAME_WIDTH * FRAME_HEIGHT * 16/8); #else tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)frames[frame_num % 8].buffer, frames[frame_num % 8].size); - #endif + #endif #else fill_color_bar(frame_buffer, frame_num); tud_video_n_frame_xfer(0, 0, (void*) frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16 / 8); diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 326f5c13d..adf8ab821 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -870,9 +870,9 @@ static uint_fast16_t _prepare_in_payload(videod_streaming_interface_t *stm, uint memcpy(&ep_buf[hdr_len], stm->buffer + stm->offset, data_len); } else { tud_video_payload_request_t rqst = { - .buf = &ep_buf[hdr_len], - .length = data_len, - .offset = stm->offset + .buf = &ep_buf[hdr_len], + .length = data_len, + .offset = stm->offset }; tud_video_prepare_payload_cb(stm->index_vc, stm->index_vs, &rqst); } -- cgit v1.3.1 From f11adb02ebc0c594a7114b08585b8af18c3ee6d6 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 12 Nov 2025 21:22:25 +0700 Subject: migrate cdc device to use edpt stream API tu_edpt_stream_open() does not clear fifo, allow for persistent stream when disconnect/reconnect --- .clang-format | 7 +- .../net_lwip_webserver/src/usb_descriptors.c | 2 +- src/class/cdc/cdc_device.c | 393 +++++++++------------ src/class/midi/midi_device.c | 2 + src/class/vendor/vendor_device.c | 16 +- src/common/tusb_private.h | 7 +- src/tusb.c | 8 +- 7 files changed, 194 insertions(+), 241 deletions(-) (limited to 'examples') diff --git a/.clang-format b/.clang-format index c278fec37..40d40f7e9 100644 --- a/.clang-format +++ b/.clang-format @@ -1,7 +1,7 @@ --- Language: Cpp BasedOnStyle: LLVM -AlignAfterOpenBracket: AlwaysBreak +AlignAfterOpenBracket: Align AlignConsecutiveAssignments: Enabled: true AcrossEmptyLines: false @@ -38,6 +38,7 @@ AllowShortEnumsOnASingleLine: false AllowShortFunctionsOnASingleLine: None AllowShortIfStatementsOnASingleLine: Never AlwaysBreakTemplateDeclarations: Yes +BinPackArguments: true BreakBeforeBraces: Custom BraceWrapping: AfterCaseLabel: false @@ -57,8 +58,10 @@ BraceWrapping: SplitEmptyRecord: true SplitEmptyNamespace: true BracedInitializerIndentWidth: 2 +BreakBeforeBinaryOperators: None BreakConstructorInitializers: AfterColon BreakConstructorInitializersBeforeComma: false +ContinuationIndentWidth: 2 ColumnLimit: 120 ConstructorInitializerAllOnOneLineOrOnePerLine: false Cpp11BracedListStyle: true @@ -78,6 +81,8 @@ MacroBlockBegin: '' MacroBlockEnd: '' MaxEmptyLinesToKeep: 2 NamespaceIndentation: All +PenaltyBreakBeforeFirstCallParameter: 1000000 +PenaltyBreakOpenParenthesis: 1000000 QualifierAlignment: Custom QualifierOrder: ['static', 'const', 'volatile', 'restrict', 'type'] ReflowComments: false diff --git a/examples/device/net_lwip_webserver/src/usb_descriptors.c b/examples/device/net_lwip_webserver/src/usb_descriptors.c index b49962d65..c976cb62b 100644 --- a/examples/device/net_lwip_webserver/src/usb_descriptors.c +++ b/examples/device/net_lwip_webserver/src/usb_descriptors.c @@ -270,7 +270,7 @@ bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_contro switch (request->bmRequestType_bit.type) { case TUSB_REQ_TYPE_VENDOR: - switch (request->bRequest) { //-V2520 //-V2659 + switch (request->bRequest) { case 1: if (request->wIndex == 7) { // Get Microsoft OS 2.0 compatible descriptor diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index b3253b141..92139b14e 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -48,28 +48,23 @@ typedef struct { uint8_t rhport; uint8_t itf_num; - uint8_t ep_in; - uint8_t ep_out; - uint8_t ep_notify; uint8_t line_state; // Bit 0: DTR, Bit 1: RTS /*------------- From this point, data is not cleared by bus reset -------------*/ - char wanted_char; TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding; + char wanted_char; - // FIFO - tu_fifo_t rx_ff; - tu_fifo_t tx_ff; - - uint8_t rx_ff_buf[CFG_TUD_CDC_RX_BUFSIZE]; - uint8_t tx_ff_buf[CFG_TUD_CDC_TX_BUFSIZE]; + struct { + tu_edpt_stream_t tx; + tu_edpt_stream_t rx; - OSAL_MUTEX_DEF(rx_ff_mutex); - OSAL_MUTEX_DEF(tx_ff_mutex); + uint8_t tx_ff_buf[CFG_TUD_CDC_TX_BUFSIZE]; + uint8_t rx_ff_buf[CFG_TUD_CDC_RX_BUFSIZE]; + } stream; } cdcd_interface_t; -#define ITF_MEM_RESET_SIZE offsetof(cdcd_interface_t, wanted_char) +#define ITF_MEM_RESET_SIZE offsetof(cdcd_interface_t, line_coding) typedef struct { TUD_EPBUF_DEF(epout, CFG_TUD_CDC_EP_BUFSIZE); @@ -80,111 +75,102 @@ typedef struct { #endif } cdcd_epbuf_t; -//--------------------------------------------------------------------+ -// INTERNAL OBJECT & FUNCTION DECLARATION -//--------------------------------------------------------------------+ -static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC]; -CFG_TUD_MEM_SECTION static cdcd_epbuf_t _cdcd_epbuf[CFG_TUD_CDC]; - -static tud_cdc_configure_t _cdcd_cfg = TUD_CDC_CONFIGURE_DEFAULT(); - -static bool _prep_out_transaction(uint8_t itf) { - const uint8_t rhport = 0; - cdcd_interface_t* p_cdc = &_cdcd_itf[itf]; - cdcd_epbuf_t* p_epbuf = &_cdcd_epbuf[itf]; - - // Skip if usb is not ready yet - TU_VERIFY(tud_ready() && p_cdc->ep_out); - - uint16_t available = tu_fifo_remaining(&p_cdc->rx_ff); - - // Prepare for incoming data but only allow what we can store in the ring buffer. - // TODO Actually we can still carry out the transfer, keeping count of received bytes - // and slowly move it to the FIFO when read(). - // This pre-check reduces endpoint claiming - TU_VERIFY(available >= CFG_TUD_CDC_EP_BUFSIZE); - - // claim endpoint - TU_VERIFY(usbd_edpt_claim(p_cdc->rhport, p_cdc->ep_out)); - - // fifo can be changed before endpoint is claimed - available = tu_fifo_remaining(&p_cdc->rx_ff); - - if (available >= CFG_TUD_CDC_EP_BUFSIZE) { - return usbd_edpt_xfer(rhport, p_cdc->ep_out, p_epbuf->epout, CFG_TUD_CDC_EP_BUFSIZE); - } else { - // Release endpoint since we don't make any transfer - usbd_edpt_release(p_cdc->rhport, p_cdc->ep_out); - return false; - } -} - //--------------------------------------------------------------------+ // Weak stubs: invoked if no strong implementation is available //--------------------------------------------------------------------+ TU_ATTR_WEAK void tud_cdc_rx_cb(uint8_t itf) { - (void) itf; + (void)itf; } TU_ATTR_WEAK void tud_cdc_rx_wanted_cb(uint8_t itf, char wanted_char) { - (void) itf; - (void) wanted_char; + (void)itf; + (void)wanted_char; } TU_ATTR_WEAK void tud_cdc_tx_complete_cb(uint8_t itf) { - (void) itf; + (void)itf; } TU_ATTR_WEAK void tud_cdc_notify_complete_cb(uint8_t itf) { - (void) itf; + (void)itf; } TU_ATTR_WEAK void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) { - (void) itf; - (void) dtr; - (void) rts; + (void)itf; + (void)dtr; + (void)rts; } -TU_ATTR_WEAK void tud_cdc_line_coding_cb(uint8_t itf, cdc_line_coding_t const* p_line_coding) { - (void) itf; - (void) p_line_coding; +TU_ATTR_WEAK void tud_cdc_line_coding_cb(uint8_t itf, const cdc_line_coding_t *p_line_coding) { + (void)itf; + (void)p_line_coding; } TU_ATTR_WEAK void tud_cdc_send_break_cb(uint8_t itf, uint16_t duration_ms) { - (void) itf; - (void) duration_ms; + (void)itf; + (void)duration_ms; +} + +//--------------------------------------------------------------------+ +// INTERNAL OBJECT & FUNCTION DECLARATION +//--------------------------------------------------------------------+ +static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC]; +CFG_TUD_MEM_SECTION static cdcd_epbuf_t _cdcd_epbuf[CFG_TUD_CDC]; +static tud_cdc_configure_t _cdcd_cfg = TUD_CDC_CONFIGURE_DEFAULT(); + +TU_ATTR_ALWAYS_INLINE static inline uint8_t find_cdc_itf(uint8_t ep_addr) { + for (uint8_t idx = 0; idx < CFG_TUD_CDC; idx++) { + const cdcd_interface_t *p_cdc = &_cdcd_itf[idx]; + if (ep_addr == p_cdc->stream.rx.ep_addr || ep_addr == p_cdc->stream.tx.ep_addr || + (ep_addr == p_cdc->ep_notify && ep_addr != 0)) { + return idx; + } + } + return TUSB_INDEX_INVALID_8; } //--------------------------------------------------------------------+ // APPLICATION API //--------------------------------------------------------------------+ bool tud_cdc_configure(const tud_cdc_configure_t* driver_cfg) { - TU_VERIFY(driver_cfg); + TU_VERIFY(driver_cfg != NULL); _cdcd_cfg = *driver_cfg; return true; } bool tud_cdc_n_ready(uint8_t itf) { - return tud_ready() && _cdcd_itf[itf].ep_in != 0 && _cdcd_itf[itf].ep_out != 0; + TU_VERIFY(itf < CFG_TUD_CDC); + TU_VERIFY(tud_ready()); + cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; + + const bool in_opened = tu_edpt_stream_is_opened(&p_cdc->stream.tx); + const bool out_opened = tu_edpt_stream_is_opened(&p_cdc->stream.rx); + return in_opened && out_opened; } bool tud_cdc_n_connected(uint8_t itf) { + TU_VERIFY(itf < CFG_TUD_CDC); + TU_VERIFY(tud_ready()); + cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; // DTR (bit 0) active is considered as connected - return tud_ready() && tu_bit_test(_cdcd_itf[itf].line_state, 0); + return tu_bit_test(p_cdc->line_state, 0); } uint8_t tud_cdc_n_get_line_state(uint8_t itf) { + TU_VERIFY(itf < CFG_TUD_CDC, 0); return _cdcd_itf[itf].line_state; } -void tud_cdc_n_get_line_coding(uint8_t itf, cdc_line_coding_t* coding) { +void tud_cdc_n_get_line_coding(uint8_t itf, cdc_line_coding_t *coding) { + TU_VERIFY(itf < CFG_TUD_CDC, ); (*coding) = _cdcd_itf[itf].line_coding; } #if CFG_TUD_CDC_NOTIFY bool tud_cdc_n_notify_uart_state (uint8_t itf, const cdc_notify_uart_state_t *state) { - cdcd_interface_t* p_cdc = &_cdcd_itf[itf]; - cdcd_epbuf_t* p_epbuf = &_cdcd_epbuf[itf]; + TU_VERIFY(itf < CFG_TUD_CDC); + cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; + cdcd_epbuf_t *p_epbuf = &_cdcd_epbuf[itf]; TU_VERIFY(tud_ready() && p_cdc->ep_notify != 0); TU_VERIFY(usbd_edpt_claim(p_cdc->rhport, p_cdc->ep_notify)); @@ -200,8 +186,9 @@ bool tud_cdc_n_notify_uart_state (uint8_t itf, const cdc_notify_uart_state_t *st } bool tud_cdc_n_notify_conn_speed_change(uint8_t itf, const cdc_notify_conn_speed_change_t* conn_speed_change) { - cdcd_interface_t* p_cdc = &_cdcd_itf[itf]; - cdcd_epbuf_t* p_epbuf = &_cdcd_epbuf[itf]; + TU_VERIFY(itf < CFG_TUD_CDC); + cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; + cdcd_epbuf_t *p_epbuf = &_cdcd_epbuf[itf]; TU_VERIFY(tud_ready() && p_cdc->ep_notify != 0); TU_VERIFY(usbd_edpt_claim(p_cdc->rhport, p_cdc->ep_notify)); @@ -218,6 +205,7 @@ bool tud_cdc_n_notify_conn_speed_change(uint8_t itf, const cdc_notify_conn_speed #endif void tud_cdc_n_set_wanted_char(uint8_t itf, char wanted) { + TU_VERIFY(itf < CFG_TUD_CDC, ); _cdcd_itf[itf].wanted_char = wanted; } @@ -225,77 +213,55 @@ void tud_cdc_n_set_wanted_char(uint8_t itf, char wanted) { // READ API //--------------------------------------------------------------------+ uint32_t tud_cdc_n_available(uint8_t itf) { - return tu_fifo_count(&_cdcd_itf[itf].rx_ff); + TU_VERIFY(itf < CFG_TUD_CDC, 0); + cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; + return tu_edpt_stream_read_available(&p_cdc->stream.rx); } uint32_t tud_cdc_n_read(uint8_t itf, void* buffer, uint32_t bufsize) { - cdcd_interface_t* p_cdc = &_cdcd_itf[itf]; - uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX)); - _prep_out_transaction(itf); - return num_read; + TU_VERIFY(itf < CFG_TUD_CDC, 0); + cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; + return tu_edpt_stream_read(p_cdc->rhport, &p_cdc->stream.rx, buffer, bufsize); } -bool tud_cdc_n_peek(uint8_t itf, uint8_t* chr) { - return tu_fifo_peek(&_cdcd_itf[itf].rx_ff, chr); +bool tud_cdc_n_peek(uint8_t itf, uint8_t *chr) { + TU_VERIFY(itf < CFG_TUD_CDC); + cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; + return tu_edpt_stream_peek(&p_cdc->stream.rx, chr); } void tud_cdc_n_read_flush(uint8_t itf) { - cdcd_interface_t* p_cdc = &_cdcd_itf[itf]; - tu_fifo_clear(&p_cdc->rx_ff); - _prep_out_transaction(itf); + TU_VERIFY(itf < CFG_TUD_CDC, ); + cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; + tu_edpt_stream_clear(&p_cdc->stream.rx); + tu_edpt_stream_read_xfer(p_cdc->rhport, &p_cdc->stream.rx); } //--------------------------------------------------------------------+ // WRITE API //--------------------------------------------------------------------+ uint32_t tud_cdc_n_write(uint8_t itf, const void* buffer, uint32_t bufsize) { - cdcd_interface_t* p_cdc = &_cdcd_itf[itf]; - uint16_t wr_count = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX)); - - // flush if queue more than packet size - if (tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE - #if CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE - || tu_fifo_full(&p_cdc->tx_ff) // check full if fifo size is less than packet size - #endif - ) { - tud_cdc_n_write_flush(itf); - } - - return wr_count; + TU_VERIFY(itf < CFG_TUD_CDC, 0); + cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; + return tu_edpt_stream_write(p_cdc->rhport, &p_cdc->stream.tx, buffer, bufsize); } uint32_t tud_cdc_n_write_flush(uint8_t itf) { - cdcd_interface_t* p_cdc = &_cdcd_itf[itf]; - cdcd_epbuf_t* p_epbuf = &_cdcd_epbuf[itf]; - TU_VERIFY(tud_ready(), 0); // Skip if usb is not ready yet - - // No data to send - if (0 == tu_fifo_count(&p_cdc->tx_ff)) { - return 0; - } - - TU_VERIFY(usbd_edpt_claim(p_cdc->rhport, p_cdc->ep_in), 0); // Claim the endpoint - - // Pull data from FIFO - const uint16_t count = tu_fifo_read_n(&p_cdc->tx_ff, p_epbuf->epin, CFG_TUD_CDC_EP_BUFSIZE); - - if (count > 0) { - TU_ASSERT(usbd_edpt_xfer(p_cdc->rhport, p_cdc->ep_in, p_epbuf->epin, count), 0); - return count; - } else { - // Release endpoint since we don't make any transfer - // Note: data is dropped if terminal is not connected - usbd_edpt_release(p_cdc->rhport, p_cdc->ep_in); - return 0; - } + TU_VERIFY(itf < CFG_TUD_CDC, 0); + cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; + return tu_edpt_stream_write_xfer(p_cdc->rhport, &p_cdc->stream.tx); } uint32_t tud_cdc_n_write_available(uint8_t itf) { - return tu_fifo_remaining(&_cdcd_itf[itf].tx_ff); + TU_VERIFY(itf < CFG_TUD_CDC, 0); + cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; + return tu_edpt_stream_write_available(p_cdc->rhport, &p_cdc->stream.tx); } bool tud_cdc_n_write_clear(uint8_t itf) { - return tu_fifo_clear(&_cdcd_itf[itf].tx_ff); + TU_VERIFY(itf < CFG_TUD_CDC); + cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; + return tu_edpt_stream_clear(&p_cdc->stream.tx); } //--------------------------------------------------------------------+ @@ -304,7 +270,8 @@ bool tud_cdc_n_write_clear(uint8_t itf) { void cdcd_init(void) { tu_memclr(_cdcd_itf, sizeof(_cdcd_itf)); for (uint8_t i = 0; i < CFG_TUD_CDC; i++) { - cdcd_interface_t* p_cdc = &_cdcd_itf[i]; + cdcd_interface_t *p_cdc = &_cdcd_itf[i]; + cdcd_epbuf_t *p_epbuf = &_cdcd_epbuf[i]; p_cdc->wanted_char = (char) -1; @@ -314,44 +281,23 @@ void cdcd_init(void) { p_cdc->line_coding.parity = 0; p_cdc->line_coding.data_bits = 8; - // Config RX fifo - tu_fifo_config(&p_cdc->rx_ff, p_cdc->rx_ff_buf, TU_ARRAY_SIZE(p_cdc->rx_ff_buf), 1, false); + tu_edpt_stream_init(&p_cdc->stream.rx, false, false, false, p_cdc->stream.rx_ff_buf, CFG_TUD_CDC_RX_BUFSIZE, + p_epbuf->epout, CFG_TUD_CDC_EP_BUFSIZE); // TX fifo can be configured to change to overwritable if not connected (DTR bit not set). Without DTR we do not // know if data is actually polled by terminal. This way the most current data is prioritized. // Default: is overwritable - tu_fifo_config(&p_cdc->tx_ff, p_cdc->tx_ff_buf, TU_ARRAY_SIZE(p_cdc->tx_ff_buf), 1, _cdcd_cfg.tx_overwritabe_if_not_connected); - - #if OSAL_MUTEX_REQUIRED - osal_mutex_t mutex_rd = osal_mutex_create(&p_cdc->rx_ff_mutex); - osal_mutex_t mutex_wr = osal_mutex_create(&p_cdc->tx_ff_mutex); - TU_ASSERT(mutex_rd != NULL && mutex_wr != NULL, ); - - tu_fifo_config_mutex(&p_cdc->rx_ff, NULL, mutex_rd); - tu_fifo_config_mutex(&p_cdc->tx_ff, mutex_wr, NULL); - #endif + tu_edpt_stream_init(&p_cdc->stream.tx, false, true, _cdcd_cfg.tx_overwritabe_if_not_connected, + p_cdc->stream.tx_ff_buf, CFG_TUD_CDC_TX_BUFSIZE, p_epbuf->epin, CFG_TUD_CDC_EP_BUFSIZE); } } bool cdcd_deinit(void) { - #if OSAL_MUTEX_REQUIRED for(uint8_t i=0; irx_ff.mutex_rd; - const osal_mutex_t mutex_wr = p_cdc->tx_ff.mutex_wr; - - if (mutex_rd != NULL) { - osal_mutex_delete(mutex_rd); - tu_fifo_config_mutex(&p_cdc->rx_ff, NULL, NULL); - } - - if (mutex_wr != NULL) { - osal_mutex_delete(mutex_wr); - tu_fifo_config_mutex(&p_cdc->tx_ff, NULL, NULL); - } + tu_edpt_stream_deinit(&p_cdc->stream.rx); + tu_edpt_stream_deinit(&p_cdc->stream.tx); } - #endif - return true; } @@ -360,74 +306,85 @@ void cdcd_reset(uint8_t rhport) { for (uint8_t i = 0; i < CFG_TUD_CDC; i++) { cdcd_interface_t* p_cdc = &_cdcd_itf[i]; - tu_memclr(p_cdc, ITF_MEM_RESET_SIZE); - if (!_cdcd_cfg.rx_persistent) { - tu_fifo_clear(&p_cdc->rx_ff); - } - if (!_cdcd_cfg.tx_persistent) { - tu_fifo_clear(&p_cdc->tx_ff); - } - tu_fifo_set_overwritable(&p_cdc->tx_ff, _cdcd_cfg.tx_overwritabe_if_not_connected); + + tu_fifo_set_overwritable(&p_cdc->stream.tx.ff, _cdcd_cfg.tx_overwritabe_if_not_connected); // // back to default + tu_edpt_stream_close(&p_cdc->stream.rx); + tu_edpt_stream_close(&p_cdc->stream.tx); } } uint16_t cdcd_open(uint8_t rhport, const tusb_desc_interface_t* itf_desc, uint16_t max_len) { // Only support ACM subclass - TU_VERIFY( TUSB_CLASS_CDC == itf_desc->bInterfaceClass && - CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass, 0); + TU_VERIFY(TUSB_CLASS_CDC == itf_desc->bInterfaceClass && + CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass, + 0); - // Find available interface - cdcd_interface_t* p_cdc; - uint8_t cdc_id; - for (cdc_id = 0; cdc_id < CFG_TUD_CDC; cdc_id++) { - p_cdc = &_cdcd_itf[cdc_id]; - if (p_cdc->ep_in == 0) { - break; - } - } + const uint8_t cdc_id = find_cdc_itf(0); // Find available interface TU_ASSERT(cdc_id < CFG_TUD_CDC, 0); + cdcd_interface_t *p_cdc = &_cdcd_itf[cdc_id]; //------------- Control Interface -------------// p_cdc->rhport = rhport; p_cdc->itf_num = itf_desc->bInterfaceNumber; - uint16_t drv_len = sizeof(tusb_desc_interface_t); - const uint8_t* p_desc = tu_desc_next(itf_desc); + const uint8_t *p_desc = (const uint8_t *)itf_desc; + const uint8_t *desc_end = p_desc + max_len; - // Communication Functional Descriptors - while (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len) { - drv_len += tu_desc_len(p_desc); + // Skip all class-specific descriptor + p_desc = tu_desc_next(itf_desc); + while (tu_desc_in_bounds(p_desc, desc_end) && TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc)) { p_desc = tu_desc_next(p_desc); } + // notification endpoint (optional) if (TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)) { - // notification endpoint const tusb_desc_endpoint_t* desc_ep = (const tusb_desc_endpoint_t*) p_desc; TU_ASSERT(usbd_edpt_open(rhport, desc_ep), 0); p_cdc->ep_notify = desc_ep->bEndpointAddress; - drv_len += tu_desc_len(p_desc); p_desc = tu_desc_next(p_desc); } - //------------- Data Interface (if any) -------------// - if ((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && - (TUSB_CLASS_CDC_DATA == ((const tusb_desc_interface_t*) p_desc)->bInterfaceClass)) { - // next to endpoint descriptor - drv_len += tu_desc_len(p_desc); - p_desc = tu_desc_next(p_desc); + //------------- Data Interface (optional) -------------// + if (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) { + const tusb_desc_interface_t *data_itf_desc = (const tusb_desc_interface_t *)p_desc; + if (TUSB_CLASS_CDC_DATA == data_itf_desc->bInterfaceClass) { + for (uint8_t e = 0; e < data_itf_desc->bNumEndpoints; e++) { + if (!tu_desc_in_bounds(p_desc, desc_end)) { + break; + } + p_desc = tu_desc_next(p_desc); - // Open endpoint pair - TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &p_cdc->ep_out, &p_cdc->ep_in), 0); + const tusb_desc_endpoint_t *desc_ep = (const tusb_desc_endpoint_t *)p_desc; + TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_BULK == desc_ep->bmAttributes.xfer, 0); - drv_len += 2 * sizeof(tusb_desc_endpoint_t); - } + TU_ASSERT(usbd_edpt_open(rhport, desc_ep), 0); + if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) { + tu_edpt_stream_t *stream_tx = &p_cdc->stream.tx; + tu_edpt_stream_open(stream_tx, desc_ep); + + if (_cdcd_cfg.tx_persistent) { + tu_edpt_stream_write_xfer(rhport, stream_tx); // flush pending data + } else { + tu_edpt_stream_clear(stream_tx); + } + } else { + tu_edpt_stream_t *stream_rx = &p_cdc->stream.rx; - // Prepare for incoming data - _prep_out_transaction(cdc_id); + tu_edpt_stream_open(stream_rx, desc_ep); + if (!_cdcd_cfg.rx_persistent) { + tu_edpt_stream_clear(stream_rx); + } + TU_ASSERT(tu_edpt_stream_read_xfer(rhport, stream_rx) > 0, 0); // prepare for incoming data + } + } - return drv_len; + p_desc = tu_desc_next(p_desc); + } + } + + return p_desc - (const uint8_t *)itf_desc; } // Invoked when a control transfer occurred on an interface of this class @@ -449,7 +406,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control_requ } TU_VERIFY(itf < CFG_TUD_CDC); - switch (request->bRequest) { //-V2520 //-V2659 + switch (request->bRequest) { case CDC_REQUEST_SET_LINE_CODING: if (stage == CONTROL_STAGE_SETUP) { TU_LOG_DRV(" Set Line Coding\r\n"); @@ -484,15 +441,13 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control_requ // If enabled: fifo overwriting is disabled if DTR bit is set and vice versa if (_cdcd_cfg.tx_overwritabe_if_not_connected) { - tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr); + tu_fifo_set_overwritable(&p_cdc->stream.tx.ff, !dtr); } else { - tu_fifo_set_overwritable(&p_cdc->tx_ff, false); + tu_fifo_set_overwritable(&p_cdc->stream.tx.ff, false); } TU_LOG_DRV(" Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts); - - // Invoke callback - tud_cdc_line_state_cb(itf, dtr, rts); + tud_cdc_line_state_cb(itf, dtr, rts); // invoke callback } else { // nothing to do } @@ -507,7 +462,6 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control_requ } else { // nothing to do } - break; default: @@ -518,58 +472,45 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control_requ } bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { - (void) result; + (void)result; - uint8_t itf; - cdcd_interface_t* p_cdc; - - // Identify which interface to use - for (itf = 0; itf < CFG_TUD_CDC; itf++) { - p_cdc = &_cdcd_itf[itf]; - if ((ep_addr == p_cdc->ep_out) || (ep_addr == p_cdc->ep_in) || (ep_addr == p_cdc->ep_notify)) { - break; - } - } + uint8_t itf = find_cdc_itf(ep_addr); TU_ASSERT(itf < CFG_TUD_CDC); - cdcd_epbuf_t* p_epbuf = &_cdcd_epbuf[itf]; + cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; + tu_edpt_stream_t *stream_rx = &p_cdc->stream.rx; + tu_edpt_stream_t *stream_tx = &p_cdc->stream.tx; - // Received new data - if (ep_addr == p_cdc->ep_out) { - tu_fifo_write_n(&p_cdc->rx_ff, p_epbuf->epout, (uint16_t) xferred_bytes); + // Received new data, move to fifo + if (ep_addr == stream_rx->ep_addr) { + tu_edpt_stream_read_xfer_complete(stream_rx, xferred_bytes); - // Check for wanted char and invoke callback if needed - if (((signed char) p_cdc->wanted_char) != -1) { + // Check for wanted char and invoke wanted callback (multiple times if multiple wanted received) + if (((signed char)p_cdc->wanted_char) != -1) { for (uint32_t i = 0; i < xferred_bytes; i++) { - if ((p_cdc->wanted_char == (char) p_epbuf->epout[i]) && !tu_fifo_empty(&p_cdc->rx_ff)) { + if ((p_cdc->wanted_char == (char)stream_rx->ep_buf[i]) && !tu_edpt_stream_empty(stream_rx)) { tud_cdc_rx_wanted_cb(itf, p_cdc->wanted_char); } } } - // invoke receive callback (if there is still data) - if (!tu_fifo_empty(&p_cdc->rx_ff)) { + // invoke receive callback if there is still data + if (!tu_edpt_stream_empty(stream_rx)) { tud_cdc_rx_cb(itf); } - // prepare for OUT transaction - _prep_out_transaction(itf); + tu_edpt_stream_read_xfer(rhport, stream_rx); // prepare for more data } // Data sent to host, we continue to fetch from tx fifo to send. // Note: This will cause incorrect baudrate set in line coding. // Though maybe the baudrate is not really important !!! - if (ep_addr == p_cdc->ep_in) { + if (ep_addr == stream_tx->ep_addr) { // invoke transmit callback to possibly refill tx fifo tud_cdc_tx_complete_cb(itf); - if (0 == tud_cdc_n_write_flush(itf)) { - // If there is no data left, a ZLP should be sent if - // xferred_bytes is multiple of EP Packet size and not zero - if (0 == tu_fifo_count(&p_cdc->tx_ff) && xferred_bytes > 0 && (0 == (xferred_bytes & (BULK_PACKET_SIZE - 1)))) { - if (usbd_edpt_claim(rhport, p_cdc->ep_in)) { - TU_ASSERT(usbd_edpt_xfer(rhport, p_cdc->ep_in, NULL, 0)); - } - } + if (0 == tu_edpt_stream_write_xfer(rhport, stream_tx)) { + // If there is no data left, a ZLP should be sent if needed + tu_edpt_stream_write_zlp_if_needed(rhport, stream_tx, xferred_bytes); } } diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c index f065e486a..79e7dfa71 100644 --- a/src/class/midi/midi_device.c +++ b/src/class/midi/midi_device.c @@ -405,8 +405,10 @@ uint16_t midid_open(uint8_t rhport, const tusb_desc_interface_t *desc_itf, uint1 if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) { tu_edpt_stream_open(&p_midi->ep_stream.tx, desc_ep); + tu_edpt_stream_clear(&p_midi->ep_stream.tx); } else { tu_edpt_stream_open(&p_midi->ep_stream.rx, desc_ep); + tu_edpt_stream_clear(&p_midi->ep_stream.rx); TU_ASSERT(tu_edpt_stream_read_xfer(rhport, &p_midi->ep_stream.rx) > 0, 0); // prepare to receive data } diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index c916ebe47..7da4d2239 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -234,16 +234,18 @@ uint16_t vendord_open(uint8_t rhport, const tusb_desc_interface_t* desc_itf, uin const tusb_desc_endpoint_t* desc_ep = (const tusb_desc_endpoint_t*) p_desc; TU_ASSERT(usbd_edpt_open(rhport, desc_ep)); - // open endpoint stream, skip if already opened + // open endpoint stream, skip if already opened (multiple IN/OUT endpoints) if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) { - if (p_vendor->tx.stream.ep_addr == 0) { - tu_edpt_stream_open(&p_vendor->tx.stream, desc_ep); - tud_vendor_n_write_flush(itf); + tu_edpt_stream_t *stream_tx = &p_vendor->tx.stream; + if (stream_tx->ep_addr == 0) { + tu_edpt_stream_open(stream_tx, desc_ep); + tu_edpt_stream_write_xfer(rhport, stream_tx); // flush pending data } } else { - if (p_vendor->rx.stream.ep_addr == 0) { - tu_edpt_stream_open(&p_vendor->rx.stream, desc_ep); - TU_ASSERT(tu_edpt_stream_read_xfer(rhport, &p_vendor->rx.stream) > 0, 0); // prepare for incoming data + tu_edpt_stream_t *stream_rx = &p_vendor->rx.stream; + if (stream_rx->ep_addr == 0) { + tu_edpt_stream_open(stream_rx, desc_ep); + TU_ASSERT(tu_edpt_stream_read_xfer(rhport, stream_rx) > 0, 0); // prepare for incoming data } } } diff --git a/src/common/tusb_private.h b/src/common/tusb_private.h index 367209e57..f82f87b6f 100644 --- a/src/common/tusb_private.h +++ b/src/common/tusb_private.h @@ -100,7 +100,6 @@ bool tu_edpt_stream_deinit(tu_edpt_stream_t* s); // Open an stream for an endpoint TU_ATTR_ALWAYS_INLINE static inline void tu_edpt_stream_open(tu_edpt_stream_t* s, tusb_desc_endpoint_t const *desc_ep) { - tu_fifo_clear(&s->ff); s->ep_addr = desc_ep->bEndpointAddress; s->is_mps512 = tu_edpt_packet_size(desc_ep) == 512; } @@ -113,11 +112,15 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_edpt_stream_close(tu_edpt_stream_t* s->ep_addr = 0; } -// Clear fifo TU_ATTR_ALWAYS_INLINE static inline bool tu_edpt_stream_clear(tu_edpt_stream_t* s) { return tu_fifo_clear(&s->ff); } +TU_ATTR_ALWAYS_INLINE static inline bool tu_edpt_stream_empty(tu_edpt_stream_t *s) { + return tu_fifo_empty(&s->ff); +} + + //--------------------------------------------------------------------+ // Stream Write //--------------------------------------------------------------------+ diff --git a/src/tusb.c b/src/tusb.c index b308e2915..df33f2680 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -354,8 +354,8 @@ bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool ove return true; } -bool tu_edpt_stream_deinit(tu_edpt_stream_t* s) { - (void) s; +bool tu_edpt_stream_deinit(tu_edpt_stream_t *s) { + (void)s; #if OSAL_MUTEX_REQUIRED if (s->ff.mutex_wr) { osal_mutex_delete(s->ff.mutex_wr); @@ -363,7 +363,7 @@ bool tu_edpt_stream_deinit(tu_edpt_stream_t* s) { if (s->ff.mutex_rd) { osal_mutex_delete(s->ff.mutex_rd); } -#endif + #endif return true; } @@ -412,7 +412,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool stream_release(uint8_t hwid, tu_edpt_st bool tu_edpt_stream_write_zlp_if_needed(uint8_t hwid, tu_edpt_stream_t* s, uint32_t last_xferred_bytes) { // ZLP condition: no pending data, last transferred bytes is multiple of packet size const uint16_t mps = s->is_mps512 ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS; - TU_VERIFY(!tu_fifo_count(&s->ff) && last_xferred_bytes > 0 && (0 == (last_xferred_bytes & (mps - 1)))); + TU_VERIFY(tu_fifo_empty(&s->ff) && last_xferred_bytes > 0 && (0 == (last_xferred_bytes & (mps - 1)))); TU_VERIFY(stream_claim(hwid, s)); TU_ASSERT(stream_xfer(hwid, s, 0)); return true; -- cgit v1.3.1 From aac7ad1eb682a86a5b67e638f9b91a5c2743d2f1 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 13 Nov 2025 13:56:02 +0700 Subject: cdc device tx_persistent for dual host info to help with hil test --- .clang-format | 1 + examples/dual/host_info_to_device_cdc/src/main.c | 10 +++------- 2 files changed, 4 insertions(+), 7 deletions(-) (limited to 'examples') diff --git a/.clang-format b/.clang-format index 40d40f7e9..f15c26c9e 100644 --- a/.clang-format +++ b/.clang-format @@ -65,6 +65,7 @@ ContinuationIndentWidth: 2 ColumnLimit: 120 ConstructorInitializerAllOnOneLineOrOnePerLine: false Cpp11BracedListStyle: true +IncludeBlocks: Preserve IncludeCategories: - Regex: '^<.*' Priority: 1 diff --git a/examples/dual/host_info_to_device_cdc/src/main.c b/examples/dual/host_info_to_device_cdc/src/main.c index 03a1ac3d8..46e1d1ab2 100644 --- a/examples/dual/host_info_to_device_cdc/src/main.c +++ b/examples/dual/host_info_to_device_cdc/src/main.c @@ -106,6 +106,9 @@ static void usb_device_init(void) { .speed = TUSB_SPEED_AUTO }; tusb_init(BOARD_TUD_RHPORT, &dev_init); + tud_cdc_configure_t cdc_cfg = TUD_CDC_CONFIGURE_DEFAULT(); + cdc_cfg.tx_persistent = true; + tud_cdc_configure(&cdc_cfg); board_init_after_tusb(); } @@ -206,13 +209,6 @@ void tud_resume_cb(void) { } void cdc_task(void) { - if (!tud_cdc_connected()) { - // delay a bit otherwise we can outpace host's terminal. Linux will set LineState (DTR) then Line Coding. - // If we send data before Linux's terminal set Line Coding, it can be ignored --> missing data with hardware test loop - tusb_time_delay_ms_api(20); - return; - } - for (uint8_t daddr = 1; daddr <= CFG_TUH_DEVICE_MAX; daddr++) { if (tuh_mounted(daddr)) { if (is_print[daddr]) { -- cgit v1.3.1 From c9a9e94ae554c3d545b5eb795f81fa9216a93e4f Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 13 Nov 2025 14:34:17 +0700 Subject: tweak to dual host info device cdc to make it easier to pass hil test --- examples/dual/host_info_to_device_cdc/src/main.c | 24 +++++++++++++++++----- .../dual/host_info_to_device_cdc/src/tusb_config.h | 2 +- 2 files changed, 20 insertions(+), 6 deletions(-) (limited to 'examples') diff --git a/examples/dual/host_info_to_device_cdc/src/main.c b/examples/dual/host_info_to_device_cdc/src/main.c index 46e1d1ab2..00d059b66 100644 --- a/examples/dual/host_info_to_device_cdc/src/main.c +++ b/examples/dual/host_info_to_device_cdc/src/main.c @@ -69,7 +69,7 @@ enum { static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED; -static bool is_print[CFG_TUH_DEVICE_MAX+1] = { 0 }; +static bool is_printable[CFG_TUH_DEVICE_MAX + 1] = {0}; static tusb_desc_device_t descriptor_device[CFG_TUH_DEVICE_MAX+1]; static void print_utf16(uint16_t *temp_buf, size_t buf_len); @@ -108,6 +108,7 @@ static void usb_device_init(void) { tusb_init(BOARD_TUD_RHPORT, &dev_init); tud_cdc_configure_t cdc_cfg = TUD_CDC_CONFIGURE_DEFAULT(); cdc_cfg.tx_persistent = true; + cdc_cfg.tx_overwritabe_if_not_connected = false; tud_cdc_configure(&cdc_cfg); board_init_after_tusb(); } @@ -209,10 +210,23 @@ void tud_resume_cb(void) { } void cdc_task(void) { + static uint32_t connected_ms = 0; + + if (!tud_cdc_connected()) { + connected_ms = board_millis(); + return; + } + + // delay a bit otherwise we can outpace host's terminal. Linux will set LineState (DTR) then Line Coding. + // If we send data before Linux's terminal set Line Coding, it can be ignored --> missing data with hardware test loop + if (board_millis() - connected_ms < 100) { + return; // wait for stable connection + } + for (uint8_t daddr = 1; daddr <= CFG_TUH_DEVICE_MAX; daddr++) { if (tuh_mounted(daddr)) { - if (is_print[daddr]) { - is_print[daddr] = false; + if (is_printable[daddr]) { + is_printable[daddr] = false; print_device_info(daddr, &descriptor_device[daddr]); tud_cdc_write_flush(); } @@ -279,13 +293,13 @@ void tuh_enum_descriptor_device_cb(uint8_t daddr, tusb_desc_device_t const* desc void tuh_mount_cb(uint8_t daddr) { cdc_printf("mounted device %u\r\n", daddr); tud_cdc_write_flush(); - is_print[daddr] = true; + is_printable[daddr] = true; } void tuh_umount_cb(uint8_t daddr) { cdc_printf("unmounted device %u\r\n", daddr); tud_cdc_write_flush(); - is_print[daddr] = false; + is_printable[daddr] = false; } //--------------------------------------------------------------------+ diff --git a/examples/dual/host_info_to_device_cdc/src/tusb_config.h b/examples/dual/host_info_to_device_cdc/src/tusb_config.h index bb47fbf4a..601c27dae 100644 --- a/examples/dual/host_info_to_device_cdc/src/tusb_config.h +++ b/examples/dual/host_info_to_device_cdc/src/tusb_config.h @@ -112,7 +112,7 @@ // CDC FIFO size of TX and RX #define CFG_TUD_CDC_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) -#define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 256) // CDC Endpoint transfer buffer size, more is faster #define CFG_TUD_CDC_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) -- cgit v1.3.1 From be9d1973ac4c30fedd24b8199fd4dee5c842e2ef Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 17 Nov 2025 17:45:38 +0700 Subject: make TUP_DCD_EDPT_ISO_ALLOC i.e dcd_edpt_iso_alloc()/dcd_edpt_iso_activate() as default driver implementation. dcd_edpt_close() is deprecated and will be removed from all driver in the future. --- examples/device/video_capture/skip.txt | 1 - examples/device/video_capture_2ch/skip.txt | 1 - hw/bsp/family_support.cmake | 3 + hw/bsp/mcx/boards/frdm_mcxa153/board.cmake | 9 +- hw/bsp/mcx/boards/frdm_mcxa153/board.mk | 8 + .../mcx/boards/frdm_mcxa153/board/clock_config.c | 559 ++++++++++++++++++++ .../mcx/boards/frdm_mcxa153/board/clock_config.h | 385 ++++++++++++++ hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.c | 492 ++++++++++++++++++ hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.h | 211 ++++++++ hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c | 466 ----------------- hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h | 170 ------ hw/bsp/mcx/boards/frdm_mcxa153/frdm_mcxa153.mex | 573 +++++++++++++++++++++ hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c | 130 ----- hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h | 51 -- hw/bsp/mcx/family.c | 7 +- hw/bsp/mcx/family.mk | 13 +- src/common/tusb_mcu.h | 11 +- src/portable/chipidea/ci_fs/dcd_ci_fs.c | 83 ++- src/portable/nxp/khci/dcd_khci.c | 78 ++- 19 files changed, 2313 insertions(+), 938 deletions(-) create mode 100644 hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.c create mode 100644 hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.h create mode 100644 hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.c create mode 100644 hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.h delete mode 100644 hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c delete mode 100644 hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h create mode 100644 hw/bsp/mcx/boards/frdm_mcxa153/frdm_mcxa153.mex delete mode 100644 hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c delete mode 100644 hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h (limited to 'examples') diff --git a/examples/device/video_capture/skip.txt b/examples/device/video_capture/skip.txt index 50302c544..cb0c7d2e6 100644 --- a/examples/device/video_capture/skip.txt +++ b/examples/device/video_capture/skip.txt @@ -1,6 +1,5 @@ mcu:CH32V103 mcu:CH32V20X -mcu:MCXA15 mcu:MSP430x5xx mcu:NUC121 mcu:SAMD11 diff --git a/examples/device/video_capture_2ch/skip.txt b/examples/device/video_capture_2ch/skip.txt index 0f6508226..af3b0de04 100644 --- a/examples/device/video_capture_2ch/skip.txt +++ b/examples/device/video_capture_2ch/skip.txt @@ -6,7 +6,6 @@ mcu:CH32V103 mcu:CH32V20X mcu:CH32V307 mcu:STM32L0 -mcu:MCXA15 family:espressif board:curiosity_nano board:kuiic diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 23dfb9d80..2b9612186 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -264,6 +264,9 @@ function(family_configure_common TARGET RTOS) ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib SKIP_LINTING ON # need cmake 4.2 ) + if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang") + set_target_properties(${BOARD_TARGET} PROPERTIES COMPILE_OPTIONS -w) + endif () endif () target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET}) endif () diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake b/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake index 7cd8991e6..e6619992f 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake +++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.cmake @@ -14,8 +14,11 @@ function(update_board TARGET) BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED CFG_EXAMPLE_VIDEO_READONLY ) - target_sources(${TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c + target_sources(${TARGET} PRIVATE + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board/clock_config.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board/pin_mux.c + ) + target_include_directories(${TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board ) endfunction() diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.mk b/hw/bsp/mcx/boards/frdm_mcxa153/board.mk index af8416d8e..34558b43e 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/board.mk +++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.mk @@ -6,6 +6,14 @@ CPU_CORE = cortex-m33-nodsp-nofp CFLAGS += \ -DCPU_MCXA153VLH \ -DCFG_TUSB_MCU=OPT_MCU_MCXA15 \ + -DCFG_EXAMPLE_VIDEO_READONLY + +SRC_C += \ + ${BOARD_PATH}/board/clock_config.c \ + ${BOARD_PATH}/board/pin_mux.c + +INC += \ + $(TOP)/$(BOARD_PATH)/board JLINK_DEVICE = MCXA153 PYOCD_TARGET = MCXA153 diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.c b/hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.c new file mode 100644 index 000000000..599110d7a --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.c @@ -0,0 +1,559 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to setup clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + * + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v18.0 +processor: MCXA153 +package_id: MCXA153VLH +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: FRDM-MCXA153 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_clock.h" +#include "clock_config.h" +#include "fsl_spc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockFRO96M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CPU_clock.outFreq, value: 12 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: MAIN_clock.outFreq, value: 12 MHz} +- {id: Slow_clock.outFreq, value: 3 MHz} +- {id: System_clock.outFreq, value: 12 MHz} +- {id: TRACE_clock.outFreq, value: 12 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +- {id: WWDT0_clock.outFreq, value: 1 MHz} +settings: +- {id: SCGMode, value: SIRC} +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} +- {id: SCG.SCSSEL.sel, value: SCG.SIRC} +- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + + /*!< Set up system dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO12M */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +} +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO24M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO24M +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CPU_clock.outFreq, value: 24 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz} +- {id: FRO_HF_clock.outFreq, value: 48 MHz} +- {id: MAIN_clock.outFreq, value: 48 MHz} +- {id: Slow_clock.outFreq, value: 6 MHz} +- {id: System_clock.outFreq, value: 24 MHz} +- {id: TRACE_clock.outFreq, value: 24 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +- {id: WWDT0_clock.outFreq, value: 1 MHz} +settings: +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} +- {id: SYSCON.AHBCLKDIV.scale, value: '2'} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO24M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO24M configuration + ******************************************************************************/ +void BOARD_BootClockFRO24M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + + /*!< Set up system dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U); /* !< Set AHBCLKDIV divider to value 2 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ + + CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */ + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI0); /* !< Switch LPSPI0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI1); /* !< Switch LPSPI1 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPI2C0); /* !< Switch LPI2C0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART0); /* !< Switch LPUART0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART1); /* !< Switch LPUART1 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART2); /* !< Switch LPUART2 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPTMR0); /* !< Switch LPTMR0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); /* !< Switch I3C0FCLK to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_CMP0); /* !< Switch CMP0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_CMP1); /* !< Switch CMP1 to FRO_HF_DIV */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO24M_CORE_CLOCK; +} +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO48M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO48M +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CPU_clock.outFreq, value: 48 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz} +- {id: FRO_HF_clock.outFreq, value: 48 MHz} +- {id: MAIN_clock.outFreq, value: 48 MHz} +- {id: Slow_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 48 MHz} +- {id: TRACE_clock.outFreq, value: 48 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +- {id: WWDT0_clock.outFreq, value: 1 MHz} +settings: +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO48M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO48M configuration + ******************************************************************************/ +void BOARD_BootClockFRO48M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + + /*!< Set up system dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ + + CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */ + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI0); /* !< Switch LPSPI0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI1); /* !< Switch LPSPI1 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPI2C0); /* !< Switch LPI2C0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART0); /* !< Switch LPUART0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART1); /* !< Switch LPUART1 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART2); /* !< Switch LPUART2 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPTMR0); /* !< Switch LPTMR0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); /* !< Switch I3C0FCLK to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_CMP0); /* !< Switch CMP0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_CMP1); /* !< Switch CMP1 to FRO_HF_DIV */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO48M_CORE_CLOCK; +} +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO64M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO64M +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CPU_clock.outFreq, value: 64 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_DIV_clock.outFreq, value: 64 MHz} +- {id: FRO_HF_clock.outFreq, value: 64 MHz} +- {id: MAIN_clock.outFreq, value: 64 MHz} +- {id: Slow_clock.outFreq, value: 16 MHz} +- {id: System_clock.outFreq, value: 64 MHz} +- {id: TRACE_clock.outFreq, value: 64 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +- {id: WWDT0_clock.outFreq, value: 1 MHz} +settings: +- {id: VDD_CORE, value: voltage_1v1} +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FROHFDIV.scale, value: '1', locked: true} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} +- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true} +sources: +- {id: SCG.FIRC.outFreq, value: 64 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO64M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO64M configuration + ******************************************************************************/ +void BOARD_BootClockFRO64M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + + /*!< Set up system dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ + + CLOCK_SetupFROHFClocking(64000000U); /*!< Enable FRO HF(64MHz) output */ + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI0); /* !< Switch LPSPI0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI1); /* !< Switch LPSPI1 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPI2C0); /* !< Switch LPI2C0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART0); /* !< Switch LPUART0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART1); /* !< Switch LPUART1 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART2); /* !< Switch LPUART2 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPTMR0); /* !< Switch LPTMR0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); /* !< Switch I3C0FCLK to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_CMP0); /* !< Switch CMP0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_CMP1); /* !< Switch CMP1 to FRO_HF_DIV */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO64M_CORE_CLOCK; +} +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO96M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO96M +called_from_default_init: true +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CPU_clock.outFreq, value: 96 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_DIV_clock.outFreq, value: 96 MHz} +- {id: FRO_HF_clock.outFreq, value: 96 MHz} +- {id: MAIN_clock.outFreq, value: 96 MHz} +- {id: Slow_clock.outFreq, value: 24 MHz} +- {id: System_clock.outFreq, value: 96 MHz} +- {id: TRACE_clock.outFreq, value: 96 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +- {id: WWDT0_clock.outFreq, value: 1 MHz} +settings: +- {id: VDD_CORE, value: voltage_1v1} +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} +sources: +- {id: SCG.FIRC.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO96M configuration + ******************************************************************************/ +void BOARD_BootClockFRO96M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + + /*!< Set up system dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ + + CLOCK_SetupFROHFClocking(96000000U); /*!< Enable FRO HF(96MHz) output */ + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI0); /* !< Switch LPSPI0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI1); /* !< Switch LPSPI1 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPI2C0); /* !< Switch LPI2C0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART0); /* !< Switch LPUART0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART1); /* !< Switch LPUART1 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART2); /* !< Switch LPUART2 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_LPTMR0); /* !< Switch LPTMR0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); /* !< Switch I3C0FCLK to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_CMP0); /* !< Switch CMP0 to FRO_HF_DIV */ + CLOCK_AttachClk(kFRO_HF_DIV_to_CMP1); /* !< Switch CMP1 to FRO_HF_DIV */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO96M_CORE_CLOCK; +} diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.h b/hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.h new file mode 100644 index 000000000..d609eb468 --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.h @@ -0,0 +1,385 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFRO12M_ADC0_CLOCK 0UL /* Clock consumers of ADC0_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFRO12M_CLK16K_0_CLOCK 0UL /* Clock consumers of CLK16K_0_clock output : CMP0, WAKETIMER0, WUU0 */ +#define BOARD_BOOTCLOCKFRO12M_CLK16K_1_CLOCK 0UL /* Clock consumers of CLK16K_1_clock output : CMP1, LPTMR0, WAKETIMER0 */ +#define BOARD_BOOTCLOCKFRO12M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_CLK_1M_CLOCK 1000000UL /* Clock consumers of CLK_1M_clock output : CMC */ +#define BOARD_BOOTCLOCKFRO12M_CLK_48M_CLOCK 0UL /* Clock consumers of CLK_48M_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_CLK_IN_CLOCK 0UL /* Clock consumers of CLK_IN_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_CMP0FDIV_CLOCK 0UL /* Clock consumers of CMP0FDIV_clock output : CMP0 */ +#define BOARD_BOOTCLOCKFRO12M_CMP0RRDIV_CLOCK 0UL /* Clock consumers of CMP0RRDIV_clock output : CMP0 */ +#define BOARD_BOOTCLOCKFRO12M_CMP1FDIV_CLOCK 0UL /* Clock consumers of CMP1FDIV_clock output : CMP1 */ +#define BOARD_BOOTCLOCKFRO12M_CMP1RRDIV_CLOCK 0UL /* Clock consumers of CMP1RRDIV_clock output : CMP1 */ +#define BOARD_BOOTCLOCKFRO12M_CPU_CLOCK 12000000UL /* Clock consumers of CPU_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFRO12M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFRO12M_FREQME_REFERENCE_CLOCK 0UL /* Clock consumers of FREQME_reference_clock output : FREQME0 */ +#define BOARD_BOOTCLOCKFRO12M_FREQME_TARGET_CLOCK 0UL /* Clock consumers of FREQME_target_clock output : FREQME0 */ +#define BOARD_BOOTCLOCKFRO12M_FRO_12M_CLOCK 12000000UL /* Clock consumers of FRO_12M_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_FRO_HF_DIV_CLOCK 0UL /* Clock consumers of FRO_HF_DIV_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_FRO_HF_CLOCK 0UL /* Clock consumers of FRO_HF_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_I3C_FCLK_CLOCK 0UL /* Clock consumers of I3C_FCLK_clock output : I3C0 */ +#define BOARD_BOOTCLOCKFRO12M_I3C_SLOW_TC_CLOCK 0UL /* Clock consumers of I3C_SLOW_TC_clock output : I3C0 */ +#define BOARD_BOOTCLOCKFRO12M_I3C_SLOW_CLOCK 0UL /* Clock consumers of I3C_SLOW_clock output : I3C0 */ +#define BOARD_BOOTCLOCKFRO12M_LPI2C0_CLOCK 0UL /* Clock consumers of LPI2C0_clock output : LPI2C0 */ +#define BOARD_BOOTCLOCKFRO12M_LPSPI0_CLOCK 0UL /* Clock consumers of LPSPI0_clock output : LPSPI0 */ +#define BOARD_BOOTCLOCKFRO12M_LPSPI1_CLOCK 0UL /* Clock consumers of LPSPI1_clock output : LPSPI1 */ +#define BOARD_BOOTCLOCKFRO12M_LPTMR0_CLOCK 0UL /* Clock consumers of LPTMR0_clock output : LPTMR0 */ +#define BOARD_BOOTCLOCKFRO12M_LPUART0_CLOCK 0UL /* Clock consumers of LPUART0_clock output : LPUART0 */ +#define BOARD_BOOTCLOCKFRO12M_LPUART1_CLOCK 0UL /* Clock consumers of LPUART1_clock output : LPUART1 */ +#define BOARD_BOOTCLOCKFRO12M_LPUART2_CLOCK 0UL /* Clock consumers of LPUART2_clock output : LPUART2 */ +#define BOARD_BOOTCLOCKFRO12M_MAIN_CLOCK 12000000UL /* Clock consumers of MAIN_clock output : FLEXPWM0 */ +#define BOARD_BOOTCLOCKFRO12M_OSTIMER_CLOCK 0UL /* Clock consumers of OSTIMER_clock output : OSTIMER0 */ +#define BOARD_BOOTCLOCKFRO12M_FIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_SLOW_CLOCK 3000000UL /* Clock consumers of Slow_clock output : AOI0, CMC, CMP0, LPTMR0, WAKETIMER0, WUU0 */ +#define BOARD_BOOTCLOCKFRO12M_SYSTEM_CLOCK 12000000UL /* Clock consumers of System_clock output : ADC0, CMP1, CTIMER0, CTIMER1, CTIMER2, DMA0, FLEXPWM0, FREQME0, GPIO0, GPIO1, GPIO2, GPIO3, I3C0, INPUTMUX0, LPI2C0, LPSPI0, LPSPI1, LPUART0, LPUART1, LPUART2, OSTIMER0, PORT0, PORT1, PORT2, PORT3, QDC0, SWD, SysTick, USB0, UTICK0, WWDT0 */ +#define BOARD_BOOTCLOCKFRO12M_TRACE_CLOCK 12000000UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFRO12M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0 */ +#define BOARD_BOOTCLOCKFRO12M_UTICK_CLOCK 1000000UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFRO12M_WUU_CLOCK 0UL /* Clock consumers of WUU_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO12M_WWDT0_CLOCK 1000000UL /* Clock consumers of WWDT0_clock output : WWDT0 */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO24M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO24M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO24M_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFRO24M_ADC0_CLOCK 0UL /* Clock consumers of ADC0_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFRO24M_CLK16K_0_CLOCK 0UL /* Clock consumers of CLK16K_0_clock output : CMP0, WAKETIMER0, WUU0 */ +#define BOARD_BOOTCLOCKFRO24M_CLK16K_1_CLOCK 0UL /* Clock consumers of CLK16K_1_clock output : CMP1, LPTMR0, WAKETIMER0 */ +#define BOARD_BOOTCLOCKFRO24M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO24M_CLK_1M_CLOCK 1000000UL /* Clock consumers of CLK_1M_clock output : CMC */ +#define BOARD_BOOTCLOCKFRO24M_CLK_48M_CLOCK 48000000UL /* Clock consumers of CLK_48M_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO24M_CLK_IN_CLOCK 0UL /* Clock consumers of CLK_IN_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO24M_CMP0FDIV_CLOCK 0UL /* Clock consumers of CMP0FDIV_clock output : CMP0 */ +#define BOARD_BOOTCLOCKFRO24M_CMP0RRDIV_CLOCK 0UL /* Clock consumers of CMP0RRDIV_clock output : CMP0 */ +#define BOARD_BOOTCLOCKFRO24M_CMP1FDIV_CLOCK 0UL /* Clock consumers of CMP1FDIV_clock output : CMP1 */ +#define BOARD_BOOTCLOCKFRO24M_CMP1RRDIV_CLOCK 0UL /* Clock consumers of CMP1RRDIV_clock output : CMP1 */ +#define BOARD_BOOTCLOCKFRO24M_CPU_CLOCK 24000000UL /* Clock consumers of CPU_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO24M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFRO24M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFRO24M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFRO24M_FREQME_REFERENCE_CLOCK 0UL /* Clock consumers of FREQME_reference_clock output : FREQME0 */ +#define BOARD_BOOTCLOCKFRO24M_FREQME_TARGET_CLOCK 0UL /* Clock consumers of FREQME_target_clock output : FREQME0 */ +#define BOARD_BOOTCLOCKFRO24M_FRO_12M_CLOCK 12000000UL /* Clock consumers of FRO_12M_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO24M_FRO_HF_DIV_CLOCK 48000000UL /* Clock consumers of FRO_HF_DIV_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO24M_FRO_HF_CLOCK 48000000UL /* Clock consumers of FRO_HF_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO24M_I3C_FCLK_CLOCK 0UL /* Clock consumers of I3C_FCLK_clock output : I3C0 */ +#define BOARD_BOOTCLOCKFRO24M_I3C_SLOW_TC_CLOCK 0UL /* Clock consumers of I3C_SLOW_TC_clock output : I3C0 */ +#define BOARD_BOOTCLOCKFRO24M_I3C_SLOW_CLOCK 0UL /* Clock consumers of I3C_SLOW_clock output : I3C0 */ +#define BOARD_BOOTCLOCKFRO24M_LPI2C0_CLOCK 0UL /* Clock consumers of LPI2C0_clock output : LPI2C0 */ +#define BOARD_BOOTCLOCKFRO24M_LPSPI0_CLOCK 0UL /* Clock consumers of LPSPI0_clock output : LPSPI0 */ +#define BOARD_BOOTCLOCKFRO24M_LPSPI1_CLOCK 0UL /* Clock consumers of LPSPI1_clock output : LPSPI1 */ +#define BOARD_BOOTCLOCKFRO24M_LPTMR0_CLOCK 0UL /* Clock consumers of LPTMR0_clock output : LPTMR0 */ +#define BOARD_BOOTCLOCKFRO24M_LPUART0_CLOCK 0UL /* Clock consumers of LPUART0_clock output : LPUART0 */ +#define BOARD_BOOTCLOCKFRO24M_LPUART1_CLOCK 0UL /* Clock consumers of LPUART1_clock output : LPUART1 */ +#define BOARD_BOOTCLOCKFRO24M_LPUART2_CLOCK 0UL /* Clock consumers of LPUART2_clock output : LPUART2 */ +#define BOARD_BOOTCLOCKFRO24M_MAIN_CLOCK 48000000UL /* Clock consumers of MAIN_clock output : FLEXPWM0 */ +#define BOARD_BOOTCLOCKFRO24M_OSTIMER_CLOCK 0UL /* Clock consumers of OSTIMER_clock output : OSTIMER0 */ +#define BOARD_BOOTCLOCKFRO24M_FIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO24M_SIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO24M_SLOW_CLOCK 6000000UL /* Clock consumers of Slow_clock output : AOI0, CMC, CMP0, LPTMR0, WAKETIMER0, WUU0 */ +#define BOARD_BOOTCLOCKFRO24M_SYSTEM_CLOCK 24000000UL /* Clock consumers of System_clock output : ADC0, CMP1, CTIMER0, CTIMER1, CTIMER2, DMA0, FLEXPWM0, FREQME0, GPIO0, GPIO1, GPIO2, GPIO3, I3C0, INPUTMUX0, LPI2C0, LPSPI0, LPSPI1, LPUART0, LPUART1, LPUART2, OSTIMER0, PORT0, PORT1, PORT2, PORT3, QDC0, SWD, SysTick, USB0, UTICK0, WWDT0 */ +#define BOARD_BOOTCLOCKFRO24M_TRACE_CLOCK 24000000UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFRO24M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0 */ +#define BOARD_BOOTCLOCKFRO24M_UTICK_CLOCK 1000000UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFRO24M_WUU_CLOCK 0UL /* Clock consumers of WUU_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO24M_WWDT0_CLOCK 1000000UL /* Clock consumers of WWDT0_clock output : WWDT0 */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO24M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO24M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO48M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO48M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFRO48M_ADC0_CLOCK 0UL /* Clock consumers of ADC0_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFRO48M_CLK16K_0_CLOCK 0UL /* Clock consumers of CLK16K_0_clock output : CMP0, WAKETIMER0, WUU0 */ +#define BOARD_BOOTCLOCKFRO48M_CLK16K_1_CLOCK 0UL /* Clock consumers of CLK16K_1_clock output : CMP1, LPTMR0, WAKETIMER0 */ +#define BOARD_BOOTCLOCKFRO48M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO48M_CLK_1M_CLOCK 1000000UL /* Clock consumers of CLK_1M_clock output : CMC */ +#define BOARD_BOOTCLOCKFRO48M_CLK_48M_CLOCK 48000000UL /* Clock consumers of CLK_48M_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO48M_CLK_IN_CLOCK 0UL /* Clock consumers of CLK_IN_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO48M_CMP0FDIV_CLOCK 0UL /* Clock consumers of CMP0FDIV_clock output : CMP0 */ +#define BOARD_BOOTCLOCKFRO48M_CMP0RRDIV_CLOCK 0UL /* Clock consumers of CMP0RRDIV_clock output : CMP0 */ +#define BOARD_BOOTCLOCKFRO48M_CMP1FDIV_CLOCK 0UL /* Clock consumers of CMP1FDIV_clock output : CMP1 */ +#define BOARD_BOOTCLOCKFRO48M_CMP1RRDIV_CLOCK 0UL /* Clock consumers of CMP1RRDIV_clock output : CMP1 */ +#define BOARD_BOOTCLOCKFRO48M_CPU_CLOCK 48000000UL /* Clock consumers of CPU_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO48M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFRO48M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFRO48M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFRO48M_FREQME_REFERENCE_CLOCK 0UL /* Clock consumers of FREQME_reference_clock output : FREQME0 */ +#define BOARD_BOOTCLOCKFRO48M_FREQME_TARGET_CLOCK 0UL /* Clock consumers of FREQME_target_clock output : FREQME0 */ +#define BOARD_BOOTCLOCKFRO48M_FRO_12M_CLOCK 12000000UL /* Clock consumers of FRO_12M_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO48M_FRO_HF_DIV_CLOCK 48000000UL /* Clock consumers of FRO_HF_DIV_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO48M_FRO_HF_CLOCK 48000000UL /* Clock consumers of FRO_HF_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO48M_I3C_FCLK_CLOCK 0UL /* Clock consumers of I3C_FCLK_clock output : I3C0 */ +#define BOARD_BOOTCLOCKFRO48M_I3C_SLOW_TC_CLOCK 0UL /* Clock consumers of I3C_SLOW_TC_clock output : I3C0 */ +#define BOARD_BOOTCLOCKFRO48M_I3C_SLOW_CLOCK 0UL /* Clock consumers of I3C_SLOW_clock output : I3C0 */ +#define BOARD_BOOTCLOCKFRO48M_LPI2C0_CLOCK 0UL /* Clock consumers of LPI2C0_clock output : LPI2C0 */ +#define BOARD_BOOTCLOCKFRO48M_LPSPI0_CLOCK 0UL /* Clock consumers of LPSPI0_clock output : LPSPI0 */ +#define BOARD_BOOTCLOCKFRO48M_LPSPI1_CLOCK 0UL /* Clock consumers of LPSPI1_clock output : LPSPI1 */ +#define BOARD_BOOTCLOCKFRO48M_LPTMR0_CLOCK 0UL /* Clock consumers of LPTMR0_clock output : LPTMR0 */ +#define BOARD_BOOTCLOCKFRO48M_LPUART0_CLOCK 0UL /* Clock consumers of LPUART0_clock output : LPUART0 */ +#define BOARD_BOOTCLOCKFRO48M_LPUART1_CLOCK 0UL /* Clock consumers of LPUART1_clock output : LPUART1 */ +#define BOARD_BOOTCLOCKFRO48M_LPUART2_CLOCK 0UL /* Clock consumers of LPUART2_clock output : LPUART2 */ +#define BOARD_BOOTCLOCKFRO48M_MAIN_CLOCK 48000000UL /* Clock consumers of MAIN_clock output : FLEXPWM0 */ +#define BOARD_BOOTCLOCKFRO48M_OSTIMER_CLOCK 0UL /* Clock consumers of OSTIMER_clock output : OSTIMER0 */ +#define BOARD_BOOTCLOCKFRO48M_FIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO48M_SIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO48M_SLOW_CLOCK 12000000UL /* Clock consumers of Slow_clock output : AOI0, CMC, CMP0, LPTMR0, WAKETIMER0, WUU0 */ +#define BOARD_BOOTCLOCKFRO48M_SYSTEM_CLOCK 48000000UL /* Clock consumers of System_clock output : ADC0, CMP1, CTIMER0, CTIMER1, CTIMER2, DMA0, FLEXPWM0, FREQME0, GPIO0, GPIO1, GPIO2, GPIO3, I3C0, INPUTMUX0, LPI2C0, LPSPI0, LPSPI1, LPUART0, LPUART1, LPUART2, OSTIMER0, PORT0, PORT1, PORT2, PORT3, QDC0, SWD, SysTick, USB0, UTICK0, WWDT0 */ +#define BOARD_BOOTCLOCKFRO48M_TRACE_CLOCK 48000000UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFRO48M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0 */ +#define BOARD_BOOTCLOCKFRO48M_UTICK_CLOCK 1000000UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFRO48M_WUU_CLOCK 0UL /* Clock consumers of WUU_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO48M_WWDT0_CLOCK 1000000UL /* Clock consumers of WWDT0_clock output : WWDT0 */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO48M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO48M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO64M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO64M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO64M_CORE_CLOCK 64000000U /*!< Core clock frequency: 64000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFRO64M_ADC0_CLOCK 0UL /* Clock consumers of ADC0_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFRO64M_CLK16K_0_CLOCK 0UL /* Clock consumers of CLK16K_0_clock output : CMP0, WAKETIMER0, WUU0 */ +#define BOARD_BOOTCLOCKFRO64M_CLK16K_1_CLOCK 0UL /* Clock consumers of CLK16K_1_clock output : CMP1, LPTMR0, WAKETIMER0 */ +#define BOARD_BOOTCLOCKFRO64M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO64M_CLK_1M_CLOCK 1000000UL /* Clock consumers of CLK_1M_clock output : CMC */ +#define BOARD_BOOTCLOCKFRO64M_CLK_48M_CLOCK 48000000UL /* Clock consumers of CLK_48M_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO64M_CLK_IN_CLOCK 0UL /* Clock consumers of CLK_IN_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO64M_CMP0FDIV_CLOCK 0UL /* Clock consumers of CMP0FDIV_clock output : CMP0 */ +#define BOARD_BOOTCLOCKFRO64M_CMP0RRDIV_CLOCK 0UL /* Clock consumers of CMP0RRDIV_clock output : CMP0 */ +#define BOARD_BOOTCLOCKFRO64M_CMP1FDIV_CLOCK 0UL /* Clock consumers of CMP1FDIV_clock output : CMP1 */ +#define BOARD_BOOTCLOCKFRO64M_CMP1RRDIV_CLOCK 0UL /* Clock consumers of CMP1RRDIV_clock output : CMP1 */ +#define BOARD_BOOTCLOCKFRO64M_CPU_CLOCK 64000000UL /* Clock consumers of CPU_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO64M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFRO64M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFRO64M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFRO64M_FREQME_REFERENCE_CLOCK 0UL /* Clock consumers of FREQME_reference_clock output : FREQME0 */ +#define BOARD_BOOTCLOCKFRO64M_FREQME_TARGET_CLOCK 0UL /* Clock consumers of FREQME_target_clock output : FREQME0 */ +#define BOARD_BOOTCLOCKFRO64M_FRO_12M_CLOCK 12000000UL /* Clock consumers of FRO_12M_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO64M_FRO_HF_DIV_CLOCK 64000000UL /* Clock consumers of FRO_HF_DIV_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO64M_FRO_HF_CLOCK 64000000UL /* Clock consumers of FRO_HF_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO64M_I3C_FCLK_CLOCK 0UL /* Clock consumers of I3C_FCLK_clock output : I3C0 */ +#define BOARD_BOOTCLOCKFRO64M_I3C_SLOW_TC_CLOCK 0UL /* Clock consumers of I3C_SLOW_TC_clock output : I3C0 */ +#define BOARD_BOOTCLOCKFRO64M_I3C_SLOW_CLOCK 0UL /* Clock consumers of I3C_SLOW_clock output : I3C0 */ +#define BOARD_BOOTCLOCKFRO64M_LPI2C0_CLOCK 0UL /* Clock consumers of LPI2C0_clock output : LPI2C0 */ +#define BOARD_BOOTCLOCKFRO64M_LPSPI0_CLOCK 0UL /* Clock consumers of LPSPI0_clock output : LPSPI0 */ +#define BOARD_BOOTCLOCKFRO64M_LPSPI1_CLOCK 0UL /* Clock consumers of LPSPI1_clock output : LPSPI1 */ +#define BOARD_BOOTCLOCKFRO64M_LPTMR0_CLOCK 0UL /* Clock consumers of LPTMR0_clock output : LPTMR0 */ +#define BOARD_BOOTCLOCKFRO64M_LPUART0_CLOCK 0UL /* Clock consumers of LPUART0_clock output : LPUART0 */ +#define BOARD_BOOTCLOCKFRO64M_LPUART1_CLOCK 0UL /* Clock consumers of LPUART1_clock output : LPUART1 */ +#define BOARD_BOOTCLOCKFRO64M_LPUART2_CLOCK 0UL /* Clock consumers of LPUART2_clock output : LPUART2 */ +#define BOARD_BOOTCLOCKFRO64M_MAIN_CLOCK 64000000UL /* Clock consumers of MAIN_clock output : FLEXPWM0 */ +#define BOARD_BOOTCLOCKFRO64M_OSTIMER_CLOCK 0UL /* Clock consumers of OSTIMER_clock output : OSTIMER0 */ +#define BOARD_BOOTCLOCKFRO64M_FIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO64M_SIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO64M_SLOW_CLOCK 16000000UL /* Clock consumers of Slow_clock output : AOI0, CMC, CMP0, LPTMR0, WAKETIMER0, WUU0 */ +#define BOARD_BOOTCLOCKFRO64M_SYSTEM_CLOCK 64000000UL /* Clock consumers of System_clock output : ADC0, CMP1, CTIMER0, CTIMER1, CTIMER2, DMA0, FLEXPWM0, FREQME0, GPIO0, GPIO1, GPIO2, GPIO3, I3C0, INPUTMUX0, LPI2C0, LPSPI0, LPSPI1, LPUART0, LPUART1, LPUART2, OSTIMER0, PORT0, PORT1, PORT2, PORT3, QDC0, SWD, SysTick, USB0, UTICK0, WWDT0 */ +#define BOARD_BOOTCLOCKFRO64M_TRACE_CLOCK 64000000UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFRO64M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0 */ +#define BOARD_BOOTCLOCKFRO64M_UTICK_CLOCK 1000000UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFRO64M_WUU_CLOCK 0UL /* Clock consumers of WUU_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO64M_WWDT0_CLOCK 1000000UL /* Clock consumers of WWDT0_clock output : WWDT0 */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO64M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO64M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO96M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKFRO96M_ADC0_CLOCK 0UL /* Clock consumers of ADC0_clock output : ADC0 */ +#define BOARD_BOOTCLOCKFRO96M_CLK16K_0_CLOCK 0UL /* Clock consumers of CLK16K_0_clock output : CMP0, WAKETIMER0, WUU0 */ +#define BOARD_BOOTCLOCKFRO96M_CLK16K_1_CLOCK 0UL /* Clock consumers of CLK16K_1_clock output : CMP1, LPTMR0, WAKETIMER0 */ +#define BOARD_BOOTCLOCKFRO96M_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO96M_CLK_1M_CLOCK 1000000UL /* Clock consumers of CLK_1M_clock output : CMC */ +#define BOARD_BOOTCLOCKFRO96M_CLK_48M_CLOCK 48000000UL /* Clock consumers of CLK_48M_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO96M_CLK_IN_CLOCK 0UL /* Clock consumers of CLK_IN_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO96M_CMP0FDIV_CLOCK 0UL /* Clock consumers of CMP0FDIV_clock output : CMP0 */ +#define BOARD_BOOTCLOCKFRO96M_CMP0RRDIV_CLOCK 0UL /* Clock consumers of CMP0RRDIV_clock output : CMP0 */ +#define BOARD_BOOTCLOCKFRO96M_CMP1FDIV_CLOCK 0UL /* Clock consumers of CMP1FDIV_clock output : CMP1 */ +#define BOARD_BOOTCLOCKFRO96M_CMP1RRDIV_CLOCK 0UL /* Clock consumers of CMP1RRDIV_clock output : CMP1 */ +#define BOARD_BOOTCLOCKFRO96M_CPU_CLOCK 96000000UL /* Clock consumers of CPU_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO96M_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */ +#define BOARD_BOOTCLOCKFRO96M_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */ +#define BOARD_BOOTCLOCKFRO96M_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */ +#define BOARD_BOOTCLOCKFRO96M_FREQME_REFERENCE_CLOCK 0UL /* Clock consumers of FREQME_reference_clock output : FREQME0 */ +#define BOARD_BOOTCLOCKFRO96M_FREQME_TARGET_CLOCK 0UL /* Clock consumers of FREQME_target_clock output : FREQME0 */ +#define BOARD_BOOTCLOCKFRO96M_FRO_12M_CLOCK 12000000UL /* Clock consumers of FRO_12M_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO96M_FRO_HF_DIV_CLOCK 96000000UL /* Clock consumers of FRO_HF_DIV_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO96M_FRO_HF_CLOCK 96000000UL /* Clock consumers of FRO_HF_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO96M_I3C_FCLK_CLOCK 0UL /* Clock consumers of I3C_FCLK_clock output : I3C0 */ +#define BOARD_BOOTCLOCKFRO96M_I3C_SLOW_TC_CLOCK 0UL /* Clock consumers of I3C_SLOW_TC_clock output : I3C0 */ +#define BOARD_BOOTCLOCKFRO96M_I3C_SLOW_CLOCK 0UL /* Clock consumers of I3C_SLOW_clock output : I3C0 */ +#define BOARD_BOOTCLOCKFRO96M_LPI2C0_CLOCK 0UL /* Clock consumers of LPI2C0_clock output : LPI2C0 */ +#define BOARD_BOOTCLOCKFRO96M_LPSPI0_CLOCK 0UL /* Clock consumers of LPSPI0_clock output : LPSPI0 */ +#define BOARD_BOOTCLOCKFRO96M_LPSPI1_CLOCK 0UL /* Clock consumers of LPSPI1_clock output : LPSPI1 */ +#define BOARD_BOOTCLOCKFRO96M_LPTMR0_CLOCK 0UL /* Clock consumers of LPTMR0_clock output : LPTMR0 */ +#define BOARD_BOOTCLOCKFRO96M_LPUART0_CLOCK 0UL /* Clock consumers of LPUART0_clock output : LPUART0 */ +#define BOARD_BOOTCLOCKFRO96M_LPUART1_CLOCK 0UL /* Clock consumers of LPUART1_clock output : LPUART1 */ +#define BOARD_BOOTCLOCKFRO96M_LPUART2_CLOCK 0UL /* Clock consumers of LPUART2_clock output : LPUART2 */ +#define BOARD_BOOTCLOCKFRO96M_MAIN_CLOCK 96000000UL /* Clock consumers of MAIN_clock output : FLEXPWM0 */ +#define BOARD_BOOTCLOCKFRO96M_OSTIMER_CLOCK 0UL /* Clock consumers of OSTIMER_clock output : OSTIMER0 */ +#define BOARD_BOOTCLOCKFRO96M_FIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO96M_SIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO96M_SLOW_CLOCK 24000000UL /* Clock consumers of Slow_clock output : AOI0, CMC, CMP0, LPTMR0, WAKETIMER0, WUU0 */ +#define BOARD_BOOTCLOCKFRO96M_SYSTEM_CLOCK 96000000UL /* Clock consumers of System_clock output : ADC0, CMP1, CTIMER0, CTIMER1, CTIMER2, DMA0, FLEXPWM0, FREQME0, GPIO0, GPIO1, GPIO2, GPIO3, I3C0, INPUTMUX0, LPI2C0, LPSPI0, LPSPI1, LPUART0, LPUART1, LPUART2, OSTIMER0, PORT0, PORT1, PORT2, PORT3, QDC0, SWD, SysTick, USB0, UTICK0, WWDT0 */ +#define BOARD_BOOTCLOCKFRO96M_TRACE_CLOCK 96000000UL /* Clock consumers of TRACE_clock output : SWD */ +#define BOARD_BOOTCLOCKFRO96M_USB0_CLOCK 0UL /* Clock consumers of USB0_clock output : USB0 */ +#define BOARD_BOOTCLOCKFRO96M_UTICK_CLOCK 1000000UL /* Clock consumers of UTICK_clock output : UTICK0 */ +#define BOARD_BOOTCLOCKFRO96M_WUU_CLOCK 0UL /* Clock consumers of WUU_clock output : N/A */ +#define BOARD_BOOTCLOCKFRO96M_WWDT0_CLOCK 1000000UL /* Clock consumers of WWDT0_clock output : WWDT0 */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.c b/hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.c new file mode 100644 index 000000000..58b0f47e9 --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.c @@ -0,0 +1,492 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v17.0 +processor: MCXA153 +package_id: MCXA153VLH +mcu_data: ksdk2_0 +processor_version: 25.09.10 +board: FRDM-MCXA153 +external_user_signals: {} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_port.h" +#include "fsl_gpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitDEBUG_UARTPins(); + BOARD_InitLEDsPins(); + BOARD_InitBUTTONsPins(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '51', peripheral: LPUART0, signal: RX, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/I3C0_PUR, slew_rate: fast, open_drain: disable, + drive_strength: high, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal} + - {pin_num: '52', peripheral: LPUART0, signal: TX, pin_signal: P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/CMP0_OUT/CMP1_IN1, slew_rate: fast, open_drain: disable, + drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) +{ + /* Write to PORT0: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GatePORT0); + /* LPUART0 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn); + /* PORT0 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); + + const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */ + .pullSelect = kPORT_PullDisable, + /* Low internal pull resistor value is selected. */ + .pullValueSelect = kPORT_LowPullResistor, + /* Fast slew rate is configured */ + .slewRate = kPORT_FastSlewRate, + /* Passive input filter is disabled */ + .passiveFilterEnable = kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + .openDrainEnable = kPORT_OpenDrainDisable, + /* High drive strength is configured */ + .driveStrength = kPORT_HighDriveStrength, + /* Normal drive strength is configured */ + .driveStrength1 = kPORT_NormalDriveStrength, + /* Pin is configured as LPUART0_RXD */ + .mux = kPORT_MuxAlt2, + /* Digital input enabled */ + .inputBuffer = kPORT_InputBufferEnable, + /* Digital input is not inverted */ + .invertInput = kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + .lockRegister = kPORT_UnlockRegister}; + /* PORT0_2 (pin 51) is configured as LPUART0_RXD */ + PORT_SetPinConfig(BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN, &DEBUG_UART_RX); + + const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up resistor is enabled */ + .pullSelect = kPORT_PullUp, + /* Low internal pull resistor value is selected. */ + .pullValueSelect = kPORT_LowPullResistor, + /* Fast slew rate is configured */ + .slewRate = kPORT_FastSlewRate, + /* Passive input filter is disabled */ + .passiveFilterEnable = kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + .openDrainEnable = kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + .driveStrength = kPORT_LowDriveStrength, + /* Normal drive strength is configured */ + .driveStrength1 = kPORT_NormalDriveStrength, + /* Pin is configured as LPUART0_TXD */ + .mux = kPORT_MuxAlt2, + /* Digital input enabled */ + .inputBuffer = kPORT_InputBufferEnable, + /* Digital input is not inverted */ + .invertInput = kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + .lockRegister = kPORT_UnlockRegister}; + /* PORT0_3 (pin 52) is configured as LPUART0_TXD */ + PORT_SetPinConfig(BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT, BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN, &DEBUG_UART_TX); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSWD_DEBUGPins: +- options: {callFromInitBoot: 'false', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '50', peripheral: SWD, signal: SWCLK, pin_signal: P0_1/TCLK/SWCLK/LPUART0_CTS_B/LPSPI0_SDI/CT_INP1, slew_rate: fast, open_drain: disable, drive_strength: low, + pull_select: down, pull_enable: enable, input_buffer: enable, invert_input: normal} + - {pin_num: '49', peripheral: SWD, signal: SWDIO, pin_signal: P0_0/TMS/SWDIO/LPUART0_RTS_B/LPSPI0_PCS0/CT_INP0, slew_rate: fast, open_drain: disable, drive_strength: high, + pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal} + - {pin_num: '51', peripheral: SWD, signal: SWO, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/I3C0_PUR, slew_rate: fast, open_drain: disable, + drive_strength: high, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitSWD_DEBUGPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitSWD_DEBUGPins(void) +{ + /* Write to PORT0: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GatePORT0); + /* PORT0 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); + /* LPUART0 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn); + + const port_pin_config_t DEBUG_SWD_SWDIO = {/* Internal pull-up resistor is enabled */ + .pullSelect = kPORT_PullUp, + /* Low internal pull resistor value is selected. */ + .pullValueSelect = kPORT_LowPullResistor, + /* Fast slew rate is configured */ + .slewRate = kPORT_FastSlewRate, + /* Passive input filter is disabled */ + .passiveFilterEnable = kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + .openDrainEnable = kPORT_OpenDrainDisable, + /* High drive strength is configured */ + .driveStrength = kPORT_HighDriveStrength, + /* Normal drive strength is configured */ + .driveStrength1 = kPORT_NormalDriveStrength, + /* Pin is configured as SWDIO */ + .mux = kPORT_MuxAlt1, + /* Digital input enabled */ + .inputBuffer = kPORT_InputBufferEnable, + /* Digital input is not inverted */ + .invertInput = kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + .lockRegister = kPORT_UnlockRegister}; + /* PORT0_0 (pin 49) is configured as SWDIO */ + PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN, &DEBUG_SWD_SWDIO); + + const port_pin_config_t DEBUG_SWD_SWDCLK = {/* Internal pull-down resistor is enabled */ + .pullSelect = kPORT_PullDown, + /* Low internal pull resistor value is selected. */ + .pullValueSelect = kPORT_LowPullResistor, + /* Fast slew rate is configured */ + .slewRate = kPORT_FastSlewRate, + /* Passive input filter is disabled */ + .passiveFilterEnable = kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + .openDrainEnable = kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + .driveStrength = kPORT_LowDriveStrength, + /* Normal drive strength is configured */ + .driveStrength1 = kPORT_NormalDriveStrength, + /* Pin is configured as SWCLK */ + .mux = kPORT_MuxAlt1, + /* Digital input enabled */ + .inputBuffer = kPORT_InputBufferEnable, + /* Digital input is not inverted */ + .invertInput = kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + .lockRegister = kPORT_UnlockRegister}; + /* PORT0_1 (pin 50) is configured as SWCLK */ + PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN, &DEBUG_SWD_SWDCLK); + + const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */ + .pullSelect = kPORT_PullDisable, + /* Low internal pull resistor value is selected. */ + .pullValueSelect = kPORT_LowPullResistor, + /* Fast slew rate is configured */ + .slewRate = kPORT_FastSlewRate, + /* Passive input filter is disabled */ + .passiveFilterEnable = kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + .openDrainEnable = kPORT_OpenDrainDisable, + /* High drive strength is configured */ + .driveStrength = kPORT_HighDriveStrength, + /* Normal drive strength is configured */ + .driveStrength1 = kPORT_NormalDriveStrength, + /* Pin is configured as SWO */ + .mux = kPORT_MuxAlt1, + /* Digital input enabled */ + .inputBuffer = kPORT_InputBufferEnable, + /* Digital input is not inverted */ + .invertInput = kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + .lockRegister = kPORT_UnlockRegister}; + /* PORT0_2 (pin 51) is configured as SWO */ + PORT_SetPinConfig(BOARD_INITSWD_DEBUGPINS_DEBUG_UART_RX_PORT, BOARD_INITSWD_DEBUGPINS_DEBUG_UART_RX_PIN, &DEBUG_UART_RX); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitLEDsPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '37', peripheral: GPIO3, signal: 'GPIO, 13', pin_signal: P3_13/LPUART2_CTS_B/CT1_MAT3/PWM0_X1, direction: OUTPUT, gpio_init_state: 'true', slew_rate: fast, + open_drain: disable, drive_strength: low, pull_select: up, pull_enable: disable, input_buffer: enable, invert_input: normal} + - {pin_num: '38', peripheral: GPIO3, signal: 'GPIO, 12', pin_signal: P3_12/LPUART2_RTS_B/CT1_MAT2/PWM0_X0, direction: OUTPUT, gpio_init_state: 'true', slew_rate: fast, + open_drain: disable, drive_strength: low, pull_select: up, pull_enable: disable, input_buffer: enable, invert_input: normal} + - {pin_num: '46', peripheral: GPIO3, signal: 'GPIO, 0', pin_signal: P3_0/WUU0_IN22/TRIG_IN0/CT_INP16/PWM0_A0, direction: OUTPUT, gpio_init_state: 'true', slew_rate: fast, + open_drain: disable, drive_strength: low, pull_select: up, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitLEDsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitLEDsPins(void) +{ + /* Write to GPIO3: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GateGPIO3); + /* Write to PORT3: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GatePORT3); + /* GPIO3 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn); + /* PORT3 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); + + gpio_pin_config_t LED_BLUE_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO3_0 (pin 46) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_BLUE_GPIO, BOARD_INITLEDSPINS_LED_BLUE_PIN, &LED_BLUE_config); + + gpio_pin_config_t LED_RED_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO3_12 (pin 38) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_RED_GPIO, BOARD_INITLEDSPINS_LED_RED_PIN, &LED_RED_config); + + gpio_pin_config_t LED_GREEN_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 1U + }; + /* Initialize GPIO functionality on pin PIO3_13 (pin 37) */ + GPIO_PinInit(BOARD_INITLEDSPINS_LED_GREEN_GPIO, BOARD_INITLEDSPINS_LED_GREEN_PIN, &LED_GREEN_config); + + /* PORT3_0 (pin 46) is configured as P3_0 */ + PORT_SetPinMux(BOARD_INITLEDSPINS_LED_BLUE_PORT, BOARD_INITLEDSPINS_LED_BLUE_PIN, kPORT_MuxAlt0); + + PORT3->PCR[0] = + ((PORT3->PCR[0] & + /* Mask bits to zero which are setting */ + (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_DSE_MASK | PORT_PCR_IBE_MASK | PORT_PCR_INV_MASK))) + + /* Pull Select: Enables internal pullup resistor. */ + | PORT_PCR_PS(PCR_PS_ps1) + + /* Pull Enable: Disables. */ + | PORT_PCR_PE(PCR_PE_pe0) + + /* Slew Rate Enable: Fast. */ + | PORT_PCR_SRE(PCR_SRE_sre0) + + /* Passive Filter Enable: Disables. */ + | PORT_PCR_PFE(PCR_PFE_pfe0) + + /* Open Drain Enable: Disables. */ + | PORT_PCR_ODE(PCR_ODE_ode0) + + /* Drive Strength Enable: Low. */ + | PORT_PCR_DSE(PCR_DSE_dse0) + + /* Input Buffer Enable: Enables. */ + | PORT_PCR_IBE(PCR_IBE_ibe1) + + /* Invert Input: Does not invert. */ + | PORT_PCR_INV(PCR_INV_inv0)); + + /* PORT3_12 (pin 38) is configured as P3_12 */ + PORT_SetPinMux(BOARD_INITLEDSPINS_LED_RED_PORT, BOARD_INITLEDSPINS_LED_RED_PIN, kPORT_MuxAlt0); + + PORT3->PCR[12] = + ((PORT3->PCR[12] & + /* Mask bits to zero which are setting */ + (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_DSE_MASK | PORT_PCR_IBE_MASK | PORT_PCR_INV_MASK))) + + /* Pull Select: Enables internal pullup resistor. */ + | PORT_PCR_PS(PCR_PS_ps1) + + /* Pull Enable: Disables. */ + | PORT_PCR_PE(PCR_PE_pe0) + + /* Slew Rate Enable: Fast. */ + | PORT_PCR_SRE(PCR_SRE_sre0) + + /* Open Drain Enable: Disables. */ + | PORT_PCR_ODE(PCR_ODE_ode0) + + /* Drive Strength Enable: Low. */ + | PORT_PCR_DSE(PCR_DSE_dse0) + + /* Input Buffer Enable: Enables. */ + | PORT_PCR_IBE(PCR_IBE_ibe1) + + /* Invert Input: Does not invert. */ + | PORT_PCR_INV(PCR_INV_inv0)); + + /* PORT3_13 (pin 37) is configured as P3_13 */ + PORT_SetPinMux(BOARD_INITLEDSPINS_LED_GREEN_PORT, BOARD_INITLEDSPINS_LED_GREEN_PIN, kPORT_MuxAlt0); + + PORT3->PCR[13] = + ((PORT3->PCR[13] & + /* Mask bits to zero which are setting */ + (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_DSE_MASK | PORT_PCR_IBE_MASK | PORT_PCR_INV_MASK))) + + /* Pull Select: Enables internal pullup resistor. */ + | PORT_PCR_PS(PCR_PS_ps1) + + /* Pull Enable: Disables. */ + | PORT_PCR_PE(PCR_PE_pe0) + + /* Slew Rate Enable: Fast. */ + | PORT_PCR_SRE(PCR_SRE_sre0) + + /* Open Drain Enable: Disables. */ + | PORT_PCR_ODE(PCR_ODE_ode0) + + /* Drive Strength Enable: Low. */ + | PORT_PCR_DSE(PCR_DSE_dse0) + + /* Input Buffer Enable: Enables. */ + | PORT_PCR_IBE(PCR_IBE_ibe1) + + /* Invert Input: Does not invert. */ + | PORT_PCR_INV(PCR_INV_inv0)); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitBUTTONsPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '1', peripheral: GPIO1, signal: 'GPIO, 7', pin_signal: P1_7/WUU0_IN9/TRIG_OUT2/LPUART2_CTS_B/CT_INP7/ADC0_A23, slew_rate: fast, open_drain: disable, + drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal} + - {pin_num: '8', peripheral: GPIO1, signal: 'GPIO, 29', pin_signal: P1_29/RESET_B/SPC_LPREQ, slew_rate: fast, open_drain: enable, drive_strength: low, pull_select: up, + pull_enable: enable, passive_filter: enable, pull_value: low, input_buffer: enable, invert_input: normal} + - {pin_num: '32', peripheral: GPIO3, signal: 'GPIO, 29', pin_signal: P3_29/WUU0_IN27/ISPMODE_N/CT_INP3/ADC0_A14, slew_rate: fast, open_drain: disable, drive_strength: low, + pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBUTTONsPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitBUTTONsPins(void) +{ + /* Write to PORT1: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GatePORT1); + /* Write to PORT3: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GatePORT3); + /* GPIO1 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn); + /* PORT1 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn); + /* GPIO3 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn); + /* PORT3 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); + + const port_pin_config_t SW1 = {/* Internal pull-up resistor is enabled */ + .pullSelect = kPORT_PullUp, + /* Low internal pull resistor value is selected. */ + .pullValueSelect = kPORT_LowPullResistor, + /* Fast slew rate is configured */ + .slewRate = kPORT_FastSlewRate, + /* Passive input filter is enabled */ + .passiveFilterEnable = kPORT_PassiveFilterEnable, + /* Open drain output is enabled */ + .openDrainEnable = kPORT_OpenDrainEnable, + /* Low drive strength is configured */ + .driveStrength = kPORT_LowDriveStrength, + /* Normal drive strength is configured */ + .driveStrength1 = kPORT_NormalDriveStrength, + /* Pin is configured as P1_29 */ + .mux = kPORT_MuxAlt0, + /* Digital input enabled */ + .inputBuffer = kPORT_InputBufferEnable, + /* Digital input is not inverted */ + .invertInput = kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + .lockRegister = kPORT_UnlockRegister}; + /* PORT1_29 (pin 8) is configured as P1_29 */ + PORT_SetPinConfig(BOARD_INITBUTTONSPINS_SW1_PORT, BOARD_INITBUTTONSPINS_SW1_PIN, &SW1); + + const port_pin_config_t SW3 = {/* Internal pull-up/down resistor is disabled */ + .pullSelect = kPORT_PullDisable, + /* Low internal pull resistor value is selected. */ + .pullValueSelect = kPORT_LowPullResistor, + /* Fast slew rate is configured */ + .slewRate = kPORT_FastSlewRate, + /* Passive input filter is disabled */ + .passiveFilterEnable = kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + .openDrainEnable = kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + .driveStrength = kPORT_LowDriveStrength, + /* Normal drive strength is configured */ + .driveStrength1 = kPORT_NormalDriveStrength, + /* Pin is configured as P1_7 */ + .mux = kPORT_MuxAlt0, + /* Digital input enabled */ + .inputBuffer = kPORT_InputBufferEnable, + /* Digital input is not inverted */ + .invertInput = kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + .lockRegister = kPORT_UnlockRegister}; + /* PORT1_7 (pin 1) is configured as P1_7 */ + PORT_SetPinConfig(BOARD_INITBUTTONSPINS_SW3_PORT, BOARD_INITBUTTONSPINS_SW3_PIN, &SW3); + + const port_pin_config_t ISP = {/* Internal pull-up resistor is enabled */ + .pullSelect = kPORT_PullUp, + /* Low internal pull resistor value is selected. */ + .pullValueSelect = kPORT_LowPullResistor, + /* Fast slew rate is configured */ + .slewRate = kPORT_FastSlewRate, + /* Passive input filter is disabled */ + .passiveFilterEnable = kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + .openDrainEnable = kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + .driveStrength = kPORT_LowDriveStrength, + /* Normal drive strength is configured */ + .driveStrength1 = kPORT_NormalDriveStrength, + /* Pin is configured as P3_29 */ + .mux = kPORT_MuxAlt0, + /* Digital input enabled */ + .inputBuffer = kPORT_InputBufferEnable, + /* Digital input is not inverted */ + .invertInput = kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + .lockRegister = kPORT_UnlockRegister}; + /* PORT3_29 (pin 32) is configured as P3_29 */ + PORT_SetPinConfig(BOARD_INITBUTTONSPINS_ISP_PORT, BOARD_INITBUTTONSPINS_ISP_PIN, &ISP); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.h b/hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.h new file mode 100644 index 000000000..4a42f266d --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa153/board/pin_mux.h @@ -0,0 +1,211 @@ +/* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! @name PORT0_2 (number 51), P0_2/SWO/J25[3]/J18[6] + @{ */ + +/* Symbols to be used with PORT driver */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PORT PORT0 /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN 2U /*!<@brief PORT pin number */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_RX_PIN_MASK (1U << 2U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PORT0_3 (number 52), P0_3/J25[1]/J18[8] + @{ */ + +/* Symbols to be used with PORT driver */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PORT PORT0 /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN 3U /*!<@brief PORT pin number */ +#define BOARD_INITDEBUG_UARTPINS_DEBUG_UART_TX_PIN_MASK (1U << 3U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + +/*! @name PORT0_1 (number 50), P0_1/SWCLK/JP10[2]/J18[4] + @{ */ + +/* Symbols to be used with PORT driver */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PORT PORT0 /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN 1U /*!<@brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDCLK_PIN_MASK (1U << 1U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PORT0_0 (number 49), P0_0/SWDIO/J18[2] + @{ */ + +/* Symbols to be used with PORT driver */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PORT PORT0 /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN 0U /*!<@brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_SWD_SWDIO_PIN_MASK (1U << 0U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PORT0_2 (number 51), P0_2/SWO/J25[3]/J18[6] + @{ */ + +/* Symbols to be used with PORT driver */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_UART_RX_PORT PORT0 /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_UART_RX_PIN 2U /*!<@brief PORT pin number */ +#define BOARD_INITSWD_DEBUGPINS_DEBUG_UART_RX_PIN_MASK (1U << 2U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSWD_DEBUGPins(void); + +#define PCR_DSE_dse0 0x00u /*!<@brief Drive Strength Enable: Low */ +#define PCR_IBE_ibe1 0x01u /*!<@brief Input Buffer Enable: Enables */ +#define PCR_INV_inv0 0x00u /*!<@brief Invert Input: Does not invert */ +#define PCR_ODE_ode0 0x00u /*!<@brief Open Drain Enable: Disables */ +#define PCR_PE_pe0 0x00u /*!<@brief Pull Enable: Disables */ +#define PCR_PFE_pfe0 0x00u /*!<@brief Passive Filter Enable: Disables */ +#define PCR_PS_ps1 0x01u /*!<@brief Pull Select: Enables internal pullup resistor */ +#define PCR_SRE_sre0 0x00u /*!<@brief Slew Rate Enable: Fast */ + +/*! @name PORT3_13 (number 37), P3_13/J1[14] + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_GREEN_GPIO GPIO3 /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_GREEN_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN 13U /*!<@brief GPIO pin number */ +#define BOARD_INITLEDSPINS_LED_GREEN_GPIO_PIN_MASK (1U << 13U) /*!<@brief GPIO pin mask */ + +/* Symbols to be used with PORT driver */ +#define BOARD_INITLEDSPINS_LED_GREEN_PORT PORT3 /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_GREEN_PIN 13U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_GREEN_PIN_MASK (1U << 13U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PORT3_12 (number 38), P3_12/J1[12]/J5[1] + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_RED_GPIO GPIO3 /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_RED_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN 12U /*!<@brief GPIO pin number */ +#define BOARD_INITLEDSPINS_LED_RED_GPIO_PIN_MASK (1U << 12U) /*!<@brief GPIO pin mask */ + +/* Symbols to be used with PORT driver */ +#define BOARD_INITLEDSPINS_LED_RED_PORT PORT3 /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_RED_PIN 12U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_RED_PIN_MASK (1U << 12U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PORT3_0 (number 46), P3_0/J1[8] + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITLEDSPINS_LED_BLUE_GPIO GPIO3 /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_BLUE_INIT_GPIO_VALUE 1U /*!<@brief GPIO output initial state */ +#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN 0U /*!<@brief GPIO pin number */ +#define BOARD_INITLEDSPINS_LED_BLUE_GPIO_PIN_MASK (1U << 0U) /*!<@brief GPIO pin mask */ + +/* Symbols to be used with PORT driver */ +#define BOARD_INITLEDSPINS_LED_BLUE_PORT PORT3 /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITLEDSPINS_LED_BLUE_PIN 0U /*!<@brief PORT pin number */ +#define BOARD_INITLEDSPINS_LED_BLUE_PIN_MASK (1U << 0U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitLEDsPins(void); + +/*! @name PORT1_7 (number 1), P1_7/J1[1] + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_SW3_GPIO GPIO1 /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_SW3_GPIO_PIN 7U /*!<@brief GPIO pin number */ +#define BOARD_INITBUTTONSPINS_SW3_GPIO_PIN_MASK (1U << 7U) /*!<@brief GPIO pin mask */ + +/* Symbols to be used with PORT driver */ +#define BOARD_INITBUTTONSPINS_SW3_PORT PORT1 /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_SW3_PIN 7U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_SW3_PIN_MASK (1U << 7U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PORT1_29 (number 8), P1_29/J3[6]/J18[10] + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_SW1_GPIO GPIO1 /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_SW1_GPIO_PIN 29U /*!<@brief GPIO pin number */ +#define BOARD_INITBUTTONSPINS_SW1_GPIO_PIN_MASK (1U << 29U) /*!<@brief GPIO pin mask */ + +/* Symbols to be used with PORT driver */ +#define BOARD_INITBUTTONSPINS_SW1_PORT PORT1 /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_SW1_PIN 29U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_SW1_PIN_MASK (1U << 29U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! @name PORT3_29 (number 32), P3_29/J18[7]/J4[11] + @{ */ + +/* Symbols to be used with GPIO driver */ +#define BOARD_INITBUTTONSPINS_ISP_GPIO GPIO3 /*!<@brief GPIO peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_ISP_GPIO_PIN 29U /*!<@brief GPIO pin number */ +#define BOARD_INITBUTTONSPINS_ISP_GPIO_PIN_MASK (1U << 29U) /*!<@brief GPIO pin mask */ + +/* Symbols to be used with PORT driver */ +#define BOARD_INITBUTTONSPINS_ISP_PORT PORT3 /*!<@brief PORT peripheral base pointer */ +#define BOARD_INITBUTTONSPINS_ISP_PIN 29U /*!<@brief PORT pin number */ +#define BOARD_INITBUTTONSPINS_ISP_PIN_MASK (1U << 29U) /*!<@brief PORT pin mask */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitBUTTONsPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c deleted file mode 100644 index 5a132dc67..000000000 --- a/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c +++ /dev/null @@ -1,466 +0,0 @@ -/* - * Copyright 2023 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ -/* - * How to setup clock using clock driver functions: - * - * 1. Setup clock sources. - * - * 2. Set up wait states of the flash. - * - * 3. Set up all dividers. - * - * 4. Set up all selectors to provide selected clocks. - * - */ - -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Clocks v12.0 -processor: MCXA153 -package_id: MCXA153VLH -mcu_data: ksdk2_0 -processor_version: 0.13.0 - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -#include "fsl_clock.h" -#include "clock_config.h" -#include "fsl_spc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* System clock frequency. */ -//extern uint32_t SystemCoreClock; - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ -void BOARD_InitBootClocks(void) -{ -} - -/******************************************************************************* - ******************** Configuration BOARD_BootClockFRO12M ********************** - ******************************************************************************/ -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockFRO12M -outputs: -- {id: CLK_1M_clock.outFreq, value: 1 MHz} -- {id: CPU_clock.outFreq, value: 12 MHz} -- {id: FRO_12M_clock.outFreq, value: 12 MHz} -- {id: MAIN_clock.outFreq, value: 12 MHz} -- {id: Slow_clock.outFreq, value: 3 MHz} -- {id: System_clock.outFreq, value: 12 MHz} -settings: -- {id: SCGMode, value: SIRC} -- {id: FRO_HF_PERIPHERALS_EN_CFG, value: Disabled} -- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} -- {id: SCG.SCSSEL.sel, value: SCG.SIRC} -- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -/******************************************************************************* - * Variables for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -void BOARD_BootClockFRO12M(void) -{ - uint32_t coreFreq; - spc_active_mode_core_ldo_option_t ldoOption; - spc_sram_voltage_config_t sramOption; - - /* Get the CPU Core frequency */ - coreFreq = CLOCK_GetCoreSysClkFreq(); - - /* The flow of increasing voltage and frequency */ - if (coreFreq <= BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) { - /* Set the LDO_CORE VDD regulator level */ - ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; - ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; - (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); - /* Configure Flash to support different voltage level and frequency */ - FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); - /* Specifies the operating voltage for the SRAM's read/write timing margin */ - sramOption.operateVoltage = kSPC_sramOperateAt1P0V; - sramOption.requestVoltageUpdate = true; - (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); - } - - CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ - - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO12M */ - - /* The flow of decreasing voltage and frequency */ - if (coreFreq > BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) { - /* Configure Flash to support different voltage level and frequency */ - FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); - /* Specifies the operating voltage for the SRAM's read/write timing margin */ - sramOption.operateVoltage = kSPC_sramOperateAt1P0V; - sramOption.requestVoltageUpdate = true; - (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); - /* Set the LDO_CORE VDD regulator level */ - ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; - ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; - (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); - } - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - - /*!< Set up dividers */ - CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ - - /* Set SystemCoreClock variable */ - SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; -} -/******************************************************************************* - ******************** Configuration BOARD_BootClockFRO24M ********************** - ******************************************************************************/ -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockFRO24M -outputs: -- {id: CLK_1M_clock.outFreq, value: 1 MHz} -- {id: CLK_48M_clock.outFreq, value: 48 MHz} -- {id: CPU_clock.outFreq, value: 24 MHz} -- {id: FRO_12M_clock.outFreq, value: 12 MHz} -- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz} -- {id: FRO_HF_clock.outFreq, value: 48 MHz} -- {id: MAIN_clock.outFreq, value: 48 MHz} -- {id: Slow_clock.outFreq, value: 6 MHz} -- {id: System_clock.outFreq, value: 24 MHz} -settings: -- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} -- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -/******************************************************************************* - * Variables for BOARD_BootClockFRO24M configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockFRO24M configuration - ******************************************************************************/ -void BOARD_BootClockFRO24M(void) -{ - uint32_t coreFreq; - spc_active_mode_core_ldo_option_t ldoOption; - spc_sram_voltage_config_t sramOption; - - /* Get the CPU Core frequency */ - coreFreq = CLOCK_GetCoreSysClkFreq(); - - /* The flow of increasing voltage and frequency */ - if (coreFreq <= BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) { - /* Set the LDO_CORE VDD regulator level */ - ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; - ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; - (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); - /* Configure Flash to support different voltage level and frequency */ - FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); - /* Specifies the operating voltage for the SRAM's read/write timing margin */ - sramOption.operateVoltage = kSPC_sramOperateAt1P0V; - sramOption.requestVoltageUpdate = true; - (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); - } - - CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */ - - CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ - - CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ - - /* The flow of decreasing voltage and frequency */ - if (coreFreq > BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) { - /* Configure Flash to support different voltage level and frequency */ - FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); - /* Specifies the operating voltage for the SRAM's read/write timing margin */ - sramOption.operateVoltage = kSPC_sramOperateAt1P0V; - sramOption.requestVoltageUpdate = true; - (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); - /* Set the LDO_CORE VDD regulator level */ - ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; - ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; - (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); - } - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - - /*!< Set up dividers */ - CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U); /* !< Set AHBCLKDIV divider to value 2 */ - CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ - - /* Set SystemCoreClock variable */ - SystemCoreClock = BOARD_BOOTCLOCKFRO24M_CORE_CLOCK; -} -/******************************************************************************* - ******************** Configuration BOARD_BootClockFRO48M ********************** - ******************************************************************************/ -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockFRO48M -outputs: -- {id: CLK_1M_clock.outFreq, value: 1 MHz} -- {id: CLK_48M_clock.outFreq, value: 48 MHz} -- {id: CPU_clock.outFreq, value: 48 MHz} -- {id: FRO_12M_clock.outFreq, value: 12 MHz} -- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz} -- {id: FRO_HF_clock.outFreq, value: 48 MHz} -- {id: MAIN_clock.outFreq, value: 48 MHz} -- {id: Slow_clock.outFreq, value: 12 MHz} -- {id: System_clock.outFreq, value: 48 MHz} -settings: -- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -/******************************************************************************* - * Variables for BOARD_BootClockFRO48M configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockFRO48M configuration - ******************************************************************************/ -void BOARD_BootClockFRO48M(void) -{ - uint32_t coreFreq; - spc_active_mode_core_ldo_option_t ldoOption; - spc_sram_voltage_config_t sramOption; - - /* Get the CPU Core frequency */ - coreFreq = CLOCK_GetCoreSysClkFreq(); - - /* The flow of increasing voltage and frequency */ - if (coreFreq <= BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) { - /* Set the LDO_CORE VDD regulator level */ - ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; - ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; - (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); - /* Configure Flash to support different voltage level and frequency */ - FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); - /* Specifies the operating voltage for the SRAM's read/write timing margin */ - sramOption.operateVoltage = kSPC_sramOperateAt1P0V; - sramOption.requestVoltageUpdate = true; - (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); - } - - CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */ - - CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ - - CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ - - /* The flow of decreasing voltage and frequency */ - if (coreFreq > BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) { - /* Configure Flash to support different voltage level and frequency */ - FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); - /* Specifies the operating voltage for the SRAM's read/write timing margin */ - sramOption.operateVoltage = kSPC_sramOperateAt1P0V; - sramOption.requestVoltageUpdate = true; - (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); - /* Set the LDO_CORE VDD regulator level */ - ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; - ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; - (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); - } - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - - /*!< Set up dividers */ - CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ - CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ - - /* Set SystemCoreClock variable */ - SystemCoreClock = BOARD_BOOTCLOCKFRO48M_CORE_CLOCK; -} -/******************************************************************************* - ******************** Configuration BOARD_BootClockFRO64M ********************** - ******************************************************************************/ -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockFRO64M -outputs: -- {id: CLK_1M_clock.outFreq, value: 1 MHz} -- {id: CLK_48M_clock.outFreq, value: 48 MHz} -- {id: CPU_clock.outFreq, value: 64 MHz} -- {id: FRO_12M_clock.outFreq, value: 12 MHz} -- {id: FRO_HF_DIV_clock.outFreq, value: 64 MHz} -- {id: FRO_HF_clock.outFreq, value: 64 MHz} -- {id: MAIN_clock.outFreq, value: 64 MHz} -- {id: Slow_clock.outFreq, value: 16 MHz} -- {id: System_clock.outFreq, value: 64 MHz} -settings: -- {id: VDD_CORE, value: voltage_1v1} -- {id: MRCC.FROHFDIV.scale, value: '1', locked: true} -- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} -- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true} -sources: -- {id: SCG.FIRC.outFreq, value: 64 MHz} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -/******************************************************************************* - * Variables for BOARD_BootClockFRO64M configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockFRO64M configuration - ******************************************************************************/ -void BOARD_BootClockFRO64M(void) -{ - uint32_t coreFreq; - spc_active_mode_core_ldo_option_t ldoOption; - spc_sram_voltage_config_t sramOption; - - /* Get the CPU Core frequency */ - coreFreq = CLOCK_GetCoreSysClkFreq(); - - /* The flow of increasing voltage and frequency */ - if (coreFreq <= BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) { - /* Set the LDO_CORE VDD regulator level */ - ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; - ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; - (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); - /* Configure Flash to support different voltage level and frequency */ - FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); - /* Specifies the operating voltage for the SRAM's read/write timing margin */ - sramOption.operateVoltage = kSPC_sramOperateAt1P1V; - sramOption.requestVoltageUpdate = true; - (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); - } - - CLOCK_SetupFROHFClocking(64000000U); /*!< Enable FRO HF(64MHz) output */ - - CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ - - CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ - - /* The flow of decreasing voltage and frequency */ - if (coreFreq > BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) { - /* Configure Flash to support different voltage level and frequency */ - FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); - /* Specifies the operating voltage for the SRAM's read/write timing margin */ - sramOption.operateVoltage = kSPC_sramOperateAt1P1V; - sramOption.requestVoltageUpdate = true; - (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); - /* Set the LDO_CORE VDD regulator level */ - ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; - ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; - (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); - } - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - - /*!< Set up dividers */ - CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ - CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ - - /* Set SystemCoreClock variable */ - SystemCoreClock = BOARD_BOOTCLOCKFRO64M_CORE_CLOCK; -} -/******************************************************************************* - ******************** Configuration BOARD_BootClockFRO96M ********************** - ******************************************************************************/ -/* clang-format off */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockFRO96M -outputs: -- {id: CLK_1M_clock.outFreq, value: 1 MHz} -- {id: CLK_48M_clock.outFreq, value: 48 MHz} -- {id: CPU_clock.outFreq, value: 96 MHz} -- {id: FRO_12M_clock.outFreq, value: 12 MHz} -- {id: FRO_HF_DIV_clock.outFreq, value: 96 MHz} -- {id: FRO_HF_clock.outFreq, value: 96 MHz} -- {id: MAIN_clock.outFreq, value: 96 MHz} -- {id: Slow_clock.outFreq, value: 24 MHz} -- {id: System_clock.outFreq, value: 96 MHz} -settings: -- {id: VDD_CORE, value: voltage_1v1} -- {id: CLKOUTDIV_HALT, value: Enable} -- {id: MRCC.FROHFDIV.scale, value: '1', locked: true} -- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} -- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true} -sources: -- {id: SCG.FIRC.outFreq, value: 96 MHz} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* clang-format on */ - -/******************************************************************************* - * Variables for BOARD_BootClockFRO96M configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockFRO96M configuration - ******************************************************************************/ -void BOARD_BootClockFRO96M(void) -{ - uint32_t coreFreq; - spc_active_mode_core_ldo_option_t ldoOption; - spc_sram_voltage_config_t sramOption; - - /* Get the CPU Core frequency */ - coreFreq = CLOCK_GetCoreSysClkFreq(); - - /* The flow of increasing voltage and frequency */ - if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) { - /* Set the LDO_CORE VDD regulator level */ - ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; - ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; - (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); - /* Configure Flash to support different voltage level and frequency */ - FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); - /* Specifies the operating voltage for the SRAM's read/write timing margin */ - sramOption.operateVoltage = kSPC_sramOperateAt1P1V; - sramOption.requestVoltageUpdate = true; - (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); - } - - CLOCK_SetupFROHFClocking(96000000U); /*!< Enable FRO HF(96MHz) output */ - - CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ - - CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ - - /* The flow of decreasing voltage and frequency */ - if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) { - /* Configure Flash to support different voltage level and frequency */ - FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); - /* Specifies the operating voltage for the SRAM's read/write timing margin */ - sramOption.operateVoltage = kSPC_sramOperateAt1P1V; - sramOption.requestVoltageUpdate = true; - (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); - /* Set the LDO_CORE VDD regulator level */ - ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; - ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; - (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); - } - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - - /*!< Set up dividers */ - CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ - CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ - - /* Set SystemCoreClock variable */ - SystemCoreClock = BOARD_BOOTCLOCKFRO96M_CORE_CLOCK; -} diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h b/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h deleted file mode 100644 index aae811052..000000000 --- a/hw/bsp/mcx/boards/frdm_mcxa153/clock_config.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright 2023 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ******************** Configuration BOARD_BootClockFRO12M ********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ - - -/******************************************************************************* - * API for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockFRO12M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ******************** Configuration BOARD_BootClockFRO24M ********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockFRO24M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKFRO24M_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */ - - -/******************************************************************************* - * API for BOARD_BootClockFRO24M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockFRO24M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ******************** Configuration BOARD_BootClockFRO48M ********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockFRO48M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKFRO48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ - - -/******************************************************************************* - * API for BOARD_BootClockFRO48M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockFRO48M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ******************** Configuration BOARD_BootClockFRO64M ********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockFRO64M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKFRO64M_CORE_CLOCK 64000000U /*!< Core clock frequency: 64000000Hz */ - - -/******************************************************************************* - * API for BOARD_BootClockFRO64M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockFRO64M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ******************** Configuration BOARD_BootClockFRO96M ********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockFRO96M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ - - -/******************************************************************************* - * API for BOARD_BootClockFRO96M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockFRO96M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/frdm_mcxa153.mex b/hw/bsp/mcx/boards/frdm_mcxa153/frdm_mcxa153.mex new file mode 100644 index 000000000..43fea73db --- /dev/null +++ b/hw/bsp/mcx/boards/frdm_mcxa153/frdm_mcxa153.mex @@ -0,0 +1,573 @@ + + + + MCXA153 + MCXA153VLH + FRDM-MCXA153 + ksdk2_0 + + + + + + + true + false + + /* + * Copyright 2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + true + + true + true + false + + + + + + + + + 25.09.10 + + + + + + + Configures pin routing and optionally pin electrical features. + + true + cm33_core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + cm33_core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + true + cm33_core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + true + cm33_core0 + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 25.09.10 + + + + + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + false + + + + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + false + + + + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + false + + + + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + false + + + + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + + N/A + + + + + + + + + + 25.09.10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + N/A + + + + diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c deleted file mode 100644 index 47709951b..000000000 --- a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright 2023 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -/* clang-format off */ -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Pins v14.0 -processor: MCXA153 -package_id: MCXA153VLH -mcu_data: ksdk2_0 -processor_version: 0.14.4 - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ -/* clang-format on */ - -#include "fsl_common.h" -#include "fsl_port.h" -#include "pin_mux.h" - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitBootPins - * Description : Calls initialization functions. - * - * END ****************************************************************************************************************/ -void BOARD_InitBootPins(void) -{ - BOARD_InitPins(); -} - -/* clang-format off */ -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitPins: -- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} -- pin_list: - - {pin_num: '51', peripheral: LPUART0, signal: RX, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/I3C0_PUR, slew_rate: fast, open_drain: disable, - drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal} - - {pin_num: '52', peripheral: LPUART0, signal: TX, pin_signal: P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/CMP0_OUT/CMP1_IN1, slew_rate: fast, open_drain: disable, - drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ -/* clang-format on */ - -/* FUNCTION ************************************************************************************************************ - * - * Function Name : BOARD_InitPins - * Description : Configures pin routing and optionally pin electrical features. - * - * END ****************************************************************************************************************/ -void BOARD_InitPins(void) -{ - CLOCK_EnableClock(kCLOCK_GateGPIO3); - /* Write to PORT3: Peripheral clock is enabled */ - CLOCK_EnableClock(kCLOCK_GatePORT3); - /* GPIO3 peripheral is released from reset */ - RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn); - /* PORT3 peripheral is released from reset */ - RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn); - - - /* Write to PORT0: Peripheral clock is enabled */ - CLOCK_EnableClock(kCLOCK_GatePORT0); - /* LPUART0 peripheral is released from reset */ - RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn); - /* PORT0 peripheral is released from reset */ - RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); - - const port_pin_config_t port0_2_pin51_config = {/* Internal pull-up resistor is enabled */ - kPORT_PullUp, - /* Low internal pull resistor value is selected. */ - kPORT_LowPullResistor, - /* Fast slew rate is configured */ - kPORT_FastSlewRate, - /* Passive input filter is disabled */ - kPORT_PassiveFilterDisable, - /* Open drain output is disabled */ - kPORT_OpenDrainDisable, - /* Low drive strength is configured */ - kPORT_LowDriveStrength, - /* Normal drive strength is configured */ - kPORT_NormalDriveStrength, - /* Pin is configured as LPUART0_RXD */ - kPORT_MuxAlt2, - /* Digital input enabled */ - kPORT_InputBufferEnable, - /* Digital input is not inverted */ - kPORT_InputNormal, - /* Pin Control Register fields [15:0] are not locked */ - kPORT_UnlockRegister}; - /* PORT0_2 (pin 51) is configured as LPUART0_RXD */ - PORT_SetPinConfig(PORT0, 2U, &port0_2_pin51_config); - - const port_pin_config_t port0_3_pin52_config = {/* Internal pull-up resistor is enabled */ - kPORT_PullUp, - /* Low internal pull resistor value is selected. */ - kPORT_LowPullResistor, - /* Fast slew rate is configured */ - kPORT_FastSlewRate, - /* Passive input filter is disabled */ - kPORT_PassiveFilterDisable, - /* Open drain output is disabled */ - kPORT_OpenDrainDisable, - /* Low drive strength is configured */ - kPORT_LowDriveStrength, - /* Normal drive strength is configured */ - kPORT_NormalDriveStrength, - /* Pin is configured as LPUART0_TXD */ - kPORT_MuxAlt2, - /* Digital input enabled */ - kPORT_InputBufferEnable, - /* Digital input is not inverted */ - kPORT_InputNormal, - /* Pin Control Register fields [15:0] are not locked */ - kPORT_UnlockRegister}; - /* PORT0_3 (pin 52) is configured as LPUART0_TXD */ - PORT_SetPinConfig(PORT0, 3U, &port0_3_pin52_config); -} -/*********************************************************************************************************************** - * EOF - **********************************************************************************************************************/ diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h b/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h deleted file mode 100644 index 2c0e617a5..000000000 --- a/hw/bsp/mcx/boards/frdm_mcxa153/pin_mux.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2023 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -#ifndef _PIN_MUX_H_ -#define _PIN_MUX_H_ - -/*! - * @addtogroup pin_mux - * @{ - */ - -/*********************************************************************************************************************** - * API - **********************************************************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Calls initialization functions. - * - */ -void BOARD_InitBootPins(void); - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitPins(void); - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ -#endif /* _PIN_MUX_H_ */ - -/*********************************************************************************************************************** - * EOF - **********************************************************************************************************************/ diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c index 2dfefeb92..e1accf941 100644 --- a/hw/bsp/mcx/family.c +++ b/hw/bsp/mcx/family.c @@ -61,14 +61,9 @@ void USB0_IRQHandler(void) { void board_init(void) { - BOARD_InitPins(); - + BOARD_InitBootPins(); BOARD_InitBootClocks(); - #ifdef XTAL0_CLK_HZ - CLOCK_SetupExtClocking(XTAL0_CLK_HZ); - #endif - #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk index a16f4b6c0..4321e654a 100644 --- a/hw/bsp/mcx/family.mk +++ b/hw/bsp/mcx/family.mk @@ -11,7 +11,7 @@ CFLAGS += \ -DBOARD_TUD_RHPORT=$(PORT) \ # mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration +CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration -Wno-error=redundant-decls LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs @@ -56,12 +56,9 @@ INC += \ $(TOP)/$(SDK_DIR)/drivers/ \ $(TOP)/$(SDK_DIR)/drivers/lpuart \ $(TOP)/$(SDK_DIR)/drivers/lpflexcomm \ - $(TOP)/$(SDK_DIR)/drivers/common\ - $(TOP)/$(SDK_DIR)/drivers/gpio\ - $(TOP)/$(SDK_DIR)/drivers/port\ - $(TOP)/hw/bsp/mcx/drivers/spc - - - + $(TOP)/$(SDK_DIR)/drivers/common\ + $(TOP)/$(SDK_DIR)/drivers/gpio\ + $(TOP)/$(SDK_DIR)/drivers/port\ + $(TOP)/hw/bsp/mcx/drivers/spc SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 05ae6929c..002cd3a0e 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -543,6 +543,10 @@ #define TUP_RHPORT_HIGHSPEED CFG_TUD_WCH_USBIP_USBHS #define TUP_DCD_ENDPOINT_MAX (CFG_TUD_WCH_USBIP_USBHS ? 16 : 8) + #if CFG_TUD_WCH_USBIP_USBHS + #define TUP_DCD_EDPT_CLOSE_API + #endif + #elif TU_CHECK_MCU(OPT_MCU_CH32V103) #define TUP_USBIP_WCH_USBFS @@ -590,6 +594,10 @@ #define TUP_RHPORT_HIGHSPEED CFG_TUD_WCH_USBIP_USBHS #define TUP_DCD_ENDPOINT_MAX (CFG_TUD_WCH_USBIP_USBHS ? 16 : 8) + #if CFG_TUD_WCH_USBIP_USBHS + #define TUP_DCD_EDPT_CLOSE_API + #endif + //--------------------------------------------------------------------+ // Analog Devices //--------------------------------------------------------------------+ @@ -681,8 +689,7 @@ #define TU_ATTR_FAST_FUNC #endif -#if defined(TUP_USBIP_CHIPIDEA_FS) || defined(TUP_USBIP_IP3511) || defined(TUP_USBIP_RUSB2) || \ - (defined(TUP_USBIP_WCH_USBFS) && CFG_TUD_WCH_USBIP_USBFS) +#if defined(TUP_USBIP_IP3511) || defined(TUP_USBIP_RUSB2) #define TUP_DCD_EDPT_CLOSE_API #endif diff --git a/src/portable/chipidea/ci_fs/dcd_ci_fs.c b/src/portable/chipidea/ci_fs/dcd_ci_fs.c index 8b5c42aa2..40ad4cf82 100644 --- a/src/portable/chipidea/ci_fs/dcd_ci_fs.c +++ b/src/portable/chipidea/ci_fs/dcd_ci_fs.c @@ -344,24 +344,21 @@ void dcd_sof_enable(uint8_t rhport, bool en) //--------------------------------------------------------------------+ // Endpoint API //--------------------------------------------------------------------+ -bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) -{ - (void) rhport; - - const unsigned ep_addr = ep_desc->bEndpointAddress; - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned dir = tu_edpt_dir(ep_addr); - const unsigned xfer = ep_desc->bmAttributes.xfer; - endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; - const unsigned odd = ep->odd; - buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; +static bool edpt_open(uint8_t rhport, uint8_t ep_addr, uint16_t max_packet_size, tusb_xfer_type_t xfer) { + (void)rhport; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir = tu_edpt_dir(ep_addr); + endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; + const unsigned odd = ep->odd; + buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; /* No support for control transfer */ TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL)); - ep->max_packet_size = tu_edpt_packet_size(ep_desc); + ep->max_packet_size = max_packet_size; + unsigned val = USB_ENDPT_EPCTLDIS_MASK; - val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0; + val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK : 0; val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK; CI_REG->EP[epn].CTL |= val; @@ -375,8 +372,27 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) return true; } -void dcd_edpt_close_all(uint8_t rhport) -{ +bool dcd_edpt_open(uint8_t rhport, const tusb_desc_endpoint_t *ep_desc) { + return edpt_open(rhport, ep_desc->bEndpointAddress, tu_edpt_packet_size(ep_desc), ep_desc->bmAttributes.xfer); +} + +bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { + return edpt_open(rhport, ep_addr, largest_packet_size, TUSB_XFER_ISOCHRONOUS); +} + +bool dcd_edpt_iso_activate(uint8_t rhport, const tusb_desc_endpoint_t *ep_desc) { + const unsigned epn = tu_edpt_number(ep_desc->bEndpointAddress); + const unsigned dir = tu_edpt_dir(ep_desc->bEndpointAddress); + endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; + + dcd_int_disable(rhport); + ep->max_packet_size = tu_edpt_packet_size(ep_desc); + dcd_int_enable(rhport); + + return true; +} + +void dcd_edpt_close_all(uint8_t rhport) { dcd_int_disable(rhport); for (unsigned i = 1; i < 16; ++i) { @@ -399,43 +415,6 @@ void dcd_edpt_close_all(uint8_t rhport) } } -#ifdef TUP_DCD_EDPT_CLOSE_API -void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) -{ - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned dir = tu_edpt_dir(ep_addr); - endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; - buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; - const unsigned msk = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK; - - dcd_int_disable(rhport); - - CI_REG->EP[epn].CTL &= ~msk; - ep->max_packet_size = 0; - ep->length = 0; - ep->remaining = 0; - bd[0].head = 0; - bd[1].head = 0; - - dcd_int_enable(rhport); -} - -#else - -bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { - (void) rhport; - (void) ep_addr; - (void) largest_packet_size; - return false; -} - -bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep) { - (void) rhport; - (void) desc_ep; - return false; -} -#endif - bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) { const unsigned epn = tu_edpt_number(ep_addr); diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index da1c5c888..9edaadf58 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -355,24 +355,21 @@ void dcd_sof_enable(uint8_t rhport, bool en) //--------------------------------------------------------------------+ // Endpoint API //--------------------------------------------------------------------+ -bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) -{ - (void) rhport; +static bool edpt_open(uint8_t rhport, uint8_t ep_addr, uint16_t max_packet_size, tusb_xfer_type_t xfer) { + (void)rhport; - const unsigned ep_addr = ep_desc->bEndpointAddress; - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned dir = tu_edpt_dir(ep_addr); - const unsigned xfer = ep_desc->bmAttributes.xfer; - endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; - const unsigned odd = ep->odd; - buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir = tu_edpt_dir(ep_addr); + endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; + const unsigned odd = ep->odd; + buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; /* No support for control transfer */ TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL)); - ep->max_packet_size = tu_edpt_packet_size(ep_desc); - unsigned val = USB_ENDPT_EPCTLDIS_MASK; - val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0; + ep->max_packet_size = max_packet_size; + unsigned val = USB_ENDPT_EPCTLDIS_MASK; + val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK : 0; val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK; KHCI->ENDPOINT[epn].ENDPT |= val; @@ -386,6 +383,26 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) return true; } +bool dcd_edpt_open(uint8_t rhport, const tusb_desc_endpoint_t *ep_desc) { + return edpt_open(rhport, ep_desc->bEndpointAddress, tu_edpt_packet_size(ep_desc), ep_desc->bmAttributes.xfer); +} + +bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { + return edpt_open(rhport, ep_addr, largest_packet_size, TUSB_XFER_ISOCHRONOUS); +} + +bool dcd_edpt_iso_activate(uint8_t rhport, const tusb_desc_endpoint_t *ep_desc) { + const unsigned epn = tu_edpt_number(ep_desc->bEndpointAddress); + const unsigned dir = tu_edpt_dir(ep_desc->bEndpointAddress); + endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; + + dcd_int_disable(rhport); + ep->max_packet_size = tu_edpt_packet_size(ep_desc); + dcd_int_enable(rhport); + + return true; +} + void dcd_edpt_close_all(uint8_t rhport) { (void) rhport; @@ -408,41 +425,6 @@ void dcd_edpt_close_all(uint8_t rhport) } } -void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) -{ - (void) rhport; - - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned dir = tu_edpt_dir(ep_addr); - endpoint_state_t *ep = &_dcd.endpoint[epn][dir]; - buffer_descriptor_t *bd = _dcd.bdt[epn][dir]; - const unsigned msk = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK; - const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn); - NVIC_DisableIRQ(USB0_IRQn); - KHCI->ENDPOINT[epn].ENDPT &= ~msk; - ep->max_packet_size = 0; - ep->length = 0; - ep->remaining = 0; - bd[0].head = 0; - bd[1].head = 0; - if (ie) NVIC_EnableIRQ(USB0_IRQn); -} - -#if 0 -bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { - (void) rhport; - (void) ep_addr; - (void) largest_packet_size; - return false; -} - -bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep) { - (void) rhport; - (void) desc_ep; - return false; -} - #endif - bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) { (void) rhport; -- cgit v1.3.1 From 1df116adfc70bb6d86f6046b46560d5c42762c28 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 19 Nov 2025 11:56:53 +0700 Subject: clean up --- examples/device/dfu/src/main.c | 99 +++++------ examples/device/dfu/src/usb_descriptors.c | 190 ++++++++++------------ examples/device/dfu_runtime/src/usb_descriptors.c | 58 ++++--- src/class/dfu/dfu_device.c | 12 +- 4 files changed, 173 insertions(+), 186 deletions(-) (limited to 'examples') diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c index 43e0af9a5..77632bf1a 100644 --- a/examples/device/dfu/src/main.c +++ b/examples/device/dfu/src/main.c @@ -23,7 +23,7 @@ * */ - /* +/* * After device is enumerated in dfu mode run the following commands * * To transfer firmware from host to device (best to test with text file) @@ -48,21 +48,18 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTYPES //--------------------------------------------------------------------+ -const char* upload_image[2]= -{ - "Hello world from TinyUSB DFU! - Partition 0", - "Hello world from TinyUSB DFU! - Partition 1" -}; +const char *upload_image[2] = {"Hello world from TinyUSB DFU! - Partition 0", + "Hello world from TinyUSB DFU! - Partition 1"}; /* Blink pattern * - 250 ms : device not mounted * - 1000 ms : device mounted * - 2500 ms : device is suspended */ -enum { +enum { BLINK_NOT_MOUNTED = 250, - BLINK_MOUNTED = 1000, - BLINK_SUSPENDED = 2500, + BLINK_MOUNTED = 1000, + BLINK_SUSPENDED = 2500, }; static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED; @@ -70,21 +67,16 @@ static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED; void led_blinking_task(void); /*------------- MAIN -------------*/ -int main(void) -{ +int main(void) { board_init(); // init device stack on configured roothub port - tusb_rhport_init_t dev_init = { - .role = TUSB_ROLE_DEVICE, - .speed = TUSB_SPEED_AUTO - }; + tusb_rhport_init_t dev_init = {.role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO}; tusb_init(BOARD_TUD_RHPORT, &dev_init); board_init_after_tusb(); - while (1) - { + while (1) { tud_task(); // tinyusb device task led_blinking_task(); } @@ -95,29 +87,25 @@ int main(void) //--------------------------------------------------------------------+ // Invoked when device is mounted -void tud_mount_cb(void) -{ +void tud_mount_cb(void) { blink_interval_ms = BLINK_MOUNTED; } // Invoked when device is unmounted -void tud_umount_cb(void) -{ +void tud_umount_cb(void) { blink_interval_ms = BLINK_NOT_MOUNTED; } // Invoked when usb bus is suspended // remote_wakeup_en : if host allow us to perform remote wakeup // Within 7ms, device must draw an average of current less than 2.5 mA from bus -void tud_suspend_cb(bool remote_wakeup_en) -{ - (void) remote_wakeup_en; +void tud_suspend_cb(bool remote_wakeup_en) { + (void)remote_wakeup_en; blink_interval_ms = BLINK_SUSPENDED; } // Invoked when usb bus is resumed -void tud_resume_cb(void) -{ +void tud_resume_cb(void) { blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED; } @@ -129,19 +117,17 @@ void tud_resume_cb(void) // Invoked right before tud_dfu_download_cb() (state=DFU_DNBUSY) or tud_dfu_manifest_cb() (state=DFU_MANIFEST) // Application return timeout in milliseconds (bwPollTimeout) for the next download/manifest operation. // During this period, USB host won't try to communicate with us. -uint32_t tud_dfu_get_timeout_cb(uint8_t alt, uint8_t state) -{ - if ( state == DFU_DNBUSY ) - { +uint32_t tud_dfu_get_timeout_cb(uint8_t alt, uint8_t state) { + if (state == DFU_DNBUSY) { // For this example // - Atl0 Flash is fast : 1 ms // - Alt1 EEPROM is slow: 100 ms return (alt == 0) ? 1 : 100; - } - else if (state == DFU_MANIFEST) - { + } else if (state == DFU_MANIFEST) { // since we don't buffer entire image and do any flashing in manifest stage return 0; + } else { + // nothing to do } return 0; @@ -150,15 +136,13 @@ uint32_t tud_dfu_get_timeout_cb(uint8_t alt, uint8_t state) // Invoked when received DFU_DNLOAD (wLength>0) following by DFU_GETSTATUS (state=DFU_DNBUSY) requests // This callback could be returned before flashing op is complete (async). // Once finished flashing, application must call tud_dfu_finish_flashing() -void tud_dfu_download_cb(uint8_t alt, uint16_t block_num, uint8_t const* data, uint16_t length) -{ - (void) alt; - (void) block_num; +void tud_dfu_download_cb(uint8_t alt, uint16_t block_num, const uint8_t *data, uint16_t length) { + (void)alt; + (void)block_num; //printf("\r\nReceived Alt %u BlockNum %u of length %u\r\n", alt, wBlockNum, length); - for(uint16_t i=0; ibmRequestType_bit.type) { - case TUSB_REQ_TYPE_VENDOR: - switch (request->bRequest) { - case VENDOR_REQUEST_MICROSOFT: - if (request->wIndex == 7) { - return tud_control_xfer(rhport, request, (void *) (uintptr_t) desc_ms_os_20, MS_OS_20_DESC_LEN); - } else { - return false; - } - - default: - break; - } - break; + if (stage != CONTROL_STAGE_SETUP) { + return true; + } - default: - break; + if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_VENDOR) { + if (request->bRequest == VENDOR_REQUEST_MICROSOFT) { + if (request->wIndex == 7) { + return tud_control_xfer(rhport, request, (void *)(uintptr_t)desc_ms_os_20, MS_OS_20_DESC_LEN); + } else { + return false; + } + } } // stall unknown request @@ -208,21 +196,21 @@ enum { }; // array of pointer to string descriptors -static char const *string_desc_arr[] = { - (const char[]){0x09, 0x04},// 0: is supported language is English (0x0409) - "TinyUSB", // 1: Manufacturer - "TinyUSB Device", // 2: Product - NULL, // 3: Serials will use unique ID if possible - "FLASH", // 4: DFU Partition 1 - "EEPROM", // 5: DFU Partition 2 +static const char *string_desc_arr[] = { + (const char[]){0x09, 0x04}, // 0: is supported language is English (0x0409) + "TinyUSB", // 1: Manufacturer + "TinyUSB Device", // 2: Product + NULL, // 3: Serials will use unique ID if possible + "FLASH", // 4: DFU Partition 1 + "EEPROM", // 5: DFU Partition 2 }; static uint16_t _desc_str[32 + 1]; // Invoked when received GET STRING DESCRIPTOR request // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete -uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { - (void) langid; +const uint16_t *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { + (void)langid; size_t chr_count; switch (index) { @@ -246,8 +234,8 @@ uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { const char *str = string_desc_arr[index]; // Cap at max char - chr_count = strlen(str); - size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type + chr_count = strlen(str); + const size_t max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type if (chr_count > max_count) { chr_count = max_count; } @@ -260,7 +248,7 @@ uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { } // first byte is length (including header), second byte is string type - _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2)); + _desc_str[0] = (uint16_t)((TUSB_DESC_STRING << 8) | (2 * chr_count + 2)); return _desc_str; } diff --git a/examples/device/dfu_runtime/src/usb_descriptors.c b/examples/device/dfu_runtime/src/usb_descriptors.c index 6a0a46b94..8fa078da2 100644 --- a/examples/device/dfu_runtime/src/usb_descriptors.c +++ b/examples/device/dfu_runtime/src/usb_descriptors.c @@ -32,9 +32,8 @@ * Auto ProductID layout's Bitmap: * [MSB] HID | MSC | CDC [LSB] */ -#define PID_MAP(itf, n) ((CFG_TUD_##itf) ? (1 << (n)) : 0) -#define USB_PID (0x4000 | PID_MAP(CDC, 0) | PID_MAP(MSC, 1) | PID_MAP(HID, 2) | \ - PID_MAP(MIDI, 3) | PID_MAP(VENDOR, 4) ) +#define PID_MAP(itf, n) ((CFG_TUD_##itf) ? (1 << (n)) : 0) +#define USB_PID (0x4000 | PID_MAP(CDC, 0) | PID_MAP(MSC, 1) | PID_MAP(HID, 2) | PID_MAP(MIDI, 3) | PID_MAP(VENDOR, 4)) //--------------------------------------------------------------------+ // Device Descriptors @@ -108,33 +107,30 @@ uint8_t const *tud_descriptor_configuration_cb(uint8_t index) { //--------------------------------------------------------------------+ /* Microsoft OS 2.0 registry property descriptor -Per MS requirements https://msdn.microsoft.com/en-us/library/windows/hardware/hh450799(v=vs.85).aspx -device should create DeviceInterfaceGUIDs. It can be done by driver and -in case of real PnP solution device should expose MS "Microsoft OS 2.0 -registry property descriptor". Such descriptor can insert any record -into Windows registry per device/configuration/interface. In our case it -will insert "DeviceInterfaceGUIDs" multistring property. -GUID is freshly generated and should be OK to use. -https://developers.google.com/web/fundamentals/native-hardware/build-for-webusb/ -(Section Microsoft OS compatibility descriptors) + Per MS requirements https://msdn.microsoft.com/en-us/library/windows/hardware/hh450799(v=vs.85).aspx + device should create DeviceInterfaceGUIDs. It can be done by driver and + in case of real PnP solution device should expose MS "Microsoft OS 2.0 + registry property descriptor". Such descriptor can insert any record + into Windows registry per device/configuration/interface. In our case it + will insert "DeviceInterfaceGUIDs" multistring property. + GUID is freshly generated and should be OK to use. + https://developers.google.com/web/fundamentals/native-hardware/build-for-webusb/ + (Section Microsoft OS compatibility descriptors) */ #define BOS_TOTAL_LEN (TUD_BOS_DESC_LEN + TUD_BOS_MICROSOFT_OS_DESC_LEN) - #define MS_OS_20_DESC_LEN 0xA2 - #define VENDOR_REQUEST_MICROSOFT 1 // BOS Descriptor is required for webUSB -uint8_t const desc_bos[] = { - // total length, number of device caps - TUD_BOS_DESCRIPTOR(BOS_TOTAL_LEN, 1), +const uint8_t desc_bos[] = { + // total length, number of device caps + TUD_BOS_DESCRIPTOR(BOS_TOTAL_LEN, 1), - // Microsoft OS 2.0 descriptor - TUD_BOS_MS_OS_20_DESCRIPTOR(MS_OS_20_DESC_LEN, 1) -}; + // Microsoft OS 2.0 descriptor + TUD_BOS_MS_OS_20_DESCRIPTOR(MS_OS_20_DESC_LEN, 1)}; -uint8_t const *tud_descriptor_bos_cb(void) { +const uint8_t *tud_descriptor_bos_cb(void) { return desc_bos; } @@ -170,6 +166,16 @@ bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_requ return true; } + if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_VENDOR) { + if (request->bRequest == VENDOR_REQUEST_MICROSOFT) { + if (request->wIndex == 7) { + return tud_control_xfer(rhport, request, (void *)(uintptr_t)desc_ms_os_20, MS_OS_20_DESC_LEN); + } else { + return false; + } + } + } + switch (request->bmRequestType_bit.type) { case TUSB_REQ_TYPE_VENDOR: switch (request->bRequest) { @@ -218,8 +224,8 @@ static uint16_t _desc_str[32 + 1]; // Invoked when received GET STRING DESCRIPTOR request // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete -uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { - (void) langid; +const uint16_t *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { + (void)langid; size_t chr_count; switch (index) { @@ -243,8 +249,8 @@ uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { const char *str = string_desc_arr[index]; // Cap at max char - chr_count = strlen(str); - size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type + chr_count = strlen(str); + const size_t max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type if (chr_count > max_count) { chr_count = max_count; } @@ -257,7 +263,7 @@ uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { } // first byte is length (including header), second byte is string type - _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2)); + _desc_str[0] = (uint16_t)((TUSB_DESC_STRING << 8) | (2 * chr_count + 2)); return _desc_str; } diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c index 24b037ebb..ffe5941e8 100644 --- a/src/class/dfu/dfu_device.c +++ b/src/class/dfu/dfu_device.c @@ -251,6 +251,8 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control tud_control_status(rhport, request); } else if (stage == CONTROL_STAGE_ACK) { tud_dfu_detach_cb(); + } else { + // nothing to do } break; @@ -273,6 +275,8 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control tud_control_status(rhport, request); } else if (stage == CONTROL_STAGE_ACK) { tud_dfu_abort_cb(_dfu_ctx.alt); + } else { + // nothing to do } break; @@ -301,7 +305,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control _dfu_ctx.block = request->wValue; _dfu_ctx.length = request->wLength; - if (request->wLength) { + if (request->wLength > 0) { // Download with payload -> transition to DOWNLOAD SYNC _dfu_ctx.state = DFU_DNLOAD_SYNC; return tud_control_xfer(rhport, request, _transfer_buf, request->wLength); @@ -350,6 +354,8 @@ void tud_dfu_finish_flashing(uint8_t status) { _dfu_ctx.state = (_dfu_ctx.attrs & DFU_ATTR_MANIFESTATION_TOLERANT) ? DFU_MANIFEST_SYNC : DFU_MANIFEST_WAIT_RESET; + } else { + // nothing to do } } else { // failed while flashing, move to dfuError @@ -380,6 +386,8 @@ static bool process_download_get_status(uint8_t rhport, uint8_t stage, const tus } else { _dfu_ctx.state = DFU_DNLOAD_IDLE; } + } else { + // nothing to do } return true; @@ -407,6 +415,8 @@ static bool process_manifest_get_status(uint8_t rhport, uint8_t stage, const tus } else { _dfu_ctx.state = DFU_IDLE; } + } else { + // nothing to do } return true; -- cgit v1.3.1 From 4b92d325beb0483584004b5005ab67d39f06a45d Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 19 Nov 2025 15:07:50 +0700 Subject: device_info wait 100ms for host's uart, needed for hil test --- examples/host/device_info/src/main.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'examples') diff --git a/examples/host/device_info/src/main.c b/examples/host/device_info/src/main.c index f71702efc..5b914a2ee 100644 --- a/examples/host/device_info/src/main.c +++ b/examples/host/device_info/src/main.c @@ -99,6 +99,7 @@ int main(void) { #if CFG_TUSB_OS == OPT_OS_FREERTOS init_freertos_task(); #else + board_delay(100); // wait for uart to be ready init_tinyusb(); while (1) { tuh_task(); // tinyusb host task @@ -289,6 +290,7 @@ void app_main(void) { void usb_host_task(void *param) { (void) param; + board_delay(100); // wait for uart to be ready init_tinyusb(); while (1) { tuh_task(); -- cgit v1.3.1