From 5e437ee1861363e6b02facc5ab814abd67173680 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 22 Oct 2021 15:37:34 +0700
Subject: pi cm4 enumerated as full speed device

---
 examples/device/cdc_msc/src/tusb_config.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'examples')

diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h
index bf6af06bc..a3802f536 100644
--- a/examples/device/cdc_msc/src/tusb_config.h
+++ b/examples/device/cdc_msc/src/tusb_config.h
@@ -48,7 +48,8 @@
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
   #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X)
+       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X || \
+       CFG_TUSB_MCU == OPT_MCU_BCM2711)
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
-- 
cgit v1.3.1


From 4ccf60954d184c0530daf800090bd7103aacee86 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 25 Oct 2021 15:51:41 +0700
Subject: moving esp32s2 to dwc2, abstract dwc2_set_turnaround()

---
 .../device/cdc_msc_freertos/src/CMakeLists.txt     |  2 +-
 hw/bsp/gd32vf103/family.mk                         |  3 +-
 src/device/dcd_attr.h                              | 16 ++--
 src/portable/synopsys/dwc2/dcd_dwc2.c              | 98 ++++++----------------
 src/portable/synopsys/dwc2/dwc2_esp32.h            | 82 ++++++++++++++++++
 src/portable/synopsys/dwc2/dwc2_gd32.h             | 37 ++++++--
 src/portable/synopsys/dwc2/dwc2_stm32.h            | 83 +++++++++++++++---
 src/tusb_option.h                                  |  2 +-
 8 files changed, 222 insertions(+), 101 deletions(-)
 create mode 100644 src/portable/synopsys/dwc2/dwc2_esp32.h

(limited to 'examples')

diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
index 07fc4df89..93ae0686a 100644
--- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
@@ -27,5 +27,5 @@ target_sources(${COMPONENT_TARGET} PUBLIC
   "${TOP}/src/class/net/ncm_device.c"
   "${TOP}/src/class/usbtmc/usbtmc_device.c"
   "${TOP}/src/class/vendor/vendor_device.c"
-  "${TOP}/src/portable/espressif/esp32sx/dcd_esp32sx.c"
+  "${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c"
 )
diff --git a/hw/bsp/gd32vf103/family.mk b/hw/bsp/gd32vf103/family.mk
index 4de23ac17..49bacdf1b 100644
--- a/hw/bsp/gd32vf103/family.mk
+++ b/hw/bsp/gd32vf103/family.mk
@@ -28,8 +28,7 @@ CFLAGS += \
 	-mstrict-align \
 	-nostdlib -nostartfiles \
 	-DCFG_TUSB_MCU=OPT_MCU_GD32VF103 \
-	-DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP \
-	-DGD32VF103 
+	-DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 3690985c6..ddec481a8 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -36,13 +36,13 @@
 // - PORT_HIGHSPEED: mask to indicate which port support highspeed mode, bit0 for port0 and so on.
 
 //------------- NXP -------------//
-#if   TU_CHECK_MCU(LPC11UXX) || TU_CHECK_MCU(LPC13XX) || TU_CHECK_MCU(LPC15XX)
+#if   TU_CHECK_MCU(LPC11UXX, LPC13XX, LPC15XX)
   #define DCD_ATTR_ENDPOINT_MAX   5
 
-#elif TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX)
+#elif TU_CHECK_MCU(LPC175X_6X, LPC177X_8X, LPC40XX)
   #define DCD_ATTR_ENDPOINT_MAX   16
 
-#elif TU_CHECK_MCU(LPC18XX) || TU_CHECK_MCU(LPC43XX)
+#elif TU_CHECK_MCU(LPC18XX, LPC43XX)
   // TODO USB0 has 6, USB1 has 4
   #define DCD_ATTR_ENDPOINT_MAX   6
 
@@ -60,7 +60,7 @@
 #elif TU_CHECK_MCU(MIMXRT10XX)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
-#elif TU_CHECK_MCU(MKL25ZXX) || TU_CHECK_MCU(K32L2BXX)
+#elif TU_CHECK_MCU(MKL25ZXX, K32L2BXX)
   #define DCD_ATTR_ENDPOINT_MAX   16
 
 #elif TU_CHECK_MCU(MM32F327X)
@@ -72,8 +72,8 @@
   #define DCD_ATTR_ENDPOINT_MAX   9
 
 //------------- Microchip -------------//
-#elif TU_CHECK_MCU(SAMD21) || TU_CHECK_MCU(SAMD51) || TU_CHECK_MCU(SAME5X) || \
-      TU_CHECK_MCU(SAMD11) || TU_CHECK_MCU(SAML21) || TU_CHECK_MCU(SAML22)
+#elif TU_CHECK_MCU(SAMD21, SAMD51, SAME5X) || \
+      TU_CHECK_MCU(SAMD11, SAML21, SAML22)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
 #elif TU_CHECK_MCU(SAMG)
@@ -119,7 +119,7 @@
   #define DCD_ATTR_ENDPOINT_MAX   9
   #define DCD_ATTR_DWC2_STM32
 
-#elif TU_CHECK_MCU(STM32L0) || TU_CHECK_MCU(STM32L1)
+#elif TU_CHECK_MCU(STM32L0, STM32L1)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
 #elif TU_CHECK_MCU(STM32L4)
@@ -157,7 +157,7 @@
   #define DCD_ATTR_ENDPOINT_MAX   12
 
 //------------- Espressif -------------//
-#elif TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+#elif TU_CHECK_MCU(ESP32S2, ESP32S3)
   #define DCD_ATTR_ENDPOINT_MAX   6
 
 //------------- Dialog -------------//
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 367fc7b56..c3773fb8b 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -30,13 +30,16 @@
 #include "tusb_option.h"
 #include "device/dcd_attr.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && (defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(GD32VF103))
+#if TUSB_OPT_DEVICE_ENABLED && \
+    ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(ESP32S2, ESP32S3, GD32VF103) )
 
 #include "device/dcd.h"
 #include "dwc2_type.h"
 
 #if defined(DCD_ATTR_DWC2_STM32)
   #include "dwc2_stm32.h"
+#elif TU_CHECK_MCU(ESP32S2, ESP32S3)
+  #include "dwc2_esp32.h"
 #elif TU_CHECK_MCU(GD32VF103)
   #include "dwc2_gd32.h"
 #else
@@ -72,7 +75,7 @@ typedef struct {
 
 typedef volatile uint32_t * usb_fifo_t;
 
-xfer_ctl_t xfer_status[EP_MAX][2];
+xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
 #define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
 
 // EP0 transfers are limited to 1 packet - larger sizes has to be split
@@ -85,7 +88,7 @@ static bool _out_ep_closed;                       // Flag to check if RX FIFO si
 // Calculate the RX FIFO size according to recommendations from reference manual
 static inline uint16_t calc_rx_ff_size(uint16_t ep_size)
 {
-  return 15 + 2*(ep_size/4) + 2*EP_MAX;
+  return 15 + 2*(ep_size/4) + 2*DWC2_EP_MAX;
 }
 
 static void update_grxfsiz(uint8_t rhport)
@@ -96,7 +99,7 @@ static void update_grxfsiz(uint8_t rhport)
 
   // Determine largest EP size for RX FIFO
   uint16_t max_epsize = 0;
-  for (uint8_t epnum = 0; epnum < EP_MAX; epnum++)
+  for (uint8_t epnum = 0; epnum < DWC2_EP_MAX; epnum++)
   {
     max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size);
   }
@@ -122,7 +125,7 @@ static void bus_reset(uint8_t rhport)
   dev->DCFG &= ~DCFG_DAD_Msk;
 
   // 1. NAK for all OUT endpoints
-  for(uint8_t n = 0; n < EP_MAX; n++) {
+  for(uint8_t n = 0; n < DWC2_EP_MAX; n++) {
     out_ep[n].DOEPCTL |= DOEPCTL_SNAK;
   }
 
@@ -171,11 +174,11 @@ static void bus_reset(uint8_t rhport)
   //   - 2 for each used OUT endpoint
   //
   //   Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum
-  //   - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x  16 + 2 x EP_MAX = 47  + 2 x EP_MAX
-  //   - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x EP_MAX = 271 + 2 x EP_MAX
+  //   - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x  16 + 2 x DWC2_EP_MAX = 47  + 2 x DWC2_EP_MAX
+  //   - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x DWC2_EP_MAX = 271 + 2 x DWC2_EP_MAX
   //
   //   NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge
-  //   of the overall picture yet. We will use the worst scenario: largest possible + EP_MAX
+  //   of the overall picture yet. We will use the worst scenario: largest possible + DWC2_EP_MAX
   //
   //   For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
   //   are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended.  Maybe provide a macro for application to
@@ -186,7 +189,7 @@ static void bus_reset(uint8_t rhport)
   _allocated_fifo_words_tx = 16;
 
   // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
-  core->DIEPTXF0_HNPTXFSIZ = (16 << TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+  core->DIEPTXF0_HNPTXFSIZ = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
   // Fixed control EP0 size to 64 bytes
   in_ep[0].DIEPCTL &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
@@ -197,47 +200,6 @@ static void bus_reset(uint8_t rhport)
   core->GINTMSK |= GINTMSK_OEPINT | GINTMSK_IEPINT;
 }
 
-// Set turn-around timeout according to link speed
-extern uint32_t SystemCoreClock;
-static void set_turnaround(dwc2_core_t * core, tusb_speed_t speed)
-{
-  core->GUSBCFG &= ~GUSBCFG_TRDT;
-
-  if ( speed == TUSB_SPEED_HIGH )
-  {
-    // Use fixed 0x09 for Highspeed
-    core->GUSBCFG |= (0x09 << GUSBCFG_TRDT_Pos);
-  }
-  else
-  {
-    // Turnaround timeout depends on the MCU clock
-    uint32_t turnaround;
-
-    if ( SystemCoreClock >= 32000000U )
-      turnaround = 0x6U;
-    else if ( SystemCoreClock >= 27500000U )
-      turnaround = 0x7U;
-    else if ( SystemCoreClock >= 24000000U )
-      turnaround = 0x8U;
-    else if ( SystemCoreClock >= 21800000U )
-      turnaround = 0x9U;
-    else if ( SystemCoreClock >= 20000000U )
-      turnaround = 0xAU;
-    else if ( SystemCoreClock >= 18500000U )
-      turnaround = 0xBU;
-    else if ( SystemCoreClock >= 17200000U )
-      turnaround = 0xCU;
-    else if ( SystemCoreClock >= 16000000U )
-      turnaround = 0xDU;
-    else if ( SystemCoreClock >= 15000000U )
-      turnaround = 0xEU;
-    else
-      turnaround = 0xFU;
-
-    // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz
-    core->GUSBCFG |= (turnaround << GUSBCFG_TRDT_Pos);
-  }
-}
 
 static tusb_speed_t get_speed(uint8_t rhport)
 {
@@ -368,6 +330,8 @@ void dcd_init (uint8_t rhport)
   // peripheral in each Reference Manual.
   dwc2_core_t * core = CORE_REG(rhport);
 
+  // check GSNPSID
+
   // No HNP/SRP (no OTG support), program timeout later.
   if ( rhport == 1 )
   {
@@ -422,7 +386,7 @@ void dcd_init (uint8_t rhport)
 
   // If USB host misbehaves during status portion of control xfer
   // (non zero-length packet), send STALL back and discard.
-  dev->DCFG |=  DCFG_NZLSOHSK;
+  dev->DCFG |= DCFG_NZLSOHSK;
 
   set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL);
 
@@ -457,16 +421,6 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 }
 
-static void remote_wakeup_delay(void)
-{
-  // try to delay for 1 ms
-  uint32_t count = SystemCoreClock / 1000;
-  while ( count-- )
-  {
-    __NOP();
-  }
-}
-
 void dcd_remote_wakeup(uint8_t rhport)
 {
   (void) rhport;
@@ -482,7 +436,7 @@ void dcd_remote_wakeup(uint8_t rhport)
   core->GINTMSK |= GINTMSK_SOFM;
 
   // Per specs: remote wakeup signal bit must be clear within 1-15ms
-  remote_wakeup_delay();
+  dwc2_remote_wakeup_delay();
 
   dev->DCTL &= ~DCTL_RWUSIG;
 }
@@ -518,7 +472,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
   uint8_t const dir   = tu_edpt_dir(desc_edpt->bEndpointAddress);
 
-  TU_ASSERT(epnum < EP_MAX);
+  TU_ASSERT(epnum < DWC2_EP_MAX);
 
   xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
   xfer->max_size = tu_edpt_packet_size(desc_edpt);
@@ -534,7 +488,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     // If size_rx needs to be extended check if possible and if so enlarge it
     if (core->GRXFSIZ < sz)
     {
-      TU_ASSERT(sz + _allocated_fifo_words_tx <= EP_FIFO_SIZE/4);
+      TU_ASSERT(sz + _allocated_fifo_words_tx <= DWC2_EP_FIFO_SIZE/4);
 
       // Enlarge RX FIFO
       core->GRXFSIZ = sz;
@@ -571,15 +525,15 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
 
     // Check if free space is available
-    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + core->GRXFSIZ <= EP_FIFO_SIZE/4);
+    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + core->GRXFSIZ <= DWC2_EP_FIFO_SIZE/4);
 
     _allocated_fifo_words_tx += fifo_size;
 
-    TU_LOG(2, "    Allocated %u bytes at offset %u", fifo_size*4, EP_FIFO_SIZE-_allocated_fifo_words_tx*4);
+    TU_LOG(2, "    Allocated %u bytes at offset %u", fifo_size*4, DWC2_EP_FIFO_SIZE-_allocated_fifo_words_tx*4);
 
     // DIEPTXF starts at FIFO #1.
     // Both TXFD and TXSA are in unit of 32-bit words.
-    core->DIEPTXF[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+    core->DIEPTXF[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
     in_ep[epnum].DIEPCTL |= (1 << DIEPCTL_USBAEP_Pos) |
         (epnum << DIEPCTL_TXFNUM_Pos) |
@@ -606,7 +560,7 @@ void dcd_edpt_close_all (uint8_t rhport)
   // Disable non-control interrupt
   dev->DAINTMSK = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
 
-  for(uint8_t n = 1; n < EP_MAX; n++)
+  for(uint8_t n = 1; n < DWC2_EP_MAX; n++)
   {
     // disable OUT endpoint
     out_ep[n].DOEPCTL = 0;
@@ -756,7 +710,7 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
     uint16_t const fifo_size = (core->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos;
     uint16_t const fifo_start = (core->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos;
     // For now only the last opened endpoint can be closed without fuss.
-    TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
+    TU_ASSERT(fifo_start == DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
     _allocated_fifo_words_tx -= fifo_size;
   }
   else
@@ -920,7 +874,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
 static void handle_epout_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epout_t * out_ep) {
   // DAINT for a given EP clears when DOEPINTx is cleared.
   // OEPINT will be cleared when DAINT's out bits are cleared.
-  for(uint8_t n = 0; n < EP_MAX; n++) {
+  for(uint8_t n = 0; n < DWC2_EP_MAX; n++) {
     xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
 
     if(dev->DAINT & (1 << (DAINT_OEPINT_Pos + n))) {
@@ -949,7 +903,7 @@ static void handle_epout_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epout_t
 static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t * in_ep) {
   // DAINT for a given EP clears when DIEPINTx is cleared.
   // IEPINT will be cleared when DAINT's out bits are cleared.
-  for ( uint8_t n = 0; n < EP_MAX; n++ )
+  for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ )
   {
     xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
 
@@ -1040,7 +994,7 @@ void dcd_int_handler(uint8_t rhport)
 
     tusb_speed_t const speed = get_speed(rhport);
 
-    set_turnaround(core, speed);
+    dwc2_set_turnaround(core, speed);
     dcd_event_bus_reset(rhport, speed, true);
   }
 
diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h
new file mode 100644
index 000000000..5e544673d
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_esp32.h
@@ -0,0 +1,82 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+
+#ifndef _DWC2_ESP32_H_
+#define _DWC2_ESP32_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "esp_intr_alloc.h"
+#include "soc/periph_defs.h"
+//#include "soc/usb_periph.h"
+
+#define DWC2_REG_BASE       0x60080000UL
+#define DWC2_EP_MAX         5             // USB_OUT_EP_NUM
+#define DWC2_EP_FIFO_SIZE   1024
+
+// #define EP_FIFO_NUM 5
+
+static intr_handle_t usb_ih;
+
+static void dcd_int_handler_wrap(void* arg)
+{
+  (void) arg;
+  dcd_int_handler(0);
+}
+
+static inline void dcd_dwc2_int_enable (uint8_t rhport)
+{
+  (void) rhport;
+  esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, dcd_int_handler_wrap, NULL, &usb_ih);
+}
+
+static inline void dcd_dwc2_int_disable (uint8_t rhport)
+{
+  (void) rhport;
+  esp_intr_free(usb_ih);
+}
+
+static inline void dwc2_remote_wakeup_delay(void)
+{
+  vTaskDelay(pdMS_TO_TICKS(1));
+}
+
+static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed)
+{
+  (void) core;
+  (void) speed;
+
+  // keep the reset value
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DWC2_ESP32_H_ */
diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h
index 8fe390fd8..1ad066720 100644
--- a/src/portable/synopsys/dwc2/dwc2_gd32.h
+++ b/src/portable/synopsys/dwc2/dwc2_gd32.h
@@ -28,14 +28,18 @@
 #ifndef DWC2_GD32_H_
 #define DWC2_GD32_H_
 
-// for remote wakeup delay
-#define __NOP()   __asm volatile ("nop")
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
 
 // These numbers are the same for the whole GD32VF103 family.
-#define DWC2_REG_BASE   0x50000000UL
-#define EP_MAX          4
-#define EP_FIFO_SIZE    1280
-#define RHPORT_IRQn     86
+#define DWC2_REG_BASE       0x50000000UL
+#define DWC2_EP_MAX         4
+#define DWC2_EP_FIFO_SIZE   1280
+#define RHPORT_IRQn         86
+
+extern uint32_t SystemCoreClock;
 
 // The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local
 // Interrupt Controller by Nuclei. It is nearly API compatible to the
@@ -66,4 +70,25 @@ static inline void dcd_dwc2_int_disable (uint8_t rhport)
   __eclic_disable_interrupt(RHPORT_IRQn);
 }
 
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_remote_wakeup_delay(void)
+{
+  // try to delay for 1 ms
+  uint32_t count = SystemCoreClock / 1000;
+  while ( count-- ) __asm volatile ("nop");
+}
+
+static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed)
+{
+  (void) core;
+  (void) speed;
+
+  // keep the reset value
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* DWC2_GD32_H_ */
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index d99e5502a..2a6d58e9a 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -24,8 +24,12 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_DWC2_STM32_H_
-#define _TUSB_DWC2_STM32_H_
+#ifndef _DWC2_STM32_H_
+#define _DWC2_STM32_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
 
 // EP_MAX       : Max number of bi-directional endpoints including EP0
 // EP_FIFO_SIZE : Size of dedicated USB SRAM
@@ -71,19 +75,21 @@
 
 // On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS
 #if TUD_OPT_RHPORT == 0
-  #define EP_MAX            EP_MAX_FS
-  #define EP_FIFO_SIZE      EP_FIFO_SIZE_FS
-  #define DWC2_REG_BASE     USB_OTG_FS_PERIPH_BASE
-  #define RHPORT_IRQn       OTG_FS_IRQn
+  #define DWC2_REG_BASE       USB_OTG_FS_PERIPH_BASE
+  #define DWC2_EP_MAX         EP_MAX_FS
+  #define DWC2_EP_FIFO_SIZE   EP_FIFO_SIZE_FS
+  #define RHPORT_IRQn         OTG_FS_IRQn
 
 #else
-  #define EP_MAX            EP_MAX_HS
-  #define EP_FIFO_SIZE      EP_FIFO_SIZE_HS
-  #define DWC2_REG_BASE     USB_OTG_HS_PERIPH_BASE
-  #define RHPORT_IRQn       OTG_HS_IRQn
+  #define DWC2_REG_BASE       USB_OTG_HS_PERIPH_BASE
+  #define DWC2_EP_MAX         EP_MAX_HS
+  #define DWC2_EP_FIFO_SIZE   EP_FIFO_SIZE_HS
+  #define RHPORT_IRQn         OTG_HS_IRQn
 
 #endif
 
+extern uint32_t SystemCoreClock;
+
 TU_ATTR_ALWAYS_INLINE
 static inline void dcd_dwc2_int_enable(uint8_t rhport)
 {
@@ -98,4 +104,59 @@ static inline void dcd_dwc2_int_disable (uint8_t rhport)
   NVIC_DisableIRQ(RHPORT_IRQn);
 }
 
-#endif /* DWC2_STM32_H_ */
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_remote_wakeup_delay(void)
+{
+  // try to delay for 1 ms
+  uint32_t count = SystemCoreClock / 1000;
+  while ( count-- ) __NOP();
+}
+
+// Set turn-around timeout according to link speed
+static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed)
+{
+  core->GUSBCFG &= ~GUSBCFG_TRDT;
+
+  if ( speed == TUSB_SPEED_HIGH )
+  {
+    // Use fixed 0x09 for Highspeed
+    core->GUSBCFG |= (0x09 << GUSBCFG_TRDT_Pos);
+  }
+  else
+  {
+    // Turnaround timeout depends on the MCU clock
+    uint32_t turnaround;
+
+    if ( SystemCoreClock >= 32000000U )
+      turnaround = 0x6U;
+    else if ( SystemCoreClock >= 27500000U )
+      turnaround = 0x7U;
+    else if ( SystemCoreClock >= 24000000U )
+      turnaround = 0x8U;
+    else if ( SystemCoreClock >= 21800000U )
+      turnaround = 0x9U;
+    else if ( SystemCoreClock >= 20000000U )
+      turnaround = 0xAU;
+    else if ( SystemCoreClock >= 18500000U )
+      turnaround = 0xBU;
+    else if ( SystemCoreClock >= 17200000U )
+      turnaround = 0xCU;
+    else if ( SystemCoreClock >= 16000000U )
+      turnaround = 0xDU;
+    else if ( SystemCoreClock >= 15000000U )
+      turnaround = 0xEU;
+    else
+      turnaround = 0xFU;
+
+    // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz
+    core->GUSBCFG |= (turnaround << GUSBCFG_TRDT_Pos);
+  }
+}
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DWC2_STM32_H_ */
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 89d83472b..d707c44c7 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -131,7 +131,7 @@
 // Helper to check if configured MCU is one of listed
 // Apply _TU_CHECK_MCU with || as separator to list of input
 #define _TU_CHECK_MCU(_m)   (CFG_TUSB_MCU == OPT_MCU_##_m)
-#define TU_CHECK_MCU(...)   TU_ARGS_APPLY(_TU_CHECK_MCU, ||, __VA_ARGS__)
+#define TU_CHECK_MCU(...)   (TU_ARGS_APPLY(_TU_CHECK_MCU, ||, __VA_ARGS__))
 
 //--------------------------------------------------------------------+
 // Supported OS
-- 
cgit v1.3.1


From dbd31895bc234ff6d76d3fe736dc613890ab7acb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 25 Oct 2021 17:04:03 +0700
Subject: change usage of TU_CHECK_MCU() to prevent macro conflict

---
 .../audio_4_channel_mic/src/usb_descriptors.c      | 12 ++--
 examples/device/audio_test/src/usb_descriptors.c   |  2 +-
 examples/device/cdc_msc_freertos/src/main.c        |  6 +-
 examples/device/cdc_msc_freertos/src/tusb_config.h |  2 +-
 examples/device/hid_composite_freertos/src/main.c  |  6 +-
 .../hid_composite_freertos/src/tusb_config.h       |  2 +-
 .../device/video_capture/src/usb_descriptors.c     |  4 +-
 src/class/msc/msc_device.c                         |  2 +-
 src/common/tusb_compiler.h                         |  2 +-
 src/device/dcd_attr.h                              | 73 +++++++++++-----------
 src/host/hcd_attr.h                                | 46 +++++++-------
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c      | 11 ++--
 src/portable/synopsys/dwc2/dcd_dwc2.c              |  6 +-
 src/tusb_option.h                                  |  2 +-
 14 files changed, 85 insertions(+), 91 deletions(-)

(limited to 'examples')

diff --git a/examples/device/audio_4_channel_mic/src/usb_descriptors.c b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
index b6a5bd5c2..93ae2ea47 100644
--- a/examples/device/audio_4_channel_mic/src/usb_descriptors.c
+++ b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
@@ -81,12 +81,12 @@ enum
 
 #define CONFIG_TOTAL_LEN    	(TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_MIC_FOUR_CH_DESC_LEN)
 
-#if TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX)
+#if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
   // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
   #define EPNUM_AUDIO   0x03
 
-#elif TU_CHECK_MCU(NRF5X)
+#elif TU_CHECK_MCU(OPT_MCU_NRF5X)
   // nRF5x ISO can only be endpoint 8
   #define EPNUM_AUDIO   0x08
 
@@ -96,11 +96,11 @@ enum
 
 uint8_t const desc_configuration[] =
 {
-    // Interface count, string index, total length, attribute, power in mA
-    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+  // Interface count, string index, total length, attribute, power in mA
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
-    // Interface number, string index, EP Out & EP In address, EP size
-    TUD_AUDIO_MIC_FOUR_CH_DESCRIPTOR(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_stridx*/ 0, /*_nBytesPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, /*_nBitsUsedPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX*8, /*_epin*/ 0x80 | EPNUM_AUDIO, /*_epsize*/ CFG_TUD_AUDIO_EP_SZ_IN)
+  // Interface number, string index, EP Out & EP In address, EP size
+  TUD_AUDIO_MIC_FOUR_CH_DESCRIPTOR(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_stridx*/ 0, /*_nBytesPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, /*_nBitsUsedPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX*8, /*_epin*/ 0x80 | EPNUM_AUDIO, /*_epsize*/ CFG_TUD_AUDIO_EP_SZ_IN)
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/examples/device/audio_test/src/usb_descriptors.c b/examples/device/audio_test/src/usb_descriptors.c
index 348f5eede..09b2a2d45 100644
--- a/examples/device/audio_test/src/usb_descriptors.c
+++ b/examples/device/audio_test/src/usb_descriptors.c
@@ -86,7 +86,7 @@ enum
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
   #define EPNUM_AUDIO   0x03
 
-#elif TU_CHECK_MCU(NRF5X)
+#elif TU_CHECK_MCU(OPT_MCU_NRF5X)
   // nRF5x ISO can only be endpoint 8
   #define EPNUM_AUDIO   0x08
 
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index 65b7fda3b..2d3426f1d 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -30,7 +30,7 @@
 #include "bsp/board.h"
 #include "tusb.h"
 
-#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   // ESP-IDF need "freertos/" prefix in include path.
   // CFG_TUSB_OS_INC_PATH should be defined accordingly.
   #include "freertos/FreeRTOS.h"
@@ -105,14 +105,14 @@ int main(void)
   (void) xTaskCreateStatic( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
 
   // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
-#if !( TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) )
+#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   vTaskStartScheduler();
 #endif
 
   return 0;
 }
 
-#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
 void app_main(void)
 {
   main();
diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h
index d4bbdee48..55e84c62d 100644
--- a/examples/device/cdc_msc_freertos/src/tusb_config.h
+++ b/examples/device/cdc_msc_freertos/src/tusb_config.h
@@ -68,7 +68,7 @@
 #define CFG_TUSB_OS               OPT_OS_FREERTOS
 
 // Espressif IDF requires "freertos/" prefix in include path
-#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   #define CFG_TUSB_OS_INC_PATH    freertos/
 #endif
 
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index b25c71f64..336f5d426 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -31,7 +31,7 @@
 #include "tusb.h"
 #include "usb_descriptors.h"
 
-#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   // ESP-IDF need "freertos/" prefix in include path.
   // CFG_TUSB_OS_INC_PATH should be defined accordingly.
   #include "freertos/FreeRTOS.h"
@@ -105,14 +105,14 @@ int main(void)
   (void) xTaskCreateStatic( hid_task, "hid", HID_STACK_SZIE, NULL, configMAX_PRIORITIES-2, hid_stack, &hid_taskdef);
 
   // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
-#if !( TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) )
+#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   vTaskStartScheduler();
 #endif
 
   return 0;
 }
 
-#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
 void app_main(void)
 {
   main();
diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h
index b061dce3f..062f32ac3 100644
--- a/examples/device/hid_composite_freertos/src/tusb_config.h
+++ b/examples/device/hid_composite_freertos/src/tusb_config.h
@@ -68,7 +68,7 @@
 #define CFG_TUSB_OS               OPT_OS_FREERTOS
 
 // Espressif IDF requires "freertos/" prefix in include path
-#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   #define CFG_TUSB_OS_INC_PATH    freertos/
 #endif
 
diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index 404ffe070..da8ec8e89 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -77,12 +77,12 @@ uint8_t const * tud_descriptor_device_cb(void)
 
 #define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_LEN)
 
-#if TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX)
+#if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
   // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ...
   #define EPNUM_VIDEO_IN    0x83
 
-#elif TU_CHECK_MCU(NRF5X)
+#elif TU_CHECK_MCU(OPT_MCU_NRF5X)
   // nRF5x ISO can only be endpoint 8
   #define EPNUM_VIDEO_IN    0x88
 
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 81522be46..dd490dd68 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -617,7 +617,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       }
     }
 
-    #if TU_CHECK_MCU(CXD56)
+    #if TU_CHECK_MCU(OPT_MCU_CXD56)
     // WORKAROUND: cxd56 has its own nuttx usb stack which does not forward Set/ClearFeature(Endpoint) to DCD.
     // There is no way for us to know when EP is un-stall, therefore we will unconditionally un-stall here and
     // hope everything will work
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index b0999b5d9..d3284c62a 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -69,7 +69,7 @@
 
 /*------------------------------------------------------------------*/
 /* Count number of arguments of __VA_ARGS__
- * - reference https://groups.google.com/forum/#!topic/comp.std.c/d-6Mj5Lko_s
+ * - reference https://stackoverflow.com/questions/2124339/c-preprocessor-va-args-number-of-arguments
  * - _GET_NTH_ARG() takes args >= N (64) but only expand to Nth one (64th)
  * - _RSEQ_N() is reverse sequential to N to add padding to have
  * Nth position is the same as the number of arguments
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index ddec481a8..54627eaa0 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -36,59 +36,59 @@
 // - PORT_HIGHSPEED: mask to indicate which port support highspeed mode, bit0 for port0 and so on.
 
 //------------- NXP -------------//
-#if   TU_CHECK_MCU(LPC11UXX, LPC13XX, LPC15XX)
+#if   TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
   #define DCD_ATTR_ENDPOINT_MAX   5
 
-#elif TU_CHECK_MCU(LPC175X_6X, LPC177X_8X, LPC40XX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
   #define DCD_ATTR_ENDPOINT_MAX   16
 
-#elif TU_CHECK_MCU(LPC18XX, LPC43XX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   // TODO USB0 has 6, USB1 has 4
   #define DCD_ATTR_ENDPOINT_MAX   6
 
-#elif TU_CHECK_MCU(LPC51UXX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX)
    #define DCD_ATTR_ENDPOINT_MAX   5
 
-#elif TU_CHECK_MCU(LPC54XXX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC54XXX)
   // TODO USB0 has 5, USB1 has 6
   #define DCD_ATTR_ENDPOINT_MAX   6
 
-#elif TU_CHECK_MCU(LPC55XX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC55XX)
   // TODO USB0 has 5, USB1 has 6
   #define DCD_ATTR_ENDPOINT_MAX   6
 
-#elif TU_CHECK_MCU(MIMXRT10XX)
+#elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
-#elif TU_CHECK_MCU(MKL25ZXX, K32L2BXX)
+#elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2BXX)
   #define DCD_ATTR_ENDPOINT_MAX   16
 
-#elif TU_CHECK_MCU(MM32F327X)
+#elif TU_CHECK_MCU(OPT_MCU_MM32F327X)
   #define DCD_ATTR_ENDPOINT_MAX   16
 
 //------------- Nordic -------------//
-#elif TU_CHECK_MCU(NRF5X)
+#elif TU_CHECK_MCU(OPT_MCU_NRF5X)
   // 8 CBI + 1 ISO
   #define DCD_ATTR_ENDPOINT_MAX   9
 
 //------------- Microchip -------------//
-#elif TU_CHECK_MCU(SAMD21, SAMD51, SAME5X) || \
-      TU_CHECK_MCU(SAMD11, SAML21, SAML22)
+#elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAMD51, OPT_MCU_SAME5X) || \
+      TU_CHECK_MCU(OPT_MCU_SAMD11, OPT_MCU_SAML21, OPT_MCU_SAML22)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
-#elif TU_CHECK_MCU(SAMG)
+#elif TU_CHECK_MCU(OPT_MCU_SAMG)
   #define DCD_ATTR_ENDPOINT_MAX   6
   #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
 
-#elif TU_CHECK_MCU(SAMX7X)
+#elif TU_CHECK_MCU(OPT_MCU_SAMX7X)
   #define DCD_ATTR_ENDPOINT_MAX   10
   #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
 
 //------------- ST -------------//
-#elif TU_CHECK_MCU(STM32F0)
+#elif TU_CHECK_MCU(OPT_MCU_STM32F0)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
-#elif TU_CHECK_MCU(STM32F1)
+#elif TU_CHECK_MCU(OPT_MCU_STM32F1)
   #if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \
       defined (STM32F107xB) || defined (STM32F107xC)
     #define DCD_ATTR_ENDPOINT_MAX   4
@@ -97,32 +97,32 @@
     #define DCD_ATTR_ENDPOINT_MAX   8
   #endif
 
-#elif TU_CHECK_MCU(STM32F2)
+#elif TU_CHECK_MCU(OPT_MCU_STM32F2)
   // FS has 4 ep, HS has 5 ep
   #define DCD_ATTR_ENDPOINT_MAX   6
   #define DCD_ATTR_DWC2_STM32
 
-#elif TU_CHECK_MCU(STM32F3)
+#elif TU_CHECK_MCU(OPT_MCU_STM32F3)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
-#elif TU_CHECK_MCU(STM32F4)
+#elif TU_CHECK_MCU(OPT_MCU_STM32F4)
   // For most mcu, FS has 4, HS has 6. TODO 446/469/479 HS has 9
   #define DCD_ATTR_ENDPOINT_MAX   6
   #define DCD_ATTR_DWC2_STM32
 
-#elif TU_CHECK_MCU(STM32F7)
+#elif TU_CHECK_MCU(OPT_MCU_STM32F7)
   // FS has 6, HS has 9
   #define DCD_ATTR_ENDPOINT_MAX   9
   #define DCD_ATTR_DWC2_STM32
 
-#elif TU_CHECK_MCU(STM32H7)
+#elif TU_CHECK_MCU(OPT_MCU_STM32H7)
   #define DCD_ATTR_ENDPOINT_MAX   9
   #define DCD_ATTR_DWC2_STM32
 
-#elif TU_CHECK_MCU(STM32L0, STM32L1)
+#elif TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
-#elif TU_CHECK_MCU(STM32L4)
+#elif TU_CHECK_MCU(OPT_MCU_STM32L4)
   #if defined (STM32L475xx) || defined (STM32L476xx) ||                          \
       defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || \
       defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || \
@@ -134,53 +134,50 @@
   #endif
 
 //------------- Sony -------------//
-#elif TU_CHECK_MCU(CXD56)
+#elif TU_CHECK_MCU(OPT_MCU_CXD56)
   #define DCD_ATTR_ENDPOINT_MAX   7
   #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
 
 //------------- TI -------------//
-#elif TU_CHECK_MCU(MSP430x5xx)
+#elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
 //------------- ValentyUSB -------------//
-#elif TU_CHECK_MCU(VALENTYUSB_EPTRI)
+#elif TU_CHECK_MCU(OPT_MCU_VALENTYUSB_EPTRI)
   #define DCD_ATTR_ENDPOINT_MAX   16
 
 //------------- Nuvoton -------------//
-#elif TU_CHECK_MCU(NUC121) || TU_CHECK_MCU(NUC126)
+#elif TU_CHECK_MCU(OPT_MCU_NUC121, OPT_MCU_NUC126)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
-#elif TU_CHECK_MCU(NUC120)
+#elif TU_CHECK_MCU(OPT_MCU_NUC120)
   #define DCD_ATTR_ENDPOINT_MAX   6
 
-#elif TU_CHECK_MCU(NUC505)
+#elif TU_CHECK_MCU(OPT_MCU_NUC505)
   #define DCD_ATTR_ENDPOINT_MAX   12
 
 //------------- Espressif -------------//
-#elif TU_CHECK_MCU(ESP32S2, ESP32S3)
+#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   #define DCD_ATTR_ENDPOINT_MAX   6
 
 //------------- Dialog -------------//
-#elif TU_CHECK_MCU(DA1469X)
+#elif TU_CHECK_MCU(OPT_MCU_DA1469X)
   #define DCD_ATTR_ENDPOINT_MAX   4
 
 //------------- Raspberry Pi -------------//
-#elif TU_CHECK_MCU(RP2040)
+#elif TU_CHECK_MCU(OPT_MCU_RP2040)
   #define DCD_ATTR_ENDPOINT_MAX   16
 
 //------------- Silabs -------------//
-#elif TU_CHECK_MCU(EFM32GG) || TU_CHECK_MCU(EFM32GG11) || TU_CHECK_MCU(EFM32GG12)
+#elif TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_EFM32GG11, OPT_MCU_EFM32GG12)
   #define DCD_ATTR_ENDPOINT_MAX   7
 
 //------------- Renesas -------------//
-#elif TU_CHECK_MCU(RX63X) || TU_CHECK_MCU(RX65X) || TU_CHECK_MCU(RX72N)
+#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
   #define DCD_ATTR_ENDPOINT_MAX   10
 
-//#elif TU_CHECK_MCU(MM32F327X)
-//  #define DCD_ATTR_ENDPOINT_MAX not known yet
-
 //------------- GigaDevice -------------//
-#elif TU_CHECK_MCU(GD32VF103)
+#elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
   #define DCD_ATTR_ENDPOINT_MAX   4
 
 #else
diff --git a/src/host/hcd_attr.h b/src/host/hcd_attr.h
index 729fc407b..a9bc242d7 100644
--- a/src/host/hcd_attr.h
+++ b/src/host/hcd_attr.h
@@ -34,64 +34,64 @@
 // - PORT_HIGHSPEED: mask to indicate which port support highspeed mode, bit0 for port0 and so on.
 
 //------------- NXP -------------//
-#if TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX)
+#if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
   #define HCD_ATTR_OHCI
 
-#elif TU_CHECK_MCU(LPC18XX) || TU_CHECK_MCU(LPC43XX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   #define HCD_ATTR_EHCI_TRANSDIMENSION
 
-#elif TU_CHECK_MCU(LPC54XXX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC54XXX)
   // #define HCD_ATTR_EHCI_NXP_PTD
 
-#elif TU_CHECK_MCU(LPC55XX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC55XX)
   // #define HCD_ATTR_EHCI_NXP_PTD
 
-#elif TU_CHECK_MCU(MIMXRT10XX)
+#elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX)
   #define HCD_ATTR_EHCI_TRANSDIMENSION
 
-#elif TU_CHECK_MCU(MKL25ZXX)
+#elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX)
 
 //------------- Microchip -------------//
-#elif TU_CHECK_MCU(SAMD21) || TU_CHECK_MCU(SAMD51) || TU_CHECK_MCU(SAME5X) || \
-      TU_CHECK_MCU(SAMD11) || TU_CHECK_MCU(SAML21) || TU_CHECK_MCU(SAML22)
+#elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAMD51, OPT_MCU_SAME5X) || \
+      TU_CHECK_MCU(OPT_MCU_SAMD11, OPT_MCU_SAML21, OPT_MCU_SAML22)
 
-#elif TU_CHECK_MCU(SAMG)
+#elif TU_CHECK_MCU(OPT_MCU_SAMG)
 
-#elif TU_CHECK_MCU(SAMX7X)
+#elif TU_CHECK_MCU(OPT_MCU_SAMX7X)
 
 //------------- ST -------------//
-#elif TU_CHECK_MCU(STM32F0) || TU_CHECK_MCU(STM32F1) || TU_CHECK_MCU(STM32F3) || \
-      TU_CHECK_MCU(STM32L0) || TU_CHECK_MCU(STM32L1) || TU_CHECK_MCU(STM32L4)
+#elif TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F1, OPT_MCU_STM32F3) || \
+      TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32L4)
 
-#elif TU_CHECK_MCU(STM32F2) || TU_CHECK_MCU(STM32F4) || TU_CHECK_MCU(STM32F3)
+#elif TU_CHECK_MCU(OPT_MCU_STM32F2, OPT_MCU_STM32F3, OPT_MCU_STM32F4)
 
-#elif TU_CHECK_MCU(STM32F7)
+#elif TU_CHECK_MCU(OPT_MCU_STM32F7)
 
-#elif TU_CHECK_MCU(STM32H7)
+#elif TU_CHECK_MCU(OPT_MCU_STM32H7)
 
 //------------- Sony -------------//
-#elif TU_CHECK_MCU(CXD56)
+#elif TU_CHECK_MCU(OPT_MCU_CXD56)
 
 //------------- Nuvoton -------------//
-#elif TU_CHECK_MCU(NUC505)
+#elif TU_CHECK_MCU(OPT_MCU_NUC505)
 
 //------------- Espressif -------------//
-#elif TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
 
 //------------- Raspberry Pi -------------//
-#elif TU_CHECK_MCU(RP2040)
+#elif TU_CHECK_MCU(OPT_MCU_RP2040)
 
 //------------- Silabs -------------//
-#elif TU_CHECK_MCU(EFM32GG) || TU_CHECK_MCU(EFM32GG11) || TU_CHECK_MCU(EFM32GG12)
+#elif TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_EFM32GG11, OPT_MCU_EFM32GG12)
 
 //------------- Renesas -------------//
-#elif TU_CHECK_MCU(RX63X) || TU_CHECK_MCU(RX65X) || TU_CHECK_MCU(RX72N)
+#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
 
-//#elif TU_CHECK_MCU(MM32F327X)
+//#elif TU_CHECK_MCU(OPT_MCU_MM32F327X)
 //  #define DCD_ATTR_ENDPOINT_MAX not known yet
 
 //------------- GigaDevice -------------//
-#elif TU_CHECK_MCU(GD32VF103)
+#elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
 
 #else
 //  #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index ca6564d46..933f352a2 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -109,13 +109,10 @@
 #define STM32F1_FSDEV
 #endif
 
-#if (TUSB_OPT_DEVICE_ENABLED) && ( \
-      (CFG_TUSB_MCU == OPT_MCU_STM32F0                          ) || \
-      (CFG_TUSB_MCU == OPT_MCU_STM32F1 && defined(STM32F1_FSDEV)) || \
-      (CFG_TUSB_MCU == OPT_MCU_STM32F3                          ) || \
-	  (CFG_TUSB_MCU == OPT_MCU_STM32L0                          ) || \
-      (CFG_TUSB_MCU == OPT_MCU_STM32L1                          ) \
-    )
+#if TUSB_OPT_DEVICE_ENABLED && \
+      ( TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1) || \
+        (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV)) \
+      )
 
 // In order to reduce the dependance on HAL, we undefine this.
 // Some definitions are copied to our private include file.
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index fca5321f7..7ae10652c 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -31,16 +31,16 @@
 #include "device/dcd_attr.h"
 
 #if TUSB_OPT_DEVICE_ENABLED && \
-    ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(ESP32S2, ESP32S3, GD32VF103) )
+    ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) )
 
 #include "device/dcd.h"
 #include "dwc2_type.h"
 
 #if defined(DCD_ATTR_DWC2_STM32)
   #include "dwc2_stm32.h"
-#elif TU_CHECK_MCU(ESP32S2, ESP32S3)
+#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   #include "dwc2_esp32.h"
-#elif TU_CHECK_MCU(GD32VF103)
+#elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
   #include "dwc2_gd32.h"
 #else
   #error "Unsupported MCUs"
diff --git a/src/tusb_option.h b/src/tusb_option.h
index d707c44c7..509ff4a3c 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -130,7 +130,7 @@
 
 // Helper to check if configured MCU is one of listed
 // Apply _TU_CHECK_MCU with || as separator to list of input
-#define _TU_CHECK_MCU(_m)   (CFG_TUSB_MCU == OPT_MCU_##_m)
+#define _TU_CHECK_MCU(_m)   (CFG_TUSB_MCU == _m)
 #define TU_CHECK_MCU(...)   (TU_ARGS_APPLY(_TU_CHECK_MCU, ||, __VA_ARGS__))
 
 //--------------------------------------------------------------------+
-- 
cgit v1.3.1


From 6c67fc412516950622a13fb34ddc10b64b9b3843 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 29 Oct 2021 00:53:30 +0700
Subject: correctly init hs phy for bcm

---
 examples/device/cdc_msc/src/tusb_config.h       |   5 +-
 examples/device/hid_composite/src/tusb_config.h |   4 +-
 src/common/tusb_types.h                         |   4 +-
 src/portable/synopsys/dwc2/dcd_dwc2.c           | 211 ++++++++++++++----------
 src/portable/synopsys/dwc2/dwc2_type.h          | 166 +++++++++----------
 5 files changed, 204 insertions(+), 186 deletions(-)

(limited to 'examples')

diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h
index a3802f536..499966cb4 100644
--- a/examples/device/cdc_msc/src/tusb_config.h
+++ b/examples/device/cdc_msc/src/tusb_config.h
@@ -47,9 +47,8 @@
 // RHPort max operational speed can defined by board.mk
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X || \
-       CFG_TUSB_MCU == OPT_MCU_BCM2711)
+  #if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX, OPT_MCU_MIMXRT10XX, OPT_MCU_NUC505) ||\
+      TU_CHECK_MCU(OPT_MCU_CXD56, OPT_MCU_SAMX7X, OPT_MCU_BCM2711)
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
diff --git a/examples/device/hid_composite/src/tusb_config.h b/examples/device/hid_composite/src/tusb_config.h
index 868424e6d..8fa5e5cd4 100644
--- a/examples/device/hid_composite/src/tusb_config.h
+++ b/examples/device/hid_composite/src/tusb_config.h
@@ -47,8 +47,8 @@
 // RHPort max operational speed can defined by board.mk
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X)
+  #if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX, OPT_MCU_MIMXRT10XX, OPT_MCU_NUC505) ||\
+      TU_CHECK_MCU(OPT_MCU_CXD56, OPT_MCU_SAMX7X, OPT_MCU_BCM2711)
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index 233def466..5b26f5aec 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -47,8 +47,8 @@
 typedef enum
 {
   TUSB_SPEED_FULL = 0,
-  TUSB_SPEED_LOW     ,
-  TUSB_SPEED_HIGH,
+  TUSB_SPEED_LOW  = 1,
+  TUSB_SPEED_HIGH = 2,
   TUSB_SPEED_INVALID = 0xff,
 }tusb_speed_t;
 
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 0d2766c38..ce9b58e03 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -199,35 +199,6 @@ static void bus_reset(uint8_t rhport)
   dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT;
 }
 
-
-static tusb_speed_t get_speed(uint8_t rhport)
-{
-  (void) rhport;
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
-  uint32_t const enum_spd = (dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos;
-  return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL;
-}
-
-static void set_speed(uint8_t rhport, tusb_speed_t speed)
-{
-  uint32_t bitvalue;
-
-  if ( rhport == 1 )
-  {
-    bitvalue = (TUSB_SPEED_HIGH == speed ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS);
-  }
-  else
-  {
-    bitvalue = DCD_FULL_SPEED;
-  }
-
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
-
-  // Clear and set speed bits
-  dwc2->dcfg &= ~(3 << DCFG_DSPD_Pos);
-  dwc2->dcfg |= (bitvalue << DCFG_DSPD_Pos);
-}
-
 static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes)
 {
   (void) rhport;
@@ -371,90 +342,136 @@ static void reset_core(dwc2_regs_t * dwc2)
   // wait for device mode ?
 }
 
-void dcd_init (uint8_t rhport)
+static bool has_hs_phy(dwc2_regs_t * dwc2)
 {
-  // Programming model begins in the last section of the chapter on the USB
-  // peripheral in each Reference Manual.
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  return TUD_OPT_HIGH_SPEED && dwc2->ghwcfg2_bm.hs_phy_type != HS_PHY_TYPE_NONE;
+}
 
-  // Check Synopsys ID, failed if controller is not enabled
-  uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
-  TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID, );
+static void phy_fs_init(dwc2_regs_t * dwc2)
+{
+  TU_LOG1("Fullspeed PHY init\r\n");
 
-  print_dwc2_info(dwc2);
+  // Select FS PHY
+  dwc2->gusbcfg |= GUSBCFG_PHYSEL;
 
-  // Force device mode
-  dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
+  // Reset core after selecting PHY
+  reset_core(dwc2);
 
-  uint32_t const hs_phy_type = dwc2->ghwcfg2_bm.hs_phy_type;
+  // set turn around
+  // The values above are calculated for the minimum AHB frequency of 30 MHz. USB turnaround
+  // time is critical for certification where long cables and 5-Hubs are used, so if
+  // you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical,
+  // these bits can be programmed to a larger value.
+  dwc2_set_turnaround(dwc2, TUSB_SPEED_FULL);
 
-  if( !TUD_OPT_HIGH_SPEED || hs_phy_type == HS_PHY_TYPE_NONE)
-  {
-    // max speed is full or core does not support highspeed
-    TU_LOG2("Fullspeed PHY init\r\n");
+  // set max speed
+  dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos);
 
-    // Select FS PHY
-    dwc2->gusbcfg |= GUSBCFG_PHYSEL;
+  #if defined(DCD_ATTR_DWC2_STM32)
+  // activate FS PHY on stm32
+  dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
+  #endif
+}
 
-    // Reset core after selecting PHY
-    reset_core(dwc2);
+static void phy_hs_init(dwc2_regs_t * dwc2)
+{
+  uint32_t gusbcfg = dwc2->gusbcfg;
 
-    #if defined(DCD_ATTR_DWC2_STM32)
-    // activate FS PHY on stm32
-    dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
-    #endif
-  }else
+  // De-select FS PHY
+  gusbcfg &= ~GUSBCFG_PHYSEL;
+
+  if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI)
   {
-    // Highspeed mode
+    TU_LOG1("Highspeed ULPI PHY init\r\n");
 
-    #if defined(DCD_ATTR_DWC2_STM32)
-    // Disable STM32 FS PHY
-    dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
-    #endif
+    // Select ULPI
+    gusbcfg |= GUSBCFG_ULPI_UTMI_SEL;
 
-    uint32_t gusbcfg = dwc2->gusbcfg;
+    // ULPI 8-bit interface, single data rate
+    gusbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
 
-    // De-select FS PHY
-    gusbcfg &= ~GUSBCFG_PHYSEL;
+    // default internal VBUS Indicator and Drive
+    gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
 
-    if (hs_phy_type == HS_PHY_TYPE_ULPI)
-    {
-      TU_LOG2("Highspeed ULPI PHY init\r\n");
+    // Disable FS/LS ULPI
+    gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM);
+  }else
+  {
+    TU_LOG1("Highspeed UTMI+ PHY init\r\n");
 
-      // Select ULPI
-      gusbcfg |= GUSBCFG_ULPI_UTMI_SEL;
+    // Select UTMI+ with 8-bit interface
+    gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
 
-      // ULPI 8-bit interface, single data rate
-      gusbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
+    // Set 16-bit interface if supported
+    if (dwc2->ghwcfg4_bm.utmi_phy_data_width) gusbcfg |= GUSBCFG_PHYIF16;
 
-      // default internal VBUS Indicator and Drive
-      gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
+    #if defined(DCD_ATTR_DWC2_STM32) && defined(USB_HS_PHYC)
+    dwc2_stm32_utmi_phy_init(dwc2);
+    #endif
+  }
 
-      // Disable FS/LS ULPI
-      gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM);
-    }else
-    {
-      TU_LOG2("Highspeed UTMI+ PHY init\r\n");
+  // Apply config
+  dwc2->gusbcfg = gusbcfg;
+
+  #if defined(DCD_ATTR_DWC2_STM32)
+  // Disable STM32 FS PHY
+  dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
+  #endif
+
+  // Reset core after selecting PHY
+  reset_core(dwc2);
+
+  // Set turn-around, must after core reset otherwise it will be clear
+  // 9 if UTMI interface is 8-bit, 5 if 16-bit
+  // The values above are calculated for the minimum AHB frequency of 30 MHz. USB turnaround
+  // time is critical for certification where long cables and 5-Hubs are used, so if
+  // you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical,
+  // these bits can be programmed to a larger value.
+  gusbcfg &= ~GUSBCFG_TRDT_Msk;
+  gusbcfg |= (dwc2->ghwcfg4_bm.utmi_phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
+  dwc2->gusbcfg = gusbcfg; // Apply config
+
+  // Set max speed
+  dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_HS << DCFG_DSPD_Pos);
+}
 
-      // Select UTMI+ with 8-bit interface
-      gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
+void dcd_init (uint8_t rhport)
+{
+  // Programming model begins in the last section of the chapter on the USB
+  // peripheral in each Reference Manual.
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
 
-      // Set 16-bit interface if supported
-      if (dwc2->ghwcfg4_bm.utmi_phy_data_width) gusbcfg |= GUSBCFG_PHYIF16;
+  // Check Synopsys ID, failed if controller is not enabled
+  uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
+  TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID, );
 
-      #if defined(DCD_ATTR_DWC2_STM32) && defined(USB_HS_PHYC)
-      dwc2_stm32_utmi_phy_init(dwc2);
-      #endif
-    }
+  print_dwc2_info(dwc2);
 
-    dwc2->gusbcfg = gusbcfg;
+  // Force device mode
+  dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
 
-    // Reset core after selecting PHY
-    reset_core(dwc2);
+  if( !has_hs_phy(dwc2) )
+  {
+    // core does not support highspeed or hs-phy is not present
+    phy_fs_init(dwc2);
+  }else
+  {
+    // Highspeed
+    phy_hs_init(dwc2);
   }
 
+	/* Set HS/FS Timeout Calibration to 7 (max available value).
+	 * The number of PHY clocks that the application programs in
+	 * this field is added to the high/full speed interpacket timeout
+	 * duration in the core to account for any additional delays
+	 * introduced by the PHY. This can be required, because the delay
+	 * introduced by the PHY in generating the linestate condition
+	 * can vary from one PHY to another.
+	 */
+  // dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos);
+
   // Restart PHY clock
-  dwc2->pcgctrl = 0;
+  dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE);
 
   // Clear all interrupts
   dwc2->gintsts |= dwc2->gintsts;
@@ -468,8 +485,6 @@ void dcd_init (uint8_t rhport)
   // (non zero-length packet), send STALL back and discard.
   dwc2->dcfg |= DCFG_NZLSOHSK;
 
-  set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL);
-
   dwc2->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM |
                    GINTMSK_WUIM   | GINTMSK_RXFLVLM;
 
@@ -1088,9 +1103,23 @@ void dcd_int_handler(uint8_t rhport)
 
     dwc2->gintsts = GINTSTS_ENUMDNE;
 
-    tusb_speed_t const speed = get_speed(rhport);
+    tusb_speed_t speed;
+    switch ((dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos)
+    {
+      case DSTS_ENUMSPD_HS:
+        speed = TUSB_SPEED_HIGH;
+      break;
+
+      case DSTS_ENUMSPD_FS_HSPHY:
+      case DSTS_ENUMSPD_FS:
+        speed = TUSB_SPEED_FULL;
+      break;
+
+      case DSTS_ENUMSPD_LS:
+        speed = TUSB_SPEED_LOW;
+      break;
+    }
 
-    dwc2_set_turnaround(dwc2, speed);
     dcd_event_bus_reset(rhport, speed, true);
   }
 
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 5ded366d7..7e472310f 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -259,8 +259,8 @@ union {
            uint32_t reservedd00[64];  // D00..DFF
 
   //------------- Power Clock -------------//
-  volatile uint32_t pcgctrl;          // E00 Power and Clock Gating Control
-  volatile uint32_t pcgcctl1;         // E04
+  volatile uint32_t pcgctl;           // E00 Power and Clock Gating Control
+  volatile uint32_t pcgctl1;          // E04
            uint32_t reservede08[126]; // E08..FFF
 
   //------------- FIFOs -------------//
@@ -273,7 +273,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x0500, "incorrect size");
 TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg   ) == 0x0800, "incorrect size");
 TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epin   ) == 0x0900, "incorrect size");
 TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout  ) == 0x0B00, "incorrect size");
-TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgctrl) == 0x0E00, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgctl ) == 0x0E00, "incorrect size");
 TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 
 //--------------------------------------------------------------------+
@@ -346,39 +346,6 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define HCFG_FSLSS_Msk                   (0x1UL << HCFG_FSLSS_Pos)                // 0x00000004 */
 #define HCFG_FSLSS                       HCFG_FSLSS_Msk                           // FS- and LS-only support */
 
-/********************  Bit definition for DCFG register  ********************/
-#define DCFG_DSPD_Pos                    (0U)
-#define DCFG_DSPD_Msk                    (0x3UL << DCFG_DSPD_Pos)                 // 0x00000003 */
-#define DCFG_DSPD                        DCFG_DSPD_Msk                            // Device speed */
-#define DCFG_DSPD_0                      (0x1UL << DCFG_DSPD_Pos)                 // 0x00000001 */
-#define DCFG_DSPD_1                      (0x2UL << DCFG_DSPD_Pos)                 // 0x00000002 */
-#define DCFG_NZLSOHSK_Pos                (2U)
-#define DCFG_NZLSOHSK_Msk                (0x1UL << DCFG_NZLSOHSK_Pos)             // 0x00000004 */
-#define DCFG_NZLSOHSK                    DCFG_NZLSOHSK_Msk                        // Nonzero-length status OUT handshake */
-
-#define DCFG_DAD_Pos                     (4U)
-#define DCFG_DAD_Msk                     (0x7FUL << DCFG_DAD_Pos)                 // 0x000007F0 */
-#define DCFG_DAD                         DCFG_DAD_Msk                             // Device address */
-#define DCFG_DAD_0                       (0x01UL << DCFG_DAD_Pos)                 // 0x00000010 */
-#define DCFG_DAD_1                       (0x02UL << DCFG_DAD_Pos)                 // 0x00000020 */
-#define DCFG_DAD_2                       (0x04UL << DCFG_DAD_Pos)                 // 0x00000040 */
-#define DCFG_DAD_3                       (0x08UL << DCFG_DAD_Pos)                 // 0x00000080 */
-#define DCFG_DAD_4                       (0x10UL << DCFG_DAD_Pos)                 // 0x00000100 */
-#define DCFG_DAD_5                       (0x20UL << DCFG_DAD_Pos)                 // 0x00000200 */
-#define DCFG_DAD_6                       (0x40UL << DCFG_DAD_Pos)                 // 0x00000400 */
-
-#define DCFG_PFIVL_Pos                   (11U)
-#define DCFG_PFIVL_Msk                   (0x3UL << DCFG_PFIVL_Pos)                // 0x00001800 */
-#define DCFG_PFIVL                       DCFG_PFIVL_Msk                           // Periodic (micro)frame interval */
-#define DCFG_PFIVL_0                     (0x1UL << DCFG_PFIVL_Pos)                // 0x00000800 */
-#define DCFG_PFIVL_1                     (0x2UL << DCFG_PFIVL_Pos)                // 0x00001000 */
-
-#define DCFG_PERSCHIVL_Pos               (24U)
-#define DCFG_PERSCHIVL_Msk               (0x3UL << DCFG_PERSCHIVL_Pos)            // 0x03000000 */
-#define DCFG_PERSCHIVL                   DCFG_PERSCHIVL_Msk                       // Periodic scheduling interval */
-#define DCFG_PERSCHIVL_0                 (0x1UL << DCFG_PERSCHIVL_Pos)            // 0x01000000 */
-#define DCFG_PERSCHIVL_1                 (0x2UL << DCFG_PERSCHIVL_Pos)            // 0x02000000 */
-
 /********************  Bit definition for PCGCR register  ********************/
 #define PCGCR_STPPCLK_Pos                (0U)
 #define PCGCR_STPPCLK_Msk                (0x1UL << PCGCR_STPPCLK_Pos)             // 0x00000001 */
@@ -413,6 +380,41 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define GOTGINT_IDCHNG_Msk               (0x1UL << GOTGINT_IDCHNG_Pos)            // 0x00100000 */
 #define GOTGINT_IDCHNG                   GOTGINT_IDCHNG_Msk                       // Change in ID pin input value           */
 
+/********************  Bit definition for DCFG register  ********************/
+#define DCFG_DSPD_Pos                    (0U)
+#define DCFG_DSPD_Msk                    (0x3UL << DCFG_DSPD_Pos)                 // 0x00000003
+#define DCFG_DSPD_HS                     0    // Highspeed
+#define DCFG_DSPD_FS_HSPHY               1    // Fullspeed on HS PHY
+#define DCFG_DSPD_LS                     2    // Lowspeed
+#define DCFG_DSPD_FS                     3    // Fullspeed on FS PHY
+
+#define DCFG_NZLSOHSK_Pos                (2U)
+#define DCFG_NZLSOHSK_Msk                (0x1UL << DCFG_NZLSOHSK_Pos)             // 0x00000004 */
+#define DCFG_NZLSOHSK                    DCFG_NZLSOHSK_Msk                        // Nonzero-length status OUT handshake */
+
+#define DCFG_DAD_Pos                     (4U)
+#define DCFG_DAD_Msk                     (0x7FUL << DCFG_DAD_Pos)                 // 0x000007F0 */
+#define DCFG_DAD                         DCFG_DAD_Msk                             // Device address */
+#define DCFG_DAD_0                       (0x01UL << DCFG_DAD_Pos)                 // 0x00000010 */
+#define DCFG_DAD_1                       (0x02UL << DCFG_DAD_Pos)                 // 0x00000020 */
+#define DCFG_DAD_2                       (0x04UL << DCFG_DAD_Pos)                 // 0x00000040 */
+#define DCFG_DAD_3                       (0x08UL << DCFG_DAD_Pos)                 // 0x00000080 */
+#define DCFG_DAD_4                       (0x10UL << DCFG_DAD_Pos)                 // 0x00000100 */
+#define DCFG_DAD_5                       (0x20UL << DCFG_DAD_Pos)                 // 0x00000200 */
+#define DCFG_DAD_6                       (0x40UL << DCFG_DAD_Pos)                 // 0x00000400 */
+
+#define DCFG_PFIVL_Pos                   (11U)
+#define DCFG_PFIVL_Msk                   (0x3UL << DCFG_PFIVL_Pos)                // 0x00001800 */
+#define DCFG_PFIVL                       DCFG_PFIVL_Msk                           // Periodic (micro)frame interval */
+#define DCFG_PFIVL_0                     (0x1UL << DCFG_PFIVL_Pos)                // 0x00000800 */
+#define DCFG_PFIVL_1                     (0x2UL << DCFG_PFIVL_Pos)                // 0x00001000 */
+
+#define DCFG_PERSCHIVL_Pos               (24U)
+#define DCFG_PERSCHIVL_Msk               (0x3UL << DCFG_PERSCHIVL_Pos)            // 0x03000000 */
+#define DCFG_PERSCHIVL                   DCFG_PERSCHIVL_Msk                       // Periodic scheduling interval */
+#define DCFG_PERSCHIVL_0                 (0x1UL << DCFG_PERSCHIVL_Pos)            // 0x01000000 */
+#define DCFG_PERSCHIVL_1                 (0x2UL << DCFG_PERSCHIVL_Pos)            // 0x02000000 */
+
 /********************  Bit definition for DCTL register  ********************/
 #define DCTL_RWUSIG_Pos                  (0U)
 #define DCTL_RWUSIG_Msk                  (0x1UL << DCTL_RWUSIG_Pos)               // 0x00000001 */
@@ -466,12 +468,15 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define DSTS_SUSPSTS_Pos                 (0U)
 #define DSTS_SUSPSTS_Msk                 (0x1UL << DSTS_SUSPSTS_Pos)              // 0x00000001 */
 #define DSTS_SUSPSTS                     DSTS_SUSPSTS_Msk                         // Suspend status   */
-
 #define DSTS_ENUMSPD_Pos                 (1U)
 #define DSTS_ENUMSPD_Msk                 (0x3UL << DSTS_ENUMSPD_Pos)              // 0x00000006 */
 #define DSTS_ENUMSPD                     DSTS_ENUMSPD_Msk                         // Enumerated speed */
-#define DSTS_ENUMSPD_0                   (0x1UL << DSTS_ENUMSPD_Pos)              // 0x00000002 */
-#define DSTS_ENUMSPD_1                   (0x2UL << DSTS_ENUMSPD_Pos)              // 0x00000004 */
+#define DSTS_ENUMSPD_HS                  0    // Highspeed
+#define DSTS_ENUMSPD_FS_HSPHY            1    // Fullspeed on HS PHY
+#define DSTS_ENUMSPD_LS                  2    // Lowspeed
+#define DSTS_ENUMSPD_FS                  3    // Fullspeed on FS PHY
+
+
 #define DSTS_EERR_Pos                    (3U)
 #define DSTS_EERR_Msk                    (0x1UL << DSTS_EERR_Pos)                 // 0x00000008 */
 #define DSTS_EERR                        DSTS_EERR_Msk                            // Erratic error     */
@@ -501,15 +506,12 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define GAHBCFG_PTXFELVL_Msk             (0x1UL << GAHBCFG_PTXFELVL_Pos)          // 0x00000100 */
 #define GAHBCFG_PTXFELVL                 GAHBCFG_PTXFELVL_Msk                     // Periodic TxFIFO empty level */
 
-#define GSNPSID_ID_MASK			             TU_GENMASK(31, 16)
+#define GSNPSID_ID_MASK                 TU_GENMASK(31, 16)
 
 /********************  Bit definition for GUSBCFG register  ********************/
 #define GUSBCFG_TOCAL_Pos                (0U)
 #define GUSBCFG_TOCAL_Msk                (0x7UL << GUSBCFG_TOCAL_Pos)             // 0x00000007 */
 #define GUSBCFG_TOCAL                    GUSBCFG_TOCAL_Msk                        // FS timeout calibration */
-#define GUSBCFG_TOCAL_0                  (0x1UL << GUSBCFG_TOCAL_Pos)             // 0x00000001 */
-#define GUSBCFG_TOCAL_1                  (0x2UL << GUSBCFG_TOCAL_Pos)             // 0x00000002 */
-#define GUSBCFG_TOCAL_2                  (0x4UL << GUSBCFG_TOCAL_Pos)             // 0x00000004 */
 #define GUSBCFG_PHYIF16_Pos              (3U)
 #define GUSBCFG_PHYIF16_Msk              (0x1UL << GUSBCFG_PHYIF16_Pos)             // 0x00000008 */
 #define GUSBCFG_PHYIF16                  GUSBCFG_PHYIF16_Msk                        // PHY Interface (PHYIf) */
@@ -519,7 +521,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define GUSBCFG_PHYSEL_Pos               (6U)
 #define GUSBCFG_PHYSEL_Msk               (0x1UL << GUSBCFG_PHYSEL_Pos)            // 0x00000040 */
 #define GUSBCFG_PHYSEL                   GUSBCFG_PHYSEL_Msk                       // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define GUSBCFG_DDRSEL			             TU_BIT(7)                                // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface.
+#define GUSBCFG_DDRSEL                TU_BIT(7)                                // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface.
 #define GUSBCFG_SRPCAP_Pos               (8U)
 #define GUSBCFG_SRPCAP_Msk               (0x1UL << GUSBCFG_SRPCAP_Pos)            // 0x00000100 */
 #define GUSBCFG_SRPCAP                   GUSBCFG_SRPCAP_Msk                       // SRP-capable */
@@ -597,8 +599,8 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define GRSTCTL_TXFNUM_2                 (0x04UL << GRSTCTL_TXFNUM_Pos)           // 0x00000100 */
 #define GRSTCTL_TXFNUM_3                 (0x08UL << GRSTCTL_TXFNUM_Pos)           // 0x00000200 */
 #define GRSTCTL_TXFNUM_4                 (0x10UL << GRSTCTL_TXFNUM_Pos)           // 0x00000400 */
-#define GRSTCTL_CSFTRST_DONE_Pos		     (29)
-#define GRSTCTL_CSFTRST_DONE		         (1u << GRSTCTL_CSFTRST_DONE_Pos)         // Reset Done, only available from v4.20a
+#define GRSTCTL_CSFTRST_DONE_Pos       (29)
+#define GRSTCTL_CSFTRST_DONE           (1u << GRSTCTL_CSFTRST_DONE_Pos)         // Reset Done, only available from v4.20a
 #define GRSTCTL_DMAREQ_Pos               (30U)
 #define GRSTCTL_DMAREQ_Msk               (0x1UL << GRSTCTL_DMAREQ_Pos)            // 0x40000000 */
 #define GRSTCTL_DMAREQ                   GRSTCTL_DMAREQ_Msk                       // DMA request signal */
@@ -1672,48 +1674,36 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define DOEPTSIZ_STUPCNT_0               (0x1UL << DOEPTSIZ_STUPCNT_Pos)          // 0x20000000 */
 #define DOEPTSIZ_STUPCNT_1               (0x2UL << DOEPTSIZ_STUPCNT_Pos)          // 0x40000000 */
 
-/********************  Bit definition for PCGCCTL register  ********************/
-#define PCGCCTL_STOPCLK_Pos              (0U)
-#define PCGCCTL_STOPCLK_Msk              (0x1UL << PCGCCTL_STOPCLK_Pos)           // 0x00000001 */
-#define PCGCCTL_STOPCLK                  PCGCCTL_STOPCLK_Msk                      // SETUP packet count */
-#define PCGCCTL_GATECLK_Pos              (1U)
-#define PCGCCTL_GATECLK_Msk              (0x1UL << PCGCCTL_GATECLK_Pos)           // 0x00000002 */
-#define PCGCCTL_GATECLK                  PCGCCTL_GATECLK_Msk                      //Bit 0 */
-#define PCGCCTL_PHYSUSP_Pos              (4U)
-#define PCGCCTL_PHYSUSP_Msk              (0x1UL << PCGCCTL_PHYSUSP_Pos)           // 0x00000010 */
-#define PCGCCTL_PHYSUSP                  PCGCCTL_PHYSUSP_Msk                      //Bit 1 */
-
-/********************  Bit definition for USBPHYC_PLL1 register  ********************/
-#define HS_PHYC_PLL1_PLLEN_Pos                (0U)
-#define HS_PHYC_PLL1_PLLEN_Msk                (0x1UL << HS_PHYC_PLL1_PLLEN_Pos)   // 0x00000001 */
-#define HS_PHYC_PLL1_PLLEN                    HS_PHYC_PLL1_PLLEN_Msk              // Enable PLL */
-#define HS_PHYC_PLL1_PLLSEL_Pos               (1U)
-#define HS_PHYC_PLL1_PLLSEL_Msk               (0x7UL << HS_PHYC_PLL1_PLLSEL_Pos)  // 0x0000000E */
-#define HS_PHYC_PLL1_PLLSEL                   HS_PHYC_PLL1_PLLSEL_Msk             // Controls PHY frequency operation selection */
-#define HS_PHYC_PLL1_PLLSEL_1                 (0x1UL << HS_PHYC_PLL1_PLLSEL_Pos)  // 0x00000002 */
-#define HS_PHYC_PLL1_PLLSEL_2                 (0x2UL << HS_PHYC_PLL1_PLLSEL_Pos)  // 0x00000004 */
-#define HS_PHYC_PLL1_PLLSEL_3                 (0x4UL << HS_PHYC_PLL1_PLLSEL_Pos)  // 0x00000008 */
-
-#define HS_PHYC_PLL1_PLLSEL_12MHZ             0x00000000U                                                       // PHY PLL1 input clock frequency 12 MHz   */
-#define HS_PHYC_PLL1_PLLSEL_12_5MHZ           HS_PHYC_PLL1_PLLSEL_1                                         // PHY PLL1 input clock frequency 12.5 MHz */
-#define HS_PHYC_PLL1_PLLSEL_16MHZ             (uint32_t)(HS_PHYC_PLL1_PLLSEL_1 | HS_PHYC_PLL1_PLLSEL_2) // PHY PLL1 input clock frequency 16 MHz   */
-#define HS_PHYC_PLL1_PLLSEL_24MHZ             HS_PHYC_PLL1_PLLSEL_3                                         // PHY PLL1 input clock frequency 24 MHz   */
-#define HS_PHYC_PLL1_PLLSEL_25MHZ             (uint32_t)(HS_PHYC_PLL1_PLLSEL_2 | HS_PHYC_PLL1_PLLSEL_3) // PHY PLL1 input clock frequency 25 MHz   */
-
-/********************  Bit definition for USBPHYC_LDO register  ********************/
-#define HS_PHYC_LDO_USED_Pos                 (0U)
-#define HS_PHYC_LDO_USED_Msk                 (0x1UL << HS_PHYC_LDO_USED_Pos) // 0x00000001 */
-#define HS_PHYC_LDO_USED                     HS_PHYC_LDO_USED_Msk      // Monitors the usage status of the PHY's LDO   */
-#define HS_PHYC_LDO_STATUS_Pos               (1U)
-#define HS_PHYC_LDO_STATUS_Msk               (0x1UL << HS_PHYC_LDO_STATUS_Pos) // 0x00000002 */
-#define HS_PHYC_LDO_STATUS                   HS_PHYC_LDO_STATUS_Msk    // Monitors the status of the PHY's LDO.        */
-#define HS_PHYC_LDO_DISABLE_Pos              (2U)
-#define HS_PHYC_LDO_DISABLE_Msk              (0x1UL << HS_PHYC_LDO_DISABLE_Pos) // 0x00000004 */
-#define HS_PHYC_LDO_DISABLE                  HS_PHYC_LDO_DISABLE_Msk    // Controls disable of the High Speed PHY's LDO */
-
-#define HS_PHYC_LDO_ENABLE_Pos               HS_PHYC_LDO_DISABLE_Pos
-#define HS_PHYC_LDO_ENABLE_Msk               HS_PHYC_LDO_DISABLE_Msk
-#define HS_PHYC_LDO_ENABLE                   HS_PHYC_LDO_DISABLE
+/********************  Bit definition for PCGCTL register  ********************/
+#define PCGCTL_IF_DEV_MODE              TU_BIT(31)
+#define PCGCTL_P2HD_PRT_SPD_MASK        (0x3ul << 29)
+#define PCGCTL_P2HD_PRT_SPD_SHIFT       29
+#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK   (0x3ul << 27)
+#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT  27
+#define PCGCTL_MAC_DEV_ADDR_MASK        (0x7ful << 20)
+#define PCGCTL_MAC_DEV_ADDR_SHIFT       20
+#define PCGCTL_MAX_TERMSEL              TU_BIT(19)
+#define PCGCTL_MAX_XCVRSELECT_MASK      (0x3ul << 17)
+#define PCGCTL_MAX_XCVRSELECT_SHIFT     17
+#define PCGCTL_PORT_POWER               TU_BIT(16)
+#define PCGCTL_PRT_CLK_SEL_MASK         (0x3ul << 14)
+#define PCGCTL_PRT_CLK_SEL_SHIFT        14
+#define PCGCTL_ESS_REG_RESTORED         TU_BIT(13)
+#define PCGCTL_EXTND_HIBER_SWITCH       TU_BIT(12)
+#define PCGCTL_EXTND_HIBER_PWRCLMP      TU_BIT(11)
+#define PCGCTL_ENBL_EXTND_HIBER         TU_BIT(10)
+#define PCGCTL_RESTOREMODE              TU_BIT(9)
+#define PCGCTL_RESETAFTSUSP             TU_BIT(8)
+#define PCGCTL_DEEP_SLEEP               TU_BIT(7)
+#define PCGCTL_PHY_IN_SLEEP             TU_BIT(6)
+#define PCGCTL_ENBL_SLEEP_GATING        TU_BIT(5)
+#define PCGCTL_RSTPDWNMODULE            TU_BIT(3)
+#define PCGCTL_PWRCLMP                  TU_BIT(2)
+#define PCGCTL_GATEHCLK                 TU_BIT(1)
+#define PCGCTL_STOPPCLK                 TU_BIT(0)
+
+#define PCGCTL1_TIMER                   (0x3ul << 1)
+#define PCGCTL1_GATEEN                  TU_BIT(0)
 
 #ifdef __cplusplus
  }
-- 
cgit v1.3.1


From 4ea8f1441dda442d784ee57f39a0adc75bf69e56 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 31 Oct 2021 00:19:17 +0700
Subject: correct freertos port for efm32gg

---
 examples/device/cdc_msc_freertos/.skip.MCU_EFM32GG12       | 0
 examples/device/hid_composite_freertos/.skip.MCU_EFM32GG12 | 0
 hw/bsp/sltb009a/board.mk                                   | 6 +-----
 3 files changed, 1 insertion(+), 5 deletions(-)
 delete mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_EFM32GG12
 delete mode 100644 examples/device/hid_composite_freertos/.skip.MCU_EFM32GG12

(limited to 'examples')

diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_EFM32GG12 b/examples/device/cdc_msc_freertos/.skip.MCU_EFM32GG12
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_EFM32GG12 b/examples/device/hid_composite_freertos/.skip.MCU_EFM32GG12
deleted file mode 100644
index e69de29bb..000000000
diff --git a/hw/bsp/sltb009a/board.mk b/hw/bsp/sltb009a/board.mk
index 7a046b34b..f5c240ca2 100644
--- a/hw/bsp/sltb009a/board.mk
+++ b/hw/bsp/sltb009a/board.mk
@@ -34,12 +34,8 @@ INC += \
   $(TOP)/$(SILABS_CMSIS)/Include \
   $(TOP)/hw/bsp/$(BOARD)
 
-# For TinyUSB port source
-VENDOR = silabs
-CHIP_FAMILY = efm32
-
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4
+FREERTOS_PORT = ARM_CM3
 
 # For flash-jlink target
 JLINK_DEVICE = EFM32GG12B810F1024
-- 
cgit v1.3.1


From 0e733ae14bf4c165abcd27ccb1408927b72a0047 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 2 Nov 2021 21:46:23 +0700
Subject: add pi4 to ci build in build_aarch64

---
 .github/workflows/build.yml                        | 160 ---------------------
 .github/workflows/build_aarch64.yml                |  67 +++++++++
 .github/workflows/build_arm.yml                    | 160 +++++++++++++++++++++
 .gitmodules                                        |   1 +
 examples/device/audio_4_channel_mic/src/main.c     |   2 +-
 examples/device/audio_test/src/main.c              |   2 +-
 examples/device/cdc_msc_freertos/.skip.MCU_BCM2711 |   0
 .../hid_composite_freertos/.skip.MCU_BCM2711       |   0
 hw/bsp/raspberrypi4/family.mk                      |   5 +-
 9 files changed, 232 insertions(+), 165 deletions(-)
 delete mode 100644 .github/workflows/build.yml
 create mode 100644 .github/workflows/build_aarch64.yml
 create mode 100644 .github/workflows/build_arm.yml
 create mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_BCM2711
 create mode 100644 examples/device/hid_composite_freertos/.skip.MCU_BCM2711

(limited to 'examples')

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
deleted file mode 100644
index 53a1628a0..000000000
--- a/.github/workflows/build.yml
+++ /dev/null
@@ -1,160 +0,0 @@
-name: Build ARM
-
-on:
-  pull_request:
-  push:
-  release:
-    types:
-      - created
-
-jobs:
-  # ---------------------------------------
-  # Unit testing with Ceedling
-  # ---------------------------------------
-  unit-test:
-    runs-on: ubuntu-latest
-    steps:
-    - name: Setup Ruby
-      uses: actions/setup-ruby@v1
-      with:
-        ruby-version: '2.7'
-
-    - name: Checkout TinyUSB
-      uses: actions/checkout@v2
-
-    - name: Unit Tests
-      run: |
-        # Install Ceedling
-        gem install ceedling
-        cd test
-        ceedling test:all
-
-  # ---------------------------------------
-  # Build ARM family
-  # ---------------------------------------
-  build-arm:
-    runs-on: ubuntu-latest
-    strategy:
-      fail-fast: false
-      matrix:
-        family:
-        # Alphabetical order
-        - 'imxrt'
-        - 'lpc15'
-        - 'lpc18'
-        - 'lpc54'
-        - 'lpc55'
-        - 'mm32'
-        - 'nrf'
-        - 'rp2040'
-        - 'samd11'
-        - 'samd21'
-        - 'samd51'
-        - 'saml2x'
-        - 'stm32f0'
-        - 'stm32f1'
-        - 'stm32f4'
-        - 'stm32f7'
-        - 'stm32h7'
-        - 'stm32l4'
-    steps:
-    - name: Setup Python
-      uses: actions/setup-python@v2
-
-    - name: Checkout TinyUSB
-      uses: actions/checkout@v2
-
-    - name: Checkout common submodules in lib
-      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel
-
-    - name: Checkout hathach/linkermap
-      uses: actions/checkout@v2
-      with:
-         repository: hathach/linkermap
-         path: linkermap
-
-    - name: Checkout pico-sdk
-      if: matrix.family == 'rp2040'
-      run: |
-        git clone --depth 1 -b develop https://github.com/raspberrypi/pico-sdk ~/pico-sdk
-        echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
-
-    - name: Set Toolchain URL
-      run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v10.2.1-1.1/xpack-arm-none-eabi-gcc-10.2.1-1.1-linux-x64.tar.gz
-
-    - name: Cache Toolchain
-      uses: actions/cache@v2
-      id: cache-toolchain
-      with:
-        path: ~/cache/
-        key: ${{ runner.os }}-21-03-04-${{ env.TOOLCHAIN_URL }}
-
-    - name: Install Toolchain
-      if: steps.cache-toolchain.outputs.cache-hit != 'true'
-      run: |
-        mkdir -p ~/cache/toolchain
-        wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.gz
-        tar -C ~/cache/toolchain -xaf toolchain.tar.gz
-
-    - name: Set Toolchain Path
-      run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
-
-    - name: Build
-      run: python3 tools/build_family.py ${{ matrix.family }}
-
-    - name: Linker Map
-      run: |
-        pip install linkermap/
-        for ex in `ls -d examples/device/*/`; do \
-          find ${ex} -name *.map -print -quit | \
-          xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \
-        done
-
-  # ---------------------------------------
-  # Build all no-family (opharned) boards
-  # ---------------------------------------
-  build-board:
-    runs-on: ubuntu-latest
-    strategy:
-      fail-fast: false
-      matrix:
-        example:
-        # Alphabetical order, a group of 4
-        - 'device/audio_test device/board_test device/cdc_dual_ports device/cdc_msc'
-        - 'device/cdc_msc_freertos device/dfu_runtime device/hid_composite device/hid_composite_freertos'
-        - 'device/hid_generic_inout device/hid_multiple_interface device/midi_test device/msc_dual_lun'
-        - 'device/net_lwip_webserver'
-        - 'device/uac2_headset device/usbtmc device/webusb_serial host/cdc_msc_hid'
-
-    steps:
-    - name: Setup Python
-      uses: actions/setup-python@v2
-
-    - name: Checkout TinyUSB
-      uses: actions/checkout@v2
-
-    - name: Checkout common submodules in lib
-      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-
-    - name: Set Toolchain URL
-      run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v10.2.1-1.1/xpack-arm-none-eabi-gcc-10.2.1-1.1-linux-x64.tar.gz
-
-    - name: Cache Toolchain
-      uses: actions/cache@v2
-      id: cache-toolchain
-      with:
-        path: ~/cache/
-        key: ${{ runner.os }}-21-03-04-${{ env.TOOLCHAIN_URL }}
-
-    - name: Install Toolchain
-      if: steps.cache-toolchain.outputs.cache-hit != 'true'
-      run: |
-        mkdir -p ~/cache/toolchain
-        wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.gz
-        tar -C ~/cache/toolchain -xaf toolchain.tar.gz
-
-    - name: Set Toolchain Path
-      run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
-
-    - name: Build
-      run: python3 tools/build_board.py ${{ matrix.example }}
diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
new file mode 100644
index 000000000..0cc7a5de1
--- /dev/null
+++ b/.github/workflows/build_aarch64.yml
@@ -0,0 +1,67 @@
+name: Build AArch64
+
+on:
+  pull_request:
+  push:
+  release:
+    types:
+      - created
+
+jobs:
+  # ---------------------------------------
+  # Build AARCH64 family
+  # ---------------------------------------
+  build-arm:
+    runs-on: ubuntu-latest
+    strategy:
+      fail-fast: false
+      matrix:
+        family:
+        # Alphabetical order
+        - 'raspberrypi4'
+    steps:
+    - name: Setup Python
+      uses: actions/setup-python@v2
+
+    - name: Checkout TinyUSB
+      uses: actions/checkout@v2
+
+    - name: Checkout common submodules in lib
+      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel
+
+    - name: Checkout hathach/linkermap
+      uses: actions/checkout@v2
+      with:
+         repository: hathach/linkermap
+         path: linkermap
+
+    - name: Set Toolchain URL
+      run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz
+
+    - name: Cache Toolchain
+      uses: actions/cache@v2
+      id: cache-toolchain
+      with:
+        path: ~/cache/
+        key: ${{ runner.os }}-21-11-02-${{ env.TOOLCHAIN_URL }}
+
+    - name: Install Toolchain
+      if: steps.cache-toolchain.outputs.cache-hit != 'true'
+      run: |
+        mkdir -p ~/cache/toolchain
+        wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.gz
+        tar -C ~/cache/toolchain -xaf toolchain.tar.gz
+
+    - name: Set Toolchain Path
+      run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
+
+    - name: Build
+      run: python3 tools/build_family.py ${{ matrix.family }}
+
+    - name: Linker Map
+      run: |
+        pip install linkermap/
+        for ex in `ls -d examples/device/*/`; do \
+          find ${ex} -name *.map -print -quit | \
+          xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \
+        done
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
new file mode 100644
index 000000000..53a1628a0
--- /dev/null
+++ b/.github/workflows/build_arm.yml
@@ -0,0 +1,160 @@
+name: Build ARM
+
+on:
+  pull_request:
+  push:
+  release:
+    types:
+      - created
+
+jobs:
+  # ---------------------------------------
+  # Unit testing with Ceedling
+  # ---------------------------------------
+  unit-test:
+    runs-on: ubuntu-latest
+    steps:
+    - name: Setup Ruby
+      uses: actions/setup-ruby@v1
+      with:
+        ruby-version: '2.7'
+
+    - name: Checkout TinyUSB
+      uses: actions/checkout@v2
+
+    - name: Unit Tests
+      run: |
+        # Install Ceedling
+        gem install ceedling
+        cd test
+        ceedling test:all
+
+  # ---------------------------------------
+  # Build ARM family
+  # ---------------------------------------
+  build-arm:
+    runs-on: ubuntu-latest
+    strategy:
+      fail-fast: false
+      matrix:
+        family:
+        # Alphabetical order
+        - 'imxrt'
+        - 'lpc15'
+        - 'lpc18'
+        - 'lpc54'
+        - 'lpc55'
+        - 'mm32'
+        - 'nrf'
+        - 'rp2040'
+        - 'samd11'
+        - 'samd21'
+        - 'samd51'
+        - 'saml2x'
+        - 'stm32f0'
+        - 'stm32f1'
+        - 'stm32f4'
+        - 'stm32f7'
+        - 'stm32h7'
+        - 'stm32l4'
+    steps:
+    - name: Setup Python
+      uses: actions/setup-python@v2
+
+    - name: Checkout TinyUSB
+      uses: actions/checkout@v2
+
+    - name: Checkout common submodules in lib
+      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel
+
+    - name: Checkout hathach/linkermap
+      uses: actions/checkout@v2
+      with:
+         repository: hathach/linkermap
+         path: linkermap
+
+    - name: Checkout pico-sdk
+      if: matrix.family == 'rp2040'
+      run: |
+        git clone --depth 1 -b develop https://github.com/raspberrypi/pico-sdk ~/pico-sdk
+        echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
+
+    - name: Set Toolchain URL
+      run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v10.2.1-1.1/xpack-arm-none-eabi-gcc-10.2.1-1.1-linux-x64.tar.gz
+
+    - name: Cache Toolchain
+      uses: actions/cache@v2
+      id: cache-toolchain
+      with:
+        path: ~/cache/
+        key: ${{ runner.os }}-21-03-04-${{ env.TOOLCHAIN_URL }}
+
+    - name: Install Toolchain
+      if: steps.cache-toolchain.outputs.cache-hit != 'true'
+      run: |
+        mkdir -p ~/cache/toolchain
+        wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.gz
+        tar -C ~/cache/toolchain -xaf toolchain.tar.gz
+
+    - name: Set Toolchain Path
+      run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
+
+    - name: Build
+      run: python3 tools/build_family.py ${{ matrix.family }}
+
+    - name: Linker Map
+      run: |
+        pip install linkermap/
+        for ex in `ls -d examples/device/*/`; do \
+          find ${ex} -name *.map -print -quit | \
+          xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \
+        done
+
+  # ---------------------------------------
+  # Build all no-family (opharned) boards
+  # ---------------------------------------
+  build-board:
+    runs-on: ubuntu-latest
+    strategy:
+      fail-fast: false
+      matrix:
+        example:
+        # Alphabetical order, a group of 4
+        - 'device/audio_test device/board_test device/cdc_dual_ports device/cdc_msc'
+        - 'device/cdc_msc_freertos device/dfu_runtime device/hid_composite device/hid_composite_freertos'
+        - 'device/hid_generic_inout device/hid_multiple_interface device/midi_test device/msc_dual_lun'
+        - 'device/net_lwip_webserver'
+        - 'device/uac2_headset device/usbtmc device/webusb_serial host/cdc_msc_hid'
+
+    steps:
+    - name: Setup Python
+      uses: actions/setup-python@v2
+
+    - name: Checkout TinyUSB
+      uses: actions/checkout@v2
+
+    - name: Checkout common submodules in lib
+      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
+
+    - name: Set Toolchain URL
+      run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v10.2.1-1.1/xpack-arm-none-eabi-gcc-10.2.1-1.1-linux-x64.tar.gz
+
+    - name: Cache Toolchain
+      uses: actions/cache@v2
+      id: cache-toolchain
+      with:
+        path: ~/cache/
+        key: ${{ runner.os }}-21-03-04-${{ env.TOOLCHAIN_URL }}
+
+    - name: Install Toolchain
+      if: steps.cache-toolchain.outputs.cache-hit != 'true'
+      run: |
+        mkdir -p ~/cache/toolchain
+        wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.gz
+        tar -C ~/cache/toolchain -xaf toolchain.tar.gz
+
+    - name: Set Toolchain Path
+      run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
+
+    - name: Build
+      run: python3 tools/build_board.py ${{ matrix.example }}
diff --git a/.gitmodules b/.gitmodules
index 79dec144e..a95e64ee6 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -130,3 +130,4 @@
 [submodule "hw/mcu/broadcom"]
 	path = hw/mcu/broadcom
 	url = https://github.com/adafruit/broadcom-peripherals.git
+	branch = main-build
diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index 983b87e5b..d085dd43a 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -141,7 +141,7 @@ void tud_resume_cb(void)
 void audio_task(void)
 {
   // Yet to be filled - e.g. put meas data into TX FIFOs etc.
-  asm("nop");
+  // asm("nop");
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c
index 9a2fdd3a1..ed13ce993 100644
--- a/examples/device/audio_test/src/main.c
+++ b/examples/device/audio_test/src/main.c
@@ -142,7 +142,7 @@ void tud_resume_cb(void)
 void audio_task(void)
 {
   // Yet to be filled - e.g. put meas data into TX FIFOs etc.
-  asm("nop");
+  // asm("nop");
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_BCM2711 b/examples/device/cdc_msc_freertos/.skip.MCU_BCM2711
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_BCM2711 b/examples/device/hid_composite_freertos/.skip.MCU_BCM2711
new file mode 100644
index 000000000..e69de29bb
diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk
index b1d14a6ec..2e61b9e74 100644
--- a/hw/bsp/raspberrypi4/family.mk
+++ b/hw/bsp/raspberrypi4/family.mk
@@ -1,9 +1,8 @@
-UF2_FAMILY_ID = 0x57755a57
+MCU_DIR = hw/mcu/broadcom
+DEPS_SUBMODULES += $(MCU_DIR)
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
-MCU_DIR = hw/mcu/broadcom
-
 CC = clang
 
 CFLAGS += \
-- 
cgit v1.3.1


From 28b177484d15971dc12ec76dfe71ffcae433835a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 2 Nov 2021 22:27:00 +0700
Subject: skip net example for pi4 due to ssize_t conflict

---
 examples/device/net_lwip_webserver/.skip.MCU_BCM2711 | 1 +
 1 file changed, 1 insertion(+)
 create mode 100644 examples/device/net_lwip_webserver/.skip.MCU_BCM2711

(limited to 'examples')

diff --git a/examples/device/net_lwip_webserver/.skip.MCU_BCM2711 b/examples/device/net_lwip_webserver/.skip.MCU_BCM2711
new file mode 100644
index 000000000..bdc68f5db
--- /dev/null
+++ b/examples/device/net_lwip_webserver/.skip.MCU_BCM2711
@@ -0,0 +1 @@
+tinyusb/lib/lwip/src/include/lwip/arch.h:202:13: error: conflicting types for 'ssize_t'
\ No newline at end of file
-- 
cgit v1.3.1