From 6e8e2caf7fc2dc5575f5e0c71e69c1b19b3f5699 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 28 Aug 2026 16:39:58 +0700 Subject: pico2_etm_trace: RP2350 board on the MIPI-20 ETM trace carrier Board files for the trace carrier (console GP12/13, LED GP10, I2C GP8/9, PIO-USB host on GP20, all retargeted in board.cmake so the SDK defaults cannot mux a trace pin), compile-time trace pin-conflict checks, the measured DBGPAUSE rationale, Ozone project, and skill/docs updates. Trace validated at the stock 150 MHz (75 MHz TRACECLK, +1 ns sampling): zero overflow through a 15 s throughput soak; V2 probe ceiling 120 MHz. --- hw/bsp/BoardPresets.json | 22 ++++++ hw/bsp/rp2040/boards/pico2_etm_trace/board.cmake | 35 ++++++++++ hw/bsp/rp2040/boards/pico2_etm_trace/board.h | 80 ++++++++++++++++++++++ .../boards/pico2_etm_trace/ozone/rp2350.jdebug | 79 +++++++++++++++++++++ .../rp2040/boards/raspberry_pi_pico2/board.cmake | 14 ---- .../boards/raspberry_pi_pico2/ozone/rp2350.jdebug | 70 ------------------- hw/bsp/rp2040/family.c | 45 +++++++----- 7 files changed, 245 insertions(+), 100 deletions(-) create mode 100644 hw/bsp/rp2040/boards/pico2_etm_trace/board.cmake create mode 100644 hw/bsp/rp2040/boards/pico2_etm_trace/board.h create mode 100644 hw/bsp/rp2040/boards/pico2_etm_trace/ozone/rp2350.jdebug delete mode 100644 hw/bsp/rp2040/boards/raspberry_pi_pico2/ozone/rp2350.jdebug (limited to 'hw') diff --git a/hw/bsp/BoardPresets.json b/hw/bsp/BoardPresets.json index a480efc3e..280d6d592 100644 --- a/hw/bsp/BoardPresets.json +++ b/hw/bsp/BoardPresets.json @@ -506,6 +506,10 @@ "name": "nutiny_sdk_nuc505", "inherits": "default" }, + { + "name": "pico2_etm_trace", + "inherits": "default" + }, { "name": "pico_sdk", "inherits": "default" @@ -1640,6 +1644,11 @@ "description": "Build preset for the nutiny_sdk_nuc505 board", "configurePreset": "nutiny_sdk_nuc505" }, + { + "name": "pico2_etm_trace", + "description": "Build preset for the pico2_etm_trace board", + "configurePreset": "pico2_etm_trace" + }, { "name": "pico_sdk", "description": "Build preset for the pico_sdk board", @@ -3900,6 +3909,19 @@ } ] }, + { + "name": "pico2_etm_trace", + "steps": [ + { + "type": "configure", + "name": "pico2_etm_trace" + }, + { + "type": "build", + "name": "pico2_etm_trace" + } + ] + }, { "name": "pico_sdk", "steps": [ diff --git a/hw/bsp/rp2040/boards/pico2_etm_trace/board.cmake b/hw/bsp/rp2040/boards/pico2_etm_trace/board.cmake new file mode 100644 index 000000000..53f9132b5 --- /dev/null +++ b/hw/bsp/rp2040/boards/pico2_etm_trace/board.cmake @@ -0,0 +1,35 @@ +set(PICO_PLATFORM rp2350-arm-s) +set(PICO_BOARD pico2) + +# ETM trace is wired on this carrier only (GP1-5 -> MIPI-20), so the trace +# build flag lives here rather than being a global -D anyone can pass: on a +# board whose PIO-USB D+ sits on GP1 (e.g. adafruit_fruit_jam) it would fight +# the trace clock. +set(TRACE_ETM 1) + +# Point the pico-sdk's own defaults at the carrier's wiring: pico2.h guards +# every PICO_DEFAULT_* with #ifndef, so these win. Without them anything that +# talks to the SDK directly instead of the TinyUSB BSP (e.g. stdio_init_all() +# in examples/device/cdc_uac2) would mux GP0/GP1 for UART - and GP1 is +# TRACECLK, so it would silently kill the trace clock mid-capture. +add_compile_definitions( + PICO_DEFAULT_UART_TX_PIN=12 + PICO_DEFAULT_UART_RX_PIN=13 + PICO_DEFAULT_LED_PIN=10 + PICO_DEFAULT_I2C=0 # STEMMA-QT / Qwiic port on GP8/9; + PICO_DEFAULT_I2C_SDA_PIN=8 # the sdk default GP4/5 is TRACEDATA2/3 + PICO_DEFAULT_I2C_SCL_PIN=9 +) + +# the carrier's MIPI-20 is driven by a J-Trace; uncomment (or pass +# -DJLINK_OPTION=...) to pin one probe by USB nickname/serial when several +# J-Links are attached during hardware validation +#set(JLINK_OPTION "-USB jtrace") + +# Clock: the rp2350 pico-sdk default, 150 MHz -> 75 MHz TRACECLK (clk_sys/2), +# validated on the trace motherboard: cdc_msc enumeration burst 3/3, zero +# overflow, +1 ns data sampling (idle eye -1000..+2000 ps; committed in the +# ozone reference). Nothing may switch clk_sys at runtime - that truncates a +# capture at the switch. Other validated rates (156000, 180000, and 240000 = +# the J-Trace PRO V2 ceiling) need PLL_SYS_* from the SDK's vcocalc.py; see +# the etm-trace skill's boards.md. diff --git a/hw/bsp/rp2040/boards/pico2_etm_trace/board.h b/hw/bsp/rp2040/boards/pico2_etm_trace/board.h new file mode 100644 index 000000000..863d0e6b9 --- /dev/null +++ b/hw/bsp/rp2040/boards/pico2_etm_trace/board.h @@ -0,0 +1,80 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: Pico 2 ETM Trace Carrier + url: https://github.com/hathach/pcb/tree/main/pico2_trace_motherboard +*/ + +// Raspberry Pi Pico 2 seated on the "pico2 trace motherboard" carrier: a +// MIPI-20 Cortex Debug+ETM adapter (SWD + 4-bit trace) plus a TinyUSB test +// bench. Same RP2350 module as raspberry_pi_pico2, different pin map: the +// carrier keeps GP1-5 free for TRACECLK/TRACEDATA0-3 and moves the console, +// LED, button and USB control pins out of the way. +// +// Carrier pin map (only the pins the BSP uses are defined below): +// 0 GND guard (JP2) 1 TRACECLK +// 2-5 TRACEDATA0-3 6 GND guard (JP3) +// 8/9 I2C0 SDA/SCL (STEMMA-QT) 10 user LED +// 11 device D+ pull-up enable 12/13 UART0 TX/RX (console) +// 14 user button (to GND, unused - BSP uses BOOTSEL) +// 15 host VBUS fault +// 16 native VBUS-detect tap 17 host VBUS enable +// 18/19 PIO-USB device D+/D- (J9) 20/21 PIO-USB host D+/D- (J5) +// 26 VBUS current sense (ADC) 27 J9 device VBUS-detect + +#ifndef TUSB_BOARD_H +#define TUSB_BOARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +//--------------------------------------------------------------------+ +// LED, UART (button: the family BSP uses BOOTSEL, like every rp2040 board) +//--------------------------------------------------------------------+ +#define LED_PIN 10 +#define LED_STATE_ON 1 + +// console is on GP12/13, NOT the pico default GP0/1: GP1 is TRACECLK, so the +// console stays full-duplex while tracing +#define UART_DEV 0 // uart0 (index, see uart_get_instance) +#define UART_TX_PIN 12 +#define UART_RX_PIN 13 + +//--------------------------------------------------------------------+ +// PIO_USB +//--------------------------------------------------------------------+ +// host port J5 (USB-A): D+ = GP20, D- = GP21, load switch enable = GP17 +#define PICO_DEFAULT_PIO_USB_DP_PIN 20 +#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 17 +#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1 + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/rp2040/boards/pico2_etm_trace/ozone/rp2350.jdebug b/hw/bsp/rp2040/boards/pico2_etm_trace/ozone/rp2350.jdebug new file mode 100644 index 000000000..fd5d589f2 --- /dev/null +++ b/hw/bsp/rp2040/boards/pico2_etm_trace/ozone/rp2350.jdebug @@ -0,0 +1,79 @@ +/********************************************************************* +* +* OnProjectLoad +* +* Function description +* Project load routine. Required. +* +* Notes +* Board pico2_etm_trace = a Pico 2 seated on the pico2 trace motherboard +* carrier (MIPI-20, source-terminated), GPIO1-5 to the MIPI20: +* TRACECLK=GPIO1->12, D0=GPIO2->14, D1=GPIO3->16, D2=GPIO4->18, +* D3=GPIO5->20. Firmware needs NO trace-specific code: J-Link's +* built-in RP2350 device script declares the off-ROM-table trace +* components (funnel/TPIU/ETM) and re-arms the whole chip-side path +* via OnTraceStart at every resume - do NOT set a custom JLinkScript +* here (it replaces that built-in script and J-Link then fails with +* "Required trace components for pin trace not found"). TRACE_ETM (set +* by this board's own board.cmake) clears TIMER0/1 DBGPAUSE - J-Link +* does not, and the reset default freezes the us-timer while a core is +* debug-halted - and adds compile-time checks that no console/I2C pin +* lands on the trace pins GP1-5; the console is full-duplex on GP12/13. +* clk_sys is the rp2350 pico-sdk default +* 150 MHz (75 MHz TRACECLK) and nothing may re-switch it at runtime: +* a mid-stream step silently truncates the capture. +* +********************************************************************** +*/ +void OnProjectLoad (void) { + Project.SetTraceSource ("Trace Pins"); + Project.SetTracePortWidth (4); + Project.SetSWO (0); + // +1 ns data sampling: at 75 MHz TRACECLK (DDR) on the trace motherboard + // the idle eye spans -1000..+2000 ps and cdc_msc passes 3/3 at +1000 + // (+3000 dead; TD aliases modulo the 6.67 ns UI) + Project.SetTraceTiming (1000, 1000, 1000, 1000); + Edit.SysVar (VAR_TRACE_CORE_CLOCK, 150000000); + Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M33F.svd"); + + Project.SetDevice ("RP2350_M33_0"); + Project.SetHostIF ("USB", ""); + Project.SetTargetIF ("SWD"); + Project.SetTIFSpeed ("25 MHz"); + + File.Open ("../../../../../../examples/cmake-build-pico2_etm_trace/device/cdc_msc/cdc_msc.elf"); +} + +/********************************************************************* +* +* AfterTargetReset +* +* Function description +* Event handler routine. +* - Sets the PC register to program reset value. +* - Sets the SP register to program reset value on Cortex-M. +* +********************************************************************** +*/ +void AfterTargetReset (void) { + // intentionally empty: the RP2350 bootrom must run to validate the + // IMAGE_DEF and hand over to the app - setting SP/PC from the vector + // table bypasses it and the pico-sdk runtime never comes up +} + +/********************************************************************* +* +* AfterTargetDownload +* +* Function description +* Event handler routine. +* - Sets the PC register to program reset value. +* - Sets the SP register to program reset value on Cortex-M. +* +********************************************************************** +*/ +void AfterTargetDownload (void) { + // intentionally empty: the RP2350 bootrom must run to validate the + // IMAGE_DEF and hand over to the app - setting SP/PC from the vector + // table bypasses it and the pico-sdk runtime never comes up +} diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake index 08384b0cd..0a7dd4d23 100644 --- a/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake +++ b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake @@ -1,17 +1,3 @@ set(PICO_PLATFORM rp2350-arm-s) set(PICO_BOARD pico2) #set(OPENOCD_SERIAL E6614103E77C5A24) - -if (TRACE_ETM STREQUAL "1") - # TRACECLK is clk_sys/2 and must stay constant once trace is armed (a step - # desyncs the decoder), so the trace clock is pinned from crt0 onwards. - # 48 MHz (24 MHz TRACECLK) holds full-width trace on a typical fly-wire - # seating; a fresh, tight seating supports up to 72-80 MHz (re-qualify per - # the etm-trace skill), and >80 MHz needs a V3 probe + real trace board. - add_compile_definitions( - SYS_CLK_KHZ=48000 - PLL_SYS_VCO_FREQ_HZ=1440000000 - PLL_SYS_POSTDIV1=6 - PLL_SYS_POSTDIV2=5 - ) -endif () diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico2/ozone/rp2350.jdebug b/hw/bsp/rp2040/boards/raspberry_pi_pico2/ozone/rp2350.jdebug deleted file mode 100644 index ff48eb673..000000000 --- a/hw/bsp/rp2040/boards/raspberry_pi_pico2/ozone/rp2350.jdebug +++ /dev/null @@ -1,70 +0,0 @@ -/********************************************************************* -* -* OnProjectLoad -* -* Function description -* Project load routine. Required. -* -* Notes -* Pico 2 has no trace connector - fly-wire GPIO1-5 to the MIPI20: -* TRACECLK=GPIO1->12, D0=GPIO2->14, D1=GPIO3->16, D2=GPIO4->18, -* D3=GPIO5->20 (SEGGER validates this board the same way). Firmware must -* be built with TRACE_ETM=1: it pins clk_sys to 48 MHz (board.cmake) so -* the 4-bit port never saturates and the clock never steps mid-stream, -* and keeps the us-timer free of TIMER DBGPAUSE (family.c). The whole -* chip-side trace path (ETM/funnel/TPIU/pin mux) is armed by J-Link's -* built-in RP2350 script at every resume - do NOT set a custom -* JLinkScript here: it would replace that script and J-Link then fails -* with "Required trace components for pin trace not found". -* GPIO1 is the default UART0 RX: console TX still works, RX is lost. -* -********************************************************************** -*/ -void OnProjectLoad (void) { - Project.SetTraceSource ("Trace Pins"); - Project.SetTracePortWidth (4); - Project.SetSWO (0); - Edit.SysVar (VAR_TRACE_CORE_CLOCK, 48000000); - Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M33F.svd"); - - Project.SetDevice ("RP2350_M33_0"); - Project.SetHostIF ("USB", ""); - Project.SetTargetIF ("SWD"); - Project.SetTIFSpeed ("25 MHz"); - - File.Open ("../../../../../../examples/cmake-build-raspberry_pi_pico2/device/cdc_msc/cdc_msc.elf"); -} - -/********************************************************************* -* -* AfterTargetReset -* -* Function description -* Event handler routine. -* - Sets the PC register to program reset value. -* - Sets the SP register to program reset value on Cortex-M. -* -********************************************************************** -*/ -void AfterTargetReset (void) { - // intentionally empty: the RP2350 bootrom must run to validate the - // IMAGE_DEF and hand over to the app - setting SP/PC from the vector - // table bypasses it and the pico-sdk runtime never comes up -} - -/********************************************************************* -* -* AfterTargetDownload -* -* Function description -* Event handler routine. -* - Sets the PC register to program reset value. -* - Sets the SP register to program reset value on Cortex-M. -* -********************************************************************** -*/ -void AfterTargetDownload (void) { - // intentionally empty: the RP2350 bootrom must run to validate the - // IMAGE_DEF and hand over to the app - setting SP/PC from the vector - // table bypasses it and the pico-sdk runtime never comes up -} diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c index e12f51b14..32b5c2312 100644 --- a/hw/bsp/rp2040/family.c +++ b/hw/bsp/rp2040/family.c @@ -158,15 +158,34 @@ static void stdio_rtt_init(void) { } #endif -//--------------------------------------------------------------------+ -// -//--------------------------------------------------------------------+ #if defined(TRACE_ETM) && defined(PICO_RP2350) && PICO_RP2350 == 1 -// J-Link's built-in RP2350 device script re-arms the whole chip-side trace -// path (ETM/funnel/TPIU/pins) via OnTraceStart at every resume, so firmware -// must NOT touch it - it only keeps the us-timer running while cores sit -// debug-halted (default TIMER DBGPAUSE freezes it, and sleep_ms() then spins -// forever after any debugger session). +// ETM trace owns GP1-5 (GP1 = TRACECLK, GP2-5 = TRACEDATA0-3): muxing any of +// them away - even briefly - gaps the trace clock/data and desyncs the probe. +#define TRACE_PIN_CONFLICT(pin) ((pin) >= 1 && (pin) <= 5) +// board_init() muxes UART_TX_PIN/UART_RX_PIN, which are defined whenever UART_DEV is +#ifdef UART_DEV + #if TRACE_PIN_CONFLICT(UART_TX_PIN) || TRACE_PIN_CONFLICT(UART_RX_PIN) + #error "TRACE_ETM: UART TX/RX sits on a trace pin (GP1-5) - route the console elsewhere (pico2_etm_trace uses GP12/13)" + #endif +#endif +// stdio_init_all() muxes the sdk defaults even when the BSP console is elsewhere +#if defined(LIB_PICO_STDIO_UART) && defined(PICO_DEFAULT_UART_TX_PIN) && \ + (TRACE_PIN_CONFLICT(PICO_DEFAULT_UART_TX_PIN) || TRACE_PIN_CONFLICT(PICO_DEFAULT_UART_RX_PIN)) + #error "TRACE_ETM: pico-sdk default UART (stdio_init_all) sits on a trace pin (GP1-5)" +#endif +#if defined(PICO_DEFAULT_I2C_SDA_PIN) && (TRACE_PIN_CONFLICT(PICO_DEFAULT_I2C_SDA_PIN) || TRACE_PIN_CONFLICT(PICO_DEFAULT_I2C_SCL_PIN)) + // #pragma message, not #warning: examples build with -Werror, and this is + // only a hazard if the app actually uses i2c_default + #pragma message("TRACE_ETM: default I2C SDA/SCL sits on a trace pin (GP1-5) - using i2c_default will corrupt the trace stream (pico2_etm_trace routes I2C to GP8/9)") +#endif + +// A debugger session leaves a core halted (Ozone captures halt at the end, +// openocd halts both cores to flash), and TIMER's reset default pauses the +// us-timer whenever EITHER core is debug-halted - J-Link's RP2350 script does +// NOT clear it (verified: DBGPAUSE still reads 0x7, TIMERAWL frozen while +// halted). tusb_time_millis_api()/sleep_ms() then spin forever and the board +// looks dead, so free the timer for trace builds, which always run under a +// probe. static void trace_etm_init(void) { *(volatile uint32_t*) 0x400B002Cu = 0; // TIMER0 DBGPAUSE *(volatile uint32_t*) 0x400B802Cu = 0; // TIMER1 DBGPAUSE @@ -177,6 +196,8 @@ static void trace_etm_init(void) { void board_init(void) { + trace_etm_init(); + #if (CFG_TUH_ENABLED && CFG_TUH_RPI_PIO_USB) || (CFG_TUD_ENABLED && CFG_TUD_RPI_PIO_USB) // Set the system clock to a multiple of 12mhz for bit-banging USB with pico-usb #if defined(PICO_RP2350) && PICO_RP2350 == 1 @@ -217,17 +238,9 @@ void board_init(void) #ifdef UART_DEV uart_inst = uart_get_instance(UART_DEV); -#if defined(TRACE_ETM) && defined(PICO_RP2350) && PICO_RP2350 == 1 - // GPIO1 (default UART RX) is TRACECLK: TX-only console, and never touch - // GPIO1 - even a brief re-mux gaps the trace clock and desyncs the probe - bi_decl(bi_1pin_with_name(UART_TX_PIN, "UART TX")); - stdio_uart_init_full(uart_inst, CFG_BOARD_UART_BAUDRATE, UART_TX_PIN, -1); -#else bi_decl(bi_2pins_with_func(UART_TX_PIN, UART_RX_PIN, GPIO_FUNC_UART)); stdio_uart_init_full(uart_inst, CFG_BOARD_UART_BAUDRATE, UART_TX_PIN, UART_RX_PIN); #endif -#endif - trace_etm_init(); #if defined(LOGGER_RTT) stdio_rtt_init(); -- cgit v1.3.1 From 839c324458f6900a58182d9aa23d846e8ec55c94 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 28 Aug 2026 16:40:07 +0700 Subject: rp2350: PIO-USB runs the pico-sdk stock 150 MHz Closes the sys-clock question. rp2350: the dynamic 156 MHz switch is removed - 150 MHz soak-tested clean (and a runtime switch truncates ETM capture on the trace carrier). rp2040 keeps its existing 120 MHz: soak sweeps show 120 = 8/8, stock 125 = 0/3 (bulk-OUT collapses, device NAKs ~600:1 with zero CRC errors on the wire), and 132 = 2/10 flaky despite an exact 12n/375k divider - no divider criterion predicts rp2040 PIO-USB health (the RX state machine samples at raw sysclk), so only soak-validated clocks ship. --- hw/bsp/rp2040/family.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) (limited to 'hw') diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c index 32b5c2312..9de1658eb 100644 --- a/hw/bsp/rp2040/family.c +++ b/hw/bsp/rp2040/family.c @@ -199,19 +199,12 @@ void board_init(void) trace_etm_init(); #if (CFG_TUH_ENABLED && CFG_TUH_RPI_PIO_USB) || (CFG_TUD_ENABLED && CFG_TUD_RPI_PIO_USB) - // Set the system clock to a multiple of 12mhz for bit-banging USB with pico-usb - #if defined(PICO_RP2350) && PICO_RP2350 == 1 - #ifdef TRACE_ETM - #error "TRACE_ETM pins clk_sys to 48 MHz (board.cmake) - too slow for PIO-USB, and a runtime clock switch desyncs the trace stream" - #endif - set_sys_clock_khz(156000, true); // rp2350 default is 150Mhz - #else + // rp2350 runs the pico-sdk stock 150 MHz (a runtime switch also truncates ETM + // capture). rp2040 keeps 120 MHz: soak-tested — the stock 125 MHz collapses + // PIO-USB bulk-OUT (device NAKs ~600:1, wire-measured, zero CRC errors). + #if !(defined(PICO_RP2350) && PICO_RP2350 == 1) set_sys_clock_khz(120000, true); // rp2040 default is 125Mhz #endif - // set_sys_clock_khz(180000, true); - // set_sys_clock_khz(192000, true); - // set_sys_clock_khz(240000, true); - // set_sys_clock_khz(264000, true); #ifdef PICO_DEFAULT_PIO_USB_VBUSEN_PIN gpio_init(PICO_DEFAULT_PIO_USB_VBUSEN_PIN); -- cgit v1.3.1